* [PATCH v7 01/64] linux-user/nios2: Hoist pc advance to the top of EXCP_TRAP
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 02/64] linux-user/nios2: Fix clone child return Richard Henderson
` (62 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Note that this advance *should* be done by the translator, as
that's the pc value that's supposed to be generated by hardware.
However, that's a much larger change across sysemu as well.
In the meantime, produce the correct PC for any signals raised
by the trap instruction. Note the special case of TRAP_BRKPT,
which itself is special cased within the kernel.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/nios2/cpu_loop.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c
index 1e93ef34e6..2e9296750d 100644
--- a/linux-user/nios2/cpu_loop.c
+++ b/linux-user/nios2/cpu_loop.c
@@ -40,6 +40,12 @@ void cpu_loop(CPUNios2State *env)
break;
case EXCP_TRAP:
+ /*
+ * TODO: This advance should be done in the translator, as
+ * hardware produces an advanced pc as part of all exceptions.
+ */
+ env->regs[R_PC] += 4;
+
switch (env->error_code) {
case 0:
qemu_log_mask(CPU_LOG_INT, "\nSyscall\n");
@@ -56,7 +62,6 @@ void cpu_loop(CPUNios2State *env)
env->regs[2] = abs(ret);
/* Return value is 0..4096 */
env->regs[7] = ret > 0xfffff000u;
- env->regs[R_PC] += 4;
break;
case 1:
@@ -69,6 +74,8 @@ void cpu_loop(CPUNios2State *env)
break;
case 31:
qemu_log_mask(CPU_LOG_INT, "\nTrap 31\n");
+ /* Match kernel's breakpoint_c(). */
+ env->regs[R_PC] -= 4;
force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[R_PC]);
break;
default:
@@ -99,7 +106,6 @@ void cpu_loop(CPUNios2State *env)
o = env->regs[5];
n = env->regs[6];
env->regs[2] = qatomic_cmpxchg(h, o, n) - o;
- env->regs[R_PC] += 4;
}
break;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 02/64] linux-user/nios2: Fix clone child return
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
2022-04-21 15:16 ` [PATCH v7 01/64] linux-user/nios2: Hoist pc advance to the top of EXCP_TRAP Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 03/64] linux-user/nios2: Drop syscall 0 "workaround" Richard Henderson
` (61 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
The child side of clone needs to set the secondary
syscall return value, r7, to indicate syscall success.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/nios2/target_cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-user/nios2/target_cpu.h b/linux-user/nios2/target_cpu.h
index 2d2008f002..830b4c0741 100644
--- a/linux-user/nios2/target_cpu.h
+++ b/linux-user/nios2/target_cpu.h
@@ -27,6 +27,7 @@ static inline void cpu_clone_regs_child(CPUNios2State *env, target_ulong newsp,
env->regs[R_SP] = newsp;
}
env->regs[R_RET0] = 0;
+ env->regs[7] = 0;
}
static inline void cpu_clone_regs_parent(CPUNios2State *env, unsigned flags)
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 03/64] linux-user/nios2: Drop syscall 0 "workaround"
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
2022-04-21 15:16 ` [PATCH v7 01/64] linux-user/nios2: Hoist pc advance to the top of EXCP_TRAP Richard Henderson
2022-04-21 15:16 ` [PATCH v7 02/64] linux-user/nios2: Fix clone child return Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 04/64] linux-user/nios2: Adjust error return Richard Henderson
` (60 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Syscall 0 is __NR_io_setup for this target; there is nothing
to work around.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Fixes: a0a839b65b6 ("nios2: Add usermode binaries emulation")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/nios2/cpu_loop.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c
index 2e9296750d..91737c568f 100644
--- a/linux-user/nios2/cpu_loop.c
+++ b/linux-user/nios2/cpu_loop.c
@@ -55,10 +55,6 @@ void cpu_loop(CPUNios2State *env)
env->regs[7], env->regs[8], env->regs[9],
0, 0);
- if (env->regs[2] == 0) { /* FIXME: syscall 0 workaround */
- ret = 0;
- }
-
env->regs[2] = abs(ret);
/* Return value is 0..4096 */
env->regs[7] = ret > 0xfffff000u;
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 04/64] linux-user/nios2: Adjust error return
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (2 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 03/64] linux-user/nios2: Drop syscall 0 "workaround" Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 05/64] linux-user/nios2: Handle special qemu syscall return values Richard Henderson
` (59 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Follow the kernel assembly, which considers all negative
return values to be errors.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/nios2/cpu_loop.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c
index 91737c568f..63afba5862 100644
--- a/linux-user/nios2/cpu_loop.c
+++ b/linux-user/nios2/cpu_loop.c
@@ -55,9 +55,14 @@ void cpu_loop(CPUNios2State *env)
env->regs[7], env->regs[8], env->regs[9],
0, 0);
+ /*
+ * See the code after translate_rc_and_ret: all negative
+ * values are errors (aided by userspace restricted to 2G),
+ * errno is returned positive in r2, and error indication
+ * is a boolean in r7.
+ */
env->regs[2] = abs(ret);
- /* Return value is 0..4096 */
- env->regs[7] = ret > 0xfffff000u;
+ env->regs[7] = ret < 0;
break;
case 1:
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 05/64] linux-user/nios2: Handle special qemu syscall return values
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (3 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 04/64] linux-user/nios2: Adjust error return Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 06/64] linux-user/nios2: Remove do_sigreturn Richard Henderson
` (58 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Honor QEMU_ESIGRETURN and QEMU_ERESTARTSYS.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/nios2/cpu_loop.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c
index 63afba5862..2963fc62b4 100644
--- a/linux-user/nios2/cpu_loop.c
+++ b/linux-user/nios2/cpu_loop.c
@@ -55,6 +55,14 @@ void cpu_loop(CPUNios2State *env)
env->regs[7], env->regs[8], env->regs[9],
0, 0);
+ if (ret == -QEMU_ESIGRETURN) {
+ /* rt_sigreturn has set all state. */
+ break;
+ }
+ if (ret == -QEMU_ERESTARTSYS) {
+ env->regs[R_PC] -= 4;
+ break;
+ }
/*
* See the code after translate_rc_and_ret: all negative
* values are errors (aided by userspace restricted to 2G),
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 06/64] linux-user/nios2: Remove do_sigreturn
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (4 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 05/64] linux-user/nios2: Handle special qemu syscall return values Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 07/64] linux-user/nios2: Use QEMU_ESIGRETURN from do_rt_sigreturn Richard Henderson
` (57 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
There is no sigreturn syscall, only rt_sigreturn.
This function is unused.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/nios2/signal.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/linux-user/nios2/signal.c b/linux-user/nios2/signal.c
index 517cd39270..133bc05673 100644
--- a/linux-user/nios2/signal.c
+++ b/linux-user/nios2/signal.c
@@ -185,13 +185,6 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
unlock_user_struct(frame, frame_addr, 1);
}
-long do_sigreturn(CPUNios2State *env)
-{
- trace_user_do_sigreturn(env, 0);
- qemu_log_mask(LOG_UNIMP, "do_sigreturn: not implemented\n");
- return -TARGET_ENOSYS;
-}
-
long do_rt_sigreturn(CPUNios2State *env)
{
/* Verify, can we follow the stack back */
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 07/64] linux-user/nios2: Use QEMU_ESIGRETURN from do_rt_sigreturn
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (5 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 06/64] linux-user/nios2: Remove do_sigreturn Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 08/64] tests/tcg/nios2: Re-enable linux-user tests Richard Henderson
` (56 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Drop the kernel-specific "pr2" code structure and use
the qemu-specific error return value.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/nios2/signal.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/linux-user/nios2/signal.c b/linux-user/nios2/signal.c
index 133bc05673..9aa525e723 100644
--- a/linux-user/nios2/signal.c
+++ b/linux-user/nios2/signal.c
@@ -77,8 +77,7 @@ static void rt_setup_ucontext(struct target_ucontext *uc, CPUNios2State *env)
__put_user(env->regs[R_SP], &gregs[28]);
}
-static int rt_restore_ucontext(CPUNios2State *env, struct target_ucontext *uc,
- int *pr2)
+static int rt_restore_ucontext(CPUNios2State *env, struct target_ucontext *uc)
{
int temp;
unsigned long *gregs = uc->tuc_mcontext.gregs;
@@ -128,8 +127,6 @@ static int rt_restore_ucontext(CPUNios2State *env, struct target_ucontext *uc,
__get_user(env->regs[R_SP], &gregs[28]);
target_restore_altstack(&uc->tuc_stack, env);
-
- *pr2 = env->regs[2];
return 0;
}
@@ -191,7 +188,6 @@ long do_rt_sigreturn(CPUNios2State *env)
abi_ulong frame_addr = env->regs[R_SP];
struct target_rt_sigframe *frame;
sigset_t set;
- int rval;
if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) {
goto badframe;
@@ -200,15 +196,15 @@ long do_rt_sigreturn(CPUNios2State *env)
target_to_host_sigset(&set, &frame->uc.tuc_sigmask);
set_sigmask(&set);
- if (rt_restore_ucontext(env, &frame->uc, &rval)) {
+ if (rt_restore_ucontext(env, &frame->uc)) {
goto badframe;
}
unlock_user_struct(frame, frame_addr, 0);
- return rval;
+ return -QEMU_ESIGRETURN;
badframe:
unlock_user_struct(frame, frame_addr, 0);
force_sig(TARGET_SIGSEGV);
- return 0;
+ return -QEMU_ESIGRETURN;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 08/64] tests/tcg/nios2: Re-enable linux-user tests
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (6 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 07/64] linux-user/nios2: Use QEMU_ESIGRETURN from do_rt_sigreturn Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 09/64] target/nios2: Remove user-only nios2_cpu_do_interrupt Richard Henderson
` (55 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Now that threads and signals have been fixed, re-enable tests.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tests/tcg/nios2/Makefile.target | 11 -----------
1 file changed, 11 deletions(-)
delete mode 100644 tests/tcg/nios2/Makefile.target
diff --git a/tests/tcg/nios2/Makefile.target b/tests/tcg/nios2/Makefile.target
deleted file mode 100644
index b38e2352b7..0000000000
--- a/tests/tcg/nios2/Makefile.target
+++ /dev/null
@@ -1,11 +0,0 @@
-# nios2 specific test tweaks
-
-# Currently nios2 signal handling is broken
-run-signals: signals
- $(call skip-test, $<, "BROKEN")
-run-plugin-signals-with-%:
- $(call skip-test, $<, "BROKEN")
-run-linux-test: linux-test
- $(call skip-test, $<, "BROKEN")
-run-plugin-linux-test-with-%:
- $(call skip-test, $<, "BROKEN")
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 09/64] target/nios2: Remove user-only nios2_cpu_do_interrupt
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (7 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 08/64] tests/tcg/nios2: Re-enable linux-user tests Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-22 12:51 ` Peter Maydell
2022-04-21 15:16 ` [PATCH v7 10/64] target/nios2: Remove nios2_cpu_record_sigsegv Richard Henderson
` (54 subsequent siblings)
63 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel
Since 78271684719, this function is unused for user-only,
when the TCGCPUOps.do_interrupt hook itself became system-only.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/helper.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index e5c98650e1..678fd96c4e 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -30,14 +30,6 @@
#if defined(CONFIG_USER_ONLY)
-void nios2_cpu_do_interrupt(CPUState *cs)
-{
- Nios2CPU *cpu = NIOS2_CPU(cs);
- CPUNios2State *env = &cpu->env;
- cs->exception_index = -1;
- env->regs[R_EA] = env->regs[R_PC] + 4;
-}
-
void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr,
MMUAccessType access_type,
bool maperr, uintptr_t retaddr)
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 10/64] target/nios2: Remove nios2_cpu_record_sigsegv
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (8 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 09/64] target/nios2: Remove user-only nios2_cpu_do_interrupt Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-22 12:53 ` Peter Maydell
2022-04-21 15:16 ` [PATCH v7 11/64] target/nios2: Build helper.c for system only Richard Henderson
` (53 subsequent siblings)
63 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel
Since f5ef0e518d0, we have a real page mapped for kuser,
which means the special casing for SIGSEGV can go away.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 6 +-----
linux-user/nios2/cpu_loop.c | 10 ----------
target/nios2/cpu.c | 4 +---
target/nios2/helper.c | 14 +-------------
4 files changed, 3 insertions(+), 31 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index ca0f3420cd..7b75641788 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -216,11 +216,7 @@ static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
MMU_SUPERVISOR_IDX;
}
-#ifdef CONFIG_USER_ONLY
-void nios2_cpu_record_sigsegv(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
- bool maperr, uintptr_t ra);
-#else
+#ifndef CONFIG_USER_ONLY
bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c
index 2963fc62b4..f37850fe81 100644
--- a/linux-user/nios2/cpu_loop.c
+++ b/linux-user/nios2/cpu_loop.c
@@ -126,16 +126,6 @@ void cpu_loop(CPUNios2State *env)
info.si_code = TARGET_TRAP_BRKPT;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
- case 0xaa:
- {
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- /* TODO: check env->error_code */
- info.si_code = TARGET_SEGV_MAPERR;
- info._sifields._sigfault._addr = env->regs[R_PC];
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- }
- break;
default:
EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
trapnr);
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index b0877cb39e..9774a3b8a4 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -210,9 +210,7 @@ static const struct SysemuCPUOps nios2_sysemu_ops = {
static const struct TCGCPUOps nios2_tcg_ops = {
.initialize = nios2_tcg_init,
-#ifdef CONFIG_USER_ONLY
- .record_sigsegv = nios2_cpu_record_sigsegv,
-#else
+#ifndef CONFIG_USER_ONLY
.tlb_fill = nios2_cpu_tlb_fill,
.cpu_exec_interrupt = nios2_cpu_exec_interrupt,
.do_interrupt = nios2_cpu_do_interrupt,
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 678fd96c4e..55b8fb0bcb 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -28,19 +28,7 @@
#include "exec/helper-proto.h"
#include "semihosting/semihost.h"
-#if defined(CONFIG_USER_ONLY)
-
-void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr,
- MMUAccessType access_type,
- bool maperr, uintptr_t retaddr)
-{
- /* FIXME: Disentangle kuser page from linux-user sigsegv handling. */
- cs->exception_index = 0xaa;
- cpu_loop_exit_restore(cs, retaddr);
-}
-
-#else /* !CONFIG_USER_ONLY */
-
+#if !defined(CONFIG_USER_ONLY)
void nios2_cpu_do_interrupt(CPUState *cs)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 11/64] target/nios2: Build helper.c for system only
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (9 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 10/64] target/nios2: Remove nios2_cpu_record_sigsegv Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-22 12:54 ` Peter Maydell
2022-04-21 15:16 ` [PATCH v7 12/64] linux-user/nios2: Use force_sig_fault for EXCP_DEBUG Richard Henderson
` (52 subsequent siblings)
63 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel
Remove the #ifdef !defined(CONFIG_USER_ONLY) that surrounds
the whole file, and move helper.c to nios2_softmmu_ss.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/helper.c | 3 +--
target/nios2/meson.build | 7 +++++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 55b8fb0bcb..04a8831443 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -28,7 +28,7 @@
#include "exec/helper-proto.h"
#include "semihosting/semihost.h"
-#if !defined(CONFIG_USER_ONLY)
+
void nios2_cpu_do_interrupt(CPUState *cs)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
@@ -292,4 +292,3 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
env->regs[CR_BADADDR] = address;
cpu_loop_exit_restore(cs, retaddr);
}
-#endif /* !CONFIG_USER_ONLY */
diff --git a/target/nios2/meson.build b/target/nios2/meson.build
index 62b384702d..2bd60ba306 100644
--- a/target/nios2/meson.build
+++ b/target/nios2/meson.build
@@ -1,14 +1,17 @@
nios2_ss = ss.source_set()
nios2_ss.add(files(
'cpu.c',
- 'helper.c',
'nios2-semi.c',
'op_helper.c',
'translate.c',
))
nios2_softmmu_ss = ss.source_set()
-nios2_softmmu_ss.add(files('monitor.c', 'mmu.c'))
+nios2_softmmu_ss.add(files(
+ 'helper.c',
+ 'monitor.c',
+ 'mmu.c'
+))
target_arch += {'nios2': nios2_ss}
target_softmmu_arch += {'nios2': nios2_softmmu_ss}
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 12/64] linux-user/nios2: Use force_sig_fault for EXCP_DEBUG
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (10 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 11/64] target/nios2: Build helper.c for system only Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-22 12:54 ` Peter Maydell
2022-04-21 15:16 ` [PATCH v7 13/64] target/nios2: Check supervisor on eret Richard Henderson
` (51 subsequent siblings)
63 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel
Use the simpler signal interface, which forces us to supply
the missing PC value to si_addr.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/nios2/cpu_loop.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c
index f37850fe81..e725036628 100644
--- a/linux-user/nios2/cpu_loop.c
+++ b/linux-user/nios2/cpu_loop.c
@@ -26,7 +26,6 @@
void cpu_loop(CPUNios2State *env)
{
CPUState *cs = env_cpu(env);
- target_siginfo_t info;
int trapnr, ret;
for (;;) {
@@ -121,10 +120,7 @@ void cpu_loop(CPUNios2State *env)
break;
case EXCP_DEBUG:
- info.si_signo = TARGET_SIGTRAP;
- info.si_errno = 0;
- info.si_code = TARGET_TRAP_BRKPT;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[R_PC]);
break;
default:
EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 13/64] target/nios2: Check supervisor on eret
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (11 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 12/64] linux-user/nios2: Use force_sig_fault for EXCP_DEBUG Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 14/64] target/nios2: Stop generating code if gen_check_supervisor fails Richard Henderson
` (50 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Amir Gonnen
From: Amir Gonnen <amir.gonnen@neuroblade.ai>
eret instruction is only allowed in supervisor mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Amir Gonnen <amir.gonnen@neuroblade.ai>
Message-Id: <20220303153906.2024748-2-amir.gonnen@neuroblade.ai>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 89b97ef520..eb97e13feb 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -384,6 +384,8 @@ static const Nios2Instruction i_type_instructions[] = {
*/
static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
{
+ gen_check_supervisor(dc);
+
tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]);
tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]);
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 14/64] target/nios2: Stop generating code if gen_check_supervisor fails
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (12 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 13/64] target/nios2: Check supervisor on eret Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 15/64] target/nios2: Add NUM_GP_REGS and NUM_CP_REGS Richard Henderson
` (49 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Whether the cpu is in user-mode or not is something that we
know at translation-time. We do not need to generate code
after having raised an exception.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/translate.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index eb97e13feb..d61e349207 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -169,12 +169,14 @@ static void gen_excp(DisasContext *dc, uint32_t code, uint32_t flags)
t_gen_helper_raise_exception(dc, flags);
}
-static void gen_check_supervisor(DisasContext *dc)
+static bool gen_check_supervisor(DisasContext *dc)
{
if (dc->base.tb->flags & CR_STATUS_U) {
/* CPU in user mode, privileged instruction called, stop. */
t_gen_helper_raise_exception(dc, EXCP_SUPERI);
+ return false;
}
+ return true;
}
/*
@@ -384,7 +386,9 @@ static const Nios2Instruction i_type_instructions[] = {
*/
static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
{
- gen_check_supervisor(dc);
+ if (!gen_check_supervisor(dc)) {
+ return;
+ }
tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]);
tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]);
@@ -447,7 +451,9 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, code);
- gen_check_supervisor(dc);
+ if (!gen_check_supervisor(dc)) {
+ return;
+ }
if (unlikely(instr.c == R_ZERO)) {
return;
@@ -474,9 +480,13 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
/* ctlN <- rA */
static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
{
- gen_check_supervisor(dc);
+ if (!gen_check_supervisor(dc)) {
+ return;
+ }
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ g_assert_not_reached();
+#else
R_TYPE(instr, code);
TCGv v = load_gpr(dc, instr.a);
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 15/64] target/nios2: Add NUM_GP_REGS and NUM_CP_REGS
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (13 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 14/64] target/nios2: Stop generating code if gen_check_supervisor fails Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 16/64] target/nios2: Split PC out of env->regs[] Richard Henderson
` (48 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Amir Gonnen
From: Amir Gonnen <amir.gonnen@neuroblade.ai>
Split NUM_CORE_REGS into components that can be used elsewhere.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Amir Gonnen <amir.gonnen@neuroblade.ai>
Message-Id: <20220303153906.2024748-3-amir.gonnen@neuroblade.ai>
[rth: Split out of a larger patch for shadow register sets.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 7b75641788..2a53b1fcf2 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -56,9 +56,11 @@ struct Nios2CPUClass {
#define EXCEPTION_ADDRESS 0x00000004
#define FAST_TLB_MISS_ADDRESS 0x00000008
+#define NUM_GP_REGS 32
+#define NUM_CR_REGS 32
/* GP regs + CR regs + PC */
-#define NUM_CORE_REGS (32 + 32 + 1)
+#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS + 1)
/* General purpose register aliases */
#define R_ZERO 0
@@ -79,7 +81,7 @@ struct Nios2CPUClass {
#define R_RA 31
/* Control register aliases */
-#define CR_BASE 32
+#define CR_BASE NUM_GP_REGS
#define CR_STATUS (CR_BASE + 0)
#define CR_STATUS_PIE (1 << 0)
#define CR_STATUS_U (1 << 1)
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 16/64] target/nios2: Split PC out of env->regs[]
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (14 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 15/64] target/nios2: Add NUM_GP_REGS and NUM_CP_REGS Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 17/64] target/nios2: Split out helper for eret instruction Richard Henderson
` (47 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
It is cleaner to have a separate name for this variable.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 10 +++-----
linux-user/elfload.c | 2 +-
linux-user/nios2/cpu_loop.c | 19 +++++++-------
linux-user/nios2/signal.c | 6 ++---
target/nios2/cpu.c | 8 +++---
target/nios2/helper.c | 49 +++++++++++++++++--------------------
target/nios2/translate.c | 29 +++++++++++-----------
7 files changed, 58 insertions(+), 65 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 2a53b1fcf2..dbd9d1b587 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -59,8 +59,8 @@ struct Nios2CPUClass {
#define NUM_GP_REGS 32
#define NUM_CR_REGS 32
-/* GP regs + CR regs + PC */
-#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS + 1)
+/* GP regs + CR regs */
+#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS)
/* General purpose register aliases */
#define R_ZERO 0
@@ -130,9 +130,6 @@ struct Nios2CPUClass {
#define CR_MPUBASE (CR_BASE + 14)
#define CR_MPUACC (CR_BASE + 15)
-/* Other registers */
-#define R_PC 64
-
/* Exceptions */
#define EXCP_BREAK 0x1000
#define EXCP_RESET 0
@@ -158,6 +155,7 @@ struct Nios2CPUClass {
struct CPUArchState {
uint32_t regs[NUM_CORE_REGS];
+ uint32_t pc;
#if !defined(CONFIG_USER_ONLY)
Nios2MMU mmu;
@@ -237,7 +235,7 @@ typedef Nios2CPU ArchCPU;
static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
{
- *pc = env->regs[R_PC];
+ *pc = env->pc;
*cs_base = 0;
*flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U));
}
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index d6bb1fc7ca..397dec5eb8 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1170,7 +1170,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
(*regs)[30] = -1; /* R_SSTATUS */
(*regs)[31] = tswapreg(env->regs[R_RA]);
- (*regs)[32] = tswapreg(env->regs[R_PC]);
+ (*regs)[32] = tswapreg(env->pc);
(*regs)[33] = -1; /* R_STATUS */
(*regs)[34] = tswapreg(env->regs[CR_ESTATUS]);
diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c
index e725036628..a941f9032e 100644
--- a/linux-user/nios2/cpu_loop.c
+++ b/linux-user/nios2/cpu_loop.c
@@ -43,7 +43,7 @@ void cpu_loop(CPUNios2State *env)
* TODO: This advance should be done in the translator, as
* hardware produces an advanced pc as part of all exceptions.
*/
- env->regs[R_PC] += 4;
+ env->pc += 4;
switch (env->error_code) {
case 0:
@@ -59,7 +59,7 @@ void cpu_loop(CPUNios2State *env)
break;
}
if (ret == -QEMU_ERESTARTSYS) {
- env->regs[R_PC] -= 4;
+ env->pc -= 4;
break;
}
/*
@@ -74,22 +74,21 @@ void cpu_loop(CPUNios2State *env)
case 1:
qemu_log_mask(CPU_LOG_INT, "\nTrap 1\n");
- force_sig_fault(TARGET_SIGUSR1, 0, env->regs[R_PC]);
+ force_sig_fault(TARGET_SIGUSR1, 0, env->pc);
break;
case 2:
qemu_log_mask(CPU_LOG_INT, "\nTrap 2\n");
- force_sig_fault(TARGET_SIGUSR2, 0, env->regs[R_PC]);
+ force_sig_fault(TARGET_SIGUSR2, 0, env->pc);
break;
case 31:
qemu_log_mask(CPU_LOG_INT, "\nTrap 31\n");
/* Match kernel's breakpoint_c(). */
- env->regs[R_PC] -= 4;
- force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[R_PC]);
+ env->pc -= 4;
+ force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
break;
default:
qemu_log_mask(CPU_LOG_INT, "\nTrap %d\n", env->error_code);
- force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP,
- env->regs[R_PC]);
+ force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, env->pc);
break;
case 16: /* QEMU specific, for __kuser_cmpxchg */
@@ -120,7 +119,7 @@ void cpu_loop(CPUNios2State *env)
break;
case EXCP_DEBUG:
- force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[R_PC]);
+ force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
break;
default:
EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
@@ -156,6 +155,6 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
env->regs[R_SP] = regs->sp;
env->regs[R_GP] = regs->gp;
env->regs[CR_ESTATUS] = regs->estatus;
- env->regs[R_PC] = regs->ea;
+ env->pc = regs->ea;
/* TODO: unsigned long orig_r7; */
}
diff --git a/linux-user/nios2/signal.c b/linux-user/nios2/signal.c
index 9aa525e723..32b3dc99c6 100644
--- a/linux-user/nios2/signal.c
+++ b/linux-user/nios2/signal.c
@@ -73,7 +73,7 @@ static void rt_setup_ucontext(struct target_ucontext *uc, CPUNios2State *env)
__put_user(env->regs[R_RA], &gregs[23]);
__put_user(env->regs[R_FP], &gregs[24]);
__put_user(env->regs[R_GP], &gregs[25]);
- __put_user(env->regs[R_PC], &gregs[27]);
+ __put_user(env->pc, &gregs[27]);
__put_user(env->regs[R_SP], &gregs[28]);
}
@@ -121,7 +121,7 @@ static int rt_restore_ucontext(CPUNios2State *env, struct target_ucontext *uc)
__get_user(env->regs[R_GP], &gregs[25]);
/* Not really necessary no user settable bits */
__get_user(temp, &gregs[26]);
- __get_user(env->regs[R_PC], &gregs[27]);
+ __get_user(env->pc, &gregs[27]);
__get_user(env->regs[R_RA], &gregs[23]);
__get_user(env->regs[R_SP], &gregs[28]);
@@ -177,7 +177,7 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
env->regs[4] = sig;
env->regs[5] = frame_addr + offsetof(struct target_rt_sigframe, info);
env->regs[6] = frame_addr + offsetof(struct target_rt_sigframe, uc);
- env->regs[R_PC] = ka->_sa_handler;
+ env->pc = ka->_sa_handler;
unlock_user_struct(frame, frame_addr, 1);
}
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 9774a3b8a4..dc1551241e 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -31,7 +31,7 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
Nios2CPU *cpu = NIOS2_CPU(cs);
CPUNios2State *env = &cpu->env;
- env->regs[R_PC] = value;
+ env->pc = value;
}
static bool nios2_cpu_has_work(CPUState *cs)
@@ -49,7 +49,7 @@ static void nios2_cpu_reset(DeviceState *dev)
ncc->parent_reset(dev);
memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS);
- env->regs[R_PC] = cpu->reset_addr;
+ env->pc = cpu->reset_addr;
#if defined(CONFIG_USER_ONLY)
/* Start in user mode with interrupts enabled. */
@@ -156,7 +156,7 @@ static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
if (n < 32) { /* GP regs */
return gdb_get_reg32(mem_buf, env->regs[n]);
} else if (n == 32) { /* PC */
- return gdb_get_reg32(mem_buf, env->regs[R_PC]);
+ return gdb_get_reg32(mem_buf, env->pc);
} else if (n < 49) { /* Status regs */
return gdb_get_reg32(mem_buf, env->regs[n - 1]);
}
@@ -178,7 +178,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
if (n < 32) { /* GP regs */
env->regs[n] = ldl_p(mem_buf);
} else if (n == 32) { /* PC */
- env->regs[R_PC] = ldl_p(mem_buf);
+ env->pc = ldl_p(mem_buf);
} else if (n < 49) { /* Status regs */
env->regs[n - 1] = ldl_p(mem_buf);
}
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 04a8831443..34b3e18e37 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -38,7 +38,7 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_IRQ:
assert(env->regs[CR_STATUS] & CR_STATUS_PIE);
- qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->regs[R_PC]);
+ qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc);
env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
env->regs[CR_STATUS] |= CR_STATUS_IH;
@@ -47,14 +47,13 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
- env->regs[R_EA] = env->regs[R_PC] + 4;
- env->regs[R_PC] = cpu->exception_addr;
+ env->regs[R_EA] = env->pc + 4;
+ env->pc = cpu->exception_addr;
break;
case EXCP_TLBD:
if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
- qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n",
- env->regs[R_PC]);
+ qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc);
/* Fast TLB miss */
/* Variation from the spec. Table 3-35 of the cpu reference shows
@@ -70,11 +69,10 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->regs[CR_TLBMISC] &= ~CR_TLBMISC_DBL;
env->regs[CR_TLBMISC] |= CR_TLBMISC_WR;
- env->regs[R_EA] = env->regs[R_PC] + 4;
- env->regs[R_PC] = cpu->fast_tlb_miss_addr;
+ env->regs[R_EA] = env->pc + 4;
+ env->pc = cpu->fast_tlb_miss_addr;
} else {
- qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n",
- env->regs[R_PC]);
+ qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc);
/* Double TLB miss */
env->regs[CR_STATUS] |= CR_STATUS_EH;
@@ -85,14 +83,14 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->regs[CR_TLBMISC] |= CR_TLBMISC_DBL;
- env->regs[R_PC] = cpu->exception_addr;
+ env->pc = cpu->exception_addr;
}
break;
case EXCP_TLBR:
case EXCP_TLBW:
case EXCP_TLBX:
- qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->regs[R_PC]);
+ qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc);
env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
env->regs[CR_STATUS] |= CR_STATUS_EH;
@@ -105,19 +103,18 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->regs[CR_TLBMISC] |= CR_TLBMISC_WR;
}
- env->regs[R_EA] = env->regs[R_PC] + 4;
- env->regs[R_PC] = cpu->exception_addr;
+ env->regs[R_EA] = env->pc + 4;
+ env->pc = cpu->exception_addr;
break;
case EXCP_SUPERA:
case EXCP_SUPERI:
case EXCP_SUPERD:
- qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n",
- env->regs[R_PC]);
+ qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc);
if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
- env->regs[R_EA] = env->regs[R_PC] + 4;
+ env->regs[R_EA] = env->pc + 4;
}
env->regs[CR_STATUS] |= CR_STATUS_EH;
@@ -126,17 +123,16 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
- env->regs[R_PC] = cpu->exception_addr;
+ env->pc = cpu->exception_addr;
break;
case EXCP_ILLEGAL:
case EXCP_TRAP:
- qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n",
- env->regs[R_PC]);
+ qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc);
if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
- env->regs[R_EA] = env->regs[R_PC] + 4;
+ env->regs[R_EA] = env->pc + 4;
}
env->regs[CR_STATUS] |= CR_STATUS_EH;
@@ -145,24 +141,23 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
- env->regs[R_PC] = cpu->exception_addr;
+ env->pc = cpu->exception_addr;
break;
case EXCP_BREAK:
- qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n",
- env->regs[R_PC]);
+ qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc);
/* The semihosting instruction is "break 1". */
if (semihosting_enabled() &&
- cpu_ldl_code(env, env->regs[R_PC]) == 0x003da07a) {
+ cpu_ldl_code(env, env->pc) == 0x003da07a) {
qemu_log_mask(CPU_LOG_INT, "Entering semihosting\n");
- env->regs[R_PC] += 4;
+ env->pc += 4;
do_nios2_semihosting(env);
break;
}
if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
env->regs[CR_BSTATUS] = env->regs[CR_STATUS];
- env->regs[R_BA] = env->regs[R_PC] + 4;
+ env->regs[R_BA] = env->pc + 4;
}
env->regs[CR_STATUS] |= CR_STATUS_EH;
@@ -171,7 +166,7 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
- env->regs[R_PC] = cpu->exception_addr;
+ env->pc = cpu->exception_addr;
break;
default:
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index d61e349207..226bd9e30b 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -104,6 +104,7 @@ typedef struct DisasContext {
} DisasContext;
static TCGv cpu_R[NUM_CORE_REGS];
+static TCGv cpu_pc;
typedef struct Nios2Instruction {
void (*handler)(DisasContext *dc, uint32_t code, uint32_t flags);
@@ -144,7 +145,7 @@ static void t_gen_helper_raise_exception(DisasContext *dc,
{
TCGv_i32 tmp = tcg_const_i32(index);
- tcg_gen_movi_tl(cpu_R[R_PC], dc->pc);
+ tcg_gen_movi_tl(cpu_pc, dc->pc);
gen_helper_raise_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
dc->base.is_jmp = DISAS_NORETURN;
@@ -156,10 +157,10 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest)
if (translator_use_goto_tb(&dc->base, dest)) {
tcg_gen_goto_tb(n);
- tcg_gen_movi_tl(cpu_R[R_PC], dest);
+ tcg_gen_movi_tl(cpu_pc, dest);
tcg_gen_exit_tb(tb, n);
} else {
- tcg_gen_movi_tl(cpu_R[R_PC], dest);
+ tcg_gen_movi_tl(cpu_pc, dest);
tcg_gen_exit_tb(NULL, 0);
}
}
@@ -391,7 +392,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
}
tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]);
- tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]);
+ tcg_gen_mov_tl(cpu_pc, cpu_R[R_EA]);
dc->base.is_jmp = DISAS_JUMP;
}
@@ -399,7 +400,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
/* PC <- ra */
static void ret(DisasContext *dc, uint32_t code, uint32_t flags)
{
- tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_RA]);
+ tcg_gen_mov_tl(cpu_pc, cpu_R[R_RA]);
dc->base.is_jmp = DISAS_JUMP;
}
@@ -407,7 +408,7 @@ static void ret(DisasContext *dc, uint32_t code, uint32_t flags)
/* PC <- ba */
static void bret(DisasContext *dc, uint32_t code, uint32_t flags)
{
- tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_BA]);
+ tcg_gen_mov_tl(cpu_pc, cpu_R[R_BA]);
dc->base.is_jmp = DISAS_JUMP;
}
@@ -417,7 +418,7 @@ static void jmp(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, code);
- tcg_gen_mov_tl(cpu_R[R_PC], load_gpr(dc, instr.a));
+ tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a));
dc->base.is_jmp = DISAS_JUMP;
}
@@ -440,7 +441,7 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, code);
- tcg_gen_mov_tl(cpu_R[R_PC], load_gpr(dc, instr.a));
+ tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a));
tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next);
dc->base.is_jmp = DISAS_JUMP;
@@ -742,7 +743,7 @@ illegal_op:
t_gen_helper_raise_exception(dc, EXCP_ILLEGAL);
}
-static const char * const regnames[] = {
+static const char * const regnames[NUM_CORE_REGS] = {
"zero", "at", "r2", "r3",
"r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11",
@@ -759,7 +760,6 @@ static const char * const regnames[] = {
"reserved6", "reserved7", "reserved8", "reserved9",
"reserved10", "reserved11", "reserved12", "reserved13",
"reserved14", "reserved15", "reserved16", "reserved17",
- "rpc"
};
#include "exec/gen-icount.h"
@@ -827,7 +827,7 @@ static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
case DISAS_TOO_MANY:
case DISAS_UPDATE:
/* Save the current PC back into the CPU register */
- tcg_gen_movi_tl(cpu_R[R_PC], dc->base.pc_next);
+ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
tcg_gen_exit_tb(NULL, 0);
break;
@@ -877,8 +877,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
return;
}
- qemu_fprintf(f, "IN: PC=%x %s\n",
- env->regs[R_PC], lookup_symbol(env->regs[R_PC]));
+ qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc));
for (i = 0; i < NUM_CORE_REGS; i++) {
qemu_fprintf(f, "%9s=%8.8x ", regnames[i], env->regs[i]);
@@ -904,10 +903,12 @@ void nios2_tcg_init(void)
offsetof(CPUNios2State, regs[i]),
regnames[i]);
}
+ cpu_pc = tcg_global_mem_new(cpu_env,
+ offsetof(CPUNios2State, pc), "pc");
}
void restore_state_to_opc(CPUNios2State *env, TranslationBlock *tb,
target_ulong *data)
{
- env->regs[R_PC] = data[0];
+ env->pc = data[0];
}
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 17/64] target/nios2: Split out helper for eret instruction
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (15 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 16/64] target/nios2: Split PC out of env->regs[] Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 18/64] target/nios2: Fix BRET instruction Richard Henderson
` (46 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Amir Gonnen
From: Amir Gonnen <amir.gonnen@neuroblade.ai>
The implementation of eret will become much more complex
with the introduction of shadow registers.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Amir Gonnen <amir.gonnen@neuroblade.ai>
Message-Id: <20220303153906.2024748-3-amir.gonnen@neuroblade.ai>
[rth: Split out of a larger patch for shadow register sets.
Directly exit to the cpu loop from the helper.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/helper.h | 1 +
target/nios2/op_helper.c | 9 +++++++++
target/nios2/translate.c | 10 ++++++----
3 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/target/nios2/helper.h b/target/nios2/helper.h
index a44ecfdf7a..525b6b685b 100644
--- a/target/nios2/helper.h
+++ b/target/nios2/helper.h
@@ -21,6 +21,7 @@
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
#if !defined(CONFIG_USER_ONLY)
+DEF_HELPER_3(eret, noreturn, env, i32, i32)
DEF_HELPER_2(mmu_write_tlbacc, void, env, i32)
DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32)
DEF_HELPER_2(mmu_write_pteaddr, void, env, i32)
diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
index caa885f7b4..ee5ad8b23f 100644
--- a/target/nios2/op_helper.c
+++ b/target/nios2/op_helper.c
@@ -30,3 +30,12 @@ void helper_raise_exception(CPUNios2State *env, uint32_t index)
cs->exception_index = index;
cpu_loop_exit(cs);
}
+
+#ifndef CONFIG_USER_ONLY
+void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc)
+{
+ env->regs[CR_STATUS] = new_status;
+ env->pc = new_pc;
+ cpu_loop_exit(env_cpu(env));
+}
+#endif /* !CONFIG_USER_ONLY */
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 226bd9e30b..53699ee088 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -391,10 +391,12 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
return;
}
- tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]);
- tcg_gen_mov_tl(cpu_pc, cpu_R[R_EA]);
-
- dc->base.is_jmp = DISAS_JUMP;
+#ifdef CONFIG_USER_ONLY
+ g_assert_not_reached();
+#else
+ gen_helper_eret(cpu_env, cpu_R[CR_ESTATUS], cpu_R[R_EA]);
+ dc->base.is_jmp = DISAS_NORETURN;
+#endif
}
/* PC <- ra */
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 18/64] target/nios2: Fix BRET instruction
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (16 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 17/64] target/nios2: Split out helper for eret instruction Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 19/64] target/nios2: Do not create TCGv for control registers Richard Henderson
` (45 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
We had failed to copy BSTATUS back to STATUS, and diagnose
supervisor-only. The spec is light on the specifics of the
implementation of bret, but it is an easy assumption that
the restore into STATUS should work the same as eret.
Therefore, reuse the existing helper_eret.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/translate.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 53699ee088..3694f2503b 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -407,12 +407,22 @@ static void ret(DisasContext *dc, uint32_t code, uint32_t flags)
dc->base.is_jmp = DISAS_JUMP;
}
-/* PC <- ba */
+/*
+ * status <- bstatus
+ * PC <- ba
+ */
static void bret(DisasContext *dc, uint32_t code, uint32_t flags)
{
- tcg_gen_mov_tl(cpu_pc, cpu_R[R_BA]);
+ if (!gen_check_supervisor(dc)) {
+ return;
+ }
- dc->base.is_jmp = DISAS_JUMP;
+#ifdef CONFIG_USER_ONLY
+ g_assert_not_reached();
+#else
+ gen_helper_eret(cpu_env, cpu_R[CR_BSTATUS], cpu_R[R_BA]);
+ dc->base.is_jmp = DISAS_NORETURN;
+#endif
}
/* PC <- rA */
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 19/64] target/nios2: Do not create TCGv for control registers
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (17 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 18/64] target/nios2: Fix BRET instruction Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 20/64] linux-user/nios2: Only initialize SP and PC in target_cpu_copy_regs Richard Henderson
` (44 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
We don't need to reference them often, and when we do it
is just as easy to load/store from cpu_env directly.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/translate.c | 33 ++++++++++++++++++++++++++-------
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 3694f2503b..6c739bfa5e 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -103,7 +103,7 @@ typedef struct DisasContext {
int mem_idx;
} DisasContext;
-static TCGv cpu_R[NUM_CORE_REGS];
+static TCGv cpu_R[NUM_GP_REGS];
static TCGv cpu_pc;
typedef struct Nios2Instruction {
@@ -394,7 +394,11 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
#ifdef CONFIG_USER_ONLY
g_assert_not_reached();
#else
- gen_helper_eret(cpu_env, cpu_R[CR_ESTATUS], cpu_R[R_EA]);
+ TCGv tmp = tcg_temp_new();
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_ESTATUS]));
+ gen_helper_eret(cpu_env, tmp, cpu_R[R_EA]);
+ tcg_temp_free(tmp);
+
dc->base.is_jmp = DISAS_NORETURN;
#endif
}
@@ -420,7 +424,11 @@ static void bret(DisasContext *dc, uint32_t code, uint32_t flags)
#ifdef CONFIG_USER_ONLY
g_assert_not_reached();
#else
- gen_helper_eret(cpu_env, cpu_R[CR_BSTATUS], cpu_R[R_BA]);
+ TCGv tmp = tcg_temp_new();
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_BSTATUS]));
+ gen_helper_eret(cpu_env, tmp, cpu_R[R_BA]);
+ tcg_temp_free(tmp);
+
dc->base.is_jmp = DISAS_NORETURN;
#endif
}
@@ -463,6 +471,7 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags)
static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, code);
+ TCGv t1, t2;
if (!gen_check_supervisor(dc)) {
return;
@@ -482,10 +491,19 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
* must perform the AND here, and anywhere else we need the
* guest value of ipending.
*/
- tcg_gen_and_tl(cpu_R[instr.c], cpu_R[CR_IPENDING], cpu_R[CR_IENABLE]);
+ t1 = tcg_temp_new();
+ t2 = tcg_temp_new();
+ tcg_gen_ld_tl(t1, cpu_env,
+ offsetof(CPUNios2State, regs[CR_IPENDING]));
+ tcg_gen_ld_tl(t2, cpu_env,
+ offsetof(CPUNios2State, regs[CR_IENABLE]));
+ tcg_gen_and_tl(cpu_R[instr.c], t1, t2);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
break;
default:
- tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]);
+ tcg_gen_ld_tl(cpu_R[instr.c], cpu_env,
+ offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE]));
break;
}
}
@@ -522,7 +540,8 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
dc->base.is_jmp = DISAS_UPDATE;
/* fall through */
default:
- tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v);
+ tcg_gen_st_tl(v, cpu_env,
+ offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE]));
break;
}
#endif
@@ -910,7 +929,7 @@ void nios2_tcg_init(void)
{
int i;
- for (i = 0; i < NUM_CORE_REGS; i++) {
+ for (i = 0; i < NUM_GP_REGS; i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUNios2State, regs[i]),
regnames[i]);
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 20/64] linux-user/nios2: Only initialize SP and PC in target_cpu_copy_regs
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (18 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 19/64] target/nios2: Do not create TCGv for control registers Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 21/64] target/nios2: Remove cpu_interrupts_enabled Richard Henderson
` (43 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Drop the set of estatus in init_thread; it was clearly intended
to be setting the value of CR_STATUS for the application, but we
never actually performed that copy. However, the proper value is
set in nios2_cpu_reset so we don't need to do anything here.
We only initialize SP and EA in init_thread, there's no value in
copying other uninitialized data into ENV.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/elfload.c | 1 -
linux-user/nios2/cpu_loop.c | 22 ----------------------
2 files changed, 23 deletions(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 397dec5eb8..61063fd974 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1096,7 +1096,6 @@ static void init_thread(struct target_pt_regs *regs, struct image_info *infop)
{
regs->ea = infop->entry;
regs->sp = infop->start_stack;
- regs->estatus = 0x3;
}
#define LO_COMMPAGE TARGET_PAGE_SIZE
diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c
index a941f9032e..c5e68ac048 100644
--- a/linux-user/nios2/cpu_loop.c
+++ b/linux-user/nios2/cpu_loop.c
@@ -133,28 +133,6 @@ void cpu_loop(CPUNios2State *env)
void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
{
- env->regs[0] = 0;
- env->regs[1] = regs->r1;
- env->regs[2] = regs->r2;
- env->regs[3] = regs->r3;
- env->regs[4] = regs->r4;
- env->regs[5] = regs->r5;
- env->regs[6] = regs->r6;
- env->regs[7] = regs->r7;
- env->regs[8] = regs->r8;
- env->regs[9] = regs->r9;
- env->regs[10] = regs->r10;
- env->regs[11] = regs->r11;
- env->regs[12] = regs->r12;
- env->regs[13] = regs->r13;
- env->regs[14] = regs->r14;
- env->regs[15] = regs->r15;
- /* TODO: unsigned long orig_r2; */
- env->regs[R_RA] = regs->ra;
- env->regs[R_FP] = regs->fp;
env->regs[R_SP] = regs->sp;
- env->regs[R_GP] = regs->gp;
- env->regs[CR_ESTATUS] = regs->estatus;
env->pc = regs->ea;
- /* TODO: unsigned long orig_r7; */
}
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 21/64] target/nios2: Remove cpu_interrupts_enabled
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (19 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 20/64] linux-user/nios2: Only initialize SP and PC in target_cpu_copy_regs Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 22/64] target/nios2: Split control registers away from general registers Richard Henderson
` (42 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
This function is unused. The real computation of this value
is located in nios2_cpu_exec_interrupt.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 5 -----
1 file changed, 5 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index dbd9d1b587..413e195187 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -222,11 +222,6 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
bool probe, uintptr_t retaddr);
#endif
-static inline int cpu_interrupts_enabled(CPUNios2State *env)
-{
- return env->regs[CR_STATUS] & CR_STATUS_PIE;
-}
-
typedef CPUNios2State CPUArchState;
typedef Nios2CPU ArchCPU;
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 22/64] target/nios2: Split control registers away from general registers
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (20 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 21/64] target/nios2: Remove cpu_interrupts_enabled Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 23/64] target/nios2: Clean up nios2_cpu_dump_state Richard Henderson
` (41 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Place the control registers into their own array, env->ctrl[].
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 43 ++++++++--------
target/nios2/cpu.c | 19 +++----
target/nios2/helper.c | 106 +++++++++++++++++++--------------------
target/nios2/mmu.c | 26 +++++-----
target/nios2/op_helper.c | 2 +-
target/nios2/translate.c | 35 +++++++------
6 files changed, 118 insertions(+), 113 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 413e195187..872bc2a46f 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -59,9 +59,6 @@ struct Nios2CPUClass {
#define NUM_GP_REGS 32
#define NUM_CR_REGS 32
-/* GP regs + CR regs */
-#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS)
-
/* General purpose register aliases */
#define R_ZERO 0
#define R_AT 1
@@ -81,8 +78,7 @@ struct Nios2CPUClass {
#define R_RA 31
/* Control register aliases */
-#define CR_BASE NUM_GP_REGS
-#define CR_STATUS (CR_BASE + 0)
+#define CR_STATUS 0
#define CR_STATUS_PIE (1 << 0)
#define CR_STATUS_U (1 << 1)
#define CR_STATUS_EH (1 << 2)
@@ -92,19 +88,19 @@ struct Nios2CPUClass {
#define CR_STATUS_PRS (63 << 16)
#define CR_STATUS_NMI (1 << 22)
#define CR_STATUS_RSIE (1 << 23)
-#define CR_ESTATUS (CR_BASE + 1)
-#define CR_BSTATUS (CR_BASE + 2)
-#define CR_IENABLE (CR_BASE + 3)
-#define CR_IPENDING (CR_BASE + 4)
-#define CR_CPUID (CR_BASE + 5)
-#define CR_CTL6 (CR_BASE + 6)
-#define CR_EXCEPTION (CR_BASE + 7)
-#define CR_PTEADDR (CR_BASE + 8)
+#define CR_ESTATUS 1
+#define CR_BSTATUS 2
+#define CR_IENABLE 3
+#define CR_IPENDING 4
+#define CR_CPUID 5
+#define CR_CTL6 6
+#define CR_EXCEPTION 7
+#define CR_PTEADDR 8
#define CR_PTEADDR_PTBASE_SHIFT 22
#define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT)
#define CR_PTEADDR_VPN_SHIFT 2
#define CR_PTEADDR_VPN_MASK (0xFFFFF << CR_PTEADDR_VPN_SHIFT)
-#define CR_TLBACC (CR_BASE + 9)
+#define CR_TLBACC 9
#define CR_TLBACC_IGN_SHIFT 25
#define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT)
#define CR_TLBACC_C (1 << 24)
@@ -113,7 +109,7 @@ struct Nios2CPUClass {
#define CR_TLBACC_X (1 << 21)
#define CR_TLBACC_G (1 << 20)
#define CR_TLBACC_PFN_MASK 0x000FFFFF
-#define CR_TLBMISC (CR_BASE + 10)
+#define CR_TLBMISC 10
#define CR_TLBMISC_WAY_SHIFT 20
#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT)
#define CR_TLBMISC_RD (1 << 19)
@@ -124,11 +120,11 @@ struct Nios2CPUClass {
#define CR_TLBMISC_BAD (1 << 2)
#define CR_TLBMISC_PERM (1 << 1)
#define CR_TLBMISC_D (1 << 0)
-#define CR_ENCINJ (CR_BASE + 11)
-#define CR_BADADDR (CR_BASE + 12)
-#define CR_CONFIG (CR_BASE + 13)
-#define CR_MPUBASE (CR_BASE + 14)
-#define CR_MPUACC (CR_BASE + 15)
+#define CR_ENCINJ 11
+#define CR_BADADDR 12
+#define CR_CONFIG 13
+#define CR_MPUBASE 14
+#define CR_MPUACC 15
/* Exceptions */
#define EXCP_BREAK 0x1000
@@ -154,7 +150,8 @@ struct Nios2CPUClass {
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
struct CPUArchState {
- uint32_t regs[NUM_CORE_REGS];
+ uint32_t regs[NUM_GP_REGS];
+ uint32_t ctrl[NUM_CR_REGS];
uint32_t pc;
#if !defined(CONFIG_USER_ONLY)
@@ -212,7 +209,7 @@ void do_nios2_semihosting(CPUNios2State *env);
static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
{
- return (env->regs[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX :
+ return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX :
MMU_SUPERVISOR_IDX;
}
@@ -232,7 +229,7 @@ static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc,
{
*pc = env->pc;
*cs_base = 0;
- *flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U));
+ *flags = env->ctrl[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U);
}
#endif /* NIOS2_CPU_H */
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index dc1551241e..fce16a2e77 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -48,14 +48,15 @@ static void nios2_cpu_reset(DeviceState *dev)
ncc->parent_reset(dev);
- memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS);
+ memset(env->regs, 0, sizeof(env->regs));
+ memset(env->ctrl, 0, sizeof(env->ctrl));
env->pc = cpu->reset_addr;
#if defined(CONFIG_USER_ONLY)
/* Start in user mode with interrupts enabled. */
- env->regs[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE;
+ env->ctrl[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE;
#else
- env->regs[CR_STATUS] = 0;
+ env->ctrl[CR_STATUS] = 0;
#endif
}
@@ -66,9 +67,9 @@ static void nios2_cpu_set_irq(void *opaque, int irq, int level)
CPUNios2State *env = &cpu->env;
CPUState *cs = CPU(cpu);
- env->regs[CR_IPENDING] = deposit32(env->regs[CR_IPENDING], irq, 1, !!level);
+ env->ctrl[CR_IPENDING] = deposit32(env->ctrl[CR_IPENDING], irq, 1, !!level);
- if (env->regs[CR_IPENDING]) {
+ if (env->ctrl[CR_IPENDING]) {
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
@@ -126,8 +127,8 @@ static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
CPUNios2State *env = &cpu->env;
if ((interrupt_request & CPU_INTERRUPT_HARD) &&
- (env->regs[CR_STATUS] & CR_STATUS_PIE) &&
- (env->regs[CR_IPENDING] & env->regs[CR_IENABLE])) {
+ (env->ctrl[CR_STATUS] & CR_STATUS_PIE) &&
+ (env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE])) {
cs->exception_index = EXCP_IRQ;
nios2_cpu_do_interrupt(cs);
return true;
@@ -158,7 +159,7 @@ static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
} else if (n == 32) { /* PC */
return gdb_get_reg32(mem_buf, env->pc);
} else if (n < 49) { /* Status regs */
- return gdb_get_reg32(mem_buf, env->regs[n - 1]);
+ return gdb_get_reg32(mem_buf, env->ctrl[n - 33]);
}
/* Invalid regs */
@@ -180,7 +181,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
} else if (n == 32) { /* PC */
env->pc = ldl_p(mem_buf);
} else if (n < 49) { /* Status regs */
- env->regs[n - 1] = ldl_p(mem_buf);
+ env->ctrl[n - 33] = ldl_p(mem_buf);
}
return 4;
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 34b3e18e37..2e5f5b8b54 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -36,38 +36,38 @@ void nios2_cpu_do_interrupt(CPUState *cs)
switch (cs->exception_index) {
case EXCP_IRQ:
- assert(env->regs[CR_STATUS] & CR_STATUS_PIE);
+ assert(env->ctrl[CR_STATUS] & CR_STATUS_PIE);
qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc);
- env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
- env->regs[CR_STATUS] |= CR_STATUS_IH;
- env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
+ env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS];
+ env->ctrl[CR_STATUS] |= CR_STATUS_IH;
+ env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
- env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
- env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
+ env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2);
+ env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
env->regs[R_EA] = env->pc + 4;
env->pc = cpu->exception_addr;
break;
case EXCP_TLBD:
- if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
+ if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc);
/* Fast TLB miss */
/* Variation from the spec. Table 3-35 of the cpu reference shows
* estatus not being changed for TLB miss but this appears to
* be incorrect. */
- env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
- env->regs[CR_STATUS] |= CR_STATUS_EH;
- env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
+ env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS];
+ env->ctrl[CR_STATUS] |= CR_STATUS_EH;
+ env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
- env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
- env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
+ env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2);
+ env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
- env->regs[CR_TLBMISC] &= ~CR_TLBMISC_DBL;
- env->regs[CR_TLBMISC] |= CR_TLBMISC_WR;
+ env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL;
+ env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR;
env->regs[R_EA] = env->pc + 4;
env->pc = cpu->fast_tlb_miss_addr;
@@ -75,13 +75,13 @@ void nios2_cpu_do_interrupt(CPUState *cs)
qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc);
/* Double TLB miss */
- env->regs[CR_STATUS] |= CR_STATUS_EH;
- env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
+ env->ctrl[CR_STATUS] |= CR_STATUS_EH;
+ env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
- env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
- env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
+ env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2);
+ env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
- env->regs[CR_TLBMISC] |= CR_TLBMISC_DBL;
+ env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL;
env->pc = cpu->exception_addr;
}
@@ -92,15 +92,15 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_TLBX:
qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc);
- env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
- env->regs[CR_STATUS] |= CR_STATUS_EH;
- env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
+ env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS];
+ env->ctrl[CR_STATUS] |= CR_STATUS_EH;
+ env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
- env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
- env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
+ env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2);
+ env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
- if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
- env->regs[CR_TLBMISC] |= CR_TLBMISC_WR;
+ if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
+ env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR;
}
env->regs[R_EA] = env->pc + 4;
@@ -112,16 +112,16 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_SUPERD:
qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc);
- if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
- env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
+ if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
+ env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS];
env->regs[R_EA] = env->pc + 4;
}
- env->regs[CR_STATUS] |= CR_STATUS_EH;
- env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
+ env->ctrl[CR_STATUS] |= CR_STATUS_EH;
+ env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
- env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
- env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
+ env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2);
+ env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
env->pc = cpu->exception_addr;
break;
@@ -130,16 +130,16 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_TRAP:
qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc);
- if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
- env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
+ if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
+ env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS];
env->regs[R_EA] = env->pc + 4;
}
- env->regs[CR_STATUS] |= CR_STATUS_EH;
- env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
+ env->ctrl[CR_STATUS] |= CR_STATUS_EH;
+ env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
- env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
- env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
+ env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2);
+ env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
env->pc = cpu->exception_addr;
break;
@@ -155,16 +155,16 @@ void nios2_cpu_do_interrupt(CPUState *cs)
break;
}
- if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
- env->regs[CR_BSTATUS] = env->regs[CR_STATUS];
+ if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
+ env->ctrl[CR_BSTATUS] = env->ctrl[CR_STATUS];
env->regs[R_BA] = env->pc + 4;
}
- env->regs[CR_STATUS] |= CR_STATUS_EH;
- env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
+ env->ctrl[CR_STATUS] |= CR_STATUS_EH;
+ env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
- env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
- env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
+ env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2);
+ env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
env->pc = cpu->exception_addr;
break;
@@ -207,8 +207,8 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
Nios2CPU *cpu = NIOS2_CPU(cs);
CPUNios2State *env = &cpu->env;
- env->regs[CR_BADADDR] = addr;
- env->regs[CR_EXCEPTION] = EXCP_UNALIGN << 2;
+ env->ctrl[CR_BADADDR] = addr;
+ env->ctrl[CR_EXCEPTION] = EXCP_UNALIGN << 2;
helper_raise_exception(env, EXCP_UNALIGN);
}
@@ -246,7 +246,7 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
return false;
}
cs->exception_index = EXCP_SUPERA;
- env->regs[CR_BADADDR] = address;
+ env->ctrl[CR_BADADDR] = address;
cpu_loop_exit_restore(cs, retaddr);
}
}
@@ -275,15 +275,15 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
}
if (access_type == MMU_INST_FETCH) {
- env->regs[CR_TLBMISC] &= ~CR_TLBMISC_D;
+ env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_D;
} else {
- env->regs[CR_TLBMISC] |= CR_TLBMISC_D;
+ env->ctrl[CR_TLBMISC] |= CR_TLBMISC_D;
}
- env->regs[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK;
- env->regs[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK;
- env->mmu.pteaddr_wr = env->regs[CR_PTEADDR];
+ env->ctrl[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK;
+ env->ctrl[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK;
+ env->mmu.pteaddr_wr = env->ctrl[CR_PTEADDR];
cs->exception_index = excp;
- env->regs[CR_BADADDR] = address;
+ env->ctrl[CR_BADADDR] = address;
cpu_loop_exit_restore(cs, retaddr);
}
diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c
index 4daab2a7ab..95900724e8 100644
--- a/target/nios2/mmu.c
+++ b/target/nios2/mmu.c
@@ -95,8 +95,8 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
v & CR_TLBACC_PFN_MASK);
/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
- if (env->regs[CR_TLBMISC] & CR_TLBMISC_WR) {
- int way = (env->regs[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT);
+ if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) {
+ int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT);
int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2;
int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
int g = (v & CR_TLBACC_G) ? 1 : 0;
@@ -117,8 +117,8 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
entry->data = newData;
}
/* Auto-increment tlbmisc.WAY */
- env->regs[CR_TLBMISC] =
- (env->regs[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) |
+ env->ctrl[CR_TLBMISC] =
+ (env->ctrl[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) |
(((way + 1) & (cpu->tlb_num_ways - 1)) <<
CR_TLBMISC_WAY_SHIFT);
}
@@ -153,17 +153,17 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
&env->mmu.tlb[(way * cpu->tlb_num_ways) +
(vpn & env->mmu.tlb_entry_mask)];
- env->regs[CR_TLBACC] &= CR_TLBACC_IGN_MASK;
- env->regs[CR_TLBACC] |= entry->data;
- env->regs[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0;
- env->regs[CR_TLBMISC] =
+ env->ctrl[CR_TLBACC] &= CR_TLBACC_IGN_MASK;
+ env->ctrl[CR_TLBACC] |= entry->data;
+ env->ctrl[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0;
+ env->ctrl[CR_TLBMISC] =
(v & ~CR_TLBMISC_PID_MASK) |
((entry->tag & ((1 << cpu->pid_num_bits) - 1)) <<
CR_TLBMISC_PID_SHIFT);
- env->regs[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK;
- env->regs[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT;
+ env->ctrl[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK;
+ env->ctrl[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT;
} else {
- env->regs[CR_TLBMISC] = v;
+ env->ctrl[CR_TLBMISC] = v;
}
env->mmu.tlbmisc_wr = v;
@@ -175,8 +175,8 @@ void helper_mmu_write_pteaddr(CPUNios2State *env, uint32_t v)
(v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT);
/* Writes to PTEADDR don't change the read-back VPN value */
- env->regs[CR_PTEADDR] = (v & ~CR_PTEADDR_VPN_MASK) |
- (env->regs[CR_PTEADDR] & CR_PTEADDR_VPN_MASK);
+ env->ctrl[CR_PTEADDR] = ((v & ~CR_PTEADDR_VPN_MASK) |
+ (env->ctrl[CR_PTEADDR] & CR_PTEADDR_VPN_MASK));
env->mmu.pteaddr_wr = v;
}
diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
index ee5ad8b23f..08ed3b4598 100644
--- a/target/nios2/op_helper.c
+++ b/target/nios2/op_helper.c
@@ -34,7 +34,7 @@ void helper_raise_exception(CPUNios2State *env, uint32_t index)
#ifndef CONFIG_USER_ONLY
void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc)
{
- env->regs[CR_STATUS] = new_status;
+ env->ctrl[CR_STATUS] = new_status;
env->pc = new_pc;
cpu_loop_exit(env_cpu(env));
}
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 6c739bfa5e..308da8057c 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -395,7 +395,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
g_assert_not_reached();
#else
TCGv tmp = tcg_temp_new();
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_ESTATUS]));
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS]));
gen_helper_eret(cpu_env, tmp, cpu_R[R_EA]);
tcg_temp_free(tmp);
@@ -425,7 +425,7 @@ static void bret(DisasContext *dc, uint32_t code, uint32_t flags)
g_assert_not_reached();
#else
TCGv tmp = tcg_temp_new();
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_BSTATUS]));
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS]));
gen_helper_eret(cpu_env, tmp, cpu_R[R_BA]);
tcg_temp_free(tmp);
@@ -481,7 +481,7 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
return;
}
- switch (instr.imm5 + CR_BASE) {
+ switch (instr.imm5) {
case CR_IPENDING:
/*
* The value of the ipending register is synthetic.
@@ -493,17 +493,15 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
*/
t1 = tcg_temp_new();
t2 = tcg_temp_new();
- tcg_gen_ld_tl(t1, cpu_env,
- offsetof(CPUNios2State, regs[CR_IPENDING]));
- tcg_gen_ld_tl(t2, cpu_env,
- offsetof(CPUNios2State, regs[CR_IENABLE]));
+ tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDING]));
+ tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE]));
tcg_gen_and_tl(cpu_R[instr.c], t1, t2);
tcg_temp_free(t1);
tcg_temp_free(t2);
break;
default:
tcg_gen_ld_tl(cpu_R[instr.c], cpu_env,
- offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE]));
+ offsetof(CPUNios2State, ctrl[instr.imm5]));
break;
}
}
@@ -521,7 +519,7 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
R_TYPE(instr, code);
TCGv v = load_gpr(dc, instr.a);
- switch (instr.imm5 + CR_BASE) {
+ switch (instr.imm5) {
case CR_PTEADDR:
gen_helper_mmu_write_pteaddr(cpu_env, v);
break;
@@ -541,7 +539,7 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
/* fall through */
default:
tcg_gen_st_tl(v, cpu_env,
- offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE]));
+ offsetof(CPUNios2State, ctrl[instr.imm5]));
break;
}
#endif
@@ -774,7 +772,7 @@ illegal_op:
t_gen_helper_raise_exception(dc, EXCP_ILLEGAL);
}
-static const char * const regnames[NUM_CORE_REGS] = {
+static const char * const gr_regnames[NUM_GP_REGS] = {
"zero", "at", "r2", "r3",
"r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11",
@@ -783,6 +781,9 @@ static const char * const regnames[NUM_CORE_REGS] = {
"r20", "r21", "r22", "r23",
"et", "bt", "gp", "sp",
"fp", "ea", "ba", "ra",
+};
+
+static const char * const cr_regnames[NUM_CR_REGS] = {
"status", "estatus", "bstatus", "ienable",
"ipending", "cpuid", "reserved0", "exception",
"pteaddr", "tlbacc", "tlbmisc", "reserved1",
@@ -910,8 +911,14 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc));
- for (i = 0; i < NUM_CORE_REGS; i++) {
- qemu_fprintf(f, "%9s=%8.8x ", regnames[i], env->regs[i]);
+ for (i = 0; i < NUM_GP_REGS; i++) {
+ qemu_fprintf(f, "%9s=%8.8x ", gr_regnames[i], env->regs[i]);
+ if ((i + 1) % 4 == 0) {
+ qemu_fprintf(f, "\n");
+ }
+ }
+ for (i = 0; i < NUM_CR_REGS; i++) {
+ qemu_fprintf(f, "%9s=%8.8x ", cr_regnames[i], env->ctrl[i]);
if ((i + 1) % 4 == 0) {
qemu_fprintf(f, "\n");
}
@@ -932,7 +939,7 @@ void nios2_tcg_init(void)
for (i = 0; i < NUM_GP_REGS; i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUNios2State, regs[i]),
- regnames[i]);
+ gr_regnames[i]);
}
cpu_pc = tcg_global_mem_new(cpu_env,
offsetof(CPUNios2State, pc), "pc");
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 23/64] target/nios2: Clean up nios2_cpu_dump_state
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (21 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 22/64] target/nios2: Split control registers away from general registers Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 24/64] target/nios2: Use hw/registerfields.h for CR_STATUS fields Richard Henderson
` (40 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Do not print control registers for user-only mode.
Rename reserved control registers to "resN", where
N is the control register index.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/translate.c | 19 +++++++++----------
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 308da8057c..fc49a7101f 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -783,16 +783,18 @@ static const char * const gr_regnames[NUM_GP_REGS] = {
"fp", "ea", "ba", "ra",
};
+#ifndef CONFIG_USER_ONLY
static const char * const cr_regnames[NUM_CR_REGS] = {
"status", "estatus", "bstatus", "ienable",
- "ipending", "cpuid", "reserved0", "exception",
+ "ipending", "cpuid", "res6", "exception",
"pteaddr", "tlbacc", "tlbmisc", "reserved1",
"badaddr", "config", "mpubase", "mpuacc",
- "reserved2", "reserved3", "reserved4", "reserved5",
- "reserved6", "reserved7", "reserved8", "reserved9",
- "reserved10", "reserved11", "reserved12", "reserved13",
- "reserved14", "reserved15", "reserved16", "reserved17",
+ "res16", "res17", "res18", "res19",
+ "res20", "res21", "res22", "res23",
+ "res24", "res25", "res26", "res27",
+ "res28", "res29", "res30", "res31",
};
+#endif
#include "exec/gen-icount.h"
@@ -905,10 +907,6 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
CPUNios2State *env = &cpu->env;
int i;
- if (!env) {
- return;
- }
-
qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc));
for (i = 0; i < NUM_GP_REGS; i++) {
@@ -917,13 +915,14 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "\n");
}
}
+
+#if !defined(CONFIG_USER_ONLY)
for (i = 0; i < NUM_CR_REGS; i++) {
qemu_fprintf(f, "%9s=%8.8x ", cr_regnames[i], env->ctrl[i]);
if ((i + 1) % 4 == 0) {
qemu_fprintf(f, "\n");
}
}
-#if !defined(CONFIG_USER_ONLY)
qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n",
env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK,
(env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4,
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 24/64] target/nios2: Use hw/registerfields.h for CR_STATUS fields
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (22 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 23/64] target/nios2: Clean up nios2_cpu_dump_state Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 25/64] target/nios2: Use hw/registerfields.h for CR_EXCEPTION fields Richard Henderson
` (39 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Add all fields; retain the helper macros for single bit fields.
So far there are no uses of the multi-bit status fields.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 28 +++++++++++++++++++---------
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 872bc2a46f..44fc681c58 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -23,6 +23,7 @@
#include "exec/cpu-defs.h"
#include "hw/core/cpu.h"
+#include "hw/registerfields.h"
#include "qom/object.h"
typedef struct CPUArchState CPUNios2State;
@@ -79,15 +80,24 @@ struct Nios2CPUClass {
/* Control register aliases */
#define CR_STATUS 0
-#define CR_STATUS_PIE (1 << 0)
-#define CR_STATUS_U (1 << 1)
-#define CR_STATUS_EH (1 << 2)
-#define CR_STATUS_IH (1 << 3)
-#define CR_STATUS_IL (63 << 4)
-#define CR_STATUS_CRS (63 << 10)
-#define CR_STATUS_PRS (63 << 16)
-#define CR_STATUS_NMI (1 << 22)
-#define CR_STATUS_RSIE (1 << 23)
+
+FIELD(CR_STATUS, PIE, 0, 1)
+FIELD(CR_STATUS, U, 1, 1)
+FIELD(CR_STATUS, EH, 2, 1)
+FIELD(CR_STATUS, IH, 3, 1)
+FIELD(CR_STATUS, IL, 4, 6)
+FIELD(CR_STATUS, CRS, 10, 6)
+FIELD(CR_STATUS, PRS, 16, 6)
+FIELD(CR_STATUS, NMI, 22, 1)
+FIELD(CR_STATUS, RSIE, 23, 1)
+
+#define CR_STATUS_PIE R_CR_STATUS_PIE_MASK
+#define CR_STATUS_U R_CR_STATUS_U_MASK
+#define CR_STATUS_EH R_CR_STATUS_EH_MASK
+#define CR_STATUS_IH R_CR_STATUS_IH_MASK
+#define CR_STATUS_NMI R_CR_STATUS_NMI_MASK
+#define CR_STATUS_RSIE R_CR_STATUS_RSIE_MASK
+
#define CR_ESTATUS 1
#define CR_BSTATUS 2
#define CR_IENABLE 3
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 25/64] target/nios2: Use hw/registerfields.h for CR_EXCEPTION fields
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (23 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 24/64] target/nios2: Use hw/registerfields.h for CR_STATUS fields Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 26/64] target/nios2: Use hw/registerfields.h for CR_TLBADDR fields Richard Henderson
` (38 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Use FIELD_DP32 instead of manual shifting and masking.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 4 ++++
target/nios2/helper.c | 37 ++++++++++++++++++++++---------------
2 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 44fc681c58..114b494294 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -105,6 +105,10 @@ FIELD(CR_STATUS, RSIE, 23, 1)
#define CR_CPUID 5
#define CR_CTL6 6
#define CR_EXCEPTION 7
+
+FIELD(CR_EXCEPTION, CAUSE, 2, 5)
+FIELD(CR_EXCEPTION, ECCFTL, 31, 1)
+
#define CR_PTEADDR 8
#define CR_PTEADDR_PTBASE_SHIFT 22
#define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT)
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 2e5f5b8b54..b30740824c 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -44,8 +44,9 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->ctrl[CR_STATUS] |= CR_STATUS_IH;
env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
- env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2);
- env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
+ env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
+ CR_EXCEPTION, CAUSE,
+ cs->exception_index);
env->regs[R_EA] = env->pc + 4;
env->pc = cpu->exception_addr;
@@ -63,8 +64,9 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->ctrl[CR_STATUS] |= CR_STATUS_EH;
env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
- env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2);
- env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
+ env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
+ CR_EXCEPTION, CAUSE,
+ cs->exception_index);
env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL;
env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR;
@@ -78,8 +80,9 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->ctrl[CR_STATUS] |= CR_STATUS_EH;
env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
- env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2);
- env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
+ env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
+ CR_EXCEPTION, CAUSE,
+ cs->exception_index);
env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL;
@@ -96,8 +99,9 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->ctrl[CR_STATUS] |= CR_STATUS_EH;
env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
- env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2);
- env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
+ env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
+ CR_EXCEPTION, CAUSE,
+ cs->exception_index);
if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR;
@@ -120,8 +124,9 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->ctrl[CR_STATUS] |= CR_STATUS_EH;
env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
- env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2);
- env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
+ env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
+ CR_EXCEPTION, CAUSE,
+ cs->exception_index);
env->pc = cpu->exception_addr;
break;
@@ -138,8 +143,9 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->ctrl[CR_STATUS] |= CR_STATUS_EH;
env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
- env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2);
- env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
+ env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
+ CR_EXCEPTION, CAUSE,
+ cs->exception_index);
env->pc = cpu->exception_addr;
break;
@@ -163,8 +169,9 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->ctrl[CR_STATUS] |= CR_STATUS_EH;
env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
- env->ctrl[CR_EXCEPTION] &= ~(0x1F << 2);
- env->ctrl[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
+ env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
+ CR_EXCEPTION, CAUSE,
+ cs->exception_index);
env->pc = cpu->exception_addr;
break;
@@ -208,7 +215,7 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
CPUNios2State *env = &cpu->env;
env->ctrl[CR_BADADDR] = addr;
- env->ctrl[CR_EXCEPTION] = EXCP_UNALIGN << 2;
+ env->ctrl[CR_EXCEPTION] = FIELD_DP32(0, CR_EXCEPTION, CAUSE, EXCP_UNALIGN);
helper_raise_exception(env, EXCP_UNALIGN);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 26/64] target/nios2: Use hw/registerfields.h for CR_TLBADDR fields
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (24 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 25/64] target/nios2: Use hw/registerfields.h for CR_EXCEPTION fields Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 27/64] target/nios2: Use hw/registerfields.h for CR_TLBACC fields Richard Henderson
` (37 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Use FIELD_EX32 and FIELD_DP32 instead of manual manipulation
of the fields.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 8 ++++----
target/nios2/helper.c | 4 ++--
target/nios2/mmu.c | 17 +++++++++--------
target/nios2/translate.c | 2 +-
4 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 114b494294..67ca62fc1f 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -110,10 +110,10 @@ FIELD(CR_EXCEPTION, CAUSE, 2, 5)
FIELD(CR_EXCEPTION, ECCFTL, 31, 1)
#define CR_PTEADDR 8
-#define CR_PTEADDR_PTBASE_SHIFT 22
-#define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT)
-#define CR_PTEADDR_VPN_SHIFT 2
-#define CR_PTEADDR_VPN_MASK (0xFFFFF << CR_PTEADDR_VPN_SHIFT)
+
+FIELD(CR_PTEADDR, VPN, 2, 20)
+FIELD(CR_PTEADDR, PTBASE, 22, 10)
+
#define CR_TLBACC 9
#define CR_TLBACC_IGN_SHIFT 25
#define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT)
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index b30740824c..c2d0afe1b6 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -286,8 +286,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
} else {
env->ctrl[CR_TLBMISC] |= CR_TLBMISC_D;
}
- env->ctrl[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK;
- env->ctrl[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK;
+ env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR, VPN,
+ address >> TARGET_PAGE_BITS);
env->mmu.pteaddr_wr = env->ctrl[CR_PTEADDR];
cs->exception_index = excp;
diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c
index 95900724e8..75afc56daf 100644
--- a/target/nios2/mmu.c
+++ b/target/nios2/mmu.c
@@ -97,7 +97,7 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) {
int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT);
- int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2;
+ int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
int g = (v & CR_TLBACC_G) ? 1 : 0;
int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0;
@@ -148,7 +148,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
/* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */
if (v & CR_TLBMISC_RD) {
int way = (v >> CR_TLBMISC_WAY_SHIFT);
- int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2;
+ int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
Nios2TLBEntry *entry =
&env->mmu.tlb[(way * cpu->tlb_num_ways) +
(vpn & env->mmu.tlb_entry_mask)];
@@ -160,8 +160,9 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
(v & ~CR_TLBMISC_PID_MASK) |
((entry->tag & ((1 << cpu->pid_num_bits) - 1)) <<
CR_TLBMISC_PID_SHIFT);
- env->ctrl[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK;
- env->ctrl[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT;
+ env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR],
+ CR_PTEADDR, VPN,
+ entry->tag >> TARGET_PAGE_BITS);
} else {
env->ctrl[CR_TLBMISC] = v;
}
@@ -171,12 +172,12 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
void helper_mmu_write_pteaddr(CPUNios2State *env, uint32_t v)
{
- trace_nios2_mmu_write_pteaddr(v >> CR_PTEADDR_PTBASE_SHIFT,
- (v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT);
+ trace_nios2_mmu_write_pteaddr(FIELD_EX32(v, CR_PTEADDR, PTBASE),
+ FIELD_EX32(v, CR_PTEADDR, VPN));
/* Writes to PTEADDR don't change the read-back VPN value */
- env->ctrl[CR_PTEADDR] = ((v & ~CR_PTEADDR_VPN_MASK) |
- (env->ctrl[CR_PTEADDR] & CR_PTEADDR_VPN_MASK));
+ env->ctrl[CR_PTEADDR] = ((v & ~R_CR_PTEADDR_VPN_MASK) |
+ (env->ctrl[CR_PTEADDR] & R_CR_PTEADDR_VPN_MASK));
env->mmu.pteaddr_wr = v;
}
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index fc49a7101f..baa22c5101 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -924,7 +924,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n",
- env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK,
+ env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK,
(env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4,
env->mmu.tlbacc_wr);
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 27/64] target/nios2: Use hw/registerfields.h for CR_TLBACC fields
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (25 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 26/64] target/nios2: Use hw/registerfields.h for CR_TLBADDR fields Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:16 ` [PATCH v7 28/64] target/nios2: Rename CR_TLBMISC_WR to CR_TLBMISC_WE Richard Henderson
` (36 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Retain the helper macros for single bit fields as aliases to
the longer R_*_MASK names. Use FIELD_EX32 and FIELD_DP32
instead of manually manipulating the fields.
Since we're rewriting the references to CR_TLBACC_IGN_* anyway,
we correct the name of this field to IG, which is its name in
the official CPU documentation.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 23 +++++++++++++++--------
target/nios2/mmu.c | 16 ++++++++--------
2 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 67ca62fc1f..11e9ed0063 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -115,14 +115,21 @@ FIELD(CR_PTEADDR, VPN, 2, 20)
FIELD(CR_PTEADDR, PTBASE, 22, 10)
#define CR_TLBACC 9
-#define CR_TLBACC_IGN_SHIFT 25
-#define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT)
-#define CR_TLBACC_C (1 << 24)
-#define CR_TLBACC_R (1 << 23)
-#define CR_TLBACC_W (1 << 22)
-#define CR_TLBACC_X (1 << 21)
-#define CR_TLBACC_G (1 << 20)
-#define CR_TLBACC_PFN_MASK 0x000FFFFF
+
+FIELD(CR_TLBACC, PFN, 0, 20)
+FIELD(CR_TLBACC, G, 20, 1)
+FIELD(CR_TLBACC, X, 21, 1)
+FIELD(CR_TLBACC, W, 22, 1)
+FIELD(CR_TLBACC, R, 23, 1)
+FIELD(CR_TLBACC, C, 24, 1)
+FIELD(CR_TLBACC, IG, 25, 7)
+
+#define CR_TLBACC_C R_CR_TLBACC_C_MASK
+#define CR_TLBACC_R R_CR_TLBACC_R_MASK
+#define CR_TLBACC_W R_CR_TLBACC_W_MASK
+#define CR_TLBACC_X R_CR_TLBACC_X_MASK
+#define CR_TLBACC_G R_CR_TLBACC_G_MASK
+
#define CR_TLBMISC 10
#define CR_TLBMISC_WAY_SHIFT 20
#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT)
diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c
index 75afc56daf..826cd2afb4 100644
--- a/target/nios2/mmu.c
+++ b/target/nios2/mmu.c
@@ -49,7 +49,7 @@ unsigned int mmu_translate(CPUNios2State *env,
}
lu->vaddr = vaddr & TARGET_PAGE_MASK;
- lu->paddr = (entry->data & CR_TLBACC_PFN_MASK) << TARGET_PAGE_BITS;
+ lu->paddr = FIELD_EX32(entry->data, CR_TLBACC, PFN) << TARGET_PAGE_BITS;
lu->prot = ((entry->data & CR_TLBACC_R) ? PAGE_READ : 0) |
((entry->data & CR_TLBACC_W) ? PAGE_WRITE : 0) |
((entry->data & CR_TLBACC_X) ? PAGE_EXEC : 0);
@@ -86,27 +86,27 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
CPUState *cs = env_cpu(env);
Nios2CPU *cpu = env_archcpu(env);
- trace_nios2_mmu_write_tlbacc(v >> CR_TLBACC_IGN_SHIFT,
+ trace_nios2_mmu_write_tlbacc(FIELD_EX32(v, CR_TLBACC, IG),
(v & CR_TLBACC_C) ? 'C' : '.',
(v & CR_TLBACC_R) ? 'R' : '.',
(v & CR_TLBACC_W) ? 'W' : '.',
(v & CR_TLBACC_X) ? 'X' : '.',
(v & CR_TLBACC_G) ? 'G' : '.',
- v & CR_TLBACC_PFN_MASK);
+ FIELD_EX32(v, CR_TLBACC, PFN));
/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) {
int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT);
int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
- int g = (v & CR_TLBACC_G) ? 1 : 0;
- int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0;
+ int g = FIELD_EX32(v, CR_TLBACC, G);
+ int valid = FIELD_EX32(vpn, CR_TLBACC, PFN) < 0xC0000;
Nios2TLBEntry *entry =
&env->mmu.tlb[(way * cpu->tlb_num_ways) +
(vpn & env->mmu.tlb_entry_mask)];
uint32_t newTag = (vpn << 12) | (g << 11) | (valid << 10) | pid;
uint32_t newData = v & (CR_TLBACC_C | CR_TLBACC_R | CR_TLBACC_W |
- CR_TLBACC_X | CR_TLBACC_PFN_MASK);
+ CR_TLBACC_X | R_CR_TLBACC_PFN_MASK);
if ((entry->tag != newTag) || (entry->data != newData)) {
if (entry->tag & (1 << 10)) {
@@ -153,7 +153,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
&env->mmu.tlb[(way * cpu->tlb_num_ways) +
(vpn & env->mmu.tlb_entry_mask)];
- env->ctrl[CR_TLBACC] &= CR_TLBACC_IGN_MASK;
+ env->ctrl[CR_TLBACC] &= R_CR_TLBACC_IG_MASK;
env->ctrl[CR_TLBACC] |= entry->data;
env->ctrl[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0;
env->ctrl[CR_TLBMISC] =
@@ -208,7 +208,7 @@ void dump_mmu(CPUNios2State *env)
entry->tag >> 12,
entry->tag & ((1 << cpu->pid_num_bits) - 1),
(entry->tag & (1 << 11)) ? 'G' : '-',
- entry->data & CR_TLBACC_PFN_MASK,
+ FIELD_EX32(entry->data, CR_TLBACC, PFN),
(entry->data & CR_TLBACC_C) ? 'C' : '-',
(entry->data & CR_TLBACC_R) ? 'R' : '-',
(entry->data & CR_TLBACC_W) ? 'W' : '-',
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 28/64] target/nios2: Rename CR_TLBMISC_WR to CR_TLBMISC_WE
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (26 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 27/64] target/nios2: Use hw/registerfields.h for CR_TLBACC fields Richard Henderson
@ 2022-04-21 15:16 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 29/64] target/nios2: Use hw/registerfields.h for CR_TLBMISC fields Richard Henderson
` (35 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
WE is the architectural name of the field, not WR.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 2 +-
target/nios2/helper.c | 4 ++--
target/nios2/mmu.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 11e9ed0063..54b592c422 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -134,7 +134,7 @@ FIELD(CR_TLBACC, IG, 25, 7)
#define CR_TLBMISC_WAY_SHIFT 20
#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT)
#define CR_TLBMISC_RD (1 << 19)
-#define CR_TLBMISC_WR (1 << 18)
+#define CR_TLBMISC_WE (1 << 18)
#define CR_TLBMISC_PID_SHIFT 4
#define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT)
#define CR_TLBMISC_DBL (1 << 3)
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index c2d0afe1b6..31d83e0291 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -69,7 +69,7 @@ void nios2_cpu_do_interrupt(CPUState *cs)
cs->exception_index);
env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL;
- env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR;
+ env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE;
env->regs[R_EA] = env->pc + 4;
env->pc = cpu->fast_tlb_miss_addr;
@@ -104,7 +104,7 @@ void nios2_cpu_do_interrupt(CPUState *cs)
cs->exception_index);
if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
- env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR;
+ env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE;
}
env->regs[R_EA] = env->pc + 4;
diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c
index 826cd2afb4..0f33ea5e04 100644
--- a/target/nios2/mmu.c
+++ b/target/nios2/mmu.c
@@ -95,7 +95,7 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
FIELD_EX32(v, CR_TLBACC, PFN));
/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
- if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) {
+ if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WE) {
int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT);
int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
@@ -133,7 +133,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT,
(v & CR_TLBMISC_RD) ? 'R' : '.',
- (v & CR_TLBMISC_WR) ? 'W' : '.',
+ (v & CR_TLBMISC_WE) ? 'W' : '.',
(v & CR_TLBMISC_DBL) ? '2' : '.',
(v & CR_TLBMISC_BAD) ? 'B' : '.',
(v & CR_TLBMISC_PERM) ? 'P' : '.',
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 29/64] target/nios2: Use hw/registerfields.h for CR_TLBMISC fields
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (27 preceding siblings ...)
2022-04-21 15:16 ` [PATCH v7 28/64] target/nios2: Rename CR_TLBMISC_WR to CR_TLBMISC_WE Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 30/64] target/nios2: Move R_FOO and CR_BAR into enumerations Richard Henderson
` (34 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Use FIELD_EX32 and FIELD_DP32 instead of managing the
masking by hand.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 29 +++++++++++++++++++----------
target/nios2/helper.c | 7 ++-----
target/nios2/mmu.c | 35 +++++++++++++++++------------------
target/nios2/translate.c | 2 +-
4 files changed, 39 insertions(+), 34 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 54b592c422..ec34cebf72 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -131,16 +131,25 @@ FIELD(CR_TLBACC, IG, 25, 7)
#define CR_TLBACC_G R_CR_TLBACC_G_MASK
#define CR_TLBMISC 10
-#define CR_TLBMISC_WAY_SHIFT 20
-#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT)
-#define CR_TLBMISC_RD (1 << 19)
-#define CR_TLBMISC_WE (1 << 18)
-#define CR_TLBMISC_PID_SHIFT 4
-#define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT)
-#define CR_TLBMISC_DBL (1 << 3)
-#define CR_TLBMISC_BAD (1 << 2)
-#define CR_TLBMISC_PERM (1 << 1)
-#define CR_TLBMISC_D (1 << 0)
+
+FIELD(CR_TLBMISC, D, 0, 1)
+FIELD(CR_TLBMISC, PERM, 1, 1)
+FIELD(CR_TLBMISC, BAD, 2, 1)
+FIELD(CR_TLBMISC, DBL, 3, 1)
+FIELD(CR_TLBMISC, PID, 4, 14)
+FIELD(CR_TLBMISC, WE, 18, 1)
+FIELD(CR_TLBMISC, RD, 19, 1)
+FIELD(CR_TLBMISC, WAY, 20, 4)
+FIELD(CR_TLBMISC, EE, 24, 1)
+
+#define CR_TLBMISC_EE R_CR_TLBMISC_EE_MASK
+#define CR_TLBMISC_RD R_CR_TLBMISC_RD_MASK
+#define CR_TLBMISC_WE R_CR_TLBMISC_WE_MASK
+#define CR_TLBMISC_DBL R_CR_TLBMISC_DBL_MASK
+#define CR_TLBMISC_BAD R_CR_TLBMISC_BAD_MASK
+#define CR_TLBMISC_PERM R_CR_TLBMISC_PERM_MASK
+#define CR_TLBMISC_D R_CR_TLBMISC_D_MASK
+
#define CR_ENCINJ 11
#define CR_BADADDR 12
#define CR_CONFIG 13
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 31d83e0291..a56aaaea18 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -281,11 +281,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
return false;
}
- if (access_type == MMU_INST_FETCH) {
- env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_D;
- } else {
- env->ctrl[CR_TLBMISC] |= CR_TLBMISC_D;
- }
+ env->ctrl[CR_TLBMISC] = FIELD_DP32(env->ctrl[CR_TLBMISC], CR_TLBMISC, D,
+ access_type != MMU_INST_FETCH);
env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR, VPN,
address >> TARGET_PAGE_BITS);
env->mmu.pteaddr_wr = env->ctrl[CR_PTEADDR];
diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c
index 0f33ea5e04..d9b690b78e 100644
--- a/target/nios2/mmu.c
+++ b/target/nios2/mmu.c
@@ -33,7 +33,7 @@ unsigned int mmu_translate(CPUNios2State *env,
target_ulong vaddr, int rw, int mmu_idx)
{
Nios2CPU *cpu = env_archcpu(env);
- int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
+ int pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID);
int vpn = vaddr >> 12;
int way, n_ways = cpu->tlb_num_ways;
@@ -96,9 +96,9 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WE) {
- int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT);
+ int way = FIELD_EX32(env->ctrl[CR_TLBMISC], CR_TLBMISC, WAY);
int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
- int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
+ int pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID);
int g = FIELD_EX32(v, CR_TLBACC, G);
int valid = FIELD_EX32(vpn, CR_TLBACC, PFN) < 0xC0000;
Nios2TLBEntry *entry =
@@ -117,10 +117,9 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
entry->data = newData;
}
/* Auto-increment tlbmisc.WAY */
- env->ctrl[CR_TLBMISC] =
- (env->ctrl[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) |
- (((way + 1) & (cpu->tlb_num_ways - 1)) <<
- CR_TLBMISC_WAY_SHIFT);
+ env->ctrl[CR_TLBMISC] = FIELD_DP32(env->ctrl[CR_TLBMISC],
+ CR_TLBMISC, WAY,
+ (way + 1) & (cpu->tlb_num_ways - 1));
}
/* Writes to TLBACC don't change the read-back value */
@@ -130,24 +129,25 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
{
Nios2CPU *cpu = env_archcpu(env);
+ uint32_t new_pid = FIELD_EX32(v, CR_TLBMISC, PID);
+ uint32_t old_pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID);
+ uint32_t way = FIELD_EX32(v, CR_TLBMISC, WAY);
- trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT,
+ trace_nios2_mmu_write_tlbmisc(way,
(v & CR_TLBMISC_RD) ? 'R' : '.',
(v & CR_TLBMISC_WE) ? 'W' : '.',
(v & CR_TLBMISC_DBL) ? '2' : '.',
(v & CR_TLBMISC_BAD) ? 'B' : '.',
(v & CR_TLBMISC_PERM) ? 'P' : '.',
(v & CR_TLBMISC_D) ? 'D' : '.',
- (v & CR_TLBMISC_PID_MASK) >> 4);
+ new_pid);
- if ((v & CR_TLBMISC_PID_MASK) !=
- (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) {
- mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >>
- CR_TLBMISC_PID_SHIFT);
+ if (new_pid != old_pid) {
+ mmu_flush_pid(env, old_pid);
}
+
/* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */
if (v & CR_TLBMISC_RD) {
- int way = (v >> CR_TLBMISC_WAY_SHIFT);
int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
Nios2TLBEntry *entry =
&env->mmu.tlb[(way * cpu->tlb_num_ways) +
@@ -156,10 +156,9 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
env->ctrl[CR_TLBACC] &= R_CR_TLBACC_IG_MASK;
env->ctrl[CR_TLBACC] |= entry->data;
env->ctrl[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0;
- env->ctrl[CR_TLBMISC] =
- (v & ~CR_TLBMISC_PID_MASK) |
- ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) <<
- CR_TLBMISC_PID_SHIFT);
+ env->ctrl[CR_TLBMISC] = FIELD_DP32(v, CR_TLBMISC, PID,
+ entry->tag &
+ ((1 << cpu->pid_num_bits) - 1));
env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR],
CR_PTEADDR, VPN,
entry->tag >> TARGET_PAGE_BITS);
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index baa22c5101..4191db1342 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -925,7 +925,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n",
env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK,
- (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4,
+ FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID),
env->mmu.tlbacc_wr);
#endif
qemu_fprintf(f, "\n\n");
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 30/64] target/nios2: Move R_FOO and CR_BAR into enumerations
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (28 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 29/64] target/nios2: Use hw/registerfields.h for CR_TLBMISC fields Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 31/64] target/nios2: Create EXCP_SEMIHOST for semi-hosting Richard Henderson
` (33 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
These symbols become available to the debugger.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 72 ++++++++++++++++++++++------------------------
1 file changed, 35 insertions(+), 37 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index ec34cebf72..1998a16940 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -61,25 +61,43 @@ struct Nios2CPUClass {
#define NUM_CR_REGS 32
/* General purpose register aliases */
-#define R_ZERO 0
-#define R_AT 1
-#define R_RET0 2
-#define R_RET1 3
-#define R_ARG0 4
-#define R_ARG1 5
-#define R_ARG2 6
-#define R_ARG3 7
-#define R_ET 24
-#define R_BT 25
-#define R_GP 26
-#define R_SP 27
-#define R_FP 28
-#define R_EA 29
-#define R_BA 30
-#define R_RA 31
+enum {
+ R_ZERO = 0,
+ R_AT = 1,
+ R_RET0 = 2,
+ R_RET1 = 3,
+ R_ARG0 = 4,
+ R_ARG1 = 5,
+ R_ARG2 = 6,
+ R_ARG3 = 7,
+ R_ET = 24,
+ R_BT = 25,
+ R_GP = 26,
+ R_SP = 27,
+ R_FP = 28,
+ R_EA = 29,
+ R_BA = 30,
+ R_RA = 31,
+};
/* Control register aliases */
-#define CR_STATUS 0
+enum {
+ CR_STATUS = 0,
+ CR_ESTATUS = 1,
+ CR_BSTATUS = 2,
+ CR_IENABLE = 3,
+ CR_IPENDING = 4,
+ CR_CPUID = 5,
+ CR_EXCEPTION = 7,
+ CR_PTEADDR = 8,
+ CR_TLBACC = 9,
+ CR_TLBMISC = 10,
+ CR_ENCINJ = 11,
+ CR_BADADDR = 12,
+ CR_CONFIG = 13,
+ CR_MPUBASE = 14,
+ CR_MPUACC = 15,
+};
FIELD(CR_STATUS, PIE, 0, 1)
FIELD(CR_STATUS, U, 1, 1)
@@ -98,24 +116,12 @@ FIELD(CR_STATUS, RSIE, 23, 1)
#define CR_STATUS_NMI R_CR_STATUS_NMI_MASK
#define CR_STATUS_RSIE R_CR_STATUS_RSIE_MASK
-#define CR_ESTATUS 1
-#define CR_BSTATUS 2
-#define CR_IENABLE 3
-#define CR_IPENDING 4
-#define CR_CPUID 5
-#define CR_CTL6 6
-#define CR_EXCEPTION 7
-
FIELD(CR_EXCEPTION, CAUSE, 2, 5)
FIELD(CR_EXCEPTION, ECCFTL, 31, 1)
-#define CR_PTEADDR 8
-
FIELD(CR_PTEADDR, VPN, 2, 20)
FIELD(CR_PTEADDR, PTBASE, 22, 10)
-#define CR_TLBACC 9
-
FIELD(CR_TLBACC, PFN, 0, 20)
FIELD(CR_TLBACC, G, 20, 1)
FIELD(CR_TLBACC, X, 21, 1)
@@ -130,8 +136,6 @@ FIELD(CR_TLBACC, IG, 25, 7)
#define CR_TLBACC_X R_CR_TLBACC_X_MASK
#define CR_TLBACC_G R_CR_TLBACC_G_MASK
-#define CR_TLBMISC 10
-
FIELD(CR_TLBMISC, D, 0, 1)
FIELD(CR_TLBMISC, PERM, 1, 1)
FIELD(CR_TLBMISC, BAD, 2, 1)
@@ -150,12 +154,6 @@ FIELD(CR_TLBMISC, EE, 24, 1)
#define CR_TLBMISC_PERM R_CR_TLBMISC_PERM_MASK
#define CR_TLBMISC_D R_CR_TLBMISC_D_MASK
-#define CR_ENCINJ 11
-#define CR_BADADDR 12
-#define CR_CONFIG 13
-#define CR_MPUBASE 14
-#define CR_MPUACC 15
-
/* Exceptions */
#define EXCP_BREAK 0x1000
#define EXCP_RESET 0
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 31/64] target/nios2: Create EXCP_SEMIHOST for semi-hosting
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (29 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 30/64] target/nios2: Move R_FOO and CR_BAR into enumerations Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 32/64] target/nios2: Clean up nios2_cpu_do_interrupt Richard Henderson
` (32 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Decode 'break 1' during translation, rather than doing
it again during exception processing.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 1 +
target/nios2/helper.c | 14 ++++++--------
target/nios2/translate.c | 17 ++++++++++++++++-
3 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 1998a16940..9e82100a1f 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -156,6 +156,7 @@ FIELD(CR_TLBMISC, EE, 24, 1)
/* Exceptions */
#define EXCP_BREAK 0x1000
+#define EXCP_SEMIHOST 0x1001
#define EXCP_RESET 0
#define EXCP_PRESET 1
#define EXCP_IRQ 2
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index a56aaaea18..1d17c0379f 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -152,14 +152,6 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_BREAK:
qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc);
- /* The semihosting instruction is "break 1". */
- if (semihosting_enabled() &&
- cpu_ldl_code(env, env->pc) == 0x003da07a) {
- qemu_log_mask(CPU_LOG_INT, "Entering semihosting\n");
- env->pc += 4;
- do_nios2_semihosting(env);
- break;
- }
if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
env->ctrl[CR_BSTATUS] = env->ctrl[CR_STATUS];
@@ -176,6 +168,12 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->pc = cpu->exception_addr;
break;
+ case EXCP_SEMIHOST:
+ qemu_log_mask(CPU_LOG_INT, "BREAK semihosting at pc=%x\n", env->pc);
+ env->pc += 4;
+ do_nios2_semihosting(env);
+ break;
+
default:
cpu_abort(cs, "unhandled exception type=%d\n",
cs->exception_index);
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 4191db1342..97e531529f 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -33,6 +33,7 @@
#include "exec/translator.h"
#include "qemu/qemu-print.h"
#include "exec/gen-icount.h"
+#include "semihosting/semihost.h"
/* is_jmp field values */
#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
@@ -686,6 +687,20 @@ static void trap(DisasContext *dc, uint32_t code, uint32_t flags)
t_gen_helper_raise_exception(dc, EXCP_TRAP);
}
+static void gen_break(DisasContext *dc, uint32_t code, uint32_t flags)
+{
+#ifndef CONFIG_USER_ONLY
+ /* The semihosting instruction is "break 1". */
+ R_TYPE(instr, code);
+ if (semihosting_enabled() && instr.imm5 == 1) {
+ t_gen_helper_raise_exception(dc, EXCP_SEMIHOST);
+ return;
+ }
+#endif
+
+ t_gen_helper_raise_exception(dc, EXCP_BREAK);
+}
+
static const Nios2Instruction r_type_instructions[] = {
INSTRUCTION_ILLEGAL(),
INSTRUCTION(eret), /* eret */
@@ -739,7 +754,7 @@ static const Nios2Instruction r_type_instructions[] = {
INSTRUCTION(add), /* add */
INSTRUCTION_ILLEGAL(),
INSTRUCTION_ILLEGAL(),
- INSTRUCTION_FLG(gen_excp, EXCP_BREAK), /* break */
+ INSTRUCTION(gen_break), /* break */
INSTRUCTION_ILLEGAL(),
INSTRUCTION(nop), /* nop */
INSTRUCTION_ILLEGAL(),
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 32/64] target/nios2: Clean up nios2_cpu_do_interrupt
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (30 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 31/64] target/nios2: Create EXCP_SEMIHOST for semi-hosting Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 33/64] target/nios2: Hoist CPU_LOG_INT logging Richard Henderson
` (31 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Split out do_exception and do_iic_irq to handle bulk of the interrupt and
exception processing. Parameterize the changes required to cpu state.
The status.EH bit, which protects some data against double-faults,
is only present with the MMU. Several exception cases did not check
for status.EH being set, as required.
The status.IH bit, which had been set by EXCP_IRQ, is exclusive to
the external interrupt controller, which we do not yet implement.
The internal interrupt controller, when the MMU is also present,
sets the status.EH bit.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/helper.c | 141 +++++++++++++-----------------------------
1 file changed, 44 insertions(+), 97 deletions(-)
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 1d17c0379f..63971a8b3c 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -29,6 +29,42 @@
#include "semihosting/semihost.h"
+static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break)
+{
+ CPUNios2State *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
+ uint32_t old_status = env->ctrl[CR_STATUS];
+ uint32_t new_status = old_status;
+
+ if ((old_status & CR_STATUS_EH) == 0) {
+ int r_ea = R_EA, cr_es = CR_ESTATUS;
+
+ if (is_break) {
+ r_ea = R_BA;
+ cr_es = CR_BSTATUS;
+ }
+ env->ctrl[cr_es] = old_status;
+ env->regs[r_ea] = env->pc + 4;
+
+ if (cpu->mmu_present) {
+ new_status |= CR_STATUS_EH;
+ }
+ }
+
+ new_status &= ~(CR_STATUS_PIE | CR_STATUS_U);
+
+ env->ctrl[CR_STATUS] = new_status;
+ env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
+ CR_EXCEPTION, CAUSE,
+ cs->exception_index);
+ env->pc = exception_addr;
+}
+
+static void do_iic_irq(Nios2CPU *cpu)
+{
+ do_exception(cpu, cpu->exception_addr, false);
+}
+
void nios2_cpu_do_interrupt(CPUState *cs)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
@@ -36,57 +72,20 @@ void nios2_cpu_do_interrupt(CPUState *cs)
switch (cs->exception_index) {
case EXCP_IRQ:
- assert(env->ctrl[CR_STATUS] & CR_STATUS_PIE);
-
qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc);
-
- env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS];
- env->ctrl[CR_STATUS] |= CR_STATUS_IH;
- env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
-
- env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
- CR_EXCEPTION, CAUSE,
- cs->exception_index);
-
- env->regs[R_EA] = env->pc + 4;
- env->pc = cpu->exception_addr;
+ do_iic_irq(cpu);
break;
case EXCP_TLBD:
if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc);
-
- /* Fast TLB miss */
- /* Variation from the spec. Table 3-35 of the cpu reference shows
- * estatus not being changed for TLB miss but this appears to
- * be incorrect. */
- env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS];
- env->ctrl[CR_STATUS] |= CR_STATUS_EH;
- env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
-
- env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
- CR_EXCEPTION, CAUSE,
- cs->exception_index);
-
env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL;
env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE;
-
- env->regs[R_EA] = env->pc + 4;
- env->pc = cpu->fast_tlb_miss_addr;
+ do_exception(cpu, cpu->fast_tlb_miss_addr, false);
} else {
qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc);
-
- /* Double TLB miss */
- env->ctrl[CR_STATUS] |= CR_STATUS_EH;
- env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
-
- env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
- CR_EXCEPTION, CAUSE,
- cs->exception_index);
-
env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL;
-
- env->pc = cpu->exception_addr;
+ do_exception(cpu, cpu->exception_addr, false);
}
break;
@@ -94,78 +93,28 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_TLBW:
case EXCP_TLBX:
qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc);
-
- env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS];
- env->ctrl[CR_STATUS] |= CR_STATUS_EH;
- env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
-
- env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
- CR_EXCEPTION, CAUSE,
- cs->exception_index);
-
if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE;
}
-
- env->regs[R_EA] = env->pc + 4;
- env->pc = cpu->exception_addr;
+ do_exception(cpu, cpu->exception_addr, false);
break;
case EXCP_SUPERA:
case EXCP_SUPERI:
case EXCP_SUPERD:
qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc);
-
- if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
- env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS];
- env->regs[R_EA] = env->pc + 4;
- }
-
- env->ctrl[CR_STATUS] |= CR_STATUS_EH;
- env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
-
- env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
- CR_EXCEPTION, CAUSE,
- cs->exception_index);
-
- env->pc = cpu->exception_addr;
+ do_exception(cpu, cpu->exception_addr, false);
break;
case EXCP_ILLEGAL:
case EXCP_TRAP:
qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc);
-
- if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
- env->ctrl[CR_ESTATUS] = env->ctrl[CR_STATUS];
- env->regs[R_EA] = env->pc + 4;
- }
-
- env->ctrl[CR_STATUS] |= CR_STATUS_EH;
- env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
-
- env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
- CR_EXCEPTION, CAUSE,
- cs->exception_index);
-
- env->pc = cpu->exception_addr;
+ do_exception(cpu, cpu->exception_addr, false);
break;
case EXCP_BREAK:
qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc);
-
- if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
- env->ctrl[CR_BSTATUS] = env->ctrl[CR_STATUS];
- env->regs[R_BA] = env->pc + 4;
- }
-
- env->ctrl[CR_STATUS] |= CR_STATUS_EH;
- env->ctrl[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
-
- env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
- CR_EXCEPTION, CAUSE,
- cs->exception_index);
-
- env->pc = cpu->exception_addr;
+ do_exception(cpu, cpu->exception_addr, true);
break;
case EXCP_SEMIHOST:
@@ -175,9 +124,7 @@ void nios2_cpu_do_interrupt(CPUState *cs)
break;
default:
- cpu_abort(cs, "unhandled exception type=%d\n",
- cs->exception_index);
- break;
+ cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 33/64] target/nios2: Hoist CPU_LOG_INT logging
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (31 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 32/64] target/nios2: Clean up nios2_cpu_do_interrupt Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 34/64] target/nios2: Handle EXCP_UNALIGN and EXCP_UALIGND Richard Henderson
` (30 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Performing this early means that we can merge more cases
within the non-logging switch statement.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/helper.c | 58 +++++++++++++++++++++++++++++++++++--------
1 file changed, 47 insertions(+), 11 deletions(-)
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 63971a8b3c..c57ffd64e0 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -70,20 +70,64 @@ void nios2_cpu_do_interrupt(CPUState *cs)
Nios2CPU *cpu = NIOS2_CPU(cs);
CPUNios2State *env = &cpu->env;
+ if (qemu_loglevel_mask(CPU_LOG_INT)) {
+ const char *name = NULL;
+
+ switch (cs->exception_index) {
+ case EXCP_IRQ:
+ name = "interrupt";
+ break;
+ case EXCP_TLBD:
+ if (env->ctrl[CR_STATUS] & CR_STATUS_EH) {
+ name = "TLB MISS (double)";
+ } else {
+ name = "TLB MISS (fast)";
+ }
+ break;
+ case EXCP_TLBR:
+ case EXCP_TLBW:
+ case EXCP_TLBX:
+ name = "TLB PERM";
+ break;
+ case EXCP_SUPERA:
+ case EXCP_SUPERD:
+ name = "SUPERVISOR (address)";
+ break;
+ case EXCP_SUPERI:
+ name = "SUPERVISOR (insn)";
+ break;
+ case EXCP_ILLEGAL:
+ name = "ILLEGAL insn";
+ break;
+ case EXCP_TRAP:
+ name = "TRAP insn";
+ break;
+ case EXCP_BREAK:
+ name = "BREAK insn";
+ break;
+ case EXCP_SEMIHOST:
+ name = "SEMIHOST insn";
+ break;
+ }
+ if (name) {
+ qemu_log("%s at pc=0x%08x\n", name, env->pc);
+ } else {
+ qemu_log("Unknown exception %d at pc=0x%08x\n",
+ cs->exception_index, env->pc);
+ }
+ }
+
switch (cs->exception_index) {
case EXCP_IRQ:
- qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->pc);
do_iic_irq(cpu);
break;
case EXCP_TLBD:
if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
- qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n", env->pc);
env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL;
env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE;
do_exception(cpu, cpu->fast_tlb_miss_addr, false);
} else {
- qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n", env->pc);
env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL;
do_exception(cpu, cpu->exception_addr, false);
}
@@ -92,7 +136,6 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_TLBR:
case EXCP_TLBW:
case EXCP_TLBX:
- qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->pc);
if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE;
}
@@ -102,23 +145,16 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_SUPERA:
case EXCP_SUPERI:
case EXCP_SUPERD:
- qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n", env->pc);
- do_exception(cpu, cpu->exception_addr, false);
- break;
-
case EXCP_ILLEGAL:
case EXCP_TRAP:
- qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n", env->pc);
do_exception(cpu, cpu->exception_addr, false);
break;
case EXCP_BREAK:
- qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=%x\n", env->pc);
do_exception(cpu, cpu->exception_addr, true);
break;
case EXCP_SEMIHOST:
- qemu_log_mask(CPU_LOG_INT, "BREAK semihosting at pc=%x\n", env->pc);
env->pc += 4;
do_nios2_semihosting(env);
break;
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 34/64] target/nios2: Handle EXCP_UNALIGN and EXCP_UALIGND
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (32 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 33/64] target/nios2: Hoist CPU_LOG_INT logging Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-22 12:56 ` Peter Maydell
2022-04-21 15:17 ` [PATCH v7 35/64] target/nios2: Cleanup set of CR_EXCEPTION for do_interrupt Richard Henderson
` (29 subsequent siblings)
63 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel
While some of the plumbing for misaligned data is present, in the form
of nios2_cpu_do_unaligned_access, the hook will not be called because
TARGET_ALIGNED_ONLY is not set in configs/targets/nios2-softmmu.mak.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/helper.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index c57ffd64e0..25a89724d0 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -99,6 +99,12 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_ILLEGAL:
name = "ILLEGAL insn";
break;
+ case EXCP_UNALIGN:
+ name = "Misaligned (data)";
+ break;
+ case EXCP_UNALIGND:
+ name = "Misaligned (destination)";
+ break;
case EXCP_TRAP:
name = "TRAP insn";
break;
@@ -147,6 +153,8 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_SUPERD:
case EXCP_ILLEGAL:
case EXCP_TRAP:
+ case EXCP_UNALIGN:
+ case EXCP_UNALIGND:
do_exception(cpu, cpu->exception_addr, false);
break;
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* Re: [PATCH v7 34/64] target/nios2: Handle EXCP_UNALIGN and EXCP_UALIGND
2022-04-21 15:17 ` [PATCH v7 34/64] target/nios2: Handle EXCP_UNALIGN and EXCP_UALIGND Richard Henderson
@ 2022-04-22 12:56 ` Peter Maydell
0 siblings, 0 replies; 78+ messages in thread
From: Peter Maydell @ 2022-04-22 12:56 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Thu, 21 Apr 2022 at 17:09, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> While some of the plumbing for misaligned data is present, in the form
> of nios2_cpu_do_unaligned_access, the hook will not be called because
> TARGET_ALIGNED_ONLY is not set in configs/targets/nios2-softmmu.mak.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/nios2/helper.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
Typo in subject (missing N in "EXCP_UNALIGND"), otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH v7 35/64] target/nios2: Cleanup set of CR_EXCEPTION for do_interrupt
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (33 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 34/64] target/nios2: Handle EXCP_UNALIGN and EXCP_UALIGND Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 36/64] target/nios2: Clean up handling of tlbmisc in do_exception Richard Henderson
` (28 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
The register is entirely read-only for software, and we do not
implement ECC, so we need not deposit the cause into an existing
value; just create a new value from scratch.
Furthermore, exception.CAUSE is not written for break exceptions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/helper.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 25a89724d0..3d9869453b 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -54,9 +54,10 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break)
new_status &= ~(CR_STATUS_PIE | CR_STATUS_U);
env->ctrl[CR_STATUS] = new_status;
- env->ctrl[CR_EXCEPTION] = FIELD_DP32(env->ctrl[CR_EXCEPTION],
- CR_EXCEPTION, CAUSE,
- cs->exception_index);
+ if (!is_break) {
+ env->ctrl[CR_EXCEPTION] = FIELD_DP32(0, CR_EXCEPTION, CAUSE,
+ cs->exception_index);
+ }
env->pc = exception_addr;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 36/64] target/nios2: Clean up handling of tlbmisc in do_exception
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (34 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 35/64] target/nios2: Cleanup set of CR_EXCEPTION for do_interrupt Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 37/64] target/nios2: Prevent writes to read-only or reserved control fields Richard Henderson
` (27 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
The 4 lower bits, D, PERM, BAD, DBL, are unconditionally set on any
exception with EH=0, or so says Table 42 (Processor Status After
Taking Exception).
We currently do not set PERM or BAD at all, and only set/clear
DBL for tlb miss, and do not clear DBL for any other exception.
It is a bit confusing to set D in tlb_fill and the rest during
do_interrupt, so move the setting of D to do_interrupt as well.
To do this, split EXP_TLBD into two cases, EXCP_TLB_X and EXCP_TLB_D,
which allows us to distinguish them during do_interrupt. Choose
a value for EXCP_TLB_D such that when truncated it produces the
correct value for exception.CAUSE.
Rename EXCP_TLB[RWX] to EXCP_PERM_[RWX], to emphasize that the
exception is permissions related. Rename EXCP_SUPER[AD] to
EXCP_SUPERA_[DX] to emphasize that they are both "supervisor
address" exceptions, data and execute.
Retain the setting of tlbmisc.WE for the fast-tlb-miss path, as it
is being relied upon, but remove it from the permission path.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 13 +++---
target/nios2/helper.c | 97 +++++++++++++++++++++++++++++--------------
2 files changed, 73 insertions(+), 37 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 9e82100a1f..7189f9a45f 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -166,13 +166,14 @@ FIELD(CR_TLBMISC, EE, 24, 1)
#define EXCP_UNALIGN 6
#define EXCP_UNALIGND 7
#define EXCP_DIV 8
-#define EXCP_SUPERA 9
+#define EXCP_SUPERA_X 9
#define EXCP_SUPERI 10
-#define EXCP_SUPERD 11
-#define EXCP_TLBD 12
-#define EXCP_TLBX 13
-#define EXCP_TLBR 14
-#define EXCP_TLBW 15
+#define EXCP_SUPERA_D 11
+#define EXCP_TLB_X 12
+#define EXCP_TLB_D (0x1000 | EXCP_TLB_X)
+#define EXCP_PERM_X 13
+#define EXCP_PERM_R 14
+#define EXCP_PERM_W 15
#define EXCP_MPUI 16
#define EXCP_MPUD 17
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 3d9869453b..4d9085f22f 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -29,7 +29,8 @@
#include "semihosting/semihost.h"
-static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break)
+static void do_exception(Nios2CPU *cpu, uint32_t exception_addr,
+ uint32_t tlbmisc_set, bool is_break)
{
CPUNios2State *env = &cpu->env;
CPUState *cs = CPU(cpu);
@@ -48,6 +49,16 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break)
if (cpu->mmu_present) {
new_status |= CR_STATUS_EH;
+
+ /*
+ * There are 4 bits that are always written.
+ * Explicitly clear them, to be set via the argument.
+ */
+ env->ctrl[CR_TLBMISC] &= ~(CR_TLBMISC_D |
+ CR_TLBMISC_PERM |
+ CR_TLBMISC_BAD |
+ CR_TLBMISC_DBL);
+ env->ctrl[CR_TLBMISC] |= tlbmisc_set;
}
}
@@ -63,13 +74,14 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_break)
static void do_iic_irq(Nios2CPU *cpu)
{
- do_exception(cpu, cpu->exception_addr, false);
+ do_exception(cpu, cpu->exception_addr, 0, false);
}
void nios2_cpu_do_interrupt(CPUState *cs)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
CPUNios2State *env = &cpu->env;
+ uint32_t tlbmisc_set = 0;
if (qemu_loglevel_mask(CPU_LOG_INT)) {
const char *name = NULL;
@@ -78,20 +90,21 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_IRQ:
name = "interrupt";
break;
- case EXCP_TLBD:
+ case EXCP_TLB_X:
+ case EXCP_TLB_D:
if (env->ctrl[CR_STATUS] & CR_STATUS_EH) {
name = "TLB MISS (double)";
} else {
name = "TLB MISS (fast)";
}
break;
- case EXCP_TLBR:
- case EXCP_TLBW:
- case EXCP_TLBX:
+ case EXCP_PERM_R:
+ case EXCP_PERM_W:
+ case EXCP_PERM_X:
name = "TLB PERM";
break;
- case EXCP_SUPERA:
- case EXCP_SUPERD:
+ case EXCP_SUPERA_X:
+ case EXCP_SUPERA_D:
name = "SUPERVISOR (address)";
break;
case EXCP_SUPERI:
@@ -129,38 +142,57 @@ void nios2_cpu_do_interrupt(CPUState *cs)
do_iic_irq(cpu);
break;
- case EXCP_TLBD:
- if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
- env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL;
- env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE;
- do_exception(cpu, cpu->fast_tlb_miss_addr, false);
+ case EXCP_TLB_D:
+ tlbmisc_set = CR_TLBMISC_D;
+ /* fall through */
+ case EXCP_TLB_X:
+ if (env->ctrl[CR_STATUS] & CR_STATUS_EH) {
+ tlbmisc_set |= CR_TLBMISC_DBL;
+ /*
+ * Normally, we don't write to tlbmisc unless !EH,
+ * so do it manually for the double-tlb miss exception.
+ */
+ env->ctrl[CR_TLBMISC] &= ~(CR_TLBMISC_D |
+ CR_TLBMISC_PERM |
+ CR_TLBMISC_BAD);
+ env->ctrl[CR_TLBMISC] |= tlbmisc_set;
+ do_exception(cpu, cpu->exception_addr, 0, false);
} else {
- env->ctrl[CR_TLBMISC] |= CR_TLBMISC_DBL;
- do_exception(cpu, cpu->exception_addr, false);
+ tlbmisc_set |= CR_TLBMISC_WE;
+ do_exception(cpu, cpu->fast_tlb_miss_addr, tlbmisc_set, false);
}
break;
- case EXCP_TLBR:
- case EXCP_TLBW:
- case EXCP_TLBX:
- if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
- env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE;
+ case EXCP_PERM_R:
+ case EXCP_PERM_W:
+ tlbmisc_set = CR_TLBMISC_D;
+ /* fall through */
+ case EXCP_PERM_X:
+ tlbmisc_set |= CR_TLBMISC_PERM;
+ if (!(env->ctrl[CR_STATUS] & CR_STATUS_EH)) {
+ tlbmisc_set |= CR_TLBMISC_WE;
}
- do_exception(cpu, cpu->exception_addr, false);
+ do_exception(cpu, cpu->exception_addr, tlbmisc_set, false);
+ break;
+
+ case EXCP_SUPERA_D:
+ case EXCP_UNALIGN:
+ tlbmisc_set = CR_TLBMISC_D;
+ /* fall through */
+ case EXCP_SUPERA_X:
+ case EXCP_UNALIGND:
+ tlbmisc_set |= CR_TLBMISC_BAD;
+ do_exception(cpu, cpu->exception_addr, tlbmisc_set, false);
break;
- case EXCP_SUPERA:
case EXCP_SUPERI:
- case EXCP_SUPERD:
case EXCP_ILLEGAL:
case EXCP_TRAP:
- case EXCP_UNALIGN:
- case EXCP_UNALIGND:
- do_exception(cpu, cpu->exception_addr, false);
+ do_exception(cpu, cpu->exception_addr, 0, false);
break;
case EXCP_BREAK:
- do_exception(cpu, cpu->exception_addr, true);
+ do_exception(cpu, cpu->exception_addr, 0, true);
break;
case EXCP_SEMIHOST:
@@ -215,7 +247,7 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
{
Nios2CPU *cpu = NIOS2_CPU(cs);
CPUNios2State *env = &cpu->env;
- unsigned int excp = EXCP_TLBD;
+ unsigned int excp;
target_ulong vaddr, paddr;
Nios2MMULookup lu;
unsigned int hit;
@@ -242,7 +274,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
if (probe) {
return false;
}
- cs->exception_index = EXCP_SUPERA;
+ cs->exception_index = (access_type == MMU_INST_FETCH
+ ? EXCP_SUPERA_X : EXCP_SUPERA_D);
env->ctrl[CR_BADADDR] = address;
cpu_loop_exit_restore(cs, retaddr);
}
@@ -263,8 +296,10 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
}
/* Permission violation */
- excp = (access_type == MMU_DATA_LOAD ? EXCP_TLBR :
- access_type == MMU_DATA_STORE ? EXCP_TLBW : EXCP_TLBX);
+ excp = (access_type == MMU_DATA_LOAD ? EXCP_PERM_R :
+ access_type == MMU_DATA_STORE ? EXCP_PERM_W : EXCP_PERM_X);
+ } else {
+ excp = (access_type == MMU_INST_FETCH ? EXCP_TLB_X: EXCP_TLB_D);
}
if (probe) {
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 37/64] target/nios2: Prevent writes to read-only or reserved control fields
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (35 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 36/64] target/nios2: Clean up handling of tlbmisc in do_exception Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-22 12:56 ` Peter Maydell
2022-04-21 15:17 ` [PATCH v7 38/64] target/nios2: Implement cpuid Richard Henderson
` (26 subsequent siblings)
63 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel
Create an array of masks which detail the writable and readonly
bits for each control register. Apply them when writing to
control registers, including the write to status during eret.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 13 +++++
target/nios2/cpu.c | 100 +++++++++++++++++++++++++++++++++------
target/nios2/op_helper.c | 9 ++++
target/nios2/translate.c | 80 ++++++++++++++++++++++++-------
4 files changed, 171 insertions(+), 31 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 7189f9a45f..5f6b9242a2 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -190,6 +190,11 @@ struct CPUArchState {
int error_code;
};
+typedef struct {
+ uint32_t writable;
+ uint32_t readonly;
+} ControlRegState;
+
/**
* Nios2CPU:
* @env: #CPUNios2State
@@ -213,9 +218,17 @@ struct ArchCPU {
uint32_t reset_addr;
uint32_t exception_addr;
uint32_t fast_tlb_miss_addr;
+
+ /* Bits within each control register which are reserved or readonly. */
+ ControlRegState cr_state[NUM_CR_REGS];
};
+static inline bool nios2_cr_reserved(const ControlRegState *s)
+{
+ return (s->writable | s->readonly) == 0;
+}
+
void nios2_tcg_init(void);
void nios2_cpu_do_interrupt(CPUState *cs);
void dump_mmu(CPUNios2State *env);
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index fce16a2e77..b3c5ae681c 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -102,6 +102,64 @@ static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_NIOS2_CPU);
}
+static void realize_cr_status(CPUState *cs)
+{
+ Nios2CPU *cpu = NIOS2_CPU(cs);
+
+ /* Begin with all fields of all registers are reserved. */
+ memset(cpu->cr_state, 0, sizeof(cpu->cr_state));
+
+ /*
+ * The combination of writable and readonly is the set of all
+ * non-reserved fields. We apply writable as a mask to bits,
+ * and merge in existing readonly bits, before storing.
+ */
+#define WR_REG(C) cpu->cr_state[C].writable = -1
+#define RO_REG(C) cpu->cr_state[C].readonly = -1
+#define WR_FIELD(C, F) cpu->cr_state[C].writable |= R_##C##_##F##_MASK
+#define RO_FIELD(C, F) cpu->cr_state[C].readonly |= R_##C##_##F##_MASK
+
+ WR_FIELD(CR_STATUS, PIE);
+ WR_REG(CR_ESTATUS);
+ WR_REG(CR_BSTATUS);
+ RO_REG(CR_CPUID);
+ RO_REG(CR_EXCEPTION);
+ WR_REG(CR_BADADDR);
+
+ /* TODO: These control registers are not present with the EIC. */
+ WR_REG(CR_IENABLE);
+ RO_REG(CR_IPENDING);
+
+ if (cpu->mmu_present) {
+ WR_FIELD(CR_STATUS, U);
+ WR_FIELD(CR_STATUS, EH);
+
+ WR_FIELD(CR_PTEADDR, VPN);
+ WR_FIELD(CR_PTEADDR, PTBASE);
+
+ RO_FIELD(CR_TLBMISC, D);
+ RO_FIELD(CR_TLBMISC, PERM);
+ RO_FIELD(CR_TLBMISC, BAD);
+ RO_FIELD(CR_TLBMISC, DBL);
+ WR_FIELD(CR_TLBMISC, PID);
+ WR_FIELD(CR_TLBMISC, WE);
+ WR_FIELD(CR_TLBMISC, RD);
+ WR_FIELD(CR_TLBMISC, WAY);
+
+ WR_REG(CR_TLBACC);
+ }
+
+ /*
+ * TODO: ECC (config, eccinj) and MPU (config, mpubase, mpuacc) are
+ * unimplemented, so their corresponding control regs remain reserved.
+ */
+
+#undef WR_REG
+#undef RO_REG
+#undef WR_FIELD
+#undef RO_FIELD
+}
+
static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
@@ -114,6 +172,7 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
+ realize_cr_status(cs);
qemu_init_vcpu(cs);
cpu_reset(cs);
@@ -147,23 +206,26 @@ static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
- CPUClass *cc = CPU_GET_CLASS(cs);
CPUNios2State *env = &cpu->env;
+ uint32_t val;
- if (n > cc->gdb_num_core_regs) {
+ if (n < 32) { /* GP regs */
+ val = env->regs[n];
+ } else if (n == 32) { /* PC */
+ val = env->pc;
+ } else if (n < 49) { /* Status regs */
+ unsigned cr = n - 33;
+ if (nios2_cr_reserved(&cpu->cr_state[cr])) {
+ val = 0;
+ } else {
+ val = env->ctrl[n - 33];
+ }
+ } else {
+ /* Invalid regs */
return 0;
}
- if (n < 32) { /* GP regs */
- return gdb_get_reg32(mem_buf, env->regs[n]);
- } else if (n == 32) { /* PC */
- return gdb_get_reg32(mem_buf, env->pc);
- } else if (n < 49) { /* Status regs */
- return gdb_get_reg32(mem_buf, env->ctrl[n - 33]);
- }
-
- /* Invalid regs */
- return 0;
+ return gdb_get_reg32(mem_buf, val);
}
static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
@@ -171,17 +233,25 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
Nios2CPU *cpu = NIOS2_CPU(cs);
CPUClass *cc = CPU_GET_CLASS(cs);
CPUNios2State *env = &cpu->env;
+ uint32_t val;
if (n > cc->gdb_num_core_regs) {
return 0;
}
+ val = ldl_p(mem_buf);
if (n < 32) { /* GP regs */
- env->regs[n] = ldl_p(mem_buf);
+ env->regs[n] = val;
} else if (n == 32) { /* PC */
- env->pc = ldl_p(mem_buf);
+ env->pc = val;
} else if (n < 49) { /* Status regs */
- env->ctrl[n - 33] = ldl_p(mem_buf);
+ unsigned cr = n - 33;
+ /* ??? Maybe allow the debugger to write to readonly fields. */
+ val &= cpu->cr_state[cr].writable;
+ val |= cpu->cr_state[cr].readonly & env->ctrl[cr];
+ env->ctrl[cr] = val;
+ } else {
+ g_assert_not_reached();
}
return 4;
diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
index 08ed3b4598..49fccf2c2c 100644
--- a/target/nios2/op_helper.c
+++ b/target/nios2/op_helper.c
@@ -34,6 +34,15 @@ void helper_raise_exception(CPUNios2State *env, uint32_t index)
#ifndef CONFIG_USER_ONLY
void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc)
{
+ Nios2CPU *cpu = env_archcpu(env);
+
+ /*
+ * Both estatus and bstatus have no constraints on write;
+ * do not allow reserved fields in status to be set.
+ * TODO: more than this is required for shadow registers.
+ */
+ new_status &= cpu->cr_state[CR_STATUS].writable;
+
env->ctrl[CR_STATUS] = new_status;
env->pc = new_pc;
cpu_loop_exit(env_cpu(env));
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 97e531529f..b8d75207a4 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -102,6 +102,7 @@ typedef struct DisasContext {
TCGv_i32 zero;
target_ulong pc;
int mem_idx;
+ const ControlRegState *cr_state;
} DisasContext;
static TCGv cpu_R[NUM_GP_REGS];
@@ -471,17 +472,26 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags)
/* rC <- ctlN */
static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
{
- R_TYPE(instr, code);
- TCGv t1, t2;
-
if (!gen_check_supervisor(dc)) {
return;
}
+#ifdef CONFIG_USER_ONLY
+ g_assert_not_reached();
+#else
+ R_TYPE(instr, code);
+ TCGv t1, t2;
+
if (unlikely(instr.c == R_ZERO)) {
return;
}
+ /* Reserved registers read as zero. */
+ if (nios2_cr_reserved(&dc->cr_state[instr.imm5])) {
+ tcg_gen_movi_tl(cpu_R[instr.c], 0);
+ return;
+ }
+
switch (instr.imm5) {
case CR_IPENDING:
/*
@@ -505,6 +515,7 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
offsetof(CPUNios2State, ctrl[instr.imm5]));
break;
}
+#endif
}
/* ctlN <- rA */
@@ -519,6 +530,14 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
#else
R_TYPE(instr, code);
TCGv v = load_gpr(dc, instr.a);
+ uint32_t ofs = offsetof(CPUNios2State, ctrl[instr.imm5]);
+ uint32_t wr = dc->cr_state[instr.imm5].writable;
+ uint32_t ro = dc->cr_state[instr.imm5].readonly;
+
+ /* Skip reserved or readonly registers. */
+ if (wr == 0) {
+ return;
+ }
switch (instr.imm5) {
case CR_PTEADDR:
@@ -530,17 +549,35 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
case CR_TLBMISC:
gen_helper_mmu_write_tlbmisc(cpu_env, v);
break;
- case CR_IPENDING:
- /* ipending is read only, writes ignored. */
- break;
case CR_STATUS:
case CR_IENABLE:
/* If interrupts were enabled using WRCTL, trigger them. */
dc->base.is_jmp = DISAS_UPDATE;
/* fall through */
default:
- tcg_gen_st_tl(v, cpu_env,
- offsetof(CPUNios2State, ctrl[instr.imm5]));
+ if (wr == -1) {
+ /* The register is entirely writable. */
+ tcg_gen_st_tl(v, cpu_env, ofs);
+ } else {
+ /*
+ * The register is partially read-only or reserved:
+ * merge the value.
+ */
+ TCGv n = tcg_temp_new();
+
+ tcg_gen_andi_tl(n, v, wr);
+
+ if (ro != 0) {
+ TCGv o = tcg_temp_new();
+ tcg_gen_ld_tl(o, cpu_env, ofs);
+ tcg_gen_andi_tl(o, o, ro);
+ tcg_gen_or_tl(n, n, o);
+ tcg_temp_free(o);
+ }
+
+ tcg_gen_st_tl(n, cpu_env, ofs);
+ tcg_temp_free(n);
+ }
break;
}
#endif
@@ -818,9 +855,11 @@ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUNios2State *env = cs->env_ptr;
+ Nios2CPU *cpu = env_archcpu(env);
int page_insns;
dc->mem_idx = cpu_mmu_index(env, false);
+ dc->cr_state = cpu->cr_state;
/* Bound the number of insns to execute to those left on the page. */
page_insns = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
@@ -932,16 +971,25 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
#if !defined(CONFIG_USER_ONLY)
- for (i = 0; i < NUM_CR_REGS; i++) {
- qemu_fprintf(f, "%9s=%8.8x ", cr_regnames[i], env->ctrl[i]);
- if ((i + 1) % 4 == 0) {
- qemu_fprintf(f, "\n");
+ int j;
+
+ for (i = j = 0; i < NUM_CR_REGS; i++) {
+ if (!nios2_cr_reserved(&cpu->cr_state[i])) {
+ qemu_fprintf(f, "%9s=%8.8x ", cr_regnames[i], env->ctrl[i]);
+ if (++j % 4 == 0) {
+ qemu_fprintf(f, "\n");
+ }
}
}
- qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n",
- env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK,
- FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID),
- env->mmu.tlbacc_wr);
+ if (j % 4 != 0) {
+ qemu_fprintf(f, "\n");
+ }
+ if (cpu->mmu_present) {
+ qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n",
+ env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK,
+ FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID),
+ env->mmu.tlbacc_wr);
+ }
#endif
qemu_fprintf(f, "\n\n");
}
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 38/64] target/nios2: Implement cpuid
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (36 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 37/64] target/nios2: Prevent writes to read-only or reserved control fields Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 39/64] target/nios2: Implement CR_STATUS.RSIE Richard Henderson
` (25 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Copy the existing cpu_index into the space reserved for CR_CPUID.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index b3c5ae681c..a0c3e97d72 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -163,6 +163,7 @@ static void realize_cr_status(CPUState *cs)
static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
+ Nios2CPU *cpu = NIOS2_CPU(cs);
Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev);
Error *local_err = NULL;
@@ -176,6 +177,9 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
qemu_init_vcpu(cs);
cpu_reset(cs);
+ /* We have reserved storage for cpuid; might as well use it. */
+ cpu->env.ctrl[CR_CPUID] = cs->cpu_index;
+
ncc->parent_realize(dev, errp);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 39/64] target/nios2: Implement CR_STATUS.RSIE
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (37 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 38/64] target/nios2: Implement cpuid Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 40/64] target/nios2: Remove CPU_INTERRUPT_NMI Richard Henderson
` (24 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Without EIC, this bit is RES1. So set the bit at reset,
and add it to the readonly fields of CR_STATUS.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index a0c3e97d72..7d734280d1 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -54,9 +54,9 @@ static void nios2_cpu_reset(DeviceState *dev)
#if defined(CONFIG_USER_ONLY)
/* Start in user mode with interrupts enabled. */
- env->ctrl[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE;
+ env->ctrl[CR_STATUS] = CR_STATUS_RSIE | CR_STATUS_U | CR_STATUS_PIE;
#else
- env->ctrl[CR_STATUS] = 0;
+ env->ctrl[CR_STATUS] = CR_STATUS_RSIE;
#endif
}
@@ -127,6 +127,7 @@ static void realize_cr_status(CPUState *cs)
WR_REG(CR_BADADDR);
/* TODO: These control registers are not present with the EIC. */
+ RO_FIELD(CR_STATUS, RSIE);
WR_REG(CR_IENABLE);
RO_REG(CR_IPENDING);
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 40/64] target/nios2: Remove CPU_INTERRUPT_NMI
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (38 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 39/64] target/nios2: Implement CR_STATUS.RSIE Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 41/64] target/nios2: Support division error exception Richard Henderson
` (23 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
This interrupt bit is never set, so testing it in
nios2_cpu_has_work is pointless.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 2 --
target/nios2/cpu.c | 2 +-
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 5f6b9242a2..5403eeae54 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -177,8 +177,6 @@ FIELD(CR_TLBMISC, EE, 24, 1)
#define EXCP_MPUI 16
#define EXCP_MPUD 17
-#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
-
struct CPUArchState {
uint32_t regs[NUM_GP_REGS];
uint32_t ctrl[NUM_CR_REGS];
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 7d734280d1..58e6ad0462 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -36,7 +36,7 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
static bool nios2_cpu_has_work(CPUState *cs)
{
- return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
+ return cs->interrupt_request & CPU_INTERRUPT_HARD;
}
static void nios2_cpu_reset(DeviceState *dev)
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 41/64] target/nios2: Support division error exception
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (39 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 40/64] target/nios2: Remove CPU_INTERRUPT_NMI Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 42/64] target/nios2: Use tcg_constant_tl Richard Henderson
` (22 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Division may (optionally) raise a division exception.
Since the linux kernel has been prepared for this for
some time, enable it by default.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 2 ++
target/nios2/helper.h | 2 ++
linux-user/nios2/cpu_loop.c | 4 +++
target/nios2/cpu.c | 1 +
target/nios2/helper.c | 4 +++
target/nios2/op_helper.c | 29 ++++++++++++++++++
target/nios2/translate.c | 60 +++++++++++++------------------------
7 files changed, 62 insertions(+), 40 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 5403eeae54..2ce76af457 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -207,7 +207,9 @@ struct ArchCPU {
CPUNegativeOffsetState neg;
CPUNios2State env;
+ bool diverr_present;
bool mmu_present;
+
uint32_t pid_num_bits;
uint32_t tlb_num_ways;
uint32_t tlb_num_entries;
diff --git a/target/nios2/helper.h b/target/nios2/helper.h
index 525b6b685b..6f5ec60b0d 100644
--- a/target/nios2/helper.h
+++ b/target/nios2/helper.h
@@ -19,6 +19,8 @@
*/
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
+DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_WG, s32, env, s32, s32)
+DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32)
#if !defined(CONFIG_USER_ONLY)
DEF_HELPER_3(eret, noreturn, env, i32, i32)
diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c
index c5e68ac048..11ecb71843 100644
--- a/linux-user/nios2/cpu_loop.c
+++ b/linux-user/nios2/cpu_loop.c
@@ -38,6 +38,10 @@ void cpu_loop(CPUNios2State *env)
/* just indicate that signals should be handled asap */
break;
+ case EXCP_DIV:
+ force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc);
+ break;
+
case EXCP_TRAP:
/*
* TODO: This advance should be done in the translator, as
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 58e6ad0462..54e7071907 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -263,6 +263,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
}
static Property nios2_properties[] = {
+ DEFINE_PROP_BOOL("diverr_present", Nios2CPU, diverr_present, true),
DEFINE_PROP_BOOL("mmu_present", Nios2CPU, mmu_present, true),
/* ALTR,pid-num-bits */
DEFINE_PROP_UINT32("mmu_pid_num_bits", Nios2CPU, pid_num_bits, 8),
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 4d9085f22f..c5a2dd65b1 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -119,6 +119,9 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_UNALIGND:
name = "Misaligned (destination)";
break;
+ case EXCP_DIV:
+ name = "DIV error";
+ break;
case EXCP_TRAP:
name = "TRAP insn";
break;
@@ -187,6 +190,7 @@ void nios2_cpu_do_interrupt(CPUState *cs)
case EXCP_SUPERI:
case EXCP_ILLEGAL:
+ case EXCP_DIV:
case EXCP_TRAP:
do_exception(cpu, cpu->exception_addr, 0, false);
break;
diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
index 49fccf2c2c..a19b504b0e 100644
--- a/target/nios2/op_helper.c
+++ b/target/nios2/op_helper.c
@@ -31,6 +31,35 @@ void helper_raise_exception(CPUNios2State *env, uint32_t index)
cpu_loop_exit(cs);
}
+static void maybe_raise_div(CPUNios2State *env, uintptr_t ra)
+{
+ Nios2CPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
+
+ if (cpu->diverr_present) {
+ cs->exception_index = EXCP_DIV;
+ cpu_loop_exit_restore(cs, ra);
+ }
+}
+
+int32_t helper_divs(CPUNios2State *env, int32_t num, int32_t den)
+{
+ if (unlikely(den == 0) || unlikely(den == -1 && num == INT32_MIN)) {
+ maybe_raise_div(env, GETPC());
+ return num; /* undefined */
+ }
+ return num / den;
+}
+
+uint32_t helper_divu(CPUNios2State *env, uint32_t num, uint32_t den)
+{
+ if (unlikely(den == 0)) {
+ maybe_raise_div(env, GETPC());
+ return num; /* undefined */
+ }
+ return num / den;
+}
+
#ifndef CONFIG_USER_ONLY
void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc)
{
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index b8d75207a4..b27269bf08 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -654,59 +654,39 @@ gen_r_shift_s(ror, rotr_tl)
static void divs(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, (code));
+ TCGv dest;
- /* Stores into R_ZERO are ignored */
- if (unlikely(instr.c == R_ZERO)) {
- return;
+ if (instr.c == R_ZERO) {
+ dest = tcg_temp_new();
+ } else {
+ dest = cpu_R[instr.c];
}
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
- TCGv t3 = tcg_temp_new();
+ gen_helper_divs(dest, cpu_env,
+ load_gpr(dc, instr.a), load_gpr(dc, instr.b));
- tcg_gen_ext32s_tl(t0, load_gpr(dc, instr.a));
- tcg_gen_ext32s_tl(t1, load_gpr(dc, instr.b));
- tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
- tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
- tcg_gen_and_tl(t2, t2, t3);
- tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
- tcg_gen_or_tl(t2, t2, t3);
- tcg_gen_movi_tl(t3, 0);
- tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
- tcg_gen_div_tl(cpu_R[instr.c], t0, t1);
- tcg_gen_ext32s_tl(cpu_R[instr.c], cpu_R[instr.c]);
-
- tcg_temp_free(t3);
- tcg_temp_free(t2);
- tcg_temp_free(t1);
- tcg_temp_free(t0);
+ if (instr.c == R_ZERO) {
+ tcg_temp_free(dest);
+ }
}
static void divu(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, (code));
+ TCGv dest;
- /* Stores into R_ZERO are ignored */
- if (unlikely(instr.c == R_ZERO)) {
- return;
+ if (instr.c == R_ZERO) {
+ dest = tcg_temp_new();
+ } else {
+ dest = cpu_R[instr.c];
}
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
+ gen_helper_divu(dest, cpu_env,
+ load_gpr(dc, instr.a), load_gpr(dc, instr.b));
- tcg_gen_ext32u_tl(t0, load_gpr(dc, instr.a));
- tcg_gen_ext32u_tl(t1, load_gpr(dc, instr.b));
- tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
- tcg_gen_divu_tl(cpu_R[instr.c], t0, t1);
- tcg_gen_ext32s_tl(cpu_R[instr.c], cpu_R[instr.c]);
-
- tcg_temp_free(t3);
- tcg_temp_free(t2);
- tcg_temp_free(t1);
- tcg_temp_free(t0);
+ if (instr.c == R_ZERO) {
+ tcg_temp_free(dest);
+ }
}
static void trap(DisasContext *dc, uint32_t code, uint32_t flags)
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 42/64] target/nios2: Use tcg_constant_tl
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (40 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 41/64] target/nios2: Support division error exception Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 43/64] target/nios2: Split out named structs for [IRJ]_TYPE Richard Henderson
` (21 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Replace current uses of tcg_const_tl, and remove the frees.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/translate.c | 30 ++++++------------------------
1 file changed, 6 insertions(+), 24 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index b27269bf08..f33015f942 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -99,7 +99,6 @@
typedef struct DisasContext {
DisasContextBase base;
- TCGv_i32 zero;
target_ulong pc;
int mem_idx;
const ControlRegState *cr_state;
@@ -125,31 +124,20 @@ static uint8_t get_opxcode(uint32_t code)
return instr.opx;
}
-static TCGv load_zero(DisasContext *dc)
+static TCGv load_gpr(DisasContext *dc, unsigned reg)
{
- if (!dc->zero) {
- dc->zero = tcg_const_i32(0);
- }
- return dc->zero;
-}
-
-static TCGv load_gpr(DisasContext *dc, uint8_t reg)
-{
- if (likely(reg != R_ZERO)) {
- return cpu_R[reg];
- } else {
- return load_zero(dc);
+ assert(reg < NUM_GP_REGS);
+ if (unlikely(reg == R_ZERO)) {
+ return tcg_constant_tl(0);
}
+ return cpu_R[reg];
}
static void t_gen_helper_raise_exception(DisasContext *dc,
uint32_t index)
{
- TCGv_i32 tmp = tcg_const_i32(index);
-
tcg_gen_movi_tl(cpu_pc, dc->pc);
- gen_helper_raise_exception(cpu_env, tmp);
- tcg_temp_free_i32(tmp);
+ gen_helper_raise_exception(cpu_env, tcg_constant_i32(index));
dc->base.is_jmp = DISAS_NORETURN;
}
@@ -876,14 +864,8 @@ static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
return;
}
- dc->zero = NULL;
-
instr = &i_type_instructions[op];
instr->handler(dc, code, instr->flags);
-
- if (dc->zero) {
- tcg_temp_free(dc->zero);
- }
}
static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 43/64] target/nios2: Split out named structs for [IRJ]_TYPE
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (41 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 42/64] target/nios2: Use tcg_constant_tl Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-22 12:57 ` Peter Maydell
2022-04-21 15:17 ` [PATCH v7 44/64] target/nios2: Split out helpers for gen_* translate macros Richard Henderson
` (20 subsequent siblings)
63 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel
Currently the structures are anonymous within the macro.
Pull them out to standalone types.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/translate.c | 48 ++++++++++++++++++++++------------------
1 file changed, 27 insertions(+), 21 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index f33015f942..a3c63dbbbd 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -53,16 +53,18 @@
#define INSN_R_TYPE 0x3A
/* I-Type instruction parsing */
+typedef struct {
+ uint8_t op;
+ union {
+ uint16_t u;
+ int16_t s;
+ } imm16;
+ uint8_t b;
+ uint8_t a;
+} InstrIType;
+
#define I_TYPE(instr, code) \
- struct { \
- uint8_t op; \
- union { \
- uint16_t u; \
- int16_t s; \
- } imm16; \
- uint8_t b; \
- uint8_t a; \
- } (instr) = { \
+ InstrIType (instr) = { \
.op = extract32((code), 0, 6), \
.imm16.u = extract32((code), 6, 16), \
.b = extract32((code), 22, 5), \
@@ -70,15 +72,17 @@
}
/* R-Type instruction parsing */
+typedef struct {
+ uint8_t op;
+ uint8_t imm5;
+ uint8_t opx;
+ uint8_t c;
+ uint8_t b;
+ uint8_t a;
+} InstrRType;
+
#define R_TYPE(instr, code) \
- struct { \
- uint8_t op; \
- uint8_t imm5; \
- uint8_t opx; \
- uint8_t c; \
- uint8_t b; \
- uint8_t a; \
- } (instr) = { \
+ InstrRType (instr) = { \
.op = extract32((code), 0, 6), \
.imm5 = extract32((code), 6, 5), \
.opx = extract32((code), 11, 6), \
@@ -88,11 +92,13 @@
}
/* J-Type instruction parsing */
+typedef struct {
+ uint8_t op;
+ uint32_t imm26;
+} InstrJType;
+
#define J_TYPE(instr, code) \
- struct { \
- uint8_t op; \
- uint32_t imm26; \
- } (instr) = { \
+ InstrJType (instr) = { \
.op = extract32((code), 0, 6), \
.imm26 = extract32((code), 6, 26), \
}
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 44/64] target/nios2: Split out helpers for gen_* translate macros
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (42 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 43/64] target/nios2: Split out named structs for [IRJ]_TYPE Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-22 13:16 ` Peter Maydell
2022-04-21 15:17 ` [PATCH v7 45/64] target/nios2: Introduce dest_gpr Richard Henderson
` (19 subsequent siblings)
63 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel
Do as little work as possible within the macros.
Split out helper functions and pass in arguments instead.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/translate.c | 215 +++++++++++++++++++++++++--------------
1 file changed, 141 insertions(+), 74 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index a3c63dbbbd..74672101ca 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -71,6 +71,21 @@ typedef struct {
.a = extract32((code), 27, 5), \
}
+static target_ulong imm_unsigned(const InstrIType *i)
+{
+ return i->imm16.u;
+}
+
+static target_ulong imm_signed(const InstrIType *i)
+{
+ return i->imm16.s;
+}
+
+static target_ulong imm_shifted(const InstrIType *i)
+{
+ return i->imm16.u << 16;
+}
+
/* R-Type instruction parsing */
typedef struct {
uint8_t op;
@@ -268,40 +283,62 @@ static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags)
}
/* Comparison instructions */
-#define gen_i_cmpxx(fname, op3) \
-static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
-{ \
- I_TYPE(instr, (code)); \
- tcg_gen_setcondi_tl(flags, cpu_R[instr.b], cpu_R[instr.a], (op3)); \
+static void do_i_cmpxx(DisasContext *dc, uint32_t insn, TCGCond cond,
+ target_ulong (*imm)(const InstrIType *))
+{
+ I_TYPE(instr, insn);
+
+ if (likely(instr.b != R_ZERO)) {
+ tcg_gen_setcondi_tl(cond, cpu_R[instr.b],
+ load_gpr(dc, instr.a), imm(&instr));
+ }
}
-gen_i_cmpxx(gen_cmpxxsi, instr.imm16.s)
-gen_i_cmpxx(gen_cmpxxui, instr.imm16.u)
+#define gen_i_cmpxx(fname, imm) \
+ static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
+ { do_i_cmpxx(dc, code, flags, imm); }
+
+gen_i_cmpxx(gen_cmpxxsi, imm_signed)
+gen_i_cmpxx(gen_cmpxxui, imm_unsigned)
/* Math/logic instructions */
-#define gen_i_math_logic(fname, insn, resimm, op3) \
-static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
-{ \
- I_TYPE(instr, (code)); \
- if (unlikely(instr.b == R_ZERO)) { /* Store to R_ZERO is ignored */ \
- return; \
- } else if (instr.a == R_ZERO) { /* MOVxI optimizations */ \
- tcg_gen_movi_tl(cpu_R[instr.b], (resimm) ? (op3) : 0); \
- } else { \
- tcg_gen_##insn##_tl(cpu_R[instr.b], cpu_R[instr.a], (op3)); \
- } \
+static void do_i_math_logic(DisasContext *dc, uint32_t insn,
+ void (*fn)(TCGv, TCGv, target_long),
+ target_ulong (*imm)(const InstrIType *),
+ bool x_op_0_eq_x)
+{
+ I_TYPE(instr, insn);
+ target_ulong val;
+
+ if (unlikely(instr.b == R_ZERO)) {
+ /* Store to R_ZERO is ignored -- this catches the canonical NOP. */
+ return;
+ }
+
+ val = imm(&instr);
+
+ if (instr.a == R_ZERO) {
+ /* This catches the canonical expansions of movi and movhi. */
+ tcg_gen_movi_tl(cpu_R[instr.b], x_op_0_eq_x ? val : 0);
+ } else {
+ fn(cpu_R[instr.b], cpu_R[instr.a], val);
+ }
}
-gen_i_math_logic(addi, addi, 1, instr.imm16.s)
-gen_i_math_logic(muli, muli, 0, instr.imm16.s)
+#define gen_i_math_logic(fname, insn, x_op_0, imm) \
+ static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
+ { do_i_math_logic(dc, code, tcg_gen_##insn##_tl, imm, x_op_0); }
-gen_i_math_logic(andi, andi, 0, instr.imm16.u)
-gen_i_math_logic(ori, ori, 1, instr.imm16.u)
-gen_i_math_logic(xori, xori, 1, instr.imm16.u)
+gen_i_math_logic(addi, addi, 1, imm_signed)
+gen_i_math_logic(muli, muli, 0, imm_signed)
-gen_i_math_logic(andhi, andi, 0, instr.imm16.u << 16)
-gen_i_math_logic(orhi , ori, 1, instr.imm16.u << 16)
-gen_i_math_logic(xorhi, xori, 1, instr.imm16.u << 16)
+gen_i_math_logic(andi, andi, 0, imm_unsigned)
+gen_i_math_logic(ori, ori, 1, imm_unsigned)
+gen_i_math_logic(xori, xori, 1, imm_unsigned)
+
+gen_i_math_logic(andhi, andi, 0, imm_shifted)
+gen_i_math_logic(orhi , ori, 1, imm_shifted)
+gen_i_math_logic(xorhi, xori, 1, imm_shifted)
/* Prototype only, defined below */
static void handle_r_type_instr(DisasContext *dc, uint32_t code,
@@ -588,62 +625,92 @@ static void gen_cmpxx(DisasContext *dc, uint32_t code, uint32_t flags)
}
/* Math/logic instructions */
-#define gen_r_math_logic(fname, insn, op3) \
-static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
-{ \
- R_TYPE(instr, (code)); \
- if (likely(instr.c != R_ZERO)) { \
- tcg_gen_##insn(cpu_R[instr.c], load_gpr((dc), instr.a), (op3)); \
- } \
+static void do_ri_math_logic(DisasContext *dc, uint32_t insn,
+ void (*fn)(TCGv, TCGv, int32_t))
+{
+ R_TYPE(instr, insn);
+
+ if (likely(instr.c != R_ZERO)) {
+ fn(cpu_R[instr.c], load_gpr(dc, instr.a), instr.imm5);
+ }
}
-gen_r_math_logic(add, add_tl, load_gpr(dc, instr.b))
-gen_r_math_logic(sub, sub_tl, load_gpr(dc, instr.b))
-gen_r_math_logic(mul, mul_tl, load_gpr(dc, instr.b))
+static void do_rr_math_logic(DisasContext *dc, uint32_t insn,
+ void (*fn)(TCGv, TCGv, TCGv))
+{
+ R_TYPE(instr, insn);
-gen_r_math_logic(and, and_tl, load_gpr(dc, instr.b))
-gen_r_math_logic(or, or_tl, load_gpr(dc, instr.b))
-gen_r_math_logic(xor, xor_tl, load_gpr(dc, instr.b))
-gen_r_math_logic(nor, nor_tl, load_gpr(dc, instr.b))
-
-gen_r_math_logic(srai, sari_tl, instr.imm5)
-gen_r_math_logic(srli, shri_tl, instr.imm5)
-gen_r_math_logic(slli, shli_tl, instr.imm5)
-gen_r_math_logic(roli, rotli_tl, instr.imm5)
-
-#define gen_r_mul(fname, insn) \
-static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
-{ \
- R_TYPE(instr, (code)); \
- if (likely(instr.c != R_ZERO)) { \
- TCGv t0 = tcg_temp_new(); \
- tcg_gen_##insn(t0, cpu_R[instr.c], \
- load_gpr(dc, instr.a), load_gpr(dc, instr.b)); \
- tcg_temp_free(t0); \
- } \
+ if (likely(instr.c != R_ZERO)) {
+ fn(cpu_R[instr.c], load_gpr(dc, instr.a), load_gpr(dc, instr.b));
+ }
}
-gen_r_mul(mulxss, muls2_tl)
-gen_r_mul(mulxuu, mulu2_tl)
-gen_r_mul(mulxsu, mulsu2_tl)
+#define gen_ri_math_logic(fname, insn) \
+ static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
+ { do_ri_math_logic(dc, code, tcg_gen_##insn##_tl); }
-#define gen_r_shift_s(fname, insn) \
-static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
-{ \
- R_TYPE(instr, (code)); \
- if (likely(instr.c != R_ZERO)) { \
- TCGv t0 = tcg_temp_new(); \
- tcg_gen_andi_tl(t0, load_gpr((dc), instr.b), 31); \
- tcg_gen_##insn(cpu_R[instr.c], load_gpr((dc), instr.a), t0); \
- tcg_temp_free(t0); \
- } \
+#define gen_rr_math_logic(fname, insn) \
+ static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
+ { do_rr_math_logic(dc, code, tcg_gen_##insn##_tl); }
+
+gen_rr_math_logic(add, add)
+gen_rr_math_logic(sub, sub)
+gen_rr_math_logic(mul, mul)
+
+gen_rr_math_logic(and, and)
+gen_rr_math_logic(or, or)
+gen_rr_math_logic(xor, xor)
+gen_rr_math_logic(nor, nor)
+
+gen_ri_math_logic(srai, sari)
+gen_ri_math_logic(srli, shri)
+gen_ri_math_logic(slli, shli)
+gen_ri_math_logic(roli, rotli)
+
+static void do_rr_mul_high(DisasContext *dc, uint32_t insn,
+ void (*fn)(TCGv, TCGv, TCGv, TCGv))
+{
+ R_TYPE(instr, insn);
+
+ if (likely(instr.c != R_ZERO)) {
+ TCGv discard = tcg_temp_new();
+ fn(discard, cpu_R[instr.c], load_gpr(dc, instr.a),
+ load_gpr(dc, instr.b));
+ tcg_temp_free(discard);
+ }
}
-gen_r_shift_s(sra, sar_tl)
-gen_r_shift_s(srl, shr_tl)
-gen_r_shift_s(sll, shl_tl)
-gen_r_shift_s(rol, rotl_tl)
-gen_r_shift_s(ror, rotr_tl)
+#define gen_rr_mul_high(fname, insn) \
+ static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
+ { do_rr_mul_high(dc, code, tcg_gen_##insn##_tl); }
+
+gen_rr_mul_high(mulxss, muls2)
+gen_rr_mul_high(mulxuu, mulu2)
+gen_rr_mul_high(mulxsu, mulsu2)
+
+static void do_rr_shift(DisasContext *dc, uint32_t insn,
+ void (*fn)(TCGv, TCGv, TCGv))
+{
+ R_TYPE(instr, insn);
+
+ if (likely(instr.c != R_ZERO)) {
+ TCGv sh = tcg_temp_new();
+
+ tcg_gen_andi_tl(sh, load_gpr(dc, instr.b), 31);
+ fn(cpu_R[instr.c], load_gpr(dc, instr.a), sh);
+ tcg_temp_free(sh);
+ }
+}
+
+#define gen_rr_shift(fname, insn) \
+ static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
+ { do_rr_shift(dc, code, tcg_gen_##insn##_tl); }
+
+gen_rr_shift(sra, sar)
+gen_rr_shift(srl, shr)
+gen_rr_shift(sll, shl)
+gen_rr_shift(rol, rotl)
+gen_rr_shift(ror, rotr)
static void divs(DisasContext *dc, uint32_t code, uint32_t flags)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* Re: [PATCH v7 44/64] target/nios2: Split out helpers for gen_* translate macros
2022-04-21 15:17 ` [PATCH v7 44/64] target/nios2: Split out helpers for gen_* translate macros Richard Henderson
@ 2022-04-22 13:16 ` Peter Maydell
0 siblings, 0 replies; 78+ messages in thread
From: Peter Maydell @ 2022-04-22 13:16 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Thu, 21 Apr 2022 at 16:55, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Do as little work as possible within the macros.
> Split out helper functions and pass in arguments instead.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/nios2/translate.c | 215 +++++++++++++++++++++++++--------------
> 1 file changed, 141 insertions(+), 74 deletions(-)
>
> diff --git a/target/nios2/translate.c b/target/nios2/translate.c
> index a3c63dbbbd..74672101ca 100644
> --- a/target/nios2/translate.c
> +++ b/target/nios2/translate.c
> @@ -71,6 +71,21 @@ typedef struct {
> .a = extract32((code), 27, 5), \
> }
>
> +static target_ulong imm_unsigned(const InstrIType *i)
> +{
> + return i->imm16.u;
> +}
> +
> +static target_ulong imm_signed(const InstrIType *i)
> +{
> + return i->imm16.s;
> +}
> +
> +static target_ulong imm_shifted(const InstrIType *i)
> +{
> + return i->imm16.u << 16;
> +}
> +
> /* R-Type instruction parsing */
> typedef struct {
> uint8_t op;
> @@ -268,40 +283,62 @@ static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags)
> }
>
> /* Comparison instructions */
> -#define gen_i_cmpxx(fname, op3) \
> -static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
> -{ \
> - I_TYPE(instr, (code)); \
> - tcg_gen_setcondi_tl(flags, cpu_R[instr.b], cpu_R[instr.a], (op3)); \
> +static void do_i_cmpxx(DisasContext *dc, uint32_t insn, TCGCond cond,
> + target_ulong (*imm)(const InstrIType *))
Can we have some typedefs if we're passing function pointers around,
please? I think they're easier to read than having raw
function-pointer type signatures in function prototypes.
> +{
> + I_TYPE(instr, insn);
> +
> + if (likely(instr.b != R_ZERO)) {
> + tcg_gen_setcondi_tl(cond, cpu_R[instr.b],
> + load_gpr(dc, instr.a), imm(&instr));
> + }
The old code didn't do this check against R_ZERO.
> }
> /* Math/logic instructions */
> -#define gen_r_math_logic(fname, insn, op3) \
> -static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
> -{ \
> - R_TYPE(instr, (code)); \
> - if (likely(instr.c != R_ZERO)) { \
> - tcg_gen_##insn(cpu_R[instr.c], load_gpr((dc), instr.a), (op3)); \
> - } \
> +static void do_ri_math_logic(DisasContext *dc, uint32_t insn,
> + void (*fn)(TCGv, TCGv, int32_t))
> +{
> + R_TYPE(instr, insn);
> +
> + if (likely(instr.c != R_ZERO)) {
> + fn(cpu_R[instr.c], load_gpr(dc, instr.a), instr.imm5);
> + }
> }
>
> -gen_r_math_logic(add, add_tl, load_gpr(dc, instr.b))
> -gen_r_math_logic(sub, sub_tl, load_gpr(dc, instr.b))
> -gen_r_math_logic(mul, mul_tl, load_gpr(dc, instr.b))
> +static void do_rr_math_logic(DisasContext *dc, uint32_t insn,
> + void (*fn)(TCGv, TCGv, TCGv))
> +{
> + R_TYPE(instr, insn);
>
> -gen_r_math_logic(and, and_tl, load_gpr(dc, instr.b))
> -gen_r_math_logic(or, or_tl, load_gpr(dc, instr.b))
> -gen_r_math_logic(xor, xor_tl, load_gpr(dc, instr.b))
> -gen_r_math_logic(nor, nor_tl, load_gpr(dc, instr.b))
> -
> -gen_r_math_logic(srai, sari_tl, instr.imm5)
> -gen_r_math_logic(srli, shri_tl, instr.imm5)
> -gen_r_math_logic(slli, shli_tl, instr.imm5)
> -gen_r_math_logic(roli, rotli_tl, instr.imm5)
> -
> -#define gen_r_mul(fname, insn) \
> -static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
> -{ \
> - R_TYPE(instr, (code)); \
> - if (likely(instr.c != R_ZERO)) { \
> - TCGv t0 = tcg_temp_new(); \
> - tcg_gen_##insn(t0, cpu_R[instr.c], \
> - load_gpr(dc, instr.a), load_gpr(dc, instr.b)); \
> - tcg_temp_free(t0); \
> - } \
> + if (likely(instr.c != R_ZERO)) {
> + fn(cpu_R[instr.c], load_gpr(dc, instr.a), load_gpr(dc, instr.b));
> + }
> }
>
> -gen_r_mul(mulxss, muls2_tl)
> -gen_r_mul(mulxuu, mulu2_tl)
> -gen_r_mul(mulxsu, mulsu2_tl)
> +#define gen_ri_math_logic(fname, insn) \
> + static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
> + { do_ri_math_logic(dc, code, tcg_gen_##insn##_tl); }
>
> -#define gen_r_shift_s(fname, insn) \
> -static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
> -{ \
> - R_TYPE(instr, (code)); \
> - if (likely(instr.c != R_ZERO)) { \
> - TCGv t0 = tcg_temp_new(); \
> - tcg_gen_andi_tl(t0, load_gpr((dc), instr.b), 31); \
> - tcg_gen_##insn(cpu_R[instr.c], load_gpr((dc), instr.a), t0); \
> - tcg_temp_free(t0); \
> - } \
> +#define gen_rr_math_logic(fname, insn) \
> + static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
> + { do_rr_math_logic(dc, code, tcg_gen_##insn##_tl); }
git diff has made a bit of a pig's ear of this, interleaving the
changes related to math_logic and the ones related to shift and mul.
If you do these changes one insn group at a time rather than
all in one patch I think the resulting diff should be easier to read.
-- PMM
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH v7 45/64] target/nios2: Introduce dest_gpr
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (43 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 44/64] target/nios2: Split out helpers for gen_* translate macros Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 46/64] target/nios2: Drop CR_STATUS_EH from tb->flags Richard Henderson
` (18 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Constrain all references to cpu_R[] to load_gpr and dest_gpr.
This will be required for supporting shadow register sets.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/translate.c | 144 +++++++++++++--------------------------
1 file changed, 49 insertions(+), 95 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 74672101ca..98efb4e10a 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -122,6 +122,7 @@ typedef struct DisasContext {
DisasContextBase base;
target_ulong pc;
int mem_idx;
+ TCGv sink;
const ControlRegState *cr_state;
} DisasContext;
@@ -154,6 +155,18 @@ static TCGv load_gpr(DisasContext *dc, unsigned reg)
return cpu_R[reg];
}
+static TCGv dest_gpr(DisasContext *dc, unsigned reg)
+{
+ assert(reg < NUM_GP_REGS);
+ if (unlikely(reg == R_ZERO)) {
+ if (dc->sink == NULL) {
+ dc->sink = tcg_temp_new();
+ }
+ return dc->sink;
+ }
+ return cpu_R[reg];
+}
+
static void t_gen_helper_raise_exception(DisasContext *dc,
uint32_t index)
{
@@ -212,7 +225,7 @@ static void jmpi(DisasContext *dc, uint32_t code, uint32_t flags)
static void call(DisasContext *dc, uint32_t code, uint32_t flags)
{
- tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next);
+ tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next);
jmpi(dc, code, flags);
}
@@ -225,27 +238,10 @@ static void gen_ldx(DisasContext *dc, uint32_t code, uint32_t flags)
I_TYPE(instr, code);
TCGv addr = tcg_temp_new();
- TCGv data;
-
- /*
- * WARNING: Loads into R_ZERO are ignored, but we must generate the
- * memory access itself to emulate the CPU precisely. Load
- * from a protected page to R_ZERO will cause SIGSEGV on
- * the Nios2 CPU.
- */
- if (likely(instr.b != R_ZERO)) {
- data = cpu_R[instr.b];
- } else {
- data = tcg_temp_new();
- }
+ TCGv data = dest_gpr(dc, instr.b);
tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s);
tcg_gen_qemu_ld_tl(data, addr, dc->mem_idx, flags);
-
- if (unlikely(instr.b == R_ZERO)) {
- tcg_temp_free(data);
- }
-
tcg_temp_free(addr);
}
@@ -275,7 +271,7 @@ static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags)
I_TYPE(instr, code);
TCGLabel *l1 = gen_new_label();
- tcg_gen_brcond_tl(flags, cpu_R[instr.a], cpu_R[instr.b], l1);
+ tcg_gen_brcond_tl(flags, load_gpr(dc, instr.a), load_gpr(dc, instr.b), l1);
gen_goto_tb(dc, 0, dc->base.pc_next);
gen_set_label(l1);
gen_goto_tb(dc, 1, dc->base.pc_next + (instr.imm16.s & -4));
@@ -287,11 +283,8 @@ static void do_i_cmpxx(DisasContext *dc, uint32_t insn, TCGCond cond,
target_ulong (*imm)(const InstrIType *))
{
I_TYPE(instr, insn);
-
- if (likely(instr.b != R_ZERO)) {
- tcg_gen_setcondi_tl(cond, cpu_R[instr.b],
- load_gpr(dc, instr.a), imm(&instr));
- }
+ tcg_gen_setcondi_tl(cond, dest_gpr(dc, instr.b),
+ load_gpr(dc, instr.a), imm(&instr));
}
#define gen_i_cmpxx(fname, imm) \
@@ -319,9 +312,9 @@ static void do_i_math_logic(DisasContext *dc, uint32_t insn,
if (instr.a == R_ZERO) {
/* This catches the canonical expansions of movi and movhi. */
- tcg_gen_movi_tl(cpu_R[instr.b], x_op_0_eq_x ? val : 0);
+ tcg_gen_movi_tl(dest_gpr(dc, instr.b), x_op_0_eq_x ? val : 0);
} else {
- fn(cpu_R[instr.b], cpu_R[instr.a], val);
+ fn(dest_gpr(dc, instr.b), load_gpr(dc, instr.a), val);
}
}
@@ -429,7 +422,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
#else
TCGv tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS]));
- gen_helper_eret(cpu_env, tmp, cpu_R[R_EA]);
+ gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA));
tcg_temp_free(tmp);
dc->base.is_jmp = DISAS_NORETURN;
@@ -439,8 +432,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
/* PC <- ra */
static void ret(DisasContext *dc, uint32_t code, uint32_t flags)
{
- tcg_gen_mov_tl(cpu_pc, cpu_R[R_RA]);
-
+ tcg_gen_mov_tl(cpu_pc, load_gpr(dc, R_RA));
dc->base.is_jmp = DISAS_JUMP;
}
@@ -459,7 +451,7 @@ static void bret(DisasContext *dc, uint32_t code, uint32_t flags)
#else
TCGv tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS]));
- gen_helper_eret(cpu_env, tmp, cpu_R[R_BA]);
+ gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_BA));
tcg_temp_free(tmp);
dc->base.is_jmp = DISAS_NORETURN;
@@ -472,7 +464,6 @@ static void jmp(DisasContext *dc, uint32_t code, uint32_t flags)
R_TYPE(instr, code);
tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a));
-
dc->base.is_jmp = DISAS_JUMP;
}
@@ -481,9 +472,7 @@ static void nextpc(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, code);
- if (likely(instr.c != R_ZERO)) {
- tcg_gen_movi_tl(cpu_R[instr.c], dc->base.pc_next);
- }
+ tcg_gen_movi_tl(dest_gpr(dc, instr.c), dc->base.pc_next);
}
/*
@@ -495,7 +484,7 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags)
R_TYPE(instr, code);
tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a));
- tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next);
+ tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next);
dc->base.is_jmp = DISAS_JUMP;
}
@@ -511,15 +500,11 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
g_assert_not_reached();
#else
R_TYPE(instr, code);
- TCGv t1, t2;
-
- if (unlikely(instr.c == R_ZERO)) {
- return;
- }
+ TCGv t1, t2, dest = dest_gpr(dc, instr.c);
/* Reserved registers read as zero. */
if (nios2_cr_reserved(&dc->cr_state[instr.imm5])) {
- tcg_gen_movi_tl(cpu_R[instr.c], 0);
+ tcg_gen_movi_tl(dest, 0);
return;
}
@@ -537,12 +522,12 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
t2 = tcg_temp_new();
tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDING]));
tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE]));
- tcg_gen_and_tl(cpu_R[instr.c], t1, t2);
+ tcg_gen_and_tl(dest, t1, t2);
tcg_temp_free(t1);
tcg_temp_free(t2);
break;
default:
- tcg_gen_ld_tl(cpu_R[instr.c], cpu_env,
+ tcg_gen_ld_tl(dest, cpu_env,
offsetof(CPUNios2State, ctrl[instr.imm5]));
break;
}
@@ -618,10 +603,8 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
static void gen_cmpxx(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, code);
- if (likely(instr.c != R_ZERO)) {
- tcg_gen_setcond_tl(flags, cpu_R[instr.c], cpu_R[instr.a],
- cpu_R[instr.b]);
- }
+ tcg_gen_setcond_tl(flags, dest_gpr(dc, instr.c),
+ load_gpr(dc, instr.a), load_gpr(dc, instr.b));
}
/* Math/logic instructions */
@@ -629,20 +612,14 @@ static void do_ri_math_logic(DisasContext *dc, uint32_t insn,
void (*fn)(TCGv, TCGv, int32_t))
{
R_TYPE(instr, insn);
-
- if (likely(instr.c != R_ZERO)) {
- fn(cpu_R[instr.c], load_gpr(dc, instr.a), instr.imm5);
- }
+ fn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), instr.imm5);
}
static void do_rr_math_logic(DisasContext *dc, uint32_t insn,
void (*fn)(TCGv, TCGv, TCGv))
{
R_TYPE(instr, insn);
-
- if (likely(instr.c != R_ZERO)) {
- fn(cpu_R[instr.c], load_gpr(dc, instr.a), load_gpr(dc, instr.b));
- }
+ fn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), load_gpr(dc, instr.b));
}
#define gen_ri_math_logic(fname, insn) \
@@ -671,13 +648,11 @@ static void do_rr_mul_high(DisasContext *dc, uint32_t insn,
void (*fn)(TCGv, TCGv, TCGv, TCGv))
{
R_TYPE(instr, insn);
+ TCGv discard = tcg_temp_new();
- if (likely(instr.c != R_ZERO)) {
- TCGv discard = tcg_temp_new();
- fn(discard, cpu_R[instr.c], load_gpr(dc, instr.a),
- load_gpr(dc, instr.b));
- tcg_temp_free(discard);
- }
+ fn(discard, dest_gpr(dc, instr.c),
+ load_gpr(dc, instr.a), load_gpr(dc, instr.b));
+ tcg_temp_free(discard);
}
#define gen_rr_mul_high(fname, insn) \
@@ -692,14 +667,11 @@ static void do_rr_shift(DisasContext *dc, uint32_t insn,
void (*fn)(TCGv, TCGv, TCGv))
{
R_TYPE(instr, insn);
+ TCGv sh = tcg_temp_new();
- if (likely(instr.c != R_ZERO)) {
- TCGv sh = tcg_temp_new();
-
- tcg_gen_andi_tl(sh, load_gpr(dc, instr.b), 31);
- fn(cpu_R[instr.c], load_gpr(dc, instr.a), sh);
- tcg_temp_free(sh);
- }
+ tcg_gen_andi_tl(sh, load_gpr(dc, instr.b), 31);
+ fn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), sh);
+ tcg_temp_free(sh);
}
#define gen_rr_shift(fname, insn) \
@@ -715,39 +687,15 @@ gen_rr_shift(ror, rotr)
static void divs(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, (code));
- TCGv dest;
-
- if (instr.c == R_ZERO) {
- dest = tcg_temp_new();
- } else {
- dest = cpu_R[instr.c];
- }
-
- gen_helper_divs(dest, cpu_env,
+ gen_helper_divs(dest_gpr(dc, instr.c), cpu_env,
load_gpr(dc, instr.a), load_gpr(dc, instr.b));
-
- if (instr.c == R_ZERO) {
- tcg_temp_free(dest);
- }
}
static void divu(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, (code));
- TCGv dest;
-
- if (instr.c == R_ZERO) {
- dest = tcg_temp_new();
- } else {
- dest = cpu_R[instr.c];
- }
-
- gen_helper_divu(dest, cpu_env,
+ gen_helper_divu(dest_gpr(dc, instr.c), cpu_env,
load_gpr(dc, instr.a), load_gpr(dc, instr.b));
-
- if (instr.c == R_ZERO) {
- tcg_temp_free(dest);
- }
}
static void trap(DisasContext *dc, uint32_t code, uint32_t flags)
@@ -937,8 +885,14 @@ static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
return;
}
+ dc->sink = NULL;
+
instr = &i_type_instructions[op];
instr->handler(dc, code, instr->flags);
+
+ if (dc->sink) {
+ tcg_temp_free(dc->sink);
+ }
}
static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 46/64] target/nios2: Drop CR_STATUS_EH from tb->flags
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (44 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 45/64] target/nios2: Introduce dest_gpr Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 47/64] target/nios2: Enable unaligned traps for system mode Richard Henderson
` (17 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
There's nothing about EH that affects translation,
so there's no need to include it in tb->flags.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 2ce76af457..6417e9bbfc 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -272,7 +272,7 @@ static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc,
{
*pc = env->pc;
*cs_base = 0;
- *flags = env->ctrl[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U);
+ *flags = env->ctrl[CR_STATUS] & CR_STATUS_U;
}
#endif /* NIOS2_CPU_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 47/64] target/nios2: Enable unaligned traps for system mode
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (45 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 46/64] target/nios2: Drop CR_STATUS_EH from tb->flags Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 48/64] target/nios2: Create gen_jumpr Richard Henderson
` (16 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Unaligned traps are optional, but required with an mmu.
Turn them on always, because the fallback behaviour undefined.
Enable alignment checks in the config file.
Unwind the guest pc properly from do_unaligned_access.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
configs/targets/nios2-softmmu.mak | 1 +
target/nios2/helper.c | 4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/configs/targets/nios2-softmmu.mak b/configs/targets/nios2-softmmu.mak
index 9a372f0717..1e93b54cd1 100644
--- a/configs/targets/nios2-softmmu.mak
+++ b/configs/targets/nios2-softmmu.mak
@@ -1 +1,2 @@
TARGET_ARCH=nios2
+TARGET_ALIGNED_ONLY=y
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index c5a2dd65b1..2e9fea4a01 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -241,8 +241,8 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
CPUNios2State *env = &cpu->env;
env->ctrl[CR_BADADDR] = addr;
- env->ctrl[CR_EXCEPTION] = FIELD_DP32(0, CR_EXCEPTION, CAUSE, EXCP_UNALIGN);
- helper_raise_exception(env, EXCP_UNALIGN);
+ cs->exception_index = EXCP_UNALIGN;
+ cpu_loop_exit_restore(cs, retaddr);
}
bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 48/64] target/nios2: Create gen_jumpr
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (46 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 47/64] target/nios2: Enable unaligned traps for system mode Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 49/64] target/nios2: Hoist set of is_jmp into gen_goto_tb Richard Henderson
` (15 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Split out a function to perform an indirect branch.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/translate.c | 27 +++++++++++++--------------
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 98efb4e10a..e39e349389 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -36,7 +36,6 @@
#include "semihosting/semihost.h"
/* is_jmp field values */
-#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
#define INSTRUCTION_FLG(func, flags) { (func), (flags) }
@@ -189,6 +188,16 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest)
}
}
+static void gen_jumpr(DisasContext *dc, int regno, bool is_call)
+{
+ tcg_gen_mov_tl(cpu_pc, load_gpr(dc, regno));
+ if (is_call) {
+ tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next);
+ }
+ tcg_gen_exit_tb(NULL, 0);
+ dc->base.is_jmp = DISAS_NORETURN;
+}
+
static void gen_excp(DisasContext *dc, uint32_t code, uint32_t flags)
{
t_gen_helper_raise_exception(dc, flags);
@@ -432,8 +441,7 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
/* PC <- ra */
static void ret(DisasContext *dc, uint32_t code, uint32_t flags)
{
- tcg_gen_mov_tl(cpu_pc, load_gpr(dc, R_RA));
- dc->base.is_jmp = DISAS_JUMP;
+ gen_jumpr(dc, R_RA, false);
}
/*
@@ -463,8 +471,7 @@ static void jmp(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, code);
- tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a));
- dc->base.is_jmp = DISAS_JUMP;
+ gen_jumpr(dc, instr.a, false);
}
/* rC <- PC + 4 */
@@ -483,10 +490,7 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, code);
- tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a));
- tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next);
-
- dc->base.is_jmp = DISAS_JUMP;
+ gen_jumpr(dc, instr.a, true);
}
/* rC <- ctlN */
@@ -908,11 +912,6 @@ static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
tcg_gen_exit_tb(NULL, 0);
break;
- case DISAS_JUMP:
- /* The jump will already have updated the PC register */
- tcg_gen_exit_tb(NULL, 0);
- break;
-
case DISAS_NORETURN:
/* nothing more to generate */
break;
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 49/64] target/nios2: Hoist set of is_jmp into gen_goto_tb
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (47 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 48/64] target/nios2: Create gen_jumpr Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 50/64] target/nios2: Use gen_goto_tb for DISAS_TOO_MANY Richard Henderson
` (14 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Rather than force all callers to set this, do it
within the subroutine.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index e39e349389..1686d2b82f 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -186,6 +186,7 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest)
tcg_gen_movi_tl(cpu_pc, dest);
tcg_gen_exit_tb(NULL, 0);
}
+ dc->base.is_jmp = DISAS_NORETURN;
}
static void gen_jumpr(DisasContext *dc, int regno, bool is_call)
@@ -229,7 +230,6 @@ static void jmpi(DisasContext *dc, uint32_t code, uint32_t flags)
{
J_TYPE(instr, code);
gen_goto_tb(dc, 0, (dc->pc & 0xF0000000) | (instr.imm26 << 2));
- dc->base.is_jmp = DISAS_NORETURN;
}
static void call(DisasContext *dc, uint32_t code, uint32_t flags)
@@ -272,7 +272,6 @@ static void br(DisasContext *dc, uint32_t code, uint32_t flags)
I_TYPE(instr, code);
gen_goto_tb(dc, 0, dc->base.pc_next + (instr.imm16.s & -4));
- dc->base.is_jmp = DISAS_NORETURN;
}
static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags)
@@ -284,7 +283,6 @@ static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags)
gen_goto_tb(dc, 0, dc->base.pc_next);
gen_set_label(l1);
gen_goto_tb(dc, 1, dc->base.pc_next + (instr.imm16.s & -4));
- dc->base.is_jmp = DISAS_NORETURN;
}
/* Comparison instructions */
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 50/64] target/nios2: Use gen_goto_tb for DISAS_TOO_MANY
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (48 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 49/64] target/nios2: Hoist set of is_jmp into gen_goto_tb Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 51/64] target/nios2: Use tcg_gen_lookup_and_goto_ptr Richard Henderson
` (13 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Depending on the reason for ending the TB, we can chain
to the next TB because the PC is constant.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/translate.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 1686d2b82f..c9b5de2981 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -904,8 +904,11 @@ static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
/* Indicate where the next block should start */
switch (dc->base.is_jmp) {
case DISAS_TOO_MANY:
+ gen_goto_tb(dc, 0, dc->base.pc_next);
+ break;
+
case DISAS_UPDATE:
- /* Save the current PC back into the CPU register */
+ /* Save the current PC, and return to the main loop. */
tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
tcg_gen_exit_tb(NULL, 0);
break;
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 51/64] target/nios2: Use tcg_gen_lookup_and_goto_ptr
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (49 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 50/64] target/nios2: Use gen_goto_tb for DISAS_TOO_MANY Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 52/64] target/nios2: Implement Misaligned destination exception Richard Henderson
` (12 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Use lookup_and_goto_ptr for indirect chaining between TBs.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index c9b5de2981..f0f5c6843a 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -184,7 +184,7 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest)
tcg_gen_exit_tb(tb, n);
} else {
tcg_gen_movi_tl(cpu_pc, dest);
- tcg_gen_exit_tb(NULL, 0);
+ tcg_gen_lookup_and_goto_ptr();
}
dc->base.is_jmp = DISAS_NORETURN;
}
@@ -195,7 +195,7 @@ static void gen_jumpr(DisasContext *dc, int regno, bool is_call)
if (is_call) {
tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next);
}
- tcg_gen_exit_tb(NULL, 0);
+ tcg_gen_lookup_and_goto_ptr();
dc->base.is_jmp = DISAS_NORETURN;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 52/64] target/nios2: Implement Misaligned destination exception
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (50 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 51/64] target/nios2: Use tcg_gen_lookup_and_goto_ptr Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 53/64] target/nios2: Introduce shadow register sets Richard Henderson
` (11 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Indirect branches, plus eret and bret optionally raise
an exception when branching to a misaligned address.
The exception is required when an mmu is enabled, but
enable it always because the fallback behaviour is not
documented (though presumably it discards low bits).
For the purposes of the linux-user cpu loop, if EXCP_UNALIGN
(misaligned data) were to arrive, it would be treated the
same as EXCP_UNALIGND (misaligned destination). See the
!defined(CONFIG_NIOS2_ALIGNMENT_TRAP) block in kernel/traps.c.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/nios2/cpu_loop.c | 6 ++++++
target/nios2/op_helper.c | 9 ++++++++-
target/nios2/translate.c | 15 ++++++++++++++-
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c
index 11ecb71843..30a27f252b 100644
--- a/linux-user/nios2/cpu_loop.c
+++ b/linux-user/nios2/cpu_loop.c
@@ -42,6 +42,12 @@ void cpu_loop(CPUNios2State *env)
force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc);
break;
+ case EXCP_UNALIGN:
+ case EXCP_UNALIGND:
+ force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN,
+ env->ctrl[CR_BADADDR]);
+ break;
+
case EXCP_TRAP:
/*
* TODO: This advance should be done in the translator, as
diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
index a19b504b0e..38a71a1f2d 100644
--- a/target/nios2/op_helper.c
+++ b/target/nios2/op_helper.c
@@ -64,6 +64,13 @@ uint32_t helper_divu(CPUNios2State *env, uint32_t num, uint32_t den)
void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc)
{
Nios2CPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
+
+ if (unlikely(new_pc & 3)) {
+ env->ctrl[CR_BADADDR] = new_pc;
+ cs->exception_index = EXCP_UNALIGND;
+ cpu_loop_exit_restore(cs, GETPC());
+ }
/*
* Both estatus and bstatus have no constraints on write;
@@ -74,6 +81,6 @@ void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc)
env->ctrl[CR_STATUS] = new_status;
env->pc = new_pc;
- cpu_loop_exit(env_cpu(env));
+ cpu_loop_exit(cs);
}
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index f0f5c6843a..827d957719 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -191,11 +191,24 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest)
static void gen_jumpr(DisasContext *dc, int regno, bool is_call)
{
- tcg_gen_mov_tl(cpu_pc, load_gpr(dc, regno));
+ TCGLabel *l = gen_new_label();
+ TCGv test = tcg_temp_new();
+ TCGv dest = load_gpr(dc, regno);
+
+ tcg_gen_andi_tl(test, dest, 3);
+ tcg_gen_brcondi_tl(TCG_COND_NE, test, 0, l);
+ tcg_temp_free(test);
+
+ tcg_gen_mov_tl(cpu_pc, dest);
if (is_call) {
tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next);
}
tcg_gen_lookup_and_goto_ptr();
+
+ gen_set_label(l);
+ tcg_gen_st_tl(dest, cpu_env, offsetof(CPUNios2State, ctrl[CR_BADADDR]));
+ t_gen_helper_raise_exception(dc, EXCP_UNALIGND);
+
dc->base.is_jmp = DISAS_NORETURN;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 53/64] target/nios2: Introduce shadow register sets
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (51 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 52/64] target/nios2: Implement Misaligned destination exception Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-22 13:21 ` Peter Maydell
2022-04-21 15:17 ` [PATCH v7 54/64] target/nios2: Implement rdprs, wrprs Richard Henderson
` (10 subsequent siblings)
63 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel
Do not actually enable them so far, in terms of being able
to change the current register set, but add all of the
plumbing to address them. Do not enable them for user-only.
Add an env->regs pointer that handles the indirection to
the current register set. The naming of the pointer hides
the difference between old and new, user-only and sysemu.
From the notes on wrprs, which states that r0 must be initialized
before use in shadow register sets, infer that R_ZERO is *not*
hardwired to zero in shadow register sets, but that it is still
read-only. Introduce tbflags bit R0_0 to track that it has been
properly set to zero. Adjust load_gpr to reflect this.
At the same time we might as well special case crs == 0 to avoid
the indirection through env->regs during translation as well; this
is intended to be the most common case for non-interrupt handlers.
Init env->regs at reset.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 29 ++++++++++++++++++-
target/nios2/cpu.c | 4 ++-
target/nios2/translate.c | 61 ++++++++++++++++++++++++++++++++++------
3 files changed, 83 insertions(+), 11 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 6417e9bbfc..08f0688628 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -60,6 +60,11 @@ struct Nios2CPUClass {
#define NUM_GP_REGS 32
#define NUM_CR_REGS 32
+#ifndef CONFIG_USER_ONLY
+/* 63 shadow register sets; index 0 is the primary register set. */
+#define NUM_REG_SETS 64
+#endif
+
/* General purpose register aliases */
enum {
R_ZERO = 0,
@@ -178,7 +183,13 @@ FIELD(CR_TLBMISC, EE, 24, 1)
#define EXCP_MPUD 17
struct CPUArchState {
+#ifdef CONFIG_USER_ONLY
uint32_t regs[NUM_GP_REGS];
+#else
+ uint32_t shadow_regs[NUM_REG_SETS][NUM_GP_REGS];
+ /* Pointer into shadow_regs for the current register set. */
+ uint32_t *regs;
+#endif
uint32_t ctrl[NUM_CR_REGS];
uint32_t pc;
@@ -229,6 +240,14 @@ static inline bool nios2_cr_reserved(const ControlRegState *s)
return (s->writable | s->readonly) == 0;
}
+static inline void nios2_update_crs(CPUNios2State *env)
+{
+#ifndef CONFIG_USER_ONLY
+ unsigned crs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS);
+ env->regs = env->shadow_regs[crs];
+#endif
+}
+
void nios2_tcg_init(void);
void nios2_cpu_do_interrupt(CPUState *cs);
void dump_mmu(CPUNios2State *env);
@@ -267,12 +286,20 @@ typedef Nios2CPU ArchCPU;
#include "exec/cpu-all.h"
+FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS == 0. */
+FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */
+FIELD(TBFLAGS, R0_0, 2, 1) /* Set if R0 == 0. */
+
static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
{
+ unsigned crs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS);
+
*pc = env->pc;
*cs_base = 0;
- *flags = env->ctrl[CR_STATUS] & CR_STATUS_U;
+ *flags = (env->ctrl[CR_STATUS] & CR_STATUS_U)
+ | (crs ? 0 : R_TBFLAGS_CRS0_MASK)
+ | (env->regs[0] ? 0 : R_TBFLAGS_R0_0_MASK);
}
#endif /* NIOS2_CPU_H */
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 54e7071907..d043c02fcd 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -48,15 +48,17 @@ static void nios2_cpu_reset(DeviceState *dev)
ncc->parent_reset(dev);
- memset(env->regs, 0, sizeof(env->regs));
memset(env->ctrl, 0, sizeof(env->ctrl));
env->pc = cpu->reset_addr;
#if defined(CONFIG_USER_ONLY)
/* Start in user mode with interrupts enabled. */
env->ctrl[CR_STATUS] = CR_STATUS_RSIE | CR_STATUS_U | CR_STATUS_PIE;
+ memset(env->regs, 0, sizeof(env->regs));
#else
env->ctrl[CR_STATUS] = CR_STATUS_RSIE;
+ nios2_update_crs(env);
+ memset(env->shadow_regs, 0, sizeof(env->shadow_regs));
#endif
}
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 827d957719..a6f5d39f4a 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -121,12 +121,16 @@ typedef struct DisasContext {
DisasContextBase base;
target_ulong pc;
int mem_idx;
+ uint32_t tb_flags;
TCGv sink;
const ControlRegState *cr_state;
} DisasContext;
static TCGv cpu_R[NUM_GP_REGS];
static TCGv cpu_pc;
+#ifndef CONFIG_USER_ONLY
+static TCGv cpu_crs_R[NUM_GP_REGS];
+#endif
typedef struct Nios2Instruction {
void (*handler)(DisasContext *dc, uint32_t code, uint32_t flags);
@@ -148,22 +152,47 @@ static uint8_t get_opxcode(uint32_t code)
static TCGv load_gpr(DisasContext *dc, unsigned reg)
{
assert(reg < NUM_GP_REGS);
- if (unlikely(reg == R_ZERO)) {
+
+ /*
+ * With shadow register sets, register r0 does not necessarily contain 0,
+ * but it is overwhelmingly likely that it does -- software is supposed
+ * to have set r0 to 0 in every shadow register set before use.
+ */
+ if (unlikely(reg == R_ZERO) && FIELD_EX32(dc->tb_flags, TBFLAGS, R0_0)) {
return tcg_constant_tl(0);
}
- return cpu_R[reg];
+ if (FIELD_EX32(dc->tb_flags, TBFLAGS, CRS0)) {
+ return cpu_R[reg];
+ }
+#ifdef CONFIG_USER_ONLY
+ g_assert_not_reached();
+#else
+ return cpu_crs_R[reg];
+#endif
}
static TCGv dest_gpr(DisasContext *dc, unsigned reg)
{
assert(reg < NUM_GP_REGS);
+
+ /*
+ * The spec for shadow register sets isn't clear, but we assume that
+ * writes to r0 are discarded regardless of CRS.
+ */
if (unlikely(reg == R_ZERO)) {
if (dc->sink == NULL) {
dc->sink = tcg_temp_new();
}
return dc->sink;
}
- return cpu_R[reg];
+ if (FIELD_EX32(dc->tb_flags, TBFLAGS, CRS0)) {
+ return cpu_R[reg];
+ }
+#ifdef CONFIG_USER_ONLY
+ g_assert_not_reached();
+#else
+ return cpu_crs_R[reg];
+#endif
}
static void t_gen_helper_raise_exception(DisasContext *dc,
@@ -219,7 +248,7 @@ static void gen_excp(DisasContext *dc, uint32_t code, uint32_t flags)
static bool gen_check_supervisor(DisasContext *dc)
{
- if (dc->base.tb->flags & CR_STATUS_U) {
+ if (FIELD_EX32(dc->tb_flags, TBFLAGS, U)) {
/* CPU in user mode, privileged instruction called, stop. */
t_gen_helper_raise_exception(dc, EXCP_SUPERI);
return false;
@@ -330,7 +359,7 @@ static void do_i_math_logic(DisasContext *dc, uint32_t insn,
val = imm(&instr);
- if (instr.a == R_ZERO) {
+ if (instr.a == R_ZERO && FIELD_EX32(dc->tb_flags, TBFLAGS, R0_0)) {
/* This catches the canonical expansions of movi and movhi. */
tcg_gen_movi_tl(dest_gpr(dc, instr.b), x_op_0_eq_x ? val : 0);
} else {
@@ -864,6 +893,7 @@ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
dc->mem_idx = cpu_mmu_index(env, false);
dc->cr_state = cpu->cr_state;
+ dc->tb_flags = dc->base.tb->flags;
/* Bound the number of insns to execute to those left on the page. */
page_insns = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
@@ -998,13 +1028,26 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
void nios2_tcg_init(void)
{
- int i;
+#ifndef CONFIG_USER_ONLY
+ TCGv_ptr crs = tcg_global_mem_new_ptr(cpu_env,
+ offsetof(CPUNios2State, regs), "crs");
- for (i = 0; i < NUM_GP_REGS; i++) {
- cpu_R[i] = tcg_global_mem_new(cpu_env,
- offsetof(CPUNios2State, regs[i]),
+ for (int i = 0; i < NUM_GP_REGS; i++) {
+ cpu_crs_R[i] = tcg_global_mem_new(crs, 4 * i, gr_regnames[i]);
+ }
+
+#define offsetof_regs0(N) offsetof(CPUNios2State, shadow_regs[0][N])
+#else
+#define offsetof_regs0(N) offsetof(CPUNios2State, regs[N])
+#endif
+
+ for (int i = 0; i < NUM_GP_REGS; i++) {
+ cpu_R[i] = tcg_global_mem_new(cpu_env, offsetof_regs0(i),
gr_regnames[i]);
}
+
+#undef offsetof_regs0
+
cpu_pc = tcg_global_mem_new(cpu_env,
offsetof(CPUNios2State, pc), "pc");
}
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* Re: [PATCH v7 53/64] target/nios2: Introduce shadow register sets
2022-04-21 15:17 ` [PATCH v7 53/64] target/nios2: Introduce shadow register sets Richard Henderson
@ 2022-04-22 13:21 ` Peter Maydell
0 siblings, 0 replies; 78+ messages in thread
From: Peter Maydell @ 2022-04-22 13:21 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Thu, 21 Apr 2022 at 17:42, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Do not actually enable them so far, in terms of being able
> to change the current register set, but add all of the
> plumbing to address them. Do not enable them for user-only.
>
> Add an env->regs pointer that handles the indirection to
> the current register set. The naming of the pointer hides
> the difference between old and new, user-only and sysemu.
>
> From the notes on wrprs, which states that r0 must be initialized
> before use in shadow register sets, infer that R_ZERO is *not*
> hardwired to zero in shadow register sets, but that it is still
> read-only. Introduce tbflags bit R0_0 to track that it has been
> properly set to zero. Adjust load_gpr to reflect this.
>
> At the same time we might as well special case crs == 0 to avoid
> the indirection through env->regs during translation as well; this
> is intended to be the most common case for non-interrupt handlers.
>
> Init env->regs at reset.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH v7 54/64] target/nios2: Implement rdprs, wrprs
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (52 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 53/64] target/nios2: Introduce shadow register sets Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 55/64] target/nios2: Update helper_eret for shadow registers Richard Henderson
` (9 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Implement these out of line, so that tcg global temps
(aka the architectural registers) are synced back to
tcg storage as required. This makes sure that we get
the proper results when status.PRS == status.CRS.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 1 +
target/nios2/helper.h | 2 ++
target/nios2/op_helper.c | 16 +++++++++++
target/nios2/translate.c | 57 ++++++++++++++++++++++++++++++++++++++--
4 files changed, 74 insertions(+), 2 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 08f0688628..d4d97a159e 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -220,6 +220,7 @@ struct ArchCPU {
bool diverr_present;
bool mmu_present;
+ bool eic_present;
uint32_t pid_num_bits;
uint32_t tlb_num_ways;
diff --git a/target/nios2/helper.h b/target/nios2/helper.h
index 6f5ec60b0d..1648d76ade 100644
--- a/target/nios2/helper.h
+++ b/target/nios2/helper.h
@@ -24,6 +24,8 @@ DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32)
#if !defined(CONFIG_USER_ONLY)
DEF_HELPER_3(eret, noreturn, env, i32, i32)
+DEF_HELPER_FLAGS_2(rdprs, TCG_CALL_NO_WG, i32, env, i32)
+DEF_HELPER_3(wrprs, void, env, i32, i32)
DEF_HELPER_2(mmu_write_tlbacc, void, env, i32)
DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32)
DEF_HELPER_2(mmu_write_pteaddr, void, env, i32)
diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
index 38a71a1f2d..a3164f5356 100644
--- a/target/nios2/op_helper.c
+++ b/target/nios2/op_helper.c
@@ -83,4 +83,20 @@ void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc)
env->pc = new_pc;
cpu_loop_exit(cs);
}
+
+/*
+ * RDPRS and WRPRS are implemented out of line so that if PRS == CRS,
+ * all of the tcg global temporaries are synced back to ENV.
+ */
+uint32_t helper_rdprs(CPUNios2State *env, uint32_t regno)
+{
+ unsigned prs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, PRS);
+ return env->shadow_regs[prs][regno];
+}
+
+void helper_wrprs(CPUNios2State *env, uint32_t regno, uint32_t val)
+{
+ unsigned prs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, PRS);
+ env->shadow_regs[prs][regno] = val;
+}
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index a6f5d39f4a..fdcc2154f2 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -124,6 +124,7 @@ typedef struct DisasContext {
uint32_t tb_flags;
TCGv sink;
const ControlRegState *cr_state;
+ bool eic_present;
} DisasContext;
static TCGv cpu_R[NUM_GP_REGS];
@@ -382,6 +383,27 @@ gen_i_math_logic(andhi, andi, 0, imm_shifted)
gen_i_math_logic(orhi , ori, 1, imm_shifted)
gen_i_math_logic(xorhi, xori, 1, imm_shifted)
+/* rB <- prs.rA + sigma(IMM16) */
+static void rdprs(DisasContext *dc, uint32_t code, uint32_t flags)
+{
+ if (!dc->eic_present) {
+ t_gen_helper_raise_exception(dc, EXCP_ILLEGAL);
+ return;
+ }
+ if (!gen_check_supervisor(dc)) {
+ return;
+ }
+
+#ifdef CONFIG_USER_ONLY
+ g_assert_not_reached();
+#else
+ I_TYPE(instr, code);
+ TCGv dest = dest_gpr(dc, instr.b);
+ gen_helper_rdprs(dest, cpu_env, tcg_constant_i32(instr.a));
+ tcg_gen_addi_tl(dest, dest, instr.imm16.s);
+#endif
+}
+
/* Prototype only, defined below */
static void handle_r_type_instr(DisasContext *dc, uint32_t code,
uint32_t flags);
@@ -443,7 +465,7 @@ static const Nios2Instruction i_type_instructions[] = {
INSTRUCTION_FLG(gen_stx, MO_SL), /* stwio */
INSTRUCTION_FLG(gen_bxx, TCG_COND_LTU), /* bltu */
INSTRUCTION_FLG(gen_ldx, MO_UL), /* ldwio */
- INSTRUCTION_UNIMPLEMENTED(), /* rdprs */
+ INSTRUCTION(rdprs), /* rdprs */
INSTRUCTION_ILLEGAL(),
INSTRUCTION_FLG(handle_r_type_instr, 0), /* R-Type */
INSTRUCTION_NOP(), /* flushd */
@@ -643,6 +665,36 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
#endif
}
+/* prs.rC <- rA */
+static void wrprs(DisasContext *dc, uint32_t code, uint32_t flags)
+{
+ if (!dc->eic_present) {
+ t_gen_helper_raise_exception(dc, EXCP_ILLEGAL);
+ return;
+ }
+ if (!gen_check_supervisor(dc)) {
+ return;
+ }
+
+#ifdef CONFIG_USER_ONLY
+ g_assert_not_reached();
+#else
+ R_TYPE(instr, code);
+ gen_helper_wrprs(cpu_env, tcg_constant_i32(instr.c),
+ load_gpr(dc, instr.a));
+ /*
+ * The expected write to PRS[r0] is 0, from CRS[r0].
+ * If not, and CRS == PRS (which we cannot tell from here),
+ * we may now have a non-zero value in our current r0.
+ * By ending the TB, we re-evaluate tb_flags and find out.
+ */
+ if (instr.c == 0
+ && (instr.a != 0 || !FIELD_EX32(dc->tb_flags, TBFLAGS, R0_0))) {
+ dc->base.is_jmp = DISAS_UPDATE;
+ }
+#endif
+}
+
/* Comparison instructions */
static void gen_cmpxx(DisasContext *dc, uint32_t code, uint32_t flags)
{
@@ -792,7 +844,7 @@ static const Nios2Instruction r_type_instructions[] = {
INSTRUCTION_ILLEGAL(),
INSTRUCTION(slli), /* slli */
INSTRUCTION(sll), /* sll */
- INSTRUCTION_UNIMPLEMENTED(), /* wrprs */
+ INSTRUCTION(wrprs), /* wrprs */
INSTRUCTION_ILLEGAL(),
INSTRUCTION(or), /* or */
INSTRUCTION(mulxsu), /* mulxsu */
@@ -894,6 +946,7 @@ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
dc->mem_idx = cpu_mmu_index(env, false);
dc->cr_state = cpu->cr_state;
dc->tb_flags = dc->base.tb->flags;
+ dc->eic_present = cpu->eic_present;
/* Bound the number of insns to execute to those left on the page. */
page_insns = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 55/64] target/nios2: Update helper_eret for shadow registers
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (53 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 54/64] target/nios2: Implement rdprs, wrprs Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 56/64] target/nios2: Implement EIC interrupt processing Richard Henderson
` (8 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
When CRS = 0, we restore from estatus; otherwise from sstatus.
Update for the new CRS.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 1 +
target/nios2/op_helper.c | 10 +++++++---
target/nios2/translate.c | 13 ++++++++-----
3 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index d4d97a159e..c2fedead54 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -82,6 +82,7 @@ enum {
R_FP = 28,
R_EA = 29,
R_BA = 30,
+ R_SSTATUS = 30,
R_RA = 31,
};
diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
index a3164f5356..94040102f4 100644
--- a/target/nios2/op_helper.c
+++ b/target/nios2/op_helper.c
@@ -73,14 +73,18 @@ void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc)
}
/*
- * Both estatus and bstatus have no constraints on write;
+ * None of estatus, bstatus, or sstatus have constraints on write;
* do not allow reserved fields in status to be set.
- * TODO: more than this is required for shadow registers.
+ * When shadow registers are enabled, eret *does* restore CRS.
+ * Rather than testing eic_present to decide, mask CRS out of
+ * the set of readonly fields.
*/
- new_status &= cpu->cr_state[CR_STATUS].writable;
+ new_status &= cpu->cr_state[CR_STATUS].writable |
+ (cpu->cr_state[CR_STATUS].readonly & R_CR_STATUS_CRS_MASK);
env->ctrl[CR_STATUS] = new_status;
env->pc = new_pc;
+ nios2_update_crs(env);
cpu_loop_exit(cs);
}
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index fdcc2154f2..29cb610aca 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -491,11 +491,14 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
#ifdef CONFIG_USER_ONLY
g_assert_not_reached();
#else
- TCGv tmp = tcg_temp_new();
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS]));
- gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA));
- tcg_temp_free(tmp);
-
+ if (FIELD_EX32(dc->tb_flags, TBFLAGS, CRS0)) {
+ TCGv tmp = tcg_temp_new();
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS]));
+ gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA));
+ tcg_temp_free(tmp);
+ } else {
+ gen_helper_eret(cpu_env, load_gpr(dc, R_SSTATUS), load_gpr(dc, R_EA));
+ }
dc->base.is_jmp = DISAS_NORETURN;
#endif
}
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 56/64] target/nios2: Implement EIC interrupt processing
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (54 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 55/64] target/nios2: Update helper_eret for shadow registers Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-22 13:24 ` Peter Maydell
2022-04-21 15:17 ` [PATCH v7 57/64] target/nios2: Advance pc when raising exceptions Richard Henderson
` (7 subsequent siblings)
63 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel
This is the cpu side of the operation. Register one irq line,
called EIC. Split out the rather different processing to a
separate function.
Delay initialization of gpio irqs until realize. We need to
provide a window after init in which the board can set eic_present.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 8 ++++
target/nios2/cpu.c | 92 +++++++++++++++++++++++++++++++++----------
target/nios2/helper.c | 51 +++++++++++++++++++++++-
3 files changed, 129 insertions(+), 22 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index c2fedead54..e25d3cdb11 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -114,6 +114,7 @@ FIELD(CR_STATUS, CRS, 10, 6)
FIELD(CR_STATUS, PRS, 16, 6)
FIELD(CR_STATUS, NMI, 22, 1)
FIELD(CR_STATUS, RSIE, 23, 1)
+FIELD(CR_STATUS, SRS, 31, 1) /* only in sstatus */
#define CR_STATUS_PIE R_CR_STATUS_PIE_MASK
#define CR_STATUS_U R_CR_STATUS_U_MASK
@@ -121,6 +122,7 @@ FIELD(CR_STATUS, RSIE, 23, 1)
#define CR_STATUS_IH R_CR_STATUS_IH_MASK
#define CR_STATUS_NMI R_CR_STATUS_NMI_MASK
#define CR_STATUS_RSIE R_CR_STATUS_RSIE_MASK
+#define CR_STATUS_SRS R_CR_STATUS_SRS_MASK
FIELD(CR_EXCEPTION, CAUSE, 2, 5)
FIELD(CR_EXCEPTION, ECCFTL, 31, 1)
@@ -234,6 +236,12 @@ struct ArchCPU {
/* Bits within each control register which are reserved or readonly. */
ControlRegState cr_state[NUM_CR_REGS];
+
+ /* External Interrupt Controller Interface */
+ uint32_t rha; /* Requested handler address */
+ uint32_t ril; /* Requested interrupt level */
+ uint32_t rrs; /* Requested register set */
+ bool rnmi; /* Requested nonmaskable interrupt */
};
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index d043c02fcd..19b2409974 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -63,7 +63,19 @@ static void nios2_cpu_reset(DeviceState *dev)
}
#ifndef CONFIG_USER_ONLY
-static void nios2_cpu_set_irq(void *opaque, int irq, int level)
+static void eic_set_irq(void *opaque, int irq, int level)
+{
+ Nios2CPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
+
+ if (level) {
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+}
+
+static void iic_set_irq(void *opaque, int irq, int level)
{
Nios2CPU *cpu = opaque;
CPUNios2State *env = &cpu->env;
@@ -87,15 +99,6 @@ static void nios2_cpu_initfn(Object *obj)
#if !defined(CONFIG_USER_ONLY)
mmu_init(&cpu->env);
-
- /*
- * These interrupt lines model the IIC (internal interrupt
- * controller). QEMU does not currently support the EIC
- * (external interrupt controller) -- if we did it would be
- * a separate device in hw/intc with a custom interface to
- * the CPU, and boards using it would not wire up these IRQ lines.
- */
- qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 32);
#endif
}
@@ -128,10 +131,18 @@ static void realize_cr_status(CPUState *cs)
RO_REG(CR_EXCEPTION);
WR_REG(CR_BADADDR);
- /* TODO: These control registers are not present with the EIC. */
- RO_FIELD(CR_STATUS, RSIE);
- WR_REG(CR_IENABLE);
- RO_REG(CR_IPENDING);
+ if (cpu->eic_present) {
+ WR_FIELD(CR_STATUS, RSIE);
+ RO_FIELD(CR_STATUS, NMI);
+ WR_FIELD(CR_STATUS, PRS);
+ RO_FIELD(CR_STATUS, CRS);
+ WR_FIELD(CR_STATUS, IL);
+ WR_FIELD(CR_STATUS, IH);
+ } else {
+ RO_FIELD(CR_STATUS, RSIE);
+ WR_REG(CR_IENABLE);
+ RO_REG(CR_IPENDING);
+ }
if (cpu->mmu_present) {
WR_FIELD(CR_STATUS, U);
@@ -170,6 +181,14 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev);
Error *local_err = NULL;
+#ifndef CONFIG_USER_ONLY
+ if (cpu->eic_present) {
+ qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1);
+ } else {
+ qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32);
+ }
+#endif
+
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
@@ -187,17 +206,48 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
}
#ifndef CONFIG_USER_ONLY
+static bool eic_take_interrupt(Nios2CPU *cpu)
+{
+ CPUNios2State *env = &cpu->env;
+ const uint32_t status = env->ctrl[CR_STATUS];
+
+ if (cpu->rnmi) {
+ return !(status & CR_STATUS_NMI);
+ }
+ if (!(status & CR_STATUS_PIE)) {
+ return false;
+ }
+ if (cpu->ril <= FIELD_EX32(status, CR_STATUS, IL)) {
+ return false;
+ }
+ if (cpu->rrs != FIELD_EX32(status, CR_STATUS, CRS)) {
+ return true;
+ }
+ return status & CR_STATUS_RSIE;
+}
+
+static bool iic_take_interrupt(Nios2CPU *cpu)
+{
+ CPUNios2State *env = &cpu->env;
+
+ if (!(env->ctrl[CR_STATUS] & CR_STATUS_PIE)) {
+ return false;
+ }
+ return env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE];
+}
+
static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
- CPUNios2State *env = &cpu->env;
- if ((interrupt_request & CPU_INTERRUPT_HARD) &&
- (env->ctrl[CR_STATUS] & CR_STATUS_PIE) &&
- (env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE])) {
- cs->exception_index = EXCP_IRQ;
- nios2_cpu_do_interrupt(cs);
- return true;
+ if (interrupt_request & CPU_INTERRUPT_HARD) {
+ if (cpu->eic_present
+ ? eic_take_interrupt(cpu)
+ : iic_take_interrupt(cpu)) {
+ cs->exception_index = EXCP_IRQ;
+ nios2_cpu_do_interrupt(cs);
+ return true;
+ }
}
return false;
}
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 2e9fea4a01..e256d1528e 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -37,6 +37,10 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr,
uint32_t old_status = env->ctrl[CR_STATUS];
uint32_t new_status = old_status;
+ /* With shadow regs, exceptions are always taken into CRS 0. */
+ new_status &= ~R_CR_STATUS_CRS_MASK;
+ env->regs = env->shadow_regs[0];
+
if ((old_status & CR_STATUS_EH) == 0) {
int r_ea = R_EA, cr_es = CR_ESTATUS;
@@ -60,6 +64,14 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr,
CR_TLBMISC_DBL);
env->ctrl[CR_TLBMISC] |= tlbmisc_set;
}
+
+ /*
+ * With shadow regs, and EH == 0, PRS is set from CRS.
+ * At least, so says Table 3-9, and some other text,
+ * though Table 3-38 says otherwise.
+ */
+ new_status = FIELD_DP32(new_status, CR_STATUS, PRS,
+ FIELD_EX32(old_status, CR_STATUS, CRS));
}
new_status &= ~(CR_STATUS_PIE | CR_STATUS_U);
@@ -77,6 +89,39 @@ static void do_iic_irq(Nios2CPU *cpu)
do_exception(cpu, cpu->exception_addr, 0, false);
}
+static void do_eic_irq(Nios2CPU *cpu)
+{
+ CPUNios2State *env = &cpu->env;
+ uint32_t old_status = env->ctrl[CR_STATUS];
+ uint32_t new_status = old_status;
+ uint32_t old_rs = FIELD_EX32(old_status, CR_STATUS, CRS);
+ uint32_t new_rs = cpu->rrs;
+
+ new_status = FIELD_DP32(new_status, CR_STATUS, CRS, new_rs);
+ new_status = FIELD_DP32(new_status, CR_STATUS, IL, cpu->ril);
+ new_status = FIELD_DP32(new_status, CR_STATUS, NMI, cpu->rnmi);
+ new_status &= ~(CR_STATUS_RSIE | CR_STATUS_U);
+ new_status |= CR_STATUS_IH;
+
+ if (!(new_status & CR_STATUS_EH)) {
+ new_status = FIELD_DP32(new_status, CR_STATUS, PRS, old_rs);
+ if (new_rs == 0) {
+ env->ctrl[CR_ESTATUS] = old_status;
+ } else {
+ if (new_rs != old_rs) {
+ old_status |= CR_STATUS_SRS;
+ }
+ env->shadow_regs[new_rs][R_SSTATUS] = old_status;
+ }
+ env->shadow_regs[new_rs][R_EA] = env->pc + 4;
+ }
+
+ env->ctrl[CR_STATUS] = new_status;
+ nios2_update_crs(env);
+
+ env->pc = cpu->rha;
+}
+
void nios2_cpu_do_interrupt(CPUState *cs)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
@@ -142,7 +187,11 @@ void nios2_cpu_do_interrupt(CPUState *cs)
switch (cs->exception_index) {
case EXCP_IRQ:
- do_iic_irq(cpu);
+ if (cpu->eic_present) {
+ do_eic_irq(cpu);
+ } else {
+ do_iic_irq(cpu);
+ }
break;
case EXCP_TLB_D:
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* Re: [PATCH v7 56/64] target/nios2: Implement EIC interrupt processing
2022-04-21 15:17 ` [PATCH v7 56/64] target/nios2: Implement EIC interrupt processing Richard Henderson
@ 2022-04-22 13:24 ` Peter Maydell
0 siblings, 0 replies; 78+ messages in thread
From: Peter Maydell @ 2022-04-22 13:24 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Thu, 21 Apr 2022 at 17:35, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This is the cpu side of the operation. Register one irq line,
> called EIC. Split out the rather different processing to a
> separate function.
>
> Delay initialization of gpio irqs until realize. We need to
> provide a window after init in which the board can set eic_present.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH v7 57/64] target/nios2: Advance pc when raising exceptions
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (55 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 56/64] target/nios2: Implement EIC interrupt processing Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-22 13:00 ` Peter Maydell
2022-04-21 15:17 ` [PATCH v7 58/64] linux-user/nios2: Handle various SIGILL exceptions Richard Henderson
` (6 subsequent siblings)
63 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel
The exception return address for nios2 is the instruction
after the one that was executing at the time of the exception.
We have so far implemented this by advancing the pc during the
process of raising the exception. It is perhaps a little less
confusing to do this advance in the translator (and helpers)
when raising the exception in the first place, so that we may
more closely match kernel sources.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 2 ++
linux-user/nios2/cpu_loop.c | 8 ++------
target/nios2/helper.c | 13 +++++++------
target/nios2/op_helper.c | 18 ++++++++++++++++--
target/nios2/translate.c | 6 +++---
5 files changed, 30 insertions(+), 17 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index e25d3cdb11..58d56e55f9 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -266,6 +266,8 @@ hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr) QEMU_NORETURN;
+void nios2_cpu_loop_exit_advance(CPUNios2State *env, uintptr_t retaddr)
+ QEMU_NORETURN;
void do_nios2_semihosting(CPUNios2State *env);
diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c
index 30a27f252b..a5e86990e2 100644
--- a/linux-user/nios2/cpu_loop.c
+++ b/linux-user/nios2/cpu_loop.c
@@ -39,6 +39,8 @@ void cpu_loop(CPUNios2State *env)
break;
case EXCP_DIV:
+ /* Match kernel's handle_diverror_c(). */
+ env->pc -= 4;
force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc);
break;
@@ -49,12 +51,6 @@ void cpu_loop(CPUNios2State *env)
break;
case EXCP_TRAP:
- /*
- * TODO: This advance should be done in the translator, as
- * hardware produces an advanced pc as part of all exceptions.
- */
- env->pc += 4;
-
switch (env->error_code) {
case 0:
qemu_log_mask(CPU_LOG_INT, "\nSyscall\n");
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index e256d1528e..bb3b09e5a7 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -49,7 +49,7 @@ static void do_exception(Nios2CPU *cpu, uint32_t exception_addr,
cr_es = CR_BSTATUS;
}
env->ctrl[cr_es] = old_status;
- env->regs[r_ea] = env->pc + 4;
+ env->regs[r_ea] = env->pc;
if (cpu->mmu_present) {
new_status |= CR_STATUS_EH;
@@ -113,7 +113,7 @@ static void do_eic_irq(Nios2CPU *cpu)
}
env->shadow_regs[new_rs][R_SSTATUS] = old_status;
}
- env->shadow_regs[new_rs][R_EA] = env->pc + 4;
+ env->shadow_regs[new_rs][R_EA] = env->pc;
}
env->ctrl[CR_STATUS] = new_status;
@@ -187,6 +187,8 @@ void nios2_cpu_do_interrupt(CPUState *cs)
switch (cs->exception_index) {
case EXCP_IRQ:
+ /* Note that PC is advanced for interrupts as well. */
+ env->pc += 4;
if (cpu->eic_present) {
do_eic_irq(cpu);
} else {
@@ -249,7 +251,6 @@ void nios2_cpu_do_interrupt(CPUState *cs)
break;
case EXCP_SEMIHOST:
- env->pc += 4;
do_nios2_semihosting(env);
break;
@@ -291,7 +292,7 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
env->ctrl[CR_BADADDR] = addr;
cs->exception_index = EXCP_UNALIGN;
- cpu_loop_exit_restore(cs, retaddr);
+ nios2_cpu_loop_exit_advance(env, retaddr);
}
bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
@@ -330,7 +331,7 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
cs->exception_index = (access_type == MMU_INST_FETCH
? EXCP_SUPERA_X : EXCP_SUPERA_D);
env->ctrl[CR_BADADDR] = address;
- cpu_loop_exit_restore(cs, retaddr);
+ nios2_cpu_loop_exit_advance(env, retaddr);
}
}
@@ -367,5 +368,5 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
cs->exception_index = excp;
env->ctrl[CR_BADADDR] = address;
- cpu_loop_exit_restore(cs, retaddr);
+ nios2_cpu_loop_exit_advance(env, retaddr);
}
diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
index 94040102f4..2e30d0a908 100644
--- a/target/nios2/op_helper.c
+++ b/target/nios2/op_helper.c
@@ -31,6 +31,20 @@ void helper_raise_exception(CPUNios2State *env, uint32_t index)
cpu_loop_exit(cs);
}
+void nios2_cpu_loop_exit_advance(CPUNios2State *env, uintptr_t retaddr)
+{
+ CPUState *cs = env_cpu(env);
+
+ /*
+ * Note that PC is advanced for all hardware exceptions.
+ * Do this here, rather than in restore_state_to_opc(),
+ * lest we affect QEMU internal exceptions, like EXCP_DEBUG.
+ */
+ cpu_restore_state(cs, retaddr, true);
+ env->pc += 4;
+ cpu_loop_exit(cs);
+}
+
static void maybe_raise_div(CPUNios2State *env, uintptr_t ra)
{
Nios2CPU *cpu = env_archcpu(env);
@@ -38,7 +52,7 @@ static void maybe_raise_div(CPUNios2State *env, uintptr_t ra)
if (cpu->diverr_present) {
cs->exception_index = EXCP_DIV;
- cpu_loop_exit_restore(cs, ra);
+ nios2_cpu_loop_exit_advance(env, ra);
}
}
@@ -69,7 +83,7 @@ void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc)
if (unlikely(new_pc & 3)) {
env->ctrl[CR_BADADDR] = new_pc;
cs->exception_index = EXCP_UNALIGND;
- cpu_loop_exit_restore(cs, GETPC());
+ nios2_cpu_loop_exit_advance(env, GETPC());
}
/*
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 29cb610aca..c06e9e7b14 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -196,10 +196,10 @@ static TCGv dest_gpr(DisasContext *dc, unsigned reg)
#endif
}
-static void t_gen_helper_raise_exception(DisasContext *dc,
- uint32_t index)
+static void t_gen_helper_raise_exception(DisasContext *dc, uint32_t index)
{
- tcg_gen_movi_tl(cpu_pc, dc->pc);
+ /* Note that PC is advanced for all hardware exceptions. */
+ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
gen_helper_raise_exception(cpu_env, tcg_constant_i32(index));
dc->base.is_jmp = DISAS_NORETURN;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* Re: [PATCH v7 57/64] target/nios2: Advance pc when raising exceptions
2022-04-21 15:17 ` [PATCH v7 57/64] target/nios2: Advance pc when raising exceptions Richard Henderson
@ 2022-04-22 13:00 ` Peter Maydell
0 siblings, 0 replies; 78+ messages in thread
From: Peter Maydell @ 2022-04-22 13:00 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Thu, 21 Apr 2022 at 17:51, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The exception return address for nios2 is the instruction
> after the one that was executing at the time of the exception.
>
> We have so far implemented this by advancing the pc during the
> process of raising the exception. It is perhaps a little less
> confusing to do this advance in the translator (and helpers)
> when raising the exception in the first place, so that we may
> more closely match kernel sources.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH v7 58/64] linux-user/nios2: Handle various SIGILL exceptions
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (56 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 57/64] target/nios2: Advance pc when raising exceptions Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 59/64] hw/intc: Vectored Interrupt Controller (VIC) Richard Henderson
` (5 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
We missed out on a couple of exception types that may
legitimately be raised by a userland program.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/nios2/cpu_loop.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c
index a5e86990e2..da77ede76b 100644
--- a/linux-user/nios2/cpu_loop.c
+++ b/linux-user/nios2/cpu_loop.c
@@ -50,6 +50,18 @@ void cpu_loop(CPUNios2State *env)
env->ctrl[CR_BADADDR]);
break;
+ case EXCP_ILLEGAL:
+ case EXCP_UNIMPL:
+ /* Match kernel's handle_illegal_c(). */
+ env->pc -= 4;
+ force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->pc);
+ break;
+ case EXCP_SUPERI:
+ /* Match kernel's handle_supervisor_instr(). */
+ env->pc -= 4;
+ force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->pc);
+ break;
+
case EXCP_TRAP:
switch (env->error_code) {
case 0:
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 59/64] hw/intc: Vectored Interrupt Controller (VIC)
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (57 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 58/64] linux-user/nios2: Handle various SIGILL exceptions Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 60/64] hw/nios2: Introduce Nios2MachineState Richard Henderson
` (4 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Amir Gonnen
From: Amir Gonnen <amir.gonnen@neuroblade.ai>
Implement nios2 Vectored Interrupt Controller (VIC).
VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi
fields on Nios2CPU before raising an IRQ.
For that purpose, VIC has a "cpu" property which should refer to the
nios2 cpu and set by the board that connects VIC.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Amir Gonnen <amir.gonnen@neuroblade.ai>
Message-Id: <20220303153906.2024748-5-amir.gonnen@neuroblade.ai>
[rth: Split out nios2_vic.h]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/intc/nios2_vic.h | 64 ++++++++
hw/intc/nios2_vic.c | 313 ++++++++++++++++++++++++++++++++++++
hw/intc/Kconfig | 3 +
hw/intc/meson.build | 1 +
4 files changed, 381 insertions(+)
create mode 100644 include/hw/intc/nios2_vic.h
create mode 100644 hw/intc/nios2_vic.c
diff --git a/include/hw/intc/nios2_vic.h b/include/hw/intc/nios2_vic.h
new file mode 100644
index 0000000000..af1517a967
--- /dev/null
+++ b/include/hw/intc/nios2_vic.h
@@ -0,0 +1,64 @@
+/*
+ * Vectored Interrupt Controller for nios2 processor
+ *
+ * Copyright (c) 2022 Neuroblade
+ *
+ * Interface:
+ * QOM property "cpu": link to the Nios2 CPU (must be set)
+ * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines
+ * IRQ should be connected to nios2 IRQ0.
+ *
+ * Reference: "Embedded Peripherals IP User Guide
+ * for Intel® Quartus® Prime Design Suite: 21.4"
+ * Chapter 38 "Vectored Interrupt Controller Core"
+ * See: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/vectored-interrupt-controller-core.html
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_INTC_NIOS2_VIC
+#define HW_INTC_NIOS2_VIC
+
+#define TYPE_NIOS2_VIC "nios2-vic"
+OBJECT_DECLARE_SIMPLE_TYPE(Nios2VIC, NIOS2_VIC)
+
+#define NIOS2_VIC_MAX_IRQ 32
+
+struct Nios2VIC {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ qemu_irq output_int;
+
+ /* properties */
+ CPUState *cpu;
+ MemoryRegion csr;
+
+ uint32_t int_config[NIOS2_VIC_MAX_IRQ];
+ uint32_t vic_config;
+ uint32_t int_raw_status;
+ uint32_t int_enable;
+ uint32_t sw_int;
+ uint32_t vic_status;
+ uint32_t vec_tbl_base;
+ uint32_t vec_tbl_addr;
+};
+
+#endif /* HW_INTC_NIOS2_VIC */
diff --git a/hw/intc/nios2_vic.c b/hw/intc/nios2_vic.c
new file mode 100644
index 0000000000..cf63212a88
--- /dev/null
+++ b/hw/intc/nios2_vic.c
@@ -0,0 +1,313 @@
+/*
+ * Vectored Interrupt Controller for nios2 processor
+ *
+ * Copyright (c) 2022 Neuroblade
+ *
+ * Interface:
+ * QOM property "cpu": link to the Nios2 CPU (must be set)
+ * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines
+ * IRQ should be connected to nios2 IRQ0.
+ *
+ * Reference: "Embedded Peripherals IP User Guide
+ * for Intel® Quartus® Prime Design Suite: 21.4"
+ * Chapter 38 "Vectored Interrupt Controller Core"
+ * See: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/vectored-interrupt-controller-core.html
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qapi/error.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qom/object.h"
+#include "hw/intc/nios2_vic.h"
+#include "cpu.h"
+
+
+enum {
+ INT_CONFIG0 = 0,
+ INT_CONFIG31 = 31,
+ INT_ENABLE = 32,
+ INT_ENABLE_SET = 33,
+ INT_ENABLE_CLR = 34,
+ INT_PENDING = 35,
+ INT_RAW_STATUS = 36,
+ SW_INTERRUPT = 37,
+ SW_INTERRUPT_SET = 38,
+ SW_INTERRUPT_CLR = 39,
+ VIC_CONFIG = 40,
+ VIC_STATUS = 41,
+ VEC_TBL_BASE = 42,
+ VEC_TBL_ADDR = 43,
+ CSR_COUNT /* Last! */
+};
+
+/* Requested interrupt level (INT_CONFIG[0:5]) */
+static inline uint32_t vic_int_config_ril(const Nios2VIC *vic, int irq_num)
+{
+ return extract32(vic->int_config[irq_num], 0, 6);
+}
+
+/* Requested NMI (INT_CONFIG[6]) */
+static inline uint32_t vic_int_config_rnmi(const Nios2VIC *vic, int irq_num)
+{
+ return extract32(vic->int_config[irq_num], 6, 1);
+}
+
+/* Requested register set (INT_CONFIG[7:12]) */
+static inline uint32_t vic_int_config_rrs(const Nios2VIC *vic, int irq_num)
+{
+ return extract32(vic->int_config[irq_num], 7, 6);
+}
+
+static inline uint32_t vic_config_vec_size(const Nios2VIC *vic)
+{
+ return 1 << (2 + extract32(vic->vic_config, 0, 3));
+}
+
+static inline uint32_t vic_int_pending(const Nios2VIC *vic)
+{
+ return (vic->int_raw_status | vic->sw_int) & vic->int_enable;
+}
+
+static void vic_update_irq(Nios2VIC *vic)
+{
+ Nios2CPU *cpu = NIOS2_CPU(vic->cpu);
+ uint32_t pending = vic_int_pending(vic);
+ int irq = -1;
+ int max_ril = 0;
+ /* Note that if RIL is 0 for an interrupt it is effectively disabled */
+
+ vic->vec_tbl_addr = 0;
+ vic->vic_status = 0;
+
+ if (pending == 0) {
+ qemu_irq_lower(vic->output_int);
+ return;
+ }
+
+ for (int i = 0; i < NIOS2_VIC_MAX_IRQ; i++) {
+ if (pending & BIT(i)) {
+ int ril = vic_int_config_ril(vic, i);
+ if (ril > max_ril) {
+ irq = i;
+ max_ril = ril;
+ }
+ }
+ }
+
+ if (irq < 0) {
+ qemu_irq_lower(vic->output_int);
+ return;
+ }
+
+ vic->vec_tbl_addr = irq * vic_config_vec_size(vic) + vic->vec_tbl_base;
+ vic->vic_status = irq | BIT(31);
+
+ /*
+ * In hardware, the interface between the VIC and the CPU is via the
+ * External Interrupt Controller interface, where the interrupt controller
+ * presents the CPU with a packet of data containing:
+ * - Requested Handler Address (RHA): 32 bits
+ * - Requested Register Set (RRS) : 6 bits
+ * - Requested Interrupt Level (RIL) : 6 bits
+ * - Requested NMI flag (RNMI) : 1 bit
+ * In our emulation, we implement this by writing the data directly to
+ * fields in the CPU object and then raising the IRQ line to tell
+ * the CPU that we've done so.
+ */
+
+ cpu->rha = vic->vec_tbl_addr;
+ cpu->ril = max_ril;
+ cpu->rrs = vic_int_config_rrs(vic, irq);
+ cpu->rnmi = vic_int_config_rnmi(vic, irq);
+
+ qemu_irq_raise(vic->output_int);
+}
+
+static void vic_set_irq(void *opaque, int irq_num, int level)
+{
+ Nios2VIC *vic = opaque;
+
+ vic->int_raw_status = deposit32(vic->int_raw_status, irq_num, 1, !!level);
+ vic_update_irq(vic);
+}
+
+static void nios2_vic_reset(DeviceState *dev)
+{
+ Nios2VIC *vic = NIOS2_VIC(dev);
+
+ memset(&vic->int_config, 0, sizeof(vic->int_config));
+ vic->vic_config = 0;
+ vic->int_raw_status = 0;
+ vic->int_enable = 0;
+ vic->sw_int = 0;
+ vic->vic_status = 0;
+ vic->vec_tbl_base = 0;
+ vic->vec_tbl_addr = 0;
+}
+
+static uint64_t nios2_vic_csr_read(void *opaque, hwaddr offset, unsigned size)
+{
+ Nios2VIC *vic = opaque;
+ int index = offset / 4;
+
+ switch (index) {
+ case INT_CONFIG0 ... INT_CONFIG31:
+ return vic->int_config[index - INT_CONFIG0];
+ case INT_ENABLE:
+ return vic->int_enable;
+ case INT_PENDING:
+ return vic_int_pending(vic);
+ case INT_RAW_STATUS:
+ return vic->int_raw_status;
+ case SW_INTERRUPT:
+ return vic->sw_int;
+ case VIC_CONFIG:
+ return vic->vic_config;
+ case VIC_STATUS:
+ return vic->vic_status;
+ case VEC_TBL_BASE:
+ return vic->vec_tbl_base;
+ case VEC_TBL_ADDR:
+ return vic->vec_tbl_addr;
+ default:
+ return 0;
+ }
+}
+
+static void nios2_vic_csr_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+ Nios2VIC *vic = opaque;
+ int index = offset / 4;
+
+ switch (index) {
+ case INT_CONFIG0 ... INT_CONFIG31:
+ vic->int_config[index - INT_CONFIG0] = value;
+ break;
+ case INT_ENABLE:
+ vic->int_enable = value;
+ break;
+ case INT_ENABLE_SET:
+ vic->int_enable |= value;
+ break;
+ case INT_ENABLE_CLR:
+ vic->int_enable &= ~value;
+ break;
+ case SW_INTERRUPT:
+ vic->sw_int = value;
+ break;
+ case SW_INTERRUPT_SET:
+ vic->sw_int |= value;
+ break;
+ case SW_INTERRUPT_CLR:
+ vic->sw_int &= ~value;
+ break;
+ case VIC_CONFIG:
+ vic->vic_config = value;
+ break;
+ case VEC_TBL_BASE:
+ vic->vec_tbl_base = value;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "nios2-vic: write to invalid CSR address %#"
+ HWADDR_PRIx "\n", offset);
+ }
+
+ vic_update_irq(vic);
+}
+
+static const MemoryRegionOps nios2_vic_csr_ops = {
+ .read = nios2_vic_csr_read,
+ .write = nios2_vic_csr_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = { .min_access_size = 4, .max_access_size = 4 }
+};
+
+static void nios2_vic_realize(DeviceState *dev, Error **errp)
+{
+ Nios2VIC *vic = NIOS2_VIC(dev);
+
+ if (!vic->cpu) {
+ /* This is a programming error in the code using this device */
+ error_setg(errp, "nios2-vic 'cpu' link property was not set");
+ return;
+ }
+
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &vic->output_int);
+ qdev_init_gpio_in(dev, vic_set_irq, NIOS2_VIC_MAX_IRQ);
+
+ memory_region_init_io(&vic->csr, OBJECT(dev), &nios2_vic_csr_ops, vic,
+ "nios2.vic.csr", CSR_COUNT * sizeof(uint32_t));
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &vic->csr);
+}
+
+static Property nios2_vic_properties[] = {
+ DEFINE_PROP_LINK("cpu", Nios2VIC, cpu, TYPE_CPU, CPUState *),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static const VMStateDescription nios2_vic_vmstate = {
+ .name = "nios2-vic",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]){
+ VMSTATE_UINT32_ARRAY(int_config, Nios2VIC, 32),
+ VMSTATE_UINT32(vic_config, Nios2VIC),
+ VMSTATE_UINT32(int_raw_status, Nios2VIC),
+ VMSTATE_UINT32(int_enable, Nios2VIC),
+ VMSTATE_UINT32(sw_int, Nios2VIC),
+ VMSTATE_UINT32(vic_status, Nios2VIC),
+ VMSTATE_UINT32(vec_tbl_base, Nios2VIC),
+ VMSTATE_UINT32(vec_tbl_addr, Nios2VIC),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+static void nios2_vic_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = nios2_vic_reset;
+ dc->realize = nios2_vic_realize;
+ dc->vmsd = &nios2_vic_vmstate;
+ device_class_set_props(dc, nios2_vic_properties);
+}
+
+static const TypeInfo nios2_vic_info = {
+ .name = TYPE_NIOS2_VIC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Nios2VIC),
+ .class_init = nios2_vic_class_init,
+};
+
+static void nios2_vic_register_types(void)
+{
+ type_register_static(&nios2_vic_info);
+}
+
+type_init(nios2_vic_register_types);
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index a7cf301eab..eded1b557e 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -84,3 +84,6 @@ config GOLDFISH_PIC
config M68K_IRQC
bool
+
+config NIOS2_VIC
+ bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index d6d012fb26..8b35139f82 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -62,3 +62,4 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
if_true: files('spapr_xive_kvm.c'))
specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.c'))
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
+specific_ss.add(when: 'CONFIG_NIOS2_VIC', if_true: files('nios2_vic.c'))
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 60/64] hw/nios2: Introduce Nios2MachineState
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (58 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 59/64] hw/intc: Vectored Interrupt Controller (VIC) Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 61/64] hw/nios2: Move memory regions into Nios2Machine Richard Henderson
` (3 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Mark Cave-Ayland
We want to move data from the heap into Nios2MachineState,
which is not possible with DEFINE_MACHINE.
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/nios2/10m50_devboard.c | 24 ++++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c
index 3d1205b8bd..bdc3ffd50d 100644
--- a/hw/nios2/10m50_devboard.c
+++ b/hw/nios2/10m50_devboard.c
@@ -36,6 +36,13 @@
#include "boot.h"
+struct Nios2MachineState {
+ MachineState parent_obj;
+};
+
+#define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd")
+OBJECT_DECLARE_TYPE(Nios2MachineState, MachineClass, NIOS2_MACHINE)
+
#define BINARY_DEVICE_TREE_FILE "10m50-devboard.dtb"
static void nios2_10m50_ghrd_init(MachineState *machine)
@@ -105,11 +112,24 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
BINARY_DEVICE_TREE_FILE, NULL);
}
-static void nios2_10m50_ghrd_machine_init(struct MachineClass *mc)
+static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data)
{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
mc->desc = "Altera 10M50 GHRD Nios II design";
mc->init = nios2_10m50_ghrd_init;
mc->is_default = true;
}
-DEFINE_MACHINE("10m50-ghrd", nios2_10m50_ghrd_machine_init);
+static const TypeInfo nios2_10m50_ghrd_type_info = {
+ .name = TYPE_NIOS2_MACHINE,
+ .parent = TYPE_MACHINE,
+ .instance_size = sizeof(Nios2MachineState),
+ .class_init = nios2_10m50_ghrd_class_init,
+};
+
+static void nios2_10m50_ghrd_type_init(void)
+{
+ type_register_static(&nios2_10m50_ghrd_type_info);
+}
+type_init(nios2_10m50_ghrd_type_init);
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 61/64] hw/nios2: Move memory regions into Nios2Machine
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (59 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 60/64] hw/nios2: Introduce Nios2MachineState Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 62/64] hw/nios2: Machine with a Vectored Interrupt Controller Richard Henderson
` (2 subsequent siblings)
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Mark Cave-Ayland
Convert to contiguous allocation, as much as possible so far.
The two timer objects are not exposed for subobject allocation.
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/nios2/10m50_devboard.c | 30 ++++++++++++++++--------------
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c
index bdc3ffd50d..dda4ab2bf5 100644
--- a/hw/nios2/10m50_devboard.c
+++ b/hw/nios2/10m50_devboard.c
@@ -38,6 +38,11 @@
struct Nios2MachineState {
MachineState parent_obj;
+
+ MemoryRegion phys_tcm;
+ MemoryRegion phys_tcm_alias;
+ MemoryRegion phys_ram;
+ MemoryRegion phys_ram_alias;
};
#define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd")
@@ -47,13 +52,10 @@ OBJECT_DECLARE_TYPE(Nios2MachineState, MachineClass, NIOS2_MACHINE)
static void nios2_10m50_ghrd_init(MachineState *machine)
{
+ Nios2MachineState *nms = NIOS2_MACHINE(machine);
Nios2CPU *cpu;
DeviceState *dev;
MemoryRegion *address_space_mem = get_system_memory();
- MemoryRegion *phys_tcm = g_new(MemoryRegion, 1);
- MemoryRegion *phys_tcm_alias = g_new(MemoryRegion, 1);
- MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
- MemoryRegion *phys_ram_alias = g_new(MemoryRegion, 1);
ram_addr_t tcm_base = 0x0;
ram_addr_t tcm_size = 0x1000; /* 1 kiB, but QEMU limit is 4 kiB */
ram_addr_t ram_base = 0x08000000;
@@ -62,22 +64,22 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
int i;
/* Physical TCM (tb_ram_1k) with alias at 0xc0000000 */
- memory_region_init_ram(phys_tcm, NULL, "nios2.tcm", tcm_size,
+ memory_region_init_ram(&nms->phys_tcm, NULL, "nios2.tcm", tcm_size,
&error_abort);
- memory_region_init_alias(phys_tcm_alias, NULL, "nios2.tcm.alias",
- phys_tcm, 0, tcm_size);
- memory_region_add_subregion(address_space_mem, tcm_base, phys_tcm);
+ memory_region_init_alias(&nms->phys_tcm_alias, NULL, "nios2.tcm.alias",
+ &nms->phys_tcm, 0, tcm_size);
+ memory_region_add_subregion(address_space_mem, tcm_base, &nms->phys_tcm);
memory_region_add_subregion(address_space_mem, 0xc0000000 + tcm_base,
- phys_tcm_alias);
+ &nms->phys_tcm_alias);
/* Physical DRAM with alias at 0xc0000000 */
- memory_region_init_ram(phys_ram, NULL, "nios2.ram", ram_size,
+ memory_region_init_ram(&nms->phys_ram, NULL, "nios2.ram", ram_size,
&error_abort);
- memory_region_init_alias(phys_ram_alias, NULL, "nios2.ram.alias",
- phys_ram, 0, ram_size);
- memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
+ memory_region_init_alias(&nms->phys_ram_alias, NULL, "nios2.ram.alias",
+ &nms->phys_ram, 0, ram_size);
+ memory_region_add_subregion(address_space_mem, ram_base, &nms->phys_ram);
memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base,
- phys_ram_alias);
+ &nms->phys_ram_alias);
/* Create CPU -- FIXME */
cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU));
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 62/64] hw/nios2: Machine with a Vectored Interrupt Controller
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (60 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 61/64] hw/nios2: Move memory regions into Nios2Machine Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-21 15:17 ` [PATCH v7 63/64] tests/tcg/nios2: Add semihosting multiarch tests Richard Henderson
2022-04-21 15:17 ` [PATCH v7 64/64] tests/tcg/nios2: Add test-shadow-1 Richard Henderson
63 siblings, 0 replies; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Amir Gonnen, Mark Cave-Ayland
From: Amir Gonnen <amir.gonnen@neuroblade.ai>
Demonstrate how to use nios2 VIC on a machine.
Introduce a new machine property to attach a VIC.
When VIC is present, let the CPU know that it should use the
External Interrupt Interface instead of the Internal Interrupt Interface.
The devices on the machine are attached to the VIC and not directly to cpu.
To allow VIC update EIC fields, we set the "cpu" property of the VIC
with a reference to the nios2 cpu.
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Amir Gonnen <amir.gonnen@neuroblade.ai>
Message-Id: <20220303153906.2024748-6-amir.gonnen@neuroblade.ai>
[rth: Put a property on the 10m50-ghrd machine, rather than
create a new machine class.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/nios2/10m50_devboard.c | 61 +++++++++++++++++++++++++++++++++------
hw/nios2/Kconfig | 1 +
2 files changed, 53 insertions(+), 9 deletions(-)
diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c
index dda4ab2bf5..91383fb097 100644
--- a/hw/nios2/10m50_devboard.c
+++ b/hw/nios2/10m50_devboard.c
@@ -27,6 +27,7 @@
#include "hw/sysbus.h"
#include "hw/char/serial.h"
+#include "hw/intc/nios2_vic.h"
#include "hw/qdev-properties.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
@@ -43,6 +44,8 @@ struct Nios2MachineState {
MemoryRegion phys_tcm_alias;
MemoryRegion phys_ram;
MemoryRegion phys_ram_alias;
+
+ bool vic;
};
#define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd")
@@ -81,10 +84,39 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base,
&nms->phys_ram_alias);
- /* Create CPU -- FIXME */
- cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU));
- for (i = 0; i < 32; i++) {
- irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i);
+ /* Create CPU. We need to set eic_present between init and realize. */
+ cpu = NIOS2_CPU(object_new(TYPE_NIOS2_CPU));
+
+ /* Enable the External Interrupt Controller within the CPU. */
+ cpu->eic_present = nms->vic;
+
+ /* Configure new exception vectors. */
+ cpu->reset_addr = 0xd4000000;
+ cpu->exception_addr = 0xc8000120;
+ cpu->fast_tlb_miss_addr = 0xc0000100;
+
+ qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal);
+
+ if (nms->vic) {
+ DeviceState *dev = qdev_new(TYPE_NIOS2_VIC);
+ MemoryRegion *dev_mr;
+ qemu_irq cpu_irq;
+
+ object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+ cpu_irq = qdev_get_gpio_in_named(DEVICE(cpu), "EIC", 0);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq);
+ for (int i = 0; i < 32; i++) {
+ irq[i] = qdev_get_gpio_in(dev, i);
+ }
+
+ dev_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+ memory_region_add_subregion(address_space_mem, 0x18002000, dev_mr);
+ } else {
+ for (i = 0; i < 32; i++) {
+ irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i);
+ }
}
/* Register: Altera 16550 UART */
@@ -105,15 +137,22 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe0000880);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]);
- /* Configure new exception vectors and reset CPU for it to take effect. */
- cpu->reset_addr = 0xd4000000;
- cpu->exception_addr = 0xc8000120;
- cpu->fast_tlb_miss_addr = 0xc0000100;
-
nios2_load_kernel(cpu, ram_base, ram_size, machine->initrd_filename,
BINARY_DEVICE_TREE_FILE, NULL);
}
+static bool get_vic(Object *obj, Error **errp)
+{
+ Nios2MachineState *nms = NIOS2_MACHINE(obj);
+ return nms->vic;
+}
+
+static void set_vic(Object *obj, bool value, Error **errp)
+{
+ Nios2MachineState *nms = NIOS2_MACHINE(obj);
+ nms->vic = value;
+}
+
static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -121,6 +160,10 @@ static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data)
mc->desc = "Altera 10M50 GHRD Nios II design";
mc->init = nios2_10m50_ghrd_init;
mc->is_default = true;
+
+ object_class_property_add_bool(oc, "vic", get_vic, set_vic);
+ object_class_property_set_description(oc, "vic",
+ "Set on/off to enable/disable the Vectored Interrupt Controller");
}
static const TypeInfo nios2_10m50_ghrd_type_info = {
diff --git a/hw/nios2/Kconfig b/hw/nios2/Kconfig
index b10ea640da..4748ae27b6 100644
--- a/hw/nios2/Kconfig
+++ b/hw/nios2/Kconfig
@@ -3,6 +3,7 @@ config NIOS2_10M50
select NIOS2
select SERIAL
select ALTERA_TIMER
+ select NIOS2_VIC
config NIOS2_GENERIC_NOMMU
bool
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* [PATCH v7 63/64] tests/tcg/nios2: Add semihosting multiarch tests
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (61 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 62/64] hw/nios2: Machine with a Vectored Interrupt Controller Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-22 13:26 ` Peter Maydell
2022-04-21 15:17 ` [PATCH v7 64/64] tests/tcg/nios2: Add test-shadow-1 Richard Henderson
63 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Alex Bennée
Add runtime supporting the nios2-semi.c interface.
Execute the hello and memory multiarch tests.
Cc: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tests/tcg/nios2/semicall.h | 25 +++
tests/tcg/nios2/10m50-ghrd.ld | 59 +++++++
tests/tcg/nios2/Makefile.softmmu-target | 29 ++++
tests/tcg/nios2/boot.S | 218 ++++++++++++++++++++++++
tests/tcg/nios2/intr.S | 31 ++++
5 files changed, 362 insertions(+)
create mode 100644 tests/tcg/nios2/semicall.h
create mode 100644 tests/tcg/nios2/10m50-ghrd.ld
create mode 100644 tests/tcg/nios2/Makefile.softmmu-target
create mode 100644 tests/tcg/nios2/boot.S
create mode 100644 tests/tcg/nios2/intr.S
diff --git a/tests/tcg/nios2/semicall.h b/tests/tcg/nios2/semicall.h
new file mode 100644
index 0000000000..d7acf665e1
--- /dev/null
+++ b/tests/tcg/nios2/semicall.h
@@ -0,0 +1,25 @@
+/*
+ * Nios2 semihosting interface.
+ */
+
+#ifndef SEMICALL_H
+#define SEMICALL_H
+
+#define HOSTED_EXIT 0
+#define HOSTED_INIT_SIM 1
+#define HOSTED_OPEN 2
+#define HOSTED_CLOSE 3
+#define HOSTED_READ 4
+#define HOSTED_WRITE 5
+#define HOSTED_LSEEK 6
+#define HOSTED_RENAME 7
+#define HOSTED_UNLINK 8
+#define HOSTED_STAT 9
+#define HOSTED_FSTAT 10
+#define HOSTED_GETTIMEOFDAY 11
+#define HOSTED_ISATTY 12
+#define HOSTED_SYSTEM 13
+
+#define semihosting_call break 1
+
+#endif /* SEMICALL_H */
diff --git a/tests/tcg/nios2/10m50-ghrd.ld b/tests/tcg/nios2/10m50-ghrd.ld
new file mode 100644
index 0000000000..d83e136267
--- /dev/null
+++ b/tests/tcg/nios2/10m50-ghrd.ld
@@ -0,0 +1,59 @@
+MEMORY
+{
+ tpf (rx) : ORIGIN = 0xc0000000, LENGTH = 1K
+ ram (rwx) : ORIGIN = 0xc8000000, LENGTH = 128M
+}
+
+PHDRS
+{
+ RAM PT_LOAD;
+}
+
+ENTRY(_start)
+EXTERN(_start)
+EXTERN(_interrupt)
+EXTERN(_fast_tlb_miss)
+
+SECTIONS
+{
+ /* Begin at the (hardcoded) _interrupt entry point. */
+ .text 0xc8000120 : {
+ *(.text.intr)
+ *(.text .text.* .gnu.linkonce.t.*)
+ } >ram :RAM
+
+ .rodata : ALIGN(4) {
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ } > ram :RAM
+
+ .eh_frame_hdr : ALIGN (4) {
+ KEEP (*(.eh_frame_hdr))
+ *(.eh_frame_entry .eh_frame_entry.*)
+ } >ram :RAM
+ .eh_frame : ALIGN (4) {
+ KEEP (*(.eh_frame)) *(.eh_frame.*)
+ } >ram :RAM
+
+ .data : ALIGN(4) {
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ . = ALIGN(4);
+ _gp = ABSOLUTE(. + 0x8000);
+ *(.got.plt) *(.got)
+ *(.lit8)
+ *(.lit4)
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ } >ram :RAM
+
+ .bss : ALIGN(4) {
+ __bss_start = ABSOLUTE(.);
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end = ABSOLUTE(.);
+ } >ram :RAM
+
+ __stack = ORIGIN(ram) + LENGTH(ram);
+}
diff --git a/tests/tcg/nios2/Makefile.softmmu-target b/tests/tcg/nios2/Makefile.softmmu-target
new file mode 100644
index 0000000000..70664db81c
--- /dev/null
+++ b/tests/tcg/nios2/Makefile.softmmu-target
@@ -0,0 +1,29 @@
+#
+# Nios2 system tests
+#
+
+NIOS2_SYSTEM_SRC = $(SRC_PATH)/tests/tcg/nios2
+VPATH += $(NIOS2_SYSTEM_SRC)
+
+# These objects provide the basic boot code and helper functions for all tests
+CRT_OBJS = boot.o intr.o $(MINILIB_OBJS)
+LINK_SCRIPT = $(NIOS2_SYSTEM_SRC)/10m50-ghrd.ld
+
+CFLAGS += -nostdlib -g -O0 $(MINILIB_INC)
+LDFLAGS += -Wl,-T$(LINK_SCRIPT) -static -nostdlib $(CRT_OBJS) -lgcc
+
+%.o: %.S
+ $(call quiet-command, $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -x assembler-with-cpp -c $< -o $@, AS, $@)
+
+%.o: %.c
+ $(call quiet-command, $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@, CC, $@)
+
+# Build and link the tests
+%: %.o $(LINK_SCRIPT) $(CRT_OBJS)
+ $(call quiet-command, $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS), LD, $@)
+
+# FIXME: nios2 semihosting writes to stdout, not a chardev
+QEMU_OPTS = -M 10m50-ghrd,vic=on -semihosting >$@.out -kernel
+
+memory: CFLAGS+=-DCHECK_UNALIGNED=0
+TESTS += $(MULTIARCH_TESTS)
diff --git a/tests/tcg/nios2/boot.S b/tests/tcg/nios2/boot.S
new file mode 100644
index 0000000000..f6771cbc81
--- /dev/null
+++ b/tests/tcg/nios2/boot.S
@@ -0,0 +1,218 @@
+/*
+ * Minimal Nios2 system boot code.
+ *
+ * Copyright Linaro Ltd 2022
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "semicall.h"
+
+ .text
+ .set noat
+
+_start:
+ /* Linker script defines stack at end of ram. */
+ movia sp, __stack
+
+ /* Install trampoline to _fast_tlb_miss at hardcoded vector. */
+ movia r4, 0xc0000100
+ movia r5, _ftm_tramp
+ movi r6, .L__ftm_end - _ftm_tramp
+ call memcpy
+
+ /* Zero the bss to satisfy C. */
+ movia r4, __bss_start
+ movia r6, __bss_end
+ sub r6, r6, r4
+ movi r5, 0
+ call memset
+
+ /* Test! */
+ call main
+
+ /* Exit with main's return value. */
+ movi r4, HOSTED_EXIT
+ mov r5, r2
+ semihosting_call
+
+ .globl _start
+ .type _start, @function
+ .size _start, . - _start
+
+_ftm_tramp:
+ movia et, _fast_tlb_miss
+ jmp et
+.L__ftm_end:
+
+ .type _ftm_tramp, @function
+ .size _ftm_tramp, . - _ftm_tramp
+
+#define dst r4
+#define src r5
+#define len r6
+
+memcpy:
+ /* Store return value right away, per API */
+ mov r2, dst
+
+ /* Check for both dst and src aligned. */
+ or at, dst, src
+ andi at, at, 3
+ bne at, zero, .L_mc_test1
+
+ /* Copy blocks of 8. */
+
+ movi at, 8
+ bltu len, at, .L_mc_test4
+
+.L_mc_loop8:
+ ldw r8, 0(src)
+ ldw r9, 4(src)
+ addi src, src, 8
+ addi dst, dst, 8
+ subi len, len, 8
+ stw r8, -8(dst)
+ stw r9, -4(dst)
+ bgeu len, at, .L_mc_loop8
+
+ /* Copy final aligned block of 4. */
+
+.L_mc_test4:
+ movi at, 4
+ bltu len, at, .L_mc_test1
+
+ ldw r8, 0(src)
+ addi src, src, 4
+ addi dst, dst, 4
+ subi len, len, 4
+ stw r8, -4(dst)
+
+ /* Copy single bytes to finish. */
+
+.L_mc_test1:
+ beq len, zero, .L_mc_done
+
+.L_mc_loop1:
+ ldb r8, 0(src)
+ addi src, src, 1
+ addi dst, dst, 1
+ subi len, len, 1
+ stb r8, -1(dst)
+ bne len, zero, .L_mc_loop1
+
+.L_mc_done:
+ ret
+
+#undef dst
+#undef src
+#undef len
+
+ .global memcpy
+ .type memcpy, @function
+ .size memcpy, . - memcpy
+
+#define dst r4
+#define val r5
+#define len r6
+
+memset:
+ /* Store return value right away, per API */
+ mov r2, dst
+
+ /* Check for small blocks; fall back to bytewise. */
+ movi r3, 8
+ bltu len, r3, .L_ms_test1
+
+ /* Replicate the byte across the word. */
+ andi val, val, 0xff
+ slli at, val, 8
+ or val, val, at
+ slli at, val, 16
+ or val, val, at
+
+ /* Check for destination alignment; realign if needed. */
+ andi at, dst, 3
+ bne at, zero, .L_ms_align
+
+ /* Set blocks of 8. */
+
+.L_ms_loop8:
+ stw val, 0(dst)
+ stw val, 4(dst)
+ addi dst, dst, 8
+ subi len, len, 8
+ bgeu len, r3, .L_ms_loop8
+
+ /* Set final aligned block of 4. */
+
+.L_ms_test4:
+ movi at, 4
+ bltu len, at, .L_ms_test1
+
+ stw r8, 0(dst)
+ addi dst, dst, 4
+ subi len, len, 4
+ stw r8, -4(dst)
+
+ /* Set single bytes to finish. */
+
+.L_ms_test1:
+ beq len, zero, .L_ms_done
+
+.L_ms_loop1:
+ stb r8, 0(dst)
+ addi dst, dst, 1
+ subi len, len, 1
+ bne len, zero, .L_ms_loop1
+
+.L_ms_done:
+ ret
+
+ /* Realign for a large block, len >= 8. */
+.L_ms_align:
+ andi at, dst, 1
+ beq at, zero, 2f
+
+ stb val, 0(dst)
+ addi dst, dst, 1
+ subi len, len, 1
+
+2: andi at, dst, 2
+ beq at, zero, 4f
+
+ sth val, 0(dst)
+ addi dst, dst, 2
+ subi len, len, 2
+
+4: bgeu len, r3, .L_ms_loop8
+ br .L_ms_test4
+
+#undef dst
+#undef val
+#undef len
+
+ .global memset
+ .type memset, @function
+ .size memset, . - memset
+
+/*
+ * void __sys_outc(char c);
+ */
+__sys_outc:
+ subi sp, sp, 16
+ stb r4, 0(sp) /* buffer[0] = c */
+ movi at, 1
+ stw at, 4(sp) /* STDOUT_FILENO */
+ stw sp, 8(sp) /* buffer */
+ stw at, 12(sp) /* len */
+
+ movi r4, HOSTED_WRITE
+ addi r5, sp, 4
+ semihosting_call
+
+ addi sp, sp, 16
+ ret
+
+ .global __sys_outc
+ .type __sys_outc, @function
+ .size __sys_outc, . - __sys_outc
diff --git a/tests/tcg/nios2/intr.S b/tests/tcg/nios2/intr.S
new file mode 100644
index 0000000000..c1730692ba
--- /dev/null
+++ b/tests/tcg/nios2/intr.S
@@ -0,0 +1,31 @@
+/*
+ * Minimal Nios2 system boot code -- exit on interrupt.
+ *
+ * Copyright Linaro Ltd 2022
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "semicall.h"
+
+ .section .text.intr, "ax"
+ .global _interrupt
+ .type _interrupt, @function
+
+_interrupt:
+ rdctl r5, exception /* extract exception.CAUSE */
+ srli r5, r5, 2
+ movi r4, HOSTED_EXIT
+ semihosting_call
+
+ .size _interrupt, . - _interrupt
+
+ .text
+ .global _fast_tlb_miss
+ .type _fast_tlb_miss, @function
+
+_fast_tlb_miss:
+ movi r5, 32
+ movi r4, HOSTED_EXIT
+ semihosting_call
+
+ .size _fast_tlb_miss, . - _fast_tlb_miss
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* Re: [PATCH v7 63/64] tests/tcg/nios2: Add semihosting multiarch tests
2022-04-21 15:17 ` [PATCH v7 63/64] tests/tcg/nios2: Add semihosting multiarch tests Richard Henderson
@ 2022-04-22 13:26 ` Peter Maydell
0 siblings, 0 replies; 78+ messages in thread
From: Peter Maydell @ 2022-04-22 13:26 UTC (permalink / raw)
To: Richard Henderson; +Cc: Alex Bennée, qemu-devel
On Thu, 21 Apr 2022 at 17:16, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Add runtime supporting the nios2-semi.c interface.
> Execute the hello and memory multiarch tests.
>
> Cc: Alex Bennée <alex.bennee@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tests/tcg/nios2/semicall.h | 25 +++
> tests/tcg/nios2/10m50-ghrd.ld | 59 +++++++
> tests/tcg/nios2/Makefile.softmmu-target | 29 ++++
> tests/tcg/nios2/boot.S | 218 ++++++++++++++++++++++++
> tests/tcg/nios2/intr.S | 31 ++++
> 5 files changed, 362 insertions(+)
> create mode 100644 tests/tcg/nios2/semicall.h
> create mode 100644 tests/tcg/nios2/10m50-ghrd.ld
> create mode 100644 tests/tcg/nios2/Makefile.softmmu-target
> create mode 100644 tests/tcg/nios2/boot.S
> create mode 100644 tests/tcg/nios2/intr.S
Most of these new files are missing the copyright/license comment header.
thanks
-- PMM
^ permalink raw reply [flat|nested] 78+ messages in thread
* [PATCH v7 64/64] tests/tcg/nios2: Add test-shadow-1
2022-04-21 15:16 [PATCH v7 00/64] nios2 fixes, cleanups, shadow reg sets Richard Henderson
` (62 preceding siblings ...)
2022-04-21 15:17 ` [PATCH v7 63/64] tests/tcg/nios2: Add semihosting multiarch tests Richard Henderson
@ 2022-04-21 15:17 ` Richard Henderson
2022-04-22 13:26 ` Peter Maydell
63 siblings, 1 reply; 78+ messages in thread
From: Richard Henderson @ 2022-04-21 15:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Alex Bennée
Add a regression test for tcg indirect global lowering.
This appeared with nios2, with cps != 0, so that we use
indirection into the shadow register set. An indirect
call verifies alignment of rA. The use of rA was live
across the brcond leading to a tcg_debug_assert failure.
Cc: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tests/tcg/nios2/Makefile.softmmu-target | 1 +
tests/tcg/nios2/test-shadow-1.S | 37 +++++++++++++++++++++++++
2 files changed, 38 insertions(+)
create mode 100644 tests/tcg/nios2/test-shadow-1.S
diff --git a/tests/tcg/nios2/Makefile.softmmu-target b/tests/tcg/nios2/Makefile.softmmu-target
index 70664db81c..b5f6a08848 100644
--- a/tests/tcg/nios2/Makefile.softmmu-target
+++ b/tests/tcg/nios2/Makefile.softmmu-target
@@ -27,3 +27,4 @@ QEMU_OPTS = -M 10m50-ghrd,vic=on -semihosting >$@.out -kernel
memory: CFLAGS+=-DCHECK_UNALIGNED=0
TESTS += $(MULTIARCH_TESTS)
+TESTS += test-shadow-1
diff --git a/tests/tcg/nios2/test-shadow-1.S b/tests/tcg/nios2/test-shadow-1.S
new file mode 100644
index 0000000000..33076ddf59
--- /dev/null
+++ b/tests/tcg/nios2/test-shadow-1.S
@@ -0,0 +1,37 @@
+/*
+ * Regresion test for TCG indirect global lowering.
+ */
+
+#include "semicall.h"
+
+ .text
+ .set noat
+ .align 2
+ .globl main
+ .type main, @function
+
+main:
+ /* Initialize r0 in shadow register set 1. */
+ movhi at, 1 /* PRS=1, CRS=0, RSIE=0, PIE=0 */
+ wrctl status, at
+ wrprs zero, zero
+
+ /* Change current register set to 1. */
+ movi at, 1 << 10 /* PRS=0, CRS=1, RSIE=0, PIE=0 */
+ wrctl estatus, at
+ movia ea, 1f
+ eret
+
+ /* Load address for callr, then end TB. */
+1: movia at, 3f
+ br 2f
+
+ /* Test case! TCG abort on indirect lowering across brcond. */
+2: callr at
+
+ /* exit(0) */
+3: movi r4, HOSTED_EXIT
+ movi r5, 0
+ semihosting_call
+
+ .size main, . - main
--
2.34.1
^ permalink raw reply related [flat|nested] 78+ messages in thread* Re: [PATCH v7 64/64] tests/tcg/nios2: Add test-shadow-1
2022-04-21 15:17 ` [PATCH v7 64/64] tests/tcg/nios2: Add test-shadow-1 Richard Henderson
@ 2022-04-22 13:26 ` Peter Maydell
0 siblings, 0 replies; 78+ messages in thread
From: Peter Maydell @ 2022-04-22 13:26 UTC (permalink / raw)
To: Richard Henderson; +Cc: Alex Bennée, qemu-devel
On Thu, 21 Apr 2022 at 17:13, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Add a regression test for tcg indirect global lowering.
>
> This appeared with nios2, with cps != 0, so that we use
> indirection into the shadow register set. An indirect
> call verifies alignment of rA. The use of rA was live
> across the brcond leading to a tcg_debug_assert failure.
>
> Cc: Alex Bennée <alex.bennee@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> +/*
> + * Regresion test for TCG indirect global lowering.
"Regression".
Also, file is missing copyright/license header comment.
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 78+ messages in thread