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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>,
	Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>,
	dri-devel@lists.freedesktop.org
Subject: [PATCH 2/2] drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines
Date: Fri, 22 Apr 2022 12:50:07 -0700	[thread overview]
Message-ID: <20220422195007.4019661-3-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20220422195007.4019661-1-matthew.d.roper@intel.com>

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b60492826478..7739d6c33481 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1037,7 +1037,8 @@ static const struct intel_device_info xehpsdv_info = {
 		BIT(RCS0) | BIT(BCS0) |
 		BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
 		BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
-		BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7),
+		BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
+		BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
 	.require_force_probe = 1,
 };
 
@@ -1056,7 +1057,8 @@ static const struct intel_device_info xehpsdv_info = {
 	.platform_engine_mask = \
 		BIT(RCS0) | BIT(BCS0) | \
 		BIT(VECS0) | BIT(VECS1) | \
-		BIT(VCS0) | BIT(VCS2)
+		BIT(VCS0) | BIT(VCS2) | \
+		BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
 
 static const struct intel_device_info dg2_info = {
 	DG2_FEATURES,
-- 
2.35.1


WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines
Date: Fri, 22 Apr 2022 12:50:07 -0700	[thread overview]
Message-ID: <20220422195007.4019661-3-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20220422195007.4019661-1-matthew.d.roper@intel.com>

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b60492826478..7739d6c33481 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1037,7 +1037,8 @@ static const struct intel_device_info xehpsdv_info = {
 		BIT(RCS0) | BIT(BCS0) |
 		BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
 		BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
-		BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7),
+		BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
+		BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
 	.require_force_probe = 1,
 };
 
@@ -1056,7 +1057,8 @@ static const struct intel_device_info xehpsdv_info = {
 	.platform_engine_mask = \
 		BIT(RCS0) | BIT(BCS0) | \
 		BIT(VECS0) | BIT(VECS1) | \
-		BIT(VCS0) | BIT(VCS2)
+		BIT(VCS0) | BIT(VCS2) | \
+		BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
 
 static const struct intel_device_info dg2_info = {
 	DG2_FEATURES,
-- 
2.35.1


  parent reply	other threads:[~2022-04-22 19:50 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-22 19:50 [PATCH 0/2] i915: Turn on compute engine support Matt Roper
2022-04-22 19:50 ` [Intel-gfx] " Matt Roper
2022-04-22 19:50 ` [PATCH 1/2] drm/i915/xehp: Add compute engine ABI Matt Roper
2022-04-22 19:50   ` [Intel-gfx] " Matt Roper
2022-04-25 10:41   ` Tvrtko Ursulin
2022-04-25 10:41     ` [Intel-gfx] " Tvrtko Ursulin
2022-04-25 17:35     ` Matt Roper
2022-04-25 17:35       ` [Intel-gfx] " Matt Roper
2022-04-25 18:40       ` Yang, Fei
2022-04-25 18:40         ` [Intel-gfx] " Yang, Fei
2022-04-26  7:25         ` Tvrtko Ursulin
2022-04-26  7:25           ` [Intel-gfx] " Tvrtko Ursulin
2022-04-28  0:27     ` Kumar Valsan, Prathap
2022-04-28  3:44     ` Matt Roper
2022-04-28  3:44       ` [Intel-gfx] " Matt Roper
2022-04-25 14:48   ` Andi Shyti
2022-04-22 19:50 ` Matt Roper [this message]
2022-04-22 19:50   ` [Intel-gfx] [PATCH 2/2] drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines Matt Roper
2022-04-25 14:48   ` Andi Shyti
2022-04-22 20:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Turn on compute engine support Patchwork
2022-04-22 20:47 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-04-22 21:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Turn on compute engine support (rev2) Patchwork
2022-04-22 22:07 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-04-22 22:33   ` Matt Roper
2022-04-22 23:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Turn on compute engine support (rev3) Patchwork
2022-04-22 23:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-04-23  1:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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