From: Samuel Holland <samuel@sholland.org>
To: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
iommu@lists.linux-foundation.org
Cc: Heiko Stuebner <heiko@sntech.de>,
Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org,
Samuel Holland <samuel@sholland.org>,
Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Maxime Ripard <mripard@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev
Subject: [PATCH 3/5] iommu/sun50i: Ensure bypass is disabled
Date: Wed, 27 Apr 2022 20:03:58 -0500 [thread overview]
Message-ID: <20220428010401.11323-4-samuel@sholland.org> (raw)
In-Reply-To: <20220428010401.11323-1-samuel@sholland.org>
The H6 variant of the hardware disables bypass by default. The D1
variant of the hardware enables bypass for all masters by default.
Since the driver expects bypass to be disabled, ensure that is the case.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/iommu/sun50i-iommu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
index ec07b60016d3..b9e644b93637 100644
--- a/drivers/iommu/sun50i-iommu.c
+++ b/drivers/iommu/sun50i-iommu.c
@@ -374,6 +374,8 @@ static int sun50i_iommu_enable(struct sun50i_iommu *iommu)
spin_lock_irqsave(&iommu->iommu_lock, flags);
+ iommu_write(iommu, IOMMU_BYPASS_REG, 0);
+
iommu_write(iommu, IOMMU_TTB_REG, sun50i_domain->dt_dma);
iommu_write(iommu, IOMMU_TLB_PREFETCH_REG,
IOMMU_TLB_PREFETCH_MASTER_ENABLE(0) |
--
2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: Samuel Holland <samuel@sholland.org>
To: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
iommu@lists.linux-foundation.org
Cc: Heiko Stuebner <heiko@sntech.de>,
Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org,
Samuel Holland <samuel@sholland.org>,
Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Maxime Ripard <mripard@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev
Subject: [PATCH 3/5] iommu/sun50i: Ensure bypass is disabled
Date: Wed, 27 Apr 2022 20:03:58 -0500 [thread overview]
Message-ID: <20220428010401.11323-4-samuel@sholland.org> (raw)
In-Reply-To: <20220428010401.11323-1-samuel@sholland.org>
The H6 variant of the hardware disables bypass by default. The D1
variant of the hardware enables bypass for all masters by default.
Since the driver expects bypass to be disabled, ensure that is the case.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/iommu/sun50i-iommu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
index ec07b60016d3..b9e644b93637 100644
--- a/drivers/iommu/sun50i-iommu.c
+++ b/drivers/iommu/sun50i-iommu.c
@@ -374,6 +374,8 @@ static int sun50i_iommu_enable(struct sun50i_iommu *iommu)
spin_lock_irqsave(&iommu->iommu_lock, flags);
+ iommu_write(iommu, IOMMU_BYPASS_REG, 0);
+
iommu_write(iommu, IOMMU_TTB_REG, sun50i_domain->dt_dma);
iommu_write(iommu, IOMMU_TLB_PREFETCH_REG,
IOMMU_TLB_PREFETCH_MASTER_ENABLE(0) |
--
2.35.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Samuel Holland <samuel@sholland.org>
To: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
iommu@lists.linux-foundation.org
Cc: Heiko Stuebner <heiko@sntech.de>,
Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org,
Samuel Holland <samuel@sholland.org>,
Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Maxime Ripard <mripard@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev
Subject: [PATCH 3/5] iommu/sun50i: Ensure bypass is disabled
Date: Wed, 27 Apr 2022 20:03:58 -0500 [thread overview]
Message-ID: <20220428010401.11323-4-samuel@sholland.org> (raw)
In-Reply-To: <20220428010401.11323-1-samuel@sholland.org>
The H6 variant of the hardware disables bypass by default. The D1
variant of the hardware enables bypass for all masters by default.
Since the driver expects bypass to be disabled, ensure that is the case.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/iommu/sun50i-iommu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
index ec07b60016d3..b9e644b93637 100644
--- a/drivers/iommu/sun50i-iommu.c
+++ b/drivers/iommu/sun50i-iommu.c
@@ -374,6 +374,8 @@ static int sun50i_iommu_enable(struct sun50i_iommu *iommu)
spin_lock_irqsave(&iommu->iommu_lock, flags);
+ iommu_write(iommu, IOMMU_BYPASS_REG, 0);
+
iommu_write(iommu, IOMMU_TTB_REG, sun50i_domain->dt_dma);
iommu_write(iommu, IOMMU_TLB_PREFETCH_REG,
IOMMU_TLB_PREFETCH_MASTER_ENABLE(0) |
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Samuel Holland <samuel@sholland.org>
To: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
iommu@lists.linux-foundation.org
Cc: devicetree@vger.kernel.org, Heiko Stuebner <heiko@sntech.de>,
Samuel Holland <samuel@sholland.org>,
linux-kernel@vger.kernel.org,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Maxime Ripard <mripard@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/5] iommu/sun50i: Ensure bypass is disabled
Date: Wed, 27 Apr 2022 20:03:58 -0500 [thread overview]
Message-ID: <20220428010401.11323-4-samuel@sholland.org> (raw)
In-Reply-To: <20220428010401.11323-1-samuel@sholland.org>
The H6 variant of the hardware disables bypass by default. The D1
variant of the hardware enables bypass for all masters by default.
Since the driver expects bypass to be disabled, ensure that is the case.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/iommu/sun50i-iommu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
index ec07b60016d3..b9e644b93637 100644
--- a/drivers/iommu/sun50i-iommu.c
+++ b/drivers/iommu/sun50i-iommu.c
@@ -374,6 +374,8 @@ static int sun50i_iommu_enable(struct sun50i_iommu *iommu)
spin_lock_irqsave(&iommu->iommu_lock, flags);
+ iommu_write(iommu, IOMMU_BYPASS_REG, 0);
+
iommu_write(iommu, IOMMU_TTB_REG, sun50i_domain->dt_dma);
iommu_write(iommu, IOMMU_TLB_PREFETCH_REG,
IOMMU_TLB_PREFETCH_MASTER_ENABLE(0) |
--
2.35.1
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2022-04-28 1:04 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-28 1:03 [PATCH 0/5] iommu/sun50i: Allwinner D1 support Samuel Holland
2022-04-28 1:03 ` Samuel Holland
2022-04-28 1:03 ` Samuel Holland
2022-04-28 1:03 ` Samuel Holland
2022-04-28 1:03 ` [PATCH 1/5] dt-bindings: iommu: sun50i: Add compatible for Allwinner D1 Samuel Holland
2022-04-28 1:03 ` Samuel Holland
2022-04-28 1:03 ` Samuel Holland
2022-04-28 1:03 ` Samuel Holland
2022-04-28 7:19 ` Krzysztof Kozlowski
2022-04-28 7:19 ` Krzysztof Kozlowski
2022-04-28 7:19 ` Krzysztof Kozlowski
2022-04-28 7:19 ` Krzysztof Kozlowski
2022-04-28 1:03 ` [PATCH 2/5] iommu/sun50i: Support variants without an external reset Samuel Holland
2022-04-28 1:03 ` Samuel Holland
2022-04-28 1:03 ` Samuel Holland
2022-04-28 1:03 ` Samuel Holland
2022-04-28 5:34 ` Jernej Škrabec
2022-04-28 5:34 ` Jernej Škrabec
2022-04-28 5:34 ` Jernej Škrabec
2022-04-28 5:34 ` Jernej Škrabec
2022-04-28 7:43 ` Philipp Zabel
2022-04-28 7:43 ` Philipp Zabel
2022-04-28 7:43 ` Philipp Zabel
2022-04-28 7:43 ` Philipp Zabel
2022-04-28 1:03 ` Samuel Holland [this message]
2022-04-28 1:03 ` [PATCH 3/5] iommu/sun50i: Ensure bypass is disabled Samuel Holland
2022-04-28 1:03 ` Samuel Holland
2022-04-28 1:03 ` Samuel Holland
2022-04-28 5:43 ` Jernej Škrabec
2022-04-28 5:43 ` Jernej Škrabec
2022-04-28 5:43 ` Jernej Škrabec
2022-04-28 5:43 ` Jernej Škrabec
2022-04-28 1:03 ` [PATCH 4/5] iommu/sun50i: Add support for the D1 variant Samuel Holland
2022-04-28 1:03 ` Samuel Holland
2022-04-28 1:03 ` Samuel Holland
2022-04-28 1:03 ` Samuel Holland
2022-04-28 5:34 ` Jernej Škrabec
2022-04-28 5:34 ` Jernej Škrabec
2022-04-28 5:34 ` Jernej Škrabec
2022-04-28 5:34 ` Jernej Škrabec
2022-04-28 1:04 ` [PATCH 5/5] iommu/sun50i: Ensure the IOMMU can be used for DMA Samuel Holland
2022-04-28 1:04 ` Samuel Holland
2022-04-28 1:04 ` Samuel Holland
2022-04-28 1:04 ` Samuel Holland
2022-04-28 5:35 ` Jernej Škrabec
2022-04-28 5:35 ` Jernej Škrabec
2022-04-28 5:35 ` Jernej Škrabec
2022-04-28 5:35 ` Jernej Škrabec
2022-04-28 11:12 ` Robin Murphy
2022-04-28 11:12 ` Robin Murphy
2022-04-28 11:12 ` Robin Murphy
2022-04-28 11:12 ` Robin Murphy
2022-04-28 5:45 ` [PATCH 0/5] iommu/sun50i: Allwinner D1 support Jernej Škrabec
2022-04-28 5:45 ` Jernej Škrabec
2022-04-28 5:45 ` Jernej Škrabec
2022-04-28 5:45 ` Jernej Škrabec
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