From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH v4 21/45] target/arm: Drop EL3 no EL2 fallbacks
Date: Sat, 30 Apr 2022 22:50:03 -0700 [thread overview]
Message-ID: <20220501055028.646596-22-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org>
Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo,
and the local vpidr_regs definition, and rely on the
squasing to ARM_CP_CONST while registering.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 158 ++++----------------------------------------
1 file changed, 13 insertions(+), 145 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 598a9253d0..e24e0749ac 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5099,124 +5099,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
};
-/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
-static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
- { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
- .access = PL2_RW,
- .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
- { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
- .access = PL2_RW,
- .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
- .access = PL2_RW,
- .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_CONST,
- .resetvalue = 0 },
- { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
- .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_CONST,
- .resetvalue = 0 },
- { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
- .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
- .access = PL2_RW, .type = ARM_CP_CONST,
- .resetvalue = 0 },
- { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_CONST,
- .resetvalue = 0 },
- { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
- .access = PL2_RW, .type = ARM_CP_CONST,
- .resetvalue = 0 },
- { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
- .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
- .cp = 15, .opc1 = 6, .crm = 2,
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
- .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
- .resetvalue = 0 },
- { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
- .resetvalue = 0 },
- { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
- .resetvalue = 0 },
- { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
- .access = PL2_RW, .accessfn = access_tda,
- .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
- .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
- .type = ARM_CP_CONST,
- .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
- .access = PL2_RW, .resetvalue = 0 },
-};
-
-/* Ditto, but for registers which exist in ARMv8 but not v7 */
-static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
- { .name = "HCR2", .state = ARM_CP_STATE_AA32,
- .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
- .access = PL2_RW,
- .type = ARM_CP_CONST, .resetvalue = 0 },
-};
-
static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
{
ARMCPU *cpu = env_archcpu(env);
@@ -7902,7 +7784,17 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, v8_idregs);
define_arm_cp_regs(cpu, v8_cp_reginfo);
}
- if (arm_feature(env, ARM_FEATURE_EL2)) {
+
+ /*
+ * Register the base EL2 cpregs.
+ * Pre v8, these registers are implemented only as part of the
+ * Virtualization Extensions (EL2 present). Beginning with v8,
+ * if EL2 is missing but EL3 is enabled, mostly these become
+ * RES0 from EL3, with some specific exceptions.
+ */
+ if (arm_feature(env, ARM_FEATURE_EL2)
+ || (arm_feature(env, ARM_FEATURE_EL3)
+ && arm_feature(env, ARM_FEATURE_V8))) {
uint64_t vmpidr_def = mpidr_read_val(env);
ARMCPRegInfo vpidr_regs[] = {
{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
@@ -7943,33 +7835,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
};
define_one_arm_cp_reg(cpu, &rvbar);
}
- } else {
- /* If EL2 is missing but higher ELs are enabled, we need to
- * register the no_el2 reginfos.
- */
- if (arm_feature(env, ARM_FEATURE_EL3)) {
- /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
- * of MIDR_EL1 and MPIDR_EL1.
- */
- ARMCPRegInfo vpidr_regs[] = {
- { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
- .type = ARM_CP_CONST, .resetvalue = cpu->midr,
- .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
- { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
- .type = ARM_CP_NO_RAW,
- .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
- };
- define_arm_cp_regs(cpu, vpidr_regs);
- define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
- if (arm_feature(env, ARM_FEATURE_V8)) {
- define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
- }
- }
}
+
+ /* Register the base EL3 cpregs. */
if (arm_feature(env, ARM_FEATURE_EL3)) {
define_arm_cp_regs(cpu, el3_cp_reginfo);
ARMCPRegInfo el3_regs[] = {
--
2.34.1
next prev parent reply other threads:[~2022-05-01 6:39 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-01 5:49 [PATCH v4 00/45] target/arm: Cleanups, new features, new cpus Richard Henderson
2022-05-01 5:49 ` [PATCH v4 01/45] target/arm: Split out cpregs.h Richard Henderson
2022-05-01 5:49 ` [PATCH v4 02/45] target/arm: Reorg CPAccessResult and access_check_cp_reg Richard Henderson
2022-05-01 5:49 ` [PATCH v4 03/45] target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h Richard Henderson
2022-05-01 5:49 ` [PATCH v4 04/45] target/arm: Make some more cpreg data static const Richard Henderson
2022-05-01 5:49 ` [PATCH v4 05/45] target/arm: Reorg ARMCPRegInfo type field bits Richard Henderson
2022-05-03 15:58 ` Peter Maydell
2022-05-01 5:49 ` [PATCH v4 06/45] target/arm: Avoid bare abort() or assert(0) Richard Henderson
2022-05-01 10:47 ` Peter Maydell
2022-05-01 5:49 ` [PATCH v4 07/45] target/arm: Change cpreg access permissions to enum Richard Henderson
2022-05-01 5:49 ` [PATCH v4 08/45] target/arm: Name CPState type Richard Henderson
2022-05-01 5:49 ` [PATCH v4 09/45] target/arm: Name CPSecureState type Richard Henderson
2022-05-01 5:49 ` [PATCH v4 10/45] target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases Richard Henderson
2022-05-03 15:59 ` Peter Maydell
2022-05-01 5:49 ` [PATCH v4 11/45] target/arm: Store cpregs key in the hash table directly Richard Henderson
2022-05-03 16:02 ` Peter Maydell
2022-05-01 5:49 ` [PATCH v4 12/45] target/arm: Merge allocation of the cpreg and its name Richard Henderson
2022-05-03 16:07 ` Peter Maydell
2022-05-01 5:49 ` [PATCH v4 13/45] target/arm: Hoist computation of key in add_cpreg_to_hashtable Richard Henderson
2022-05-03 16:13 ` Peter Maydell
2022-05-01 5:49 ` [PATCH v4 14/45] target/arm: Consolidate cpreg updates " Richard Henderson
2022-05-03 16:15 ` Peter Maydell
2022-05-01 5:49 ` [PATCH v4 15/45] target/arm: Use bool for is64 and ns " Richard Henderson
2022-05-03 16:15 ` Peter Maydell
2022-05-01 5:49 ` [PATCH v4 16/45] target/arm: Hoist isbanked computation " Richard Henderson
2022-05-03 16:16 ` Peter Maydell
2022-05-01 5:49 ` [PATCH v4 17/45] target/arm: Perform override check early " Richard Henderson
2022-05-03 16:21 ` Peter Maydell
2022-05-01 5:50 ` [PATCH v4 18/45] target/arm: Reformat comments " Richard Henderson
2022-05-03 16:22 ` Peter Maydell
2022-05-01 5:50 ` [PATCH v4 19/45] target/arm: Remove HOST_BIG_ENDIAN ifdef " Richard Henderson
2022-05-03 16:25 ` Peter Maydell
2022-05-01 5:50 ` [PATCH v4 20/45] target/arm: Handle cpreg registration for missing EL Richard Henderson
2022-05-03 16:34 ` Peter Maydell
2022-05-03 16:45 ` Richard Henderson
2022-05-03 16:50 ` Peter Maydell
2022-05-01 5:50 ` Richard Henderson [this message]
2022-05-03 17:13 ` [PATCH v4 21/45] target/arm: Drop EL3 no EL2 fallbacks Peter Maydell
2022-05-01 5:50 ` [PATCH v4 22/45] target/arm: Merge zcr reginfo Richard Henderson
2022-05-03 17:12 ` Peter Maydell
2022-05-01 5:50 ` [PATCH v4 23/45] target/arm: Add isar predicates for FEAT_Debugv8p2 Richard Henderson
2022-05-01 5:50 ` [PATCH v4 24/45] target/arm: Adjust definition of CONTEXTIDR_EL2 Richard Henderson
2022-05-01 5:50 ` [PATCH v4 25/45] target/arm: Move cortex impdef sysregs to cpu_tcg.c Richard Henderson
2022-05-01 5:50 ` [PATCH v4 26/45] target/arm: Update qemu-system-arm -cpu max to cortex-a57 Richard Henderson
2022-05-01 5:50 ` [PATCH v4 27/45] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Richard Henderson
2022-05-01 5:50 ` [PATCH v4 28/45] target/arm: Split out aa32_max_features Richard Henderson
2022-05-01 5:50 ` [PATCH v4 29/45] target/arm: Annotate arm_max_initfn with FEAT identifiers Richard Henderson
2022-05-01 5:50 ` [PATCH v4 30/45] target/arm: Use field names for manipulating EL2 and EL3 modes Richard Henderson
2022-05-01 5:50 ` [PATCH v4 31/45] target/arm: Enable FEAT_Debugv8p2 for -cpu max Richard Henderson
2022-05-01 5:50 ` [PATCH v4 32/45] target/arm: Enable FEAT_Debugv8p4 " Richard Henderson
2022-05-01 5:50 ` [PATCH v4 33/45] target/arm: Add isar_feature_{aa64,any}_ras Richard Henderson
2022-05-01 5:50 ` [PATCH v4 34/45] target/arm: Add minimal RAS registers Richard Henderson
2022-05-03 16:58 ` Peter Maydell
2022-05-01 5:50 ` [PATCH v4 35/45] target/arm: Enable SCR and HCR bits for RAS Richard Henderson
2022-05-01 5:50 ` [PATCH v4 36/45] target/arm: Implement virtual SError exceptions Richard Henderson
2022-05-01 5:50 ` [PATCH v4 37/45] target/arm: Implement ESB instruction Richard Henderson
2022-05-01 5:50 ` [PATCH v4 38/45] target/arm: Enable FEAT_RAS for -cpu max Richard Henderson
2022-05-01 5:50 ` [PATCH v4 39/45] target/arm: Enable FEAT_IESB " Richard Henderson
2022-05-01 5:50 ` [PATCH v4 40/45] target/arm: Enable FEAT_CSV2 " Richard Henderson
2022-05-01 5:50 ` [PATCH v4 41/45] target/arm: Enable FEAT_CSV2_2 " Richard Henderson
2022-05-03 17:10 ` Peter Maydell
2022-05-03 19:33 ` Richard Henderson
2022-05-01 5:50 ` [PATCH v4 42/45] target/arm: Enable FEAT_CSV3 " Richard Henderson
2022-05-01 5:50 ` [PATCH v4 43/45] target/arm: Enable FEAT_DGH " Richard Henderson
2022-05-01 5:50 ` [PATCH v4 44/45] target/arm: Define cortex-a76 Richard Henderson
2022-05-01 5:50 ` [PATCH v4 45/45] target/arm: Define neoverse-n1 Richard Henderson
2022-05-03 16:47 ` [PATCH v4 00/45] target/arm: Cleanups, new features, new cpus Peter Maydell
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