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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>, qemu-arm@nongnu.org
Subject: [PATCH v4 37/45] target/arm: Implement ESB instruction
Date: Sat, 30 Apr 2022 22:50:19 -0700	[thread overview]
Message-ID: <20220501055028.646596-38-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org>

Check for and defer any pending virtual SError.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Retain m-profile check; improve comments.
---
 target/arm/helper.h        |  1 +
 target/arm/a32.decode      | 16 ++++++++------
 target/arm/t32.decode      | 18 ++++++++--------
 target/arm/op_helper.c     | 43 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-a64.c | 17 +++++++++++++++
 target/arm/translate.c     | 23 ++++++++++++++++++++
 6 files changed, 103 insertions(+), 15 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index b463d9343b..b1334e0c42 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -54,6 +54,7 @@ DEF_HELPER_1(wfe, void, env)
 DEF_HELPER_1(yield, void, env)
 DEF_HELPER_1(pre_hvc, void, env)
 DEF_HELPER_2(pre_smc, void, env, i32)
+DEF_HELPER_1(vesb, void, env)
 
 DEF_HELPER_3(cpsr_write, void, env, i32, i32)
 DEF_HELPER_2(cpsr_write_eret, void, env, i32)
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index fcd8cd4f7d..f2ca480949 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -187,13 +187,17 @@ SMULTT           .... 0001 0110 .... 0000 .... 1110 ....      @rd0mn
 
 {
   {
-    YIELD        ---- 0011 0010 0000 1111 ---- 0000 0001
-    WFE          ---- 0011 0010 0000 1111 ---- 0000 0010
-    WFI          ---- 0011 0010 0000 1111 ---- 0000 0011
+    [
+      YIELD      ---- 0011 0010 0000 1111 ---- 0000 0001
+      WFE        ---- 0011 0010 0000 1111 ---- 0000 0010
+      WFI        ---- 0011 0010 0000 1111 ---- 0000 0011
 
-    # TODO: Implement SEV, SEVL; may help SMP performance.
-    # SEV        ---- 0011 0010 0000 1111 ---- 0000 0100
-    # SEVL       ---- 0011 0010 0000 1111 ---- 0000 0101
+      # TODO: Implement SEV, SEVL; may help SMP performance.
+      # SEV      ---- 0011 0010 0000 1111 ---- 0000 0100
+      # SEVL     ---- 0011 0010 0000 1111 ---- 0000 0101
+
+      ESB        ---- 0011 0010 0000 1111 ---- 0001 0000
+    ]
 
     # The canonical nop ends in 00000000, but the whole of the
     # rest of the space executes as nop if otherwise unsupported.
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 78fadef9d6..f21ad0167a 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -364,17 +364,17 @@ CLZ              1111 1010 1011 ---- 1111 .... 1000 ....      @rdm
   [
     # Hints, and CPS
     {
-      YIELD      1111 0011 1010 1111 1000 0000 0000 0001
-      WFE        1111 0011 1010 1111 1000 0000 0000 0010
-      WFI        1111 0011 1010 1111 1000 0000 0000 0011
+      [
+        YIELD    1111 0011 1010 1111 1000 0000 0000 0001
+        WFE      1111 0011 1010 1111 1000 0000 0000 0010
+        WFI      1111 0011 1010 1111 1000 0000 0000 0011
 
-      # TODO: Implement SEV, SEVL; may help SMP performance.
-      # SEV      1111 0011 1010 1111 1000 0000 0000 0100
-      # SEVL     1111 0011 1010 1111 1000 0000 0000 0101
+        # TODO: Implement SEV, SEVL; may help SMP performance.
+        # SEV    1111 0011 1010 1111 1000 0000 0000 0100
+        # SEVL   1111 0011 1010 1111 1000 0000 0000 0101
 
-      # For M-profile minimal-RAS ESB can be a NOP, which is the
-      # default behaviour since it is in the hint space.
-      # ESB      1111 0011 1010 1111 1000 0000 0001 0000
+        ESB      1111 0011 1010 1111 1000 0000 0001 0000
+      ]
 
       # The canonical nop ends in 0000 0000, but the whole rest
       # of the space is "reserved hint, behaves as nop".
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 76499ffa14..390b6578a8 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -960,3 +960,46 @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr,
                      access_type, mmu_idx, ra);
     }
 }
+
+/*
+ * This function corresponds to AArch64.vESBOperation().
+ * Note that the AArch32 version is not functionally different.
+ */
+void HELPER(vesb)(CPUARMState *env)
+{
+    /*
+     * The EL2Enabled() check is done inside arm_hcr_el2_eff,
+     * and will return HCR_EL2.VSE == 0, so nothing happens.
+     */
+    uint64_t hcr = arm_hcr_el2_eff(env);
+    bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO);
+    bool pending = enabled && (hcr & HCR_VSE);
+    bool masked  = (env->daif & PSTATE_A);
+
+    /* If VSE pending and masked, defer the exception.  */
+    if (pending && masked) {
+        uint32_t syndrome;
+
+        if (arm_el_is_aa64(env, 1)) {
+            /* Copy across IDS and ISS from VSESR. */
+            syndrome = env->cp15.vsesr_el2 & 0x1ffffff;
+        } else {
+            ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal };
+
+            if (extended_addresses_enabled(env)) {
+                syndrome = arm_fi_to_lfsc(&fi);
+            } else {
+                syndrome = arm_fi_to_sfsc(&fi);
+            }
+            /* Copy across AET and ExT from VSESR. */
+            syndrome |= env->cp15.vsesr_el2 & 0xd000;
+        }
+
+        /* Set VDISR_EL2.A along with the syndrome. */
+        env->cp15.vdisr_el2 = syndrome | (1u << 31);
+
+        /* Clear pending virtual SError */
+        env->cp15.hcr_el2 &= ~HCR_VSE;
+        cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR);
+    }
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b80313670f..5a02e076b7 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1454,6 +1454,23 @@ static void handle_hint(DisasContext *s, uint32_t insn,
             gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
         }
         break;
+    case 0b10000: /* ESB */
+        /* Without RAS, we must implement this as NOP. */
+        if (dc_isar_feature(aa64_ras, s)) {
+            /*
+             * QEMU does not have a source of physical SErrors,
+             * so we are only concerned with virtual SErrors.
+             * The pseudocode in the ARM for this case is
+             *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
+             *      AArch64.vESBOperation();
+             * Most of the condition can be evaluated at translation time.
+             * Test for EL2 present, and defer test for SEL2 to runtime.
+             */
+            if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
+                gen_helper_vesb(cpu_env);
+            }
+        }
+        break;
     case 0b11000: /* PACIAZ */
         if (s->pauth_active) {
             gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4e19191ed5..87a899d638 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6239,6 +6239,29 @@ static bool trans_WFI(DisasContext *s, arg_WFI *a)
     return true;
 }
 
+static bool trans_ESB(DisasContext *s, arg_ESB *a)
+{
+    /*
+     * For M-profile, minimal-RAS ESB can be a NOP.
+     * Without RAS, we must implement this as NOP.
+     */
+    if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) {
+        /*
+         * QEMU does not have a source of physical SErrors,
+         * so we are only concerned with virtual SErrors.
+         * The pseudocode in the ARM for this case is
+         *   if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
+         *      AArch32.vESBOperation();
+         * Most of the condition can be evaluated at translation time.
+         * Test for EL2 present, and defer test for SEL2 to runtime.
+         */
+        if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
+            gen_helper_vesb(cpu_env);
+        }
+    }
+    return true;
+}
+
 static bool trans_NOP(DisasContext *s, arg_NOP *a)
 {
     return true;
-- 
2.34.1



  parent reply	other threads:[~2022-05-01  6:55 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-01  5:49 [PATCH v4 00/45] target/arm: Cleanups, new features, new cpus Richard Henderson
2022-05-01  5:49 ` [PATCH v4 01/45] target/arm: Split out cpregs.h Richard Henderson
2022-05-01  5:49 ` [PATCH v4 02/45] target/arm: Reorg CPAccessResult and access_check_cp_reg Richard Henderson
2022-05-01  5:49 ` [PATCH v4 03/45] target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h Richard Henderson
2022-05-01  5:49 ` [PATCH v4 04/45] target/arm: Make some more cpreg data static const Richard Henderson
2022-05-01  5:49 ` [PATCH v4 05/45] target/arm: Reorg ARMCPRegInfo type field bits Richard Henderson
2022-05-03 15:58   ` Peter Maydell
2022-05-01  5:49 ` [PATCH v4 06/45] target/arm: Avoid bare abort() or assert(0) Richard Henderson
2022-05-01 10:47   ` Peter Maydell
2022-05-01  5:49 ` [PATCH v4 07/45] target/arm: Change cpreg access permissions to enum Richard Henderson
2022-05-01  5:49 ` [PATCH v4 08/45] target/arm: Name CPState type Richard Henderson
2022-05-01  5:49 ` [PATCH v4 09/45] target/arm: Name CPSecureState type Richard Henderson
2022-05-01  5:49 ` [PATCH v4 10/45] target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases Richard Henderson
2022-05-03 15:59   ` Peter Maydell
2022-05-01  5:49 ` [PATCH v4 11/45] target/arm: Store cpregs key in the hash table directly Richard Henderson
2022-05-03 16:02   ` Peter Maydell
2022-05-01  5:49 ` [PATCH v4 12/45] target/arm: Merge allocation of the cpreg and its name Richard Henderson
2022-05-03 16:07   ` Peter Maydell
2022-05-01  5:49 ` [PATCH v4 13/45] target/arm: Hoist computation of key in add_cpreg_to_hashtable Richard Henderson
2022-05-03 16:13   ` Peter Maydell
2022-05-01  5:49 ` [PATCH v4 14/45] target/arm: Consolidate cpreg updates " Richard Henderson
2022-05-03 16:15   ` Peter Maydell
2022-05-01  5:49 ` [PATCH v4 15/45] target/arm: Use bool for is64 and ns " Richard Henderson
2022-05-03 16:15   ` Peter Maydell
2022-05-01  5:49 ` [PATCH v4 16/45] target/arm: Hoist isbanked computation " Richard Henderson
2022-05-03 16:16   ` Peter Maydell
2022-05-01  5:49 ` [PATCH v4 17/45] target/arm: Perform override check early " Richard Henderson
2022-05-03 16:21   ` Peter Maydell
2022-05-01  5:50 ` [PATCH v4 18/45] target/arm: Reformat comments " Richard Henderson
2022-05-03 16:22   ` Peter Maydell
2022-05-01  5:50 ` [PATCH v4 19/45] target/arm: Remove HOST_BIG_ENDIAN ifdef " Richard Henderson
2022-05-03 16:25   ` Peter Maydell
2022-05-01  5:50 ` [PATCH v4 20/45] target/arm: Handle cpreg registration for missing EL Richard Henderson
2022-05-03 16:34   ` Peter Maydell
2022-05-03 16:45     ` Richard Henderson
2022-05-03 16:50       ` Peter Maydell
2022-05-01  5:50 ` [PATCH v4 21/45] target/arm: Drop EL3 no EL2 fallbacks Richard Henderson
2022-05-03 17:13   ` Peter Maydell
2022-05-01  5:50 ` [PATCH v4 22/45] target/arm: Merge zcr reginfo Richard Henderson
2022-05-03 17:12   ` Peter Maydell
2022-05-01  5:50 ` [PATCH v4 23/45] target/arm: Add isar predicates for FEAT_Debugv8p2 Richard Henderson
2022-05-01  5:50 ` [PATCH v4 24/45] target/arm: Adjust definition of CONTEXTIDR_EL2 Richard Henderson
2022-05-01  5:50 ` [PATCH v4 25/45] target/arm: Move cortex impdef sysregs to cpu_tcg.c Richard Henderson
2022-05-01  5:50 ` [PATCH v4 26/45] target/arm: Update qemu-system-arm -cpu max to cortex-a57 Richard Henderson
2022-05-01  5:50 ` [PATCH v4 27/45] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Richard Henderson
2022-05-01  5:50 ` [PATCH v4 28/45] target/arm: Split out aa32_max_features Richard Henderson
2022-05-01  5:50 ` [PATCH v4 29/45] target/arm: Annotate arm_max_initfn with FEAT identifiers Richard Henderson
2022-05-01  5:50 ` [PATCH v4 30/45] target/arm: Use field names for manipulating EL2 and EL3 modes Richard Henderson
2022-05-01  5:50 ` [PATCH v4 31/45] target/arm: Enable FEAT_Debugv8p2 for -cpu max Richard Henderson
2022-05-01  5:50 ` [PATCH v4 32/45] target/arm: Enable FEAT_Debugv8p4 " Richard Henderson
2022-05-01  5:50 ` [PATCH v4 33/45] target/arm: Add isar_feature_{aa64,any}_ras Richard Henderson
2022-05-01  5:50 ` [PATCH v4 34/45] target/arm: Add minimal RAS registers Richard Henderson
2022-05-03 16:58   ` Peter Maydell
2022-05-01  5:50 ` [PATCH v4 35/45] target/arm: Enable SCR and HCR bits for RAS Richard Henderson
2022-05-01  5:50 ` [PATCH v4 36/45] target/arm: Implement virtual SError exceptions Richard Henderson
2022-05-01  5:50 ` Richard Henderson [this message]
2022-05-01  5:50 ` [PATCH v4 38/45] target/arm: Enable FEAT_RAS for -cpu max Richard Henderson
2022-05-01  5:50 ` [PATCH v4 39/45] target/arm: Enable FEAT_IESB " Richard Henderson
2022-05-01  5:50 ` [PATCH v4 40/45] target/arm: Enable FEAT_CSV2 " Richard Henderson
2022-05-01  5:50 ` [PATCH v4 41/45] target/arm: Enable FEAT_CSV2_2 " Richard Henderson
2022-05-03 17:10   ` Peter Maydell
2022-05-03 19:33     ` Richard Henderson
2022-05-01  5:50 ` [PATCH v4 42/45] target/arm: Enable FEAT_CSV3 " Richard Henderson
2022-05-01  5:50 ` [PATCH v4 43/45] target/arm: Enable FEAT_DGH " Richard Henderson
2022-05-01  5:50 ` [PATCH v4 44/45] target/arm: Define cortex-a76 Richard Henderson
2022-05-01  5:50 ` [PATCH v4 45/45] target/arm: Define neoverse-n1 Richard Henderson
2022-05-03 16:47 ` [PATCH v4 00/45] target/arm: Cleanups, new features, new cpus Peter Maydell

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