From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: "Lucas De Marchi" <lucas.demarchi@intel.com>, "José Roberto de Souza" <jose.souza@intel.com>, dri-devel@lists.freedesktop.org, "Tvrtko Ursulin" <tvrtko.ursulin@linux.intel.com> Subject: [PATCH v2 12/12] drm/i915/pvc: read fuses for link copy engines Date: Thu, 5 May 2022 14:38:12 -0700 [thread overview] Message-ID: <20220505213812.3979301-13-matthew.d.roper@intel.com> (raw) In-Reply-To: <20220505213812.3979301-1-matthew.d.roper@intel.com> From: Lucas De Marchi <lucas.demarchi@intel.com> The new Link Copy engines in PVC may be fused off according to the mslice_mask. Each bit of the MEML3_EN_MASK we read from the GEN10_MIRROR_FUSE3 register disables a pair of link copy engines. v2 (Tvrtko): - Minor cosmetic changes: s/u8/unsigned long/, use instance local variable. (Tvrtko) Bspec: 44483 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 29 +++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c6e93db134b1..1adbf34c3632 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -686,6 +686,34 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt) } } +static void engine_mask_apply_copy_fuses(struct intel_gt *gt) +{ + struct drm_i915_private *i915 = gt->i915; + struct intel_gt_info *info = >->info; + unsigned long meml3_mask; + unsigned long quad; + + meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3); + meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask); + + /* + * Link Copy engines may be fused off according to meml3_mask. Each + * bit is a quad that houses 2 Link Copy and two Sub Copy engines. + */ + for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) { + unsigned int instance = quad * 2 + 1; + intel_engine_mask_t mask = GENMASK(_BCS(instance + 1), + _BCS(instance)); + + if (mask & info->engine_mask) { + drm_dbg(&i915->drm, "bcs%u fused off\n", instance); + drm_dbg(&i915->drm, "bcs%u fused off\n", instance + 1); + + info->engine_mask &= ~mask; + } + } +} + /* * Determine which engines are fused off in our particular hardware. * Note that we have a catch-22 situation where we need to be able to access @@ -768,6 +796,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); engine_mask_apply_compute_fuses(gt); + engine_mask_apply_copy_fuses(gt); return info->engine_mask; } -- 2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Lucas De Marchi <lucas.demarchi@intel.com>, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v2 12/12] drm/i915/pvc: read fuses for link copy engines Date: Thu, 5 May 2022 14:38:12 -0700 [thread overview] Message-ID: <20220505213812.3979301-13-matthew.d.roper@intel.com> (raw) In-Reply-To: <20220505213812.3979301-1-matthew.d.roper@intel.com> From: Lucas De Marchi <lucas.demarchi@intel.com> The new Link Copy engines in PVC may be fused off according to the mslice_mask. Each bit of the MEML3_EN_MASK we read from the GEN10_MIRROR_FUSE3 register disables a pair of link copy engines. v2 (Tvrtko): - Minor cosmetic changes: s/u8/unsigned long/, use instance local variable. (Tvrtko) Bspec: 44483 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 29 +++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c6e93db134b1..1adbf34c3632 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -686,6 +686,34 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt) } } +static void engine_mask_apply_copy_fuses(struct intel_gt *gt) +{ + struct drm_i915_private *i915 = gt->i915; + struct intel_gt_info *info = >->info; + unsigned long meml3_mask; + unsigned long quad; + + meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3); + meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask); + + /* + * Link Copy engines may be fused off according to meml3_mask. Each + * bit is a quad that houses 2 Link Copy and two Sub Copy engines. + */ + for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) { + unsigned int instance = quad * 2 + 1; + intel_engine_mask_t mask = GENMASK(_BCS(instance + 1), + _BCS(instance)); + + if (mask & info->engine_mask) { + drm_dbg(&i915->drm, "bcs%u fused off\n", instance); + drm_dbg(&i915->drm, "bcs%u fused off\n", instance + 1); + + info->engine_mask &= ~mask; + } + } +} + /* * Determine which engines are fused off in our particular hardware. * Note that we have a catch-22 situation where we need to be able to access @@ -768,6 +796,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); engine_mask_apply_compute_fuses(gt); + engine_mask_apply_copy_fuses(gt); return info->engine_mask; } -- 2.35.1
next prev parent reply other threads:[~2022-05-05 21:38 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-05 21:38 [PATCH v2 00/12] i915: Introduce Ponte Vecchio Matt Roper 2022-05-05 21:38 ` [Intel-gfx] " Matt Roper 2022-05-05 21:38 ` [PATCH v2 01/12] drm/i915/uncore: Reorganize and document shadow and forcewake tables Matt Roper 2022-05-05 21:38 ` [Intel-gfx] " Matt Roper 2022-05-05 21:38 ` [PATCH v2 02/12] drm/i915/pvc: Add forcewake support Matt Roper 2022-05-05 21:38 ` [Intel-gfx] " Matt Roper 2022-05-05 21:38 ` [PATCH v2 03/12] drm/i915/pvc: Define MOCS table for PVC Matt Roper 2022-05-05 21:38 ` [Intel-gfx] " Matt Roper 2022-05-06 17:08 ` Lucas De Marchi 2022-05-05 21:38 ` [PATCH v2 04/12] drm/i915/pvc: Read correct RP_STATE_CAP register Matt Roper 2022-05-05 21:38 ` [Intel-gfx] " Matt Roper 2022-05-05 21:38 ` [PATCH v2 05/12] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL Matt Roper 2022-05-05 21:38 ` [Intel-gfx] " Matt Roper 2022-05-06 17:23 ` Lucas De Marchi 2022-05-06 17:23 ` [Intel-gfx] " Lucas De Marchi 2022-05-06 17:32 ` Matt Roper 2022-05-06 17:32 ` [Intel-gfx] " Matt Roper 2022-05-11 5:45 ` Matt Roper 2022-05-11 5:45 ` [Intel-gfx] " Matt Roper 2022-05-05 21:38 ` [PATCH v2 06/12] drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine Matt Roper 2022-05-05 21:38 ` [Intel-gfx] " Matt Roper 2022-05-05 21:38 ` [PATCH v2 07/12] drm/i915/gvt: Use intel_engine_mask_t for ring mask Matt Roper 2022-05-05 21:38 ` [Intel-gfx] " Matt Roper 2022-05-10 6:05 ` Lucas De Marchi 2022-05-05 21:38 ` [PATCH v2 08/12] drm/i915/pvc: Engine definitions for new copy engines Matt Roper 2022-05-05 21:38 ` [Intel-gfx] " Matt Roper 2022-05-05 21:38 ` [PATCH v2 09/12] drm/i915/pvc: Interrupt support " Matt Roper 2022-05-05 21:38 ` [Intel-gfx] " Matt Roper 2022-05-05 21:38 ` [PATCH v2 10/12] drm/i915/pvc: Reset " Matt Roper 2022-05-05 21:38 ` [Intel-gfx] " Matt Roper 2022-05-05 21:38 ` [PATCH v2 11/12] drm/i915/pvc: skip all copy engines from aux table invalidate Matt Roper 2022-05-05 21:38 ` [Intel-gfx] " Matt Roper 2022-05-05 21:38 ` Matt Roper [this message] 2022-05-05 21:38 ` [Intel-gfx] [PATCH v2 12/12] drm/i915/pvc: read fuses for link copy engines Matt Roper 2022-05-05 22:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Ponte Vecchio (rev2) Patchwork 2022-05-05 22:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-05-05 22:58 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2022-05-06 0:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Ponte Vecchio (rev3) Patchwork 2022-05-06 0:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-05-06 1:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-05-06 4:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2022-05-10 22:43 ` Matt Roper
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