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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	Zhi Wang <zhi.a.wang@intel.com>,
	dri-devel@lists.freedesktop.org
Subject: [PATCH v2 07/12] drm/i915/gvt: Use intel_engine_mask_t for ring mask
Date: Thu,  5 May 2022 14:38:07 -0700	[thread overview]
Message-ID: <20220505213812.3979301-8-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20220505213812.3979301-1-matthew.d.roper@intel.com>

When i915 adds additional PVC blitter instances (in an upcoming patch),
the definition of VECS0 will change from bit(10) to bit(18), causing
GVT's R_ALL mask to overflow the u16 storage that's currently used.
Let's replace the u16 with an intel_engine_mask_t to ensure we avoid
this.

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index b9eb75a2b400..0ba2a3455d99 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -428,7 +428,7 @@ struct cmd_info {
 #define R_VECS	BIT(VECS0)
 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
 	/* rings that support this cmd: BLT/RCS/VCS/VECS */
-	u16 rings;
+	intel_engine_mask_t rings;
 
 	/* devices that support this cmd: SNB/IVB/HSW/... */
 	u16 devices;
-- 
2.35.1


WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 07/12] drm/i915/gvt: Use intel_engine_mask_t for ring mask
Date: Thu,  5 May 2022 14:38:07 -0700	[thread overview]
Message-ID: <20220505213812.3979301-8-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20220505213812.3979301-1-matthew.d.roper@intel.com>

When i915 adds additional PVC blitter instances (in an upcoming patch),
the definition of VECS0 will change from bit(10) to bit(18), causing
GVT's R_ALL mask to overflow the u16 storage that's currently used.
Let's replace the u16 with an intel_engine_mask_t to ensure we avoid
this.

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index b9eb75a2b400..0ba2a3455d99 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -428,7 +428,7 @@ struct cmd_info {
 #define R_VECS	BIT(VECS0)
 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
 	/* rings that support this cmd: BLT/RCS/VCS/VECS */
-	u16 rings;
+	intel_engine_mask_t rings;
 
 	/* devices that support this cmd: SNB/IVB/HSW/... */
 	u16 devices;
-- 
2.35.1


  parent reply	other threads:[~2022-05-05 21:38 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-05 21:38 [PATCH v2 00/12] i915: Introduce Ponte Vecchio Matt Roper
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 01/12] drm/i915/uncore: Reorganize and document shadow and forcewake tables Matt Roper
2022-05-05 21:38   ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 02/12] drm/i915/pvc: Add forcewake support Matt Roper
2022-05-05 21:38   ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 03/12] drm/i915/pvc: Define MOCS table for PVC Matt Roper
2022-05-05 21:38   ` [Intel-gfx] " Matt Roper
2022-05-06 17:08   ` Lucas De Marchi
2022-05-05 21:38 ` [PATCH v2 04/12] drm/i915/pvc: Read correct RP_STATE_CAP register Matt Roper
2022-05-05 21:38   ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 05/12] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL Matt Roper
2022-05-05 21:38   ` [Intel-gfx] " Matt Roper
2022-05-06 17:23   ` Lucas De Marchi
2022-05-06 17:23     ` [Intel-gfx] " Lucas De Marchi
2022-05-06 17:32     ` Matt Roper
2022-05-06 17:32       ` [Intel-gfx] " Matt Roper
2022-05-11  5:45     ` Matt Roper
2022-05-11  5:45       ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 06/12] drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine Matt Roper
2022-05-05 21:38   ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` Matt Roper [this message]
2022-05-05 21:38   ` [Intel-gfx] [PATCH v2 07/12] drm/i915/gvt: Use intel_engine_mask_t for ring mask Matt Roper
2022-05-10  6:05   ` Lucas De Marchi
2022-05-05 21:38 ` [PATCH v2 08/12] drm/i915/pvc: Engine definitions for new copy engines Matt Roper
2022-05-05 21:38   ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 09/12] drm/i915/pvc: Interrupt support " Matt Roper
2022-05-05 21:38   ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 10/12] drm/i915/pvc: Reset " Matt Roper
2022-05-05 21:38   ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 11/12] drm/i915/pvc: skip all copy engines from aux table invalidate Matt Roper
2022-05-05 21:38   ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 12/12] drm/i915/pvc: read fuses for link copy engines Matt Roper
2022-05-05 21:38   ` [Intel-gfx] " Matt Roper
2022-05-05 22:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Ponte Vecchio (rev2) Patchwork
2022-05-05 22:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-05 22:58 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-05-06  0:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Ponte Vecchio (rev3) Patchwork
2022-05-06  0:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-06  1:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-06  4:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-05-10 22:43   ` Matt Roper

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