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* [PATCH v5 00/10] PolarFire SoC dt for 5.19
@ 2022-05-09 14:26 ` Conor Dooley
  0 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann

Hey all,
Got a few PolarFire SoC device tree related changes here for 5.19.

Firstly, patches 1 & 2 of this series supersede [0] & are unchanged
compared to that submission, figured it would just be easier to keep
all the changes in one series.

As discussed on irc, patch 3 removes the duplicated "microchip" from
the device tree files so that they follow a soc-board.dts & a
soc{,-fabric}.dtsi format.

Patch 5 makes the fabric dtsi board specific by renaming the file to
mpfs-icicle-kit-fabric.dtsi & including it in the dts rather than
mpfs.dtsi. Additionally this will allow other boards to define their
own reference fabric design. A revision specific compatible, added in
patch 4, is added to the dt also.

The remainder of the series adds a bare minimum devicetree for the
Sundance Polarberry.

Thanks,
Conor.

Changes since v4:
- Whitespace and status ordering changes in the polarberry dt pointed
  out by Heiko
- A new patch for same whitspace and status order changes, but applied
  to the icicle dt
- A reordering of the icicle dt alphabetically to match the formatting
  of the polarberry dt

Changes since v3:
- remove an extra line of wshitespace added to dt-binding
- remove unneeded "okay" status & sort status to node end
- sort polarberry dts entries in ~alphabetical order
- add a comment explaining why the second mac (mac0) is disabled on
  polarberry

Changes since v2:
- make ,icicle-reference compatible with ,mpfs & put it inside the enum

Changes since v1:
- fixed whitespace problems in the polarberry dts
- disabled mac0 for the polarberry as its port is on the optional
  carrier board

Conor Dooley (10):
  riscv: dts: microchip: remove icicle memory clocks
  riscv: dts: microchip: move sysctrlr out of soc bus
  riscv: dts: microchip: remove soc vendor from filenames
  dt-bindings: riscv: microchip: document icicle reference design
  riscv: dts: microchip: make the fabric dtsi board specific
  dt-bindings: vendor-prefixes: add Sundance DSP
  dt-bindings: riscv: microchip: add polarberry compatible string
  riscv: dts: microchip: add the sundance polarberry
  riscv: microchip: icicle: readability fixes
  riscv: dts: icicle: sort nodes alphabetically

 .../devicetree/bindings/riscv/microchip.yaml  |   2 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 arch/riscv/boot/dts/microchip/Makefile        |   3 +-
 ...abric.dtsi => mpfs-icicle-kit-fabric.dtsi} |   2 +
 ...pfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 105 +++++++++---------
 .../dts/microchip/mpfs-polarberry-fabric.dtsi |  16 +++
 .../boot/dts/microchip/mpfs-polarberry.dts    |  99 +++++++++++++++++
 .../{microchip-mpfs.dtsi => mpfs.dtsi}        |  11 +-
 8 files changed, 181 insertions(+), 59 deletions(-)
 rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)
 rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (95%)
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
 rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (98%)

-- 
2.35.2


^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH v5 00/10] PolarFire SoC dt for 5.19
@ 2022-05-09 14:26 ` Conor Dooley
  0 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann

Hey all,
Got a few PolarFire SoC device tree related changes here for 5.19.

Firstly, patches 1 & 2 of this series supersede [0] & are unchanged
compared to that submission, figured it would just be easier to keep
all the changes in one series.

As discussed on irc, patch 3 removes the duplicated "microchip" from
the device tree files so that they follow a soc-board.dts & a
soc{,-fabric}.dtsi format.

Patch 5 makes the fabric dtsi board specific by renaming the file to
mpfs-icicle-kit-fabric.dtsi & including it in the dts rather than
mpfs.dtsi. Additionally this will allow other boards to define their
own reference fabric design. A revision specific compatible, added in
patch 4, is added to the dt also.

The remainder of the series adds a bare minimum devicetree for the
Sundance Polarberry.

Thanks,
Conor.

Changes since v4:
- Whitespace and status ordering changes in the polarberry dt pointed
  out by Heiko
- A new patch for same whitspace and status order changes, but applied
  to the icicle dt
- A reordering of the icicle dt alphabetically to match the formatting
  of the polarberry dt

Changes since v3:
- remove an extra line of wshitespace added to dt-binding
- remove unneeded "okay" status & sort status to node end
- sort polarberry dts entries in ~alphabetical order
- add a comment explaining why the second mac (mac0) is disabled on
  polarberry

Changes since v2:
- make ,icicle-reference compatible with ,mpfs & put it inside the enum

Changes since v1:
- fixed whitespace problems in the polarberry dts
- disabled mac0 for the polarberry as its port is on the optional
  carrier board

Conor Dooley (10):
  riscv: dts: microchip: remove icicle memory clocks
  riscv: dts: microchip: move sysctrlr out of soc bus
  riscv: dts: microchip: remove soc vendor from filenames
  dt-bindings: riscv: microchip: document icicle reference design
  riscv: dts: microchip: make the fabric dtsi board specific
  dt-bindings: vendor-prefixes: add Sundance DSP
  dt-bindings: riscv: microchip: add polarberry compatible string
  riscv: dts: microchip: add the sundance polarberry
  riscv: microchip: icicle: readability fixes
  riscv: dts: icicle: sort nodes alphabetically

 .../devicetree/bindings/riscv/microchip.yaml  |   2 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 arch/riscv/boot/dts/microchip/Makefile        |   3 +-
 ...abric.dtsi => mpfs-icicle-kit-fabric.dtsi} |   2 +
 ...pfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 105 +++++++++---------
 .../dts/microchip/mpfs-polarberry-fabric.dtsi |  16 +++
 .../boot/dts/microchip/mpfs-polarberry.dts    |  99 +++++++++++++++++
 .../{microchip-mpfs.dtsi => mpfs.dtsi}        |  11 +-
 8 files changed, 181 insertions(+), 59 deletions(-)
 rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)
 rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (95%)
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
 rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (98%)

-- 
2.35.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH v5 01/10] riscv: dts: microchip: remove icicle memory clocks
  2022-05-09 14:26 ` Conor Dooley
@ 2022-05-09 14:26   ` Conor Dooley
  -1 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann

The clock properties in the icicle kit's memory entries cause dtbs_check
errors:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: /: memory@80000000: 'clocks' does not match any of the regexes: 'pinctrl-[0-9]+'

Get rid of the clocks to avoid the errors.

Reported-by: Palmer Dabbelt <palmer@rivosinc.com>
Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
Fixes: 5b28df37d311 ("riscv: dts: microchip: update peripherals in icicle kit device tree")
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index 3392153dd0f1..c71d6aa6137a 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -32,14 +32,12 @@ cpus {
 	ddrc_cache_lo: memory@80000000 {
 		device_type = "memory";
 		reg = <0x0 0x80000000 0x0 0x2e000000>;
-		clocks = <&clkcfg CLK_DDRC>;
 		status = "okay";
 	};
 
 	ddrc_cache_hi: memory@1000000000 {
 		device_type = "memory";
 		reg = <0x10 0x0 0x0 0x40000000>;
-		clocks = <&clkcfg CLK_DDRC>;
 		status = "okay";
 	};
 };
-- 
2.35.2


^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 01/10] riscv: dts: microchip: remove icicle memory clocks
@ 2022-05-09 14:26   ` Conor Dooley
  0 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann

The clock properties in the icicle kit's memory entries cause dtbs_check
errors:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: /: memory@80000000: 'clocks' does not match any of the regexes: 'pinctrl-[0-9]+'

Get rid of the clocks to avoid the errors.

Reported-by: Palmer Dabbelt <palmer@rivosinc.com>
Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
Fixes: 5b28df37d311 ("riscv: dts: microchip: update peripherals in icicle kit device tree")
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index 3392153dd0f1..c71d6aa6137a 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -32,14 +32,12 @@ cpus {
 	ddrc_cache_lo: memory@80000000 {
 		device_type = "memory";
 		reg = <0x0 0x80000000 0x0 0x2e000000>;
-		clocks = <&clkcfg CLK_DDRC>;
 		status = "okay";
 	};
 
 	ddrc_cache_hi: memory@1000000000 {
 		device_type = "memory";
 		reg = <0x10 0x0 0x0 0x40000000>;
-		clocks = <&clkcfg CLK_DDRC>;
 		status = "okay";
 	};
 };
-- 
2.35.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 02/10] riscv: dts: microchip: move sysctrlr out of soc bus
  2022-05-09 14:26 ` Conor Dooley
@ 2022-05-09 14:26   ` Conor Dooley
  -1 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann, Rob Herring

The MPFS system controller has no registers of its own, so move it out
of the soc node to avoid dtbs_check warnings:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: soc: syscontroller: {'compatible': ['microchip,mpfs-sys-controller'], 'mboxes': [[15, 0]], 'status': ['okay']} should not be valid under {'type': 'object'}

Reported-by: Palmer Dabbelt <palmer@rivosinc.com>
Suggested-by: Rob Herring <robh@kernel.org>
Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 746c4d4e7686..bf21a2edd180 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -146,6 +146,11 @@ refclk: mssrefclk {
 		#clock-cells = <0>;
 	};
 
+	syscontroller: syscontroller {
+		compatible = "microchip,mpfs-sys-controller";
+		mboxes = <&mbox 0>;
+	};
+
 	soc {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -446,10 +451,5 @@ mbox: mailbox@37020000 {
 			#mbox-cells = <1>;
 			status = "disabled";
 		};
-
-		syscontroller: syscontroller {
-			compatible = "microchip,mpfs-sys-controller";
-			mboxes = <&mbox 0>;
-		};
 	};
 };
-- 
2.35.2


^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 02/10] riscv: dts: microchip: move sysctrlr out of soc bus
@ 2022-05-09 14:26   ` Conor Dooley
  0 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann, Rob Herring

The MPFS system controller has no registers of its own, so move it out
of the soc node to avoid dtbs_check warnings:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: soc: syscontroller: {'compatible': ['microchip,mpfs-sys-controller'], 'mboxes': [[15, 0]], 'status': ['okay']} should not be valid under {'type': 'object'}

Reported-by: Palmer Dabbelt <palmer@rivosinc.com>
Suggested-by: Rob Herring <robh@kernel.org>
Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 746c4d4e7686..bf21a2edd180 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -146,6 +146,11 @@ refclk: mssrefclk {
 		#clock-cells = <0>;
 	};
 
+	syscontroller: syscontroller {
+		compatible = "microchip,mpfs-sys-controller";
+		mboxes = <&mbox 0>;
+	};
+
 	soc {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -446,10 +451,5 @@ mbox: mailbox@37020000 {
 			#mbox-cells = <1>;
 			status = "disabled";
 		};
-
-		syscontroller: syscontroller {
-			compatible = "microchip,mpfs-sys-controller";
-			mboxes = <&mbox 0>;
-		};
 	};
 };
-- 
2.35.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 03/10] riscv: dts: microchip: remove soc vendor from filenames
  2022-05-09 14:26 ` Conor Dooley
@ 2022-05-09 14:26   ` Conor Dooley
  -1 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann

Having the SoC vendor both as the directory and in the filename adds
little. Remove microchip from the filenames so that the files will
resemble the other directories in riscv (and arm64). The new names
follow a soc-board.dts & soc{,-fabric}.dtsi pattern.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/microchip/Makefile                          | 2 +-
 .../microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi}  | 0
 .../{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts}      | 2 +-
 .../riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} | 2 +-
 4 files changed, 3 insertions(+), 3 deletions(-)
 rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi} (100%)
 rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (98%)
 rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (99%)

diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index 855c1502d912..af3a5059b350 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
 obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
similarity index 100%
rename from arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
rename to arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
similarity index 98%
rename from arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index c71d6aa6137a..84b0015dfd47 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -3,7 +3,7 @@
 
 /dts-v1/;
 
-#include "microchip-mpfs.dtsi"
+#include "mpfs.dtsi"
 
 /* Clock frequency (in Hz) of the rtcclk */
 #define RTCCLK_FREQ		1000000
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
similarity index 99%
rename from arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
rename to arch/riscv/boot/dts/microchip/mpfs.dtsi
index bf21a2edd180..cc3386068c2d 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -3,7 +3,7 @@
 
 /dts-v1/;
 #include "dt-bindings/clock/microchip,mpfs-clock.h"
-#include "microchip-mpfs-fabric.dtsi"
+#include "mpfs-fabric.dtsi"
 
 / {
 	#address-cells = <2>;
-- 
2.35.2


^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 03/10] riscv: dts: microchip: remove soc vendor from filenames
@ 2022-05-09 14:26   ` Conor Dooley
  0 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann

Having the SoC vendor both as the directory and in the filename adds
little. Remove microchip from the filenames so that the files will
resemble the other directories in riscv (and arm64). The new names
follow a soc-board.dts & soc{,-fabric}.dtsi pattern.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/microchip/Makefile                          | 2 +-
 .../microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi}  | 0
 .../{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts}      | 2 +-
 .../riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} | 2 +-
 4 files changed, 3 insertions(+), 3 deletions(-)
 rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi} (100%)
 rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (98%)
 rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (99%)

diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index 855c1502d912..af3a5059b350 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
 obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
similarity index 100%
rename from arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
rename to arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
similarity index 98%
rename from arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index c71d6aa6137a..84b0015dfd47 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -3,7 +3,7 @@
 
 /dts-v1/;
 
-#include "microchip-mpfs.dtsi"
+#include "mpfs.dtsi"
 
 /* Clock frequency (in Hz) of the rtcclk */
 #define RTCCLK_FREQ		1000000
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
similarity index 99%
rename from arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
rename to arch/riscv/boot/dts/microchip/mpfs.dtsi
index bf21a2edd180..cc3386068c2d 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -3,7 +3,7 @@
 
 /dts-v1/;
 #include "dt-bindings/clock/microchip,mpfs-clock.h"
-#include "microchip-mpfs-fabric.dtsi"
+#include "mpfs-fabric.dtsi"
 
 / {
 	#address-cells = <2>;
-- 
2.35.2


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 04/10] dt-bindings: riscv: microchip: document icicle reference design
  2022-05-09 14:26 ` Conor Dooley
@ 2022-05-09 14:26   ` Conor Dooley
  -1 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann, Krzysztof Kozlowski

Add a compatible for the icicle kit's reference design. This represents
the FPGA fabric's contents & is versioned to denote which release of the
reference design it applies to.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 3f981e897126..822a711df9e9 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -20,6 +20,7 @@ properties:
     items:
       - enum:
           - microchip,mpfs-icicle-kit
+          - microchip,mpfs-icicle-reference-rtlv2203
       - const: microchip,mpfs
 
 additionalProperties: true
-- 
2.35.2


^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 04/10] dt-bindings: riscv: microchip: document icicle reference design
@ 2022-05-09 14:26   ` Conor Dooley
  0 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann, Krzysztof Kozlowski

Add a compatible for the icicle kit's reference design. This represents
the FPGA fabric's contents & is versioned to denote which release of the
reference design it applies to.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 3f981e897126..822a711df9e9 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -20,6 +20,7 @@ properties:
     items:
       - enum:
           - microchip,mpfs-icicle-kit
+          - microchip,mpfs-icicle-reference-rtlv2203
       - const: microchip,mpfs
 
 additionalProperties: true
-- 
2.35.2


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 05/10] riscv: dts: microchip: make the fabric dtsi board specific
  2022-05-09 14:26 ` Conor Dooley
@ 2022-05-09 14:26   ` Conor Dooley
  -1 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann

Currently mpfs-fabric.dtsi is included by mpfs.dtsi - which is fine
currently since there is only one board with this SoC upstream.

However if another board was added, it would include the fabric contents
of the Icicle Kit's reference design. To avoid this, rename
mpfs-fabric.dtsi to mpfs-icicle-kit-fabric.dtsi & include it in the dts
rather than mpfs.dtsi.

mpfs-icicle-kit-fabric.dtsi specifically matches the 22.03 reference
design for the icicle kit's FPGA fabric & an older version of the
design may not have the i2c or pwm devices - so add the compatible
string to document this.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../microchip/{mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} | 2 ++
 arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts               | 1 +
 arch/riscv/boot/dts/microchip/mpfs.dtsi                         | 1 -
 3 files changed, 3 insertions(+), 1 deletion(-)
 rename arch/riscv/boot/dts/microchip/{mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)

diff --git a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
similarity index 91%
rename from arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index ccaac3371cf9..0d28858b83f2 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -2,6 +2,8 @@
 /* Copyright (c) 2020-2021 Microchip Technology Inc */
 
 / {
+	compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs";
+
 	core_pwm0: pwm@41000000 {
 		compatible = "microchip,corepwm-rtl-v4";
 		reg = <0x0 0x41000000 0x0 0xF0>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 84b0015dfd47..739dfa52bed1 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -4,6 +4,7 @@
 /dts-v1/;
 
 #include "mpfs.dtsi"
+#include "mpfs-icicle-kit-fabric.dtsi"
 
 /* Clock frequency (in Hz) of the rtcclk */
 #define RTCCLK_FREQ		1000000
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index cc3386068c2d..695c4e2807f5 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -3,7 +3,6 @@
 
 /dts-v1/;
 #include "dt-bindings/clock/microchip,mpfs-clock.h"
-#include "mpfs-fabric.dtsi"
 
 / {
 	#address-cells = <2>;
-- 
2.35.2


^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 05/10] riscv: dts: microchip: make the fabric dtsi board specific
@ 2022-05-09 14:26   ` Conor Dooley
  0 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann

Currently mpfs-fabric.dtsi is included by mpfs.dtsi - which is fine
currently since there is only one board with this SoC upstream.

However if another board was added, it would include the fabric contents
of the Icicle Kit's reference design. To avoid this, rename
mpfs-fabric.dtsi to mpfs-icicle-kit-fabric.dtsi & include it in the dts
rather than mpfs.dtsi.

mpfs-icicle-kit-fabric.dtsi specifically matches the 22.03 reference
design for the icicle kit's FPGA fabric & an older version of the
design may not have the i2c or pwm devices - so add the compatible
string to document this.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../microchip/{mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} | 2 ++
 arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts               | 1 +
 arch/riscv/boot/dts/microchip/mpfs.dtsi                         | 1 -
 3 files changed, 3 insertions(+), 1 deletion(-)
 rename arch/riscv/boot/dts/microchip/{mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)

diff --git a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
similarity index 91%
rename from arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index ccaac3371cf9..0d28858b83f2 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -2,6 +2,8 @@
 /* Copyright (c) 2020-2021 Microchip Technology Inc */
 
 / {
+	compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs";
+
 	core_pwm0: pwm@41000000 {
 		compatible = "microchip,corepwm-rtl-v4";
 		reg = <0x0 0x41000000 0x0 0xF0>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 84b0015dfd47..739dfa52bed1 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -4,6 +4,7 @@
 /dts-v1/;
 
 #include "mpfs.dtsi"
+#include "mpfs-icicle-kit-fabric.dtsi"
 
 /* Clock frequency (in Hz) of the rtcclk */
 #define RTCCLK_FREQ		1000000
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index cc3386068c2d..695c4e2807f5 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -3,7 +3,6 @@
 
 /dts-v1/;
 #include "dt-bindings/clock/microchip,mpfs-clock.h"
-#include "mpfs-fabric.dtsi"
 
 / {
 	#address-cells = <2>;
-- 
2.35.2


_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 06/10] dt-bindings: vendor-prefixes: add Sundance DSP
  2022-05-09 14:26 ` Conor Dooley
@ 2022-05-09 14:26   ` Conor Dooley
  -1 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann, Krzysztof Kozlowski

Sundance DSP Inc. (https://www.sundancedsp.com/) is a supplier of
high-performance DSP and FPGA processor boards and I/O modules.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 01430973ecec..1d47a38c2a2e 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1197,6 +1197,8 @@ patternProperties:
     description: Summit microelectronics
   "^sunchip,.*":
     description: Shenzhen Sunchip Technology Co., Ltd
+  "^sundance,.*":
+    description: Sundance DSP Inc.
   "^sunplus,.*":
     description: Sunplus Technology Co., Ltd.
   "^SUNW,.*":
-- 
2.35.2


_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 06/10] dt-bindings: vendor-prefixes: add Sundance DSP
@ 2022-05-09 14:26   ` Conor Dooley
  0 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann, Krzysztof Kozlowski

Sundance DSP Inc. (https://www.sundancedsp.com/) is a supplier of
high-performance DSP and FPGA processor boards and I/O modules.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 01430973ecec..1d47a38c2a2e 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1197,6 +1197,8 @@ patternProperties:
     description: Summit microelectronics
   "^sunchip,.*":
     description: Shenzhen Sunchip Technology Co., Ltd
+  "^sundance,.*":
+    description: Sundance DSP Inc.
   "^sunplus,.*":
     description: Sunplus Technology Co., Ltd.
   "^SUNW,.*":
-- 
2.35.2


^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 07/10] dt-bindings: riscv: microchip: add polarberry compatible string
  2022-05-09 14:26 ` Conor Dooley
@ 2022-05-09 14:26   ` Conor Dooley
  -1 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann, Krzysztof Kozlowski

Add a binding for the Sundance Polarberry board.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 822a711df9e9..1aa7336a9672 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -21,6 +21,7 @@ properties:
       - enum:
           - microchip,mpfs-icicle-kit
           - microchip,mpfs-icicle-reference-rtlv2203
+          - sundance,polarberry
       - const: microchip,mpfs
 
 additionalProperties: true
-- 
2.35.2


_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 07/10] dt-bindings: riscv: microchip: add polarberry compatible string
@ 2022-05-09 14:26   ` Conor Dooley
  0 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann, Krzysztof Kozlowski

Add a binding for the Sundance Polarberry board.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 822a711df9e9..1aa7336a9672 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -21,6 +21,7 @@ properties:
       - enum:
           - microchip,mpfs-icicle-kit
           - microchip,mpfs-icicle-reference-rtlv2203
+          - sundance,polarberry
       - const: microchip,mpfs
 
 additionalProperties: true
-- 
2.35.2


^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 08/10] riscv: dts: microchip: add the sundance polarberry
  2022-05-09 14:26 ` Conor Dooley
@ 2022-05-09 14:26   ` Conor Dooley
  -1 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann

Add a minimal device tree for the PolarFire SoC based Sundance
PolarBerry.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/microchip/Makefile        |  1 +
 .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 +++
 .../boot/dts/microchip/mpfs-polarberry.dts    | 99 +++++++++++++++++++
 3 files changed, 116 insertions(+)
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts

diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index af3a5059b350..39aae7b04f1c 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
 obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
new file mode 100644
index 000000000000..49380c428ec9
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2022 Microchip Technology Inc */
+
+/ {
+	fabric_clk3: fabric-clk3 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <62500000>;
+	};
+
+	fabric_clk1: fabric-clk1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
new file mode 100644
index 000000000000..82c93c8f5c17
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2022 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-polarberry-fabric.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define MTIMER_FREQ	1000000
+
+/ {
+	model = "Sundance PolarBerry";
+	compatible = "sundance,polarberry", "microchip,mpfs";
+
+	aliases {
+		ethernet0 = &mac1;
+		serial0 = &mmuart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	cpus {
+		timebase-frequency = <MTIMER_FREQ>;
+	};
+
+	ddrc_cache_lo: memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x2e000000>;
+	};
+
+	ddrc_cache_hi: memory@1000000000 {
+		device_type = "memory";
+		reg = <0x10 0x00000000 0x0 0xC0000000>;
+	};
+};
+
+/*
+ * phy0 is connected to mac0, but the port itself is on the (optional) carrier
+ * board.
+ */
+&mac0 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy0>;
+	status = "disabled";
+};
+
+&mac1 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy1>;
+	status = "okay";
+
+	phy1: ethernet-phy@5 {
+		reg = <5>;
+		ti,fifo-depth = <0x01>;
+	};
+
+	phy0: ethernet-phy@4 {
+		reg = <4>;
+		ti,fifo-depth = <0x01>;
+	};
+};
+
+&mbox {
+	status = "okay";
+};
+
+&mmc {
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+	card-detect-delay = <200>;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&mmuart0 {
+	status = "okay";
+};
+
+&refclk {
+	clock-frequency = <125000000>;
+};
+
+&rtc {
+	status = "okay";
+};
+
+&syscontroller {
+	status = "okay";
+};
-- 
2.35.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 08/10] riscv: dts: microchip: add the sundance polarberry
@ 2022-05-09 14:26   ` Conor Dooley
  0 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann

Add a minimal device tree for the PolarFire SoC based Sundance
PolarBerry.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/microchip/Makefile        |  1 +
 .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 +++
 .../boot/dts/microchip/mpfs-polarberry.dts    | 99 +++++++++++++++++++
 3 files changed, 116 insertions(+)
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts

diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index af3a5059b350..39aae7b04f1c 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
 obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
new file mode 100644
index 000000000000..49380c428ec9
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2022 Microchip Technology Inc */
+
+/ {
+	fabric_clk3: fabric-clk3 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <62500000>;
+	};
+
+	fabric_clk1: fabric-clk1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
new file mode 100644
index 000000000000..82c93c8f5c17
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2022 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-polarberry-fabric.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define MTIMER_FREQ	1000000
+
+/ {
+	model = "Sundance PolarBerry";
+	compatible = "sundance,polarberry", "microchip,mpfs";
+
+	aliases {
+		ethernet0 = &mac1;
+		serial0 = &mmuart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	cpus {
+		timebase-frequency = <MTIMER_FREQ>;
+	};
+
+	ddrc_cache_lo: memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x2e000000>;
+	};
+
+	ddrc_cache_hi: memory@1000000000 {
+		device_type = "memory";
+		reg = <0x10 0x00000000 0x0 0xC0000000>;
+	};
+};
+
+/*
+ * phy0 is connected to mac0, but the port itself is on the (optional) carrier
+ * board.
+ */
+&mac0 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy0>;
+	status = "disabled";
+};
+
+&mac1 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy1>;
+	status = "okay";
+
+	phy1: ethernet-phy@5 {
+		reg = <5>;
+		ti,fifo-depth = <0x01>;
+	};
+
+	phy0: ethernet-phy@4 {
+		reg = <4>;
+		ti,fifo-depth = <0x01>;
+	};
+};
+
+&mbox {
+	status = "okay";
+};
+
+&mmc {
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+	card-detect-delay = <200>;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&mmuart0 {
+	status = "okay";
+};
+
+&refclk {
+	clock-frequency = <125000000>;
+};
+
+&rtc {
+	status = "okay";
+};
+
+&syscontroller {
+	status = "okay";
+};
-- 
2.35.2


^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 09/10] riscv: microchip: icicle: readability fixes
  2022-05-09 14:26 ` Conor Dooley
@ 2022-05-09 14:26   ` Conor Dooley
  -1 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann

Fix the sort order of the status properties, remove some
extra whitespace in the mmc entry & add whitespace to the mac entry
containing the phys so that the dt is easier to read.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 739dfa52bed1..9cd1a30edf2c 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -64,8 +64,6 @@ &mmuart4 {
 };
 
 &mmc {
-	status = "okay";
-
 	bus-width = <4>;
 	disable-wp;
 	cap-sd-highspeed;
@@ -77,6 +75,7 @@ &mmc {
 	sd-uhs-sdr25;
 	sd-uhs-sdr50;
 	sd-uhs-sdr104;
+	status = "okay";
 };
 
 &spi0 {
@@ -106,16 +105,19 @@ &i2c2 {
 &mac0 {
 	phy-mode = "sgmii";
 	phy-handle = <&phy0>;
+	status = "okay";
 };
 
 &mac1 {
-	status = "okay";
 	phy-mode = "sgmii";
 	phy-handle = <&phy1>;
+	status = "okay";
+
 	phy1: ethernet-phy@9 {
 		reg = <9>;
 		ti,fifo-depth = <0x1>;
 	};
+
 	phy0: ethernet-phy@8 {
 		reg = <8>;
 		ti,fifo-depth = <0x1>;
-- 
2.35.2


^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 09/10] riscv: microchip: icicle: readability fixes
@ 2022-05-09 14:26   ` Conor Dooley
  0 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann

Fix the sort order of the status properties, remove some
extra whitespace in the mmc entry & add whitespace to the mac entry
containing the phys so that the dt is easier to read.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 739dfa52bed1..9cd1a30edf2c 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -64,8 +64,6 @@ &mmuart4 {
 };
 
 &mmc {
-	status = "okay";
-
 	bus-width = <4>;
 	disable-wp;
 	cap-sd-highspeed;
@@ -77,6 +75,7 @@ &mmc {
 	sd-uhs-sdr25;
 	sd-uhs-sdr50;
 	sd-uhs-sdr104;
+	status = "okay";
 };
 
 &spi0 {
@@ -106,16 +105,19 @@ &i2c2 {
 &mac0 {
 	phy-mode = "sgmii";
 	phy-handle = <&phy0>;
+	status = "okay";
 };
 
 &mac1 {
-	status = "okay";
 	phy-mode = "sgmii";
 	phy-handle = <&phy1>;
+	status = "okay";
+
 	phy1: ethernet-phy@9 {
 		reg = <9>;
 		ti,fifo-depth = <0x1>;
 	};
+
 	phy0: ethernet-phy@8 {
 		reg = <8>;
 		ti,fifo-depth = <0x1>;
-- 
2.35.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 10/10] riscv: dts: icicle: sort nodes alphabetically
  2022-05-09 14:26 ` Conor Dooley
@ 2022-05-09 14:26   ` Conor Dooley
  -1 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann

The icicle device tree is in a "random" order, so clean it up and sort
its elements alphabetically to match the newly added PolarBerry dts.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../boot/dts/microchip/mpfs-icicle-kit.dts    | 104 +++++++++---------
 1 file changed, 52 insertions(+), 52 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 9cd1a30edf2c..044982a11df5 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -43,23 +43,57 @@ ddrc_cache_hi: memory@1000000000 {
 	};
 };
 
-&refclk {
-	clock-frequency = <125000000>;
+&core_pwm0 {
+	status = "okay";
 };
 
-&mmuart1 {
+&gpio2 {
+	interrupts = <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>;
 	status = "okay";
 };
 
-&mmuart2 {
+&i2c0 {
 	status = "okay";
 };
 
-&mmuart3 {
+&i2c1 {
 	status = "okay";
 };
 
-&mmuart4 {
+&i2c2 {
+	status = "okay";
+};
+
+&mac0 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy0>;
+	status = "okay";
+};
+
+&mac1 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy1>;
+	status = "okay";
+
+	phy1: ethernet-phy@9 {
+		reg = <9>;
+		ti,fifo-depth = <0x1>;
+	};
+
+	phy0: ethernet-phy@8 {
+		reg = <8>;
+		ti,fifo-depth = <0x1>;
+	};
+};
+
+&mbox {
 	status = "okay";
 };
 
@@ -78,74 +112,43 @@ &mmc {
 	status = "okay";
 };
 
-&spi0 {
-	status = "okay";
-};
-
-&spi1 {
-	status = "okay";
-};
-
-&qspi {
+&mmuart1 {
 	status = "okay";
 };
 
-&i2c0 {
+&mmuart2 {
 	status = "okay";
 };
 
-&i2c1 {
+&mmuart3 {
 	status = "okay";
 };
 
-&i2c2 {
+&mmuart4 {
 	status = "okay";
 };
 
-&mac0 {
-	phy-mode = "sgmii";
-	phy-handle = <&phy0>;
+&pcie {
 	status = "okay";
 };
 
-&mac1 {
-	phy-mode = "sgmii";
-	phy-handle = <&phy1>;
+&qspi {
 	status = "okay";
-
-	phy1: ethernet-phy@9 {
-		reg = <9>;
-		ti,fifo-depth = <0x1>;
-	};
-
-	phy0: ethernet-phy@8 {
-		reg = <8>;
-		ti,fifo-depth = <0x1>;
-	};
 };
 
-&gpio2 {
-	interrupts = <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>;
-	status = "okay";
+&refclk {
+	clock-frequency = <125000000>;
 };
 
 &rtc {
 	status = "okay";
 };
 
-&usb {
+&spi0 {
 	status = "okay";
-	dr_mode = "host";
 };
 
-&mbox {
+&spi1 {
 	status = "okay";
 };
 
@@ -153,10 +156,7 @@ &syscontroller {
 	status = "okay";
 };
 
-&pcie {
-	status = "okay";
-};
-
-&core_pwm0 {
+&usb {
 	status = "okay";
+	dr_mode = "host";
 };
-- 
2.35.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH v5 10/10] riscv: dts: icicle: sort nodes alphabetically
@ 2022-05-09 14:26   ` Conor Dooley
  0 siblings, 0 replies; 34+ messages in thread
From: Conor Dooley @ 2022-05-09 14:26 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, heiko, Arnd Bergmann

The icicle device tree is in a "random" order, so clean it up and sort
its elements alphabetically to match the newly added PolarBerry dts.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../boot/dts/microchip/mpfs-icicle-kit.dts    | 104 +++++++++---------
 1 file changed, 52 insertions(+), 52 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 9cd1a30edf2c..044982a11df5 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -43,23 +43,57 @@ ddrc_cache_hi: memory@1000000000 {
 	};
 };
 
-&refclk {
-	clock-frequency = <125000000>;
+&core_pwm0 {
+	status = "okay";
 };
 
-&mmuart1 {
+&gpio2 {
+	interrupts = <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>;
 	status = "okay";
 };
 
-&mmuart2 {
+&i2c0 {
 	status = "okay";
 };
 
-&mmuart3 {
+&i2c1 {
 	status = "okay";
 };
 
-&mmuart4 {
+&i2c2 {
+	status = "okay";
+};
+
+&mac0 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy0>;
+	status = "okay";
+};
+
+&mac1 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy1>;
+	status = "okay";
+
+	phy1: ethernet-phy@9 {
+		reg = <9>;
+		ti,fifo-depth = <0x1>;
+	};
+
+	phy0: ethernet-phy@8 {
+		reg = <8>;
+		ti,fifo-depth = <0x1>;
+	};
+};
+
+&mbox {
 	status = "okay";
 };
 
@@ -78,74 +112,43 @@ &mmc {
 	status = "okay";
 };
 
-&spi0 {
-	status = "okay";
-};
-
-&spi1 {
-	status = "okay";
-};
-
-&qspi {
+&mmuart1 {
 	status = "okay";
 };
 
-&i2c0 {
+&mmuart2 {
 	status = "okay";
 };
 
-&i2c1 {
+&mmuart3 {
 	status = "okay";
 };
 
-&i2c2 {
+&mmuart4 {
 	status = "okay";
 };
 
-&mac0 {
-	phy-mode = "sgmii";
-	phy-handle = <&phy0>;
+&pcie {
 	status = "okay";
 };
 
-&mac1 {
-	phy-mode = "sgmii";
-	phy-handle = <&phy1>;
+&qspi {
 	status = "okay";
-
-	phy1: ethernet-phy@9 {
-		reg = <9>;
-		ti,fifo-depth = <0x1>;
-	};
-
-	phy0: ethernet-phy@8 {
-		reg = <8>;
-		ti,fifo-depth = <0x1>;
-	};
 };
 
-&gpio2 {
-	interrupts = <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>;
-	status = "okay";
+&refclk {
+	clock-frequency = <125000000>;
 };
 
 &rtc {
 	status = "okay";
 };
 
-&usb {
+&spi0 {
 	status = "okay";
-	dr_mode = "host";
 };
 
-&mbox {
+&spi1 {
 	status = "okay";
 };
 
@@ -153,10 +156,7 @@ &syscontroller {
 	status = "okay";
 };
 
-&pcie {
-	status = "okay";
-};
-
-&core_pwm0 {
+&usb {
 	status = "okay";
+	dr_mode = "host";
 };
-- 
2.35.2


^ permalink raw reply related	[flat|nested] 34+ messages in thread
* Re: [PATCH v5 04/10] dt-bindings: riscv: microchip: document icicle reference design
  2022-05-09 14:26   ` Conor Dooley
@ 2022-05-11 13:33     ` Rob Herring
  -1 siblings, 0 replies; 34+ messages in thread
From: Rob Herring @ 2022-05-11 13:33 UTC (permalink / raw)
  To: Conor Dooley
  Cc: Daire McNamara, Albert Ou, Rob Herring, Krzysztof Kozlowski,
	Palmer Dabbelt, devicetree, Paul Walmsley, heiko, linux-kernel,
	Palmer Dabbelt, Arnd Bergmann, Krzysztof Kozlowski, Cyril Jean,
	linux-riscv

On Mon, 09 May 2022 15:26:05 +0100, Conor Dooley wrote:
> Add a compatible for the icicle kit's reference design. This represents
> the FPGA fabric's contents & is versioned to denote which release of the
> reference design it applies to.
> 
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH v5 04/10] dt-bindings: riscv: microchip: document icicle reference design
@ 2022-05-11 13:33     ` Rob Herring
  0 siblings, 0 replies; 34+ messages in thread
From: Rob Herring @ 2022-05-11 13:33 UTC (permalink / raw)
  To: Conor Dooley
  Cc: Daire McNamara, Albert Ou, Rob Herring, Krzysztof Kozlowski,
	Palmer Dabbelt, devicetree, Paul Walmsley, heiko, linux-kernel,
	Palmer Dabbelt, Arnd Bergmann, Krzysztof Kozlowski, Cyril Jean,
	linux-riscv

On Mon, 09 May 2022 15:26:05 +0100, Conor Dooley wrote:
> Add a compatible for the icicle kit's reference design. This represents
> the FPGA fabric's contents & is versioned to denote which release of the
> reference design it applies to.
> 
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH v5 10/10] riscv: dts: icicle: sort nodes alphabetically
  2022-05-09 14:26   ` Conor Dooley
@ 2022-05-15 19:51     ` Heiko Stübner
  -1 siblings, 0 replies; 34+ messages in thread
From: Heiko Stübner @ 2022-05-15 19:51 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt, Conor Dooley
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, Arnd Bergmann

Am Montag, 9. Mai 2022, 16:26:11 CEST schrieb Conor Dooley:
> The icicle device tree is in a "random" order, so clean it up and sort
> its elements alphabetically to match the newly added PolarBerry dts.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>




^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH v5 10/10] riscv: dts: icicle: sort nodes alphabetically
@ 2022-05-15 19:51     ` Heiko Stübner
  0 siblings, 0 replies; 34+ messages in thread
From: Heiko Stübner @ 2022-05-15 19:51 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt, Conor Dooley
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, Arnd Bergmann

Am Montag, 9. Mai 2022, 16:26:11 CEST schrieb Conor Dooley:
> The icicle device tree is in a "random" order, so clean it up and sort
> its elements alphabetically to match the newly added PolarBerry dts.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>




_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH v5 09/10] riscv: microchip: icicle: readability fixes
  2022-05-09 14:26   ` Conor Dooley
@ 2022-05-15 19:51     ` Heiko Stübner
  -1 siblings, 0 replies; 34+ messages in thread
From: Heiko Stübner @ 2022-05-15 19:51 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt, Conor Dooley
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, Arnd Bergmann

Am Montag, 9. Mai 2022, 16:26:10 CEST schrieb Conor Dooley:
> Fix the sort order of the status properties, remove some
> extra whitespace in the mmc entry & add whitespace to the mac entry
> containing the phys so that the dt is easier to read.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>




^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH v5 09/10] riscv: microchip: icicle: readability fixes
@ 2022-05-15 19:51     ` Heiko Stübner
  0 siblings, 0 replies; 34+ messages in thread
From: Heiko Stübner @ 2022-05-15 19:51 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt, Conor Dooley
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, Cyril Jean, devicetree, linux-riscv,
	linux-kernel, Arnd Bergmann

Am Montag, 9. Mai 2022, 16:26:10 CEST schrieb Conor Dooley:
> Fix the sort order of the status properties, remove some
> extra whitespace in the mmc entry & add whitespace to the mac entry
> containing the phys so that the dt is easier to read.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>




_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH v5 00/10] PolarFire SoC dt for 5.19
  2022-05-09 14:26 ` Conor Dooley
@ 2022-05-23 11:47   ` Conor.Dooley
  -1 siblings, 0 replies; 34+ messages in thread
From: Conor.Dooley @ 2022-05-23 11:47 UTC (permalink / raw)
  To: robh+dt, krzk+dt, palmer, palmer
  Cc: paul.walmsley, aou, Daire.McNamara, Cyril.Jean, devicetree,
	linux-riscv, linux-kernel, heiko, arnd

On 09/05/2022 15:26, Conor Dooley wrote:
> Hey all,
> Got a few PolarFire SoC device tree related changes here for 5.19.

Hey Palmer,
I know you're busy etc but I had been hoping you'd take this for
5.19. I know it's late, so nw if it's too late.
Thanks,
Conor.

> 
> Firstly, patches 1 & 2 of this series supersede [0] & are unchanged
> compared to that submission, figured it would just be easier to keep
> all the changes in one series.
> 
> As discussed on irc, patch 3 removes the duplicated "microchip" from
> the device tree files so that they follow a soc-board.dts & a
> soc{,-fabric}.dtsi format.
> 
> Patch 5 makes the fabric dtsi board specific by renaming the file to
> mpfs-icicle-kit-fabric.dtsi & including it in the dts rather than
> mpfs.dtsi. Additionally this will allow other boards to define their
> own reference fabric design. A revision specific compatible, added in
> patch 4, is added to the dt also.
> 
> The remainder of the series adds a bare minimum devicetree for the
> Sundance Polarberry.
> 
> Thanks,
> Conor.
> 
> Changes since v4:
> - Whitespace and status ordering changes in the polarberry dt pointed
>    out by Heiko
> - A new patch for same whitspace and status order changes, but applied
>    to the icicle dt
> - A reordering of the icicle dt alphabetically to match the formatting
>    of the polarberry dt
> 
> Changes since v3:
> - remove an extra line of wshitespace added to dt-binding
> - remove unneeded "okay" status & sort status to node end
> - sort polarberry dts entries in ~alphabetical order
> - add a comment explaining why the second mac (mac0) is disabled on
>    polarberry
> 
> Changes since v2:
> - make ,icicle-reference compatible with ,mpfs & put it inside the enum
> 
> Changes since v1:
> - fixed whitespace problems in the polarberry dts
> - disabled mac0 for the polarberry as its port is on the optional
>    carrier board
> 
> Conor Dooley (10):
>    riscv: dts: microchip: remove icicle memory clocks
>    riscv: dts: microchip: move sysctrlr out of soc bus
>    riscv: dts: microchip: remove soc vendor from filenames
>    dt-bindings: riscv: microchip: document icicle reference design
>    riscv: dts: microchip: make the fabric dtsi board specific
>    dt-bindings: vendor-prefixes: add Sundance DSP
>    dt-bindings: riscv: microchip: add polarberry compatible string
>    riscv: dts: microchip: add the sundance polarberry
>    riscv: microchip: icicle: readability fixes
>    riscv: dts: icicle: sort nodes alphabetically
> 
>   .../devicetree/bindings/riscv/microchip.yaml  |   2 +
>   .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
>   arch/riscv/boot/dts/microchip/Makefile        |   3 +-
>   ...abric.dtsi => mpfs-icicle-kit-fabric.dtsi} |   2 +
>   ...pfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 105 +++++++++---------
>   .../dts/microchip/mpfs-polarberry-fabric.dtsi |  16 +++
>   .../boot/dts/microchip/mpfs-polarberry.dts    |  99 +++++++++++++++++
>   .../{microchip-mpfs.dtsi => mpfs.dtsi}        |  11 +-
>   8 files changed, 181 insertions(+), 59 deletions(-)
>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)
>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (95%)
>   create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
>   create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (98%)
> 


^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH v5 00/10] PolarFire SoC dt for 5.19
@ 2022-05-23 11:47   ` Conor.Dooley
  0 siblings, 0 replies; 34+ messages in thread
From: Conor.Dooley @ 2022-05-23 11:47 UTC (permalink / raw)
  To: robh+dt, krzk+dt, palmer, palmer
  Cc: paul.walmsley, aou, Daire.McNamara, Cyril.Jean, devicetree,
	linux-riscv, linux-kernel, heiko, arnd

On 09/05/2022 15:26, Conor Dooley wrote:
> Hey all,
> Got a few PolarFire SoC device tree related changes here for 5.19.

Hey Palmer,
I know you're busy etc but I had been hoping you'd take this for
5.19. I know it's late, so nw if it's too late.
Thanks,
Conor.

> 
> Firstly, patches 1 & 2 of this series supersede [0] & are unchanged
> compared to that submission, figured it would just be easier to keep
> all the changes in one series.
> 
> As discussed on irc, patch 3 removes the duplicated "microchip" from
> the device tree files so that they follow a soc-board.dts & a
> soc{,-fabric}.dtsi format.
> 
> Patch 5 makes the fabric dtsi board specific by renaming the file to
> mpfs-icicle-kit-fabric.dtsi & including it in the dts rather than
> mpfs.dtsi. Additionally this will allow other boards to define their
> own reference fabric design. A revision specific compatible, added in
> patch 4, is added to the dt also.
> 
> The remainder of the series adds a bare minimum devicetree for the
> Sundance Polarberry.
> 
> Thanks,
> Conor.
> 
> Changes since v4:
> - Whitespace and status ordering changes in the polarberry dt pointed
>    out by Heiko
> - A new patch for same whitspace and status order changes, but applied
>    to the icicle dt
> - A reordering of the icicle dt alphabetically to match the formatting
>    of the polarberry dt
> 
> Changes since v3:
> - remove an extra line of wshitespace added to dt-binding
> - remove unneeded "okay" status & sort status to node end
> - sort polarberry dts entries in ~alphabetical order
> - add a comment explaining why the second mac (mac0) is disabled on
>    polarberry
> 
> Changes since v2:
> - make ,icicle-reference compatible with ,mpfs & put it inside the enum
> 
> Changes since v1:
> - fixed whitespace problems in the polarberry dts
> - disabled mac0 for the polarberry as its port is on the optional
>    carrier board
> 
> Conor Dooley (10):
>    riscv: dts: microchip: remove icicle memory clocks
>    riscv: dts: microchip: move sysctrlr out of soc bus
>    riscv: dts: microchip: remove soc vendor from filenames
>    dt-bindings: riscv: microchip: document icicle reference design
>    riscv: dts: microchip: make the fabric dtsi board specific
>    dt-bindings: vendor-prefixes: add Sundance DSP
>    dt-bindings: riscv: microchip: add polarberry compatible string
>    riscv: dts: microchip: add the sundance polarberry
>    riscv: microchip: icicle: readability fixes
>    riscv: dts: icicle: sort nodes alphabetically
> 
>   .../devicetree/bindings/riscv/microchip.yaml  |   2 +
>   .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
>   arch/riscv/boot/dts/microchip/Makefile        |   3 +-
>   ...abric.dtsi => mpfs-icicle-kit-fabric.dtsi} |   2 +
>   ...pfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 105 +++++++++---------
>   .../dts/microchip/mpfs-polarberry-fabric.dtsi |  16 +++
>   .../boot/dts/microchip/mpfs-polarberry.dts    |  99 +++++++++++++++++
>   .../{microchip-mpfs.dtsi => mpfs.dtsi}        |  11 +-
>   8 files changed, 181 insertions(+), 59 deletions(-)
>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)
>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (95%)
>   create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
>   create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (98%)
> 

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH v5 00/10] PolarFire SoC dt for 5.19
  2022-05-23 11:47   ` Conor.Dooley
@ 2022-06-02  2:07     ` Palmer Dabbelt
  -1 siblings, 0 replies; 34+ messages in thread
From: Palmer Dabbelt @ 2022-06-02  2:07 UTC (permalink / raw)
  To: Conor.Dooley
  Cc: robh+dt, krzk+dt, Paul Walmsley, aou, Daire.McNamara, Cyril.Jean,
	devicetree, linux-riscv, linux-kernel, heiko, Arnd Bergmann

On Mon, 23 May 2022 04:47:55 PDT (-0700), Conor.Dooley@microchip.com wrote:
> On 09/05/2022 15:26, Conor Dooley wrote:
>> Hey all,
>> Got a few PolarFire SoC device tree related changes here for 5.19.
> 
> Hey Palmer,
> I know you're busy etc but I had been hoping you'd take this for
> 5.19. I know it's late, so nw if it's too late.

It wasn't too late for me, this is on for-next.  Thanks!

> Thanks,
> Conor.
> 
>> 
>> Firstly, patches 1 & 2 of this series supersede [0] & are unchanged
>> compared to that submission, figured it would just be easier to keep
>> all the changes in one series.
>> 
>> As discussed on irc, patch 3 removes the duplicated "microchip" from
>> the device tree files so that they follow a soc-board.dts & a
>> soc{,-fabric}.dtsi format.
>> 
>> Patch 5 makes the fabric dtsi board specific by renaming the file to
>> mpfs-icicle-kit-fabric.dtsi & including it in the dts rather than
>> mpfs.dtsi. Additionally this will allow other boards to define their
>> own reference fabric design. A revision specific compatible, added in
>> patch 4, is added to the dt also.
>> 
>> The remainder of the series adds a bare minimum devicetree for the
>> Sundance Polarberry.
>> 
>> Thanks,
>> Conor.
>> 
>> Changes since v4:
>> - Whitespace and status ordering changes in the polarberry dt pointed
>>    out by Heiko
>> - A new patch for same whitspace and status order changes, but applied
>>    to the icicle dt
>> - A reordering of the icicle dt alphabetically to match the formatting
>>    of the polarberry dt
>> 
>> Changes since v3:
>> - remove an extra line of wshitespace added to dt-binding
>> - remove unneeded "okay" status & sort status to node end
>> - sort polarberry dts entries in ~alphabetical order
>> - add a comment explaining why the second mac (mac0) is disabled on
>>    polarberry
>> 
>> Changes since v2:
>> - make ,icicle-reference compatible with ,mpfs & put it inside the enum
>> 
>> Changes since v1:
>> - fixed whitespace problems in the polarberry dts
>> - disabled mac0 for the polarberry as its port is on the optional
>>    carrier board
>> 
>> Conor Dooley (10):
>>    riscv: dts: microchip: remove icicle memory clocks
>>    riscv: dts: microchip: move sysctrlr out of soc bus
>>    riscv: dts: microchip: remove soc vendor from filenames
>>    dt-bindings: riscv: microchip: document icicle reference design
>>    riscv: dts: microchip: make the fabric dtsi board specific
>>    dt-bindings: vendor-prefixes: add Sundance DSP
>>    dt-bindings: riscv: microchip: add polarberry compatible string
>>    riscv: dts: microchip: add the sundance polarberry
>>    riscv: microchip: icicle: readability fixes
>>    riscv: dts: icicle: sort nodes alphabetically
>> 
>>   .../devicetree/bindings/riscv/microchip.yaml  |   2 +
>>   .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
>>   arch/riscv/boot/dts/microchip/Makefile        |   3 +-
>>   ...abric.dtsi => mpfs-icicle-kit-fabric.dtsi} |   2 +
>>   ...pfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 105 +++++++++---------
>>   .../dts/microchip/mpfs-polarberry-fabric.dtsi |  16 +++
>>   .../boot/dts/microchip/mpfs-polarberry.dts    |  99 +++++++++++++++++
>>   .../{microchip-mpfs.dtsi => mpfs.dtsi}        |  11 +-
>>   8 files changed, 181 insertions(+), 59 deletions(-)
>>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)
>>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (95%)
>>   create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
>>   create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (98%)
>> 
> 

^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH v5 00/10] PolarFire SoC dt for 5.19
@ 2022-06-02  2:07     ` Palmer Dabbelt
  0 siblings, 0 replies; 34+ messages in thread
From: Palmer Dabbelt @ 2022-06-02  2:07 UTC (permalink / raw)
  To: Conor.Dooley
  Cc: robh+dt, krzk+dt, Paul Walmsley, aou, Daire.McNamara, Cyril.Jean,
	devicetree, linux-riscv, linux-kernel, heiko, Arnd Bergmann

On Mon, 23 May 2022 04:47:55 PDT (-0700), Conor.Dooley@microchip.com wrote:
> On 09/05/2022 15:26, Conor Dooley wrote:
>> Hey all,
>> Got a few PolarFire SoC device tree related changes here for 5.19.
> 
> Hey Palmer,
> I know you're busy etc but I had been hoping you'd take this for
> 5.19. I know it's late, so nw if it's too late.

It wasn't too late for me, this is on for-next.  Thanks!

> Thanks,
> Conor.
> 
>> 
>> Firstly, patches 1 & 2 of this series supersede [0] & are unchanged
>> compared to that submission, figured it would just be easier to keep
>> all the changes in one series.
>> 
>> As discussed on irc, patch 3 removes the duplicated "microchip" from
>> the device tree files so that they follow a soc-board.dts & a
>> soc{,-fabric}.dtsi format.
>> 
>> Patch 5 makes the fabric dtsi board specific by renaming the file to
>> mpfs-icicle-kit-fabric.dtsi & including it in the dts rather than
>> mpfs.dtsi. Additionally this will allow other boards to define their
>> own reference fabric design. A revision specific compatible, added in
>> patch 4, is added to the dt also.
>> 
>> The remainder of the series adds a bare minimum devicetree for the
>> Sundance Polarberry.
>> 
>> Thanks,
>> Conor.
>> 
>> Changes since v4:
>> - Whitespace and status ordering changes in the polarberry dt pointed
>>    out by Heiko
>> - A new patch for same whitspace and status order changes, but applied
>>    to the icicle dt
>> - A reordering of the icicle dt alphabetically to match the formatting
>>    of the polarberry dt
>> 
>> Changes since v3:
>> - remove an extra line of wshitespace added to dt-binding
>> - remove unneeded "okay" status & sort status to node end
>> - sort polarberry dts entries in ~alphabetical order
>> - add a comment explaining why the second mac (mac0) is disabled on
>>    polarberry
>> 
>> Changes since v2:
>> - make ,icicle-reference compatible with ,mpfs & put it inside the enum
>> 
>> Changes since v1:
>> - fixed whitespace problems in the polarberry dts
>> - disabled mac0 for the polarberry as its port is on the optional
>>    carrier board
>> 
>> Conor Dooley (10):
>>    riscv: dts: microchip: remove icicle memory clocks
>>    riscv: dts: microchip: move sysctrlr out of soc bus
>>    riscv: dts: microchip: remove soc vendor from filenames
>>    dt-bindings: riscv: microchip: document icicle reference design
>>    riscv: dts: microchip: make the fabric dtsi board specific
>>    dt-bindings: vendor-prefixes: add Sundance DSP
>>    dt-bindings: riscv: microchip: add polarberry compatible string
>>    riscv: dts: microchip: add the sundance polarberry
>>    riscv: microchip: icicle: readability fixes
>>    riscv: dts: icicle: sort nodes alphabetically
>> 
>>   .../devicetree/bindings/riscv/microchip.yaml  |   2 +
>>   .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
>>   arch/riscv/boot/dts/microchip/Makefile        |   3 +-
>>   ...abric.dtsi => mpfs-icicle-kit-fabric.dtsi} |   2 +
>>   ...pfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 105 +++++++++---------
>>   .../dts/microchip/mpfs-polarberry-fabric.dtsi |  16 +++
>>   .../boot/dts/microchip/mpfs-polarberry.dts    |  99 +++++++++++++++++
>>   .../{microchip-mpfs.dtsi => mpfs.dtsi}        |  11 +-
>>   8 files changed, 181 insertions(+), 59 deletions(-)
>>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)
>>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (95%)
>>   create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
>>   create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (98%)
>> 
> 

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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH v5 00/10] PolarFire SoC dt for 5.19
  2022-06-02  2:07     ` Palmer Dabbelt
@ 2022-06-02  4:39       ` Conor.Dooley
  -1 siblings, 0 replies; 34+ messages in thread
From: Conor.Dooley @ 2022-06-02  4:39 UTC (permalink / raw)
  To: palmer
  Cc: robh+dt, krzk+dt, paul.walmsley, aou, Daire.McNamara, Cyril.Jean,
	devicetree, linux-riscv, linux-kernel, heiko, arnd

On 02/06/2022 03:07, Palmer Dabbelt wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Mon, 23 May 2022 04:47:55 PDT (-0700), Conor.Dooley@microchip.com wrote:
>> On 09/05/2022 15:26, Conor Dooley wrote:
>>> Hey all,
>>> Got a few PolarFire SoC device tree related changes here for 5.19.
>>
>> Hey Palmer,
>> I know you're busy etc but I had been hoping you'd take this for
>> 5.19. I know it's late, so nw if it's too late.
> 
> It wasn't too late for me, this is on for-next.  Thanks!

Thanks

> 
>> Thanks,
>> Conor.
>>
>>>
>>> Firstly, patches 1 & 2 of this series supersede [0] & are unchanged
>>> compared to that submission, figured it would just be easier to keep
>>> all the changes in one series.
>>>
>>> As discussed on irc, patch 3 removes the duplicated "microchip" from
>>> the device tree files so that they follow a soc-board.dts & a
>>> soc{,-fabric}.dtsi format.
>>>
>>> Patch 5 makes the fabric dtsi board specific by renaming the file to
>>> mpfs-icicle-kit-fabric.dtsi & including it in the dts rather than
>>> mpfs.dtsi. Additionally this will allow other boards to define their
>>> own reference fabric design. A revision specific compatible, added in
>>> patch 4, is added to the dt also.
>>>
>>> The remainder of the series adds a bare minimum devicetree for the
>>> Sundance Polarberry.
>>>
>>> Thanks,
>>> Conor.
>>>
>>> Changes since v4:
>>> - Whitespace and status ordering changes in the polarberry dt pointed
>>>    out by Heiko
>>> - A new patch for same whitspace and status order changes, but applied
>>>    to the icicle dt
>>> - A reordering of the icicle dt alphabetically to match the formatting
>>>    of the polarberry dt
>>>
>>> Changes since v3:
>>> - remove an extra line of wshitespace added to dt-binding
>>> - remove unneeded "okay" status & sort status to node end
>>> - sort polarberry dts entries in ~alphabetical order
>>> - add a comment explaining why the second mac (mac0) is disabled on
>>>    polarberry
>>>
>>> Changes since v2:
>>> - make ,icicle-reference compatible with ,mpfs & put it inside the enum
>>>
>>> Changes since v1:
>>> - fixed whitespace problems in the polarberry dts
>>> - disabled mac0 for the polarberry as its port is on the optional
>>>    carrier board
>>>
>>> Conor Dooley (10):
>>>    riscv: dts: microchip: remove icicle memory clocks
>>>    riscv: dts: microchip: move sysctrlr out of soc bus
>>>    riscv: dts: microchip: remove soc vendor from filenames
>>>    dt-bindings: riscv: microchip: document icicle reference design
>>>    riscv: dts: microchip: make the fabric dtsi board specific
>>>    dt-bindings: vendor-prefixes: add Sundance DSP
>>>    dt-bindings: riscv: microchip: add polarberry compatible string
>>>    riscv: dts: microchip: add the sundance polarberry
>>>    riscv: microchip: icicle: readability fixes
>>>    riscv: dts: icicle: sort nodes alphabetically
>>>
>>>   .../devicetree/bindings/riscv/microchip.yaml  |   2 +
>>>   .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
>>>   arch/riscv/boot/dts/microchip/Makefile        |   3 +-
>>>   ...abric.dtsi => mpfs-icicle-kit-fabric.dtsi} |   2 +
>>>   ...pfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 105 +++++++++---------
>>>   .../dts/microchip/mpfs-polarberry-fabric.dtsi |  16 +++
>>>   .../boot/dts/microchip/mpfs-polarberry.dts    |  99 +++++++++++++++++
>>>   .../{microchip-mpfs.dtsi => mpfs.dtsi}        |  11 +-
>>>   8 files changed, 181 insertions(+), 59 deletions(-)
>>>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)
>>>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (95%)
>>>   create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
>>>   create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>>>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (98%)
>>>
>>

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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH v5 00/10] PolarFire SoC dt for 5.19
@ 2022-06-02  4:39       ` Conor.Dooley
  0 siblings, 0 replies; 34+ messages in thread
From: Conor.Dooley @ 2022-06-02  4:39 UTC (permalink / raw)
  To: palmer
  Cc: robh+dt, krzk+dt, paul.walmsley, aou, Daire.McNamara, Cyril.Jean,
	devicetree, linux-riscv, linux-kernel, heiko, arnd

On 02/06/2022 03:07, Palmer Dabbelt wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Mon, 23 May 2022 04:47:55 PDT (-0700), Conor.Dooley@microchip.com wrote:
>> On 09/05/2022 15:26, Conor Dooley wrote:
>>> Hey all,
>>> Got a few PolarFire SoC device tree related changes here for 5.19.
>>
>> Hey Palmer,
>> I know you're busy etc but I had been hoping you'd take this for
>> 5.19. I know it's late, so nw if it's too late.
> 
> It wasn't too late for me, this is on for-next.  Thanks!

Thanks

> 
>> Thanks,
>> Conor.
>>
>>>
>>> Firstly, patches 1 & 2 of this series supersede [0] & are unchanged
>>> compared to that submission, figured it would just be easier to keep
>>> all the changes in one series.
>>>
>>> As discussed on irc, patch 3 removes the duplicated "microchip" from
>>> the device tree files so that they follow a soc-board.dts & a
>>> soc{,-fabric}.dtsi format.
>>>
>>> Patch 5 makes the fabric dtsi board specific by renaming the file to
>>> mpfs-icicle-kit-fabric.dtsi & including it in the dts rather than
>>> mpfs.dtsi. Additionally this will allow other boards to define their
>>> own reference fabric design. A revision specific compatible, added in
>>> patch 4, is added to the dt also.
>>>
>>> The remainder of the series adds a bare minimum devicetree for the
>>> Sundance Polarberry.
>>>
>>> Thanks,
>>> Conor.
>>>
>>> Changes since v4:
>>> - Whitespace and status ordering changes in the polarberry dt pointed
>>>    out by Heiko
>>> - A new patch for same whitspace and status order changes, but applied
>>>    to the icicle dt
>>> - A reordering of the icicle dt alphabetically to match the formatting
>>>    of the polarberry dt
>>>
>>> Changes since v3:
>>> - remove an extra line of wshitespace added to dt-binding
>>> - remove unneeded "okay" status & sort status to node end
>>> - sort polarberry dts entries in ~alphabetical order
>>> - add a comment explaining why the second mac (mac0) is disabled on
>>>    polarberry
>>>
>>> Changes since v2:
>>> - make ,icicle-reference compatible with ,mpfs & put it inside the enum
>>>
>>> Changes since v1:
>>> - fixed whitespace problems in the polarberry dts
>>> - disabled mac0 for the polarberry as its port is on the optional
>>>    carrier board
>>>
>>> Conor Dooley (10):
>>>    riscv: dts: microchip: remove icicle memory clocks
>>>    riscv: dts: microchip: move sysctrlr out of soc bus
>>>    riscv: dts: microchip: remove soc vendor from filenames
>>>    dt-bindings: riscv: microchip: document icicle reference design
>>>    riscv: dts: microchip: make the fabric dtsi board specific
>>>    dt-bindings: vendor-prefixes: add Sundance DSP
>>>    dt-bindings: riscv: microchip: add polarberry compatible string
>>>    riscv: dts: microchip: add the sundance polarberry
>>>    riscv: microchip: icicle: readability fixes
>>>    riscv: dts: icicle: sort nodes alphabetically
>>>
>>>   .../devicetree/bindings/riscv/microchip.yaml  |   2 +
>>>   .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
>>>   arch/riscv/boot/dts/microchip/Makefile        |   3 +-
>>>   ...abric.dtsi => mpfs-icicle-kit-fabric.dtsi} |   2 +
>>>   ...pfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 105 +++++++++---------
>>>   .../dts/microchip/mpfs-polarberry-fabric.dtsi |  16 +++
>>>   .../boot/dts/microchip/mpfs-polarberry.dts    |  99 +++++++++++++++++
>>>   .../{microchip-mpfs.dtsi => mpfs.dtsi}        |  11 +-
>>>   8 files changed, 181 insertions(+), 59 deletions(-)
>>>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)
>>>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (95%)
>>>   create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
>>>   create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>>>   rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (98%)
>>>
>>


^ permalink raw reply	[flat|nested] 34+ messages in thread
end of thread, other threads:[~2022-06-02  4:39 UTC | newest]

Thread overview: 34+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-09 14:26 [PATCH v5 00/10] PolarFire SoC dt for 5.19 Conor Dooley
2022-05-09 14:26 ` Conor Dooley
2022-05-09 14:26 ` [PATCH v5 01/10] riscv: dts: microchip: remove icicle memory clocks Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-09 14:26 ` [PATCH v5 02/10] riscv: dts: microchip: move sysctrlr out of soc bus Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-09 14:26 ` [PATCH v5 03/10] riscv: dts: microchip: remove soc vendor from filenames Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-09 14:26 ` [PATCH v5 04/10] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-11 13:33   ` Rob Herring
2022-05-11 13:33     ` Rob Herring
2022-05-09 14:26 ` [PATCH v5 05/10] riscv: dts: microchip: make the fabric dtsi board specific Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-09 14:26 ` [PATCH v5 06/10] dt-bindings: vendor-prefixes: add Sundance DSP Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-09 14:26 ` [PATCH v5 07/10] dt-bindings: riscv: microchip: add polarberry compatible string Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-09 14:26 ` [PATCH v5 08/10] riscv: dts: microchip: add the sundance polarberry Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-09 14:26 ` [PATCH v5 09/10] riscv: microchip: icicle: readability fixes Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-15 19:51   ` Heiko Stübner
2022-05-15 19:51     ` Heiko Stübner
2022-05-09 14:26 ` [PATCH v5 10/10] riscv: dts: icicle: sort nodes alphabetically Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-15 19:51   ` Heiko Stübner
2022-05-15 19:51     ` Heiko Stübner
2022-05-23 11:47 ` [PATCH v5 00/10] PolarFire SoC dt for 5.19 Conor.Dooley
2022-05-23 11:47   ` Conor.Dooley
2022-06-02  2:07   ` Palmer Dabbelt
2022-06-02  2:07     ` Palmer Dabbelt
2022-06-02  4:39     ` Conor.Dooley
2022-06-02  4:39       ` Conor.Dooley

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