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From: David Zhang <dingchen.zhang@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, David Zhang <dingchen.zhang@amd.com>,
	Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com, solomon.chiu@amd.com, jerry.zuo@amd.com,
	Aurabindo.Pillai@amd.com, wayne.lin@amd.com,
	Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com,
	pavle.kotarac@amd.com
Subject: [PATCH v2 13/19] drm/amd/display: PSRSU+DSC WA for specific TCON
Date: Tue, 10 May 2022 16:45:02 -0400	[thread overview]
Message-ID: <20220510204508.506089-14-dingchen.zhang@amd.com> (raw)
In-Reply-To: <20220510204508.506089-1-dingchen.zhang@amd.com>

[why]
Some specific TCON chip has HW limitation to support PSRSU+DSC.

[how]
Force ffu mode when DSC enabled if we detect it is the specific
model from sink OUI DPCD. And disable ABM update for this case.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  1 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 14 ++++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 251f2bbc96b9..5e7f70840e1a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -108,6 +108,7 @@ struct psr_settings {
 	 */
 	bool psr_frame_capture_indication_req;
 	unsigned int psr_sdp_transmit_line_num_deadline;
+	uint8_t force_ffu_mode;
 	unsigned int psr_power_opt;
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index e784002fe312..9ca0cbb0af9b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -349,6 +349,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 	copy_settings_data->debug.u32All = 0;
 	copy_settings_data->debug.bitfields.visual_confirm	= dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;
 	copy_settings_data->debug.bitfields.use_hw_lock_mgr		= 1;
+	copy_settings_data->debug.bitfields.force_full_frame_update	= 0;
 
 	if (psr_context->su_granularity_required == 0)
 		copy_settings_data->su_y_granularity = 0;
@@ -363,6 +364,19 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 	copy_settings_data->panel_inst = panel_inst;
 	copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);
 
+	/**
+	 * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update)
+	 * Note that PSRSU+DSC is still under development.
+	 */
+	if (copy_settings_data->dsc_enable_status &&
+		link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 &&
+		!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
+			sizeof(link->dpcd_caps.sink_dev_id_str)))
+		link->psr_settings.force_ffu_mode = 1;
+	else
+		link->psr_settings.force_ffu_mode = 0;
+	copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode;
+
 	if (link->fec_state == dc_link_fec_enabled &&
 		(!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
 			sizeof(link->dpcd_caps.sink_dev_id_str)) ||
-- 
2.25.1


  parent reply	other threads:[~2022-05-10 20:46 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-10 20:44 [PATCH v2 00/19] DC/DM changes needed for amdgpu PSR-SU David Zhang
2022-05-10 20:44 ` [PATCH v2 01/19] drm/amd/display: align dmub cmd header to latest dmub FW to support PSR-SU David Zhang
2022-05-10 20:44 ` [PATCH v2 02/19] drm/amd/display: feed PSR-SU as psr version to dmub FW David Zhang
2022-05-10 20:44 ` [PATCH v2 03/19] drm/amd/display: combine dirty rectangles in DMUB FW David Zhang
2022-05-10 20:44 ` [PATCH v2 04/19] drm/amd/display: update GSP1 generic info packet for PSRSU David Zhang
2022-05-10 20:44 ` [PATCH v2 05/19] drm/amd/display: revise Start/End SDP data David Zhang
2022-05-10 20:44 ` [PATCH v2 06/19] drm/amd/display: program PSR2 DPCD Configuration David Zhang
2022-05-10 20:44 ` [PATCH v2 07/19] drm/amd/display: Passing Y-granularity to dmub fw David Zhang
2022-05-10 20:44 ` [PATCH v2 08/19] drm/amd/display: Set default value of line_capture_indication David Zhang
2022-05-10 20:44 ` [PATCH v2 09/19] drm/amd/display: add vline time in micro sec to PSR context David Zhang
2022-05-10 20:44 ` [PATCH v2 10/19] drm/amd/display: fix system hang when PSR exits David Zhang
2022-05-10 20:45 ` [PATCH v2 11/19] drm/amd/display: Set PSR level to enable ALPM by default David Zhang
2022-05-10 20:45 ` [PATCH v2 12/19] drm/amd/display: use HW lock mgr for PSR-SU David Zhang
2022-05-10 20:45 ` David Zhang [this message]
2022-05-10 20:45 ` [PATCH v2 14/19] drm/amd/display: add shared helpers to update psr config fields to power module David Zhang
2022-05-10 20:45 ` [PATCH v2 15/19] drm/amd/display: calculate psr config settings in runtime in DM David Zhang
2022-05-10 20:45 ` [PATCH v2 16/19] drm/amd/display: update cursor position to DMUB FW David Zhang
2022-05-10 20:45 ` [PATCH v2 17/19] drm/amd/display: Implement MPO PSR SU David Zhang
2022-05-10 20:45 ` [PATCH v2 18/19] drm/amd/display: expose AMD source specific DPCD for FreeSync PSR support David Zhang
2022-05-10 20:45 ` [PATCH v2 19/19] drm/amd/display: PSR-SU rate control support in DC David Zhang
2022-05-19 15:37   ` Harry Wentland
2022-05-11 15:35 ` [PATCH v2 00/19] DC/DM changes needed for amdgpu PSR-SU Alex Deucher
2022-05-12 11:22   ` Daniel Vetter
2022-05-12 17:22     ` Zhang, Dingchen (David)
2022-05-12 17:39       ` Daniel Vetter
2022-05-16 16:23         ` Leo Li
2022-05-16 17:21           ` Daniel Vetter
2022-05-19 15:38 ` Harry Wentland

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