[PATCH 0/7] MediaTek Helio X10 MT6795 - Devicetree, part 1

[PATCH 0/7] MediaTek Helio X10 MT6795 - Devicetree, part 1

[AngeloGioacchino Del Regno]

In an effort to give some love to the apparently forgotten MT6795 SoC,
I am upstreaming more components that are necessary to support platforms
powered by this one apart from a simple boot to serial console.

This series modernizes the devicetree of the MT6795 SoC and adds a
couple of nodes that are supported by this SoC.

In my local tree I have much more than that (including the dts for
that Xperia M5 smartphone that I always mention...), but I decided
to push the devicetree commits in multiple parts, as to get these
in sooner than later because that reduces my delta, and this makes
upstreaming a bit easier, especially when having to rebase things
around, which happens a lot.

So, this series *does NOT* depends on any of the other series that
I've pushed and is mergeable in parallel.

Tested on a MT6795 Sony Xperia M5 (codename "Holly") smartphone.

AngeloGioacchino Del Regno (7):
  arm64: dts: mediatek: mt6795: Create soc bus node and move mmio
    devices
  arm64: dts: mediatek: mt6795: Add cpu-map and L2 cache
  arm64: dts: mediatek: mt6795: Add Cortex A53 PMU nodes
  arm64: dts: mediatek: mt6795: Add watchdog node to avoid timeouts
  arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs
  arm64: dts: mediatek: mt6795: Add general purpose timer node
  arm64: dts: mediatek: mt6795: Add ARM CCI-400 node and assign to CPUs

 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 244 ++++++++++++++++++-----
 1 file changed, 189 insertions(+), 55 deletions(-)

-- 
2.35.1

[PATCH 0/7] MediaTek Helio X10 MT6795 - Devicetree, part 1

[AngeloGioacchino Del Regno]

In an effort to give some love to the apparently forgotten MT6795 SoC,
I am upstreaming more components that are necessary to support platforms
powered by this one apart from a simple boot to serial console.

This series modernizes the devicetree of the MT6795 SoC and adds a
couple of nodes that are supported by this SoC.

In my local tree I have much more than that (including the dts for
that Xperia M5 smartphone that I always mention...), but I decided
to push the devicetree commits in multiple parts, as to get these
in sooner than later because that reduces my delta, and this makes
upstreaming a bit easier, especially when having to rebase things
around, which happens a lot.

So, this series *does NOT* depends on any of the other series that
I've pushed and is mergeable in parallel.

Tested on a MT6795 Sony Xperia M5 (codename "Holly") smartphone.

AngeloGioacchino Del Regno (7):
  arm64: dts: mediatek: mt6795: Create soc bus node and move mmio
    devices
  arm64: dts: mediatek: mt6795: Add cpu-map and L2 cache
  arm64: dts: mediatek: mt6795: Add Cortex A53 PMU nodes
  arm64: dts: mediatek: mt6795: Add watchdog node to avoid timeouts
  arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs
  arm64: dts: mediatek: mt6795: Add general purpose timer node
  arm64: dts: mediatek: mt6795: Add ARM CCI-400 node and assign to CPUs

 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 244 ++++++++++++++++++-----
 1 file changed, 189 insertions(+), 55 deletions(-)

-- 
2.35.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 0/7] MediaTek Helio X10 MT6795 - Devicetree, part 1

[AngeloGioacchino Del Regno]

In an effort to give some love to the apparently forgotten MT6795 SoC,
I am upstreaming more components that are necessary to support platforms
powered by this one apart from a simple boot to serial console.

This series modernizes the devicetree of the MT6795 SoC and adds a
couple of nodes that are supported by this SoC.

In my local tree I have much more than that (including the dts for
that Xperia M5 smartphone that I always mention...), but I decided
to push the devicetree commits in multiple parts, as to get these
in sooner than later because that reduces my delta, and this makes
upstreaming a bit easier, especially when having to rebase things
around, which happens a lot.

So, this series *does NOT* depends on any of the other series that
I've pushed and is mergeable in parallel.

Tested on a MT6795 Sony Xperia M5 (codename "Holly") smartphone.

AngeloGioacchino Del Regno (7):
  arm64: dts: mediatek: mt6795: Create soc bus node and move mmio
    devices
  arm64: dts: mediatek: mt6795: Add cpu-map and L2 cache
  arm64: dts: mediatek: mt6795: Add Cortex A53 PMU nodes
  arm64: dts: mediatek: mt6795: Add watchdog node to avoid timeouts
  arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs
  arm64: dts: mediatek: mt6795: Add general purpose timer node
  arm64: dts: mediatek: mt6795: Add ARM CCI-400 node and assign to CPUs

 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 244 ++++++++++++++++++-----
 1 file changed, 189 insertions(+), 55 deletions(-)

-- 
2.35.1


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH 1/7] arm64: dts: mediatek: mt6795: Create soc bus node and move mmio devices

[AngeloGioacchino Del Regno]

MMIO devices should be inside of a soc bus node, as it's done for the
vast majority of ARM64 devicetrees, and for almost all MTK devicetrees.
Create a simple-bus soc node and move all devices with a MMIO address
space in there.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 105 ++++++++++++-----------
 1 file changed, 56 insertions(+), 49 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index c85659d0ff5d..167f90bd991a 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -117,59 +117,66 @@ timer {
 			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
-	sysirq: intpol-controller@10200620 {
-		compatible = "mediatek,mt6795-sysirq",
-			     "mediatek,mt6577-sysirq";
-		interrupt-controller;
-		#interrupt-cells = <3>;
-		interrupt-parent = <&gic>;
-		reg = <0 0x10200620 0 0x20>;
-	};
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		sysirq: intpol-controller@10200620 {
+			compatible = "mediatek,mt6795-sysirq",
+				     "mediatek,mt6577-sysirq";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			reg = <0 0x10200620 0 0x20>;
+		};
 
-	gic: interrupt-controller@10221000 {
-		compatible = "arm,gic-400";
-		#interrupt-cells = <3>;
-		interrupt-parent = <&gic>;
-		interrupt-controller;
-		reg = <0 0x10221000 0 0x1000>,
-		      <0 0x10222000 0 0x2000>,
-		      <0 0x10224000 0 0x2000>,
-		      <0 0x10226000 0 0x2000>;
-	};
+		gic: interrupt-controller@10221000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			reg = <0 0x10221000 0 0x1000>,
+			      <0 0x10222000 0 0x2000>,
+			      <0 0x10224000 0 0x2000>,
+			      <0 0x10226000 0 0x2000>;
+		};
 
-	uart0: serial@11002000 {
-		compatible = "mediatek,mt6795-uart",
-			     "mediatek,mt6577-uart";
-		reg = <0 0x11002000 0 0x400>;
-		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&uart_clk>;
-		status = "disabled";
-	};
+		uart0: serial@11002000 {
+			compatible = "mediatek,mt6795-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11002000 0 0x400>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
 
-	uart1: serial@11003000 {
-		compatible = "mediatek,mt6795-uart",
-			     "mediatek,mt6577-uart";
-		reg = <0 0x11003000 0 0x400>;
-		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&uart_clk>;
-		status = "disabled";
-	};
+		uart1: serial@11003000 {
+			compatible = "mediatek,mt6795-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11003000 0 0x400>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
 
-	uart2: serial@11004000 {
-		compatible = "mediatek,mt6795-uart",
-			     "mediatek,mt6577-uart";
-		reg = <0 0x11004000 0 0x400>;
-		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&uart_clk>;
-		status = "disabled";
-	};
+		uart2: serial@11004000 {
+			compatible = "mediatek,mt6795-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11004000 0 0x400>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
 
-	uart3: serial@11005000 {
-		compatible = "mediatek,mt6795-uart",
-			     "mediatek,mt6577-uart";
-		reg = <0 0x11005000 0 0x400>;
-		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&uart_clk>;
-		status = "disabled";
+		uart3: serial@11005000 {
+			compatible = "mediatek,mt6795-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11005000 0 0x400>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
 	};
 };
-- 
2.35.1

[PATCH 1/7] arm64: dts: mediatek: mt6795: Create soc bus node and move mmio devices

[AngeloGioacchino Del Regno]

MMIO devices should be inside of a soc bus node, as it's done for the
vast majority of ARM64 devicetrees, and for almost all MTK devicetrees.
Create a simple-bus soc node and move all devices with a MMIO address
space in there.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 105 ++++++++++++-----------
 1 file changed, 56 insertions(+), 49 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index c85659d0ff5d..167f90bd991a 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -117,59 +117,66 @@ timer {
 			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
-	sysirq: intpol-controller@10200620 {
-		compatible = "mediatek,mt6795-sysirq",
-			     "mediatek,mt6577-sysirq";
-		interrupt-controller;
-		#interrupt-cells = <3>;
-		interrupt-parent = <&gic>;
-		reg = <0 0x10200620 0 0x20>;
-	};
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		sysirq: intpol-controller@10200620 {
+			compatible = "mediatek,mt6795-sysirq",
+				     "mediatek,mt6577-sysirq";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			reg = <0 0x10200620 0 0x20>;
+		};
 
-	gic: interrupt-controller@10221000 {
-		compatible = "arm,gic-400";
-		#interrupt-cells = <3>;
-		interrupt-parent = <&gic>;
-		interrupt-controller;
-		reg = <0 0x10221000 0 0x1000>,
-		      <0 0x10222000 0 0x2000>,
-		      <0 0x10224000 0 0x2000>,
-		      <0 0x10226000 0 0x2000>;
-	};
+		gic: interrupt-controller@10221000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			reg = <0 0x10221000 0 0x1000>,
+			      <0 0x10222000 0 0x2000>,
+			      <0 0x10224000 0 0x2000>,
+			      <0 0x10226000 0 0x2000>;
+		};
 
-	uart0: serial@11002000 {
-		compatible = "mediatek,mt6795-uart",
-			     "mediatek,mt6577-uart";
-		reg = <0 0x11002000 0 0x400>;
-		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&uart_clk>;
-		status = "disabled";
-	};
+		uart0: serial@11002000 {
+			compatible = "mediatek,mt6795-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11002000 0 0x400>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
 
-	uart1: serial@11003000 {
-		compatible = "mediatek,mt6795-uart",
-			     "mediatek,mt6577-uart";
-		reg = <0 0x11003000 0 0x400>;
-		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&uart_clk>;
-		status = "disabled";
-	};
+		uart1: serial@11003000 {
+			compatible = "mediatek,mt6795-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11003000 0 0x400>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
 
-	uart2: serial@11004000 {
-		compatible = "mediatek,mt6795-uart",
-			     "mediatek,mt6577-uart";
-		reg = <0 0x11004000 0 0x400>;
-		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&uart_clk>;
-		status = "disabled";
-	};
+		uart2: serial@11004000 {
+			compatible = "mediatek,mt6795-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11004000 0 0x400>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
 
-	uart3: serial@11005000 {
-		compatible = "mediatek,mt6795-uart",
-			     "mediatek,mt6577-uart";
-		reg = <0 0x11005000 0 0x400>;
-		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&uart_clk>;
-		status = "disabled";
+		uart3: serial@11005000 {
+			compatible = "mediatek,mt6795-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11005000 0 0x400>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
 	};
 };
-- 
2.35.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 1/7] arm64: dts: mediatek: mt6795: Create soc bus node and move mmio devices

[AngeloGioacchino Del Regno]

MMIO devices should be inside of a soc bus node, as it's done for the
vast majority of ARM64 devicetrees, and for almost all MTK devicetrees.
Create a simple-bus soc node and move all devices with a MMIO address
space in there.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 105 ++++++++++++-----------
 1 file changed, 56 insertions(+), 49 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index c85659d0ff5d..167f90bd991a 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -117,59 +117,66 @@ timer {
 			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
-	sysirq: intpol-controller@10200620 {
-		compatible = "mediatek,mt6795-sysirq",
-			     "mediatek,mt6577-sysirq";
-		interrupt-controller;
-		#interrupt-cells = <3>;
-		interrupt-parent = <&gic>;
-		reg = <0 0x10200620 0 0x20>;
-	};
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		sysirq: intpol-controller@10200620 {
+			compatible = "mediatek,mt6795-sysirq",
+				     "mediatek,mt6577-sysirq";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			reg = <0 0x10200620 0 0x20>;
+		};
 
-	gic: interrupt-controller@10221000 {
-		compatible = "arm,gic-400";
-		#interrupt-cells = <3>;
-		interrupt-parent = <&gic>;
-		interrupt-controller;
-		reg = <0 0x10221000 0 0x1000>,
-		      <0 0x10222000 0 0x2000>,
-		      <0 0x10224000 0 0x2000>,
-		      <0 0x10226000 0 0x2000>;
-	};
+		gic: interrupt-controller@10221000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			reg = <0 0x10221000 0 0x1000>,
+			      <0 0x10222000 0 0x2000>,
+			      <0 0x10224000 0 0x2000>,
+			      <0 0x10226000 0 0x2000>;
+		};
 
-	uart0: serial@11002000 {
-		compatible = "mediatek,mt6795-uart",
-			     "mediatek,mt6577-uart";
-		reg = <0 0x11002000 0 0x400>;
-		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&uart_clk>;
-		status = "disabled";
-	};
+		uart0: serial@11002000 {
+			compatible = "mediatek,mt6795-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11002000 0 0x400>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
 
-	uart1: serial@11003000 {
-		compatible = "mediatek,mt6795-uart",
-			     "mediatek,mt6577-uart";
-		reg = <0 0x11003000 0 0x400>;
-		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&uart_clk>;
-		status = "disabled";
-	};
+		uart1: serial@11003000 {
+			compatible = "mediatek,mt6795-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11003000 0 0x400>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
 
-	uart2: serial@11004000 {
-		compatible = "mediatek,mt6795-uart",
-			     "mediatek,mt6577-uart";
-		reg = <0 0x11004000 0 0x400>;
-		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&uart_clk>;
-		status = "disabled";
-	};
+		uart2: serial@11004000 {
+			compatible = "mediatek,mt6795-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11004000 0 0x400>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
 
-	uart3: serial@11005000 {
-		compatible = "mediatek,mt6795-uart",
-			     "mediatek,mt6577-uart";
-		reg = <0 0x11005000 0 0x400>;
-		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
-		clocks = <&uart_clk>;
-		status = "disabled";
+		uart3: serial@11005000 {
+			compatible = "mediatek,mt6795-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11005000 0 0x400>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
 	};
 };
-- 
2.35.1


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[PATCH 2/7] arm64: dts: mediatek: mt6795: Add cpu-map and L2 cache

[AngeloGioacchino Del Regno]

This SoC is HMP and has two clusters with four Cortex-A53 cores each:
declare a cpu map and, while at it, also add the next-level-cache
properties.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 56 ++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 167f90bd991a..1456b9035336 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -34,6 +34,7 @@ cpu0: cpu@0 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x000>;
+			next-level-cache = <&l2_0>;
 		};
 
 		cpu1: cpu@1 {
@@ -41,6 +42,7 @@ cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x001>;
+			next-level-cache = <&l2_0>;
 		};
 
 		cpu2: cpu@2 {
@@ -48,6 +50,7 @@ cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x002>;
+			next-level-cache = <&l2_0>;
 		};
 
 		cpu3: cpu@3 {
@@ -55,6 +58,7 @@ cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x003>;
+			next-level-cache = <&l2_0>;
 		};
 
 		cpu4: cpu@100 {
@@ -62,6 +66,7 @@ cpu4: cpu@100 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x100>;
+			next-level-cache = <&l2_1>;
 		};
 
 		cpu5: cpu@101 {
@@ -69,6 +74,7 @@ cpu5: cpu@101 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x101>;
+			next-level-cache = <&l2_1>;
 		};
 
 		cpu6: cpu@102 {
@@ -76,6 +82,7 @@ cpu6: cpu@102 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x102>;
+			next-level-cache = <&l2_1>;
 		};
 
 		cpu7: cpu@103 {
@@ -83,6 +90,55 @@ cpu7: cpu@103 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x103>;
+			next-level-cache = <&l2_1>;
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+
+				core1 {
+					cpu = <&cpu5>;
+				};
+
+				core2 {
+					cpu = <&cpu6>;
+				};
+
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		l2_0: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+		};
+
+		l2_1: l2-cache1 {
+			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 
-- 
2.35.1

[PATCH 2/7] arm64: dts: mediatek: mt6795: Add cpu-map and L2 cache

[AngeloGioacchino Del Regno]

This SoC is HMP and has two clusters with four Cortex-A53 cores each:
declare a cpu map and, while at it, also add the next-level-cache
properties.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 56 ++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 167f90bd991a..1456b9035336 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -34,6 +34,7 @@ cpu0: cpu@0 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x000>;
+			next-level-cache = <&l2_0>;
 		};
 
 		cpu1: cpu@1 {
@@ -41,6 +42,7 @@ cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x001>;
+			next-level-cache = <&l2_0>;
 		};
 
 		cpu2: cpu@2 {
@@ -48,6 +50,7 @@ cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x002>;
+			next-level-cache = <&l2_0>;
 		};
 
 		cpu3: cpu@3 {
@@ -55,6 +58,7 @@ cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x003>;
+			next-level-cache = <&l2_0>;
 		};
 
 		cpu4: cpu@100 {
@@ -62,6 +66,7 @@ cpu4: cpu@100 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x100>;
+			next-level-cache = <&l2_1>;
 		};
 
 		cpu5: cpu@101 {
@@ -69,6 +74,7 @@ cpu5: cpu@101 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x101>;
+			next-level-cache = <&l2_1>;
 		};
 
 		cpu6: cpu@102 {
@@ -76,6 +82,7 @@ cpu6: cpu@102 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x102>;
+			next-level-cache = <&l2_1>;
 		};
 
 		cpu7: cpu@103 {
@@ -83,6 +90,55 @@ cpu7: cpu@103 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x103>;
+			next-level-cache = <&l2_1>;
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+
+				core1 {
+					cpu = <&cpu5>;
+				};
+
+				core2 {
+					cpu = <&cpu6>;
+				};
+
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		l2_0: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+		};
+
+		l2_1: l2-cache1 {
+			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 
-- 
2.35.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 2/7] arm64: dts: mediatek: mt6795: Add cpu-map and L2 cache

[AngeloGioacchino Del Regno]

This SoC is HMP and has two clusters with four Cortex-A53 cores each:
declare a cpu map and, while at it, also add the next-level-cache
properties.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 56 ++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 167f90bd991a..1456b9035336 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -34,6 +34,7 @@ cpu0: cpu@0 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x000>;
+			next-level-cache = <&l2_0>;
 		};
 
 		cpu1: cpu@1 {
@@ -41,6 +42,7 @@ cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x001>;
+			next-level-cache = <&l2_0>;
 		};
 
 		cpu2: cpu@2 {
@@ -48,6 +50,7 @@ cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x002>;
+			next-level-cache = <&l2_0>;
 		};
 
 		cpu3: cpu@3 {
@@ -55,6 +58,7 @@ cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x003>;
+			next-level-cache = <&l2_0>;
 		};
 
 		cpu4: cpu@100 {
@@ -62,6 +66,7 @@ cpu4: cpu@100 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x100>;
+			next-level-cache = <&l2_1>;
 		};
 
 		cpu5: cpu@101 {
@@ -69,6 +74,7 @@ cpu5: cpu@101 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x101>;
+			next-level-cache = <&l2_1>;
 		};
 
 		cpu6: cpu@102 {
@@ -76,6 +82,7 @@ cpu6: cpu@102 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x102>;
+			next-level-cache = <&l2_1>;
 		};
 
 		cpu7: cpu@103 {
@@ -83,6 +90,55 @@ cpu7: cpu@103 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x103>;
+			next-level-cache = <&l2_1>;
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+
+				core1 {
+					cpu = <&cpu5>;
+				};
+
+				core2 {
+					cpu = <&cpu6>;
+				};
+
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		l2_0: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+		};
+
+		l2_1: l2-cache1 {
+			compatible = "cache";
+			cache-level = <2>;
 		};
 	};
 
-- 
2.35.1


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH 3/7] arm64: dts: mediatek: mt6795: Add Cortex A53 PMU nodes

[AngeloGioacchino Del Regno]

Add the required nodes to enable the PMU on this SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 1456b9035336..639104b3f693 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -160,6 +160,15 @@ uart_clk: dummy26m {
 		#clock-cells = <0>;
 	};
 
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI  8 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI  9 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupt-parent = <&gic>;
-- 
2.35.1

[PATCH 3/7] arm64: dts: mediatek: mt6795: Add Cortex A53 PMU nodes

[AngeloGioacchino Del Regno]

Add the required nodes to enable the PMU on this SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 1456b9035336..639104b3f693 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -160,6 +160,15 @@ uart_clk: dummy26m {
 		#clock-cells = <0>;
 	};
 
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI  8 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI  9 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupt-parent = <&gic>;
-- 
2.35.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 3/7] arm64: dts: mediatek: mt6795: Add Cortex A53 PMU nodes

[AngeloGioacchino Del Regno]

Add the required nodes to enable the PMU on this SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 1456b9035336..639104b3f693 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -160,6 +160,15 @@ uart_clk: dummy26m {
 		#clock-cells = <0>;
 	};
 
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI  8 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI  9 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupt-parent = <&gic>;
-- 
2.35.1


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH 4/7] arm64: dts: mediatek: mt6795: Add watchdog node to avoid timeouts

[AngeloGioacchino Del Regno]

At least on commercial devices like some smartphones, the bootloader
will initialize the SoC watchdog and set it to reboot the board when
it times out. The last pet that this watchdog is getting is right
before booting the kernel and left it enabled as a protection against
boot failure: this means that Linux is expected to initialize this
device and pet as soon as possible, or it will bark and reset the AP.

In order to prevent that, add the required watchdog node as default
enabled: this will have no side effects on boards that are not
performing the aforementioned watchdog setup before booting Linux.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 639104b3f693..363fa25b4edc 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -188,6 +188,14 @@ soc {
 		compatible = "simple-bus";
 		ranges;
 
+		watchdog: watchdog@10007000 {
+			compatible = "mediatek,mt6795-wdt";
+			reg = <0 0x10007000 0 0x100>;
+			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
+			#reset-cells = <1>;
+			timeout-sec = <20>;
+		};
+
 		sysirq: intpol-controller@10200620 {
 			compatible = "mediatek,mt6795-sysirq",
 				     "mediatek,mt6577-sysirq";
-- 
2.35.1

[PATCH 4/7] arm64: dts: mediatek: mt6795: Add watchdog node to avoid timeouts

[AngeloGioacchino Del Regno]

At least on commercial devices like some smartphones, the bootloader
will initialize the SoC watchdog and set it to reboot the board when
it times out. The last pet that this watchdog is getting is right
before booting the kernel and left it enabled as a protection against
boot failure: this means that Linux is expected to initialize this
device and pet as soon as possible, or it will bark and reset the AP.

In order to prevent that, add the required watchdog node as default
enabled: this will have no side effects on boards that are not
performing the aforementioned watchdog setup before booting Linux.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 639104b3f693..363fa25b4edc 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -188,6 +188,14 @@ soc {
 		compatible = "simple-bus";
 		ranges;
 
+		watchdog: watchdog@10007000 {
+			compatible = "mediatek,mt6795-wdt";
+			reg = <0 0x10007000 0 0x100>;
+			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
+			#reset-cells = <1>;
+			timeout-sec = <20>;
+		};
+
 		sysirq: intpol-controller@10200620 {
 			compatible = "mediatek,mt6795-sysirq",
 				     "mediatek,mt6577-sysirq";
-- 
2.35.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 4/7] arm64: dts: mediatek: mt6795: Add watchdog node to avoid timeouts

[AngeloGioacchino Del Regno]

At least on commercial devices like some smartphones, the bootloader
will initialize the SoC watchdog and set it to reboot the board when
it times out. The last pet that this watchdog is getting is right
before booting the kernel and left it enabled as a protection against
boot failure: this means that Linux is expected to initialize this
device and pet as soon as possible, or it will bark and reset the AP.

In order to prevent that, add the required watchdog node as default
enabled: this will have no side effects on boards that are not
performing the aforementioned watchdog setup before booting Linux.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 639104b3f693..363fa25b4edc 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -188,6 +188,14 @@ soc {
 		compatible = "simple-bus";
 		ranges;
 
+		watchdog: watchdog@10007000 {
+			compatible = "mediatek,mt6795-wdt";
+			reg = <0 0x10007000 0 0x100>;
+			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
+			#reset-cells = <1>;
+			timeout-sec = <20>;
+		};
+
 		sysirq: intpol-controller@10200620 {
 			compatible = "mediatek,mt6795-sysirq",
 				     "mediatek,mt6577-sysirq";
-- 
2.35.1


_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[AngeloGioacchino Del Regno]

Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to
provide a good initial clock spec, since this SoC features two always
on oscillators running at the aforementioned frequencies.
While at it, since the UART clock is actually referring to the 26MHz
oscillator, remove it and assign clk26m as "baud" clock for the UARTs.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 363fa25b4edc..b6f7681cc151 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -142,21 +142,23 @@ l2_1: l2-cache1 {
 		};
 	};
 
-	system_clk: dummy13m {
+	clk26m: oscillator-26m {
 		compatible = "fixed-clock";
-		clock-frequency = <13000000>;
 		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+		clock-output-names = "clk26m";
 	};
 
-	rtc_clk: dummy32k {
+	clk32k: oscillator-32k {
 		compatible = "fixed-clock";
-		clock-frequency = <32000>;
 		#clock-cells = <0>;
+		clock-frequency = <32000>;
+		clock-output-names = "clk32k";
 	};
 
-	uart_clk: dummy26m {
+	system_clk: dummy13m {
 		compatible = "fixed-clock";
-		clock-frequency = <26000000>;
+		clock-frequency = <13000000>;
 		#clock-cells = <0>;
 	};
 
@@ -221,7 +223,7 @@ uart0: serial@11002000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11002000 0 0x400>;
 			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&uart_clk>;
+			clocks = <&clk26m>;
 			status = "disabled";
 		};
 
@@ -230,7 +232,7 @@ uart1: serial@11003000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11003000 0 0x400>;
 			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&uart_clk>;
+			clocks = <&clk26m>;
 			status = "disabled";
 		};
 
@@ -239,7 +241,7 @@ uart2: serial@11004000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11004000 0 0x400>;
 			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&uart_clk>;
+			clocks = <&clk26m>;
 			status = "disabled";
 		};
 
@@ -248,7 +250,7 @@ uart3: serial@11005000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11005000 0 0x400>;
 			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&uart_clk>;
+			clocks = <&clk26m>;
 			status = "disabled";
 		};
 	};
-- 
2.35.1

[PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[AngeloGioacchino Del Regno]

Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to
provide a good initial clock spec, since this SoC features two always
on oscillators running at the aforementioned frequencies.
While at it, since the UART clock is actually referring to the 26MHz
oscillator, remove it and assign clk26m as "baud" clock for the UARTs.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 363fa25b4edc..b6f7681cc151 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -142,21 +142,23 @@ l2_1: l2-cache1 {
 		};
 	};
 
-	system_clk: dummy13m {
+	clk26m: oscillator-26m {
 		compatible = "fixed-clock";
-		clock-frequency = <13000000>;
 		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+		clock-output-names = "clk26m";
 	};
 
-	rtc_clk: dummy32k {
+	clk32k: oscillator-32k {
 		compatible = "fixed-clock";
-		clock-frequency = <32000>;
 		#clock-cells = <0>;
+		clock-frequency = <32000>;
+		clock-output-names = "clk32k";
 	};
 
-	uart_clk: dummy26m {
+	system_clk: dummy13m {
 		compatible = "fixed-clock";
-		clock-frequency = <26000000>;
+		clock-frequency = <13000000>;
 		#clock-cells = <0>;
 	};
 
@@ -221,7 +223,7 @@ uart0: serial@11002000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11002000 0 0x400>;
 			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&uart_clk>;
+			clocks = <&clk26m>;
 			status = "disabled";
 		};
 
@@ -230,7 +232,7 @@ uart1: serial@11003000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11003000 0 0x400>;
 			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&uart_clk>;
+			clocks = <&clk26m>;
 			status = "disabled";
 		};
 
@@ -239,7 +241,7 @@ uart2: serial@11004000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11004000 0 0x400>;
 			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&uart_clk>;
+			clocks = <&clk26m>;
 			status = "disabled";
 		};
 
@@ -248,7 +250,7 @@ uart3: serial@11005000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11005000 0 0x400>;
 			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&uart_clk>;
+			clocks = <&clk26m>;
 			status = "disabled";
 		};
 	};
-- 
2.35.1


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[PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[AngeloGioacchino Del Regno]

Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to
provide a good initial clock spec, since this SoC features two always
on oscillators running at the aforementioned frequencies.
While at it, since the UART clock is actually referring to the 26MHz
oscillator, remove it and assign clk26m as "baud" clock for the UARTs.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 363fa25b4edc..b6f7681cc151 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -142,21 +142,23 @@ l2_1: l2-cache1 {
 		};
 	};
 
-	system_clk: dummy13m {
+	clk26m: oscillator-26m {
 		compatible = "fixed-clock";
-		clock-frequency = <13000000>;
 		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+		clock-output-names = "clk26m";
 	};
 
-	rtc_clk: dummy32k {
+	clk32k: oscillator-32k {
 		compatible = "fixed-clock";
-		clock-frequency = <32000>;
 		#clock-cells = <0>;
+		clock-frequency = <32000>;
+		clock-output-names = "clk32k";
 	};
 
-	uart_clk: dummy26m {
+	system_clk: dummy13m {
 		compatible = "fixed-clock";
-		clock-frequency = <26000000>;
+		clock-frequency = <13000000>;
 		#clock-cells = <0>;
 	};
 
@@ -221,7 +223,7 @@ uart0: serial@11002000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11002000 0 0x400>;
 			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&uart_clk>;
+			clocks = <&clk26m>;
 			status = "disabled";
 		};
 
@@ -230,7 +232,7 @@ uart1: serial@11003000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11003000 0 0x400>;
 			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&uart_clk>;
+			clocks = <&clk26m>;
 			status = "disabled";
 		};
 
@@ -239,7 +241,7 @@ uart2: serial@11004000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11004000 0 0x400>;
 			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&uart_clk>;
+			clocks = <&clk26m>;
 			status = "disabled";
 		};
 
@@ -248,7 +250,7 @@ uart3: serial@11005000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11005000 0 0x400>;
 			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&uart_clk>;
+			clocks = <&clk26m>;
 			status = "disabled";
 		};
 	};
-- 
2.35.1


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Re: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[Krzysztof Kozlowski]

On 13/05/2022 19:16, AngeloGioacchino Del Regno wrote:
> Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to
> provide a good initial clock spec, since this SoC features two always

I don't understand that part with actual patch. You claim here you add
clocks, but in DTS they were already before.

Additionally, these clocks do not belong to DTSI because, AFAIU, these
are properties of boards. At least their frequencies should be moved to
the board DTS.



Best regards,
Krzysztof

Re: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[Krzysztof Kozlowski]

On 13/05/2022 19:16, AngeloGioacchino Del Regno wrote:
> Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to
> provide a good initial clock spec, since this SoC features two always

I don't understand that part with actual patch. You claim here you add
clocks, but in DTS they were already before.

Additionally, these clocks do not belong to DTSI because, AFAIU, these
are properties of boards. At least their frequencies should be moved to
the board DTS.



Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[Krzysztof Kozlowski]

On 13/05/2022 19:16, AngeloGioacchino Del Regno wrote:
> Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to
> provide a good initial clock spec, since this SoC features two always

I don't understand that part with actual patch. You claim here you add
clocks, but in DTS they were already before.

Additionally, these clocks do not belong to DTSI because, AFAIU, these
are properties of boards. At least their frequencies should be moved to
the board DTS.



Best regards,
Krzysztof

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[AngeloGioacchino Del Regno]

Il 16/05/22 09:10, Krzysztof Kozlowski ha scritto:
> On 13/05/2022 19:16, AngeloGioacchino Del Regno wrote:
>> Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to
>> provide a good initial clock spec, since this SoC features two always
> 
> I don't understand that part with actual patch. You claim here you add
> clocks, but in DTS they were already before.
> 
> Additionally, these clocks do not belong to DTSI because, AFAIU, these
> are properties of boards. At least their frequencies should be moved to
> the board DTS.
> 
> 

I should reword the commit description to be clearer, sorry about that: I
went with "exactly what I've done", but looking at the actual diff, it is
just a rename. What my brain was ticking on here was about removing clocks
that didn't really exist (uart_clk is not a fixed clock, etc), and adding
the ones that do exist.... but then again, the result, casually, is a rename.

In any case... no, these clocks are not board-specific for two reasons:
1. AFAIK, these fixed clock outputs are from the SoC itself, not from
    external components placed on the board, and
2. Even if these were from external components, the SoC *needs* these
    ones to work and any board that doesn't have these fixed XOs simply
    wouldn't be able to work.

Cheers,
Angelo

Re: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[AngeloGioacchino Del Regno]

Il 16/05/22 09:10, Krzysztof Kozlowski ha scritto:
> On 13/05/2022 19:16, AngeloGioacchino Del Regno wrote:
>> Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to
>> provide a good initial clock spec, since this SoC features two always
> 
> I don't understand that part with actual patch. You claim here you add
> clocks, but in DTS they were already before.
> 
> Additionally, these clocks do not belong to DTSI because, AFAIU, these
> are properties of boards. At least their frequencies should be moved to
> the board DTS.
> 
> 

I should reword the commit description to be clearer, sorry about that: I
went with "exactly what I've done", but looking at the actual diff, it is
just a rename. What my brain was ticking on here was about removing clocks
that didn't really exist (uart_clk is not a fixed clock, etc), and adding
the ones that do exist.... but then again, the result, casually, is a rename.

In any case... no, these clocks are not board-specific for two reasons:
1. AFAIK, these fixed clock outputs are from the SoC itself, not from
    external components placed on the board, and
2. Even if these were from external components, the SoC *needs* these
    ones to work and any board that doesn't have these fixed XOs simply
    wouldn't be able to work.

Cheers,
Angelo

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[AngeloGioacchino Del Regno]

Il 16/05/22 09:10, Krzysztof Kozlowski ha scritto:
> On 13/05/2022 19:16, AngeloGioacchino Del Regno wrote:
>> Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to
>> provide a good initial clock spec, since this SoC features two always
> 
> I don't understand that part with actual patch. You claim here you add
> clocks, but in DTS they were already before.
> 
> Additionally, these clocks do not belong to DTSI because, AFAIU, these
> are properties of boards. At least their frequencies should be moved to
> the board DTS.
> 
> 

I should reword the commit description to be clearer, sorry about that: I
went with "exactly what I've done", but looking at the actual diff, it is
just a rename. What my brain was ticking on here was about removing clocks
that didn't really exist (uart_clk is not a fixed clock, etc), and adding
the ones that do exist.... but then again, the result, casually, is a rename.

In any case... no, these clocks are not board-specific for two reasons:
1. AFAIK, these fixed clock outputs are from the SoC itself, not from
    external components placed on the board, and
2. Even if these were from external components, the SoC *needs* these
    ones to work and any board that doesn't have these fixed XOs simply
    wouldn't be able to work.

Cheers,
Angelo

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[Krzysztof Kozlowski]

On 16/05/2022 10:51, AngeloGioacchino Del Regno wrote:

>>
>>
> 
> I should reword the commit description to be clearer, sorry about that: I
> went with "exactly what I've done", but looking at the actual diff, it is
> just a rename. What my brain was ticking on here was about removing clocks
> that didn't really exist (uart_clk is not a fixed clock, etc), and adding
> the ones that do exist.... but then again, the result, casually, is a rename.

Yes, some better explanation would help.

> 
> In any case... no, these clocks are not board-specific for two reasons:
> 1. AFAIK, these fixed clock outputs are from the SoC itself, not from
>     external components placed on the board, and

This would be fine.

> 2. Even if these were from external components, the SoC *needs* these
>     ones to work and any board that doesn't have these fixed XOs simply
>     wouldn't be able to work.

This is common pattern and Mediatek is not different here. In all cases
these are needed by SoC and in (almost?) all cases these should be
provided by board DTS. The DTS describes here the hardware, the board
has the clock thus the board DTS should define it.


Best regards,
Krzysztof

Re: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[Krzysztof Kozlowski]

On 16/05/2022 10:51, AngeloGioacchino Del Regno wrote:

>>
>>
> 
> I should reword the commit description to be clearer, sorry about that: I
> went with "exactly what I've done", but looking at the actual diff, it is
> just a rename. What my brain was ticking on here was about removing clocks
> that didn't really exist (uart_clk is not a fixed clock, etc), and adding
> the ones that do exist.... but then again, the result, casually, is a rename.

Yes, some better explanation would help.

> 
> In any case... no, these clocks are not board-specific for two reasons:
> 1. AFAIK, these fixed clock outputs are from the SoC itself, not from
>     external components placed on the board, and

This would be fine.

> 2. Even if these were from external components, the SoC *needs* these
>     ones to work and any board that doesn't have these fixed XOs simply
>     wouldn't be able to work.

This is common pattern and Mediatek is not different here. In all cases
these are needed by SoC and in (almost?) all cases these should be
provided by board DTS. The DTS describes here the hardware, the board
has the clock thus the board DTS should define it.


Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[Krzysztof Kozlowski]

On 16/05/2022 10:51, AngeloGioacchino Del Regno wrote:

>>
>>
> 
> I should reword the commit description to be clearer, sorry about that: I
> went with "exactly what I've done", but looking at the actual diff, it is
> just a rename. What my brain was ticking on here was about removing clocks
> that didn't really exist (uart_clk is not a fixed clock, etc), and adding
> the ones that do exist.... but then again, the result, casually, is a rename.

Yes, some better explanation would help.

> 
> In any case... no, these clocks are not board-specific for two reasons:
> 1. AFAIK, these fixed clock outputs are from the SoC itself, not from
>     external components placed on the board, and

This would be fine.

> 2. Even if these were from external components, the SoC *needs* these
>     ones to work and any board that doesn't have these fixed XOs simply
>     wouldn't be able to work.

This is common pattern and Mediatek is not different here. In all cases
these are needed by SoC and in (almost?) all cases these should be
provided by board DTS. The DTS describes here the hardware, the board
has the clock thus the board DTS should define it.


Best regards,
Krzysztof

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[AngeloGioacchino Del Regno]

Il 16/05/22 16:51, Krzysztof Kozlowski ha scritto:
> On 16/05/2022 10:51, AngeloGioacchino Del Regno wrote:
> 
>>>
>>>
>>
>> I should reword the commit description to be clearer, sorry about that: I
>> went with "exactly what I've done", but looking at the actual diff, it is
>> just a rename. What my brain was ticking on here was about removing clocks
>> that didn't really exist (uart_clk is not a fixed clock, etc), and adding
>> the ones that do exist.... but then again, the result, casually, is a rename.
> 
> Yes, some better explanation would help.
> 

Will do for v2 then!

>>
>> In any case... no, these clocks are not board-specific for two reasons:
>> 1. AFAIK, these fixed clock outputs are from the SoC itself, not from
>>      external components placed on the board, and
> 
> This would be fine.
> 
>> 2. Even if these were from external components, the SoC *needs* these
>>      ones to work and any board that doesn't have these fixed XOs simply
>>      wouldn't be able to work.
> 
> This is common pattern and Mediatek is not different here. In all cases
> these are needed by SoC and in (almost?) all cases these should be
> provided by board DTS. The DTS describes here the hardware, the board
> has the clock thus the board DTS should define it.
> 

Right. If external components are strictly necessary, physically, they're
still external components and not inside of the SoC, and anything external
*may* change depending on the (hardware) implementation.

Anyway - I was wondering if splitting this change in two commits would be
better to let people understand what's going on... probably it would, as
that would clearly show both the addition of the 32K/26M clocks and the
subsequent removal of the other two: I would at this point do that, what
do you think?

Regards,
Angelo

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Re: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[AngeloGioacchino Del Regno]

Il 16/05/22 16:51, Krzysztof Kozlowski ha scritto:
> On 16/05/2022 10:51, AngeloGioacchino Del Regno wrote:
> 
>>>
>>>
>>
>> I should reword the commit description to be clearer, sorry about that: I
>> went with "exactly what I've done", but looking at the actual diff, it is
>> just a rename. What my brain was ticking on here was about removing clocks
>> that didn't really exist (uart_clk is not a fixed clock, etc), and adding
>> the ones that do exist.... but then again, the result, casually, is a rename.
> 
> Yes, some better explanation would help.
> 

Will do for v2 then!

>>
>> In any case... no, these clocks are not board-specific for two reasons:
>> 1. AFAIK, these fixed clock outputs are from the SoC itself, not from
>>      external components placed on the board, and
> 
> This would be fine.
> 
>> 2. Even if these were from external components, the SoC *needs* these
>>      ones to work and any board that doesn't have these fixed XOs simply
>>      wouldn't be able to work.
> 
> This is common pattern and Mediatek is not different here. In all cases
> these are needed by SoC and in (almost?) all cases these should be
> provided by board DTS. The DTS describes here the hardware, the board
> has the clock thus the board DTS should define it.
> 

Right. If external components are strictly necessary, physically, they're
still external components and not inside of the SoC, and anything external
*may* change depending on the (hardware) implementation.

Anyway - I was wondering if splitting this change in two commits would be
better to let people understand what's going on... probably it would, as
that would clearly show both the addition of the 32K/26M clocks and the
subsequent removal of the other two: I would at this point do that, what
do you think?

Regards,
Angelo

Re: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[AngeloGioacchino Del Regno]

Il 16/05/22 16:51, Krzysztof Kozlowski ha scritto:
> On 16/05/2022 10:51, AngeloGioacchino Del Regno wrote:
> 
>>>
>>>
>>
>> I should reword the commit description to be clearer, sorry about that: I
>> went with "exactly what I've done", but looking at the actual diff, it is
>> just a rename. What my brain was ticking on here was about removing clocks
>> that didn't really exist (uart_clk is not a fixed clock, etc), and adding
>> the ones that do exist.... but then again, the result, casually, is a rename.
> 
> Yes, some better explanation would help.
> 

Will do for v2 then!

>>
>> In any case... no, these clocks are not board-specific for two reasons:
>> 1. AFAIK, these fixed clock outputs are from the SoC itself, not from
>>      external components placed on the board, and
> 
> This would be fine.
> 
>> 2. Even if these were from external components, the SoC *needs* these
>>      ones to work and any board that doesn't have these fixed XOs simply
>>      wouldn't be able to work.
> 
> This is common pattern and Mediatek is not different here. In all cases
> these are needed by SoC and in (almost?) all cases these should be
> provided by board DTS. The DTS describes here the hardware, the board
> has the clock thus the board DTS should define it.
> 

Right. If external components are strictly necessary, physically, they're
still external components and not inside of the SoC, and anything external
*may* change depending on the (hardware) implementation.

Anyway - I was wondering if splitting this change in two commits would be
better to let people understand what's going on... probably it would, as
that would clearly show both the addition of the 32K/26M clocks and the
subsequent removal of the other two: I would at this point do that, what
do you think?

Regards,
Angelo

_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[Krzysztof Kozlowski]

On 17/05/2022 10:14, AngeloGioacchino Del Regno wrote:

> Right. If external components are strictly necessary, physically, they're
> still external components and not inside of the SoC, and anything external
> *may* change depending on the (hardware) implementation.
> 
> Anyway - I was wondering if splitting this change in two commits would be
> better to let people understand what's going on... probably it would, as
> that would clearly show both the addition of the 32K/26M clocks and the
> subsequent removal of the other two: I would at this point do that, what
> do you think?

Could help.


Best regards,
Krzysztof

Re: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[Krzysztof Kozlowski]

On 17/05/2022 10:14, AngeloGioacchino Del Regno wrote:

> Right. If external components are strictly necessary, physically, they're
> still external components and not inside of the SoC, and anything external
> *may* change depending on the (hardware) implementation.
> 
> Anyway - I was wondering if splitting this change in two commits would be
> better to let people understand what's going on... probably it would, as
> that would clearly show both the addition of the 32K/26M clocks and the
> subsequent removal of the other two: I would at this point do that, what
> do you think?

Could help.


Best regards,
Krzysztof

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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs

[Krzysztof Kozlowski]

On 17/05/2022 10:14, AngeloGioacchino Del Regno wrote:

> Right. If external components are strictly necessary, physically, they're
> still external components and not inside of the SoC, and anything external
> *may* change depending on the (hardware) implementation.
> 
> Anyway - I was wondering if splitting this change in two commits would be
> better to let people understand what's going on... probably it would, as
> that would clearly show both the addition of the 32K/26M clocks and the
> subsequent removal of the other two: I would at this point do that, what
> do you think?

Could help.


Best regards,
Krzysztof

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[PATCH 6/7] arm64: dts: mediatek: mt6795: Add general purpose timer node

[AngeloGioacchino Del Regno]

Add the timer node, enabling two GPTs, of which one will be used as
sched_clock.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index b6f7681cc151..217d99621558 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -198,6 +198,14 @@ watchdog: watchdog@10007000 {
 			timeout-sec = <20>;
 		};
 
+		timer: timer@10008000 {
+			compatible = "mediatek,mt6795-timer",
+				     "mediatek,mt6577-timer";
+			reg = <0 0x10008000 0 0x1000>;
+			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&system_clk>, <&clk32k>;
+		};
+
 		sysirq: intpol-controller@10200620 {
 			compatible = "mediatek,mt6795-sysirq",
 				     "mediatek,mt6577-sysirq";
-- 
2.35.1

[PATCH 6/7] arm64: dts: mediatek: mt6795: Add general purpose timer node

[AngeloGioacchino Del Regno]

Add the timer node, enabling two GPTs, of which one will be used as
sched_clock.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index b6f7681cc151..217d99621558 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -198,6 +198,14 @@ watchdog: watchdog@10007000 {
 			timeout-sec = <20>;
 		};
 
+		timer: timer@10008000 {
+			compatible = "mediatek,mt6795-timer",
+				     "mediatek,mt6577-timer";
+			reg = <0 0x10008000 0 0x1000>;
+			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&system_clk>, <&clk32k>;
+		};
+
 		sysirq: intpol-controller@10200620 {
 			compatible = "mediatek,mt6795-sysirq",
 				     "mediatek,mt6577-sysirq";
-- 
2.35.1


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[PATCH 6/7] arm64: dts: mediatek: mt6795: Add general purpose timer node

[AngeloGioacchino Del Regno]

Add the timer node, enabling two GPTs, of which one will be used as
sched_clock.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index b6f7681cc151..217d99621558 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -198,6 +198,14 @@ watchdog: watchdog@10007000 {
 			timeout-sec = <20>;
 		};
 
+		timer: timer@10008000 {
+			compatible = "mediatek,mt6795-timer",
+				     "mediatek,mt6577-timer";
+			reg = <0 0x10008000 0 0x1000>;
+			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&system_clk>, <&clk32k>;
+		};
+
 		sysirq: intpol-controller@10200620 {
 			compatible = "mediatek,mt6795-sysirq",
 				     "mediatek,mt6577-sysirq";
-- 
2.35.1


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[PATCH 7/7] arm64: dts: mediatek: mt6795: Add ARM CCI-400 node and assign to CPUs

[AngeloGioacchino Del Regno]

This SoC features an ARM CCI-400 IP: add the required node and
assign the cci control ports to the CPU cores.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 44 ++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 217d99621558..db1f24b3b9a9 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -34,6 +34,7 @@ cpu0: cpu@0 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x000>;
+			cci-control-port = <&cci_control2>;
 			next-level-cache = <&l2_0>;
 		};
 
@@ -42,6 +43,7 @@ cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x001>;
+			cci-control-port = <&cci_control2>;
 			next-level-cache = <&l2_0>;
 		};
 
@@ -50,6 +52,7 @@ cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x002>;
+			cci-control-port = <&cci_control2>;
 			next-level-cache = <&l2_0>;
 		};
 
@@ -58,6 +61,7 @@ cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x003>;
+			cci-control-port = <&cci_control2>;
 			next-level-cache = <&l2_0>;
 		};
 
@@ -66,6 +70,7 @@ cpu4: cpu@100 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x100>;
+			cci-control-port = <&cci_control1>;
 			next-level-cache = <&l2_1>;
 		};
 
@@ -74,6 +79,7 @@ cpu5: cpu@101 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x101>;
+			cci-control-port = <&cci_control1>;
 			next-level-cache = <&l2_1>;
 		};
 
@@ -82,6 +88,7 @@ cpu6: cpu@102 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x102>;
+			cci-control-port = <&cci_control1>;
 			next-level-cache = <&l2_1>;
 		};
 
@@ -90,6 +97,7 @@ cpu7: cpu@103 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x103>;
+			cci-control-port = <&cci_control1>;
 			next-level-cache = <&l2_1>;
 		};
 
@@ -226,6 +234,42 @@ gic: interrupt-controller@10221000 {
 			      <0 0x10226000 0 0x2000>;
 		};
 
+		cci: cci@10390000 {
+			compatible = "arm,cci-400";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0 0x10390000 0 0x1000>;
+			ranges = <0 0 0x10390000 0x10000>;
+
+			cci_control0: slave-if@1000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace-lite";
+				reg = <0x1000 0x1000>;
+			};
+
+			cci_control1: slave-if@4000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace";
+				reg = <0x4000 0x1000>;
+			};
+
+			cci_control2: slave-if@5000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace";
+				reg = <0x5000 0x1000>;
+			};
+
+			pmu@9000 {
+				compatible = "arm,cci-400-pmu,r1";
+				reg = <0x9000 0x5000>;
+				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		uart0: serial@11002000 {
 			compatible = "mediatek,mt6795-uart",
 				     "mediatek,mt6577-uart";
-- 
2.35.1

[PATCH 7/7] arm64: dts: mediatek: mt6795: Add ARM CCI-400 node and assign to CPUs

[AngeloGioacchino Del Regno]

This SoC features an ARM CCI-400 IP: add the required node and
assign the cci control ports to the CPU cores.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 44 ++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 217d99621558..db1f24b3b9a9 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -34,6 +34,7 @@ cpu0: cpu@0 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x000>;
+			cci-control-port = <&cci_control2>;
 			next-level-cache = <&l2_0>;
 		};
 
@@ -42,6 +43,7 @@ cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x001>;
+			cci-control-port = <&cci_control2>;
 			next-level-cache = <&l2_0>;
 		};
 
@@ -50,6 +52,7 @@ cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x002>;
+			cci-control-port = <&cci_control2>;
 			next-level-cache = <&l2_0>;
 		};
 
@@ -58,6 +61,7 @@ cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x003>;
+			cci-control-port = <&cci_control2>;
 			next-level-cache = <&l2_0>;
 		};
 
@@ -66,6 +70,7 @@ cpu4: cpu@100 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x100>;
+			cci-control-port = <&cci_control1>;
 			next-level-cache = <&l2_1>;
 		};
 
@@ -74,6 +79,7 @@ cpu5: cpu@101 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x101>;
+			cci-control-port = <&cci_control1>;
 			next-level-cache = <&l2_1>;
 		};
 
@@ -82,6 +88,7 @@ cpu6: cpu@102 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x102>;
+			cci-control-port = <&cci_control1>;
 			next-level-cache = <&l2_1>;
 		};
 
@@ -90,6 +97,7 @@ cpu7: cpu@103 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x103>;
+			cci-control-port = <&cci_control1>;
 			next-level-cache = <&l2_1>;
 		};
 
@@ -226,6 +234,42 @@ gic: interrupt-controller@10221000 {
 			      <0 0x10226000 0 0x2000>;
 		};
 
+		cci: cci@10390000 {
+			compatible = "arm,cci-400";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0 0x10390000 0 0x1000>;
+			ranges = <0 0 0x10390000 0x10000>;
+
+			cci_control0: slave-if@1000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace-lite";
+				reg = <0x1000 0x1000>;
+			};
+
+			cci_control1: slave-if@4000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace";
+				reg = <0x4000 0x1000>;
+			};
+
+			cci_control2: slave-if@5000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace";
+				reg = <0x5000 0x1000>;
+			};
+
+			pmu@9000 {
+				compatible = "arm,cci-400-pmu,r1";
+				reg = <0x9000 0x5000>;
+				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		uart0: serial@11002000 {
 			compatible = "mediatek,mt6795-uart",
 				     "mediatek,mt6577-uart";
-- 
2.35.1


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[PATCH 7/7] arm64: dts: mediatek: mt6795: Add ARM CCI-400 node and assign to CPUs

[AngeloGioacchino Del Regno]

This SoC features an ARM CCI-400 IP: add the required node and
assign the cci control ports to the CPU cores.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 44 ++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 217d99621558..db1f24b3b9a9 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -34,6 +34,7 @@ cpu0: cpu@0 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x000>;
+			cci-control-port = <&cci_control2>;
 			next-level-cache = <&l2_0>;
 		};
 
@@ -42,6 +43,7 @@ cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x001>;
+			cci-control-port = <&cci_control2>;
 			next-level-cache = <&l2_0>;
 		};
 
@@ -50,6 +52,7 @@ cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x002>;
+			cci-control-port = <&cci_control2>;
 			next-level-cache = <&l2_0>;
 		};
 
@@ -58,6 +61,7 @@ cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x003>;
+			cci-control-port = <&cci_control2>;
 			next-level-cache = <&l2_0>;
 		};
 
@@ -66,6 +70,7 @@ cpu4: cpu@100 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x100>;
+			cci-control-port = <&cci_control1>;
 			next-level-cache = <&l2_1>;
 		};
 
@@ -74,6 +79,7 @@ cpu5: cpu@101 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x101>;
+			cci-control-port = <&cci_control1>;
 			next-level-cache = <&l2_1>;
 		};
 
@@ -82,6 +88,7 @@ cpu6: cpu@102 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x102>;
+			cci-control-port = <&cci_control1>;
 			next-level-cache = <&l2_1>;
 		};
 
@@ -90,6 +97,7 @@ cpu7: cpu@103 {
 			compatible = "arm,cortex-a53";
 			enable-method = "psci";
 			reg = <0x103>;
+			cci-control-port = <&cci_control1>;
 			next-level-cache = <&l2_1>;
 		};
 
@@ -226,6 +234,42 @@ gic: interrupt-controller@10221000 {
 			      <0 0x10226000 0 0x2000>;
 		};
 
+		cci: cci@10390000 {
+			compatible = "arm,cci-400";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0 0x10390000 0 0x1000>;
+			ranges = <0 0 0x10390000 0x10000>;
+
+			cci_control0: slave-if@1000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace-lite";
+				reg = <0x1000 0x1000>;
+			};
+
+			cci_control1: slave-if@4000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace";
+				reg = <0x4000 0x1000>;
+			};
+
+			cci_control2: slave-if@5000 {
+				compatible = "arm,cci-400-ctrl-if";
+				interface-type = "ace";
+				reg = <0x5000 0x1000>;
+			};
+
+			pmu@9000 {
+				compatible = "arm,cci-400-pmu,r1";
+				reg = <0x9000 0x5000>;
+				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		uart0: serial@11002000 {
 			compatible = "mediatek,mt6795-uart",
 				     "mediatek,mt6577-uart";
-- 
2.35.1


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