* [RFC v3 0/5] RK3568 PCIe V3 support @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> This series adds Rockchip PCIe V3 support found on rk3568 SOC. It is based on "Enable rk356x PCIe controller" series of Peter Geis v9: https://patchwork.kernel.org/project/linux-rockchip/list/?series=636944 Compared to PCIeV2 which uses the Naneng combphy, PCIe v3 uses a dedicated PCI-phy. New in this version is that lane-map is no separate patch and moved from PCIe- to phy-driver. Peter has tested m2-slot too and so the bifurcation. The Phy-Patch is now changed to original author, but our changes are squashed in. Frank Wunderlich (4): dt-bindings: phy: rockchip: add PCIe v3 phy dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf arm64: dts: rockchip: rk3568: Add PCIe v3 nodes arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro Shawn Lin (1): phy: rockchip: Support PCIe v3 .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++ .../devicetree/bindings/soc/rockchip/grf.yaml | 3 + .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 90 +++++ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++ drivers/phy/rockchip/Kconfig | 9 + drivers/phy/rockchip/Makefile | 1 + .../phy/rockchip/phy-rockchip-snps-pcie3.c | 317 ++++++++++++++++++ include/linux/phy/pcie.h | 12 + 8 files changed, 636 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c create mode 100644 include/linux/phy/pcie.h -- 2.25.1 ^ permalink raw reply [flat|nested] 60+ messages in thread
* [RFC v3 0/5] RK3568 PCIe V3 support @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> This series adds Rockchip PCIe V3 support found on rk3568 SOC. It is based on "Enable rk356x PCIe controller" series of Peter Geis v9: https://patchwork.kernel.org/project/linux-rockchip/list/?series=636944 Compared to PCIeV2 which uses the Naneng combphy, PCIe v3 uses a dedicated PCI-phy. New in this version is that lane-map is no separate patch and moved from PCIe- to phy-driver. Peter has tested m2-slot too and so the bifurcation. The Phy-Patch is now changed to original author, but our changes are squashed in. Frank Wunderlich (4): dt-bindings: phy: rockchip: add PCIe v3 phy dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf arm64: dts: rockchip: rk3568: Add PCIe v3 nodes arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro Shawn Lin (1): phy: rockchip: Support PCIe v3 .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++ .../devicetree/bindings/soc/rockchip/grf.yaml | 3 + .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 90 +++++ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++ drivers/phy/rockchip/Kconfig | 9 + drivers/phy/rockchip/Makefile | 1 + .../phy/rockchip/phy-rockchip-snps-pcie3.c | 317 ++++++++++++++++++ include/linux/phy/pcie.h | 12 + 8 files changed, 636 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c create mode 100644 include/linux/phy/pcie.h -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 60+ messages in thread
* [RFC v3 0/5] RK3568 PCIe V3 support @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> This series adds Rockchip PCIe V3 support found on rk3568 SOC. It is based on "Enable rk356x PCIe controller" series of Peter Geis v9: https://patchwork.kernel.org/project/linux-rockchip/list/?series=636944 Compared to PCIeV2 which uses the Naneng combphy, PCIe v3 uses a dedicated PCI-phy. New in this version is that lane-map is no separate patch and moved from PCIe- to phy-driver. Peter has tested m2-slot too and so the bifurcation. The Phy-Patch is now changed to original author, but our changes are squashed in. Frank Wunderlich (4): dt-bindings: phy: rockchip: add PCIe v3 phy dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf arm64: dts: rockchip: rk3568: Add PCIe v3 nodes arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro Shawn Lin (1): phy: rockchip: Support PCIe v3 .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++ .../devicetree/bindings/soc/rockchip/grf.yaml | 3 + .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 90 +++++ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++ drivers/phy/rockchip/Kconfig | 9 + drivers/phy/rockchip/Makefile | 1 + .../phy/rockchip/phy-rockchip-snps-pcie3.c | 317 ++++++++++++++++++ include/linux/phy/pcie.h | 12 + 8 files changed, 636 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c create mode 100644 include/linux/phy/pcie.h -- 2.25.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 60+ messages in thread
* [RFC v3 0/5] RK3568 PCIe V3 support @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> This series adds Rockchip PCIe V3 support found on rk3568 SOC. It is based on "Enable rk356x PCIe controller" series of Peter Geis v9: https://patchwork.kernel.org/project/linux-rockchip/list/?series=636944 Compared to PCIeV2 which uses the Naneng combphy, PCIe v3 uses a dedicated PCI-phy. New in this version is that lane-map is no separate patch and moved from PCIe- to phy-driver. Peter has tested m2-slot too and so the bifurcation. The Phy-Patch is now changed to original author, but our changes are squashed in. Frank Wunderlich (4): dt-bindings: phy: rockchip: add PCIe v3 phy dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf arm64: dts: rockchip: rk3568: Add PCIe v3 nodes arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro Shawn Lin (1): phy: rockchip: Support PCIe v3 .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++ .../devicetree/bindings/soc/rockchip/grf.yaml | 3 + .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 90 +++++ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++ drivers/phy/rockchip/Kconfig | 9 + drivers/phy/rockchip/Makefile | 1 + .../phy/rockchip/phy-rockchip-snps-pcie3.c | 317 ++++++++++++++++++ include/linux/phy/pcie.h | 12 + 8 files changed, 636 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c create mode 100644 include/linux/phy/pcie.h -- 2.25.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 60+ messages in thread
* [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy 2022-05-14 11:59 ` Frank Wunderlich (?) (?) @ 2022-05-14 11:59 ` Frank Wunderlich -1 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> Add a new binding file for Rockchip PCIe v3 phy driver. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - drop quotes - drop rk3588 - make clockcount fixed to 3 - full path for binding header file - drop phy-mode and its header and add lane-map v2: dt-bindings: rename yaml for PCIe v3 rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml changes in pcie3 phy yaml - change clock names to ordered const list - extend pcie30-phymode description - add phy-cells to required properties - drop unevaluatedProperties - example with 1 clock each line - use default property instead of text describing it - update license --- .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml new file mode 100644 index 000000000000..ac82f551bbfb --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip PCIe v3 phy + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,rk3568-pcie3-phy + + reg: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: refclk_m + - const: refclk_n + - const: pclk + + minItems: 3 + + lane-map: + description: which lanes (by position) should be mapped to which + controller (value). 0 means lane unused, higher value means used. + (controller-number +1 ) + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 16 + items: + minimum: 0 + maximum: 16 + + "#phy-cells": + const: 0 + + resets: + maxItems: 1 + + reset-names: + const: phy + + rockchip,phy-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the syscon managing the phy "general register files" + + rockchip,pipe-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the syscon managing the pipe "general register files" + +required: + - compatible + - reg + - rockchip,phy-grf + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3568-cru.h> + pcie30phy: phy@fe8c0000 { + compatible = "rockchip,rk3568-pcie3-phy"; + reg = <0x0 0xfe8c0000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, + <&pmucru CLK_PCIE30PHY_REF_N>, + <&cru PCLK_PCIE30PHY>; + clock-names = "refclk_m", "refclk_n", "pclk"; + resets = <&cru SRST_PCIE30PHY>; + reset-names = "phy"; + rockchip,phy-grf = <&pcie30_phy_grf>; + }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> Add a new binding file for Rockchip PCIe v3 phy driver. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - drop quotes - drop rk3588 - make clockcount fixed to 3 - full path for binding header file - drop phy-mode and its header and add lane-map v2: dt-bindings: rename yaml for PCIe v3 rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml changes in pcie3 phy yaml - change clock names to ordered const list - extend pcie30-phymode description - add phy-cells to required properties - drop unevaluatedProperties - example with 1 clock each line - use default property instead of text describing it - update license --- .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml new file mode 100644 index 000000000000..ac82f551bbfb --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip PCIe v3 phy + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,rk3568-pcie3-phy + + reg: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: refclk_m + - const: refclk_n + - const: pclk + + minItems: 3 + + lane-map: + description: which lanes (by position) should be mapped to which + controller (value). 0 means lane unused, higher value means used. + (controller-number +1 ) + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 16 + items: + minimum: 0 + maximum: 16 + + "#phy-cells": + const: 0 + + resets: + maxItems: 1 + + reset-names: + const: phy + + rockchip,phy-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the syscon managing the phy "general register files" + + rockchip,pipe-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the syscon managing the pipe "general register files" + +required: + - compatible + - reg + - rockchip,phy-grf + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3568-cru.h> + pcie30phy: phy@fe8c0000 { + compatible = "rockchip,rk3568-pcie3-phy"; + reg = <0x0 0xfe8c0000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, + <&pmucru CLK_PCIE30PHY_REF_N>, + <&cru PCLK_PCIE30PHY>; + clock-names = "refclk_m", "refclk_n", "pclk"; + resets = <&cru SRST_PCIE30PHY>; + reset-names = "phy"; + rockchip,phy-grf = <&pcie30_phy_grf>; + }; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> Add a new binding file for Rockchip PCIe v3 phy driver. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - drop quotes - drop rk3588 - make clockcount fixed to 3 - full path for binding header file - drop phy-mode and its header and add lane-map v2: dt-bindings: rename yaml for PCIe v3 rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml changes in pcie3 phy yaml - change clock names to ordered const list - extend pcie30-phymode description - add phy-cells to required properties - drop unevaluatedProperties - example with 1 clock each line - use default property instead of text describing it - update license --- .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml new file mode 100644 index 000000000000..ac82f551bbfb --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip PCIe v3 phy + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,rk3568-pcie3-phy + + reg: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: refclk_m + - const: refclk_n + - const: pclk + + minItems: 3 + + lane-map: + description: which lanes (by position) should be mapped to which + controller (value). 0 means lane unused, higher value means used. + (controller-number +1 ) + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 16 + items: + minimum: 0 + maximum: 16 + + "#phy-cells": + const: 0 + + resets: + maxItems: 1 + + reset-names: + const: phy + + rockchip,phy-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the syscon managing the phy "general register files" + + rockchip,pipe-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the syscon managing the pipe "general register files" + +required: + - compatible + - reg + - rockchip,phy-grf + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3568-cru.h> + pcie30phy: phy@fe8c0000 { + compatible = "rockchip,rk3568-pcie3-phy"; + reg = <0x0 0xfe8c0000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, + <&pmucru CLK_PCIE30PHY_REF_N>, + <&cru PCLK_PCIE30PHY>; + clock-names = "refclk_m", "refclk_n", "pclk"; + resets = <&cru SRST_PCIE30PHY>; + reset-names = "phy"; + rockchip,phy-grf = <&pcie30_phy_grf>; + }; -- 2.25.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> Add a new binding file for Rockchip PCIe v3 phy driver. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - drop quotes - drop rk3588 - make clockcount fixed to 3 - full path for binding header file - drop phy-mode and its header and add lane-map v2: dt-bindings: rename yaml for PCIe v3 rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml changes in pcie3 phy yaml - change clock names to ordered const list - extend pcie30-phymode description - add phy-cells to required properties - drop unevaluatedProperties - example with 1 clock each line - use default property instead of text describing it - update license --- .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml new file mode 100644 index 000000000000..ac82f551bbfb --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip PCIe v3 phy + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,rk3568-pcie3-phy + + reg: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: refclk_m + - const: refclk_n + - const: pclk + + minItems: 3 + + lane-map: + description: which lanes (by position) should be mapped to which + controller (value). 0 means lane unused, higher value means used. + (controller-number +1 ) + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 16 + items: + minimum: 0 + maximum: 16 + + "#phy-cells": + const: 0 + + resets: + maxItems: 1 + + reset-names: + const: phy + + rockchip,phy-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the syscon managing the phy "general register files" + + rockchip,pipe-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the syscon managing the pipe "general register files" + +required: + - compatible + - reg + - rockchip,phy-grf + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3568-cru.h> + pcie30phy: phy@fe8c0000 { + compatible = "rockchip,rk3568-pcie3-phy"; + reg = <0x0 0xfe8c0000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, + <&pmucru CLK_PCIE30PHY_REF_N>, + <&cru PCLK_PCIE30PHY>; + clock-names = "refclk_m", "refclk_n", "pclk"; + resets = <&cru SRST_PCIE30PHY>; + reset-names = "phy"; + rockchip,phy-grf = <&pcie30_phy_grf>; + }; -- 2.25.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 60+ messages in thread
* Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy 2022-05-14 11:59 ` Frank Wunderlich (?) (?) @ 2022-05-14 20:44 ` Krzysztof Kozlowski -1 siblings, 0 replies; 60+ messages in thread From: Krzysztof Kozlowski @ 2022-05-14 20:44 UTC (permalink / raw) To: Frank Wunderlich, linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy On 14/05/2022 13:59, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > Add a new binding file for Rockchip PCIe v3 phy driver. > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-14 20:44 ` Krzysztof Kozlowski 0 siblings, 0 replies; 60+ messages in thread From: Krzysztof Kozlowski @ 2022-05-14 20:44 UTC (permalink / raw) To: Frank Wunderlich, linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy On 14/05/2022 13:59, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > Add a new binding file for Rockchip PCIe v3 phy driver. > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-14 20:44 ` Krzysztof Kozlowski 0 siblings, 0 replies; 60+ messages in thread From: Krzysztof Kozlowski @ 2022-05-14 20:44 UTC (permalink / raw) To: Frank Wunderlich, linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy On 14/05/2022 13:59, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > Add a new binding file for Rockchip PCIe v3 phy driver. > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-14 20:44 ` Krzysztof Kozlowski 0 siblings, 0 replies; 60+ messages in thread From: Krzysztof Kozlowski @ 2022-05-14 20:44 UTC (permalink / raw) To: Frank Wunderlich, linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy On 14/05/2022 13:59, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > Add a new binding file for Rockchip PCIe v3 phy driver. > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy 2022-05-14 11:59 ` Frank Wunderlich (?) (?) @ 2022-05-14 23:14 ` Rob Herring -1 siblings, 0 replies; 60+ messages in thread From: Rob Herring @ 2022-05-14 23:14 UTC (permalink / raw) To: Frank Wunderlich Cc: Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, Frank Wunderlich, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, Rob Herring, devicetree, Krzysztof Wilczyński On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > Add a new binding file for Rockchip PCIe v3 phy driver. > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > > --- > v3: > - drop quotes > - drop rk3588 > - make clockcount fixed to 3 > - full path for binding header file > - drop phy-mode and its header and add lane-map > > v2: > dt-bindings: rename yaml for PCIe v3 > rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml > > changes in pcie3 phy yaml > - change clock names to ordered const list > - extend pcie30-phymode description > - add phy-cells to required properties > - drop unevaluatedProperties > - example with 1 clock each line > - use default property instead of text describing it > - update license > --- > .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ > 1 file changed, 82 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: properties:clock-names: 'oneOf' conditional failed, one must be fixed: [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too long [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too short False schema does not allow 3 1 was expected 3 is greater than the maximum of 2 hint: "minItems" is only needed if less than the "items" list length from schema $id: http://devicetree.org/meta-schemas/items.yaml# /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: ignoring, error in schema: properties: clock-names Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: /example-0/phy@fe8c0000: failed to match any schema with compatible: ['rockchip,rk3568-pcie3-phy'] doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-14 23:14 ` Rob Herring 0 siblings, 0 replies; 60+ messages in thread From: Rob Herring @ 2022-05-14 23:14 UTC (permalink / raw) To: Frank Wunderlich Cc: Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, Frank Wunderlich, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, Rob Herring, devicetree, Krzysztof Wilczyński On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > Add a new binding file for Rockchip PCIe v3 phy driver. > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > > --- > v3: > - drop quotes > - drop rk3588 > - make clockcount fixed to 3 > - full path for binding header file > - drop phy-mode and its header and add lane-map > > v2: > dt-bindings: rename yaml for PCIe v3 > rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml > > changes in pcie3 phy yaml > - change clock names to ordered const list > - extend pcie30-phymode description > - add phy-cells to required properties > - drop unevaluatedProperties > - example with 1 clock each line > - use default property instead of text describing it > - update license > --- > .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ > 1 file changed, 82 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: properties:clock-names: 'oneOf' conditional failed, one must be fixed: [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too long [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too short False schema does not allow 3 1 was expected 3 is greater than the maximum of 2 hint: "minItems" is only needed if less than the "items" list length from schema $id: http://devicetree.org/meta-schemas/items.yaml# /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: ignoring, error in schema: properties: clock-names Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: /example-0/phy@fe8c0000: failed to match any schema with compatible: ['rockchip,rk3568-pcie3-phy'] doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-14 23:14 ` Rob Herring 0 siblings, 0 replies; 60+ messages in thread From: Rob Herring @ 2022-05-14 23:14 UTC (permalink / raw) To: Frank Wunderlich Cc: Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, Frank Wunderlich, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, Rob Herring, devicetree, Krzysztof Wilczyński On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > Add a new binding file for Rockchip PCIe v3 phy driver. > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > > --- > v3: > - drop quotes > - drop rk3588 > - make clockcount fixed to 3 > - full path for binding header file > - drop phy-mode and its header and add lane-map > > v2: > dt-bindings: rename yaml for PCIe v3 > rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml > > changes in pcie3 phy yaml > - change clock names to ordered const list > - extend pcie30-phymode description > - add phy-cells to required properties > - drop unevaluatedProperties > - example with 1 clock each line > - use default property instead of text describing it > - update license > --- > .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ > 1 file changed, 82 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: properties:clock-names: 'oneOf' conditional failed, one must be fixed: [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too long [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too short False schema does not allow 3 1 was expected 3 is greater than the maximum of 2 hint: "minItems" is only needed if less than the "items" list length from schema $id: http://devicetree.org/meta-schemas/items.yaml# /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: ignoring, error in schema: properties: clock-names Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: /example-0/phy@fe8c0000: failed to match any schema with compatible: ['rockchip,rk3568-pcie3-phy'] doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-14 23:14 ` Rob Herring 0 siblings, 0 replies; 60+ messages in thread From: Rob Herring @ 2022-05-14 23:14 UTC (permalink / raw) To: Frank Wunderlich Cc: Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, Frank Wunderlich, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, Rob Herring, devicetree, Krzysztof Wilczyński On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > Add a new binding file for Rockchip PCIe v3 phy driver. > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > > --- > v3: > - drop quotes > - drop rk3588 > - make clockcount fixed to 3 > - full path for binding header file > - drop phy-mode and its header and add lane-map > > v2: > dt-bindings: rename yaml for PCIe v3 > rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml > > changes in pcie3 phy yaml > - change clock names to ordered const list > - extend pcie30-phymode description > - add phy-cells to required properties > - drop unevaluatedProperties > - example with 1 clock each line > - use default property instead of text describing it > - update license > --- > .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ > 1 file changed, 82 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: properties:clock-names: 'oneOf' conditional failed, one must be fixed: [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too long [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too short False schema does not allow 3 1 was expected 3 is greater than the maximum of 2 hint: "minItems" is only needed if less than the "items" list length from schema $id: http://devicetree.org/meta-schemas/items.yaml# /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: ignoring, error in schema: properties: clock-names Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: /example-0/phy@fe8c0000: failed to match any schema with compatible: ['rockchip,rk3568-pcie3-phy'] doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 60+ messages in thread
* Aw: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy 2022-05-14 23:14 ` Rob Herring (?) (?) @ 2022-05-15 11:49 ` Frank Wunderlich -1 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-15 11:49 UTC (permalink / raw) To: Rob Herring Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, Rob Herring, devicetree, Krzysztof Wilczyński Hi > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr > Von: "Rob Herring" <robh@kernel.org> > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > > From: Frank Wunderlich <frank-w@public-files.de> > > > > Add a new binding file for Rockchip PCIe v3 phy driver. > > > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > > > > --- > > v3: > > - drop quotes > > - drop rk3588 > > - make clockcount fixed to 3 > > - full path for binding header file > > - drop phy-mode and its header and add lane-map > > > > v2: > > dt-bindings: rename yaml for PCIe v3 > > rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml > > > > changes in pcie3 phy yaml > > - change clock names to ordered const list > > - extend pcie30-phymode description > > - add phy-cells to required properties > > - drop unevaluatedProperties > > - example with 1 clock each line > > - use default property instead of text describing it > > - update license > > --- > > .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ > > 1 file changed, 82 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: properties:clock-names: 'oneOf' conditional failed, one must be fixed: > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too long > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too short > False schema does not allow 3 > 1 was expected > 3 is greater than the maximum of 2 > hint: "minItems" is only needed if less than the "items" list length > from schema $id: http://devicetree.org/meta-schemas/items.yaml# > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: ignoring, error in schema: properties: clock-names > Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: /example-0/phy@fe8c0000: failed to match any schema with compatible: ['rockchip,rk3568-pcie3-phy'] seems this is fixed when i remove the "minItems: 3" from clock names (which is already fixed length because of the list). needed to change type of lane-map to this: $ref: /schemas/types.yaml#/definitions/uint8-array then it looks clean for it.... -m causes many errors unrelated to this schema-file even if i pass DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml will wait a bit for other comments (for driver) till i send another version. maybe you can confirm my changes are the right way to fix. regards Frank ^ permalink raw reply [flat|nested] 60+ messages in thread
* Aw: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-15 11:49 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-15 11:49 UTC (permalink / raw) To: Rob Herring Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, Rob Herring, devicetree, Krzysztof Wilczyński Hi > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr > Von: "Rob Herring" <robh@kernel.org> > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > > From: Frank Wunderlich <frank-w@public-files.de> > > > > Add a new binding file for Rockchip PCIe v3 phy driver. > > > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > > > > --- > > v3: > > - drop quotes > > - drop rk3588 > > - make clockcount fixed to 3 > > - full path for binding header file > > - drop phy-mode and its header and add lane-map > > > > v2: > > dt-bindings: rename yaml for PCIe v3 > > rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml > > > > changes in pcie3 phy yaml > > - change clock names to ordered const list > > - extend pcie30-phymode description > > - add phy-cells to required properties > > - drop unevaluatedProperties > > - example with 1 clock each line > > - use default property instead of text describing it > > - update license > > --- > > .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ > > 1 file changed, 82 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: properties:clock-names: 'oneOf' conditional failed, one must be fixed: > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too long > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too short > False schema does not allow 3 > 1 was expected > 3 is greater than the maximum of 2 > hint: "minItems" is only needed if less than the "items" list length > from schema $id: http://devicetree.org/meta-schemas/items.yaml# > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: ignoring, error in schema: properties: clock-names > Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: /example-0/phy@fe8c0000: failed to match any schema with compatible: ['rockchip,rk3568-pcie3-phy'] seems this is fixed when i remove the "minItems: 3" from clock names (which is already fixed length because of the list). needed to change type of lane-map to this: $ref: /schemas/types.yaml#/definitions/uint8-array then it looks clean for it.... -m causes many errors unrelated to this schema-file even if i pass DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml will wait a bit for other comments (for driver) till i send another version. maybe you can confirm my changes are the right way to fix. regards Frank _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 60+ messages in thread
* Aw: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-15 11:49 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-15 11:49 UTC (permalink / raw) To: Rob Herring Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, Rob Herring, devicetree, Krzysztof Wilczyński Hi > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr > Von: "Rob Herring" <robh@kernel.org> > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > > From: Frank Wunderlich <frank-w@public-files.de> > > > > Add a new binding file for Rockchip PCIe v3 phy driver. > > > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > > > > --- > > v3: > > - drop quotes > > - drop rk3588 > > - make clockcount fixed to 3 > > - full path for binding header file > > - drop phy-mode and its header and add lane-map > > > > v2: > > dt-bindings: rename yaml for PCIe v3 > > rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml > > > > changes in pcie3 phy yaml > > - change clock names to ordered const list > > - extend pcie30-phymode description > > - add phy-cells to required properties > > - drop unevaluatedProperties > > - example with 1 clock each line > > - use default property instead of text describing it > > - update license > > --- > > .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ > > 1 file changed, 82 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: properties:clock-names: 'oneOf' conditional failed, one must be fixed: > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too long > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too short > False schema does not allow 3 > 1 was expected > 3 is greater than the maximum of 2 > hint: "minItems" is only needed if less than the "items" list length > from schema $id: http://devicetree.org/meta-schemas/items.yaml# > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: ignoring, error in schema: properties: clock-names > Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: /example-0/phy@fe8c0000: failed to match any schema with compatible: ['rockchip,rk3568-pcie3-phy'] seems this is fixed when i remove the "minItems: 3" from clock names (which is already fixed length because of the list). needed to change type of lane-map to this: $ref: /schemas/types.yaml#/definitions/uint8-array then it looks clean for it.... -m causes many errors unrelated to this schema-file even if i pass DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml will wait a bit for other comments (for driver) till i send another version. maybe you can confirm my changes are the right way to fix. regards Frank -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 60+ messages in thread
* Aw: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-15 11:49 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-15 11:49 UTC (permalink / raw) To: Rob Herring Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, Rob Herring, devicetree, Krzysztof Wilczyński Hi > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr > Von: "Rob Herring" <robh@kernel.org> > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > > From: Frank Wunderlich <frank-w@public-files.de> > > > > Add a new binding file for Rockchip PCIe v3 phy driver. > > > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > > > > --- > > v3: > > - drop quotes > > - drop rk3588 > > - make clockcount fixed to 3 > > - full path for binding header file > > - drop phy-mode and its header and add lane-map > > > > v2: > > dt-bindings: rename yaml for PCIe v3 > > rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml > > > > changes in pcie3 phy yaml > > - change clock names to ordered const list > > - extend pcie30-phymode description > > - add phy-cells to required properties > > - drop unevaluatedProperties > > - example with 1 clock each line > > - use default property instead of text describing it > > - update license > > --- > > .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ > > 1 file changed, 82 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: properties:clock-names: 'oneOf' conditional failed, one must be fixed: > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too long > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too short > False schema does not allow 3 > 1 was expected > 3 is greater than the maximum of 2 > hint: "minItems" is only needed if less than the "items" list length > from schema $id: http://devicetree.org/meta-schemas/items.yaml# > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: ignoring, error in schema: properties: clock-names > Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: /example-0/phy@fe8c0000: failed to match any schema with compatible: ['rockchip,rk3568-pcie3-phy'] seems this is fixed when i remove the "minItems: 3" from clock names (which is already fixed length because of the list). needed to change type of lane-map to this: $ref: /schemas/types.yaml#/definitions/uint8-array then it looks clean for it.... -m causes many errors unrelated to this schema-file even if i pass DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml will wait a bit for other comments (for driver) till i send another version. maybe you can confirm my changes are the right way to fix. regards Frank _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy 2022-05-15 11:49 ` Frank Wunderlich (?) (?) @ 2022-05-16 17:35 ` Rob Herring -1 siblings, 0 replies; 60+ messages in thread From: Rob Herring @ 2022-05-16 17:35 UTC (permalink / raw) To: Frank Wunderlich Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński On Sun, May 15, 2022 at 01:49:47PM +0200, Frank Wunderlich wrote: > Hi > > > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr > > Von: "Rob Herring" <robh@kernel.org> > > > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > > > From: Frank Wunderlich <frank-w@public-files.de> > > > > > > Add a new binding file for Rockchip PCIe v3 phy driver. > > > > > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > > > > > > --- > > > v3: > > > - drop quotes > > > - drop rk3588 > > > - make clockcount fixed to 3 > > > - full path for binding header file > > > - drop phy-mode and its header and add lane-map > > > > > > v2: > > > dt-bindings: rename yaml for PCIe v3 > > > rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml > > > > > > changes in pcie3 phy yaml > > > - change clock names to ordered const list > > > - extend pcie30-phymode description > > > - add phy-cells to required properties > > > - drop unevaluatedProperties > > > - example with 1 clock each line > > > - use default property instead of text describing it > > > - update license > > > --- > > > .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ > > > 1 file changed, 82 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > > > > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > > > yamllint warnings/errors: > > > > dtschema/dtc warnings/errors: > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: properties:clock-names: 'oneOf' conditional failed, one must be fixed: > > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too long > > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too short > > False schema does not allow 3 > > 1 was expected > > 3 is greater than the maximum of 2 > > hint: "minItems" is only needed if less than the "items" list length > > from schema $id: http://devicetree.org/meta-schemas/items.yaml# > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: ignoring, error in schema: properties: clock-names > > Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: /example-0/phy@fe8c0000: failed to match any schema with compatible: ['rockchip,rk3568-pcie3-phy'] > > seems this is fixed when i remove the "minItems: 3" from clock names > (which is already fixed length because of the list). Yes. > needed to change type of lane-map to this: > > $ref: /schemas/types.yaml#/definitions/uint8-array Why? That's not a standard property though, so needs a 'rockchip' prefix. Though maybe a common property would be appropriate here. > then it looks clean for it.... > > -m causes many errors unrelated to this schema-file even if i pass > DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml The fix is fixing the remaining 40 or so '-m' errors. Rob ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-16 17:35 ` Rob Herring 0 siblings, 0 replies; 60+ messages in thread From: Rob Herring @ 2022-05-16 17:35 UTC (permalink / raw) To: Frank Wunderlich Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński On Sun, May 15, 2022 at 01:49:47PM +0200, Frank Wunderlich wrote: > Hi > > > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr > > Von: "Rob Herring" <robh@kernel.org> > > > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > > > From: Frank Wunderlich <frank-w@public-files.de> > > > > > > Add a new binding file for Rockchip PCIe v3 phy driver. > > > > > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > > > > > > --- > > > v3: > > > - drop quotes > > > - drop rk3588 > > > - make clockcount fixed to 3 > > > - full path for binding header file > > > - drop phy-mode and its header and add lane-map > > > > > > v2: > > > dt-bindings: rename yaml for PCIe v3 > > > rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml > > > > > > changes in pcie3 phy yaml > > > - change clock names to ordered const list > > > - extend pcie30-phymode description > > > - add phy-cells to required properties > > > - drop unevaluatedProperties > > > - example with 1 clock each line > > > - use default property instead of text describing it > > > - update license > > > --- > > > .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ > > > 1 file changed, 82 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > > > > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > > > yamllint warnings/errors: > > > > dtschema/dtc warnings/errors: > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: properties:clock-names: 'oneOf' conditional failed, one must be fixed: > > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too long > > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too short > > False schema does not allow 3 > > 1 was expected > > 3 is greater than the maximum of 2 > > hint: "minItems" is only needed if less than the "items" list length > > from schema $id: http://devicetree.org/meta-schemas/items.yaml# > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: ignoring, error in schema: properties: clock-names > > Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: /example-0/phy@fe8c0000: failed to match any schema with compatible: ['rockchip,rk3568-pcie3-phy'] > > seems this is fixed when i remove the "minItems: 3" from clock names > (which is already fixed length because of the list). Yes. > needed to change type of lane-map to this: > > $ref: /schemas/types.yaml#/definitions/uint8-array Why? That's not a standard property though, so needs a 'rockchip' prefix. Though maybe a common property would be appropriate here. > then it looks clean for it.... > > -m causes many errors unrelated to this schema-file even if i pass > DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml The fix is fixing the remaining 40 or so '-m' errors. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-16 17:35 ` Rob Herring 0 siblings, 0 replies; 60+ messages in thread From: Rob Herring @ 2022-05-16 17:35 UTC (permalink / raw) To: Frank Wunderlich Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński On Sun, May 15, 2022 at 01:49:47PM +0200, Frank Wunderlich wrote: > Hi > > > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr > > Von: "Rob Herring" <robh@kernel.org> > > > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > > > From: Frank Wunderlich <frank-w@public-files.de> > > > > > > Add a new binding file for Rockchip PCIe v3 phy driver. > > > > > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > > > > > > --- > > > v3: > > > - drop quotes > > > - drop rk3588 > > > - make clockcount fixed to 3 > > > - full path for binding header file > > > - drop phy-mode and its header and add lane-map > > > > > > v2: > > > dt-bindings: rename yaml for PCIe v3 > > > rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml > > > > > > changes in pcie3 phy yaml > > > - change clock names to ordered const list > > > - extend pcie30-phymode description > > > - add phy-cells to required properties > > > - drop unevaluatedProperties > > > - example with 1 clock each line > > > - use default property instead of text describing it > > > - update license > > > --- > > > .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ > > > 1 file changed, 82 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > > > > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > > > yamllint warnings/errors: > > > > dtschema/dtc warnings/errors: > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: properties:clock-names: 'oneOf' conditional failed, one must be fixed: > > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too long > > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too short > > False schema does not allow 3 > > 1 was expected > > 3 is greater than the maximum of 2 > > hint: "minItems" is only needed if less than the "items" list length > > from schema $id: http://devicetree.org/meta-schemas/items.yaml# > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: ignoring, error in schema: properties: clock-names > > Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: /example-0/phy@fe8c0000: failed to match any schema with compatible: ['rockchip,rk3568-pcie3-phy'] > > seems this is fixed when i remove the "minItems: 3" from clock names > (which is already fixed length because of the list). Yes. > needed to change type of lane-map to this: > > $ref: /schemas/types.yaml#/definitions/uint8-array Why? That's not a standard property though, so needs a 'rockchip' prefix. Though maybe a common property would be appropriate here. > then it looks clean for it.... > > -m causes many errors unrelated to this schema-file even if i pass > DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml The fix is fixing the remaining 40 or so '-m' errors. Rob -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-16 17:35 ` Rob Herring 0 siblings, 0 replies; 60+ messages in thread From: Rob Herring @ 2022-05-16 17:35 UTC (permalink / raw) To: Frank Wunderlich Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński On Sun, May 15, 2022 at 01:49:47PM +0200, Frank Wunderlich wrote: > Hi > > > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr > > Von: "Rob Herring" <robh@kernel.org> > > > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > > > From: Frank Wunderlich <frank-w@public-files.de> > > > > > > Add a new binding file for Rockchip PCIe v3 phy driver. > > > > > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > > > > > > --- > > > v3: > > > - drop quotes > > > - drop rk3588 > > > - make clockcount fixed to 3 > > > - full path for binding header file > > > - drop phy-mode and its header and add lane-map > > > > > > v2: > > > dt-bindings: rename yaml for PCIe v3 > > > rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml > > > > > > changes in pcie3 phy yaml > > > - change clock names to ordered const list > > > - extend pcie30-phymode description > > > - add phy-cells to required properties > > > - drop unevaluatedProperties > > > - example with 1 clock each line > > > - use default property instead of text describing it > > > - update license > > > --- > > > .../bindings/phy/rockchip,pcie3-phy.yaml | 82 +++++++++++++++++++ > > > 1 file changed, 82 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > > > > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > > > yamllint warnings/errors: > > > > dtschema/dtc warnings/errors: > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: properties:clock-names: 'oneOf' conditional failed, one must be fixed: > > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too long > > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] is too short > > False schema does not allow 3 > > 1 was expected > > 3 is greater than the maximum of 2 > > hint: "minItems" is only needed if less than the "items" list length > > from schema $id: http://devicetree.org/meta-schemas/items.yaml# > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: ignoring, error in schema: properties: clock-names > > Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: /example-0/phy@fe8c0000: failed to match any schema with compatible: ['rockchip,rk3568-pcie3-phy'] > > seems this is fixed when i remove the "minItems: 3" from clock names > (which is already fixed length because of the list). Yes. > needed to change type of lane-map to this: > > $ref: /schemas/types.yaml#/definitions/uint8-array Why? That's not a standard property though, so needs a 'rockchip' prefix. Though maybe a common property would be appropriate here. > then it looks clean for it.... > > -m causes many errors unrelated to this schema-file even if i pass > DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml The fix is fixing the remaining 40 or so '-m' errors. Rob _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy 2022-05-16 17:35 ` Rob Herring (?) (?) @ 2022-05-16 19:21 ` Frank Wunderlich -1 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-16 19:21 UTC (permalink / raw) To: Rob Herring Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński Am 16. Mai 2022 19:35:37 MESZ schrieb Rob Herring <robh@kernel.org>: >On Sun, May 15, 2022 at 01:49:47PM +0200, Frank Wunderlich wrote: >> Hi >> >> > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr >> > Von: "Rob Herring" <robh@kernel.org> >> >> > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: >Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml >> > > >> > >> > My bot found errors running 'make DT_CHECKER_FLAGS=-m >dt_binding_check' >> > on your patch (DT_CHECKER_FLAGS is new in v5.13): >> > >> > yamllint warnings/errors: >> > >> > dtschema/dtc warnings/errors: >> > >/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: >properties:clock-names: 'oneOf' conditional failed, one must be fixed: >> > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] >is too long >> > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] >is too short >> > False schema does not allow 3 >> > 1 was expected >> > 3 is greater than the maximum of 2 >> > hint: "minItems" is only needed if less than the "items" list >length >> > from schema $id: http://devicetree.org/meta-schemas/items.yaml# >> > >/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: >ignoring, error in schema: properties: clock-names >> > >Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: >/example-0/phy@fe8c0000: failed to match any schema with compatible: >['rockchip,rk3568-pcie3-phy'] >> >> seems this is fixed when i remove the "minItems: 3" from clock names >> (which is already fixed length because of the list). > >Yes. > >> needed to change type of lane-map to this: >> >> $ref: /schemas/types.yaml#/definitions/uint8-array > >Why? That's not a standard property though, so needs a 'rockchip' >prefix. Though maybe a common property would be appropriate here. Originally it was a bool property named "rockchip,bifurcation" and we changed it (after comments) to be a more generic property "lane-map" that can be re-used on other vendors/controllers/phys. Driver reads as u8 array and range is small enough for u8 even if used for larger controllers (e.g. PCIe x16). >> then it looks clean for it.... >> >> -m causes many errors unrelated to this schema-file even if i pass >> >DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > >The fix is fixing the remaining 40 or so '-m' errors. So now clean for you(r bot), too? Did only get a bunch of other unrelated messages. >Rob regards Frank ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-16 19:21 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-16 19:21 UTC (permalink / raw) To: Rob Herring Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński Am 16. Mai 2022 19:35:37 MESZ schrieb Rob Herring <robh@kernel.org>: >On Sun, May 15, 2022 at 01:49:47PM +0200, Frank Wunderlich wrote: >> Hi >> >> > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr >> > Von: "Rob Herring" <robh@kernel.org> >> >> > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: >Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml >> > > >> > >> > My bot found errors running 'make DT_CHECKER_FLAGS=-m >dt_binding_check' >> > on your patch (DT_CHECKER_FLAGS is new in v5.13): >> > >> > yamllint warnings/errors: >> > >> > dtschema/dtc warnings/errors: >> > >/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: >properties:clock-names: 'oneOf' conditional failed, one must be fixed: >> > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] >is too long >> > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] >is too short >> > False schema does not allow 3 >> > 1 was expected >> > 3 is greater than the maximum of 2 >> > hint: "minItems" is only needed if less than the "items" list >length >> > from schema $id: http://devicetree.org/meta-schemas/items.yaml# >> > >/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: >ignoring, error in schema: properties: clock-names >> > >Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: >/example-0/phy@fe8c0000: failed to match any schema with compatible: >['rockchip,rk3568-pcie3-phy'] >> >> seems this is fixed when i remove the "minItems: 3" from clock names >> (which is already fixed length because of the list). > >Yes. > >> needed to change type of lane-map to this: >> >> $ref: /schemas/types.yaml#/definitions/uint8-array > >Why? That's not a standard property though, so needs a 'rockchip' >prefix. Though maybe a common property would be appropriate here. Originally it was a bool property named "rockchip,bifurcation" and we changed it (after comments) to be a more generic property "lane-map" that can be re-used on other vendors/controllers/phys. Driver reads as u8 array and range is small enough for u8 even if used for larger controllers (e.g. PCIe x16). >> then it looks clean for it.... >> >> -m causes many errors unrelated to this schema-file even if i pass >> >DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > >The fix is fixing the remaining 40 or so '-m' errors. So now clean for you(r bot), too? Did only get a bunch of other unrelated messages. >Rob regards Frank _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-16 19:21 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-16 19:21 UTC (permalink / raw) To: Rob Herring Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński Am 16. Mai 2022 19:35:37 MESZ schrieb Rob Herring <robh@kernel.org>: >On Sun, May 15, 2022 at 01:49:47PM +0200, Frank Wunderlich wrote: >> Hi >> >> > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr >> > Von: "Rob Herring" <robh@kernel.org> >> >> > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: >Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml >> > > >> > >> > My bot found errors running 'make DT_CHECKER_FLAGS=-m >dt_binding_check' >> > on your patch (DT_CHECKER_FLAGS is new in v5.13): >> > >> > yamllint warnings/errors: >> > >> > dtschema/dtc warnings/errors: >> > >/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: >properties:clock-names: 'oneOf' conditional failed, one must be fixed: >> > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] >is too long >> > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] >is too short >> > False schema does not allow 3 >> > 1 was expected >> > 3 is greater than the maximum of 2 >> > hint: "minItems" is only needed if less than the "items" list >length >> > from schema $id: http://devicetree.org/meta-schemas/items.yaml# >> > >/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: >ignoring, error in schema: properties: clock-names >> > >Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: >/example-0/phy@fe8c0000: failed to match any schema with compatible: >['rockchip,rk3568-pcie3-phy'] >> >> seems this is fixed when i remove the "minItems: 3" from clock names >> (which is already fixed length because of the list). > >Yes. > >> needed to change type of lane-map to this: >> >> $ref: /schemas/types.yaml#/definitions/uint8-array > >Why? That's not a standard property though, so needs a 'rockchip' >prefix. Though maybe a common property would be appropriate here. Originally it was a bool property named "rockchip,bifurcation" and we changed it (after comments) to be a more generic property "lane-map" that can be re-used on other vendors/controllers/phys. Driver reads as u8 array and range is small enough for u8 even if used for larger controllers (e.g. PCIe x16). >> then it looks clean for it.... >> >> -m causes many errors unrelated to this schema-file even if i pass >> >DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > >The fix is fixing the remaining 40 or so '-m' errors. So now clean for you(r bot), too? Did only get a bunch of other unrelated messages. >Rob regards Frank -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-16 19:21 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-16 19:21 UTC (permalink / raw) To: Rob Herring Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński Am 16. Mai 2022 19:35:37 MESZ schrieb Rob Herring <robh@kernel.org>: >On Sun, May 15, 2022 at 01:49:47PM +0200, Frank Wunderlich wrote: >> Hi >> >> > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr >> > Von: "Rob Herring" <robh@kernel.org> >> >> > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: >Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml >> > > >> > >> > My bot found errors running 'make DT_CHECKER_FLAGS=-m >dt_binding_check' >> > on your patch (DT_CHECKER_FLAGS is new in v5.13): >> > >> > yamllint warnings/errors: >> > >> > dtschema/dtc warnings/errors: >> > >/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: >properties:clock-names: 'oneOf' conditional failed, one must be fixed: >> > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] >is too long >> > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] >is too short >> > False schema does not allow 3 >> > 1 was expected >> > 3 is greater than the maximum of 2 >> > hint: "minItems" is only needed if less than the "items" list >length >> > from schema $id: http://devicetree.org/meta-schemas/items.yaml# >> > >/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: >ignoring, error in schema: properties: clock-names >> > >Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: >/example-0/phy@fe8c0000: failed to match any schema with compatible: >['rockchip,rk3568-pcie3-phy'] >> >> seems this is fixed when i remove the "minItems: 3" from clock names >> (which is already fixed length because of the list). > >Yes. > >> needed to change type of lane-map to this: >> >> $ref: /schemas/types.yaml#/definitions/uint8-array > >Why? That's not a standard property though, so needs a 'rockchip' >prefix. Though maybe a common property would be appropriate here. Originally it was a bool property named "rockchip,bifurcation" and we changed it (after comments) to be a more generic property "lane-map" that can be re-used on other vendors/controllers/phys. Driver reads as u8 array and range is small enough for u8 even if used for larger controllers (e.g. PCIe x16). >> then it looks clean for it.... >> >> -m causes many errors unrelated to this schema-file even if i pass >> >DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > >The fix is fixing the remaining 40 or so '-m' errors. So now clean for you(r bot), too? Did only get a bunch of other unrelated messages. >Rob regards Frank _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy 2022-05-16 19:21 ` Frank Wunderlich (?) (?) @ 2022-05-18 15:55 ` Rob Herring -1 siblings, 0 replies; 60+ messages in thread From: Rob Herring @ 2022-05-18 15:55 UTC (permalink / raw) To: Frank Wunderlich Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński On Mon, May 16, 2022 at 09:21:31PM +0200, Frank Wunderlich wrote: > Am 16. Mai 2022 19:35:37 MESZ schrieb Rob Herring <robh@kernel.org>: > >On Sun, May 15, 2022 at 01:49:47PM +0200, Frank Wunderlich wrote: > >> Hi > >> > >> > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr > >> > Von: "Rob Herring" <robh@kernel.org> > >> > >> > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > > >Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > >> > > > >> > > >> > My bot found errors running 'make DT_CHECKER_FLAGS=-m > >dt_binding_check' > >> > on your patch (DT_CHECKER_FLAGS is new in v5.13): > >> > > >> > yamllint warnings/errors: > >> > > >> > dtschema/dtc warnings/errors: > >> > > >/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: > >properties:clock-names: 'oneOf' conditional failed, one must be fixed: > >> > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] > >is too long > >> > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] > >is too short > >> > False schema does not allow 3 > >> > 1 was expected > >> > 3 is greater than the maximum of 2 > >> > hint: "minItems" is only needed if less than the "items" list > >length > >> > from schema $id: http://devicetree.org/meta-schemas/items.yaml# > >> > > >/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: > >ignoring, error in schema: properties: clock-names > >> > > >Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: > >/example-0/phy@fe8c0000: failed to match any schema with compatible: > >['rockchip,rk3568-pcie3-phy'] > >> > >> seems this is fixed when i remove the "minItems: 3" from clock names > >> (which is already fixed length because of the list). > > > >Yes. > > > >> needed to change type of lane-map to this: > >> > >> $ref: /schemas/types.yaml#/definitions/uint8-array > > > >Why? That's not a standard property though, so needs a 'rockchip' > >prefix. Though maybe a common property would be appropriate here. > > Originally it was a bool property named "rockchip,bifurcation" and we > changed it (after comments) to be a more generic property "lane-map" > that can be re-used on other vendors/controllers/phys. Fair enough. The type needs to be defined in a common binding though. phy/phy-provider.yaml in dtschema probably. We already have clock-lanes and data-lanes for other serdes interfaces. Maybe data-lanes works here? > Driver reads as u8 array and range is small enough for u8 even if > used for larger controllers (e.g. PCIe x16). Not arguing that it shouldn't be, just confused how the type was related to warnings. > > >> then it looks clean for it.... > >> > >> -m causes many errors unrelated to this schema-file even if i pass > >> > >DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > > > >The fix is fixing the remaining 40 or so '-m' errors. > > So now clean for you(r bot), too? Did only get a bunch of other unrelated messages. No, the bot does a baseline build and extracts the diff in warnings. Still too many warnings popping up frequently... :( Rob ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-18 15:55 ` Rob Herring 0 siblings, 0 replies; 60+ messages in thread From: Rob Herring @ 2022-05-18 15:55 UTC (permalink / raw) To: Frank Wunderlich Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński On Mon, May 16, 2022 at 09:21:31PM +0200, Frank Wunderlich wrote: > Am 16. Mai 2022 19:35:37 MESZ schrieb Rob Herring <robh@kernel.org>: > >On Sun, May 15, 2022 at 01:49:47PM +0200, Frank Wunderlich wrote: > >> Hi > >> > >> > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr > >> > Von: "Rob Herring" <robh@kernel.org> > >> > >> > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > > >Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > >> > > > >> > > >> > My bot found errors running 'make DT_CHECKER_FLAGS=-m > >dt_binding_check' > >> > on your patch (DT_CHECKER_FLAGS is new in v5.13): > >> > > >> > yamllint warnings/errors: > >> > > >> > dtschema/dtc warnings/errors: > >> > > >/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: > >properties:clock-names: 'oneOf' conditional failed, one must be fixed: > >> > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] > >is too long > >> > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] > >is too short > >> > False schema does not allow 3 > >> > 1 was expected > >> > 3 is greater than the maximum of 2 > >> > hint: "minItems" is only needed if less than the "items" list > >length > >> > from schema $id: http://devicetree.org/meta-schemas/items.yaml# > >> > > >/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: > >ignoring, error in schema: properties: clock-names > >> > > >Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: > >/example-0/phy@fe8c0000: failed to match any schema with compatible: > >['rockchip,rk3568-pcie3-phy'] > >> > >> seems this is fixed when i remove the "minItems: 3" from clock names > >> (which is already fixed length because of the list). > > > >Yes. > > > >> needed to change type of lane-map to this: > >> > >> $ref: /schemas/types.yaml#/definitions/uint8-array > > > >Why? That's not a standard property though, so needs a 'rockchip' > >prefix. Though maybe a common property would be appropriate here. > > Originally it was a bool property named "rockchip,bifurcation" and we > changed it (after comments) to be a more generic property "lane-map" > that can be re-used on other vendors/controllers/phys. Fair enough. The type needs to be defined in a common binding though. phy/phy-provider.yaml in dtschema probably. We already have clock-lanes and data-lanes for other serdes interfaces. Maybe data-lanes works here? > Driver reads as u8 array and range is small enough for u8 even if > used for larger controllers (e.g. PCIe x16). Not arguing that it shouldn't be, just confused how the type was related to warnings. > > >> then it looks clean for it.... > >> > >> -m causes many errors unrelated to this schema-file even if i pass > >> > >DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > > > >The fix is fixing the remaining 40 or so '-m' errors. > > So now clean for you(r bot), too? Did only get a bunch of other unrelated messages. No, the bot does a baseline build and extracts the diff in warnings. Still too many warnings popping up frequently... :( Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-18 15:55 ` Rob Herring 0 siblings, 0 replies; 60+ messages in thread From: Rob Herring @ 2022-05-18 15:55 UTC (permalink / raw) To: Frank Wunderlich Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński On Mon, May 16, 2022 at 09:21:31PM +0200, Frank Wunderlich wrote: > Am 16. Mai 2022 19:35:37 MESZ schrieb Rob Herring <robh@kernel.org>: > >On Sun, May 15, 2022 at 01:49:47PM +0200, Frank Wunderlich wrote: > >> Hi > >> > >> > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr > >> > Von: "Rob Herring" <robh@kernel.org> > >> > >> > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > > >Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > >> > > > >> > > >> > My bot found errors running 'make DT_CHECKER_FLAGS=-m > >dt_binding_check' > >> > on your patch (DT_CHECKER_FLAGS is new in v5.13): > >> > > >> > yamllint warnings/errors: > >> > > >> > dtschema/dtc warnings/errors: > >> > > >/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: > >properties:clock-names: 'oneOf' conditional failed, one must be fixed: > >> > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] > >is too long > >> > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] > >is too short > >> > False schema does not allow 3 > >> > 1 was expected > >> > 3 is greater than the maximum of 2 > >> > hint: "minItems" is only needed if less than the "items" list > >length > >> > from schema $id: http://devicetree.org/meta-schemas/items.yaml# > >> > > >/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: > >ignoring, error in schema: properties: clock-names > >> > > >Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: > >/example-0/phy@fe8c0000: failed to match any schema with compatible: > >['rockchip,rk3568-pcie3-phy'] > >> > >> seems this is fixed when i remove the "minItems: 3" from clock names > >> (which is already fixed length because of the list). > > > >Yes. > > > >> needed to change type of lane-map to this: > >> > >> $ref: /schemas/types.yaml#/definitions/uint8-array > > > >Why? That's not a standard property though, so needs a 'rockchip' > >prefix. Though maybe a common property would be appropriate here. > > Originally it was a bool property named "rockchip,bifurcation" and we > changed it (after comments) to be a more generic property "lane-map" > that can be re-used on other vendors/controllers/phys. Fair enough. The type needs to be defined in a common binding though. phy/phy-provider.yaml in dtschema probably. We already have clock-lanes and data-lanes for other serdes interfaces. Maybe data-lanes works here? > Driver reads as u8 array and range is small enough for u8 even if > used for larger controllers (e.g. PCIe x16). Not arguing that it shouldn't be, just confused how the type was related to warnings. > > >> then it looks clean for it.... > >> > >> -m causes many errors unrelated to this schema-file even if i pass > >> > >DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > > > >The fix is fixing the remaining 40 or so '-m' errors. > > So now clean for you(r bot), too? Did only get a bunch of other unrelated messages. No, the bot does a baseline build and extracts the diff in warnings. Still too many warnings popping up frequently... :( Rob -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-18 15:55 ` Rob Herring 0 siblings, 0 replies; 60+ messages in thread From: Rob Herring @ 2022-05-18 15:55 UTC (permalink / raw) To: Frank Wunderlich Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński On Mon, May 16, 2022 at 09:21:31PM +0200, Frank Wunderlich wrote: > Am 16. Mai 2022 19:35:37 MESZ schrieb Rob Herring <robh@kernel.org>: > >On Sun, May 15, 2022 at 01:49:47PM +0200, Frank Wunderlich wrote: > >> Hi > >> > >> > Gesendet: Sonntag, 15. Mai 2022 um 01:14 Uhr > >> > Von: "Rob Herring" <robh@kernel.org> > >> > >> > On Sat, 14 May 2022 13:59:42 +0200, Frank Wunderlich wrote: > > >Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > >> > > > >> > > >> > My bot found errors running 'make DT_CHECKER_FLAGS=-m > >dt_binding_check' > >> > on your patch (DT_CHECKER_FLAGS is new in v5.13): > >> > > >> > yamllint warnings/errors: > >> > > >> > dtschema/dtc warnings/errors: > >> > > >/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: > >properties:clock-names: 'oneOf' conditional failed, one must be fixed: > >> > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] > >is too long > >> > [{'const': 'refclk_m'}, {'const': 'refclk_n'}, {'const': 'pclk'}] > >is too short > >> > False schema does not allow 3 > >> > 1 was expected > >> > 3 is greater than the maximum of 2 > >> > hint: "minItems" is only needed if less than the "items" list > >length > >> > from schema $id: http://devicetree.org/meta-schemas/items.yaml# > >> > > >/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml: > >ignoring, error in schema: properties: clock-names > >> > > >Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.example.dtb:0:0: > >/example-0/phy@fe8c0000: failed to match any schema with compatible: > >['rockchip,rk3568-pcie3-phy'] > >> > >> seems this is fixed when i remove the "minItems: 3" from clock names > >> (which is already fixed length because of the list). > > > >Yes. > > > >> needed to change type of lane-map to this: > >> > >> $ref: /schemas/types.yaml#/definitions/uint8-array > > > >Why? That's not a standard property though, so needs a 'rockchip' > >prefix. Though maybe a common property would be appropriate here. > > Originally it was a bool property named "rockchip,bifurcation" and we > changed it (after comments) to be a more generic property "lane-map" > that can be re-used on other vendors/controllers/phys. Fair enough. The type needs to be defined in a common binding though. phy/phy-provider.yaml in dtschema probably. We already have clock-lanes and data-lanes for other serdes interfaces. Maybe data-lanes works here? > Driver reads as u8 array and range is small enough for u8 even if > used for larger controllers (e.g. PCIe x16). Not arguing that it shouldn't be, just confused how the type was related to warnings. > > >> then it looks clean for it.... > >> > >> -m causes many errors unrelated to this schema-file even if i pass > >> > >DT_SCHEMA_FILES=Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > > > >The fix is fixing the remaining 40 or so '-m' errors. > > So now clean for you(r bot), too? Did only get a bunch of other unrelated messages. No, the bot does a baseline build and extracts the diff in warnings. Still too many warnings popping up frequently... :( Rob _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 60+ messages in thread
* Aw: Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy 2022-05-18 15:55 ` Rob Herring (?) (?) @ 2022-05-20 11:50 ` Frank Wunderlich -1 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-20 11:50 UTC (permalink / raw) To: Rob Herring Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński Hi, fixed reg-error by using 32bit-address in example, in my test output is clean. +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -68,7 +68,7 @@ examples: #include <dt-bindings/clock/rk3568-cru.h> pcie30phy: phy@fe8c0000 { compatible = "rockchip,rk3568-pcie3-phy"; - reg = <0x0 0xfe8c0000 0x0 0x20000>; + reg = <0xfe8c0000 0x20000>; i hope yours is clean too regarding data-lanes instead of own lane-map, Peter and me only find this in special bindings outside the phy-"namespace" like this. https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/media/video-interfaces.yaml#L157 do you mean converting this binding and add it there and base out binding on it? https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/phy/phy-bindings.txt regards Frank ^ permalink raw reply [flat|nested] 60+ messages in thread
* Aw: Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-20 11:50 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-20 11:50 UTC (permalink / raw) To: Rob Herring Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński Hi, fixed reg-error by using 32bit-address in example, in my test output is clean. +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -68,7 +68,7 @@ examples: #include <dt-bindings/clock/rk3568-cru.h> pcie30phy: phy@fe8c0000 { compatible = "rockchip,rk3568-pcie3-phy"; - reg = <0x0 0xfe8c0000 0x0 0x20000>; + reg = <0xfe8c0000 0x20000>; i hope yours is clean too regarding data-lanes instead of own lane-map, Peter and me only find this in special bindings outside the phy-"namespace" like this. https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/media/video-interfaces.yaml#L157 do you mean converting this binding and add it there and base out binding on it? https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/phy/phy-bindings.txt regards Frank -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 60+ messages in thread
* Aw: Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-20 11:50 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-20 11:50 UTC (permalink / raw) To: Rob Herring Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński Hi, fixed reg-error by using 32bit-address in example, in my test output is clean. +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -68,7 +68,7 @@ examples: #include <dt-bindings/clock/rk3568-cru.h> pcie30phy: phy@fe8c0000 { compatible = "rockchip,rk3568-pcie3-phy"; - reg = <0x0 0xfe8c0000 0x0 0x20000>; + reg = <0xfe8c0000 0x20000>; i hope yours is clean too regarding data-lanes instead of own lane-map, Peter and me only find this in special bindings outside the phy-"namespace" like this. https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/media/video-interfaces.yaml#L157 do you mean converting this binding and add it there and base out binding on it? https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/phy/phy-bindings.txt regards Frank _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 60+ messages in thread
* Aw: Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-05-20 11:50 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-20 11:50 UTC (permalink / raw) To: Rob Herring Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński Hi, fixed reg-error by using 32bit-address in example, in my test output is clean. +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -68,7 +68,7 @@ examples: #include <dt-bindings/clock/rk3568-cru.h> pcie30phy: phy@fe8c0000 { compatible = "rockchip,rk3568-pcie3-phy"; - reg = <0x0 0xfe8c0000 0x0 0x20000>; + reg = <0xfe8c0000 0x20000>; i hope yours is clean too regarding data-lanes instead of own lane-map, Peter and me only find this in special bindings outside the phy-"namespace" like this. https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/media/video-interfaces.yaml#L157 do you mean converting this binding and add it there and base out binding on it? https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/phy/phy-bindings.txt regards Frank _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 60+ messages in thread
* Aw: Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy 2022-05-20 11:50 ` Frank Wunderlich (?) (?) @ 2022-06-02 13:47 ` Frank Wunderlich -1 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-06-02 13:47 UTC (permalink / raw) To: Rob Herring Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński > Gesendet: Freitag, 20. Mai 2022 um 13:50 Uhr > Von: "Frank Wunderlich" <frank-w@public-files.de> > An: "Rob Herring" <robh@kernel.org> > Hi, > > fixed reg-error by using 32bit-address in example, in my test output is clean. > > +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > @@ -68,7 +68,7 @@ examples: > #include <dt-bindings/clock/rk3568-cru.h> > pcie30phy: phy@fe8c0000 { > compatible = "rockchip,rk3568-pcie3-phy"; > - reg = <0x0 0xfe8c0000 0x0 0x20000>; > + reg = <0xfe8c0000 0x20000>; > > > i hope yours is clean too have you tried it? > regarding data-lanes instead of own lane-map, Peter and me only find this in special > bindings outside the phy-"namespace" like this. > > https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/media/video-interfaces.yaml#L157 > > do you mean converting this binding and add it there and base out binding on it? > > https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/phy/phy-bindings.txt is this the right binding to add the data-lanes or do you refer another one (have not found phy-provider)? regards Frank -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 60+ messages in thread
* Aw: Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-06-02 13:47 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-06-02 13:47 UTC (permalink / raw) To: Rob Herring Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński > Gesendet: Freitag, 20. Mai 2022 um 13:50 Uhr > Von: "Frank Wunderlich" <frank-w@public-files.de> > An: "Rob Herring" <robh@kernel.org> > Hi, > > fixed reg-error by using 32bit-address in example, in my test output is clean. > > +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > @@ -68,7 +68,7 @@ examples: > #include <dt-bindings/clock/rk3568-cru.h> > pcie30phy: phy@fe8c0000 { > compatible = "rockchip,rk3568-pcie3-phy"; > - reg = <0x0 0xfe8c0000 0x0 0x20000>; > + reg = <0xfe8c0000 0x20000>; > > > i hope yours is clean too have you tried it? > regarding data-lanes instead of own lane-map, Peter and me only find this in special > bindings outside the phy-"namespace" like this. > > https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/media/video-interfaces.yaml#L157 > > do you mean converting this binding and add it there and base out binding on it? > > https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/phy/phy-bindings.txt is this the right binding to add the data-lanes or do you refer another one (have not found phy-provider)? regards Frank _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 60+ messages in thread
* Aw: Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-06-02 13:47 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-06-02 13:47 UTC (permalink / raw) To: Rob Herring Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński > Gesendet: Freitag, 20. Mai 2022 um 13:50 Uhr > Von: "Frank Wunderlich" <frank-w@public-files.de> > An: "Rob Herring" <robh@kernel.org> > Hi, > > fixed reg-error by using 32bit-address in example, in my test output is clean. > > +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > @@ -68,7 +68,7 @@ examples: > #include <dt-bindings/clock/rk3568-cru.h> > pcie30phy: phy@fe8c0000 { > compatible = "rockchip,rk3568-pcie3-phy"; > - reg = <0x0 0xfe8c0000 0x0 0x20000>; > + reg = <0xfe8c0000 0x20000>; > > > i hope yours is clean too have you tried it? > regarding data-lanes instead of own lane-map, Peter and me only find this in special > bindings outside the phy-"namespace" like this. > > https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/media/video-interfaces.yaml#L157 > > do you mean converting this binding and add it there and base out binding on it? > > https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/phy/phy-bindings.txt is this the right binding to add the data-lanes or do you refer another one (have not found phy-provider)? regards Frank _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 60+ messages in thread
* Aw: Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy @ 2022-06-02 13:47 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-06-02 13:47 UTC (permalink / raw) To: Rob Herring Cc: Frank Wunderlich, Michael Riesch, Vinod Koul, Johan Jonker, linux-rockchip, linux-pci, Kishon Vijay Abraham I, linux-kernel, linux-phy, Bjorn Helgaas, Philipp Zabel, Lorenzo Pieralisi, Peter Geis, Heiko Stuebner, Krzysztof Kozlowski, linux-arm-kernel, devicetree, Krzysztof Wilczyński > Gesendet: Freitag, 20. Mai 2022 um 13:50 Uhr > Von: "Frank Wunderlich" <frank-w@public-files.de> > An: "Rob Herring" <robh@kernel.org> > Hi, > > fixed reg-error by using 32bit-address in example, in my test output is clean. > > +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml > @@ -68,7 +68,7 @@ examples: > #include <dt-bindings/clock/rk3568-cru.h> > pcie30phy: phy@fe8c0000 { > compatible = "rockchip,rk3568-pcie3-phy"; > - reg = <0x0 0xfe8c0000 0x0 0x20000>; > + reg = <0xfe8c0000 0x20000>; > > > i hope yours is clean too have you tried it? > regarding data-lanes instead of own lane-map, Peter and me only find this in special > bindings outside the phy-"namespace" like this. > > https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/media/video-interfaces.yaml#L157 > > do you mean converting this binding and add it there and base out binding on it? > > https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/phy/phy-bindings.txt is this the right binding to add the data-lanes or do you refer another one (have not found phy-provider)? regards Frank ^ permalink raw reply [flat|nested] 60+ messages in thread
* [RFC v3 2/5] dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf 2022-05-14 11:59 ` Frank Wunderlich (?) (?) @ 2022-05-14 11:59 ` Frank Wunderlich -1 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> Add compatibles for PCIe v3 General Register Files. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - fix order of grf-bindings v2: - add soc-part to pcie3-phy-grf --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 3be3cfd52f7b..a854e1f10d63 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -16,7 +16,10 @@ properties: - enum: - rockchip,rk3288-sgrf - rockchip,rk3566-pipe-grf + - rockchip,rk3568-pcie3-phy-grf - rockchip,rk3568-usb2phy-grf + - rockchip,rk3588-pcie3-phy-grf + - rockchip,rk3588-pcie3-pipe-grf - rockchip,rv1108-usbgrf - const: syscon - items: -- 2.25.1 ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 2/5] dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> Add compatibles for PCIe v3 General Register Files. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - fix order of grf-bindings v2: - add soc-part to pcie3-phy-grf --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 3be3cfd52f7b..a854e1f10d63 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -16,7 +16,10 @@ properties: - enum: - rockchip,rk3288-sgrf - rockchip,rk3566-pipe-grf + - rockchip,rk3568-pcie3-phy-grf - rockchip,rk3568-usb2phy-grf + - rockchip,rk3588-pcie3-phy-grf + - rockchip,rk3588-pcie3-pipe-grf - rockchip,rv1108-usbgrf - const: syscon - items: -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 2/5] dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> Add compatibles for PCIe v3 General Register Files. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - fix order of grf-bindings v2: - add soc-part to pcie3-phy-grf --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 3be3cfd52f7b..a854e1f10d63 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -16,7 +16,10 @@ properties: - enum: - rockchip,rk3288-sgrf - rockchip,rk3566-pipe-grf + - rockchip,rk3568-pcie3-phy-grf - rockchip,rk3568-usb2phy-grf + - rockchip,rk3588-pcie3-phy-grf + - rockchip,rk3588-pcie3-pipe-grf - rockchip,rv1108-usbgrf - const: syscon - items: -- 2.25.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 2/5] dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> Add compatibles for PCIe v3 General Register Files. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - fix order of grf-bindings v2: - add soc-part to pcie3-phy-grf --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 3be3cfd52f7b..a854e1f10d63 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -16,7 +16,10 @@ properties: - enum: - rockchip,rk3288-sgrf - rockchip,rk3566-pipe-grf + - rockchip,rk3568-pcie3-phy-grf - rockchip,rk3568-usb2phy-grf + - rockchip,rk3588-pcie3-phy-grf + - rockchip,rk3588-pcie3-pipe-grf - rockchip,rv1108-usbgrf - const: syscon - items: -- 2.25.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 60+ messages in thread
* Re: [RFC v3 2/5] dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf 2022-05-14 11:59 ` Frank Wunderlich (?) (?) @ 2022-05-14 20:43 ` Krzysztof Kozlowski -1 siblings, 0 replies; 60+ messages in thread From: Krzysztof Kozlowski @ 2022-05-14 20:43 UTC (permalink / raw) To: Frank Wunderlich, linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy On 14/05/2022 13:59, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > Add compatibles for PCIe v3 General Register Files. > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [RFC v3 2/5] dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf @ 2022-05-14 20:43 ` Krzysztof Kozlowski 0 siblings, 0 replies; 60+ messages in thread From: Krzysztof Kozlowski @ 2022-05-14 20:43 UTC (permalink / raw) To: Frank Wunderlich, linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy On 14/05/2022 13:59, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > Add compatibles for PCIe v3 General Register Files. > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [RFC v3 2/5] dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf @ 2022-05-14 20:43 ` Krzysztof Kozlowski 0 siblings, 0 replies; 60+ messages in thread From: Krzysztof Kozlowski @ 2022-05-14 20:43 UTC (permalink / raw) To: Frank Wunderlich, linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy On 14/05/2022 13:59, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > Add compatibles for PCIe v3 General Register Files. > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [RFC v3 2/5] dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf @ 2022-05-14 20:43 ` Krzysztof Kozlowski 0 siblings, 0 replies; 60+ messages in thread From: Krzysztof Kozlowski @ 2022-05-14 20:43 UTC (permalink / raw) To: Frank Wunderlich, linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy On 14/05/2022 13:59, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > Add compatibles for PCIe v3 General Register Files. > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 60+ messages in thread
* [RFC v3 3/5] phy: rockchip: Support PCIe v3 2022-05-14 11:59 ` Frank Wunderlich (?) (?) @ 2022-05-14 11:59 ` Frank Wunderlich -1 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy, Shawn Lin From: Shawn Lin <shawn.lin@rock-chips.com> RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566. It use a dedicated PCIe-phy. Add support for this. Initial support by Shawn Lin, modifications by Peter Geis and Frank Wunderlich. Add lane-map support for splitting pcie-lanes across controllers. The lane-map is an array where x=0 means lane is disabled and x > 0 means controller x is assigned to phy lane. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Suggested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - change dt-binding include - change reset to devm_reset_control_get_optional_exclusive exit on error and lower severity of message if unset - fix from peter: disable reg-write for phy-mode in rockchip_p3phy_probe - move bifurcation/lane-map support from PCIe to phy driver v2: - move dt-bindings header into separate patch - use BIT-macro - make constants better readable - use dev_err instead of pr_* - change dt-binding include due to renaming (phy-snps-pcie3.h => phy-rockchip-pcie3.h) - use exclusive variant of devm_reset_control_get{,_exclusive} - fix semicolon.cocci warnings reported by kernel test robot <lkp@intel.com> --- driver was taken from linux 5.10 based on in https://github.com/JeffyCN/mirrors which now has disappeared --- drivers/phy/rockchip/Kconfig | 9 + drivers/phy/rockchip/Makefile | 1 + .../phy/rockchip/phy-rockchip-snps-pcie3.c | 317 ++++++++++++++++++ include/linux/phy/pcie.h | 12 + 4 files changed, 339 insertions(+) create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c create mode 100644 include/linux/phy/pcie.h diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index 9022e395c056..94360fc96a6f 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -83,6 +83,15 @@ config PHY_ROCKCHIP_PCIE help Enable this to support the Rockchip PCIe PHY. +config PHY_ROCKCHIP_SNPS_PCIE3 + tristate "Rockchip Snps PCIe3 PHY Driver" + depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST + depends on HAS_IOMEM + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support the Rockchip snps PCIe3 PHY. + config PHY_ROCKCHIP_TYPEC tristate "Rockchip TYPEC PHY Driver" depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST) diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index a5041efb5b8f..7eab129230d1 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o +obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c new file mode 100644 index 000000000000..9d8fadff8a04 --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip PCIE3.0 phy driver + * + * Copyright (C) 2020 Rockchip Electronics Co., Ltd. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/phy/pcie.h> +#include <linux/phy/phy.h> +#include <linux/regmap.h> +#include <linux/reset.h> + +/* Register for RK3568 */ +#define GRF_PCIE30PHY_CON1 0x4 +#define GRF_PCIE30PHY_CON6 0x18 +#define GRF_PCIE30PHY_CON9 0x24 +#define GRF_PCIE30PHY_STATUS0 0x80 +#define SRAM_INIT_DONE(reg) (reg & BIT(14)) + +#define RK3568_BIFURCATION_LANE_0_1 BIT(0) + +/* Register for RK3588 */ +#define PHP_GRF_PCIESEL_CON 0x100 +#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0 +#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904 +#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04 +#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0)) + +#define RK3588_BIFURCATION_LANE_0_1 BIT(0) +#define RK3588_BIFURCATION_LANE_2_3 BIT(1) +#define RK3588_LANE_AGGREGATION BIT(2) + +struct rockchip_p3phy_ops; + +struct rockchip_p3phy_priv { + const struct rockchip_p3phy_ops *ops; + void __iomem *mmio; + /* mode: RC, EP */ + int mode; + /* pcie30_phymode: Aggregation, Bifurcation */ + int pcie30_phymode; + struct regmap *phy_grf; + struct regmap *pipe_grf; + struct reset_control *p30phy; + struct phy *phy; + struct clk_bulk_data *clks; + int num_clks; + int num_lanes; + u8 lanes[4]; +}; + +struct rockchip_p3phy_ops { + int (*phy_init)(struct rockchip_p3phy_priv *priv); +}; + +static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + + /* Actually We don't care EP/RC mode, but just record it */ + switch (submode) { + case PHY_MODE_PCIE_RC: + priv->mode = PHY_MODE_PCIE_RC; + break; + case PHY_MODE_PCIE_EP: + priv->mode = PHY_MODE_PCIE_EP; + break; + default: + dev_err(&phy->dev, "%s, invalid mode\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv) +{ + struct phy *phy = priv->phy; + bool bifurcation = false; + int ret; + u32 reg; + + /* Deassert PCIe PMA output clamp mode */ + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, BIT(15) | BIT(31)); + + for (int i = 0; i < priv->num_lanes; i++) { + dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]); + if (priv->lanes[i] > 1) + bifurcation = true; + } + + /* Set bifurcation if needed, and it doesn't care RC/EP */ + if (bifurcation) { + dev_info(&phy->dev, "bifurcation enabled\n"); + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, + (0xf << 16) | RK3568_BIFURCATION_LANE_0_1); + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1, + BIT(15) | BIT(31)); + } else { + dev_info(&phy->dev, "bifurcation disabled\n"); + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, + (0xf << 16) & ~RK3568_BIFURCATION_LANE_0_1); + } + + reset_control_deassert(priv->p30phy); + + ret = regmap_read_poll_timeout(priv->phy_grf, + GRF_PCIE30PHY_STATUS0, + reg, SRAM_INIT_DONE(reg), + 0, 500); + if (ret) + dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n", + __func__, reg); + return ret; +} + +static const struct rockchip_p3phy_ops rk3568_ops = { + .phy_init = rockchip_p3phy_rk3568_init, +}; + +static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv) +{ + u32 reg = 0; + u8 mode = 0; + int ret; + + /* Deassert PCIe PMA output clamp mode */ + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24)); + + /* Set bifurcation if needed */ + for (int i = 0; i < priv->num_lanes; i++) { + if (!priv->lanes[i]) + mode |= (BIT(i) << 3); + + if (priv->lanes[i] > 1) + mode |= (BIT(i) >> 1); + } + + if (!mode) + reg = RK3588_LANE_AGGREGATION; + else { + if (mode & (BIT(0) | BIT(1))) + reg |= RK3588_BIFURCATION_LANE_0_1; + + if (mode & (BIT(2) | BIT(3))) + reg |= RK3588_BIFURCATION_LANE_2_3; + } + + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg); + + /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */ + if (!IS_ERR(priv->pipe_grf)) { + reg = (mode & (BIT(6) | BIT(7))) >> 6; + if (reg) + regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON, + (reg << 16) | reg); + } + + reset_control_deassert(priv->p30phy); + + ret = regmap_read_poll_timeout(priv->phy_grf, + RK3588_PCIE3PHY_GRF_PHY0_STATUS1, + reg, RK3588_SRAM_INIT_DONE(reg), + 0, 500); + ret |= regmap_read_poll_timeout(priv->phy_grf, + RK3588_PCIE3PHY_GRF_PHY1_STATUS1, + reg, RK3588_SRAM_INIT_DONE(reg), + 0, 500); + if (ret) + pr_err("%s: lock failed 0x%x, check input refclk and power supply\n", + __func__, reg); + return ret; +} + +static const struct rockchip_p3phy_ops rk3588_ops = { + .phy_init = rockchip_p3phy_rk3588_init, +}; + +static int rochchip_p3phy_init(struct phy *phy) +{ + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) { + pr_err("failed to enable PCIe bulk clks %d\n", ret); + return ret; + } + + reset_control_assert(priv->p30phy); + udelay(1); + + if (priv->ops->phy_init) { + ret = priv->ops->phy_init(priv); + if (ret) + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + } + + return ret; +} + +static int rochchip_p3phy_exit(struct phy *phy) +{ + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + reset_control_assert(priv->p30phy); + return 0; +} + +static const struct phy_ops rochchip_p3phy_ops = { + .init = rochchip_p3phy_init, + .exit = rochchip_p3phy_exit, + .set_mode = rockchip_p3phy_set_mode, + .owner = THIS_MODULE, +}; + +static int rockchip_p3phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct rockchip_p3phy_priv *priv; + struct device_node *np = dev->of_node; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->mmio = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->mmio)) { + ret = PTR_ERR(priv->mmio); + return ret; + } + + priv->ops = of_device_get_match_data(&pdev->dev); + if (!priv->ops) { + dev_err(&pdev->dev, "no of match data provided\n"); + return -EINVAL; + } + + priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf"); + if (IS_ERR(priv->phy_grf)) { + dev_err(dev, "failed to find rockchip,phy_grf regmap\n"); + return PTR_ERR(priv->phy_grf); + } + + priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, + "rockchip,pipe-grf"); + if (IS_ERR(priv->pipe_grf)) + dev_info(dev, "failed to find rockchip,pipe_grf regmap\n"); + + priv->num_lanes = of_property_read_variable_u8_array(dev->of_node, "lane-map", + priv->lanes, 2, + ARRAY_SIZE(priv->lanes)); + + /* if no lane-map assume aggregation */ + if (priv->num_lanes == -EINVAL) { + dev_dbg(dev, "no lane-map property found\n"); + priv->num_lanes = 1; + priv->lanes[0] = 1; + } else if (priv->num_lanes < 0) { + dev_err(dev, "failed to read lane-map property %d\n", priv->num_lanes); + return priv->num_lanes; + } + + priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops); + if (IS_ERR(priv->phy)) { + dev_err(dev, "failed to create combphy\n"); + return PTR_ERR(priv->phy); + } + + priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy"); + if (IS_ERR(priv->p30phy)) { + return dev_err_probe(dev, PTR_ERR(priv->p30phy), + "failed to get phy reset control\n"); + } + if (!priv->p30phy) + dev_info(dev, "no phy reset control specified\n"); + + priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); + if (priv->num_clks < 1) + return -ENODEV; + + dev_set_drvdata(dev, priv); + phy_set_drvdata(priv->phy, priv); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id rockchip_p3phy_of_match[] = { + { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops }, + { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops }, + { }, +}; +MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match); + +static struct platform_driver rockchip_p3phy_driver = { + .probe = rockchip_p3phy_probe, + .driver = { + .name = "rockchip-snps-pcie3-phy", + .of_match_table = rockchip_p3phy_of_match, + }, +}; +module_platform_driver(rockchip_p3phy_driver); +MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/phy/pcie.h b/include/linux/phy/pcie.h new file mode 100644 index 000000000000..93c997f520fe --- /dev/null +++ b/include/linux/phy/pcie.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ +#ifndef __PHY_PCIE_H +#define __PHY_PCIE_H + +#define PHY_MODE_PCIE_RC 20 +#define PHY_MODE_PCIE_EP 21 +#define PHY_MODE_PCIE_BIFURCATION 22 + +#endif -- 2.25.1 ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 3/5] phy: rockchip: Support PCIe v3 @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy, Shawn Lin From: Shawn Lin <shawn.lin@rock-chips.com> RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566. It use a dedicated PCIe-phy. Add support for this. Initial support by Shawn Lin, modifications by Peter Geis and Frank Wunderlich. Add lane-map support for splitting pcie-lanes across controllers. The lane-map is an array where x=0 means lane is disabled and x > 0 means controller x is assigned to phy lane. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Suggested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - change dt-binding include - change reset to devm_reset_control_get_optional_exclusive exit on error and lower severity of message if unset - fix from peter: disable reg-write for phy-mode in rockchip_p3phy_probe - move bifurcation/lane-map support from PCIe to phy driver v2: - move dt-bindings header into separate patch - use BIT-macro - make constants better readable - use dev_err instead of pr_* - change dt-binding include due to renaming (phy-snps-pcie3.h => phy-rockchip-pcie3.h) - use exclusive variant of devm_reset_control_get{,_exclusive} - fix semicolon.cocci warnings reported by kernel test robot <lkp@intel.com> --- driver was taken from linux 5.10 based on in https://github.com/JeffyCN/mirrors which now has disappeared --- drivers/phy/rockchip/Kconfig | 9 + drivers/phy/rockchip/Makefile | 1 + .../phy/rockchip/phy-rockchip-snps-pcie3.c | 317 ++++++++++++++++++ include/linux/phy/pcie.h | 12 + 4 files changed, 339 insertions(+) create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c create mode 100644 include/linux/phy/pcie.h diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index 9022e395c056..94360fc96a6f 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -83,6 +83,15 @@ config PHY_ROCKCHIP_PCIE help Enable this to support the Rockchip PCIe PHY. +config PHY_ROCKCHIP_SNPS_PCIE3 + tristate "Rockchip Snps PCIe3 PHY Driver" + depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST + depends on HAS_IOMEM + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support the Rockchip snps PCIe3 PHY. + config PHY_ROCKCHIP_TYPEC tristate "Rockchip TYPEC PHY Driver" depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST) diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index a5041efb5b8f..7eab129230d1 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o +obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c new file mode 100644 index 000000000000..9d8fadff8a04 --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip PCIE3.0 phy driver + * + * Copyright (C) 2020 Rockchip Electronics Co., Ltd. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/phy/pcie.h> +#include <linux/phy/phy.h> +#include <linux/regmap.h> +#include <linux/reset.h> + +/* Register for RK3568 */ +#define GRF_PCIE30PHY_CON1 0x4 +#define GRF_PCIE30PHY_CON6 0x18 +#define GRF_PCIE30PHY_CON9 0x24 +#define GRF_PCIE30PHY_STATUS0 0x80 +#define SRAM_INIT_DONE(reg) (reg & BIT(14)) + +#define RK3568_BIFURCATION_LANE_0_1 BIT(0) + +/* Register for RK3588 */ +#define PHP_GRF_PCIESEL_CON 0x100 +#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0 +#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904 +#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04 +#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0)) + +#define RK3588_BIFURCATION_LANE_0_1 BIT(0) +#define RK3588_BIFURCATION_LANE_2_3 BIT(1) +#define RK3588_LANE_AGGREGATION BIT(2) + +struct rockchip_p3phy_ops; + +struct rockchip_p3phy_priv { + const struct rockchip_p3phy_ops *ops; + void __iomem *mmio; + /* mode: RC, EP */ + int mode; + /* pcie30_phymode: Aggregation, Bifurcation */ + int pcie30_phymode; + struct regmap *phy_grf; + struct regmap *pipe_grf; + struct reset_control *p30phy; + struct phy *phy; + struct clk_bulk_data *clks; + int num_clks; + int num_lanes; + u8 lanes[4]; +}; + +struct rockchip_p3phy_ops { + int (*phy_init)(struct rockchip_p3phy_priv *priv); +}; + +static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + + /* Actually We don't care EP/RC mode, but just record it */ + switch (submode) { + case PHY_MODE_PCIE_RC: + priv->mode = PHY_MODE_PCIE_RC; + break; + case PHY_MODE_PCIE_EP: + priv->mode = PHY_MODE_PCIE_EP; + break; + default: + dev_err(&phy->dev, "%s, invalid mode\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv) +{ + struct phy *phy = priv->phy; + bool bifurcation = false; + int ret; + u32 reg; + + /* Deassert PCIe PMA output clamp mode */ + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, BIT(15) | BIT(31)); + + for (int i = 0; i < priv->num_lanes; i++) { + dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]); + if (priv->lanes[i] > 1) + bifurcation = true; + } + + /* Set bifurcation if needed, and it doesn't care RC/EP */ + if (bifurcation) { + dev_info(&phy->dev, "bifurcation enabled\n"); + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, + (0xf << 16) | RK3568_BIFURCATION_LANE_0_1); + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1, + BIT(15) | BIT(31)); + } else { + dev_info(&phy->dev, "bifurcation disabled\n"); + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, + (0xf << 16) & ~RK3568_BIFURCATION_LANE_0_1); + } + + reset_control_deassert(priv->p30phy); + + ret = regmap_read_poll_timeout(priv->phy_grf, + GRF_PCIE30PHY_STATUS0, + reg, SRAM_INIT_DONE(reg), + 0, 500); + if (ret) + dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n", + __func__, reg); + return ret; +} + +static const struct rockchip_p3phy_ops rk3568_ops = { + .phy_init = rockchip_p3phy_rk3568_init, +}; + +static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv) +{ + u32 reg = 0; + u8 mode = 0; + int ret; + + /* Deassert PCIe PMA output clamp mode */ + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24)); + + /* Set bifurcation if needed */ + for (int i = 0; i < priv->num_lanes; i++) { + if (!priv->lanes[i]) + mode |= (BIT(i) << 3); + + if (priv->lanes[i] > 1) + mode |= (BIT(i) >> 1); + } + + if (!mode) + reg = RK3588_LANE_AGGREGATION; + else { + if (mode & (BIT(0) | BIT(1))) + reg |= RK3588_BIFURCATION_LANE_0_1; + + if (mode & (BIT(2) | BIT(3))) + reg |= RK3588_BIFURCATION_LANE_2_3; + } + + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg); + + /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */ + if (!IS_ERR(priv->pipe_grf)) { + reg = (mode & (BIT(6) | BIT(7))) >> 6; + if (reg) + regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON, + (reg << 16) | reg); + } + + reset_control_deassert(priv->p30phy); + + ret = regmap_read_poll_timeout(priv->phy_grf, + RK3588_PCIE3PHY_GRF_PHY0_STATUS1, + reg, RK3588_SRAM_INIT_DONE(reg), + 0, 500); + ret |= regmap_read_poll_timeout(priv->phy_grf, + RK3588_PCIE3PHY_GRF_PHY1_STATUS1, + reg, RK3588_SRAM_INIT_DONE(reg), + 0, 500); + if (ret) + pr_err("%s: lock failed 0x%x, check input refclk and power supply\n", + __func__, reg); + return ret; +} + +static const struct rockchip_p3phy_ops rk3588_ops = { + .phy_init = rockchip_p3phy_rk3588_init, +}; + +static int rochchip_p3phy_init(struct phy *phy) +{ + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) { + pr_err("failed to enable PCIe bulk clks %d\n", ret); + return ret; + } + + reset_control_assert(priv->p30phy); + udelay(1); + + if (priv->ops->phy_init) { + ret = priv->ops->phy_init(priv); + if (ret) + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + } + + return ret; +} + +static int rochchip_p3phy_exit(struct phy *phy) +{ + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + reset_control_assert(priv->p30phy); + return 0; +} + +static const struct phy_ops rochchip_p3phy_ops = { + .init = rochchip_p3phy_init, + .exit = rochchip_p3phy_exit, + .set_mode = rockchip_p3phy_set_mode, + .owner = THIS_MODULE, +}; + +static int rockchip_p3phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct rockchip_p3phy_priv *priv; + struct device_node *np = dev->of_node; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->mmio = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->mmio)) { + ret = PTR_ERR(priv->mmio); + return ret; + } + + priv->ops = of_device_get_match_data(&pdev->dev); + if (!priv->ops) { + dev_err(&pdev->dev, "no of match data provided\n"); + return -EINVAL; + } + + priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf"); + if (IS_ERR(priv->phy_grf)) { + dev_err(dev, "failed to find rockchip,phy_grf regmap\n"); + return PTR_ERR(priv->phy_grf); + } + + priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, + "rockchip,pipe-grf"); + if (IS_ERR(priv->pipe_grf)) + dev_info(dev, "failed to find rockchip,pipe_grf regmap\n"); + + priv->num_lanes = of_property_read_variable_u8_array(dev->of_node, "lane-map", + priv->lanes, 2, + ARRAY_SIZE(priv->lanes)); + + /* if no lane-map assume aggregation */ + if (priv->num_lanes == -EINVAL) { + dev_dbg(dev, "no lane-map property found\n"); + priv->num_lanes = 1; + priv->lanes[0] = 1; + } else if (priv->num_lanes < 0) { + dev_err(dev, "failed to read lane-map property %d\n", priv->num_lanes); + return priv->num_lanes; + } + + priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops); + if (IS_ERR(priv->phy)) { + dev_err(dev, "failed to create combphy\n"); + return PTR_ERR(priv->phy); + } + + priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy"); + if (IS_ERR(priv->p30phy)) { + return dev_err_probe(dev, PTR_ERR(priv->p30phy), + "failed to get phy reset control\n"); + } + if (!priv->p30phy) + dev_info(dev, "no phy reset control specified\n"); + + priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); + if (priv->num_clks < 1) + return -ENODEV; + + dev_set_drvdata(dev, priv); + phy_set_drvdata(priv->phy, priv); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id rockchip_p3phy_of_match[] = { + { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops }, + { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops }, + { }, +}; +MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match); + +static struct platform_driver rockchip_p3phy_driver = { + .probe = rockchip_p3phy_probe, + .driver = { + .name = "rockchip-snps-pcie3-phy", + .of_match_table = rockchip_p3phy_of_match, + }, +}; +module_platform_driver(rockchip_p3phy_driver); +MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/phy/pcie.h b/include/linux/phy/pcie.h new file mode 100644 index 000000000000..93c997f520fe --- /dev/null +++ b/include/linux/phy/pcie.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ +#ifndef __PHY_PCIE_H +#define __PHY_PCIE_H + +#define PHY_MODE_PCIE_RC 20 +#define PHY_MODE_PCIE_EP 21 +#define PHY_MODE_PCIE_BIFURCATION 22 + +#endif -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 3/5] phy: rockchip: Support PCIe v3 @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy, Shawn Lin From: Shawn Lin <shawn.lin@rock-chips.com> RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566. It use a dedicated PCIe-phy. Add support for this. Initial support by Shawn Lin, modifications by Peter Geis and Frank Wunderlich. Add lane-map support for splitting pcie-lanes across controllers. The lane-map is an array where x=0 means lane is disabled and x > 0 means controller x is assigned to phy lane. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Suggested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - change dt-binding include - change reset to devm_reset_control_get_optional_exclusive exit on error and lower severity of message if unset - fix from peter: disable reg-write for phy-mode in rockchip_p3phy_probe - move bifurcation/lane-map support from PCIe to phy driver v2: - move dt-bindings header into separate patch - use BIT-macro - make constants better readable - use dev_err instead of pr_* - change dt-binding include due to renaming (phy-snps-pcie3.h => phy-rockchip-pcie3.h) - use exclusive variant of devm_reset_control_get{,_exclusive} - fix semicolon.cocci warnings reported by kernel test robot <lkp@intel.com> --- driver was taken from linux 5.10 based on in https://github.com/JeffyCN/mirrors which now has disappeared --- drivers/phy/rockchip/Kconfig | 9 + drivers/phy/rockchip/Makefile | 1 + .../phy/rockchip/phy-rockchip-snps-pcie3.c | 317 ++++++++++++++++++ include/linux/phy/pcie.h | 12 + 4 files changed, 339 insertions(+) create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c create mode 100644 include/linux/phy/pcie.h diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index 9022e395c056..94360fc96a6f 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -83,6 +83,15 @@ config PHY_ROCKCHIP_PCIE help Enable this to support the Rockchip PCIe PHY. +config PHY_ROCKCHIP_SNPS_PCIE3 + tristate "Rockchip Snps PCIe3 PHY Driver" + depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST + depends on HAS_IOMEM + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support the Rockchip snps PCIe3 PHY. + config PHY_ROCKCHIP_TYPEC tristate "Rockchip TYPEC PHY Driver" depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST) diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index a5041efb5b8f..7eab129230d1 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o +obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c new file mode 100644 index 000000000000..9d8fadff8a04 --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip PCIE3.0 phy driver + * + * Copyright (C) 2020 Rockchip Electronics Co., Ltd. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/phy/pcie.h> +#include <linux/phy/phy.h> +#include <linux/regmap.h> +#include <linux/reset.h> + +/* Register for RK3568 */ +#define GRF_PCIE30PHY_CON1 0x4 +#define GRF_PCIE30PHY_CON6 0x18 +#define GRF_PCIE30PHY_CON9 0x24 +#define GRF_PCIE30PHY_STATUS0 0x80 +#define SRAM_INIT_DONE(reg) (reg & BIT(14)) + +#define RK3568_BIFURCATION_LANE_0_1 BIT(0) + +/* Register for RK3588 */ +#define PHP_GRF_PCIESEL_CON 0x100 +#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0 +#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904 +#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04 +#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0)) + +#define RK3588_BIFURCATION_LANE_0_1 BIT(0) +#define RK3588_BIFURCATION_LANE_2_3 BIT(1) +#define RK3588_LANE_AGGREGATION BIT(2) + +struct rockchip_p3phy_ops; + +struct rockchip_p3phy_priv { + const struct rockchip_p3phy_ops *ops; + void __iomem *mmio; + /* mode: RC, EP */ + int mode; + /* pcie30_phymode: Aggregation, Bifurcation */ + int pcie30_phymode; + struct regmap *phy_grf; + struct regmap *pipe_grf; + struct reset_control *p30phy; + struct phy *phy; + struct clk_bulk_data *clks; + int num_clks; + int num_lanes; + u8 lanes[4]; +}; + +struct rockchip_p3phy_ops { + int (*phy_init)(struct rockchip_p3phy_priv *priv); +}; + +static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + + /* Actually We don't care EP/RC mode, but just record it */ + switch (submode) { + case PHY_MODE_PCIE_RC: + priv->mode = PHY_MODE_PCIE_RC; + break; + case PHY_MODE_PCIE_EP: + priv->mode = PHY_MODE_PCIE_EP; + break; + default: + dev_err(&phy->dev, "%s, invalid mode\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv) +{ + struct phy *phy = priv->phy; + bool bifurcation = false; + int ret; + u32 reg; + + /* Deassert PCIe PMA output clamp mode */ + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, BIT(15) | BIT(31)); + + for (int i = 0; i < priv->num_lanes; i++) { + dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]); + if (priv->lanes[i] > 1) + bifurcation = true; + } + + /* Set bifurcation if needed, and it doesn't care RC/EP */ + if (bifurcation) { + dev_info(&phy->dev, "bifurcation enabled\n"); + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, + (0xf << 16) | RK3568_BIFURCATION_LANE_0_1); + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1, + BIT(15) | BIT(31)); + } else { + dev_info(&phy->dev, "bifurcation disabled\n"); + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, + (0xf << 16) & ~RK3568_BIFURCATION_LANE_0_1); + } + + reset_control_deassert(priv->p30phy); + + ret = regmap_read_poll_timeout(priv->phy_grf, + GRF_PCIE30PHY_STATUS0, + reg, SRAM_INIT_DONE(reg), + 0, 500); + if (ret) + dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n", + __func__, reg); + return ret; +} + +static const struct rockchip_p3phy_ops rk3568_ops = { + .phy_init = rockchip_p3phy_rk3568_init, +}; + +static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv) +{ + u32 reg = 0; + u8 mode = 0; + int ret; + + /* Deassert PCIe PMA output clamp mode */ + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24)); + + /* Set bifurcation if needed */ + for (int i = 0; i < priv->num_lanes; i++) { + if (!priv->lanes[i]) + mode |= (BIT(i) << 3); + + if (priv->lanes[i] > 1) + mode |= (BIT(i) >> 1); + } + + if (!mode) + reg = RK3588_LANE_AGGREGATION; + else { + if (mode & (BIT(0) | BIT(1))) + reg |= RK3588_BIFURCATION_LANE_0_1; + + if (mode & (BIT(2) | BIT(3))) + reg |= RK3588_BIFURCATION_LANE_2_3; + } + + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg); + + /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */ + if (!IS_ERR(priv->pipe_grf)) { + reg = (mode & (BIT(6) | BIT(7))) >> 6; + if (reg) + regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON, + (reg << 16) | reg); + } + + reset_control_deassert(priv->p30phy); + + ret = regmap_read_poll_timeout(priv->phy_grf, + RK3588_PCIE3PHY_GRF_PHY0_STATUS1, + reg, RK3588_SRAM_INIT_DONE(reg), + 0, 500); + ret |= regmap_read_poll_timeout(priv->phy_grf, + RK3588_PCIE3PHY_GRF_PHY1_STATUS1, + reg, RK3588_SRAM_INIT_DONE(reg), + 0, 500); + if (ret) + pr_err("%s: lock failed 0x%x, check input refclk and power supply\n", + __func__, reg); + return ret; +} + +static const struct rockchip_p3phy_ops rk3588_ops = { + .phy_init = rockchip_p3phy_rk3588_init, +}; + +static int rochchip_p3phy_init(struct phy *phy) +{ + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) { + pr_err("failed to enable PCIe bulk clks %d\n", ret); + return ret; + } + + reset_control_assert(priv->p30phy); + udelay(1); + + if (priv->ops->phy_init) { + ret = priv->ops->phy_init(priv); + if (ret) + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + } + + return ret; +} + +static int rochchip_p3phy_exit(struct phy *phy) +{ + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + reset_control_assert(priv->p30phy); + return 0; +} + +static const struct phy_ops rochchip_p3phy_ops = { + .init = rochchip_p3phy_init, + .exit = rochchip_p3phy_exit, + .set_mode = rockchip_p3phy_set_mode, + .owner = THIS_MODULE, +}; + +static int rockchip_p3phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct rockchip_p3phy_priv *priv; + struct device_node *np = dev->of_node; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->mmio = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->mmio)) { + ret = PTR_ERR(priv->mmio); + return ret; + } + + priv->ops = of_device_get_match_data(&pdev->dev); + if (!priv->ops) { + dev_err(&pdev->dev, "no of match data provided\n"); + return -EINVAL; + } + + priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf"); + if (IS_ERR(priv->phy_grf)) { + dev_err(dev, "failed to find rockchip,phy_grf regmap\n"); + return PTR_ERR(priv->phy_grf); + } + + priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, + "rockchip,pipe-grf"); + if (IS_ERR(priv->pipe_grf)) + dev_info(dev, "failed to find rockchip,pipe_grf regmap\n"); + + priv->num_lanes = of_property_read_variable_u8_array(dev->of_node, "lane-map", + priv->lanes, 2, + ARRAY_SIZE(priv->lanes)); + + /* if no lane-map assume aggregation */ + if (priv->num_lanes == -EINVAL) { + dev_dbg(dev, "no lane-map property found\n"); + priv->num_lanes = 1; + priv->lanes[0] = 1; + } else if (priv->num_lanes < 0) { + dev_err(dev, "failed to read lane-map property %d\n", priv->num_lanes); + return priv->num_lanes; + } + + priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops); + if (IS_ERR(priv->phy)) { + dev_err(dev, "failed to create combphy\n"); + return PTR_ERR(priv->phy); + } + + priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy"); + if (IS_ERR(priv->p30phy)) { + return dev_err_probe(dev, PTR_ERR(priv->p30phy), + "failed to get phy reset control\n"); + } + if (!priv->p30phy) + dev_info(dev, "no phy reset control specified\n"); + + priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); + if (priv->num_clks < 1) + return -ENODEV; + + dev_set_drvdata(dev, priv); + phy_set_drvdata(priv->phy, priv); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id rockchip_p3phy_of_match[] = { + { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops }, + { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops }, + { }, +}; +MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match); + +static struct platform_driver rockchip_p3phy_driver = { + .probe = rockchip_p3phy_probe, + .driver = { + .name = "rockchip-snps-pcie3-phy", + .of_match_table = rockchip_p3phy_of_match, + }, +}; +module_platform_driver(rockchip_p3phy_driver); +MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/phy/pcie.h b/include/linux/phy/pcie.h new file mode 100644 index 000000000000..93c997f520fe --- /dev/null +++ b/include/linux/phy/pcie.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ +#ifndef __PHY_PCIE_H +#define __PHY_PCIE_H + +#define PHY_MODE_PCIE_RC 20 +#define PHY_MODE_PCIE_EP 21 +#define PHY_MODE_PCIE_BIFURCATION 22 + +#endif -- 2.25.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 3/5] phy: rockchip: Support PCIe v3 @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy, Shawn Lin From: Shawn Lin <shawn.lin@rock-chips.com> RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566. It use a dedicated PCIe-phy. Add support for this. Initial support by Shawn Lin, modifications by Peter Geis and Frank Wunderlich. Add lane-map support for splitting pcie-lanes across controllers. The lane-map is an array where x=0 means lane is disabled and x > 0 means controller x is assigned to phy lane. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Suggested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - change dt-binding include - change reset to devm_reset_control_get_optional_exclusive exit on error and lower severity of message if unset - fix from peter: disable reg-write for phy-mode in rockchip_p3phy_probe - move bifurcation/lane-map support from PCIe to phy driver v2: - move dt-bindings header into separate patch - use BIT-macro - make constants better readable - use dev_err instead of pr_* - change dt-binding include due to renaming (phy-snps-pcie3.h => phy-rockchip-pcie3.h) - use exclusive variant of devm_reset_control_get{,_exclusive} - fix semicolon.cocci warnings reported by kernel test robot <lkp@intel.com> --- driver was taken from linux 5.10 based on in https://github.com/JeffyCN/mirrors which now has disappeared --- drivers/phy/rockchip/Kconfig | 9 + drivers/phy/rockchip/Makefile | 1 + .../phy/rockchip/phy-rockchip-snps-pcie3.c | 317 ++++++++++++++++++ include/linux/phy/pcie.h | 12 + 4 files changed, 339 insertions(+) create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c create mode 100644 include/linux/phy/pcie.h diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index 9022e395c056..94360fc96a6f 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -83,6 +83,15 @@ config PHY_ROCKCHIP_PCIE help Enable this to support the Rockchip PCIe PHY. +config PHY_ROCKCHIP_SNPS_PCIE3 + tristate "Rockchip Snps PCIe3 PHY Driver" + depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST + depends on HAS_IOMEM + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support the Rockchip snps PCIe3 PHY. + config PHY_ROCKCHIP_TYPEC tristate "Rockchip TYPEC PHY Driver" depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST) diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index a5041efb5b8f..7eab129230d1 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o +obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c new file mode 100644 index 000000000000..9d8fadff8a04 --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip PCIE3.0 phy driver + * + * Copyright (C) 2020 Rockchip Electronics Co., Ltd. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/phy/pcie.h> +#include <linux/phy/phy.h> +#include <linux/regmap.h> +#include <linux/reset.h> + +/* Register for RK3568 */ +#define GRF_PCIE30PHY_CON1 0x4 +#define GRF_PCIE30PHY_CON6 0x18 +#define GRF_PCIE30PHY_CON9 0x24 +#define GRF_PCIE30PHY_STATUS0 0x80 +#define SRAM_INIT_DONE(reg) (reg & BIT(14)) + +#define RK3568_BIFURCATION_LANE_0_1 BIT(0) + +/* Register for RK3588 */ +#define PHP_GRF_PCIESEL_CON 0x100 +#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0 +#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904 +#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04 +#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0)) + +#define RK3588_BIFURCATION_LANE_0_1 BIT(0) +#define RK3588_BIFURCATION_LANE_2_3 BIT(1) +#define RK3588_LANE_AGGREGATION BIT(2) + +struct rockchip_p3phy_ops; + +struct rockchip_p3phy_priv { + const struct rockchip_p3phy_ops *ops; + void __iomem *mmio; + /* mode: RC, EP */ + int mode; + /* pcie30_phymode: Aggregation, Bifurcation */ + int pcie30_phymode; + struct regmap *phy_grf; + struct regmap *pipe_grf; + struct reset_control *p30phy; + struct phy *phy; + struct clk_bulk_data *clks; + int num_clks; + int num_lanes; + u8 lanes[4]; +}; + +struct rockchip_p3phy_ops { + int (*phy_init)(struct rockchip_p3phy_priv *priv); +}; + +static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + + /* Actually We don't care EP/RC mode, but just record it */ + switch (submode) { + case PHY_MODE_PCIE_RC: + priv->mode = PHY_MODE_PCIE_RC; + break; + case PHY_MODE_PCIE_EP: + priv->mode = PHY_MODE_PCIE_EP; + break; + default: + dev_err(&phy->dev, "%s, invalid mode\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv) +{ + struct phy *phy = priv->phy; + bool bifurcation = false; + int ret; + u32 reg; + + /* Deassert PCIe PMA output clamp mode */ + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, BIT(15) | BIT(31)); + + for (int i = 0; i < priv->num_lanes; i++) { + dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]); + if (priv->lanes[i] > 1) + bifurcation = true; + } + + /* Set bifurcation if needed, and it doesn't care RC/EP */ + if (bifurcation) { + dev_info(&phy->dev, "bifurcation enabled\n"); + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, + (0xf << 16) | RK3568_BIFURCATION_LANE_0_1); + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1, + BIT(15) | BIT(31)); + } else { + dev_info(&phy->dev, "bifurcation disabled\n"); + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, + (0xf << 16) & ~RK3568_BIFURCATION_LANE_0_1); + } + + reset_control_deassert(priv->p30phy); + + ret = regmap_read_poll_timeout(priv->phy_grf, + GRF_PCIE30PHY_STATUS0, + reg, SRAM_INIT_DONE(reg), + 0, 500); + if (ret) + dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n", + __func__, reg); + return ret; +} + +static const struct rockchip_p3phy_ops rk3568_ops = { + .phy_init = rockchip_p3phy_rk3568_init, +}; + +static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv) +{ + u32 reg = 0; + u8 mode = 0; + int ret; + + /* Deassert PCIe PMA output clamp mode */ + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24)); + + /* Set bifurcation if needed */ + for (int i = 0; i < priv->num_lanes; i++) { + if (!priv->lanes[i]) + mode |= (BIT(i) << 3); + + if (priv->lanes[i] > 1) + mode |= (BIT(i) >> 1); + } + + if (!mode) + reg = RK3588_LANE_AGGREGATION; + else { + if (mode & (BIT(0) | BIT(1))) + reg |= RK3588_BIFURCATION_LANE_0_1; + + if (mode & (BIT(2) | BIT(3))) + reg |= RK3588_BIFURCATION_LANE_2_3; + } + + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg); + + /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */ + if (!IS_ERR(priv->pipe_grf)) { + reg = (mode & (BIT(6) | BIT(7))) >> 6; + if (reg) + regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON, + (reg << 16) | reg); + } + + reset_control_deassert(priv->p30phy); + + ret = regmap_read_poll_timeout(priv->phy_grf, + RK3588_PCIE3PHY_GRF_PHY0_STATUS1, + reg, RK3588_SRAM_INIT_DONE(reg), + 0, 500); + ret |= regmap_read_poll_timeout(priv->phy_grf, + RK3588_PCIE3PHY_GRF_PHY1_STATUS1, + reg, RK3588_SRAM_INIT_DONE(reg), + 0, 500); + if (ret) + pr_err("%s: lock failed 0x%x, check input refclk and power supply\n", + __func__, reg); + return ret; +} + +static const struct rockchip_p3phy_ops rk3588_ops = { + .phy_init = rockchip_p3phy_rk3588_init, +}; + +static int rochchip_p3phy_init(struct phy *phy) +{ + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) { + pr_err("failed to enable PCIe bulk clks %d\n", ret); + return ret; + } + + reset_control_assert(priv->p30phy); + udelay(1); + + if (priv->ops->phy_init) { + ret = priv->ops->phy_init(priv); + if (ret) + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + } + + return ret; +} + +static int rochchip_p3phy_exit(struct phy *phy) +{ + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); + + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + reset_control_assert(priv->p30phy); + return 0; +} + +static const struct phy_ops rochchip_p3phy_ops = { + .init = rochchip_p3phy_init, + .exit = rochchip_p3phy_exit, + .set_mode = rockchip_p3phy_set_mode, + .owner = THIS_MODULE, +}; + +static int rockchip_p3phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct rockchip_p3phy_priv *priv; + struct device_node *np = dev->of_node; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->mmio = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->mmio)) { + ret = PTR_ERR(priv->mmio); + return ret; + } + + priv->ops = of_device_get_match_data(&pdev->dev); + if (!priv->ops) { + dev_err(&pdev->dev, "no of match data provided\n"); + return -EINVAL; + } + + priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf"); + if (IS_ERR(priv->phy_grf)) { + dev_err(dev, "failed to find rockchip,phy_grf regmap\n"); + return PTR_ERR(priv->phy_grf); + } + + priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, + "rockchip,pipe-grf"); + if (IS_ERR(priv->pipe_grf)) + dev_info(dev, "failed to find rockchip,pipe_grf regmap\n"); + + priv->num_lanes = of_property_read_variable_u8_array(dev->of_node, "lane-map", + priv->lanes, 2, + ARRAY_SIZE(priv->lanes)); + + /* if no lane-map assume aggregation */ + if (priv->num_lanes == -EINVAL) { + dev_dbg(dev, "no lane-map property found\n"); + priv->num_lanes = 1; + priv->lanes[0] = 1; + } else if (priv->num_lanes < 0) { + dev_err(dev, "failed to read lane-map property %d\n", priv->num_lanes); + return priv->num_lanes; + } + + priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops); + if (IS_ERR(priv->phy)) { + dev_err(dev, "failed to create combphy\n"); + return PTR_ERR(priv->phy); + } + + priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy"); + if (IS_ERR(priv->p30phy)) { + return dev_err_probe(dev, PTR_ERR(priv->p30phy), + "failed to get phy reset control\n"); + } + if (!priv->p30phy) + dev_info(dev, "no phy reset control specified\n"); + + priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); + if (priv->num_clks < 1) + return -ENODEV; + + dev_set_drvdata(dev, priv); + phy_set_drvdata(priv->phy, priv); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id rockchip_p3phy_of_match[] = { + { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops }, + { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops }, + { }, +}; +MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match); + +static struct platform_driver rockchip_p3phy_driver = { + .probe = rockchip_p3phy_probe, + .driver = { + .name = "rockchip-snps-pcie3-phy", + .of_match_table = rockchip_p3phy_of_match, + }, +}; +module_platform_driver(rockchip_p3phy_driver); +MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/phy/pcie.h b/include/linux/phy/pcie.h new file mode 100644 index 000000000000..93c997f520fe --- /dev/null +++ b/include/linux/phy/pcie.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ +#ifndef __PHY_PCIE_H +#define __PHY_PCIE_H + +#define PHY_MODE_PCIE_RC 20 +#define PHY_MODE_PCIE_EP 21 +#define PHY_MODE_PCIE_BIFURCATION 22 + +#endif -- 2.25.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 4/5] arm64: dts: rockchip: rk3568: Add PCIe v3 nodes 2022-05-14 11:59 ` Frank Wunderlich (?) (?) @ 2022-05-14 11:59 ` Frank Wunderlich -1 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> Add nodes to rk356x devicetree to support PCIe v3. Co-developed-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - fix from Peter: change bus-range and msi-map, msi-map needs to start from 0x0 v2: - change to compatible with soc-part - change rockchip,bifurcation to vendor unspecific bifurcation --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 5eafddf62edc..6dbe73c9cddf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -42,6 +42,128 @@ qos_sata0: qos@fe190200 { reg = <0x0 0xfe190200 0x0 0x20>; }; + pcie30_phy_grf: syscon@fdcb8000 { + compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfdcb8000 0x0 0x10000>; + }; + + pcie30phy: phy@fe8c0000 { + compatible = "rockchip,rk3568-pcie3-phy"; + reg = <0x0 0xfe8c0000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, + <&cru PCLK_PCIE30PHY>; + clock-names = "refclk_m", "refclk_n", "pclk"; + resets = <&cru SRST_PCIE30PHY>; + reset-names = "phy"; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; + + pcie3x1: pcie@fe270000 { + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, + <&cru CLK_PCIE30X1_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, + <0 0 0 2 &pcie3x1_intc 1>, + <0 0 0 3 &pcie3x1_intc 2>, + <0 0 0 4 &pcie3x1_intc 3>; + linux,pci-domain = <1>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; + msi-map = <0x0 &gic 0x1000 0x1000>; + num-lanes = <1>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + reg = <0x3 0xc0400000 0x0 0x00400000>, + <0x0 0xfe270000 0x0 0x00010000>, + <0x3 0x40000000 0x0 0x01000000>; + ranges = <0x01000000 0x0 0x01000000 0x3 0x41000000 0x0 0x00100000>, + <0x02000000 0x0 0x02000000 0x3 0x41100000 0x0 0x3ef00000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE30X1_POWERUP>; + reset-names = "pipe"; + /* bifurcation; lane1 when using 1+1 */ + status = "disabled"; + + pcie3x1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pcie3x2: pcie@fe280000 { + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <2>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; + msi-map = <0x0 &gic 0x2000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + reg = <0x3 0xc0800000 0x0 0x00400000>, + <0x0 0xfe280000 0x0 0x00010000>, + <0x3 0x80000000 0x0 0x01000000>; + ranges = <0x01000000 0x0 0x01000000 0x3 0x81000000 0x0 0x00100000>, + <0x02000000 0x0 0x02000000 0x3 0x81100000 0x0 0x3ef00000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE30X2_POWERUP>; + reset-names = "pipe"; + /* bifurcation; lane0 when using 1+1 */ + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>; + }; + }; + gmac0: ethernet@fe2a0000 { compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe2a0000 0x0 0x10000>; -- 2.25.1 ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 4/5] arm64: dts: rockchip: rk3568: Add PCIe v3 nodes @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> Add nodes to rk356x devicetree to support PCIe v3. Co-developed-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - fix from Peter: change bus-range and msi-map, msi-map needs to start from 0x0 v2: - change to compatible with soc-part - change rockchip,bifurcation to vendor unspecific bifurcation --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 5eafddf62edc..6dbe73c9cddf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -42,6 +42,128 @@ qos_sata0: qos@fe190200 { reg = <0x0 0xfe190200 0x0 0x20>; }; + pcie30_phy_grf: syscon@fdcb8000 { + compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfdcb8000 0x0 0x10000>; + }; + + pcie30phy: phy@fe8c0000 { + compatible = "rockchip,rk3568-pcie3-phy"; + reg = <0x0 0xfe8c0000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, + <&cru PCLK_PCIE30PHY>; + clock-names = "refclk_m", "refclk_n", "pclk"; + resets = <&cru SRST_PCIE30PHY>; + reset-names = "phy"; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; + + pcie3x1: pcie@fe270000 { + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, + <&cru CLK_PCIE30X1_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, + <0 0 0 2 &pcie3x1_intc 1>, + <0 0 0 3 &pcie3x1_intc 2>, + <0 0 0 4 &pcie3x1_intc 3>; + linux,pci-domain = <1>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; + msi-map = <0x0 &gic 0x1000 0x1000>; + num-lanes = <1>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + reg = <0x3 0xc0400000 0x0 0x00400000>, + <0x0 0xfe270000 0x0 0x00010000>, + <0x3 0x40000000 0x0 0x01000000>; + ranges = <0x01000000 0x0 0x01000000 0x3 0x41000000 0x0 0x00100000>, + <0x02000000 0x0 0x02000000 0x3 0x41100000 0x0 0x3ef00000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE30X1_POWERUP>; + reset-names = "pipe"; + /* bifurcation; lane1 when using 1+1 */ + status = "disabled"; + + pcie3x1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pcie3x2: pcie@fe280000 { + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <2>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; + msi-map = <0x0 &gic 0x2000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + reg = <0x3 0xc0800000 0x0 0x00400000>, + <0x0 0xfe280000 0x0 0x00010000>, + <0x3 0x80000000 0x0 0x01000000>; + ranges = <0x01000000 0x0 0x01000000 0x3 0x81000000 0x0 0x00100000>, + <0x02000000 0x0 0x02000000 0x3 0x81100000 0x0 0x3ef00000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE30X2_POWERUP>; + reset-names = "pipe"; + /* bifurcation; lane0 when using 1+1 */ + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>; + }; + }; + gmac0: ethernet@fe2a0000 { compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe2a0000 0x0 0x10000>; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 4/5] arm64: dts: rockchip: rk3568: Add PCIe v3 nodes @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> Add nodes to rk356x devicetree to support PCIe v3. Co-developed-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - fix from Peter: change bus-range and msi-map, msi-map needs to start from 0x0 v2: - change to compatible with soc-part - change rockchip,bifurcation to vendor unspecific bifurcation --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 5eafddf62edc..6dbe73c9cddf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -42,6 +42,128 @@ qos_sata0: qos@fe190200 { reg = <0x0 0xfe190200 0x0 0x20>; }; + pcie30_phy_grf: syscon@fdcb8000 { + compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfdcb8000 0x0 0x10000>; + }; + + pcie30phy: phy@fe8c0000 { + compatible = "rockchip,rk3568-pcie3-phy"; + reg = <0x0 0xfe8c0000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, + <&cru PCLK_PCIE30PHY>; + clock-names = "refclk_m", "refclk_n", "pclk"; + resets = <&cru SRST_PCIE30PHY>; + reset-names = "phy"; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; + + pcie3x1: pcie@fe270000 { + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, + <&cru CLK_PCIE30X1_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, + <0 0 0 2 &pcie3x1_intc 1>, + <0 0 0 3 &pcie3x1_intc 2>, + <0 0 0 4 &pcie3x1_intc 3>; + linux,pci-domain = <1>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; + msi-map = <0x0 &gic 0x1000 0x1000>; + num-lanes = <1>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + reg = <0x3 0xc0400000 0x0 0x00400000>, + <0x0 0xfe270000 0x0 0x00010000>, + <0x3 0x40000000 0x0 0x01000000>; + ranges = <0x01000000 0x0 0x01000000 0x3 0x41000000 0x0 0x00100000>, + <0x02000000 0x0 0x02000000 0x3 0x41100000 0x0 0x3ef00000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE30X1_POWERUP>; + reset-names = "pipe"; + /* bifurcation; lane1 when using 1+1 */ + status = "disabled"; + + pcie3x1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pcie3x2: pcie@fe280000 { + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <2>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; + msi-map = <0x0 &gic 0x2000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + reg = <0x3 0xc0800000 0x0 0x00400000>, + <0x0 0xfe280000 0x0 0x00010000>, + <0x3 0x80000000 0x0 0x01000000>; + ranges = <0x01000000 0x0 0x01000000 0x3 0x81000000 0x0 0x00100000>, + <0x02000000 0x0 0x02000000 0x3 0x81100000 0x0 0x3ef00000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE30X2_POWERUP>; + reset-names = "pipe"; + /* bifurcation; lane0 when using 1+1 */ + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>; + }; + }; + gmac0: ethernet@fe2a0000 { compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe2a0000 0x0 0x10000>; -- 2.25.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 4/5] arm64: dts: rockchip: rk3568: Add PCIe v3 nodes @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> Add nodes to rk356x devicetree to support PCIe v3. Co-developed-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - fix from Peter: change bus-range and msi-map, msi-map needs to start from 0x0 v2: - change to compatible with soc-part - change rockchip,bifurcation to vendor unspecific bifurcation --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 5eafddf62edc..6dbe73c9cddf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -42,6 +42,128 @@ qos_sata0: qos@fe190200 { reg = <0x0 0xfe190200 0x0 0x20>; }; + pcie30_phy_grf: syscon@fdcb8000 { + compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfdcb8000 0x0 0x10000>; + }; + + pcie30phy: phy@fe8c0000 { + compatible = "rockchip,rk3568-pcie3-phy"; + reg = <0x0 0xfe8c0000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, + <&cru PCLK_PCIE30PHY>; + clock-names = "refclk_m", "refclk_n", "pclk"; + resets = <&cru SRST_PCIE30PHY>; + reset-names = "phy"; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; + + pcie3x1: pcie@fe270000 { + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, + <&cru CLK_PCIE30X1_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, + <0 0 0 2 &pcie3x1_intc 1>, + <0 0 0 3 &pcie3x1_intc 2>, + <0 0 0 4 &pcie3x1_intc 3>; + linux,pci-domain = <1>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; + msi-map = <0x0 &gic 0x1000 0x1000>; + num-lanes = <1>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + reg = <0x3 0xc0400000 0x0 0x00400000>, + <0x0 0xfe270000 0x0 0x00010000>, + <0x3 0x40000000 0x0 0x01000000>; + ranges = <0x01000000 0x0 0x01000000 0x3 0x41000000 0x0 0x00100000>, + <0x02000000 0x0 0x02000000 0x3 0x41100000 0x0 0x3ef00000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE30X1_POWERUP>; + reset-names = "pipe"; + /* bifurcation; lane1 when using 1+1 */ + status = "disabled"; + + pcie3x1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pcie3x2: pcie@fe280000 { + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <2>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <3>; + msi-map = <0x0 &gic 0x2000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + reg = <0x3 0xc0800000 0x0 0x00400000>, + <0x0 0xfe280000 0x0 0x00010000>, + <0x3 0x80000000 0x0 0x01000000>; + ranges = <0x01000000 0x0 0x01000000 0x3 0x81000000 0x0 0x00100000>, + <0x02000000 0x0 0x02000000 0x3 0x81100000 0x0 0x3ef00000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE30X2_POWERUP>; + reset-names = "pipe"; + /* bifurcation; lane0 when using 1+1 */ + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>; + }; + }; + gmac0: ethernet@fe2a0000 { compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe2a0000 0x0 0x10000>; -- 2.25.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 5/5] arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro 2022-05-14 11:59 ` Frank Wunderlich (?) (?) @ 2022-05-14 11:59 ` Frank Wunderlich -1 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> Add Nodes to Bananapi-R2-Pro board to support PCIe v3 and set PCIe related regulators to always on. Suggested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - squash lane-map over bifurcation property - add comment which slot is M2 and which one if mPCIe - fixes from Peter: - drop regulator-always-on/regulator-boot-on from regulators - increase startup-delay-us for regulators - set phy-mode on PCIe3-phy - add num-lanes to PCIe overrides - add usb node for to PCIe/m2 - move lane-map from PCIe controller to PCIe-phy v2: - underscores in nodenames - rockchip,bifurcation to vendor unspecific bifurcation - fix trailing space --- .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts index 2700fb18a3bc..8b3b774a9dac 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -74,6 +74,62 @@ vcc5v0_sys: vcc5v0-sys { vin-supply = <&dc_12v>; }; + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* pi6c pcie clock generator feeds both ports */ + vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ + vcc3v3_minipcie: vcc3v3-minipcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_minipcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc3v3_pi6c_05>; + }; + + /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ + vcc3v3_ngff: vcc3v3-ngff-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_ngff"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc3v3_pi6c_05>; + }; + vbus: vbus { compatible = "regulator-fixed"; regulator-name = "vbus"; @@ -411,6 +467,27 @@ rgmii_phy1: ethernet-phy@0 { }; }; +&pcie30phy { + lane-map = /bits/ 8 <1 2>; + status = "okay"; +}; + +&pcie3x1 { + /* M.2 slot */ + num-lanes = <1>; + reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_ngff>; + status = "okay"; +}; + +&pcie3x2 { + /* mPCIe slot */ + num-lanes = <1>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + &pinctrl { leds { blue_led_pin: blue-led-pin { @@ -597,3 +674,16 @@ &usb2phy0_otg { phy-supply = <&vcc5v0_usb_otg>; status = "okay"; }; + +&usb2phy1 { + /* USB for PCIe/M2 */ + status = "okay"; +}; + +&usb2phy1_host { + status = "okay"; +}; + +&usb2phy1_otg { + status = "okay"; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 5/5] arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> Add Nodes to Bananapi-R2-Pro board to support PCIe v3 and set PCIe related regulators to always on. Suggested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - squash lane-map over bifurcation property - add comment which slot is M2 and which one if mPCIe - fixes from Peter: - drop regulator-always-on/regulator-boot-on from regulators - increase startup-delay-us for regulators - set phy-mode on PCIe3-phy - add num-lanes to PCIe overrides - add usb node for to PCIe/m2 - move lane-map from PCIe controller to PCIe-phy v2: - underscores in nodenames - rockchip,bifurcation to vendor unspecific bifurcation - fix trailing space --- .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts index 2700fb18a3bc..8b3b774a9dac 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -74,6 +74,62 @@ vcc5v0_sys: vcc5v0-sys { vin-supply = <&dc_12v>; }; + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* pi6c pcie clock generator feeds both ports */ + vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ + vcc3v3_minipcie: vcc3v3-minipcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_minipcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc3v3_pi6c_05>; + }; + + /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ + vcc3v3_ngff: vcc3v3-ngff-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_ngff"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc3v3_pi6c_05>; + }; + vbus: vbus { compatible = "regulator-fixed"; regulator-name = "vbus"; @@ -411,6 +467,27 @@ rgmii_phy1: ethernet-phy@0 { }; }; +&pcie30phy { + lane-map = /bits/ 8 <1 2>; + status = "okay"; +}; + +&pcie3x1 { + /* M.2 slot */ + num-lanes = <1>; + reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_ngff>; + status = "okay"; +}; + +&pcie3x2 { + /* mPCIe slot */ + num-lanes = <1>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + &pinctrl { leds { blue_led_pin: blue-led-pin { @@ -597,3 +674,16 @@ &usb2phy0_otg { phy-supply = <&vcc5v0_usb_otg>; status = "okay"; }; + +&usb2phy1 { + /* USB for PCIe/M2 */ + status = "okay"; +}; + +&usb2phy1_host { + status = "okay"; +}; + +&usb2phy1_otg { + status = "okay"; +}; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 5/5] arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> Add Nodes to Bananapi-R2-Pro board to support PCIe v3 and set PCIe related regulators to always on. Suggested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - squash lane-map over bifurcation property - add comment which slot is M2 and which one if mPCIe - fixes from Peter: - drop regulator-always-on/regulator-boot-on from regulators - increase startup-delay-us for regulators - set phy-mode on PCIe3-phy - add num-lanes to PCIe overrides - add usb node for to PCIe/m2 - move lane-map from PCIe controller to PCIe-phy v2: - underscores in nodenames - rockchip,bifurcation to vendor unspecific bifurcation - fix trailing space --- .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts index 2700fb18a3bc..8b3b774a9dac 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -74,6 +74,62 @@ vcc5v0_sys: vcc5v0-sys { vin-supply = <&dc_12v>; }; + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* pi6c pcie clock generator feeds both ports */ + vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ + vcc3v3_minipcie: vcc3v3-minipcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_minipcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc3v3_pi6c_05>; + }; + + /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ + vcc3v3_ngff: vcc3v3-ngff-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_ngff"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc3v3_pi6c_05>; + }; + vbus: vbus { compatible = "regulator-fixed"; regulator-name = "vbus"; @@ -411,6 +467,27 @@ rgmii_phy1: ethernet-phy@0 { }; }; +&pcie30phy { + lane-map = /bits/ 8 <1 2>; + status = "okay"; +}; + +&pcie3x1 { + /* M.2 slot */ + num-lanes = <1>; + reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_ngff>; + status = "okay"; +}; + +&pcie3x2 { + /* mPCIe slot */ + num-lanes = <1>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + &pinctrl { leds { blue_led_pin: blue-led-pin { @@ -597,3 +674,16 @@ &usb2phy0_otg { phy-supply = <&vcc5v0_usb_otg>; status = "okay"; }; + +&usb2phy1 { + /* USB for PCIe/M2 */ + status = "okay"; +}; + +&usb2phy1_host { + status = "okay"; +}; + +&usb2phy1_otg { + status = "okay"; +}; -- 2.25.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply related [flat|nested] 60+ messages in thread
* [RFC v3 5/5] arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro @ 2022-05-14 11:59 ` Frank Wunderlich 0 siblings, 0 replies; 60+ messages in thread From: Frank Wunderlich @ 2022-05-14 11:59 UTC (permalink / raw) To: linux-rockchip Cc: Frank Wunderlich, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Kishon Vijay Abraham I, Vinod Koul, Lorenzo Pieralisi, Krzysztof Wilczyński, Philipp Zabel, Johan Jonker, Peter Geis, Michael Riesch, linux-pci, devicetree, linux-arm-kernel, linux-kernel, linux-phy From: Frank Wunderlich <frank-w@public-files.de> Add Nodes to Bananapi-R2-Pro board to support PCIe v3 and set PCIe related regulators to always on. Suggested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> --- v3: - squash lane-map over bifurcation property - add comment which slot is M2 and which one if mPCIe - fixes from Peter: - drop regulator-always-on/regulator-boot-on from regulators - increase startup-delay-us for regulators - set phy-mode on PCIe3-phy - add num-lanes to PCIe overrides - add usb node for to PCIe/m2 - move lane-map from PCIe controller to PCIe-phy v2: - underscores in nodenames - rockchip,bifurcation to vendor unspecific bifurcation - fix trailing space --- .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts index 2700fb18a3bc..8b3b774a9dac 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -74,6 +74,62 @@ vcc5v0_sys: vcc5v0-sys { vin-supply = <&dc_12v>; }; + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* pi6c pcie clock generator feeds both ports */ + vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ + vcc3v3_minipcie: vcc3v3-minipcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_minipcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc3v3_pi6c_05>; + }; + + /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ + vcc3v3_ngff: vcc3v3-ngff-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_ngff"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc3v3_pi6c_05>; + }; + vbus: vbus { compatible = "regulator-fixed"; regulator-name = "vbus"; @@ -411,6 +467,27 @@ rgmii_phy1: ethernet-phy@0 { }; }; +&pcie30phy { + lane-map = /bits/ 8 <1 2>; + status = "okay"; +}; + +&pcie3x1 { + /* M.2 slot */ + num-lanes = <1>; + reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_ngff>; + status = "okay"; +}; + +&pcie3x2 { + /* mPCIe slot */ + num-lanes = <1>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + &pinctrl { leds { blue_led_pin: blue-led-pin { @@ -597,3 +674,16 @@ &usb2phy0_otg { phy-supply = <&vcc5v0_usb_otg>; status = "okay"; }; + +&usb2phy1 { + /* USB for PCIe/M2 */ + status = "okay"; +}; + +&usb2phy1_host { + status = "okay"; +}; + +&usb2phy1_otg { + status = "okay"; +}; -- 2.25.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 60+ messages in thread
end of thread, other threads:[~2022-06-02 13:54 UTC | newest] Thread overview: 60+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-05-14 11:59 [RFC v3 0/5] RK3568 PCIe V3 support Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 11:59 ` [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 20:44 ` Krzysztof Kozlowski 2022-05-14 20:44 ` Krzysztof Kozlowski 2022-05-14 20:44 ` Krzysztof Kozlowski 2022-05-14 20:44 ` Krzysztof Kozlowski 2022-05-14 23:14 ` Rob Herring 2022-05-14 23:14 ` Rob Herring 2022-05-14 23:14 ` Rob Herring 2022-05-14 23:14 ` Rob Herring 2022-05-15 11:49 ` Aw: " Frank Wunderlich 2022-05-15 11:49 ` Frank Wunderlich 2022-05-15 11:49 ` Frank Wunderlich 2022-05-15 11:49 ` Frank Wunderlich 2022-05-16 17:35 ` Rob Herring 2022-05-16 17:35 ` Rob Herring 2022-05-16 17:35 ` Rob Herring 2022-05-16 17:35 ` Rob Herring 2022-05-16 19:21 ` Frank Wunderlich 2022-05-16 19:21 ` Frank Wunderlich 2022-05-16 19:21 ` Frank Wunderlich 2022-05-16 19:21 ` Frank Wunderlich 2022-05-18 15:55 ` Rob Herring 2022-05-18 15:55 ` Rob Herring 2022-05-18 15:55 ` Rob Herring 2022-05-18 15:55 ` Rob Herring 2022-05-20 11:50 ` Aw: " Frank Wunderlich 2022-05-20 11:50 ` Frank Wunderlich 2022-05-20 11:50 ` Frank Wunderlich 2022-05-20 11:50 ` Frank Wunderlich 2022-06-02 13:47 ` Frank Wunderlich 2022-06-02 13:47 ` Frank Wunderlich 2022-06-02 13:47 ` Frank Wunderlich 2022-06-02 13:47 ` Frank Wunderlich 2022-05-14 11:59 ` [RFC v3 2/5] dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 20:43 ` Krzysztof Kozlowski 2022-05-14 20:43 ` Krzysztof Kozlowski 2022-05-14 20:43 ` Krzysztof Kozlowski 2022-05-14 20:43 ` Krzysztof Kozlowski 2022-05-14 11:59 ` [RFC v3 3/5] phy: rockchip: Support PCIe v3 Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 11:59 ` [RFC v3 4/5] arm64: dts: rockchip: rk3568: Add PCIe v3 nodes Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 11:59 ` [RFC v3 5/5] arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich 2022-05-14 11:59 ` Frank Wunderlich
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