From: James Clark <james.clark@arm.com> To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, broonie@kernel.org, acme@kernel.org Cc: german.gomez@arm.com, leo.yan@linaro.org, mathieu.poirier@linaro.org, john.garry@huawei.com, James Clark <james.clark@arm.com>, Will Deacon <will@kernel.org>, Mike Leach <mike.leach@linaro.org>, Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>, Mark Rutland <mark.rutland@arm.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 4/4] perf tools: arm64: Add support for VG register Date: Tue, 17 May 2022 11:20:05 +0100 [thread overview] Message-ID: <20220517102005.3022017-5-james.clark@arm.com> (raw) In-Reply-To: <20220517102005.3022017-1-james.clark@arm.com> Add the name of the VG register so it can be used in --user-regs The event will fail to open if the register is requested but not available so only add it to the mask if the kernel supports sve and also if it supports that specific register. Signed-off-by: James Clark <james.clark@arm.com> --- tools/perf/arch/arm64/util/perf_regs.c | 34 ++++++++++++++++++++++++++ tools/perf/util/perf_regs.c | 2 ++ 2 files changed, 36 insertions(+) diff --git a/tools/perf/arch/arm64/util/perf_regs.c b/tools/perf/arch/arm64/util/perf_regs.c index 476b037eea1c..c0a921512a90 100644 --- a/tools/perf/arch/arm64/util/perf_regs.c +++ b/tools/perf/arch/arm64/util/perf_regs.c @@ -2,9 +2,11 @@ #include <errno.h> #include <regex.h> #include <string.h> +#include <sys/auxv.h> #include <linux/kernel.h> #include <linux/zalloc.h> +#include "../../../perf-sys.h" #include "../../../util/debug.h" #include "../../../util/event.h" #include "../../../util/perf_regs.h" @@ -43,6 +45,7 @@ const struct sample_reg sample_reg_masks[] = { SMPL_REG(lr, PERF_REG_ARM64_LR), SMPL_REG(sp, PERF_REG_ARM64_SP), SMPL_REG(pc, PERF_REG_ARM64_PC), + SMPL_REG(vg, PERF_REG_ARM64_VG), SMPL_REG_END }; @@ -131,3 +134,34 @@ int arch_sdt_arg_parse_op(char *old_op, char **new_op) return SDT_ARG_VALID; } + +uint64_t arch__user_reg_mask(void) +{ + struct perf_event_attr attr = { + .type = PERF_TYPE_HARDWARE, + .config = PERF_COUNT_HW_CPU_CYCLES, + .sample_type = PERF_SAMPLE_REGS_USER, + .disabled = 1, + .exclude_kernel = 1, + .sample_period = 1, + .sample_regs_user = PERF_REGS_MASK + }; + int fd; + + if (getauxval(AT_HWCAP) & HWCAP_SVE) + attr.sample_regs_user |= SMPL_REG_MASK(PERF_REG_ARM64_VG); + + /* + * Check if the pmu supports perf extended regs, before + * returning the register mask to sample. + */ + if (attr.sample_regs_user != PERF_REGS_MASK) { + event_attr_init(&attr); + fd = sys_perf_event_open(&attr, 0, -1, -1, 0); + if (fd != -1) { + close(fd); + return attr.sample_regs_user; + } + } + return PERF_REGS_MASK; +} diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c index a982e40ee5a9..872dd3d38782 100644 --- a/tools/perf/util/perf_regs.c +++ b/tools/perf/util/perf_regs.c @@ -103,6 +103,8 @@ static const char *__perf_reg_name_arm64(int id) return "lr"; case PERF_REG_ARM64_PC: return "pc"; + case PERF_REG_ARM64_VG: + return "vg"; default: return NULL; } -- 2.28.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: James Clark <james.clark@arm.com> To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, broonie@kernel.org, acme@kernel.org Cc: german.gomez@arm.com, leo.yan@linaro.org, mathieu.poirier@linaro.org, john.garry@huawei.com, James Clark <james.clark@arm.com>, Will Deacon <will@kernel.org>, Mike Leach <mike.leach@linaro.org>, Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>, Mark Rutland <mark.rutland@arm.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 4/4] perf tools: arm64: Add support for VG register Date: Tue, 17 May 2022 11:20:05 +0100 [thread overview] Message-ID: <20220517102005.3022017-5-james.clark@arm.com> (raw) In-Reply-To: <20220517102005.3022017-1-james.clark@arm.com> Add the name of the VG register so it can be used in --user-regs The event will fail to open if the register is requested but not available so only add it to the mask if the kernel supports sve and also if it supports that specific register. Signed-off-by: James Clark <james.clark@arm.com> --- tools/perf/arch/arm64/util/perf_regs.c | 34 ++++++++++++++++++++++++++ tools/perf/util/perf_regs.c | 2 ++ 2 files changed, 36 insertions(+) diff --git a/tools/perf/arch/arm64/util/perf_regs.c b/tools/perf/arch/arm64/util/perf_regs.c index 476b037eea1c..c0a921512a90 100644 --- a/tools/perf/arch/arm64/util/perf_regs.c +++ b/tools/perf/arch/arm64/util/perf_regs.c @@ -2,9 +2,11 @@ #include <errno.h> #include <regex.h> #include <string.h> +#include <sys/auxv.h> #include <linux/kernel.h> #include <linux/zalloc.h> +#include "../../../perf-sys.h" #include "../../../util/debug.h" #include "../../../util/event.h" #include "../../../util/perf_regs.h" @@ -43,6 +45,7 @@ const struct sample_reg sample_reg_masks[] = { SMPL_REG(lr, PERF_REG_ARM64_LR), SMPL_REG(sp, PERF_REG_ARM64_SP), SMPL_REG(pc, PERF_REG_ARM64_PC), + SMPL_REG(vg, PERF_REG_ARM64_VG), SMPL_REG_END }; @@ -131,3 +134,34 @@ int arch_sdt_arg_parse_op(char *old_op, char **new_op) return SDT_ARG_VALID; } + +uint64_t arch__user_reg_mask(void) +{ + struct perf_event_attr attr = { + .type = PERF_TYPE_HARDWARE, + .config = PERF_COUNT_HW_CPU_CYCLES, + .sample_type = PERF_SAMPLE_REGS_USER, + .disabled = 1, + .exclude_kernel = 1, + .sample_period = 1, + .sample_regs_user = PERF_REGS_MASK + }; + int fd; + + if (getauxval(AT_HWCAP) & HWCAP_SVE) + attr.sample_regs_user |= SMPL_REG_MASK(PERF_REG_ARM64_VG); + + /* + * Check if the pmu supports perf extended regs, before + * returning the register mask to sample. + */ + if (attr.sample_regs_user != PERF_REGS_MASK) { + event_attr_init(&attr); + fd = sys_perf_event_open(&attr, 0, -1, -1, 0); + if (fd != -1) { + close(fd); + return attr.sample_regs_user; + } + } + return PERF_REGS_MASK; +} diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c index a982e40ee5a9..872dd3d38782 100644 --- a/tools/perf/util/perf_regs.c +++ b/tools/perf/util/perf_regs.c @@ -103,6 +103,8 @@ static const char *__perf_reg_name_arm64(int id) return "lr"; case PERF_REG_ARM64_PC: return "pc"; + case PERF_REG_ARM64_VG: + return "vg"; default: return NULL; } -- 2.28.0
next prev parent reply other threads:[~2022-05-17 10:23 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-17 10:20 [PATCH v2 0/2] perf: arm64: Tools support for Dwarf unwinding through SVE functions James Clark 2022-05-17 10:20 ` James Clark 2022-05-17 10:20 ` [PATCH v2 1/4] perf tools: arm64: Copy perf_regs.h from the kernel James Clark 2022-05-17 10:20 ` James Clark 2022-05-17 10:50 ` Leo Yan 2022-05-17 10:50 ` Leo Yan 2022-05-17 10:20 ` [PATCH v2 2/4] perf tools: Use dynamic register set for Dwarf unwind James Clark 2022-05-17 10:20 ` James Clark 2022-05-17 11:03 ` Leo Yan 2022-05-17 11:03 ` Leo Yan 2022-05-18 13:25 ` James Clark 2022-05-18 13:25 ` James Clark 2022-05-18 14:00 ` Leo Yan 2022-05-18 14:00 ` Leo Yan 2022-05-17 10:20 ` [PATCH v2 3/4] perf tools: arm64: Decouple Libunwind register names from Perf James Clark 2022-05-17 10:20 ` James Clark 2022-05-17 12:54 ` Leo Yan 2022-05-17 12:54 ` Leo Yan 2022-05-17 10:20 ` James Clark [this message] 2022-05-17 10:20 ` [PATCH v2 4/4] perf tools: arm64: Add support for VG register James Clark 2022-05-17 13:19 ` Leo Yan 2022-05-17 13:19 ` Leo Yan 2022-05-18 9:44 ` James Clark 2022-05-18 9:44 ` James Clark 2022-05-18 9:57 ` Leo Yan 2022-05-18 9:57 ` Leo Yan 2022-05-17 14:58 ` [PATCH v2 0/2] perf: arm64: Tools support for Dwarf unwinding through SVE functions Arnaldo Carvalho de Melo 2022-05-17 14:58 ` Arnaldo Carvalho de Melo 2022-05-20 11:46 ` German Gomez 2022-05-20 11:46 ` German Gomez 2022-05-20 12:32 ` Arnaldo Carvalho de Melo 2022-05-20 12:32 ` Arnaldo Carvalho de Melo 2022-05-20 14:52 ` James Clark 2022-05-20 14:52 ` James Clark
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