* [PATCH v1 1/9] arm64/sysreg: Generate definitions for CCSIDR2_EL1
2022-05-17 18:22 [PATCH v1 0/9] arm64/sysreg: More system register generation Mark Brown
@ 2022-05-17 18:22 ` Mark Brown
2022-05-20 14:53 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 2/9] arm64/sysreg: Generate definitions for CLIDR_EL1 Mark Brown
` (7 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Mark Brown @ 2022-05-17 18:22 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon; +Cc: Mark Rutland, linux-arm-kernel, Mark Brown
Convert CCSIDR2_EL1 to be automatically generated as per DDI0487H.a. No
functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 8 ++++++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 91e4f8601393..45d29f34d9b3 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -456,7 +456,6 @@
#define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
-#define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0)
#define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
#define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4)
#define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index a236d7a821b4..db395dabc9e9 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -212,6 +212,14 @@ Sysreg SMCR_EL1 3 0 1 2 6
Fields SMCR_ELx
EndSysreg
+Sysreg CCSIDR_EL1 3 1 0 0 0
+Res0 63:56
+Field 55:32 NumSets
+Res0 31:24
+Field 23:3 Associativity
+Field 2:0 LineSize
+EndSysreg
+
Sysreg SMIDR_EL1 3 1 0 0 6
Res0 63:32
Field 31:24 IMPLEMENTER
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v1 1/9] arm64/sysreg: Generate definitions for CCSIDR2_EL1
2022-05-17 18:22 ` [PATCH v1 1/9] arm64/sysreg: Generate definitions for CCSIDR2_EL1 Mark Brown
@ 2022-05-20 14:53 ` Mark Rutland
0 siblings, 0 replies; 21+ messages in thread
From: Mark Rutland @ 2022-05-20 14:53 UTC (permalink / raw)
To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, linux-arm-kernel
On Tue, May 17, 2022 at 07:22:11PM +0100, Mark Brown wrote:
> Convert CCSIDR2_EL1 to be automatically generated as per DDI0487H.a. No
> functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
The commit message and title say CCSIDR2_EL1, but the patch changes CCSIDR_EL1
(no '2').
> ---
> arch/arm64/include/asm/sysreg.h | 1 -
> arch/arm64/tools/sysreg | 8 ++++++++
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 91e4f8601393..45d29f34d9b3 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -456,7 +456,6 @@
>
> #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
>
> -#define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0)
> #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
> #define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4)
> #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index a236d7a821b4..db395dabc9e9 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -212,6 +212,14 @@ Sysreg SMCR_EL1 3 0 1 2 6
> Fields SMCR_ELx
> EndSysreg
>
> +Sysreg CCSIDR_EL1 3 1 0 0 0
> +Res0 63:56
> +Field 55:32 NumSets
> +Res0 31:24
> +Field 23:3 Associativity
> +Field 2:0 LineSize
> +EndSysreg
Looking at ARM DDI 0487H.a pages D13-5299 to D13-5301, the layout of CCSIDR_EL1
depends on whether FEAT_CCIDX is implemented:
* When FEAT_CCIDX is implemented:
63:56 RES0
55:32 NumSets
31:24 RES0
23:3 Associativity
2:0 LineSize
* When FEAT_CCIDX is not implemented (e.g. baseline ARMv8.0)
63:32 RES0
31:28 UNKNOWN
27:13 NumSets
12:3 Associativity
2:0 LineSize
The existing code doesn't depend upn the layout, so I agree there's no
functional change.
However, since this patch adds the FEAT_CCIDX layout specifically, I reckon we
need to think about how to capture that fact in the naming.
Thanks,
Mark.
> +
> Sysreg SMIDR_EL1 3 1 0 0 6
> Res0 63:32
> Field 31:24 IMPLEMENTER
> --
> 2.30.2
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v1 2/9] arm64/sysreg: Generate definitions for CLIDR_EL1
2022-05-17 18:22 [PATCH v1 0/9] arm64/sysreg: More system register generation Mark Brown
2022-05-17 18:22 ` [PATCH v1 1/9] arm64/sysreg: Generate definitions for CCSIDR2_EL1 Mark Brown
@ 2022-05-17 18:22 ` Mark Brown
2022-05-20 14:56 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 3/9] arm64/sysreg: Generate definitions for CONTEXTIDR_ELx Mark Brown
` (6 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Mark Brown @ 2022-05-17 18:22 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon; +Cc: Mark Rutland, linux-arm-kernel, Mark Brown
Convert CLIDR_EL1 to be automatically generated with definition as per
DDI0487H.a. No functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 16 ++++++++++++++++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 45d29f34d9b3..d7a98dc62029 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -456,7 +456,6 @@
#define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
-#define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
#define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4)
#define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index db395dabc9e9..8b5788cbf099 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -220,6 +220,22 @@ Field 23:3 Associativity
Field 2:0 LineSize
EndSysreg
+Sysreg CLIDR_EL1 3 1 0 0 1
+Res0 63:47
+Field 46:33 Ttypen
+Field 32:30 ICB
+Field 29:27 LoUU
+Field 26:24 LoC
+Field 23:21 LoUIS
+Field 20:18 Ctype7
+Field 17:15 Ctype6
+Field 14:12 Ctype5
+Field 11:9 Ctype4
+Field 8:6 Ctype3
+Field 5:3 Ctype2
+Field 2:0 Ctype1
+EndSysreg
+
Sysreg SMIDR_EL1 3 1 0 0 6
Res0 63:32
Field 31:24 IMPLEMENTER
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v1 2/9] arm64/sysreg: Generate definitions for CLIDR_EL1
2022-05-17 18:22 ` [PATCH v1 2/9] arm64/sysreg: Generate definitions for CLIDR_EL1 Mark Brown
@ 2022-05-20 14:56 ` Mark Rutland
0 siblings, 0 replies; 21+ messages in thread
From: Mark Rutland @ 2022-05-20 14:56 UTC (permalink / raw)
To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, linux-arm-kernel
On Tue, May 17, 2022 at 07:22:12PM +0100, Mark Brown wrote:
> Convert CLIDR_EL1 to be automatically generated with definition as per
> DDI0487H.a. No functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 1 -
> arch/arm64/tools/sysreg | 16 ++++++++++++++++
> 2 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 45d29f34d9b3..d7a98dc62029 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -456,7 +456,6 @@
>
> #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
>
> -#define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
> #define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4)
> #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
>
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index db395dabc9e9..8b5788cbf099 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -220,6 +220,22 @@ Field 23:3 Associativity
> Field 2:0 LineSize
> EndSysreg
>
> +Sysreg CLIDR_EL1 3 1 0 0 1
> +Res0 63:47
> +Field 46:33 Ttypen
> +Field 32:30 ICB
> +Field 29:27 LoUU
> +Field 26:24 LoC
> +Field 23:21 LoUIS
> +Field 20:18 Ctype7
> +Field 17:15 Ctype6
> +Field 14:12 Ctype5
> +Field 11:9 Ctype4
> +Field 8:6 Ctype3
> +Field 5:3 Ctype2
> +Field 2:0 Ctype1
> +EndSysreg
I've compared this to ARM DDI 0487H.a, pages D13-5302 to D13-5304,
and this all looks correct to me:
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Mark.
> +
> Sysreg SMIDR_EL1 3 1 0 0 6
> Res0 63:32
> Field 31:24 IMPLEMENTER
> --
> 2.30.2
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v1 3/9] arm64/sysreg: Generate definitions for CONTEXTIDR_ELx
2022-05-17 18:22 [PATCH v1 0/9] arm64/sysreg: More system register generation Mark Brown
2022-05-17 18:22 ` [PATCH v1 1/9] arm64/sysreg: Generate definitions for CCSIDR2_EL1 Mark Brown
2022-05-17 18:22 ` [PATCH v1 2/9] arm64/sysreg: Generate definitions for CLIDR_EL1 Mark Brown
@ 2022-05-17 18:22 ` Mark Brown
2022-05-20 15:01 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 4/9] arm64/sysreg: Generate definitions for CPACR_ELx Mark Brown
` (5 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Mark Brown @ 2022-05-17 18:22 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon; +Cc: Mark Rutland, linux-arm-kernel, Mark Brown
Convert the various CONTEXTIDR_ELx register definitions to be automatically
generated following the definitions in DDI0487H.a. No functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 2 --
arch/arm64/tools/sysreg | 21 +++++++++++++++++++++
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index d7a98dc62029..5a5d6bdaa806 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -449,7 +449,6 @@
#define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
#define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
-#define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
#define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
#define SYS_SCXTNUM_EL1 sys_reg(3, 0, 13, 0, 7)
@@ -628,7 +627,6 @@
#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
-#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
#define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
#define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
#define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 8b5788cbf099..e938d1117d36 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -212,6 +212,15 @@ Sysreg SMCR_EL1 3 0 1 2 6
Fields SMCR_ELx
EndSysreg
+SysregFields CONTEXTIDR_ELx
+Res0 63:32
+Field 31:0 PROCID
+EndSysregFields
+
+Sysreg CONTEXTIDR_EL1 3 0 13 0 1
+Fields CONTEXTIDR_ELx
+EndSysreg
+
Sysreg CCSIDR_EL1 3 1 0 0 0
Res0 63:56
Field 55:32 NumSets
@@ -278,6 +287,14 @@ Sysreg SMCR_EL2 3 4 1 2 6
Fields SMCR_ELx
EndSysreg
+Sysreg CONTEXTIDR_EL2 3 4 13 0 1
+Fields CONTEXTIDR_ELx
+EndSysreg
+
+Sysreg CPACR_EL12 3 5 1 0 2
+Fields CPACR_ELx
+EndSysreg
+
Sysreg ZCR_EL12 3 5 1 2 0
Fields ZCR_ELx
EndSysreg
@@ -286,6 +303,10 @@ Sysreg SMCR_EL12 3 5 1 2 6
Fields SMCR_ELx
EndSysreg
+Sysreg CONTEXTIDR_EL12 3 5 13 0 1
+Fields CONTEXTIDR_ELx
+EndSysreg
+
SysregFields TTBRx_EL1
Field 63:48 ASID
Field 47:1 BADDR
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v1 3/9] arm64/sysreg: Generate definitions for CONTEXTIDR_ELx
2022-05-17 18:22 ` [PATCH v1 3/9] arm64/sysreg: Generate definitions for CONTEXTIDR_ELx Mark Brown
@ 2022-05-20 15:01 ` Mark Rutland
0 siblings, 0 replies; 21+ messages in thread
From: Mark Rutland @ 2022-05-20 15:01 UTC (permalink / raw)
To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, linux-arm-kernel
On Tue, May 17, 2022 at 07:22:13PM +0100, Mark Brown wrote:
> Convert the various CONTEXTIDR_ELx register definitions to be automatically
> generated following the definitions in DDI0487H.a. No functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 2 --
> arch/arm64/tools/sysreg | 21 +++++++++++++++++++++
> 2 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index d7a98dc62029..5a5d6bdaa806 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -449,7 +449,6 @@
> #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
> #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
>
> -#define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
> #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
>
> #define SYS_SCXTNUM_EL1 sys_reg(3, 0, 13, 0, 7)
> @@ -628,7 +627,6 @@
> #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
> #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
> #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
> -#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
> #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
> #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
> #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 8b5788cbf099..e938d1117d36 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -212,6 +212,15 @@ Sysreg SMCR_EL1 3 0 1 2 6
> Fields SMCR_ELx
> EndSysreg
>
> +SysregFields CONTEXTIDR_ELx
> +Res0 63:32
> +Field 31:0 PROCID
> +EndSysregFields
> +
> +Sysreg CONTEXTIDR_EL1 3 0 13 0 1
> +Fields CONTEXTIDR_ELx
> +EndSysreg
> +
> Sysreg CCSIDR_EL1 3 1 0 0 0
> Res0 63:56
> Field 55:32 NumSets
> @@ -278,6 +287,14 @@ Sysreg SMCR_EL2 3 4 1 2 6
> Fields SMCR_ELx
> EndSysreg
>
> +Sysreg CONTEXTIDR_EL2 3 4 13 0 1
> +Fields CONTEXTIDR_ELx
> +EndSysreg
> +
> +Sysreg CPACR_EL12 3 5 1 0 2
> +Fields CPACR_ELx
> +EndSysreg
Accidental addition?
> +
> Sysreg ZCR_EL12 3 5 1 2 0
> Fields ZCR_ELx
> EndSysreg
> @@ -286,6 +303,10 @@ Sysreg SMCR_EL12 3 5 1 2 6
> Fields SMCR_ELx
> EndSysreg
>
> +Sysreg CONTEXTIDR_EL12 3 5 13 0 1
> +Fields CONTEXTIDR_ELx
> +EndSysreg
All the CONTEXTIDR_ELx bits look correct, per ARM DDI 0487H.a.
With the CPACR_EL12 definition removed:
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Mark.
> +
> SysregFields TTBRx_EL1
> Field 63:48 ASID
> Field 47:1 BADDR
> --
> 2.30.2
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v1 4/9] arm64/sysreg: Generate definitions for CPACR_ELx
2022-05-17 18:22 [PATCH v1 0/9] arm64/sysreg: More system register generation Mark Brown
` (2 preceding siblings ...)
2022-05-17 18:22 ` [PATCH v1 3/9] arm64/sysreg: Generate definitions for CONTEXTIDR_ELx Mark Brown
@ 2022-05-17 18:22 ` Mark Brown
2022-05-20 15:10 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 5/9] arm64/sysreg: Generate definitions for CSSELR_EL1 Mark Brown
` (4 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Mark Brown @ 2022-05-17 18:22 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon; +Cc: Mark Rutland, linux-arm-kernel, Mark Brown
Convert the CPACR system register definitions to be automatically generated
using the definitions in DDI0487H.a. The kernel does have some additional
definitions for subfields of SMEN, FPEN and ZEN which are not identified as
distinct subfields in the architecture so the definitions are not updated
as part of this patch.
No functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 2 --
arch/arm64/tools/sysreg | 16 ++++++++++++++++
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 5a5d6bdaa806..c30f5aafde34 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -209,7 +209,6 @@
#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
-#define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
@@ -613,7 +612,6 @@
/* VHE encodings for architectural EL0/1 system registers */
#define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
-#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
#define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
#define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
#define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index e938d1117d36..21d5c140fde3 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -185,6 +185,22 @@ Field 1 A
Field 0 M
EndSysreg
+SysregFields CPACR_ELx
+Res0 63:29
+Field 28 TTA
+Res0 27:26
+Field 25:24 SMEN
+Res0 23:22
+Field 21:20 FPEN
+Res0 19:18
+Field 17:16 ZEN
+Res0 15:0
+EndSysregFields
+
+Sysreg CPACR_EL1 3 0 1 0 2
+Fields CPACR_ELx
+EndSysreg
+
Sysreg SMPRI_EL1 3 0 1 2 4
Res0 63:4
Field 3:0 PRIORITY
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v1 4/9] arm64/sysreg: Generate definitions for CPACR_ELx
2022-05-17 18:22 ` [PATCH v1 4/9] arm64/sysreg: Generate definitions for CPACR_ELx Mark Brown
@ 2022-05-20 15:10 ` Mark Rutland
2022-05-20 15:29 ` Mark Brown
0 siblings, 1 reply; 21+ messages in thread
From: Mark Rutland @ 2022-05-20 15:10 UTC (permalink / raw)
To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, linux-arm-kernel
On Tue, May 17, 2022 at 07:22:14PM +0100, Mark Brown wrote:
> Convert the CPACR system register definitions to be automatically generated
> using the definitions in DDI0487H.a. The kernel does have some additional
> definitions for subfields of SMEN, FPEN and ZEN which are not identified as
> distinct subfields in the architecture so the definitions are not updated
> as part of this patch.
Maybe we should covert those over to an enumeration style?
>
> No functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 2 --
> arch/arm64/tools/sysreg | 16 ++++++++++++++++
> 2 files changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 5a5d6bdaa806..c30f5aafde34 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -209,7 +209,6 @@
> #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
>
> #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
> -#define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
> #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
> #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
>
> @@ -613,7 +612,6 @@
>
> /* VHE encodings for architectural EL0/1 system registers */
> #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
> -#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
The corresponding addition to the sysreg file got caught in the prior patch
(bad rebase?).
> #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
> #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
> #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index e938d1117d36..21d5c140fde3 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -185,6 +185,22 @@ Field 1 A
> Field 0 M
> EndSysreg
>
> +SysregFields CPACR_ELx
> +Res0 63:29
> +Field 28 TTA
> +Res0 27:26
> +Field 25:24 SMEN
> +Res0 23:22
> +Field 21:20 FPEN
> +Res0 19:18
> +Field 17:16 ZEN
> +Res0 15:0
> +EndSysregFields
> +
> +Sysreg CPACR_EL1 3 0 1 0 2
> +Fields CPACR_ELx
> +EndSysreg
These all look right to me for CPACR_EL1.
Thanks,
Mark.
> +
> Sysreg SMPRI_EL1 3 0 1 2 4
> Res0 63:4
> Field 3:0 PRIORITY
> --
> 2.30.2
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 4/9] arm64/sysreg: Generate definitions for CPACR_ELx
2022-05-20 15:10 ` Mark Rutland
@ 2022-05-20 15:29 ` Mark Brown
0 siblings, 0 replies; 21+ messages in thread
From: Mark Brown @ 2022-05-20 15:29 UTC (permalink / raw)
To: Mark Rutland; +Cc: Catalin Marinas, Will Deacon, linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 714 bytes --]
On Fri, May 20, 2022 at 04:10:15PM +0100, Mark Rutland wrote:
> On Tue, May 17, 2022 at 07:22:14PM +0100, Mark Brown wrote:
> > Convert the CPACR system register definitions to be automatically generated
> > using the definitions in DDI0487H.a. The kernel does have some additional
> > definitions for subfields of SMEN, FPEN and ZEN which are not identified as
> > distinct subfields in the architecture so the definitions are not updated
> > as part of this patch.
> Maybe we should covert those over to an enumeration style?
That doesn't really help our usage at all, the effective bitfields are
two independent bits for EL1 and EL0 which we use as such. Enumeration
values would cover the two bits at once.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v1 5/9] arm64/sysreg: Generate definitions for CSSELR_EL1
2022-05-17 18:22 [PATCH v1 0/9] arm64/sysreg: More system register generation Mark Brown
` (3 preceding siblings ...)
2022-05-17 18:22 ` [PATCH v1 4/9] arm64/sysreg: Generate definitions for CPACR_ELx Mark Brown
@ 2022-05-17 18:22 ` Mark Brown
2022-05-20 15:12 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 6/9] arm64/sysreg: Generate definitions for CTR_EL0 Mark Brown
` (3 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Mark Brown @ 2022-05-17 18:22 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon; +Cc: Mark Rutland, linux-arm-kernel, Mark Brown
Convert CSSELR_EL1 to automatic generation as per DDI0487H.a, no functional
change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 2 --
arch/arm64/tools/sysreg | 7 +++++++
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index c30f5aafde34..6240149f9818 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -461,8 +461,6 @@
#define SMIDR_EL1_SMPS_SHIFT 15
#define SMIDR_EL1_AFFINITY_SHIFT 0
-#define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
-
#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 21d5c140fde3..47c4c45d5dc3 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -270,6 +270,13 @@ Res0 14:12
Field 11:0 AFFINITY
EndSysreg
+Sysreg CSSELR_EL1 3 2 0 0 0
+Res0 63:5
+Field 4 TnD
+Field 3:1 Level
+Field 0 InD
+EndSysreg
+
Sysreg SVCR 3 3 4 2 2
Res0 63:2
Field 1 ZA
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v1 5/9] arm64/sysreg: Generate definitions for CSSELR_EL1
2022-05-17 18:22 ` [PATCH v1 5/9] arm64/sysreg: Generate definitions for CSSELR_EL1 Mark Brown
@ 2022-05-20 15:12 ` Mark Rutland
0 siblings, 0 replies; 21+ messages in thread
From: Mark Rutland @ 2022-05-20 15:12 UTC (permalink / raw)
To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, linux-arm-kernel
On Tue, May 17, 2022 at 07:22:15PM +0100, Mark Brown wrote:
> Convert CSSELR_EL1 to automatic generation as per DDI0487H.a, no functional
> change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 2 --
> arch/arm64/tools/sysreg | 7 +++++++
> 2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index c30f5aafde34..6240149f9818 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -461,8 +461,6 @@
> #define SMIDR_EL1_SMPS_SHIFT 15
> #define SMIDR_EL1_AFFINITY_SHIFT 0
>
> -#define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
> -
> #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
> #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
>
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 21d5c140fde3..47c4c45d5dc3 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -270,6 +270,13 @@ Res0 14:12
> Field 11:0 AFFINITY
> EndSysreg
>
> +Sysreg CSSELR_EL1 3 2 0 0 0
> +Res0 63:5
> +Field 4 TnD
> +Field 3:1 Level
> +Field 0 InD
> +EndSysreg
These all look right to me per ARM DDI 0487H.a pages D13-5332 to D13-5334:
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Mark.
> +
> Sysreg SVCR 3 3 4 2 2
> Res0 63:2
> Field 1 ZA
> --
> 2.30.2
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v1 6/9] arm64/sysreg: Generate definitions for CTR_EL0
2022-05-17 18:22 [PATCH v1 0/9] arm64/sysreg: More system register generation Mark Brown
` (4 preceding siblings ...)
2022-05-17 18:22 ` [PATCH v1 5/9] arm64/sysreg: Generate definitions for CSSELR_EL1 Mark Brown
@ 2022-05-17 18:22 ` Mark Brown
2022-05-20 15:20 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 7/9] arm64/sysreg: Generate definitions for DACR32_EL2 Mark Brown
` (2 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Mark Brown @ 2022-05-17 18:22 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon; +Cc: Mark Rutland, linux-arm-kernel, Mark Brown
Convert CTR_EL0 to automatic register generation as per DDI0487H.a, no
functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 15 +++++++++++++++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 6240149f9818..c77e2310d189 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -461,7 +461,6 @@
#define SMIDR_EL1_SMPS_SHIFT 15
#define SMIDR_EL1_AFFINITY_SHIFT 0
-#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
#define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 47c4c45d5dc3..3971e1fb6af4 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -277,6 +277,21 @@ Field 3:1 Level
Field 0 InD
EndSysreg
+Sysreg CTR_EL0 3 3 0 0 1
+Res0 63:38
+Field 37:32 TminLine
+Res1 31
+Res0 30
+Field 29 DIC
+Field 28 IDC
+Field 27:24 CWG
+Field 23:20 ERG
+Field 19:16 DminLine
+Field 15:14 L1Ip
+Res0 13:4
+Field 3:0 IminLine
+EndSysreg
+
Sysreg SVCR 3 3 4 2 2
Res0 63:2
Field 1 ZA
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v1 6/9] arm64/sysreg: Generate definitions for CTR_EL0
2022-05-17 18:22 ` [PATCH v1 6/9] arm64/sysreg: Generate definitions for CTR_EL0 Mark Brown
@ 2022-05-20 15:20 ` Mark Rutland
2022-05-20 15:29 ` Mark Rutland
0 siblings, 1 reply; 21+ messages in thread
From: Mark Rutland @ 2022-05-20 15:20 UTC (permalink / raw)
To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, linux-arm-kernel
On Tue, May 17, 2022 at 07:22:16PM +0100, Mark Brown wrote:
> Convert CTR_EL0 to automatic register generation as per DDI0487H.a, no
> functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 1 -
> arch/arm64/tools/sysreg | 15 +++++++++++++++
> 2 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 6240149f9818..c77e2310d189 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -461,7 +461,6 @@
> #define SMIDR_EL1_SMPS_SHIFT 15
> #define SMIDR_EL1_AFFINITY_SHIFT 0
>
> -#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
> #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
>
> #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 47c4c45d5dc3..3971e1fb6af4 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -277,6 +277,21 @@ Field 3:1 Level
> Field 0 InD
> EndSysreg
>
> +Sysreg CTR_EL0 3 3 0 0 1
> +Res0 63:38
> +Field 37:32 TminLine
> +Res1 31
> +Res0 30
> +Field 29 DIC
> +Field 28 IDC
> +Field 27:24 CWG
> +Field 23:20 ERG
> +Field 19:16 DminLine
> +Field 15:14 L1Ip
> +Res0 13:4
> +Field 3:0 IminLine
> +EndSysreg
The values all look right to me.
The L1Ip field is an enumeration where:
* 0b00 means VPIPT
* 0b01 means AIVIVT // reserved in ARMv8
* 0b10 means VIPT
* 0b11 means PIPT
So I reckon we want to describe that as:
Enum 15:14 L1Ip
0b00 VPIPT
0b01 AIVIVT # or RESERVED
0b10 VIPT
0b11 PIPT
EndEnum
We have some existing definitions that could be removed (and their users
converted over):
| arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_VPIPT 0
| arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_RESERVED 1
| arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_VIPT 2
| arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_PIPT 3
Thanks,
Mark.
> +
> Sysreg SVCR 3 3 4 2 2
> Res0 63:2
> Field 1 ZA
> --
> 2.30.2
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 6/9] arm64/sysreg: Generate definitions for CTR_EL0
2022-05-20 15:20 ` Mark Rutland
@ 2022-05-20 15:29 ` Mark Rutland
0 siblings, 0 replies; 21+ messages in thread
From: Mark Rutland @ 2022-05-20 15:29 UTC (permalink / raw)
To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, linux-arm-kernel
On Fri, May 20, 2022 at 04:20:25PM +0100, Mark Rutland wrote:
> On Tue, May 17, 2022 at 07:22:16PM +0100, Mark Brown wrote:
> > Convert CTR_EL0 to automatic register generation as per DDI0487H.a, no
> > functional change.
> >
> > Signed-off-by: Mark Brown <broonie@kernel.org>
> > ---
> > arch/arm64/include/asm/sysreg.h | 1 -
> > arch/arm64/tools/sysreg | 15 +++++++++++++++
> > 2 files changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> > index 6240149f9818..c77e2310d189 100644
> > --- a/arch/arm64/include/asm/sysreg.h
> > +++ b/arch/arm64/include/asm/sysreg.h
> > @@ -461,7 +461,6 @@
> > #define SMIDR_EL1_SMPS_SHIFT 15
> > #define SMIDR_EL1_AFFINITY_SHIFT 0
> >
> > -#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
> > #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
> >
> > #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
> > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> > index 47c4c45d5dc3..3971e1fb6af4 100644
> > --- a/arch/arm64/tools/sysreg
> > +++ b/arch/arm64/tools/sysreg
> > @@ -277,6 +277,21 @@ Field 3:1 Level
> > Field 0 InD
> > EndSysreg
> >
> > +Sysreg CTR_EL0 3 3 0 0 1
> > +Res0 63:38
> > +Field 37:32 TminLine
> > +Res1 31
> > +Res0 30
> > +Field 29 DIC
> > +Field 28 IDC
> > +Field 27:24 CWG
> > +Field 23:20 ERG
> > +Field 19:16 DminLine
> > +Field 15:14 L1Ip
> > +Res0 13:4
> > +Field 3:0 IminLine
> > +EndSysreg
>
> The values all look right to me.
>
> The L1Ip field is an enumeration where:
>
> * 0b00 means VPIPT
> * 0b01 means AIVIVT // reserved in ARMv8
> * 0b10 means VIPT
> * 0b11 means PIPT
>
> So I reckon we want to describe that as:
>
> Enum 15:14 L1Ip
> 0b00 VPIPT
> 0b01 AIVIVT # or RESERVED
> 0b10 VIPT
> 0b11 PIPT
> EndEnum
>
> We have some existing definitions that could be removed (and their users
> converted over):
>
> | arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_VPIPT 0
> | arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_RESERVED 1
> | arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_VIPT 2
> | arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_PIPT 3
Likewise there are CTR_* definitions that should be converted over along with
their users:
arch/arm64/include/asm/cache.h:#define CTR_L1IP_MASK 3
arch/arm64/include/asm/cache.h:#define CTR_DMINLINE_SHIFT 16
arch/arm64/include/asm/cache.h:#define CTR_IMINLINE_SHIFT 0
arch/arm64/include/asm/cache.h:#define CTR_IMINLINE_MASK 0xf
arch/arm64/include/asm/cache.h:#define CTR_ERG_SHIFT 20
arch/arm64/include/asm/cache.h:#define CTR_CWG_SHIFT 24
arch/arm64/include/asm/cache.h:#define CTR_CWG_MASK 15
arch/arm64/include/asm/cache.h:#define CTR_IDC_SHIFT 28
arch/arm64/include/asm/cache.h:#define CTR_DIC_SHIFT 29
arch/arm64/include/asm/cache.h:#define CTR_CACHE_MINLINE_MASK \
arch/arm64/include/asm/cache.h: (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)
arch/arm64/include/asm/cache.h:#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
Mark.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v1 7/9] arm64/sysreg: Generate definitions for DACR32_EL2
2022-05-17 18:22 [PATCH v1 0/9] arm64/sysreg: More system register generation Mark Brown
` (5 preceding siblings ...)
2022-05-17 18:22 ` [PATCH v1 6/9] arm64/sysreg: Generate definitions for CTR_EL0 Mark Brown
@ 2022-05-17 18:22 ` Mark Brown
2022-05-20 15:22 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 8/9] arm64/sysreg: Generate definitions for DCZID_EL0 Mark Brown
2022-05-17 18:22 ` [PATCH v1 9/9] arm64/sysreg: Generate definitions for FAR_ELx Mark Brown
8 siblings, 1 reply; 21+ messages in thread
From: Mark Brown @ 2022-05-17 18:22 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon; +Cc: Mark Rutland, linux-arm-kernel, Mark Brown
Convert DACR32_EL2 to automatic register generation as per DDI0487H.a, no
functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 20 ++++++++++++++++++++
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index c77e2310d189..e8e9040227f6 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -552,7 +552,6 @@
#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
#define SYS_HCRX_EL2 sys_reg(3, 4, 1, 2, 2)
-#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
#define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4)
#define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5)
#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 3971e1fb6af4..543ba10f3dac 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -325,6 +325,26 @@ Sysreg SMCR_EL2 3 4 1 2 6
Fields SMCR_ELx
EndSysreg
+Sysreg DACR32_EL2 3 4 3 0 0
+Res0 63:32
+Field 31:30 D15
+Field 29:28 D14
+Field 27:26 D13
+Field 25:24 D12
+Field 23:22 D11
+Field 21:20 D10
+Field 19:18 D9
+Field 17:16 D8
+Field 15:14 D7
+Field 13:12 D6
+Field 11:10 D5
+Field 9:8 D4
+Field 7:6 D3
+Field 5:4 D2
+Field 3:2 D1
+Field 1:0 D0
+EndSysreg
+
Sysreg CONTEXTIDR_EL2 3 4 13 0 1
Fields CONTEXTIDR_ELx
EndSysreg
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v1 7/9] arm64/sysreg: Generate definitions for DACR32_EL2
2022-05-17 18:22 ` [PATCH v1 7/9] arm64/sysreg: Generate definitions for DACR32_EL2 Mark Brown
@ 2022-05-20 15:22 ` Mark Rutland
0 siblings, 0 replies; 21+ messages in thread
From: Mark Rutland @ 2022-05-20 15:22 UTC (permalink / raw)
To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, linux-arm-kernel
On Tue, May 17, 2022 at 07:22:17PM +0100, Mark Brown wrote:
> Convert DACR32_EL2 to automatic register generation as per DDI0487H.a, no
> functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 1 -
> arch/arm64/tools/sysreg | 20 ++++++++++++++++++++
> 2 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index c77e2310d189..e8e9040227f6 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -552,7 +552,6 @@
> #define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
> #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
> #define SYS_HCRX_EL2 sys_reg(3, 4, 1, 2, 2)
> -#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
> #define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4)
> #define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5)
> #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 3971e1fb6af4..543ba10f3dac 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -325,6 +325,26 @@ Sysreg SMCR_EL2 3 4 1 2 6
> Fields SMCR_ELx
> EndSysreg
>
> +Sysreg DACR32_EL2 3 4 3 0 0
> +Res0 63:32
> +Field 31:30 D15
> +Field 29:28 D14
> +Field 27:26 D13
> +Field 25:24 D12
> +Field 23:22 D11
> +Field 21:20 D10
> +Field 19:18 D9
> +Field 17:16 D8
> +Field 15:14 D7
> +Field 13:12 D6
> +Field 11:10 D5
> +Field 9:8 D4
> +Field 7:6 D3
> +Field 5:4 D2
> +Field 3:2 D1
> +Field 1:0 D0
> +EndSysreg
These all look correct to me per ARM DDI 0487H.a pages D13-5338 to D13-5339:
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Mark.
> +
> Sysreg CONTEXTIDR_EL2 3 4 13 0 1
> Fields CONTEXTIDR_ELx
> EndSysreg
> --
> 2.30.2
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v1 8/9] arm64/sysreg: Generate definitions for DCZID_EL0
2022-05-17 18:22 [PATCH v1 0/9] arm64/sysreg: More system register generation Mark Brown
` (6 preceding siblings ...)
2022-05-17 18:22 ` [PATCH v1 7/9] arm64/sysreg: Generate definitions for DACR32_EL2 Mark Brown
@ 2022-05-17 18:22 ` Mark Brown
2022-05-20 15:26 ` Mark Rutland
2022-05-17 18:22 ` [PATCH v1 9/9] arm64/sysreg: Generate definitions for FAR_ELx Mark Brown
8 siblings, 1 reply; 21+ messages in thread
From: Mark Brown @ 2022-05-17 18:22 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon; +Cc: Mark Rutland, linux-arm-kernel, Mark Brown
Convert DCZID_EL0 to automatic register generation as per DDI0487H.a, no
functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 2 --
arch/arm64/tools/sysreg | 6 ++++++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index e8e9040227f6..09dc437030f5 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -461,8 +461,6 @@
#define SMIDR_EL1_SMPS_SHIFT 15
#define SMIDR_EL1_AFFINITY_SHIFT 0
-#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
-
#define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
#define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 543ba10f3dac..1cd1e4ea42e3 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -292,6 +292,12 @@ Res0 13:4
Field 3:0 IminLine
EndSysreg
+Sysreg DCZID_EL0 3 3 0 0 7
+Res0 63:5
+Field 4 DZP
+Field 3:0 BS
+EndSysreg
+
Sysreg SVCR 3 3 4 2 2
Res0 63:2
Field 1 ZA
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v1 8/9] arm64/sysreg: Generate definitions for DCZID_EL0
2022-05-17 18:22 ` [PATCH v1 8/9] arm64/sysreg: Generate definitions for DCZID_EL0 Mark Brown
@ 2022-05-20 15:26 ` Mark Rutland
0 siblings, 0 replies; 21+ messages in thread
From: Mark Rutland @ 2022-05-20 15:26 UTC (permalink / raw)
To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, linux-arm-kernel
On Tue, May 17, 2022 at 07:22:18PM +0100, Mark Brown wrote:
> Convert DCZID_EL0 to automatic register generation as per DDI0487H.a, no
> functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 2 --
> arch/arm64/tools/sysreg | 6 ++++++
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index e8e9040227f6..09dc437030f5 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -461,8 +461,6 @@
> #define SMIDR_EL1_SMPS_SHIFT 15
> #define SMIDR_EL1_AFFINITY_SHIFT 0
>
> -#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
> -
> #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
> #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
>
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 543ba10f3dac..1cd1e4ea42e3 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -292,6 +292,12 @@ Res0 13:4
> Field 3:0 IminLine
> EndSysreg
>
> +Sysreg DCZID_EL0 3 3 0 0 7
> +Res0 63:5
> +Field 4 DZP
> +Field 3:0 BS
> +EndSysreg
These all look correct to me per ARM DDI 0487H.a pages D13-5340 to D13-5341.
However, we have existing DCZID_DZP_SHIFT and DCZID_BS_SHIFT definitions that
should be converted over:
arch/arm64/include/asm/sysreg.h:#define DCZID_DZP_SHIFT 4
arch/arm64/include/asm/sysreg.h:#define DCZID_BS_SHIFT 0
arch/arm64/kernel/cpufeature.c: ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1),
arch/arm64/kernel/cpufeature.c: ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0),
Mark.
> +
> Sysreg SVCR 3 3 4 2 2
> Res0 63:2
> Field 1 ZA
> --
> 2.30.2
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v1 9/9] arm64/sysreg: Generate definitions for FAR_ELx
2022-05-17 18:22 [PATCH v1 0/9] arm64/sysreg: More system register generation Mark Brown
` (7 preceding siblings ...)
2022-05-17 18:22 ` [PATCH v1 8/9] arm64/sysreg: Generate definitions for DCZID_EL0 Mark Brown
@ 2022-05-17 18:22 ` Mark Brown
2022-05-20 15:32 ` Mark Rutland
8 siblings, 1 reply; 21+ messages in thread
From: Mark Brown @ 2022-05-17 18:22 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon; +Cc: Mark Rutland, linux-arm-kernel, Mark Brown
Convert FAR_ELx to automatic register generation as per DDI0487H.a. In the
architecture these registers have a single field "named" as "Faulting
Virtual Address for synchronous exceptions taken to ELx" occupying the
entire register, in order to fit in with the requirement to describe the
contents of the register I have created a single field named ADDR.
No functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 3 ---
arch/arm64/tools/sysreg | 12 ++++++++++++
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 09dc437030f5..8ab15c262864 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -249,7 +249,6 @@
#define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
#define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
-#define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
#define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
#define SYS_PAR_EL1_F BIT(0)
@@ -560,7 +559,6 @@
#define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
#define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
#define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
-#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
#define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
#define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
@@ -615,7 +613,6 @@
#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
#define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
-#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 1cd1e4ea42e3..b725edc9626b 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -228,6 +228,10 @@ Sysreg SMCR_EL1 3 0 1 2 6
Fields SMCR_ELx
EndSysreg
+Sysreg FAR_EL1 3 0 6 0 0
+Field 63:0 ADDR
+EndSysreg
+
SysregFields CONTEXTIDR_ELx
Res0 63:32
Field 31:0 PROCID
@@ -351,6 +355,10 @@ Field 3:2 D1
Field 1:0 D0
EndSysreg
+Sysreg FAR_EL2 3 4 6 0 0
+Field 63:0 ADDR
+EndSysreg
+
Sysreg CONTEXTIDR_EL2 3 4 13 0 1
Fields CONTEXTIDR_ELx
EndSysreg
@@ -367,6 +375,10 @@ Sysreg SMCR_EL12 3 5 1 2 6
Fields SMCR_ELx
EndSysreg
+Sysreg FAR_EL12 3 5 6 0 0
+Field 63:0 ADDR
+EndSysreg
+
Sysreg CONTEXTIDR_EL12 3 5 13 0 1
Fields CONTEXTIDR_ELx
EndSysreg
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v1 9/9] arm64/sysreg: Generate definitions for FAR_ELx
2022-05-17 18:22 ` [PATCH v1 9/9] arm64/sysreg: Generate definitions for FAR_ELx Mark Brown
@ 2022-05-20 15:32 ` Mark Rutland
0 siblings, 0 replies; 21+ messages in thread
From: Mark Rutland @ 2022-05-20 15:32 UTC (permalink / raw)
To: Mark Brown; +Cc: Catalin Marinas, Will Deacon, linux-arm-kernel
On Tue, May 17, 2022 at 07:22:19PM +0100, Mark Brown wrote:
> Convert FAR_ELx to automatic register generation as per DDI0487H.a. In the
> architecture these registers have a single field "named" as "Faulting
> Virtual Address for synchronous exceptions taken to ELx" occupying the
> entire register, in order to fit in with the requirement to describe the
> contents of the register I have created a single field named ADDR.
FWIW, that sounds fine by me.
>
> No functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 3 ---
> arch/arm64/tools/sysreg | 12 ++++++++++++
> 2 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 09dc437030f5..8ab15c262864 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -249,7 +249,6 @@
> #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
> #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
>
> -#define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
> #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
>
> #define SYS_PAR_EL1_F BIT(0)
> @@ -560,7 +559,6 @@
> #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
> #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
> #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
> -#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
>
> #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
> #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
> @@ -615,7 +613,6 @@
> #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
> #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
> #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
> -#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
> #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
> #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
> #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 1cd1e4ea42e3..b725edc9626b 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -228,6 +228,10 @@ Sysreg SMCR_EL1 3 0 1 2 6
> Fields SMCR_ELx
> EndSysreg
>
> +Sysreg FAR_EL1 3 0 6 0 0
> +Field 63:0 ADDR
> +EndSysreg
> +
> SysregFields CONTEXTIDR_ELx
> Res0 63:32
> Field 31:0 PROCID
> @@ -351,6 +355,10 @@ Field 3:2 D1
> Field 1:0 D0
> EndSysreg
>
> +Sysreg FAR_EL2 3 4 6 0 0
> +Field 63:0 ADDR
> +EndSysreg
> +
> Sysreg CONTEXTIDR_EL2 3 4 13 0 1
> Fields CONTEXTIDR_ELx
> EndSysreg
> @@ -367,6 +375,10 @@ Sysreg SMCR_EL12 3 5 1 2 6
> Fields SMCR_ELx
> EndSysreg
>
> +Sysreg FAR_EL12 3 5 6 0 0
> +Field 63:0 ADDR
> +EndSysreg
These all look correct to me per ARM DDI 0487H.a.
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Mark.
> +
> Sysreg CONTEXTIDR_EL12 3 5 13 0 1
> Fields CONTEXTIDR_ELx
> EndSysreg
> --
> 2.30.2
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread