From: Sunil V L <sunilvl@ventanamicro.com> To: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Ard Biesheuvel <ardb@kernel.org>, Marc Zyngier <maz@kernel.org>, Atish Patra <atishp@rivosinc.com>, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>, Anup Patel <apatel@ventanamicro.com> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L <sunil.vl@gmail.com>, Sunil V L <sunilvl@ventanamicro.com> Subject: [PATCH 2/5] riscv: cpu_ops_spinwait: Support for 64bit hartid Date: Wed, 25 May 2022 20:41:03 +0530 [thread overview] Message-ID: <20220525151106.2176147-3-sunilvl@ventanamicro.com> (raw) In-Reply-To: <20220525151106.2176147-1-sunilvl@ventanamicro.com> The hartid can be a 64bit value on RV64 platforms. This patch modifies the hartid variable type to unsigned long so that it can hold 64bit value on RV64 platforms. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> --- arch/riscv/kernel/cpu_ops_spinwait.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpu_ops_spinwait.c b/arch/riscv/kernel/cpu_ops_spinwait.c index 346847f6c41c..51ac07514a62 100644 --- a/arch/riscv/kernel/cpu_ops_spinwait.c +++ b/arch/riscv/kernel/cpu_ops_spinwait.c @@ -18,7 +18,7 @@ void *__cpu_spinwait_task_pointer[NR_CPUS] __section(".data"); static void cpu_update_secondary_bootdata(unsigned int cpuid, struct task_struct *tidle) { - int hartid = cpuid_to_hartid_map(cpuid); + unsigned long hartid = cpuid_to_hartid_map(cpuid); /* * The hartid must be less than NR_CPUS to avoid out-of-bound access -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Sunil V L <sunilvl@ventanamicro.com> To: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Ard Biesheuvel <ardb@kernel.org>, Marc Zyngier <maz@kernel.org>, Atish Patra <atishp@rivosinc.com>, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>, Anup Patel <apatel@ventanamicro.com> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L <sunil.vl@gmail.com>, Sunil V L <sunilvl@ventanamicro.com> Subject: [PATCH 2/5] riscv: cpu_ops_spinwait: Support for 64bit hartid Date: Wed, 25 May 2022 20:41:03 +0530 [thread overview] Message-ID: <20220525151106.2176147-3-sunilvl@ventanamicro.com> (raw) In-Reply-To: <20220525151106.2176147-1-sunilvl@ventanamicro.com> The hartid can be a 64bit value on RV64 platforms. This patch modifies the hartid variable type to unsigned long so that it can hold 64bit value on RV64 platforms. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> --- arch/riscv/kernel/cpu_ops_spinwait.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpu_ops_spinwait.c b/arch/riscv/kernel/cpu_ops_spinwait.c index 346847f6c41c..51ac07514a62 100644 --- a/arch/riscv/kernel/cpu_ops_spinwait.c +++ b/arch/riscv/kernel/cpu_ops_spinwait.c @@ -18,7 +18,7 @@ void *__cpu_spinwait_task_pointer[NR_CPUS] __section(".data"); static void cpu_update_secondary_bootdata(unsigned int cpuid, struct task_struct *tidle) { - int hartid = cpuid_to_hartid_map(cpuid); + unsigned long hartid = cpuid_to_hartid_map(cpuid); /* * The hartid must be less than NR_CPUS to avoid out-of-bound access -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-05-25 15:11 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-25 15:11 [PATCH 0/5] Support for 64bit hartid on RV64 platforms Sunil V L 2022-05-25 15:11 ` Sunil V L 2022-05-25 15:11 ` [PATCH 1/5] riscv: cpu_ops_sbi: Support for 64bit hartid Sunil V L 2022-05-25 15:11 ` Sunil V L 2022-05-25 15:17 ` Heinrich Schuchardt 2022-05-25 15:17 ` Heinrich Schuchardt 2022-05-25 15:11 ` Sunil V L [this message] 2022-05-25 15:11 ` [PATCH 2/5] riscv: cpu_ops_spinwait: " Sunil V L 2022-05-25 15:27 ` Heinrich Schuchardt 2022-05-25 15:27 ` Heinrich Schuchardt 2022-05-26 10:15 ` Sunil V L 2022-05-26 10:15 ` Sunil V L 2022-05-25 15:11 ` [PATCH 3/5] riscv: smp: " Sunil V L 2022-05-25 15:11 ` Sunil V L 2022-05-25 15:58 ` Heinrich Schuchardt 2022-05-25 15:58 ` Heinrich Schuchardt 2022-05-25 15:11 ` [PATCH 4/5] riscv: cpu: " Sunil V L 2022-05-25 15:11 ` Sunil V L 2022-05-25 15:11 ` [PATCH 5/5] riscv/efi_stub: Support for 64bit boot-hartid Sunil V L 2022-05-25 15:11 ` Sunil V L 2022-05-25 15:48 ` Ard Biesheuvel 2022-05-25 15:48 ` Ard Biesheuvel 2022-05-25 16:09 ` Heinrich Schuchardt 2022-05-25 16:09 ` Heinrich Schuchardt 2022-05-25 23:11 ` Atish Patra 2022-05-25 23:11 ` Atish Patra 2022-05-25 23:36 ` Jessica Clarke 2022-05-25 23:36 ` Jessica Clarke 2022-05-25 23:49 ` Atish Patra 2022-05-25 23:49 ` Atish Patra 2022-05-26 0:06 ` Jessica Clarke 2022-05-26 0:06 ` Jessica Clarke 2022-05-26 10:13 ` Sunil V L 2022-05-26 10:13 ` Sunil V L
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