From: Pavel Machek <pavel@ucw.cz>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: a.zummo@towertech.it, alexandre.belloni@bootlin.com,
daire.mcnamara@microchip.com, lewis.hanly@microchip.com,
linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 1/2] rtc: Add driver for Microchip PolarFire SoC
Date: Mon, 30 May 2022 09:07:28 +0200 [thread overview]
Message-ID: <20220530070728.GH1363@bug> (raw)
In-Reply-To: <20220516082838.3717982-2-conor.dooley@microchip.com>
Hi!
> Add support for the built-in RTC on Microchip PolarFire SoC
> +#define CONTROL_UPLOAD_BIT BIT(5)
> +#define CONTROL_DOWNLOAD_BIT BIT(6)
> +#define CONTROL_DOWNLOAD_BIT BIT(6)
> +#define CONTROL_WAKEUP_CLR_BIT BIT(8)
Dup?
> +static void mpfs_rtc_start(struct mpfs_rtc_dev *rtcdev)
> +{
> + u32 ctrl;
> +
> + ctrl = readl(rtcdev->base + CONTROL_REG);
> + ctrl &= ~(CONTROL_STOP_BIT | CONTROL_START_BIT);
> + ctrl |= CONTROL_START_BIT;
> + writel(ctrl, rtcdev->base + CONTROL_REG);
> +}
You don't need to clear bit just to set it.
> + do {
> + prog = readl(rtcdev->base + CONTROL_REG);
> + prog &= CONTROL_UPLOAD_BIT;
> + } while (prog);
Limit to XY iterations?
> +
> +static int mpfs_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
> +{
> + u32 mode = readl(rtcdev->base + MODE_REG);
> + u64 time;
> +
> + mode = readl(rtcdev->base + MODE_REG);
Dup?
> + if (mode & MODE_WAKE_EN) + alrm->enabled = true; + else + alrm->enabled = false; +
enabled = ()?
Best regards,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
WARNING: multiple messages have this Message-ID (diff)
From: Pavel Machek <pavel@ucw.cz>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: a.zummo@towertech.it, alexandre.belloni@bootlin.com,
daire.mcnamara@microchip.com, lewis.hanly@microchip.com,
linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 1/2] rtc: Add driver for Microchip PolarFire SoC
Date: Mon, 30 May 2022 09:07:28 +0200 [thread overview]
Message-ID: <20220530070728.GH1363@bug> (raw)
In-Reply-To: <20220516082838.3717982-2-conor.dooley@microchip.com>
Hi!
> Add support for the built-in RTC on Microchip PolarFire SoC
> +#define CONTROL_UPLOAD_BIT BIT(5)
> +#define CONTROL_DOWNLOAD_BIT BIT(6)
> +#define CONTROL_DOWNLOAD_BIT BIT(6)
> +#define CONTROL_WAKEUP_CLR_BIT BIT(8)
Dup?
> +static void mpfs_rtc_start(struct mpfs_rtc_dev *rtcdev)
> +{
> + u32 ctrl;
> +
> + ctrl = readl(rtcdev->base + CONTROL_REG);
> + ctrl &= ~(CONTROL_STOP_BIT | CONTROL_START_BIT);
> + ctrl |= CONTROL_START_BIT;
> + writel(ctrl, rtcdev->base + CONTROL_REG);
> +}
You don't need to clear bit just to set it.
> + do {
> + prog = readl(rtcdev->base + CONTROL_REG);
> + prog &= CONTROL_UPLOAD_BIT;
> + } while (prog);
Limit to XY iterations?
> +
> +static int mpfs_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
> +{
> + u32 mode = readl(rtcdev->base + MODE_REG);
> + u64 time;
> +
> + mode = readl(rtcdev->base + MODE_REG);
Dup?
> + if (mode & MODE_WAKE_EN) + alrm->enabled = true; + else + alrm->enabled = false; +
enabled = ()?
Best regards,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-05-30 7:07 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-16 8:28 [PATCH v3 0/2] rtc: microchip: Add driver for PolarFire SoC Conor Dooley
2022-05-16 8:28 ` Conor Dooley
2022-05-16 8:28 ` [PATCH v3 1/2] rtc: Add driver for Microchip " Conor Dooley
2022-05-16 8:28 ` Conor Dooley
2022-05-17 21:09 ` Alexandre Belloni
2022-05-17 21:09 ` Alexandre Belloni
2022-05-17 21:37 ` Conor.Dooley
2022-05-17 21:37 ` Conor.Dooley
2022-05-30 7:07 ` Pavel Machek [this message]
2022-05-30 7:07 ` Pavel Machek
2022-05-30 13:27 ` Geert Uytterhoeven
2022-05-30 13:27 ` Geert Uytterhoeven
2022-05-16 8:28 ` [PATCH v3 2/2] MAINTAINERS: add PolarFire SoC's RTC Conor Dooley
2022-05-16 8:28 ` Conor Dooley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220530070728.GH1363@bug \
--to=pavel@ucw.cz \
--cc=a.zummo@towertech.it \
--cc=alexandre.belloni@bootlin.com \
--cc=conor.dooley@microchip.com \
--cc=daire.mcnamara@microchip.com \
--cc=lewis.hanly@microchip.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=linux-rtc@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.