* [PATCH v3 0/2] rtc: microchip: Add driver for PolarFire SoC
@ 2022-05-16 8:28 ` Conor Dooley
0 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-05-16 8:28 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: daire.mcnamara, lewis.hanly, conor.dooley, linux-kernel,
linux-rtc, linux-riscv
Hey all,
This is technically a v3 of [0], although a fair bit of time has
passed since then. In the meantime I upstreamed the dt-binding, which
was in the v1, and this patch depends on the fixes to the dt-binding
and device tree etc which landed in v5.18-rc5.
The driver is quite substantially rewritten from the v1, as you wanted
it to be switched to "binary" rather than calendar mode - so hopefully I
have satisfied your concerns with the original driver. Specifically you
had an significant issue with the counter being reset on startup & that
is no longer the case.
Thanks,
Conor.
Changes from v2:
- move prescaler out of mpfs_rtc_dev & into probe
Changes from v1:
- remove duplicate and unused defines
- remove oneline mpfs_rtc_set_prescaler function
- dont unconditionally turn off the rtc in the init function
- dont reset the rtc when init is run.
- dont disable the alarm when we boot
- use binary, not calendar mode
- delete mpfs_rtc_init & set prescale in probe
- use dev_pm_set_wake_irq rather than writing suspend/resume functions
- delete calendar mode only register defines
- since using binary mode, set range min to zero
- set range max to max alarm value (is this acceptable?)
- added a MAINTAINERS entry: when v1 was submitted there was nothing to
add to, but there is now.
[0] https://lore.kernel.org/linux-rtc/20210512111133.1650740-1-daire.mcnamara@microchip.com/
Conor Dooley (2):
rtc: Add driver for Microchip PolarFire SoC
MAINTAINERS: add PolarFire SoC's RTC
MAINTAINERS | 1 +
drivers/rtc/Kconfig | 10 ++
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-mpfs.c | 328 +++++++++++++++++++++++++++++++++++++++++
4 files changed, 340 insertions(+)
create mode 100644 drivers/rtc/rtc-mpfs.c
--
2.36.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 0/2] rtc: microchip: Add driver for PolarFire SoC
@ 2022-05-16 8:28 ` Conor Dooley
0 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-05-16 8:28 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: daire.mcnamara, lewis.hanly, conor.dooley, linux-kernel,
linux-rtc, linux-riscv
Hey all,
This is technically a v3 of [0], although a fair bit of time has
passed since then. In the meantime I upstreamed the dt-binding, which
was in the v1, and this patch depends on the fixes to the dt-binding
and device tree etc which landed in v5.18-rc5.
The driver is quite substantially rewritten from the v1, as you wanted
it to be switched to "binary" rather than calendar mode - so hopefully I
have satisfied your concerns with the original driver. Specifically you
had an significant issue with the counter being reset on startup & that
is no longer the case.
Thanks,
Conor.
Changes from v2:
- move prescaler out of mpfs_rtc_dev & into probe
Changes from v1:
- remove duplicate and unused defines
- remove oneline mpfs_rtc_set_prescaler function
- dont unconditionally turn off the rtc in the init function
- dont reset the rtc when init is run.
- dont disable the alarm when we boot
- use binary, not calendar mode
- delete mpfs_rtc_init & set prescale in probe
- use dev_pm_set_wake_irq rather than writing suspend/resume functions
- delete calendar mode only register defines
- since using binary mode, set range min to zero
- set range max to max alarm value (is this acceptable?)
- added a MAINTAINERS entry: when v1 was submitted there was nothing to
add to, but there is now.
[0] https://lore.kernel.org/linux-rtc/20210512111133.1650740-1-daire.mcnamara@microchip.com/
Conor Dooley (2):
rtc: Add driver for Microchip PolarFire SoC
MAINTAINERS: add PolarFire SoC's RTC
MAINTAINERS | 1 +
drivers/rtc/Kconfig | 10 ++
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-mpfs.c | 328 +++++++++++++++++++++++++++++++++++++++++
4 files changed, 340 insertions(+)
create mode 100644 drivers/rtc/rtc-mpfs.c
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 1/2] rtc: Add driver for Microchip PolarFire SoC
2022-05-16 8:28 ` Conor Dooley
@ 2022-05-16 8:28 ` Conor Dooley
-1 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-05-16 8:28 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: daire.mcnamara, lewis.hanly, conor.dooley, linux-kernel,
linux-rtc, linux-riscv
Add support for the built-in RTC on Microchip PolarFire SoC
Co-Developed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/rtc/Kconfig | 10 ++
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-mpfs.c | 328 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 339 insertions(+)
create mode 100644 drivers/rtc/rtc-mpfs.c
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 41c65b4d2baf..a194422328da 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1966,4 +1966,14 @@ config RTC_DRV_MSC313
This driver can also be built as a module, if so, the module
will be called "rtc-msc313".
+config RTC_DRV_POLARFIRE_SOC
+ tristate "Microchip PolarFire SoC built-in RTC"
+ depends on SOC_MICROCHIP_POLARFIRE
+ help
+ If you say yes here you will get support for the
+ built-in RTC on Polarfire SoC.
+
+ This driver can also be built as a module, if so, the module
+ will be called "rtc-mpfs".
+
endif # RTC_CLASS
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 2d827d8261d5..25ee5ba870a9 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -130,6 +130,7 @@ obj-$(CONFIG_RTC_DRV_PIC32) += rtc-pic32.o
obj-$(CONFIG_RTC_DRV_PL030) += rtc-pl030.o
obj-$(CONFIG_RTC_DRV_PL031) += rtc-pl031.o
obj-$(CONFIG_RTC_DRV_PM8XXX) += rtc-pm8xxx.o
+obj-$(CONFIG_RTC_DRV_POLARFIRE_SOC) += rtc-mpfs.o
obj-$(CONFIG_RTC_DRV_PS3) += rtc-ps3.o
obj-$(CONFIG_RTC_DRV_PXA) += rtc-pxa.o
obj-$(CONFIG_RTC_DRV_R7301) += rtc-r7301.o
diff --git a/drivers/rtc/rtc-mpfs.c b/drivers/rtc/rtc-mpfs.c
new file mode 100644
index 000000000000..614a1d6b44c7
--- /dev/null
+++ b/drivers/rtc/rtc-mpfs.c
@@ -0,0 +1,328 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Microchip MPFS RTC driver
+ *
+ * Copyright (c) 2021-2022 Microchip Corporation. All rights reserved.
+ *
+ * Author: Daire McNamara <daire.mcnamara@microchip.com>
+ * & Conor Dooley <conor.dooley@microchip.com>
+ */
+#include "linux/bits.h"
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_wakeirq.h>
+#include <linux/slab.h>
+#include <linux/rtc.h>
+
+#define CONTROL_REG 0x00
+#define MODE_REG 0x04
+#define PRESCALER_REG 0x08
+#define ALARM_LOWER_REG 0x0c
+#define ALARM_UPPER_REG 0x10
+#define COMPARE_LOWER_REG 0x14
+#define COMPARE_UPPER_REG 0x18
+#define DATETIME_LOWER_REG 0x20
+#define DATETIME_UPPER_REG 0x24
+
+#define CONTROL_RUNNING_BIT BIT(0)
+#define CONTROL_START_BIT BIT(0)
+#define CONTROL_STOP_BIT BIT(1)
+#define CONTROL_ALARM_ON_BIT BIT(2)
+#define CONTROL_ALARM_OFF_BIT BIT(3)
+#define CONTROL_RESET_BIT BIT(4)
+#define CONTROL_UPLOAD_BIT BIT(5)
+#define CONTROL_DOWNLOAD_BIT BIT(6)
+#define CONTROL_DOWNLOAD_BIT BIT(6)
+#define CONTROL_WAKEUP_CLR_BIT BIT(8)
+#define CONTROL_WAKEUP_SET_BIT BIT(9)
+#define CONTROL_UPDATED_BIT BIT(10)
+
+#define MODE_CLOCK_CALENDAR BIT(0)
+#define MODE_WAKE_EN BIT(1)
+#define MODE_WAKE_RESET BIT(2)
+#define MODE_WAKE_CONTINUE BIT(3)
+
+#define MAX_PRESCALER_COUNT GENMASK(25, 0)
+#define DATETIME_UPPER_MASK GENMASK(29, 0)
+#define ALARM_UPPER_MASK GENMASK(10, 0)
+
+struct mpfs_rtc_dev {
+ struct rtc_device *rtc;
+ void __iomem *base;
+ int wakeup_irq;
+};
+
+static void mpfs_rtc_start(struct mpfs_rtc_dev *rtcdev)
+{
+ u32 ctrl;
+
+ ctrl = readl(rtcdev->base + CONTROL_REG);
+ ctrl &= ~(CONTROL_STOP_BIT | CONTROL_START_BIT);
+ ctrl |= CONTROL_START_BIT;
+ writel(ctrl, rtcdev->base + CONTROL_REG);
+}
+
+static void mpfs_rtc_clear_irq(struct mpfs_rtc_dev *rtcdev)
+{
+ u32 val = readl(rtcdev->base + CONTROL_REG);
+
+ val &= ~(CONTROL_ALARM_ON_BIT | CONTROL_STOP_BIT);
+ val |= CONTROL_ALARM_OFF_BIT;
+ writel(val, rtcdev->base + CONTROL_REG);
+ /*
+ * Ensure that the posted write to the CONTROL_REG register completed before
+ * returning from this function. Not doing this may result in the interrupt
+ * only being cleared some time after this function returns.
+ */
+ (void)readl(rtcdev->base + CONTROL_REG);
+}
+
+static int mpfs_rtc_readtime(struct device *dev, struct rtc_time *tm)
+{
+ struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
+ u64 time;
+
+ time = ((u64)readl(rtcdev->base + DATETIME_UPPER_REG) & DATETIME_UPPER_MASK) << 32;
+ time |= readl(rtcdev->base + DATETIME_LOWER_REG);
+ rtc_time64_to_tm(time + rtcdev->rtc->range_min, tm);
+
+ return 0;
+}
+
+static int mpfs_rtc_settime(struct device *dev, struct rtc_time *tm)
+{
+ struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
+ u32 ctrl, prog;
+ u64 time;
+
+ time = rtc_tm_to_time64(tm) - rtcdev->rtc->range_min;
+
+ writel((u32)time, rtcdev->base + DATETIME_LOWER_REG);
+ writel((u32)(time >> 32) & DATETIME_UPPER_MASK, rtcdev->base + DATETIME_UPPER_REG);
+
+ ctrl = readl(rtcdev->base + CONTROL_REG);
+ ctrl &= ~CONTROL_STOP_BIT;
+ ctrl |= CONTROL_UPLOAD_BIT;
+ writel(ctrl, rtcdev->base + CONTROL_REG);
+
+ do {
+ prog = readl(rtcdev->base + CONTROL_REG);
+ prog &= CONTROL_UPLOAD_BIT;
+ } while (prog);
+
+ mpfs_rtc_start(rtcdev);
+
+ return 0;
+}
+
+static int mpfs_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
+ u32 mode = readl(rtcdev->base + MODE_REG);
+ u64 time;
+
+ mode = readl(rtcdev->base + MODE_REG);
+
+ if (mode & MODE_WAKE_EN)
+ alrm->enabled = true;
+ else
+ alrm->enabled = false;
+
+ time = (u64)readl(rtcdev->base + ALARM_LOWER_REG) << 32;
+ time |= (readl(rtcdev->base + ALARM_UPPER_REG) & ALARM_UPPER_MASK);
+ rtc_time64_to_tm(time + rtcdev->rtc->range_min, &alrm->time);
+
+ return 0;
+}
+
+static int mpfs_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
+ u32 mode, ctrl;
+ u64 time;
+
+ /* Disable the alarm before updating */
+ ctrl = readl(rtcdev->base + CONTROL_REG);
+ ctrl |= CONTROL_ALARM_OFF_BIT;
+ writel(ctrl, rtcdev->base + CONTROL_REG);
+
+ time = rtc_tm_to_time64(&alrm->time) - rtcdev->rtc->range_min;
+
+ writel((u32)time, rtcdev->base + ALARM_LOWER_REG);
+ writel((u32)(time >> 32) & ALARM_UPPER_MASK, rtcdev->base + ALARM_UPPER_REG);
+
+ /* Bypass compare register in alarm mode */
+ writel(GENMASK(31, 0), rtcdev->base + COMPARE_LOWER_REG);
+ writel(GENMASK(29, 0), rtcdev->base + COMPARE_UPPER_REG);
+
+ /* Configure the RTC to enable the alarm. */
+ ctrl = readl(rtcdev->base + CONTROL_REG);
+ mode = readl(rtcdev->base + MODE_REG);
+ if (alrm->enabled) {
+ mode = MODE_WAKE_EN | MODE_WAKE_CONTINUE;
+ /* Enable the alarm */
+ ctrl &= ~CONTROL_ALARM_OFF_BIT;
+ ctrl |= CONTROL_ALARM_ON_BIT;
+ }
+ ctrl &= ~CONTROL_STOP_BIT;
+ ctrl |= CONTROL_START_BIT;
+ writel(ctrl, rtcdev->base + CONTROL_REG);
+ writel(mode, rtcdev->base + MODE_REG);
+
+ return 0;
+}
+
+static int mpfs_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
+{
+ struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
+ u32 ctrl;
+
+ ctrl = readl(rtcdev->base + CONTROL_REG);
+ ctrl &= ~(CONTROL_ALARM_ON_BIT | CONTROL_ALARM_OFF_BIT | CONTROL_STOP_BIT);
+
+ if (enabled)
+ ctrl |= CONTROL_ALARM_ON_BIT;
+ else
+ ctrl |= CONTROL_ALARM_OFF_BIT;
+
+ writel(ctrl, rtcdev->base + CONTROL_REG);
+
+ return 0;
+}
+
+static inline struct clk *mpfs_rtc_init_clk(struct device *dev)
+{
+ struct clk *clk;
+ int ret;
+
+ clk = devm_clk_get(dev, "rtc");
+ if (IS_ERR(clk))
+ return clk;
+
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ return ERR_PTR(ret);
+
+ devm_add_action_or_reset(dev, (void (*) (void *))clk_disable_unprepare, clk);
+ return clk;
+}
+
+static irqreturn_t mpfs_rtc_wakeup_irq_handler(int irq, void *d)
+{
+ struct mpfs_rtc_dev *rtcdev = d;
+ unsigned long pending;
+
+ pending = readl(rtcdev->base + CONTROL_REG);
+ pending &= CONTROL_ALARM_ON_BIT;
+ mpfs_rtc_clear_irq(rtcdev);
+
+ rtc_update_irq(rtcdev->rtc, 1, RTC_IRQF | RTC_AF);
+
+ return IRQ_HANDLED;
+}
+
+static const struct rtc_class_ops mpfs_rtc_ops = {
+ .read_time = mpfs_rtc_readtime,
+ .set_time = mpfs_rtc_settime,
+ .read_alarm = mpfs_rtc_readalarm,
+ .set_alarm = mpfs_rtc_setalarm,
+ .alarm_irq_enable = mpfs_rtc_alarm_irq_enable,
+};
+
+static int mpfs_rtc_probe(struct platform_device *pdev)
+{
+ struct mpfs_rtc_dev *rtcdev;
+ struct clk *clk;
+ u32 prescaler;
+ int ret;
+
+ rtcdev = devm_kzalloc(&pdev->dev, sizeof(struct mpfs_rtc_dev), GFP_KERNEL);
+ if (!rtcdev)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, rtcdev);
+
+ rtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
+ if (IS_ERR(rtcdev->rtc))
+ return PTR_ERR(rtcdev->rtc);
+
+ rtcdev->rtc->ops = &mpfs_rtc_ops;
+
+ /* range is capped by alarm max, lower reg is 31:0 & upper is 10:0 */
+ rtcdev->rtc->range_max = GENMASK_ULL(42, 0);
+
+ clk = mpfs_rtc_init_clk(&pdev->dev);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ rtcdev->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(rtcdev->base)) {
+ dev_dbg(&pdev->dev, "invalid ioremap resources\n");
+ return PTR_ERR(rtcdev->base);
+ }
+
+ rtcdev->wakeup_irq = platform_get_irq(pdev, 0);
+ if (rtcdev->wakeup_irq <= 0) {
+ dev_dbg(&pdev->dev, "could not get wakeup irq\n");
+ return rtcdev->wakeup_irq;
+ }
+ ret = devm_request_irq(&pdev->dev, rtcdev->wakeup_irq, mpfs_rtc_wakeup_irq_handler, 0,
+ dev_name(&pdev->dev), rtcdev);
+ if (ret) {
+ dev_dbg(&pdev->dev, "could not request wakeup irq\n");
+ return ret;
+ }
+
+ /* prescaler hardware adds 1 to reg value */
+ prescaler = clk_get_rate(devm_clk_get(&pdev->dev, "rtcref")) - 1;
+
+ if (prescaler > MAX_PRESCALER_COUNT) {
+ dev_dbg(&pdev->dev, "invalid prescaler %d\n", prescaler);
+ return -EINVAL;
+ }
+
+ writel(prescaler, rtcdev->base + PRESCALER_REG);
+ dev_info(&pdev->dev, "prescaler set to: 0x%X \r\n", prescaler);
+
+ device_init_wakeup(&pdev->dev, true);
+ ret = dev_pm_set_wake_irq(&pdev->dev, rtcdev->wakeup_irq);
+ if (ret)
+ dev_err(&pdev->dev, "failed to enable irq wake\n");
+
+ return devm_rtc_register_device(rtcdev->rtc);
+}
+
+static int mpfs_rtc_remove(struct platform_device *pdev)
+{
+ mpfs_rtc_alarm_irq_enable(&pdev->dev, 0);
+ device_init_wakeup(&pdev->dev, 0);
+
+ return 0;
+}
+
+static const struct of_device_id mpfs_rtc_of_match[] = {
+ { .compatible = "microchip,mpfs-rtc" },
+ { }
+};
+
+MODULE_DEVICE_TABLE(of, mpfs_rtc_of_match);
+
+static struct platform_driver mpfs_rtc_driver = {
+ .probe = mpfs_rtc_probe,
+ .remove = mpfs_rtc_remove,
+ .driver = {
+ .name = "mpfs_rtc",
+ .of_match_table = mpfs_rtc_of_match,
+ },
+};
+
+module_platform_driver(mpfs_rtc_driver);
+
+MODULE_DESCRIPTION("Real time clock for Microchip Polarfire SoC");
+MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
+MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
+MODULE_LICENSE("GPL");
--
2.36.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v3 1/2] rtc: Add driver for Microchip PolarFire SoC
@ 2022-05-16 8:28 ` Conor Dooley
0 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-05-16 8:28 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: daire.mcnamara, lewis.hanly, conor.dooley, linux-kernel,
linux-rtc, linux-riscv
Add support for the built-in RTC on Microchip PolarFire SoC
Co-Developed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/rtc/Kconfig | 10 ++
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-mpfs.c | 328 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 339 insertions(+)
create mode 100644 drivers/rtc/rtc-mpfs.c
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 41c65b4d2baf..a194422328da 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1966,4 +1966,14 @@ config RTC_DRV_MSC313
This driver can also be built as a module, if so, the module
will be called "rtc-msc313".
+config RTC_DRV_POLARFIRE_SOC
+ tristate "Microchip PolarFire SoC built-in RTC"
+ depends on SOC_MICROCHIP_POLARFIRE
+ help
+ If you say yes here you will get support for the
+ built-in RTC on Polarfire SoC.
+
+ This driver can also be built as a module, if so, the module
+ will be called "rtc-mpfs".
+
endif # RTC_CLASS
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 2d827d8261d5..25ee5ba870a9 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -130,6 +130,7 @@ obj-$(CONFIG_RTC_DRV_PIC32) += rtc-pic32.o
obj-$(CONFIG_RTC_DRV_PL030) += rtc-pl030.o
obj-$(CONFIG_RTC_DRV_PL031) += rtc-pl031.o
obj-$(CONFIG_RTC_DRV_PM8XXX) += rtc-pm8xxx.o
+obj-$(CONFIG_RTC_DRV_POLARFIRE_SOC) += rtc-mpfs.o
obj-$(CONFIG_RTC_DRV_PS3) += rtc-ps3.o
obj-$(CONFIG_RTC_DRV_PXA) += rtc-pxa.o
obj-$(CONFIG_RTC_DRV_R7301) += rtc-r7301.o
diff --git a/drivers/rtc/rtc-mpfs.c b/drivers/rtc/rtc-mpfs.c
new file mode 100644
index 000000000000..614a1d6b44c7
--- /dev/null
+++ b/drivers/rtc/rtc-mpfs.c
@@ -0,0 +1,328 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Microchip MPFS RTC driver
+ *
+ * Copyright (c) 2021-2022 Microchip Corporation. All rights reserved.
+ *
+ * Author: Daire McNamara <daire.mcnamara@microchip.com>
+ * & Conor Dooley <conor.dooley@microchip.com>
+ */
+#include "linux/bits.h"
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_wakeirq.h>
+#include <linux/slab.h>
+#include <linux/rtc.h>
+
+#define CONTROL_REG 0x00
+#define MODE_REG 0x04
+#define PRESCALER_REG 0x08
+#define ALARM_LOWER_REG 0x0c
+#define ALARM_UPPER_REG 0x10
+#define COMPARE_LOWER_REG 0x14
+#define COMPARE_UPPER_REG 0x18
+#define DATETIME_LOWER_REG 0x20
+#define DATETIME_UPPER_REG 0x24
+
+#define CONTROL_RUNNING_BIT BIT(0)
+#define CONTROL_START_BIT BIT(0)
+#define CONTROL_STOP_BIT BIT(1)
+#define CONTROL_ALARM_ON_BIT BIT(2)
+#define CONTROL_ALARM_OFF_BIT BIT(3)
+#define CONTROL_RESET_BIT BIT(4)
+#define CONTROL_UPLOAD_BIT BIT(5)
+#define CONTROL_DOWNLOAD_BIT BIT(6)
+#define CONTROL_DOWNLOAD_BIT BIT(6)
+#define CONTROL_WAKEUP_CLR_BIT BIT(8)
+#define CONTROL_WAKEUP_SET_BIT BIT(9)
+#define CONTROL_UPDATED_BIT BIT(10)
+
+#define MODE_CLOCK_CALENDAR BIT(0)
+#define MODE_WAKE_EN BIT(1)
+#define MODE_WAKE_RESET BIT(2)
+#define MODE_WAKE_CONTINUE BIT(3)
+
+#define MAX_PRESCALER_COUNT GENMASK(25, 0)
+#define DATETIME_UPPER_MASK GENMASK(29, 0)
+#define ALARM_UPPER_MASK GENMASK(10, 0)
+
+struct mpfs_rtc_dev {
+ struct rtc_device *rtc;
+ void __iomem *base;
+ int wakeup_irq;
+};
+
+static void mpfs_rtc_start(struct mpfs_rtc_dev *rtcdev)
+{
+ u32 ctrl;
+
+ ctrl = readl(rtcdev->base + CONTROL_REG);
+ ctrl &= ~(CONTROL_STOP_BIT | CONTROL_START_BIT);
+ ctrl |= CONTROL_START_BIT;
+ writel(ctrl, rtcdev->base + CONTROL_REG);
+}
+
+static void mpfs_rtc_clear_irq(struct mpfs_rtc_dev *rtcdev)
+{
+ u32 val = readl(rtcdev->base + CONTROL_REG);
+
+ val &= ~(CONTROL_ALARM_ON_BIT | CONTROL_STOP_BIT);
+ val |= CONTROL_ALARM_OFF_BIT;
+ writel(val, rtcdev->base + CONTROL_REG);
+ /*
+ * Ensure that the posted write to the CONTROL_REG register completed before
+ * returning from this function. Not doing this may result in the interrupt
+ * only being cleared some time after this function returns.
+ */
+ (void)readl(rtcdev->base + CONTROL_REG);
+}
+
+static int mpfs_rtc_readtime(struct device *dev, struct rtc_time *tm)
+{
+ struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
+ u64 time;
+
+ time = ((u64)readl(rtcdev->base + DATETIME_UPPER_REG) & DATETIME_UPPER_MASK) << 32;
+ time |= readl(rtcdev->base + DATETIME_LOWER_REG);
+ rtc_time64_to_tm(time + rtcdev->rtc->range_min, tm);
+
+ return 0;
+}
+
+static int mpfs_rtc_settime(struct device *dev, struct rtc_time *tm)
+{
+ struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
+ u32 ctrl, prog;
+ u64 time;
+
+ time = rtc_tm_to_time64(tm) - rtcdev->rtc->range_min;
+
+ writel((u32)time, rtcdev->base + DATETIME_LOWER_REG);
+ writel((u32)(time >> 32) & DATETIME_UPPER_MASK, rtcdev->base + DATETIME_UPPER_REG);
+
+ ctrl = readl(rtcdev->base + CONTROL_REG);
+ ctrl &= ~CONTROL_STOP_BIT;
+ ctrl |= CONTROL_UPLOAD_BIT;
+ writel(ctrl, rtcdev->base + CONTROL_REG);
+
+ do {
+ prog = readl(rtcdev->base + CONTROL_REG);
+ prog &= CONTROL_UPLOAD_BIT;
+ } while (prog);
+
+ mpfs_rtc_start(rtcdev);
+
+ return 0;
+}
+
+static int mpfs_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
+ u32 mode = readl(rtcdev->base + MODE_REG);
+ u64 time;
+
+ mode = readl(rtcdev->base + MODE_REG);
+
+ if (mode & MODE_WAKE_EN)
+ alrm->enabled = true;
+ else
+ alrm->enabled = false;
+
+ time = (u64)readl(rtcdev->base + ALARM_LOWER_REG) << 32;
+ time |= (readl(rtcdev->base + ALARM_UPPER_REG) & ALARM_UPPER_MASK);
+ rtc_time64_to_tm(time + rtcdev->rtc->range_min, &alrm->time);
+
+ return 0;
+}
+
+static int mpfs_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
+ u32 mode, ctrl;
+ u64 time;
+
+ /* Disable the alarm before updating */
+ ctrl = readl(rtcdev->base + CONTROL_REG);
+ ctrl |= CONTROL_ALARM_OFF_BIT;
+ writel(ctrl, rtcdev->base + CONTROL_REG);
+
+ time = rtc_tm_to_time64(&alrm->time) - rtcdev->rtc->range_min;
+
+ writel((u32)time, rtcdev->base + ALARM_LOWER_REG);
+ writel((u32)(time >> 32) & ALARM_UPPER_MASK, rtcdev->base + ALARM_UPPER_REG);
+
+ /* Bypass compare register in alarm mode */
+ writel(GENMASK(31, 0), rtcdev->base + COMPARE_LOWER_REG);
+ writel(GENMASK(29, 0), rtcdev->base + COMPARE_UPPER_REG);
+
+ /* Configure the RTC to enable the alarm. */
+ ctrl = readl(rtcdev->base + CONTROL_REG);
+ mode = readl(rtcdev->base + MODE_REG);
+ if (alrm->enabled) {
+ mode = MODE_WAKE_EN | MODE_WAKE_CONTINUE;
+ /* Enable the alarm */
+ ctrl &= ~CONTROL_ALARM_OFF_BIT;
+ ctrl |= CONTROL_ALARM_ON_BIT;
+ }
+ ctrl &= ~CONTROL_STOP_BIT;
+ ctrl |= CONTROL_START_BIT;
+ writel(ctrl, rtcdev->base + CONTROL_REG);
+ writel(mode, rtcdev->base + MODE_REG);
+
+ return 0;
+}
+
+static int mpfs_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
+{
+ struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
+ u32 ctrl;
+
+ ctrl = readl(rtcdev->base + CONTROL_REG);
+ ctrl &= ~(CONTROL_ALARM_ON_BIT | CONTROL_ALARM_OFF_BIT | CONTROL_STOP_BIT);
+
+ if (enabled)
+ ctrl |= CONTROL_ALARM_ON_BIT;
+ else
+ ctrl |= CONTROL_ALARM_OFF_BIT;
+
+ writel(ctrl, rtcdev->base + CONTROL_REG);
+
+ return 0;
+}
+
+static inline struct clk *mpfs_rtc_init_clk(struct device *dev)
+{
+ struct clk *clk;
+ int ret;
+
+ clk = devm_clk_get(dev, "rtc");
+ if (IS_ERR(clk))
+ return clk;
+
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ return ERR_PTR(ret);
+
+ devm_add_action_or_reset(dev, (void (*) (void *))clk_disable_unprepare, clk);
+ return clk;
+}
+
+static irqreturn_t mpfs_rtc_wakeup_irq_handler(int irq, void *d)
+{
+ struct mpfs_rtc_dev *rtcdev = d;
+ unsigned long pending;
+
+ pending = readl(rtcdev->base + CONTROL_REG);
+ pending &= CONTROL_ALARM_ON_BIT;
+ mpfs_rtc_clear_irq(rtcdev);
+
+ rtc_update_irq(rtcdev->rtc, 1, RTC_IRQF | RTC_AF);
+
+ return IRQ_HANDLED;
+}
+
+static const struct rtc_class_ops mpfs_rtc_ops = {
+ .read_time = mpfs_rtc_readtime,
+ .set_time = mpfs_rtc_settime,
+ .read_alarm = mpfs_rtc_readalarm,
+ .set_alarm = mpfs_rtc_setalarm,
+ .alarm_irq_enable = mpfs_rtc_alarm_irq_enable,
+};
+
+static int mpfs_rtc_probe(struct platform_device *pdev)
+{
+ struct mpfs_rtc_dev *rtcdev;
+ struct clk *clk;
+ u32 prescaler;
+ int ret;
+
+ rtcdev = devm_kzalloc(&pdev->dev, sizeof(struct mpfs_rtc_dev), GFP_KERNEL);
+ if (!rtcdev)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, rtcdev);
+
+ rtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
+ if (IS_ERR(rtcdev->rtc))
+ return PTR_ERR(rtcdev->rtc);
+
+ rtcdev->rtc->ops = &mpfs_rtc_ops;
+
+ /* range is capped by alarm max, lower reg is 31:0 & upper is 10:0 */
+ rtcdev->rtc->range_max = GENMASK_ULL(42, 0);
+
+ clk = mpfs_rtc_init_clk(&pdev->dev);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ rtcdev->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(rtcdev->base)) {
+ dev_dbg(&pdev->dev, "invalid ioremap resources\n");
+ return PTR_ERR(rtcdev->base);
+ }
+
+ rtcdev->wakeup_irq = platform_get_irq(pdev, 0);
+ if (rtcdev->wakeup_irq <= 0) {
+ dev_dbg(&pdev->dev, "could not get wakeup irq\n");
+ return rtcdev->wakeup_irq;
+ }
+ ret = devm_request_irq(&pdev->dev, rtcdev->wakeup_irq, mpfs_rtc_wakeup_irq_handler, 0,
+ dev_name(&pdev->dev), rtcdev);
+ if (ret) {
+ dev_dbg(&pdev->dev, "could not request wakeup irq\n");
+ return ret;
+ }
+
+ /* prescaler hardware adds 1 to reg value */
+ prescaler = clk_get_rate(devm_clk_get(&pdev->dev, "rtcref")) - 1;
+
+ if (prescaler > MAX_PRESCALER_COUNT) {
+ dev_dbg(&pdev->dev, "invalid prescaler %d\n", prescaler);
+ return -EINVAL;
+ }
+
+ writel(prescaler, rtcdev->base + PRESCALER_REG);
+ dev_info(&pdev->dev, "prescaler set to: 0x%X \r\n", prescaler);
+
+ device_init_wakeup(&pdev->dev, true);
+ ret = dev_pm_set_wake_irq(&pdev->dev, rtcdev->wakeup_irq);
+ if (ret)
+ dev_err(&pdev->dev, "failed to enable irq wake\n");
+
+ return devm_rtc_register_device(rtcdev->rtc);
+}
+
+static int mpfs_rtc_remove(struct platform_device *pdev)
+{
+ mpfs_rtc_alarm_irq_enable(&pdev->dev, 0);
+ device_init_wakeup(&pdev->dev, 0);
+
+ return 0;
+}
+
+static const struct of_device_id mpfs_rtc_of_match[] = {
+ { .compatible = "microchip,mpfs-rtc" },
+ { }
+};
+
+MODULE_DEVICE_TABLE(of, mpfs_rtc_of_match);
+
+static struct platform_driver mpfs_rtc_driver = {
+ .probe = mpfs_rtc_probe,
+ .remove = mpfs_rtc_remove,
+ .driver = {
+ .name = "mpfs_rtc",
+ .of_match_table = mpfs_rtc_of_match,
+ },
+};
+
+module_platform_driver(mpfs_rtc_driver);
+
+MODULE_DESCRIPTION("Real time clock for Microchip Polarfire SoC");
+MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
+MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
+MODULE_LICENSE("GPL");
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v3 2/2] MAINTAINERS: add PolarFire SoC's RTC
2022-05-16 8:28 ` Conor Dooley
@ 2022-05-16 8:28 ` Conor Dooley
-1 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-05-16 8:28 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: daire.mcnamara, lewis.hanly, conor.dooley, linux-kernel,
linux-rtc, linux-riscv
Add an entry for PolarFire SoC's RTC drver to the existing support
for PolarFire SoC.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e8c52d0192a6..625d735f6a24 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16952,6 +16952,7 @@ L: linux-riscv@lists.infradead.org
S: Supported
F: arch/riscv/boot/dts/microchip/
F: drivers/mailbox/mailbox-mpfs.c
+F: drivers/rtc/rtc-mpfs.c
F: drivers/soc/microchip/
F: include/soc/microchip/mpfs.h
--
2.36.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v3 2/2] MAINTAINERS: add PolarFire SoC's RTC
@ 2022-05-16 8:28 ` Conor Dooley
0 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-05-16 8:28 UTC (permalink / raw)
To: a.zummo, alexandre.belloni
Cc: daire.mcnamara, lewis.hanly, conor.dooley, linux-kernel,
linux-rtc, linux-riscv
Add an entry for PolarFire SoC's RTC drver to the existing support
for PolarFire SoC.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e8c52d0192a6..625d735f6a24 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16952,6 +16952,7 @@ L: linux-riscv@lists.infradead.org
S: Supported
F: arch/riscv/boot/dts/microchip/
F: drivers/mailbox/mailbox-mpfs.c
+F: drivers/rtc/rtc-mpfs.c
F: drivers/soc/microchip/
F: include/soc/microchip/mpfs.h
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v3 1/2] rtc: Add driver for Microchip PolarFire SoC
2022-05-16 8:28 ` Conor Dooley
@ 2022-05-17 21:09 ` Alexandre Belloni
-1 siblings, 0 replies; 14+ messages in thread
From: Alexandre Belloni @ 2022-05-17 21:09 UTC (permalink / raw)
To: Conor Dooley
Cc: a.zummo, daire.mcnamara, lewis.hanly, linux-kernel, linux-rtc,
linux-riscv
Hello,
On 16/05/2022 09:28:38+0100, Conor Dooley wrote:
> +struct mpfs_rtc_dev {
> + struct rtc_device *rtc;
> + void __iomem *base;
> + int wakeup_irq;
I believe this is only used in .probe so you make it local to this
function.
> +};
> +
> +static int mpfs_rtc_readtime(struct device *dev, struct rtc_time *tm)
> +{
> + struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
> + u64 time;
> +
> + time = ((u64)readl(rtcdev->base + DATETIME_UPPER_REG) & DATETIME_UPPER_MASK) << 32;
> + time |= readl(rtcdev->base + DATETIME_LOWER_REG);
Are the registers properly latched on a DATETIME_UPPER_REG read?
> + rtc_time64_to_tm(time + rtcdev->rtc->range_min, tm);
range_min is never set so it will end up being 0. I guess you can avoid
a bunch of arithmetic in all the driver. Offsetting will happen in the
core which will probably never happen anyway because the max year is
141338. I guess we will all be gone by then ;)
> +
> + return 0;
> +}
> +
> +static int mpfs_rtc_probe(struct platform_device *pdev)
> +{
> + struct mpfs_rtc_dev *rtcdev;
> + struct clk *clk;
> + u32 prescaler;
> + int ret;
> +
> + rtcdev = devm_kzalloc(&pdev->dev, sizeof(struct mpfs_rtc_dev), GFP_KERNEL);
> + if (!rtcdev)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, rtcdev);
> +
> + rtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
> + if (IS_ERR(rtcdev->rtc))
> + return PTR_ERR(rtcdev->rtc);
> +
> + rtcdev->rtc->ops = &mpfs_rtc_ops;
> +
> + /* range is capped by alarm max, lower reg is 31:0 & upper is 10:0 */
> + rtcdev->rtc->range_max = GENMASK_ULL(42, 0);
> +
> + clk = mpfs_rtc_init_clk(&pdev->dev);
> + if (IS_ERR(clk))
> + return PTR_ERR(clk);
> +
> + rtcdev->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(rtcdev->base)) {
> + dev_dbg(&pdev->dev, "invalid ioremap resources\n");
> + return PTR_ERR(rtcdev->base);
> + }
> +
> + rtcdev->wakeup_irq = platform_get_irq(pdev, 0);
> + if (rtcdev->wakeup_irq <= 0) {
> + dev_dbg(&pdev->dev, "could not get wakeup irq\n");
> + return rtcdev->wakeup_irq;
> + }
> + ret = devm_request_irq(&pdev->dev, rtcdev->wakeup_irq, mpfs_rtc_wakeup_irq_handler, 0,
> + dev_name(&pdev->dev), rtcdev);
> + if (ret) {
> + dev_dbg(&pdev->dev, "could not request wakeup irq\n");
> + return ret;
> + }
> +
> + /* prescaler hardware adds 1 to reg value */
> + prescaler = clk_get_rate(devm_clk_get(&pdev->dev, "rtcref")) - 1;
> +
> + if (prescaler > MAX_PRESCALER_COUNT) {
> + dev_dbg(&pdev->dev, "invalid prescaler %d\n", prescaler);
> + return -EINVAL;
> + }
> +
> + writel(prescaler, rtcdev->base + PRESCALER_REG);
> + dev_info(&pdev->dev, "prescaler set to: 0x%X \r\n", prescaler);
> +
> + device_init_wakeup(&pdev->dev, true);
> + ret = dev_pm_set_wake_irq(&pdev->dev, rtcdev->wakeup_irq);
> + if (ret)
> + dev_err(&pdev->dev, "failed to enable irq wake\n");
> +
> + return devm_rtc_register_device(rtcdev->rtc);
> +}
> +
> +static int mpfs_rtc_remove(struct platform_device *pdev)
> +{
> + mpfs_rtc_alarm_irq_enable(&pdev->dev, 0);
This is not something you want to do if you want to wake up from
hibernate or any similar sleep state.
> + device_init_wakeup(&pdev->dev, 0);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id mpfs_rtc_of_match[] = {
> + { .compatible = "microchip,mpfs-rtc" },
> + { }
> +};
> +
> +MODULE_DEVICE_TABLE(of, mpfs_rtc_of_match);
> +
> +static struct platform_driver mpfs_rtc_driver = {
> + .probe = mpfs_rtc_probe,
> + .remove = mpfs_rtc_remove,
> + .driver = {
> + .name = "mpfs_rtc",
> + .of_match_table = mpfs_rtc_of_match,
> + },
> +};
> +
> +module_platform_driver(mpfs_rtc_driver);
> +
> +MODULE_DESCRIPTION("Real time clock for Microchip Polarfire SoC");
> +MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
> +MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
> +MODULE_LICENSE("GPL");
> --
> 2.36.1
>
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 1/2] rtc: Add driver for Microchip PolarFire SoC
@ 2022-05-17 21:09 ` Alexandre Belloni
0 siblings, 0 replies; 14+ messages in thread
From: Alexandre Belloni @ 2022-05-17 21:09 UTC (permalink / raw)
To: Conor Dooley
Cc: a.zummo, daire.mcnamara, lewis.hanly, linux-kernel, linux-rtc,
linux-riscv
Hello,
On 16/05/2022 09:28:38+0100, Conor Dooley wrote:
> +struct mpfs_rtc_dev {
> + struct rtc_device *rtc;
> + void __iomem *base;
> + int wakeup_irq;
I believe this is only used in .probe so you make it local to this
function.
> +};
> +
> +static int mpfs_rtc_readtime(struct device *dev, struct rtc_time *tm)
> +{
> + struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
> + u64 time;
> +
> + time = ((u64)readl(rtcdev->base + DATETIME_UPPER_REG) & DATETIME_UPPER_MASK) << 32;
> + time |= readl(rtcdev->base + DATETIME_LOWER_REG);
Are the registers properly latched on a DATETIME_UPPER_REG read?
> + rtc_time64_to_tm(time + rtcdev->rtc->range_min, tm);
range_min is never set so it will end up being 0. I guess you can avoid
a bunch of arithmetic in all the driver. Offsetting will happen in the
core which will probably never happen anyway because the max year is
141338. I guess we will all be gone by then ;)
> +
> + return 0;
> +}
> +
> +static int mpfs_rtc_probe(struct platform_device *pdev)
> +{
> + struct mpfs_rtc_dev *rtcdev;
> + struct clk *clk;
> + u32 prescaler;
> + int ret;
> +
> + rtcdev = devm_kzalloc(&pdev->dev, sizeof(struct mpfs_rtc_dev), GFP_KERNEL);
> + if (!rtcdev)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, rtcdev);
> +
> + rtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
> + if (IS_ERR(rtcdev->rtc))
> + return PTR_ERR(rtcdev->rtc);
> +
> + rtcdev->rtc->ops = &mpfs_rtc_ops;
> +
> + /* range is capped by alarm max, lower reg is 31:0 & upper is 10:0 */
> + rtcdev->rtc->range_max = GENMASK_ULL(42, 0);
> +
> + clk = mpfs_rtc_init_clk(&pdev->dev);
> + if (IS_ERR(clk))
> + return PTR_ERR(clk);
> +
> + rtcdev->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(rtcdev->base)) {
> + dev_dbg(&pdev->dev, "invalid ioremap resources\n");
> + return PTR_ERR(rtcdev->base);
> + }
> +
> + rtcdev->wakeup_irq = platform_get_irq(pdev, 0);
> + if (rtcdev->wakeup_irq <= 0) {
> + dev_dbg(&pdev->dev, "could not get wakeup irq\n");
> + return rtcdev->wakeup_irq;
> + }
> + ret = devm_request_irq(&pdev->dev, rtcdev->wakeup_irq, mpfs_rtc_wakeup_irq_handler, 0,
> + dev_name(&pdev->dev), rtcdev);
> + if (ret) {
> + dev_dbg(&pdev->dev, "could not request wakeup irq\n");
> + return ret;
> + }
> +
> + /* prescaler hardware adds 1 to reg value */
> + prescaler = clk_get_rate(devm_clk_get(&pdev->dev, "rtcref")) - 1;
> +
> + if (prescaler > MAX_PRESCALER_COUNT) {
> + dev_dbg(&pdev->dev, "invalid prescaler %d\n", prescaler);
> + return -EINVAL;
> + }
> +
> + writel(prescaler, rtcdev->base + PRESCALER_REG);
> + dev_info(&pdev->dev, "prescaler set to: 0x%X \r\n", prescaler);
> +
> + device_init_wakeup(&pdev->dev, true);
> + ret = dev_pm_set_wake_irq(&pdev->dev, rtcdev->wakeup_irq);
> + if (ret)
> + dev_err(&pdev->dev, "failed to enable irq wake\n");
> +
> + return devm_rtc_register_device(rtcdev->rtc);
> +}
> +
> +static int mpfs_rtc_remove(struct platform_device *pdev)
> +{
> + mpfs_rtc_alarm_irq_enable(&pdev->dev, 0);
This is not something you want to do if you want to wake up from
hibernate or any similar sleep state.
> + device_init_wakeup(&pdev->dev, 0);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id mpfs_rtc_of_match[] = {
> + { .compatible = "microchip,mpfs-rtc" },
> + { }
> +};
> +
> +MODULE_DEVICE_TABLE(of, mpfs_rtc_of_match);
> +
> +static struct platform_driver mpfs_rtc_driver = {
> + .probe = mpfs_rtc_probe,
> + .remove = mpfs_rtc_remove,
> + .driver = {
> + .name = "mpfs_rtc",
> + .of_match_table = mpfs_rtc_of_match,
> + },
> +};
> +
> +module_platform_driver(mpfs_rtc_driver);
> +
> +MODULE_DESCRIPTION("Real time clock for Microchip Polarfire SoC");
> +MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
> +MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
> +MODULE_LICENSE("GPL");
> --
> 2.36.1
>
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 1/2] rtc: Add driver for Microchip PolarFire SoC
2022-05-17 21:09 ` Alexandre Belloni
@ 2022-05-17 21:37 ` Conor.Dooley
-1 siblings, 0 replies; 14+ messages in thread
From: Conor.Dooley @ 2022-05-17 21:37 UTC (permalink / raw)
To: alexandre.belloni
Cc: a.zummo, Daire.McNamara, Lewis.Hanly, linux-kernel, linux-rtc,
linux-riscv
On 17/05/2022 22:09, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hello,
>
> On 16/05/2022 09:28:38+0100, Conor Dooley wrote:
>> +struct mpfs_rtc_dev {
>> + struct rtc_device *rtc;
>> + void __iomem *base;
>> + int wakeup_irq;
>
> I believe this is only used in .probe so you make it local to this
> function.>
>> +};
>> +
>
>
>> +static int mpfs_rtc_readtime(struct device *dev, struct rtc_time *tm)
>> +{
>> + struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
>> + u64 time;
>> +
>> + time = ((u64)readl(rtcdev->base + DATETIME_UPPER_REG) & DATETIME_UPPER_MASK) << 32;
>> + time |= readl(rtcdev->base + DATETIME_LOWER_REG);
>
> Are the registers properly latched on a DATETIME_UPPER_REG read?
It's a good thing you asked - I went to double check and these reads are
backwards. /facepalm
A read from the upper register will always be aligned with the last read
of the lower register. Stupid oversight, sorry.
>
>> + rtc_time64_to_tm(time + rtcdev->rtc->range_min, tm);
>
> range_min is never set so it will end up being 0. I guess you can avoid
> a bunch of arithmetic in all the driver. Offsetting will happen in the
> core which will probably never happen anyway because the max year is
> 141338. I guess we will all be gone by then ;)
SGTM, including not being around in year 141338...
Thanks,
Conor.
>
>> +
>> + return 0;
>> +}
>> +
>
>> +static int mpfs_rtc_probe(struct platform_device *pdev)
>> +{
>> + struct mpfs_rtc_dev *rtcdev;
>> + struct clk *clk;
>> + u32 prescaler;
>> + int ret;
>> +
>> + rtcdev = devm_kzalloc(&pdev->dev, sizeof(struct mpfs_rtc_dev), GFP_KERNEL);
>> + if (!rtcdev)
>> + return -ENOMEM;
>> +
>> + platform_set_drvdata(pdev, rtcdev);
>> +
>> + rtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
>> + if (IS_ERR(rtcdev->rtc))
>> + return PTR_ERR(rtcdev->rtc);
>> +
>> + rtcdev->rtc->ops = &mpfs_rtc_ops;
>> +
>> + /* range is capped by alarm max, lower reg is 31:0 & upper is 10:0 */
>> + rtcdev->rtc->range_max = GENMASK_ULL(42, 0);
>> +
>> + clk = mpfs_rtc_init_clk(&pdev->dev);
>> + if (IS_ERR(clk))
>> + return PTR_ERR(clk);
>> +
>> + rtcdev->base = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(rtcdev->base)) {
>> + dev_dbg(&pdev->dev, "invalid ioremap resources\n");
>> + return PTR_ERR(rtcdev->base);
>> + }
>> +
>> + rtcdev->wakeup_irq = platform_get_irq(pdev, 0);
>> + if (rtcdev->wakeup_irq <= 0) {
>> + dev_dbg(&pdev->dev, "could not get wakeup irq\n");
>> + return rtcdev->wakeup_irq;
>> + }
>> + ret = devm_request_irq(&pdev->dev, rtcdev->wakeup_irq, mpfs_rtc_wakeup_irq_handler, 0,
>> + dev_name(&pdev->dev), rtcdev);
>> + if (ret) {
>> + dev_dbg(&pdev->dev, "could not request wakeup irq\n");
>> + return ret;
>> + }
>> +
>> + /* prescaler hardware adds 1 to reg value */
>> + prescaler = clk_get_rate(devm_clk_get(&pdev->dev, "rtcref")) - 1;
>> +
>> + if (prescaler > MAX_PRESCALER_COUNT) {
>> + dev_dbg(&pdev->dev, "invalid prescaler %d\n", prescaler);
>> + return -EINVAL;
>> + }
>> +
>> + writel(prescaler, rtcdev->base + PRESCALER_REG);
>> + dev_info(&pdev->dev, "prescaler set to: 0x%X \r\n", prescaler);
>> +
>> + device_init_wakeup(&pdev->dev, true);
>> + ret = dev_pm_set_wake_irq(&pdev->dev, rtcdev->wakeup_irq);
>> + if (ret)
>> + dev_err(&pdev->dev, "failed to enable irq wake\n");
>> +
>> + return devm_rtc_register_device(rtcdev->rtc);
>> +}
>> +
>> +static int mpfs_rtc_remove(struct platform_device *pdev)
>> +{
>> + mpfs_rtc_alarm_irq_enable(&pdev->dev, 0);
>
> This is not something you want to do if you want to wake up from
> hibernate or any similar sleep state.
>
>> + device_init_wakeup(&pdev->dev, 0);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id mpfs_rtc_of_match[] = {
>> + { .compatible = "microchip,mpfs-rtc" },
>> + { }
>> +};
>> +
>> +MODULE_DEVICE_TABLE(of, mpfs_rtc_of_match);
>> +
>> +static struct platform_driver mpfs_rtc_driver = {
>> + .probe = mpfs_rtc_probe,
>> + .remove = mpfs_rtc_remove,
>> + .driver = {
>> + .name = "mpfs_rtc",
>> + .of_match_table = mpfs_rtc_of_match,
>> + },
>> +};
>> +
>> +module_platform_driver(mpfs_rtc_driver);
>> +
>> +MODULE_DESCRIPTION("Real time clock for Microchip Polarfire SoC");
>> +MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
>> +MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
>> +MODULE_LICENSE("GPL");
>> --
>> 2.36.1
>>
>
> --
> Alexandre Belloni, co-owner and COO, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 1/2] rtc: Add driver for Microchip PolarFire SoC
@ 2022-05-17 21:37 ` Conor.Dooley
0 siblings, 0 replies; 14+ messages in thread
From: Conor.Dooley @ 2022-05-17 21:37 UTC (permalink / raw)
To: alexandre.belloni
Cc: a.zummo, Daire.McNamara, Lewis.Hanly, linux-kernel, linux-rtc,
linux-riscv
On 17/05/2022 22:09, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hello,
>
> On 16/05/2022 09:28:38+0100, Conor Dooley wrote:
>> +struct mpfs_rtc_dev {
>> + struct rtc_device *rtc;
>> + void __iomem *base;
>> + int wakeup_irq;
>
> I believe this is only used in .probe so you make it local to this
> function.>
>> +};
>> +
>
>
>> +static int mpfs_rtc_readtime(struct device *dev, struct rtc_time *tm)
>> +{
>> + struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
>> + u64 time;
>> +
>> + time = ((u64)readl(rtcdev->base + DATETIME_UPPER_REG) & DATETIME_UPPER_MASK) << 32;
>> + time |= readl(rtcdev->base + DATETIME_LOWER_REG);
>
> Are the registers properly latched on a DATETIME_UPPER_REG read?
It's a good thing you asked - I went to double check and these reads are
backwards. /facepalm
A read from the upper register will always be aligned with the last read
of the lower register. Stupid oversight, sorry.
>
>> + rtc_time64_to_tm(time + rtcdev->rtc->range_min, tm);
>
> range_min is never set so it will end up being 0. I guess you can avoid
> a bunch of arithmetic in all the driver. Offsetting will happen in the
> core which will probably never happen anyway because the max year is
> 141338. I guess we will all be gone by then ;)
SGTM, including not being around in year 141338...
Thanks,
Conor.
>
>> +
>> + return 0;
>> +}
>> +
>
>> +static int mpfs_rtc_probe(struct platform_device *pdev)
>> +{
>> + struct mpfs_rtc_dev *rtcdev;
>> + struct clk *clk;
>> + u32 prescaler;
>> + int ret;
>> +
>> + rtcdev = devm_kzalloc(&pdev->dev, sizeof(struct mpfs_rtc_dev), GFP_KERNEL);
>> + if (!rtcdev)
>> + return -ENOMEM;
>> +
>> + platform_set_drvdata(pdev, rtcdev);
>> +
>> + rtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
>> + if (IS_ERR(rtcdev->rtc))
>> + return PTR_ERR(rtcdev->rtc);
>> +
>> + rtcdev->rtc->ops = &mpfs_rtc_ops;
>> +
>> + /* range is capped by alarm max, lower reg is 31:0 & upper is 10:0 */
>> + rtcdev->rtc->range_max = GENMASK_ULL(42, 0);
>> +
>> + clk = mpfs_rtc_init_clk(&pdev->dev);
>> + if (IS_ERR(clk))
>> + return PTR_ERR(clk);
>> +
>> + rtcdev->base = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(rtcdev->base)) {
>> + dev_dbg(&pdev->dev, "invalid ioremap resources\n");
>> + return PTR_ERR(rtcdev->base);
>> + }
>> +
>> + rtcdev->wakeup_irq = platform_get_irq(pdev, 0);
>> + if (rtcdev->wakeup_irq <= 0) {
>> + dev_dbg(&pdev->dev, "could not get wakeup irq\n");
>> + return rtcdev->wakeup_irq;
>> + }
>> + ret = devm_request_irq(&pdev->dev, rtcdev->wakeup_irq, mpfs_rtc_wakeup_irq_handler, 0,
>> + dev_name(&pdev->dev), rtcdev);
>> + if (ret) {
>> + dev_dbg(&pdev->dev, "could not request wakeup irq\n");
>> + return ret;
>> + }
>> +
>> + /* prescaler hardware adds 1 to reg value */
>> + prescaler = clk_get_rate(devm_clk_get(&pdev->dev, "rtcref")) - 1;
>> +
>> + if (prescaler > MAX_PRESCALER_COUNT) {
>> + dev_dbg(&pdev->dev, "invalid prescaler %d\n", prescaler);
>> + return -EINVAL;
>> + }
>> +
>> + writel(prescaler, rtcdev->base + PRESCALER_REG);
>> + dev_info(&pdev->dev, "prescaler set to: 0x%X \r\n", prescaler);
>> +
>> + device_init_wakeup(&pdev->dev, true);
>> + ret = dev_pm_set_wake_irq(&pdev->dev, rtcdev->wakeup_irq);
>> + if (ret)
>> + dev_err(&pdev->dev, "failed to enable irq wake\n");
>> +
>> + return devm_rtc_register_device(rtcdev->rtc);
>> +}
>> +
>> +static int mpfs_rtc_remove(struct platform_device *pdev)
>> +{
>> + mpfs_rtc_alarm_irq_enable(&pdev->dev, 0);
>
> This is not something you want to do if you want to wake up from
> hibernate or any similar sleep state.
>
>> + device_init_wakeup(&pdev->dev, 0);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id mpfs_rtc_of_match[] = {
>> + { .compatible = "microchip,mpfs-rtc" },
>> + { }
>> +};
>> +
>> +MODULE_DEVICE_TABLE(of, mpfs_rtc_of_match);
>> +
>> +static struct platform_driver mpfs_rtc_driver = {
>> + .probe = mpfs_rtc_probe,
>> + .remove = mpfs_rtc_remove,
>> + .driver = {
>> + .name = "mpfs_rtc",
>> + .of_match_table = mpfs_rtc_of_match,
>> + },
>> +};
>> +
>> +module_platform_driver(mpfs_rtc_driver);
>> +
>> +MODULE_DESCRIPTION("Real time clock for Microchip Polarfire SoC");
>> +MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
>> +MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
>> +MODULE_LICENSE("GPL");
>> --
>> 2.36.1
>>
>
> --
> Alexandre Belloni, co-owner and COO, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 1/2] rtc: Add driver for Microchip PolarFire SoC
2022-05-16 8:28 ` Conor Dooley
@ 2022-05-30 7:07 ` Pavel Machek
-1 siblings, 0 replies; 14+ messages in thread
From: Pavel Machek @ 2022-05-30 7:07 UTC (permalink / raw)
To: Conor Dooley
Cc: a.zummo, alexandre.belloni, daire.mcnamara, lewis.hanly,
linux-kernel, linux-rtc, linux-riscv
Hi!
> Add support for the built-in RTC on Microchip PolarFire SoC
> +#define CONTROL_UPLOAD_BIT BIT(5)
> +#define CONTROL_DOWNLOAD_BIT BIT(6)
> +#define CONTROL_DOWNLOAD_BIT BIT(6)
> +#define CONTROL_WAKEUP_CLR_BIT BIT(8)
Dup?
> +static void mpfs_rtc_start(struct mpfs_rtc_dev *rtcdev)
> +{
> + u32 ctrl;
> +
> + ctrl = readl(rtcdev->base + CONTROL_REG);
> + ctrl &= ~(CONTROL_STOP_BIT | CONTROL_START_BIT);
> + ctrl |= CONTROL_START_BIT;
> + writel(ctrl, rtcdev->base + CONTROL_REG);
> +}
You don't need to clear bit just to set it.
> + do {
> + prog = readl(rtcdev->base + CONTROL_REG);
> + prog &= CONTROL_UPLOAD_BIT;
> + } while (prog);
Limit to XY iterations?
> +
> +static int mpfs_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
> +{
> + u32 mode = readl(rtcdev->base + MODE_REG);
> + u64 time;
> +
> + mode = readl(rtcdev->base + MODE_REG);
Dup?
> + if (mode & MODE_WAKE_EN) + alrm->enabled = true; + else + alrm->enabled = false; +
enabled = ()?
Best regards,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 1/2] rtc: Add driver for Microchip PolarFire SoC
@ 2022-05-30 7:07 ` Pavel Machek
0 siblings, 0 replies; 14+ messages in thread
From: Pavel Machek @ 2022-05-30 7:07 UTC (permalink / raw)
To: Conor Dooley
Cc: a.zummo, alexandre.belloni, daire.mcnamara, lewis.hanly,
linux-kernel, linux-rtc, linux-riscv
Hi!
> Add support for the built-in RTC on Microchip PolarFire SoC
> +#define CONTROL_UPLOAD_BIT BIT(5)
> +#define CONTROL_DOWNLOAD_BIT BIT(6)
> +#define CONTROL_DOWNLOAD_BIT BIT(6)
> +#define CONTROL_WAKEUP_CLR_BIT BIT(8)
Dup?
> +static void mpfs_rtc_start(struct mpfs_rtc_dev *rtcdev)
> +{
> + u32 ctrl;
> +
> + ctrl = readl(rtcdev->base + CONTROL_REG);
> + ctrl &= ~(CONTROL_STOP_BIT | CONTROL_START_BIT);
> + ctrl |= CONTROL_START_BIT;
> + writel(ctrl, rtcdev->base + CONTROL_REG);
> +}
You don't need to clear bit just to set it.
> + do {
> + prog = readl(rtcdev->base + CONTROL_REG);
> + prog &= CONTROL_UPLOAD_BIT;
> + } while (prog);
Limit to XY iterations?
> +
> +static int mpfs_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
> +{
> + u32 mode = readl(rtcdev->base + MODE_REG);
> + u64 time;
> +
> + mode = readl(rtcdev->base + MODE_REG);
Dup?
> + if (mode & MODE_WAKE_EN) + alrm->enabled = true; + else + alrm->enabled = false; +
enabled = ()?
Best regards,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 1/2] rtc: Add driver for Microchip PolarFire SoC
2022-05-30 7:07 ` Pavel Machek
@ 2022-05-30 13:27 ` Geert Uytterhoeven
-1 siblings, 0 replies; 14+ messages in thread
From: Geert Uytterhoeven @ 2022-05-30 13:27 UTC (permalink / raw)
To: Pavel Machek
Cc: Conor Dooley, Alessandro Zummo, Alexandre Belloni,
daire.mcnamara, Lewis Hanly, Linux Kernel Mailing List,
linux-rtc, linux-riscv
On Mon, May 30, 2022 at 9:13 AM Pavel Machek <pavel@ucw.cz> wrote:
> Add support for the built-in RTC on Microchip PolarFire SoC
> > + do {
> > + prog = readl(rtcdev->base + CONTROL_REG);
> > + prog &= CONTROL_UPLOAD_BIT;
> > + } while (prog);
>
> Limit to XY iterations?
Perhaps read_poll_timeout()?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 1/2] rtc: Add driver for Microchip PolarFire SoC
@ 2022-05-30 13:27 ` Geert Uytterhoeven
0 siblings, 0 replies; 14+ messages in thread
From: Geert Uytterhoeven @ 2022-05-30 13:27 UTC (permalink / raw)
To: Pavel Machek
Cc: Conor Dooley, Alessandro Zummo, Alexandre Belloni,
daire.mcnamara, Lewis Hanly, Linux Kernel Mailing List,
linux-rtc, linux-riscv
On Mon, May 30, 2022 at 9:13 AM Pavel Machek <pavel@ucw.cz> wrote:
> Add support for the built-in RTC on Microchip PolarFire SoC
> > + do {
> > + prog = readl(rtcdev->base + CONTROL_REG);
> > + prog &= CONTROL_UPLOAD_BIT;
> > + } while (prog);
>
> Limit to XY iterations?
Perhaps read_poll_timeout()?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2022-05-30 13:36 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-16 8:28 [PATCH v3 0/2] rtc: microchip: Add driver for PolarFire SoC Conor Dooley
2022-05-16 8:28 ` Conor Dooley
2022-05-16 8:28 ` [PATCH v3 1/2] rtc: Add driver for Microchip " Conor Dooley
2022-05-16 8:28 ` Conor Dooley
2022-05-17 21:09 ` Alexandre Belloni
2022-05-17 21:09 ` Alexandre Belloni
2022-05-17 21:37 ` Conor.Dooley
2022-05-17 21:37 ` Conor.Dooley
2022-05-30 7:07 ` Pavel Machek
2022-05-30 7:07 ` Pavel Machek
2022-05-30 13:27 ` Geert Uytterhoeven
2022-05-30 13:27 ` Geert Uytterhoeven
2022-05-16 8:28 ` [PATCH v3 2/2] MAINTAINERS: add PolarFire SoC's RTC Conor Dooley
2022-05-16 8:28 ` Conor Dooley
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