* [PATCH 0/8] hw/cxl: Move CXL emulation options and state to machines.
@ 2022-05-30 13:45 ` Jonathan Cameron
0 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron via @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
Currently only machine with CXL support upstream is i386/pc but arm/virt
patches have been posted and once this is merged an updated series will
follow. Switch support is queued behind this as well because they both
include documentation updates.
Paolo Bonzini highlighted a couple of issues with the current CXL
emulation code.
* Top level parameter rather than machine for fixed memory windows
The --cxl-fixed-memory-window top level command line parameters won't play
well with efforts to make it possible to instantiate entire machines via
RPC. Better to move these to be machine configuration. This change is
relatively straight forward, but does result in very long command lines
(cannot break fixed window setup into multiple -M entries).
* Move all CXL stuff to machine specific code and helpers
To simplify the various interactions between machine setup and host
bridges etc, currently various CXL steps are called from the generic
core/machine.c and softmmu/vl.c + there are CXL elements in MachineState.
Much of this is straight forward to do with one exception:
The CXL pci_expander_bridge host bridges require MMIO register space.
This series does this by walking the bus and filling the register space
in via the machine_done callback. This is similar to the walk done for
identifying host bridges in the ACPI building code but it is rather ugly
and postpones rejection of PXB_CXL instances where cxl=off (default).
All comments welcome, but the first patch at least changes the command-line
so to avoid have to add backwards compatibility code, it would be great
to merge that before 7.1 is released.
Run through the CI at:
https://gitlab.com/jic23/qemu/-/pipelines/551206618
(rerunning a few test cases that timed out, but all passed for the
full tree with arm/virt and switch support, so should be fine)
Thanks,
Jonathan
Jonathan Cameron (8):
hw/cxl: Make the CXL fixed memory window setup a machine parameter.
hw/acpi/cxl: Pass in the CXLState directly rather than MachineState
hw/cxl: Push linking of CXL targets into i386/pc rather than in
machine.c
tests/acpi: Allow modification of q35 CXL CEDT table.
pci/pci_expander_bridge: For CXL HB delay the HB register memory
region setup.
tests/acpi: Update q35/CEDT.cxl for new memory addresses.
hw/cxl: Move the CXLState from MachineState to machine type specific
state.
hw/machine: Drop cxl_supported flag as no longer useful
docs/system/devices/cxl.rst | 4 +-
hw/acpi/cxl.c | 9 +--
hw/core/machine.c | 28 -------
hw/cxl/cxl-host-stubs.c | 8 +-
hw/cxl/cxl-host.c | 80 +++++++++++++++++---
hw/i386/acpi-build.c | 8 +-
hw/i386/pc.c | 44 ++++++++---
hw/pci-bridge/meson.build | 5 +-
hw/pci-bridge/pci_expander_bridge.c | 32 +++++---
hw/pci-bridge/pci_expander_bridge_stubs.c | 14 ++++
include/hw/acpi/cxl.h | 5 +-
include/hw/boards.h | 3 +-
include/hw/cxl/cxl.h | 9 +--
include/hw/cxl/cxl_host.h | 22 ++++++
include/hw/i386/pc.h | 2 +
include/hw/pci-bridge/pci_expander_bridge.h | 12 +++
qapi/machine.json | 13 ++++
softmmu/vl.c | 46 -----------
tests/data/acpi/q35/CEDT.cxl | Bin 184 -> 184 bytes
tests/qtest/bios-tables-test.c | 4 +-
tests/qtest/cxl-test.c | 4 +-
21 files changed, 213 insertions(+), 139 deletions(-)
create mode 100644 hw/pci-bridge/pci_expander_bridge_stubs.c
create mode 100644 include/hw/cxl/cxl_host.h
create mode 100644 include/hw/pci-bridge/pci_expander_bridge.h
--
2.32.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 0/8] hw/cxl: Move CXL emulation options and state to machines.
@ 2022-05-30 13:45 ` Jonathan Cameron
0 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
Currently only machine with CXL support upstream is i386/pc but arm/virt
patches have been posted and once this is merged an updated series will
follow. Switch support is queued behind this as well because they both
include documentation updates.
Paolo Bonzini highlighted a couple of issues with the current CXL
emulation code.
* Top level parameter rather than machine for fixed memory windows
The --cxl-fixed-memory-window top level command line parameters won't play
well with efforts to make it possible to instantiate entire machines via
RPC. Better to move these to be machine configuration. This change is
relatively straight forward, but does result in very long command lines
(cannot break fixed window setup into multiple -M entries).
* Move all CXL stuff to machine specific code and helpers
To simplify the various interactions between machine setup and host
bridges etc, currently various CXL steps are called from the generic
core/machine.c and softmmu/vl.c + there are CXL elements in MachineState.
Much of this is straight forward to do with one exception:
The CXL pci_expander_bridge host bridges require MMIO register space.
This series does this by walking the bus and filling the register space
in via the machine_done callback. This is similar to the walk done for
identifying host bridges in the ACPI building code but it is rather ugly
and postpones rejection of PXB_CXL instances where cxl=off (default).
All comments welcome, but the first patch at least changes the command-line
so to avoid have to add backwards compatibility code, it would be great
to merge that before 7.1 is released.
Run through the CI at:
https://gitlab.com/jic23/qemu/-/pipelines/551206618
(rerunning a few test cases that timed out, but all passed for the
full tree with arm/virt and switch support, so should be fine)
Thanks,
Jonathan
Jonathan Cameron (8):
hw/cxl: Make the CXL fixed memory window setup a machine parameter.
hw/acpi/cxl: Pass in the CXLState directly rather than MachineState
hw/cxl: Push linking of CXL targets into i386/pc rather than in
machine.c
tests/acpi: Allow modification of q35 CXL CEDT table.
pci/pci_expander_bridge: For CXL HB delay the HB register memory
region setup.
tests/acpi: Update q35/CEDT.cxl for new memory addresses.
hw/cxl: Move the CXLState from MachineState to machine type specific
state.
hw/machine: Drop cxl_supported flag as no longer useful
docs/system/devices/cxl.rst | 4 +-
hw/acpi/cxl.c | 9 +--
hw/core/machine.c | 28 -------
hw/cxl/cxl-host-stubs.c | 8 +-
hw/cxl/cxl-host.c | 80 +++++++++++++++++---
hw/i386/acpi-build.c | 8 +-
hw/i386/pc.c | 44 ++++++++---
hw/pci-bridge/meson.build | 5 +-
hw/pci-bridge/pci_expander_bridge.c | 32 +++++---
hw/pci-bridge/pci_expander_bridge_stubs.c | 14 ++++
include/hw/acpi/cxl.h | 5 +-
include/hw/boards.h | 3 +-
include/hw/cxl/cxl.h | 9 +--
include/hw/cxl/cxl_host.h | 22 ++++++
include/hw/i386/pc.h | 2 +
include/hw/pci-bridge/pci_expander_bridge.h | 12 +++
qapi/machine.json | 13 ++++
softmmu/vl.c | 46 -----------
tests/data/acpi/q35/CEDT.cxl | Bin 184 -> 184 bytes
tests/qtest/bios-tables-test.c | 4 +-
tests/qtest/cxl-test.c | 4 +-
21 files changed, 213 insertions(+), 139 deletions(-)
create mode 100644 hw/pci-bridge/pci_expander_bridge_stubs.c
create mode 100644 include/hw/cxl/cxl_host.h
create mode 100644 include/hw/pci-bridge/pci_expander_bridge.h
--
2.32.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 1/8] hw/cxl: Make the CXL fixed memory window setup a machine parameter.
2022-05-30 13:45 ` Jonathan Cameron
@ 2022-05-30 13:45 ` Jonathan Cameron
-1 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron via @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
Paolo Bonzini requested this change to simplify the ongoing
effort to allow machine setup entirely via RPC.
Includes shortening the command line form cxl-fixed-memory-window
to cxl-fmw as the command lines are extremely long even with this
change.
The json change is needed to ensure that there is
a CXLFixedMemoryWindowOptionsList even though the actual
element in the json is never used. Similar to existing
SgxEpcProperties.
Update cxl-test and bios-tables-test to reflect new parameters.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
docs/system/devices/cxl.rst | 4 +-
hw/core/machine.c | 22 ---------
hw/cxl/cxl-host-stubs.c | 6 +--
hw/cxl/cxl-host.c | 72 +++++++++++++++++++++++++++--
hw/i386/pc.c | 3 ++
hw/pci-bridge/pci_expander_bridge.c | 2 +-
include/hw/boards.h | 1 +
include/hw/cxl/cxl.h | 7 +--
include/hw/cxl/cxl_host.h | 21 +++++++++
qapi/machine.json | 13 ++++++
softmmu/vl.c | 44 ------------------
tests/qtest/bios-tables-test.c | 4 +-
tests/qtest/cxl-test.c | 4 +-
13 files changed, 116 insertions(+), 87 deletions(-)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index 9293cbf01a..bcbfe8c490 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.rst
@@ -251,7 +251,7 @@ A very simple setup with just one directly attached CXL Type 3 device::
-device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \
-device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \
-device cxl-type3,bus=root_port13,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \
- -cxl-fixed-memory-window targets.0=cxl.1,size=4G
+ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G
A setup suitable for 4 way interleave. Only one fixed window provided, to enable 2 way
interleave across 2 CXL host bridges. Each host bridge has 2 CXL Root Ports, with
@@ -277,7 +277,7 @@ the CXL Type3 device directly attached (no switches).::
-device cxl-type3,bus=root_port15,memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2 \
-device cxl-rp,port=1,bus=cxl.2,id=root_port16,chassis=0,slot=6 \
-device cxl-type3,bus=root_port16,memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3 \
- -cxl-fixed-memory-window targets.0=cxl.1,targets.1=cxl.2,size=4G,interleave-granularity=8k
+ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.targets.1=cxl.2,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=8k
Kernel Configuration Options
----------------------------
diff --git a/hw/core/machine.c b/hw/core/machine.c
index bb0dc8f6a9..87787b5604 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -628,20 +628,6 @@ static void machine_set_nvdimm_persistence(Object *obj, const char *value,
nvdimms_state->persistence_string = g_strdup(value);
}
-static bool machine_get_cxl(Object *obj, Error **errp)
-{
- MachineState *ms = MACHINE(obj);
-
- return ms->cxl_devices_state->is_enabled;
-}
-
-static void machine_set_cxl(Object *obj, bool value, Error **errp)
-{
- MachineState *ms = MACHINE(obj);
-
- ms->cxl_devices_state->is_enabled = value;
-}
-
void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type)
{
QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type));
@@ -928,8 +914,6 @@ static void machine_class_init(ObjectClass *oc, void *data)
mc->default_ram_size = 128 * MiB;
mc->rom_file_has_mr = true;
- /* Few machines support CXL, so default to off */
- mc->cxl_supported = false;
/* numa node memory size aligned on 8MB by default.
* On Linux, each node's border has to be 8MB aligned
*/
@@ -1091,13 +1075,7 @@ static void machine_initfn(Object *obj)
}
if (mc->cxl_supported) {
- Object *obj = OBJECT(ms);
-
ms->cxl_devices_state = g_new0(CXLState, 1);
- object_property_add_bool(obj, "cxl", machine_get_cxl, machine_set_cxl);
- object_property_set_description(obj, "cxl",
- "Set on/off to enable/disable "
- "CXL instantiation");
}
if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) {
diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c
index 24465a52ab..de3e8894d5 100644
--- a/hw/cxl/cxl-host-stubs.c
+++ b/hw/cxl/cxl-host-stubs.c
@@ -6,11 +6,9 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/cxl/cxl.h"
-
-void cxl_fixed_memory_window_config(MachineState *ms,
- CXLFixedMemoryWindowOptions *object,
- Error **errp) {};
+#include "hw/cxl/cxl_host.h"
void cxl_fixed_memory_window_link_targets(Error **errp) {};
+void cxl_machine_init(Object *obj, CXLState *state) {};
const MemoryRegionOps cfmws_ops;
diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
index 469b3c4ced..bcf09c466c 100644
--- a/hw/cxl/cxl-host.c
+++ b/hw/cxl/cxl-host.c
@@ -15,14 +15,15 @@
#include "qapi/qapi-visit-machine.h"
#include "hw/cxl/cxl.h"
+#include "hw/cxl/cxl_host.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_host.h"
#include "hw/pci/pcie_port.h"
-void cxl_fixed_memory_window_config(MachineState *ms,
- CXLFixedMemoryWindowOptions *object,
- Error **errp)
+static void cxl_fixed_memory_window_config(CXLState *cxl_state,
+ CXLFixedMemoryWindowOptions *object,
+ Error **errp)
{
CXLFixedWindow *fw = g_malloc0(sizeof(*fw));
strList *target;
@@ -62,8 +63,7 @@ void cxl_fixed_memory_window_config(MachineState *ms,
fw->enc_int_gran = 0;
}
- ms->cxl_devices_state->fixed_windows =
- g_list_append(ms->cxl_devices_state->fixed_windows, fw);
+ cxl_state->fixed_windows = g_list_append(cxl_state->fixed_windows, fw);
return;
}
@@ -220,3 +220,65 @@ const MemoryRegionOps cfmws_ops = {
.unaligned = true,
},
};
+
+static void machine_get_cxl(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ CXLState *cxl_state = opaque;
+ bool value = cxl_state->is_enabled;
+
+ visit_type_bool(v, name, &value, errp);
+}
+
+static void machine_set_cxl(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ CXLState *cxl_state = opaque;
+ bool value;
+
+ if (!visit_type_bool(v, name, &value, errp)) {
+ return;
+ }
+ cxl_state->is_enabled = value;
+}
+
+static void machine_get_cfmw(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ CXLFixedMemoryWindowOptionsList **list = opaque;
+
+ visit_type_CXLFixedMemoryWindowOptionsList(v, name, list, errp);
+}
+
+static void machine_set_cfmw(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ CXLState *state = opaque;
+ CXLFixedMemoryWindowOptionsList *cfmw_list = NULL;
+ CXLFixedMemoryWindowOptionsList *it;
+
+ visit_type_CXLFixedMemoryWindowOptionsList(v, name, &cfmw_list, errp);
+ if (!cfmw_list) {
+ return;
+ }
+
+ for (it = cfmw_list; it; it = it->next) {
+ cxl_fixed_memory_window_config(state, it->value, errp);
+ }
+ state->cfmw_list = cfmw_list;
+}
+
+void cxl_machine_init(Object *obj, CXLState *state)
+{
+ object_property_add(obj, "cxl", "bool", machine_get_cxl,
+ machine_set_cxl, NULL, state);
+ object_property_set_description(obj, "cxl",
+ "Set on/off to enable/disable "
+ "CXL instantiation");
+
+ object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow",
+ machine_get_cfmw, machine_set_cfmw,
+ NULL, state);
+ object_property_set_description(obj, "cxl-fmw",
+ "CXL Fixed Memory Window");
+}
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 7c39c91335..98e63347f2 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -76,6 +76,7 @@
#include "hw/mem/pc-dimm.h"
#include "hw/mem/nvdimm.h"
#include "hw/cxl/cxl.h"
+#include "hw/cxl/cxl_host.h"
#include "qapi/error.h"
#include "qapi/qapi-visit-common.h"
#include "qapi/qapi-visit-machine.h"
@@ -1682,6 +1683,7 @@ static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
static void pc_machine_initfn(Object *obj)
{
PCMachineState *pcms = PC_MACHINE(obj);
+ MachineState *ms = MACHINE(obj);
#ifdef CONFIG_VMPORT
pcms->vmport = ON_OFF_AUTO_AUTO;
@@ -1706,6 +1708,7 @@ static void pc_machine_initfn(Object *obj)
pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
OBJECT(pcms->pcspk), "audiodev");
+ cxl_machine_init(obj, ms->cxl_devices_state);
}
static void pc_machine_reset(MachineState *machine)
diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c
index 69244decdb..02032360f5 100644
--- a/hw/pci-bridge/pci_expander_bridge.c
+++ b/hw/pci-bridge/pci_expander_bridge.c
@@ -468,7 +468,7 @@ static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp)
error_setg(errp, "pxb-cxl devices cannot reside on a PCI bus");
return;
}
- if (!ms->cxl_devices_state->is_enabled) {
+ if (!ms->cxl_devices_state || !ms->cxl_devices_state->is_enabled) {
error_setg(errp, "Machine does not have cxl=on");
return;
}
diff --git a/include/hw/boards.h b/include/hw/boards.h
index fa57bac4fb..dd9fc56df2 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -362,6 +362,7 @@ struct MachineState {
struct NVDIMMState *nvdimms_state;
struct CXLState *cxl_devices_state;
struct NumaState *numa_state;
+ CXLFixedMemoryWindowOptionsList *cfmws_list;
};
#define DEFINE_MACHINE(namestr, machine_initfn) \
diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h
index 21d28ca110..84078a484d 100644
--- a/include/hw/cxl/cxl.h
+++ b/include/hw/cxl/cxl.h
@@ -12,6 +12,7 @@
#include "qapi/qapi-types-machine.h"
+#include "qapi/qapi-visit-machine.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_host.h"
#include "cxl_pci.h"
@@ -40,6 +41,7 @@ typedef struct CXLState {
MemoryRegion host_mr;
unsigned int next_mr_idx;
GList *fixed_windows;
+ CXLFixedMemoryWindowOptionsList *cfmw_list;
} CXLState;
struct CXLHost {
@@ -51,11 +53,6 @@ struct CXLHost {
#define TYPE_PXB_CXL_HOST "pxb-cxl-host"
OBJECT_DECLARE_SIMPLE_TYPE(CXLHost, PXB_CXL_HOST)
-void cxl_fixed_memory_window_config(MachineState *ms,
- CXLFixedMemoryWindowOptions *object,
- Error **errp);
void cxl_fixed_memory_window_link_targets(Error **errp);
-extern const MemoryRegionOps cfmws_ops;
-
#endif
diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h
new file mode 100644
index 0000000000..87a6933de2
--- /dev/null
+++ b/include/hw/cxl/cxl_host.h
@@ -0,0 +1,21 @@
+/*
+ * QEMU CXL Host Setup
+ *
+ * Copyright (c) 2022 Huawei
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See the
+ * COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/cxl/cxl.h"
+#include "hw/boards.h"
+
+#ifndef CXL_HOST_H
+#define CXL_HOST_H
+
+void cxl_machine_init(Object *obj, CXLState *state);
+
+extern const MemoryRegionOps cfmws_ops;
+
+#endif
diff --git a/qapi/machine.json b/qapi/machine.json
index 883ce3f9ea..b17ac79494 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -523,6 +523,19 @@
'*interleave-granularity': 'size',
'targets': ['str'] }}
+##
+# @CXLFMWProperties:
+#
+# List of CXL Fixed Memory Windows.
+#
+# @cxl-fmw: List of CXLFixedMemoryWindowOptions
+#
+# Since 7.1
+##
+{ 'struct' : 'CXLFMWProperties',
+ 'data': { 'cxl-fmw': ['CXLFixedMemoryWindowOptions'] }
+}
+
##
# @X86CPURegister32:
#
diff --git a/softmmu/vl.c b/softmmu/vl.c
index 84a31eba76..10d50a2af1 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -147,12 +147,6 @@ typedef struct BlockdevOptionsQueueEntry {
typedef QSIMPLEQ_HEAD(, BlockdevOptionsQueueEntry) BlockdevOptionsQueue;
-typedef struct CXLFMWOptionQueueEntry {
- CXLFixedMemoryWindowOptions *opts;
- Location loc;
- QSIMPLEQ_ENTRY(CXLFMWOptionQueueEntry) entry;
-} CXLFMWOptionQueueEntry;
-
typedef struct ObjectOption {
ObjectOptions *opts;
QTAILQ_ENTRY(ObjectOption) next;
@@ -179,8 +173,6 @@ static int snapshot;
static bool preconfig_requested;
static QemuPluginList plugin_list = QTAILQ_HEAD_INITIALIZER(plugin_list);
static BlockdevOptionsQueue bdo_queue = QSIMPLEQ_HEAD_INITIALIZER(bdo_queue);
-static QSIMPLEQ_HEAD(, CXLFMWOptionQueueEntry) CXLFMW_opts =
- QSIMPLEQ_HEAD_INITIALIZER(CXLFMW_opts);
static bool nographic = false;
static int mem_prealloc; /* force preallocation of physical target memory */
static const char *vga_model = NULL;
@@ -1165,24 +1157,6 @@ static void parse_display(const char *p)
}
}
-static void parse_cxl_fixed_memory_window(const char *optarg)
-{
- CXLFMWOptionQueueEntry *cfmws_entry;
- Visitor *v;
-
- v = qobject_input_visitor_new_str(optarg, "cxl-fixed-memory-window",
- &error_fatal);
- cfmws_entry = g_new(CXLFMWOptionQueueEntry, 1);
- visit_type_CXLFixedMemoryWindowOptions(v, NULL, &cfmws_entry->opts,
- &error_fatal);
- if (!cfmws_entry->opts) {
- exit(1);
- }
- visit_free(v);
- loc_save(&cfmws_entry->loc);
- QSIMPLEQ_INSERT_TAIL(&CXLFMW_opts, cfmws_entry, entry);
-}
-
static inline bool nonempty_str(const char *str)
{
return str && *str;
@@ -2045,20 +2019,6 @@ static void qemu_create_late_backends(void)
qemu_semihosting_console_init();
}
-static void cxl_set_opts(void)
-{
- while (!QSIMPLEQ_EMPTY(&CXLFMW_opts)) {
- CXLFMWOptionQueueEntry *cfmws_entry = QSIMPLEQ_FIRST(&CXLFMW_opts);
-
- loc_restore(&cfmws_entry->loc);
- QSIMPLEQ_REMOVE_HEAD(&CXLFMW_opts, entry);
- cxl_fixed_memory_window_config(current_machine, cfmws_entry->opts,
- &error_fatal);
- qapi_free_CXLFixedMemoryWindowOptions(cfmws_entry->opts);
- g_free(cfmws_entry);
- }
-}
-
static void qemu_resolve_machine_memdev(void)
{
if (ram_memdev_id) {
@@ -2886,9 +2846,6 @@ void qemu_init(int argc, char **argv, char **envp)
exit(1);
}
break;
- case QEMU_OPTION_cxl_fixed_memory_window:
- parse_cxl_fixed_memory_window(optarg);
- break;
case QEMU_OPTION_display:
parse_display(optarg);
break;
@@ -3724,7 +3681,6 @@ void qemu_init(int argc, char **argv, char **envp)
qemu_resolve_machine_memdev();
parse_numa_opts(current_machine);
- cxl_set_opts();
if (vmstate_dump_file) {
/* dump and exit */
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index a4a46e97f0..8a3a320aea 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1567,8 +1567,8 @@ static void test_acpi_q35_cxl(void)
" -device cxl-type3,bus=rp3,memdev=cxl-mem3,lsa=lsa3"
" -device cxl-rp,port=1,bus=cxl.2,id=rp4,chassis=0,slot=6"
" -device cxl-type3,bus=rp4,memdev=cxl-mem4,lsa=lsa4"
- " -cxl-fixed-memory-window targets.0=cxl.1,size=4G,interleave-granularity=8k"
- " -cxl-fixed-memory-window targets.0=cxl.1,targets.1=cxl.2,size=4G,interleave-granularity=8k",
+ " -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=8k,"
+ "cxl-fmw.1.targets.0=cxl.1,cxl-fmw.1.targets.1=cxl.2,cxl-fmw.1.size=4G,cxl-fmw.1.interleave-granularity=8k",
tmp_path, tmp_path, tmp_path, tmp_path,
tmp_path, tmp_path, tmp_path, tmp_path);
test_acpi_one(params, &data);
diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
index 079011af6a..2133e973f4 100644
--- a/tests/qtest/cxl-test.c
+++ b/tests/qtest/cxl-test.c
@@ -10,12 +10,12 @@
#define QEMU_PXB_CMD "-machine q35,cxl=on " \
"-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
- "-cxl-fixed-memory-window targets.0=cxl.0,size=4G "
+ "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.size=4G "
#define QEMU_2PXB_CMD "-machine q35,cxl=on " \
"-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
"-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \
- "-cxl-fixed-memory-window targets.0=cxl.0,targets.1=cxl.1,size=4G "
+ "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G "
#define QEMU_RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 "
--
2.32.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 1/8] hw/cxl: Make the CXL fixed memory window setup a machine parameter.
@ 2022-05-30 13:45 ` Jonathan Cameron
0 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
Paolo Bonzini requested this change to simplify the ongoing
effort to allow machine setup entirely via RPC.
Includes shortening the command line form cxl-fixed-memory-window
to cxl-fmw as the command lines are extremely long even with this
change.
The json change is needed to ensure that there is
a CXLFixedMemoryWindowOptionsList even though the actual
element in the json is never used. Similar to existing
SgxEpcProperties.
Update cxl-test and bios-tables-test to reflect new parameters.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
docs/system/devices/cxl.rst | 4 +-
hw/core/machine.c | 22 ---------
hw/cxl/cxl-host-stubs.c | 6 +--
hw/cxl/cxl-host.c | 72 +++++++++++++++++++++++++++--
hw/i386/pc.c | 3 ++
hw/pci-bridge/pci_expander_bridge.c | 2 +-
include/hw/boards.h | 1 +
include/hw/cxl/cxl.h | 7 +--
include/hw/cxl/cxl_host.h | 21 +++++++++
qapi/machine.json | 13 ++++++
softmmu/vl.c | 44 ------------------
tests/qtest/bios-tables-test.c | 4 +-
tests/qtest/cxl-test.c | 4 +-
13 files changed, 116 insertions(+), 87 deletions(-)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index 9293cbf01a..bcbfe8c490 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.rst
@@ -251,7 +251,7 @@ A very simple setup with just one directly attached CXL Type 3 device::
-device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \
-device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \
-device cxl-type3,bus=root_port13,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \
- -cxl-fixed-memory-window targets.0=cxl.1,size=4G
+ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G
A setup suitable for 4 way interleave. Only one fixed window provided, to enable 2 way
interleave across 2 CXL host bridges. Each host bridge has 2 CXL Root Ports, with
@@ -277,7 +277,7 @@ the CXL Type3 device directly attached (no switches).::
-device cxl-type3,bus=root_port15,memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2 \
-device cxl-rp,port=1,bus=cxl.2,id=root_port16,chassis=0,slot=6 \
-device cxl-type3,bus=root_port16,memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3 \
- -cxl-fixed-memory-window targets.0=cxl.1,targets.1=cxl.2,size=4G,interleave-granularity=8k
+ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.targets.1=cxl.2,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=8k
Kernel Configuration Options
----------------------------
diff --git a/hw/core/machine.c b/hw/core/machine.c
index bb0dc8f6a9..87787b5604 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -628,20 +628,6 @@ static void machine_set_nvdimm_persistence(Object *obj, const char *value,
nvdimms_state->persistence_string = g_strdup(value);
}
-static bool machine_get_cxl(Object *obj, Error **errp)
-{
- MachineState *ms = MACHINE(obj);
-
- return ms->cxl_devices_state->is_enabled;
-}
-
-static void machine_set_cxl(Object *obj, bool value, Error **errp)
-{
- MachineState *ms = MACHINE(obj);
-
- ms->cxl_devices_state->is_enabled = value;
-}
-
void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type)
{
QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type));
@@ -928,8 +914,6 @@ static void machine_class_init(ObjectClass *oc, void *data)
mc->default_ram_size = 128 * MiB;
mc->rom_file_has_mr = true;
- /* Few machines support CXL, so default to off */
- mc->cxl_supported = false;
/* numa node memory size aligned on 8MB by default.
* On Linux, each node's border has to be 8MB aligned
*/
@@ -1091,13 +1075,7 @@ static void machine_initfn(Object *obj)
}
if (mc->cxl_supported) {
- Object *obj = OBJECT(ms);
-
ms->cxl_devices_state = g_new0(CXLState, 1);
- object_property_add_bool(obj, "cxl", machine_get_cxl, machine_set_cxl);
- object_property_set_description(obj, "cxl",
- "Set on/off to enable/disable "
- "CXL instantiation");
}
if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) {
diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c
index 24465a52ab..de3e8894d5 100644
--- a/hw/cxl/cxl-host-stubs.c
+++ b/hw/cxl/cxl-host-stubs.c
@@ -6,11 +6,9 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/cxl/cxl.h"
-
-void cxl_fixed_memory_window_config(MachineState *ms,
- CXLFixedMemoryWindowOptions *object,
- Error **errp) {};
+#include "hw/cxl/cxl_host.h"
void cxl_fixed_memory_window_link_targets(Error **errp) {};
+void cxl_machine_init(Object *obj, CXLState *state) {};
const MemoryRegionOps cfmws_ops;
diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
index 469b3c4ced..bcf09c466c 100644
--- a/hw/cxl/cxl-host.c
+++ b/hw/cxl/cxl-host.c
@@ -15,14 +15,15 @@
#include "qapi/qapi-visit-machine.h"
#include "hw/cxl/cxl.h"
+#include "hw/cxl/cxl_host.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_host.h"
#include "hw/pci/pcie_port.h"
-void cxl_fixed_memory_window_config(MachineState *ms,
- CXLFixedMemoryWindowOptions *object,
- Error **errp)
+static void cxl_fixed_memory_window_config(CXLState *cxl_state,
+ CXLFixedMemoryWindowOptions *object,
+ Error **errp)
{
CXLFixedWindow *fw = g_malloc0(sizeof(*fw));
strList *target;
@@ -62,8 +63,7 @@ void cxl_fixed_memory_window_config(MachineState *ms,
fw->enc_int_gran = 0;
}
- ms->cxl_devices_state->fixed_windows =
- g_list_append(ms->cxl_devices_state->fixed_windows, fw);
+ cxl_state->fixed_windows = g_list_append(cxl_state->fixed_windows, fw);
return;
}
@@ -220,3 +220,65 @@ const MemoryRegionOps cfmws_ops = {
.unaligned = true,
},
};
+
+static void machine_get_cxl(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ CXLState *cxl_state = opaque;
+ bool value = cxl_state->is_enabled;
+
+ visit_type_bool(v, name, &value, errp);
+}
+
+static void machine_set_cxl(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ CXLState *cxl_state = opaque;
+ bool value;
+
+ if (!visit_type_bool(v, name, &value, errp)) {
+ return;
+ }
+ cxl_state->is_enabled = value;
+}
+
+static void machine_get_cfmw(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ CXLFixedMemoryWindowOptionsList **list = opaque;
+
+ visit_type_CXLFixedMemoryWindowOptionsList(v, name, list, errp);
+}
+
+static void machine_set_cfmw(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ CXLState *state = opaque;
+ CXLFixedMemoryWindowOptionsList *cfmw_list = NULL;
+ CXLFixedMemoryWindowOptionsList *it;
+
+ visit_type_CXLFixedMemoryWindowOptionsList(v, name, &cfmw_list, errp);
+ if (!cfmw_list) {
+ return;
+ }
+
+ for (it = cfmw_list; it; it = it->next) {
+ cxl_fixed_memory_window_config(state, it->value, errp);
+ }
+ state->cfmw_list = cfmw_list;
+}
+
+void cxl_machine_init(Object *obj, CXLState *state)
+{
+ object_property_add(obj, "cxl", "bool", machine_get_cxl,
+ machine_set_cxl, NULL, state);
+ object_property_set_description(obj, "cxl",
+ "Set on/off to enable/disable "
+ "CXL instantiation");
+
+ object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow",
+ machine_get_cfmw, machine_set_cfmw,
+ NULL, state);
+ object_property_set_description(obj, "cxl-fmw",
+ "CXL Fixed Memory Window");
+}
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 7c39c91335..98e63347f2 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -76,6 +76,7 @@
#include "hw/mem/pc-dimm.h"
#include "hw/mem/nvdimm.h"
#include "hw/cxl/cxl.h"
+#include "hw/cxl/cxl_host.h"
#include "qapi/error.h"
#include "qapi/qapi-visit-common.h"
#include "qapi/qapi-visit-machine.h"
@@ -1682,6 +1683,7 @@ static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
static void pc_machine_initfn(Object *obj)
{
PCMachineState *pcms = PC_MACHINE(obj);
+ MachineState *ms = MACHINE(obj);
#ifdef CONFIG_VMPORT
pcms->vmport = ON_OFF_AUTO_AUTO;
@@ -1706,6 +1708,7 @@ static void pc_machine_initfn(Object *obj)
pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
OBJECT(pcms->pcspk), "audiodev");
+ cxl_machine_init(obj, ms->cxl_devices_state);
}
static void pc_machine_reset(MachineState *machine)
diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c
index 69244decdb..02032360f5 100644
--- a/hw/pci-bridge/pci_expander_bridge.c
+++ b/hw/pci-bridge/pci_expander_bridge.c
@@ -468,7 +468,7 @@ static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp)
error_setg(errp, "pxb-cxl devices cannot reside on a PCI bus");
return;
}
- if (!ms->cxl_devices_state->is_enabled) {
+ if (!ms->cxl_devices_state || !ms->cxl_devices_state->is_enabled) {
error_setg(errp, "Machine does not have cxl=on");
return;
}
diff --git a/include/hw/boards.h b/include/hw/boards.h
index fa57bac4fb..dd9fc56df2 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -362,6 +362,7 @@ struct MachineState {
struct NVDIMMState *nvdimms_state;
struct CXLState *cxl_devices_state;
struct NumaState *numa_state;
+ CXLFixedMemoryWindowOptionsList *cfmws_list;
};
#define DEFINE_MACHINE(namestr, machine_initfn) \
diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h
index 21d28ca110..84078a484d 100644
--- a/include/hw/cxl/cxl.h
+++ b/include/hw/cxl/cxl.h
@@ -12,6 +12,7 @@
#include "qapi/qapi-types-machine.h"
+#include "qapi/qapi-visit-machine.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_host.h"
#include "cxl_pci.h"
@@ -40,6 +41,7 @@ typedef struct CXLState {
MemoryRegion host_mr;
unsigned int next_mr_idx;
GList *fixed_windows;
+ CXLFixedMemoryWindowOptionsList *cfmw_list;
} CXLState;
struct CXLHost {
@@ -51,11 +53,6 @@ struct CXLHost {
#define TYPE_PXB_CXL_HOST "pxb-cxl-host"
OBJECT_DECLARE_SIMPLE_TYPE(CXLHost, PXB_CXL_HOST)
-void cxl_fixed_memory_window_config(MachineState *ms,
- CXLFixedMemoryWindowOptions *object,
- Error **errp);
void cxl_fixed_memory_window_link_targets(Error **errp);
-extern const MemoryRegionOps cfmws_ops;
-
#endif
diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h
new file mode 100644
index 0000000000..87a6933de2
--- /dev/null
+++ b/include/hw/cxl/cxl_host.h
@@ -0,0 +1,21 @@
+/*
+ * QEMU CXL Host Setup
+ *
+ * Copyright (c) 2022 Huawei
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See the
+ * COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/cxl/cxl.h"
+#include "hw/boards.h"
+
+#ifndef CXL_HOST_H
+#define CXL_HOST_H
+
+void cxl_machine_init(Object *obj, CXLState *state);
+
+extern const MemoryRegionOps cfmws_ops;
+
+#endif
diff --git a/qapi/machine.json b/qapi/machine.json
index 883ce3f9ea..b17ac79494 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -523,6 +523,19 @@
'*interleave-granularity': 'size',
'targets': ['str'] }}
+##
+# @CXLFMWProperties:
+#
+# List of CXL Fixed Memory Windows.
+#
+# @cxl-fmw: List of CXLFixedMemoryWindowOptions
+#
+# Since 7.1
+##
+{ 'struct' : 'CXLFMWProperties',
+ 'data': { 'cxl-fmw': ['CXLFixedMemoryWindowOptions'] }
+}
+
##
# @X86CPURegister32:
#
diff --git a/softmmu/vl.c b/softmmu/vl.c
index 84a31eba76..10d50a2af1 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -147,12 +147,6 @@ typedef struct BlockdevOptionsQueueEntry {
typedef QSIMPLEQ_HEAD(, BlockdevOptionsQueueEntry) BlockdevOptionsQueue;
-typedef struct CXLFMWOptionQueueEntry {
- CXLFixedMemoryWindowOptions *opts;
- Location loc;
- QSIMPLEQ_ENTRY(CXLFMWOptionQueueEntry) entry;
-} CXLFMWOptionQueueEntry;
-
typedef struct ObjectOption {
ObjectOptions *opts;
QTAILQ_ENTRY(ObjectOption) next;
@@ -179,8 +173,6 @@ static int snapshot;
static bool preconfig_requested;
static QemuPluginList plugin_list = QTAILQ_HEAD_INITIALIZER(plugin_list);
static BlockdevOptionsQueue bdo_queue = QSIMPLEQ_HEAD_INITIALIZER(bdo_queue);
-static QSIMPLEQ_HEAD(, CXLFMWOptionQueueEntry) CXLFMW_opts =
- QSIMPLEQ_HEAD_INITIALIZER(CXLFMW_opts);
static bool nographic = false;
static int mem_prealloc; /* force preallocation of physical target memory */
static const char *vga_model = NULL;
@@ -1165,24 +1157,6 @@ static void parse_display(const char *p)
}
}
-static void parse_cxl_fixed_memory_window(const char *optarg)
-{
- CXLFMWOptionQueueEntry *cfmws_entry;
- Visitor *v;
-
- v = qobject_input_visitor_new_str(optarg, "cxl-fixed-memory-window",
- &error_fatal);
- cfmws_entry = g_new(CXLFMWOptionQueueEntry, 1);
- visit_type_CXLFixedMemoryWindowOptions(v, NULL, &cfmws_entry->opts,
- &error_fatal);
- if (!cfmws_entry->opts) {
- exit(1);
- }
- visit_free(v);
- loc_save(&cfmws_entry->loc);
- QSIMPLEQ_INSERT_TAIL(&CXLFMW_opts, cfmws_entry, entry);
-}
-
static inline bool nonempty_str(const char *str)
{
return str && *str;
@@ -2045,20 +2019,6 @@ static void qemu_create_late_backends(void)
qemu_semihosting_console_init();
}
-static void cxl_set_opts(void)
-{
- while (!QSIMPLEQ_EMPTY(&CXLFMW_opts)) {
- CXLFMWOptionQueueEntry *cfmws_entry = QSIMPLEQ_FIRST(&CXLFMW_opts);
-
- loc_restore(&cfmws_entry->loc);
- QSIMPLEQ_REMOVE_HEAD(&CXLFMW_opts, entry);
- cxl_fixed_memory_window_config(current_machine, cfmws_entry->opts,
- &error_fatal);
- qapi_free_CXLFixedMemoryWindowOptions(cfmws_entry->opts);
- g_free(cfmws_entry);
- }
-}
-
static void qemu_resolve_machine_memdev(void)
{
if (ram_memdev_id) {
@@ -2886,9 +2846,6 @@ void qemu_init(int argc, char **argv, char **envp)
exit(1);
}
break;
- case QEMU_OPTION_cxl_fixed_memory_window:
- parse_cxl_fixed_memory_window(optarg);
- break;
case QEMU_OPTION_display:
parse_display(optarg);
break;
@@ -3724,7 +3681,6 @@ void qemu_init(int argc, char **argv, char **envp)
qemu_resolve_machine_memdev();
parse_numa_opts(current_machine);
- cxl_set_opts();
if (vmstate_dump_file) {
/* dump and exit */
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index a4a46e97f0..8a3a320aea 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1567,8 +1567,8 @@ static void test_acpi_q35_cxl(void)
" -device cxl-type3,bus=rp3,memdev=cxl-mem3,lsa=lsa3"
" -device cxl-rp,port=1,bus=cxl.2,id=rp4,chassis=0,slot=6"
" -device cxl-type3,bus=rp4,memdev=cxl-mem4,lsa=lsa4"
- " -cxl-fixed-memory-window targets.0=cxl.1,size=4G,interleave-granularity=8k"
- " -cxl-fixed-memory-window targets.0=cxl.1,targets.1=cxl.2,size=4G,interleave-granularity=8k",
+ " -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=8k,"
+ "cxl-fmw.1.targets.0=cxl.1,cxl-fmw.1.targets.1=cxl.2,cxl-fmw.1.size=4G,cxl-fmw.1.interleave-granularity=8k",
tmp_path, tmp_path, tmp_path, tmp_path,
tmp_path, tmp_path, tmp_path, tmp_path);
test_acpi_one(params, &data);
diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
index 079011af6a..2133e973f4 100644
--- a/tests/qtest/cxl-test.c
+++ b/tests/qtest/cxl-test.c
@@ -10,12 +10,12 @@
#define QEMU_PXB_CMD "-machine q35,cxl=on " \
"-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
- "-cxl-fixed-memory-window targets.0=cxl.0,size=4G "
+ "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.size=4G "
#define QEMU_2PXB_CMD "-machine q35,cxl=on " \
"-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
"-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \
- "-cxl-fixed-memory-window targets.0=cxl.0,targets.1=cxl.1,size=4G "
+ "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G "
#define QEMU_RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 "
--
2.32.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/8] hw/acpi/cxl: Pass in the CXLState directly rather than MachineState
2022-05-30 13:45 ` Jonathan Cameron
@ 2022-05-30 13:45 ` Jonathan Cameron
-1 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron via @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
Refactoring step on path to moving all CXL state out of
MachineState.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/acpi/cxl.c | 9 ++++-----
hw/i386/acpi-build.c | 4 ++--
include/hw/acpi/cxl.h | 5 +++--
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c
index 31d5235136..2bf8c07993 100644
--- a/hw/acpi/cxl.c
+++ b/hw/acpi/cxl.c
@@ -65,9 +65,8 @@ static void cedt_build_chbs(GArray *table_data, PXBDev *cxl)
* Interleave ways encoding in CXL 2.0 ECN: 3, 6, 12 and 16-way memory
* interleaving.
*/
-static void cedt_build_cfmws(GArray *table_data, MachineState *ms)
+static void cedt_build_cfmws(GArray *table_data, CXLState *cxls)
{
- CXLState *cxls = ms->cxl_devices_state;
GList *it;
for (it = cxls->fixed_windows; it; it = it->next) {
@@ -129,9 +128,9 @@ static int cxl_foreach_pxb_hb(Object *obj, void *opaque)
return 0;
}
-void cxl_build_cedt(MachineState *ms, GArray *table_offsets, GArray *table_data,
+void cxl_build_cedt(GArray *table_offsets, GArray *table_data,
BIOSLinker *linker, const char *oem_id,
- const char *oem_table_id)
+ const char *oem_table_id, CXLState *cxl_state)
{
Aml *cedt;
AcpiTable table = { .sig = "CEDT", .rev = 1, .oem_id = oem_id,
@@ -144,7 +143,7 @@ void cxl_build_cedt(MachineState *ms, GArray *table_offsets, GArray *table_data,
/* reserve space for CEDT header */
object_child_foreach_recursive(object_get_root(), cxl_foreach_pxb_hb, cedt);
- cedt_build_cfmws(cedt->buf, ms);
+ cedt_build_cfmws(cedt->buf, cxl_state);
/* copy AML table into ACPI tables blob and patch header there */
g_array_append_vals(table_data, cedt->buf->data, cedt->buf->len);
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index c125939ed6..2e3b1dd9a2 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -2712,8 +2712,8 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
x86ms->oem_id, x86ms->oem_table_id);
}
if (machine->cxl_devices_state->is_enabled) {
- cxl_build_cedt(machine, table_offsets, tables_blob, tables->linker,
- x86ms->oem_id, x86ms->oem_table_id);
+ cxl_build_cedt(table_offsets, tables_blob, tables->linker,
+ x86ms->oem_id, x86ms->oem_table_id, machine->cxl_devices_state);
}
acpi_add_table(table_offsets, tables_blob);
diff --git a/include/hw/acpi/cxl.h b/include/hw/acpi/cxl.h
index 0c496538c0..acf4418886 100644
--- a/include/hw/acpi/cxl.h
+++ b/include/hw/acpi/cxl.h
@@ -19,10 +19,11 @@
#define HW_ACPI_CXL_H
#include "hw/acpi/bios-linker-loader.h"
+#include "hw/cxl/cxl.h"
-void cxl_build_cedt(MachineState *ms, GArray *table_offsets, GArray *table_data,
+void cxl_build_cedt(GArray *table_offsets, GArray *table_data,
BIOSLinker *linker, const char *oem_id,
- const char *oem_table_id);
+ const char *oem_table_id, CXLState *cxl_state);
void build_cxl_osc_method(Aml *dev);
#endif
--
2.32.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/8] hw/acpi/cxl: Pass in the CXLState directly rather than MachineState
@ 2022-05-30 13:45 ` Jonathan Cameron
0 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
Refactoring step on path to moving all CXL state out of
MachineState.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/acpi/cxl.c | 9 ++++-----
hw/i386/acpi-build.c | 4 ++--
include/hw/acpi/cxl.h | 5 +++--
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c
index 31d5235136..2bf8c07993 100644
--- a/hw/acpi/cxl.c
+++ b/hw/acpi/cxl.c
@@ -65,9 +65,8 @@ static void cedt_build_chbs(GArray *table_data, PXBDev *cxl)
* Interleave ways encoding in CXL 2.0 ECN: 3, 6, 12 and 16-way memory
* interleaving.
*/
-static void cedt_build_cfmws(GArray *table_data, MachineState *ms)
+static void cedt_build_cfmws(GArray *table_data, CXLState *cxls)
{
- CXLState *cxls = ms->cxl_devices_state;
GList *it;
for (it = cxls->fixed_windows; it; it = it->next) {
@@ -129,9 +128,9 @@ static int cxl_foreach_pxb_hb(Object *obj, void *opaque)
return 0;
}
-void cxl_build_cedt(MachineState *ms, GArray *table_offsets, GArray *table_data,
+void cxl_build_cedt(GArray *table_offsets, GArray *table_data,
BIOSLinker *linker, const char *oem_id,
- const char *oem_table_id)
+ const char *oem_table_id, CXLState *cxl_state)
{
Aml *cedt;
AcpiTable table = { .sig = "CEDT", .rev = 1, .oem_id = oem_id,
@@ -144,7 +143,7 @@ void cxl_build_cedt(MachineState *ms, GArray *table_offsets, GArray *table_data,
/* reserve space for CEDT header */
object_child_foreach_recursive(object_get_root(), cxl_foreach_pxb_hb, cedt);
- cedt_build_cfmws(cedt->buf, ms);
+ cedt_build_cfmws(cedt->buf, cxl_state);
/* copy AML table into ACPI tables blob and patch header there */
g_array_append_vals(table_data, cedt->buf->data, cedt->buf->len);
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index c125939ed6..2e3b1dd9a2 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -2712,8 +2712,8 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
x86ms->oem_id, x86ms->oem_table_id);
}
if (machine->cxl_devices_state->is_enabled) {
- cxl_build_cedt(machine, table_offsets, tables_blob, tables->linker,
- x86ms->oem_id, x86ms->oem_table_id);
+ cxl_build_cedt(table_offsets, tables_blob, tables->linker,
+ x86ms->oem_id, x86ms->oem_table_id, machine->cxl_devices_state);
}
acpi_add_table(table_offsets, tables_blob);
diff --git a/include/hw/acpi/cxl.h b/include/hw/acpi/cxl.h
index 0c496538c0..acf4418886 100644
--- a/include/hw/acpi/cxl.h
+++ b/include/hw/acpi/cxl.h
@@ -19,10 +19,11 @@
#define HW_ACPI_CXL_H
#include "hw/acpi/bios-linker-loader.h"
+#include "hw/cxl/cxl.h"
-void cxl_build_cedt(MachineState *ms, GArray *table_offsets, GArray *table_data,
+void cxl_build_cedt(GArray *table_offsets, GArray *table_data,
BIOSLinker *linker, const char *oem_id,
- const char *oem_table_id);
+ const char *oem_table_id, CXLState *cxl_state);
void build_cxl_osc_method(Aml *dev);
#endif
--
2.32.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 3/8] hw/cxl: Push linking of CXL targets into i386/pc rather than in machine.c
2022-05-30 13:45 ` Jonathan Cameron
@ 2022-05-30 13:45 ` Jonathan Cameron
-1 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron via @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
Whilst here take the oportunity to shorten the function name.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/cxl/cxl-host-stubs.c | 2 +-
hw/cxl/cxl-host.c | 8 +++-----
hw/i386/pc.c | 5 +++++
include/hw/cxl/cxl.h | 2 --
include/hw/cxl/cxl_host.h | 1 +
softmmu/vl.c | 2 --
6 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c
index de3e8894d5..e0d5ec8ad5 100644
--- a/hw/cxl/cxl-host-stubs.c
+++ b/hw/cxl/cxl-host-stubs.c
@@ -8,7 +8,7 @@
#include "hw/cxl/cxl.h"
#include "hw/cxl/cxl_host.h"
-void cxl_fixed_memory_window_link_targets(Error **errp) {};
+void cxl_fmws_link_targets(CXLState *stat, Error **errp) {};
void cxl_machine_init(Object *obj, CXLState *state) {};
const MemoryRegionOps cfmws_ops;
diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
index bcf09c466c..c23137acaf 100644
--- a/hw/cxl/cxl-host.c
+++ b/hw/cxl/cxl-host.c
@@ -68,14 +68,12 @@ static void cxl_fixed_memory_window_config(CXLState *cxl_state,
return;
}
-void cxl_fixed_memory_window_link_targets(Error **errp)
+void cxl_fmws_link_targets(CXLState *cxl_state, Error **errp)
{
- MachineState *ms = MACHINE(qdev_get_machine());
-
- if (ms->cxl_devices_state && ms->cxl_devices_state->fixed_windows) {
+ if (cxl_state && cxl_state->fixed_windows) {
GList *it;
- for (it = ms->cxl_devices_state->fixed_windows; it; it = it->next) {
+ for (it = cxl_state->fixed_windows; it; it = it->next) {
CXLFixedWindow *fw = it->data;
int i;
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 98e63347f2..6cecd74d58 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -732,6 +732,11 @@ void pc_machine_done(Notifier *notifier, void *data)
PCMachineState *pcms = container_of(notifier,
PCMachineState, machine_done);
X86MachineState *x86ms = X86_MACHINE(pcms);
+ MachineState *ms = MACHINE(pcms);
+
+ if (ms->cxl_devices_state) {
+ cxl_fmws_link_targets(ms->cxl_devices_state, &error_fatal);
+ }
/* set the number of CPUs */
x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h
index 84078a484d..134b295b40 100644
--- a/include/hw/cxl/cxl.h
+++ b/include/hw/cxl/cxl.h
@@ -53,6 +53,4 @@ struct CXLHost {
#define TYPE_PXB_CXL_HOST "pxb-cxl-host"
OBJECT_DECLARE_SIMPLE_TYPE(CXLHost, PXB_CXL_HOST)
-void cxl_fixed_memory_window_link_targets(Error **errp);
-
#endif
diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h
index 87a6933de2..4d642a81fa 100644
--- a/include/hw/cxl/cxl_host.h
+++ b/include/hw/cxl/cxl_host.h
@@ -15,6 +15,7 @@
#define CXL_HOST_H
void cxl_machine_init(Object *obj, CXLState *state);
+void cxl_fmws_link_targets(CXLState *stat, Error **errp);
extern const MemoryRegionOps cfmws_ops;
diff --git a/softmmu/vl.c b/softmmu/vl.c
index 10d50a2af1..ecef75b77b 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -93,7 +93,6 @@
#include "qemu/config-file.h"
#include "qemu/qemu-options.h"
#include "qemu/main-loop.h"
-#include "hw/cxl/cxl.h"
#ifdef CONFIG_VIRTFS
#include "fsdev/qemu-fsdev.h"
#endif
@@ -2665,7 +2664,6 @@ void qmp_x_exit_preconfig(Error **errp)
qemu_init_board();
qemu_create_cli_devices();
- cxl_fixed_memory_window_link_targets(errp);
qemu_machine_creation_done();
if (loadvm) {
--
2.32.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 3/8] hw/cxl: Push linking of CXL targets into i386/pc rather than in machine.c
@ 2022-05-30 13:45 ` Jonathan Cameron
0 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
Whilst here take the oportunity to shorten the function name.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/cxl/cxl-host-stubs.c | 2 +-
hw/cxl/cxl-host.c | 8 +++-----
hw/i386/pc.c | 5 +++++
include/hw/cxl/cxl.h | 2 --
include/hw/cxl/cxl_host.h | 1 +
softmmu/vl.c | 2 --
6 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c
index de3e8894d5..e0d5ec8ad5 100644
--- a/hw/cxl/cxl-host-stubs.c
+++ b/hw/cxl/cxl-host-stubs.c
@@ -8,7 +8,7 @@
#include "hw/cxl/cxl.h"
#include "hw/cxl/cxl_host.h"
-void cxl_fixed_memory_window_link_targets(Error **errp) {};
+void cxl_fmws_link_targets(CXLState *stat, Error **errp) {};
void cxl_machine_init(Object *obj, CXLState *state) {};
const MemoryRegionOps cfmws_ops;
diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
index bcf09c466c..c23137acaf 100644
--- a/hw/cxl/cxl-host.c
+++ b/hw/cxl/cxl-host.c
@@ -68,14 +68,12 @@ static void cxl_fixed_memory_window_config(CXLState *cxl_state,
return;
}
-void cxl_fixed_memory_window_link_targets(Error **errp)
+void cxl_fmws_link_targets(CXLState *cxl_state, Error **errp)
{
- MachineState *ms = MACHINE(qdev_get_machine());
-
- if (ms->cxl_devices_state && ms->cxl_devices_state->fixed_windows) {
+ if (cxl_state && cxl_state->fixed_windows) {
GList *it;
- for (it = ms->cxl_devices_state->fixed_windows; it; it = it->next) {
+ for (it = cxl_state->fixed_windows; it; it = it->next) {
CXLFixedWindow *fw = it->data;
int i;
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 98e63347f2..6cecd74d58 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -732,6 +732,11 @@ void pc_machine_done(Notifier *notifier, void *data)
PCMachineState *pcms = container_of(notifier,
PCMachineState, machine_done);
X86MachineState *x86ms = X86_MACHINE(pcms);
+ MachineState *ms = MACHINE(pcms);
+
+ if (ms->cxl_devices_state) {
+ cxl_fmws_link_targets(ms->cxl_devices_state, &error_fatal);
+ }
/* set the number of CPUs */
x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h
index 84078a484d..134b295b40 100644
--- a/include/hw/cxl/cxl.h
+++ b/include/hw/cxl/cxl.h
@@ -53,6 +53,4 @@ struct CXLHost {
#define TYPE_PXB_CXL_HOST "pxb-cxl-host"
OBJECT_DECLARE_SIMPLE_TYPE(CXLHost, PXB_CXL_HOST)
-void cxl_fixed_memory_window_link_targets(Error **errp);
-
#endif
diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h
index 87a6933de2..4d642a81fa 100644
--- a/include/hw/cxl/cxl_host.h
+++ b/include/hw/cxl/cxl_host.h
@@ -15,6 +15,7 @@
#define CXL_HOST_H
void cxl_machine_init(Object *obj, CXLState *state);
+void cxl_fmws_link_targets(CXLState *stat, Error **errp);
extern const MemoryRegionOps cfmws_ops;
diff --git a/softmmu/vl.c b/softmmu/vl.c
index 10d50a2af1..ecef75b77b 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -93,7 +93,6 @@
#include "qemu/config-file.h"
#include "qemu/qemu-options.h"
#include "qemu/main-loop.h"
-#include "hw/cxl/cxl.h"
#ifdef CONFIG_VIRTFS
#include "fsdev/qemu-fsdev.h"
#endif
@@ -2665,7 +2664,6 @@ void qmp_x_exit_preconfig(Error **errp)
qemu_init_board();
qemu_create_cli_devices();
- cxl_fixed_memory_window_link_targets(errp);
qemu_machine_creation_done();
if (loadvm) {
--
2.32.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 4/8] tests/acpi: Allow modification of q35 CXL CEDT table.
2022-05-30 13:45 ` Jonathan Cameron
@ 2022-05-30 13:45 ` Jonathan Cameron
-1 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron via @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
Needed to allow memory address changes as a result of next patch.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..effa58b75b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/CEDT.cxl",
--
2.32.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 4/8] tests/acpi: Allow modification of q35 CXL CEDT table.
@ 2022-05-30 13:45 ` Jonathan Cameron
0 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
Needed to allow memory address changes as a result of next patch.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..effa58b75b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/CEDT.cxl",
--
2.32.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 5/8] pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.
2022-05-30 13:45 ` Jonathan Cameron
@ 2022-05-30 13:45 ` Jonathan Cameron
-1 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron via @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
As the CXLState will no long be accessible via MachineState
at time of PXB_CXL realization, come back later from the machine specific
code to fill in the missing memory region setup. Only at this stage
is it possible to check if cxl=on, so that check is moved to this
later point.
Note that for multiple host bridges, the allocation order of the
register spaces is changed. This will be reflected in ACPI CEDT.
Stubs are added to handle case of CONFIG_PXB=n for machines that
call these functions.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/i386/pc.c | 17 +++++++++++
hw/pci-bridge/meson.build | 5 +++-
hw/pci-bridge/pci_expander_bridge.c | 32 +++++++++++++--------
hw/pci-bridge/pci_expander_bridge_stubs.c | 14 +++++++++
include/hw/pci-bridge/pci_expander_bridge.h | 12 ++++++++
5 files changed, 67 insertions(+), 13 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 6cecd74d58..88b5454aaf 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -37,6 +37,7 @@
#include "hw/ide.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
+#include "hw/pci-bridge/pci_expander_bridge.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/timer/hpet.h"
#include "hw/firmware/smbios.h"
@@ -733,7 +734,23 @@ void pc_machine_done(Notifier *notifier, void *data)
PCMachineState, machine_done);
X86MachineState *x86ms = X86_MACHINE(pcms);
MachineState *ms = MACHINE(pcms);
+ PCIBus *bus = pcms->bus;
+ /* Walk the pci busses looking for pxb busses to hook up */
+ if (bus) {
+ QLIST_FOREACH(bus, &bus->child, sibling) {
+ if (!pci_bus_is_root(bus)) {
+ continue;
+ }
+ if (pci_bus_is_cxl(bus)) {
+ if (!ms->cxl_devices_state->is_enabled) {
+ error_report("CXL host bridges present, but cxl=off");
+ exit(EXIT_FAILURE);
+ }
+ pxb_cxl_hook_up_registers(ms->cxl_devices_state, bus, &error_fatal);
+ }
+ }
+ }
if (ms->cxl_devices_state) {
cxl_fmws_link_targets(ms->cxl_devices_state, &error_fatal);
}
diff --git a/hw/pci-bridge/meson.build b/hw/pci-bridge/meson.build
index b6d26a03d5..fdbe2e07c5 100644
--- a/hw/pci-bridge/meson.build
+++ b/hw/pci-bridge/meson.build
@@ -3,7 +3,8 @@ pci_ss.add(files('pci_bridge_dev.c'))
pci_ss.add(when: 'CONFIG_I82801B11', if_true: files('i82801b11.c'))
pci_ss.add(when: 'CONFIG_IOH3420', if_true: files('ioh3420.c'))
pci_ss.add(when: 'CONFIG_PCIE_PORT', if_true: files('pcie_root_port.c', 'gen_pcie_root_port.c', 'pcie_pci_bridge.c'))
-pci_ss.add(when: 'CONFIG_PXB', if_true: files('pci_expander_bridge.c'))
+pci_ss.add(when: 'CONFIG_PXB', if_true: files('pci_expander_bridge.c'),
+ if_false: files('pci_expander_bridge_stubs.c'))
pci_ss.add(when: 'CONFIG_XIO3130', if_true: files('xio3130_upstream.c', 'xio3130_downstream.c'))
pci_ss.add(when: 'CONFIG_CXL', if_true: files('cxl_root_port.c'))
@@ -13,3 +14,5 @@ pci_ss.add(when: 'CONFIG_DEC_PCI', if_true: files('dec.c'))
pci_ss.add(when: 'CONFIG_SIMBA', if_true: files('simba.c'))
softmmu_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss)
+
+softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('pci_expander_bridge_stubs.c'))
diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c
index 02032360f5..c9e817aa58 100644
--- a/hw/pci-bridge/pci_expander_bridge.c
+++ b/hw/pci-bridge/pci_expander_bridge.c
@@ -17,6 +17,7 @@
#include "hw/pci/pci_host.h"
#include "hw/qdev-properties.h"
#include "hw/pci/pci_bridge.h"
+#include "hw/pci-bridge/pci_expander_bridge.h"
#include "hw/cxl/cxl.h"
#include "qemu/range.h"
#include "qemu/error-report.h"
@@ -186,25 +187,38 @@ static const TypeInfo pxb_host_info = {
static void pxb_cxl_realize(DeviceState *dev, Error **errp)
{
- MachineState *ms = MACHINE(qdev_get_machine());
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
CXLHost *cxl = PXB_CXL_HOST(dev);
CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
struct MemoryRegion *mr = &cxl_cstate->crb.component_registers;
- hwaddr offset;
cxl_component_register_block_init(OBJECT(dev), cxl_cstate,
TYPE_PXB_CXL_HOST);
sysbus_init_mmio(sbd, mr);
+}
+
+/*
+ * Host bridge realization has no means of knowning state associated
+ * with a particular machine. As such, it is nececssary to delay
+ * final setup of the host bridge register space until later in the
+ * machine bring up.
+ */
+void pxb_cxl_hook_up_registers(CXLState *cxl_state, PCIBus *bus, Error **errp)
+{
+ PXBDev *pxb = PXB_CXL_DEV(pci_bridge_get_device(bus));
+ CXLHost *cxl = pxb->cxl.cxl_host_bridge;
+ CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
+ struct MemoryRegion *mr = &cxl_cstate->crb.component_registers;
+ hwaddr offset;
- offset = memory_region_size(mr) * ms->cxl_devices_state->next_mr_idx;
- if (offset > memory_region_size(&ms->cxl_devices_state->host_mr)) {
+ offset = memory_region_size(mr) * cxl_state->next_mr_idx;
+ if (offset > memory_region_size(&cxl_state->host_mr)) {
error_setg(errp, "Insufficient space for pxb cxl host register space");
return;
}
- memory_region_add_subregion(&ms->cxl_devices_state->host_mr, offset, mr);
- ms->cxl_devices_state->next_mr_idx++;
+ memory_region_add_subregion(&cxl_state->host_mr, offset, mr);
+ cxl_state->next_mr_idx++;
}
static void pxb_cxl_host_class_init(ObjectClass *class, void *data)
@@ -461,17 +475,11 @@ static const TypeInfo pxb_pcie_dev_info = {
static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp)
{
- MachineState *ms = MACHINE(qdev_get_machine());
-
/* A CXL PXB's parent bus is still PCIe */
if (!pci_bus_is_express(pci_get_bus(dev))) {
error_setg(errp, "pxb-cxl devices cannot reside on a PCI bus");
return;
}
- if (!ms->cxl_devices_state || !ms->cxl_devices_state->is_enabled) {
- error_setg(errp, "Machine does not have cxl=on");
- return;
- }
pxb_dev_realize_common(dev, CXL, errp);
pxb_dev_reset(DEVICE(dev));
diff --git a/hw/pci-bridge/pci_expander_bridge_stubs.c b/hw/pci-bridge/pci_expander_bridge_stubs.c
new file mode 100644
index 0000000000..b35180311f
--- /dev/null
+++ b/hw/pci-bridge/pci_expander_bridge_stubs.c
@@ -0,0 +1,14 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Stubs for calls made from machines to handle the case where CONFIG_PXB
+ * is not enabled.
+ */
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/pci/pci.h"
+#include "hw/pci/pci_bus.h"
+#include "hw/pci-bridge/pci_expander_bridge.h"
+#include "hw/cxl/cxl.h"
+
+void pxb_cxl_hook_up_registers(CXLState *state, PCIBus *bus, Error **errp) {};
diff --git a/include/hw/pci-bridge/pci_expander_bridge.h b/include/hw/pci-bridge/pci_expander_bridge.h
new file mode 100644
index 0000000000..0b3856d615
--- /dev/null
+++ b/include/hw/pci-bridge/pci_expander_bridge.h
@@ -0,0 +1,12 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef PCI_EXPANDER_BRIDGE_H
+#define PCI_EXPANDER_BRIDGE_H
+
+#include "hw/cxl/cxl.h"
+
+void pxb_cxl_hook_up_registers(CXLState *state, PCIBus *bus, Error **errp);
+
+#endif /* PCI_EXPANDER_BRIDGE_H */
--
2.32.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 5/8] pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.
@ 2022-05-30 13:45 ` Jonathan Cameron
0 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
As the CXLState will no long be accessible via MachineState
at time of PXB_CXL realization, come back later from the machine specific
code to fill in the missing memory region setup. Only at this stage
is it possible to check if cxl=on, so that check is moved to this
later point.
Note that for multiple host bridges, the allocation order of the
register spaces is changed. This will be reflected in ACPI CEDT.
Stubs are added to handle case of CONFIG_PXB=n for machines that
call these functions.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/i386/pc.c | 17 +++++++++++
hw/pci-bridge/meson.build | 5 +++-
hw/pci-bridge/pci_expander_bridge.c | 32 +++++++++++++--------
hw/pci-bridge/pci_expander_bridge_stubs.c | 14 +++++++++
include/hw/pci-bridge/pci_expander_bridge.h | 12 ++++++++
5 files changed, 67 insertions(+), 13 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 6cecd74d58..88b5454aaf 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -37,6 +37,7 @@
#include "hw/ide.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
+#include "hw/pci-bridge/pci_expander_bridge.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/timer/hpet.h"
#include "hw/firmware/smbios.h"
@@ -733,7 +734,23 @@ void pc_machine_done(Notifier *notifier, void *data)
PCMachineState, machine_done);
X86MachineState *x86ms = X86_MACHINE(pcms);
MachineState *ms = MACHINE(pcms);
+ PCIBus *bus = pcms->bus;
+ /* Walk the pci busses looking for pxb busses to hook up */
+ if (bus) {
+ QLIST_FOREACH(bus, &bus->child, sibling) {
+ if (!pci_bus_is_root(bus)) {
+ continue;
+ }
+ if (pci_bus_is_cxl(bus)) {
+ if (!ms->cxl_devices_state->is_enabled) {
+ error_report("CXL host bridges present, but cxl=off");
+ exit(EXIT_FAILURE);
+ }
+ pxb_cxl_hook_up_registers(ms->cxl_devices_state, bus, &error_fatal);
+ }
+ }
+ }
if (ms->cxl_devices_state) {
cxl_fmws_link_targets(ms->cxl_devices_state, &error_fatal);
}
diff --git a/hw/pci-bridge/meson.build b/hw/pci-bridge/meson.build
index b6d26a03d5..fdbe2e07c5 100644
--- a/hw/pci-bridge/meson.build
+++ b/hw/pci-bridge/meson.build
@@ -3,7 +3,8 @@ pci_ss.add(files('pci_bridge_dev.c'))
pci_ss.add(when: 'CONFIG_I82801B11', if_true: files('i82801b11.c'))
pci_ss.add(when: 'CONFIG_IOH3420', if_true: files('ioh3420.c'))
pci_ss.add(when: 'CONFIG_PCIE_PORT', if_true: files('pcie_root_port.c', 'gen_pcie_root_port.c', 'pcie_pci_bridge.c'))
-pci_ss.add(when: 'CONFIG_PXB', if_true: files('pci_expander_bridge.c'))
+pci_ss.add(when: 'CONFIG_PXB', if_true: files('pci_expander_bridge.c'),
+ if_false: files('pci_expander_bridge_stubs.c'))
pci_ss.add(when: 'CONFIG_XIO3130', if_true: files('xio3130_upstream.c', 'xio3130_downstream.c'))
pci_ss.add(when: 'CONFIG_CXL', if_true: files('cxl_root_port.c'))
@@ -13,3 +14,5 @@ pci_ss.add(when: 'CONFIG_DEC_PCI', if_true: files('dec.c'))
pci_ss.add(when: 'CONFIG_SIMBA', if_true: files('simba.c'))
softmmu_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss)
+
+softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('pci_expander_bridge_stubs.c'))
diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c
index 02032360f5..c9e817aa58 100644
--- a/hw/pci-bridge/pci_expander_bridge.c
+++ b/hw/pci-bridge/pci_expander_bridge.c
@@ -17,6 +17,7 @@
#include "hw/pci/pci_host.h"
#include "hw/qdev-properties.h"
#include "hw/pci/pci_bridge.h"
+#include "hw/pci-bridge/pci_expander_bridge.h"
#include "hw/cxl/cxl.h"
#include "qemu/range.h"
#include "qemu/error-report.h"
@@ -186,25 +187,38 @@ static const TypeInfo pxb_host_info = {
static void pxb_cxl_realize(DeviceState *dev, Error **errp)
{
- MachineState *ms = MACHINE(qdev_get_machine());
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
CXLHost *cxl = PXB_CXL_HOST(dev);
CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
struct MemoryRegion *mr = &cxl_cstate->crb.component_registers;
- hwaddr offset;
cxl_component_register_block_init(OBJECT(dev), cxl_cstate,
TYPE_PXB_CXL_HOST);
sysbus_init_mmio(sbd, mr);
+}
+
+/*
+ * Host bridge realization has no means of knowning state associated
+ * with a particular machine. As such, it is nececssary to delay
+ * final setup of the host bridge register space until later in the
+ * machine bring up.
+ */
+void pxb_cxl_hook_up_registers(CXLState *cxl_state, PCIBus *bus, Error **errp)
+{
+ PXBDev *pxb = PXB_CXL_DEV(pci_bridge_get_device(bus));
+ CXLHost *cxl = pxb->cxl.cxl_host_bridge;
+ CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
+ struct MemoryRegion *mr = &cxl_cstate->crb.component_registers;
+ hwaddr offset;
- offset = memory_region_size(mr) * ms->cxl_devices_state->next_mr_idx;
- if (offset > memory_region_size(&ms->cxl_devices_state->host_mr)) {
+ offset = memory_region_size(mr) * cxl_state->next_mr_idx;
+ if (offset > memory_region_size(&cxl_state->host_mr)) {
error_setg(errp, "Insufficient space for pxb cxl host register space");
return;
}
- memory_region_add_subregion(&ms->cxl_devices_state->host_mr, offset, mr);
- ms->cxl_devices_state->next_mr_idx++;
+ memory_region_add_subregion(&cxl_state->host_mr, offset, mr);
+ cxl_state->next_mr_idx++;
}
static void pxb_cxl_host_class_init(ObjectClass *class, void *data)
@@ -461,17 +475,11 @@ static const TypeInfo pxb_pcie_dev_info = {
static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp)
{
- MachineState *ms = MACHINE(qdev_get_machine());
-
/* A CXL PXB's parent bus is still PCIe */
if (!pci_bus_is_express(pci_get_bus(dev))) {
error_setg(errp, "pxb-cxl devices cannot reside on a PCI bus");
return;
}
- if (!ms->cxl_devices_state || !ms->cxl_devices_state->is_enabled) {
- error_setg(errp, "Machine does not have cxl=on");
- return;
- }
pxb_dev_realize_common(dev, CXL, errp);
pxb_dev_reset(DEVICE(dev));
diff --git a/hw/pci-bridge/pci_expander_bridge_stubs.c b/hw/pci-bridge/pci_expander_bridge_stubs.c
new file mode 100644
index 0000000000..b35180311f
--- /dev/null
+++ b/hw/pci-bridge/pci_expander_bridge_stubs.c
@@ -0,0 +1,14 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Stubs for calls made from machines to handle the case where CONFIG_PXB
+ * is not enabled.
+ */
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/pci/pci.h"
+#include "hw/pci/pci_bus.h"
+#include "hw/pci-bridge/pci_expander_bridge.h"
+#include "hw/cxl/cxl.h"
+
+void pxb_cxl_hook_up_registers(CXLState *state, PCIBus *bus, Error **errp) {};
diff --git a/include/hw/pci-bridge/pci_expander_bridge.h b/include/hw/pci-bridge/pci_expander_bridge.h
new file mode 100644
index 0000000000..0b3856d615
--- /dev/null
+++ b/include/hw/pci-bridge/pci_expander_bridge.h
@@ -0,0 +1,12 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef PCI_EXPANDER_BRIDGE_H
+#define PCI_EXPANDER_BRIDGE_H
+
+#include "hw/cxl/cxl.h"
+
+void pxb_cxl_hook_up_registers(CXLState *state, PCIBus *bus, Error **errp);
+
+#endif /* PCI_EXPANDER_BRIDGE_H */
--
2.32.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 6/8] tests/acpi: Update q35/CEDT.cxl for new memory addresses.
2022-05-30 13:45 ` Jonathan Cameron
@ 2022-05-30 13:45 ` Jonathan Cameron
-1 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron via @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
The CEDT table includes addreses of host bridge registers.
There are allocated in a different order due to the previous
patch, so update to the table is needed.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
tests/data/acpi/q35/CEDT.cxl | Bin 184 -> 184 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
2 files changed, 1 deletion(-)
diff --git a/tests/data/acpi/q35/CEDT.cxl b/tests/data/acpi/q35/CEDT.cxl
index b8fa06b00e65712e91e0a5ea0d9277e0146d1c00..ff8203af070241bd23dd0eb8a51460692bb7d229 100644
GIT binary patch
delta 18
acmdnNxPx(m*~Boui7rAD&G;s!ga80Nd<HWB
delta 18
acmdnNxPx(m*~Boui7rAD&G;s!ga80Nd<HWB
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index effa58b75b..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/CEDT.cxl",
--
2.32.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 6/8] tests/acpi: Update q35/CEDT.cxl for new memory addresses.
@ 2022-05-30 13:45 ` Jonathan Cameron
0 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
The CEDT table includes addreses of host bridge registers.
There are allocated in a different order due to the previous
patch, so update to the table is needed.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
tests/data/acpi/q35/CEDT.cxl | Bin 184 -> 184 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
2 files changed, 1 deletion(-)
diff --git a/tests/data/acpi/q35/CEDT.cxl b/tests/data/acpi/q35/CEDT.cxl
index b8fa06b00e65712e91e0a5ea0d9277e0146d1c00..ff8203af070241bd23dd0eb8a51460692bb7d229 100644
GIT binary patch
delta 18
acmdnNxPx(m*~Boui7rAD&G;s!ga80Nd<HWB
delta 18
acmdnNxPx(m*~Boui7rAD&G;s!ga80Nd<HWB
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index effa58b75b..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/CEDT.cxl",
--
2.32.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 7/8] hw/cxl: Move the CXLState from MachineState to machine type specific state.
2022-05-30 13:45 ` Jonathan Cameron
@ 2022-05-30 13:45 ` Jonathan Cameron
-1 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron via @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
This removes the last of the CXL code from the MachineState where it
is visible to all Machines to only those that support CXL (currently i386/pc)
As i386/pc always support CXL now, stop allocating the state independently.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/core/machine.c | 6 ------
hw/i386/acpi-build.c | 6 +++---
hw/i386/pc.c | 32 +++++++++++++++-----------------
include/hw/boards.h | 1 -
include/hw/i386/pc.h | 2 ++
5 files changed, 20 insertions(+), 27 deletions(-)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 87787b5604..eb3f1b5302 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -33,7 +33,6 @@
#include "sysemu/qtest.h"
#include "hw/pci/pci.h"
#include "hw/mem/nvdimm.h"
-#include "hw/cxl/cxl.h"
#include "migration/global_state.h"
#include "migration/vmstate.h"
#include "exec/confidential-guest-support.h"
@@ -1074,10 +1073,6 @@ static void machine_initfn(Object *obj)
"Valid values are cpu, mem-ctrl");
}
- if (mc->cxl_supported) {
- ms->cxl_devices_state = g_new0(CXLState, 1);
- }
-
if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) {
ms->numa_state = g_new0(NumaState, 1);
object_property_add_bool(obj, "hmat",
@@ -1115,7 +1110,6 @@ static void machine_finalize(Object *obj)
g_free(ms->device_memory);
g_free(ms->nvdimms_state);
g_free(ms->numa_state);
- g_free(ms->cxl_devices_state);
}
bool machine_usb(MachineState *machine)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 2e3b1dd9a2..e8b7844841 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1633,7 +1633,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
/* Handle the ranges for the PXB expanders */
if (pci_bus_is_cxl(bus)) {
- MemoryRegion *mr = &machine->cxl_devices_state->host_mr;
+ MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
uint64_t base = mr->addr;
cxl_present = true;
@@ -2711,9 +2711,9 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
machine->nvdimms_state, machine->ram_slots,
x86ms->oem_id, x86ms->oem_table_id);
}
- if (machine->cxl_devices_state->is_enabled) {
+ if (pcms->cxl_devices_state.is_enabled) {
cxl_build_cedt(table_offsets, tables_blob, tables->linker,
- x86ms->oem_id, x86ms->oem_table_id, machine->cxl_devices_state);
+ x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state);
}
acpi_add_table(table_offsets, tables_blob);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 88b5454aaf..19420b043b 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -733,7 +733,6 @@ void pc_machine_done(Notifier *notifier, void *data)
PCMachineState *pcms = container_of(notifier,
PCMachineState, machine_done);
X86MachineState *x86ms = X86_MACHINE(pcms);
- MachineState *ms = MACHINE(pcms);
PCIBus *bus = pcms->bus;
/* Walk the pci busses looking for pxb busses to hook up */
@@ -743,16 +742,16 @@ void pc_machine_done(Notifier *notifier, void *data)
continue;
}
if (pci_bus_is_cxl(bus)) {
- if (!ms->cxl_devices_state->is_enabled) {
+ if (!pcms->cxl_devices_state.is_enabled) {
error_report("CXL host bridges present, but cxl=off");
exit(EXIT_FAILURE);
}
- pxb_cxl_hook_up_registers(ms->cxl_devices_state, bus, &error_fatal);
+ pxb_cxl_hook_up_registers(&pcms->cxl_devices_state, bus, &error_fatal);
}
}
}
- if (ms->cxl_devices_state) {
- cxl_fmws_link_targets(ms->cxl_devices_state, &error_fatal);
+ if (pcms->cxl_devices_state.is_enabled) {
+ cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
}
/* set the number of CPUs */
@@ -922,8 +921,8 @@ void pc_memory_init(PCMachineState *pcms,
&machine->device_memory->mr);
}
- if (machine->cxl_devices_state->is_enabled) {
- MemoryRegion *mr = &machine->cxl_devices_state->host_mr;
+ if (pcms->cxl_devices_state.is_enabled) {
+ MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
hwaddr cxl_size = MiB;
if (pcmc->has_reserved_memory && machine->device_memory->base) {
@@ -941,12 +940,12 @@ void pc_memory_init(PCMachineState *pcms,
memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
memory_region_add_subregion(system_memory, cxl_base, mr);
cxl_resv_end = cxl_base + cxl_size;
- if (machine->cxl_devices_state->fixed_windows) {
+ if (pcms->cxl_devices_state.fixed_windows) {
hwaddr cxl_fmw_base;
GList *it;
cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
- for (it = machine->cxl_devices_state->fixed_windows; it; it = it->next) {
+ for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
CXLFixedWindow *fw = it->data;
fw->base = cxl_fmw_base;
@@ -988,7 +987,7 @@ void pc_memory_init(PCMachineState *pcms,
res_mem_end += memory_region_size(&machine->device_memory->mr);
}
- if (machine->cxl_devices_state->is_enabled) {
+ if (pcms->cxl_devices_state.is_enabled) {
res_mem_end = cxl_resv_end;
}
*val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
@@ -1024,12 +1023,12 @@ uint64_t pc_pci_hole64_start(void)
X86MachineState *x86ms = X86_MACHINE(pcms);
uint64_t hole64_start = 0;
- if (ms->cxl_devices_state->host_mr.addr) {
- hole64_start = ms->cxl_devices_state->host_mr.addr +
- memory_region_size(&ms->cxl_devices_state->host_mr);
- if (ms->cxl_devices_state->fixed_windows) {
+ if (pcms->cxl_devices_state.host_mr.addr) {
+ hole64_start = pcms->cxl_devices_state.host_mr.addr +
+ memory_region_size(&pcms->cxl_devices_state.host_mr);
+ if (pcms->cxl_devices_state.fixed_windows) {
GList *it;
- for (it = ms->cxl_devices_state->fixed_windows; it; it = it->next) {
+ for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
CXLFixedWindow *fw = it->data;
hole64_start = fw->mr.addr + memory_region_size(&fw->mr);
}
@@ -1705,7 +1704,6 @@ static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
static void pc_machine_initfn(Object *obj)
{
PCMachineState *pcms = PC_MACHINE(obj);
- MachineState *ms = MACHINE(obj);
#ifdef CONFIG_VMPORT
pcms->vmport = ON_OFF_AUTO_AUTO;
@@ -1730,7 +1728,7 @@ static void pc_machine_initfn(Object *obj)
pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
OBJECT(pcms->pcspk), "audiodev");
- cxl_machine_init(obj, ms->cxl_devices_state);
+ cxl_machine_init(obj, &pcms->cxl_devices_state);
}
static void pc_machine_reset(MachineState *machine)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index dd9fc56df2..031f5f884d 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -360,7 +360,6 @@ struct MachineState {
CPUArchIdList *possible_cpus;
CpuTopology smp;
struct NVDIMMState *nvdimms_state;
- struct CXLState *cxl_devices_state;
struct NumaState *numa_state;
CXLFixedMemoryWindowOptionsList *cfmws_list;
};
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index ffcac5121e..21be7aff26 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -14,6 +14,7 @@
#include "qom/object.h"
#include "hw/i386/sgx-epc.h"
#include "hw/firmware/smbios.h"
+#include "hw/cxl/cxl.h"
#define HPET_INTCAP "hpet-intcap"
@@ -55,6 +56,7 @@ typedef struct PCMachineState {
hwaddr memhp_io_base;
SGXEPCState sgx_epc;
+ CXLState cxl_devices_state;
} PCMachineState;
#define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
--
2.32.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 7/8] hw/cxl: Move the CXLState from MachineState to machine type specific state.
@ 2022-05-30 13:45 ` Jonathan Cameron
0 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
This removes the last of the CXL code from the MachineState where it
is visible to all Machines to only those that support CXL (currently i386/pc)
As i386/pc always support CXL now, stop allocating the state independently.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/core/machine.c | 6 ------
hw/i386/acpi-build.c | 6 +++---
hw/i386/pc.c | 32 +++++++++++++++-----------------
include/hw/boards.h | 1 -
include/hw/i386/pc.h | 2 ++
5 files changed, 20 insertions(+), 27 deletions(-)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 87787b5604..eb3f1b5302 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -33,7 +33,6 @@
#include "sysemu/qtest.h"
#include "hw/pci/pci.h"
#include "hw/mem/nvdimm.h"
-#include "hw/cxl/cxl.h"
#include "migration/global_state.h"
#include "migration/vmstate.h"
#include "exec/confidential-guest-support.h"
@@ -1074,10 +1073,6 @@ static void machine_initfn(Object *obj)
"Valid values are cpu, mem-ctrl");
}
- if (mc->cxl_supported) {
- ms->cxl_devices_state = g_new0(CXLState, 1);
- }
-
if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) {
ms->numa_state = g_new0(NumaState, 1);
object_property_add_bool(obj, "hmat",
@@ -1115,7 +1110,6 @@ static void machine_finalize(Object *obj)
g_free(ms->device_memory);
g_free(ms->nvdimms_state);
g_free(ms->numa_state);
- g_free(ms->cxl_devices_state);
}
bool machine_usb(MachineState *machine)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 2e3b1dd9a2..e8b7844841 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1633,7 +1633,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
/* Handle the ranges for the PXB expanders */
if (pci_bus_is_cxl(bus)) {
- MemoryRegion *mr = &machine->cxl_devices_state->host_mr;
+ MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
uint64_t base = mr->addr;
cxl_present = true;
@@ -2711,9 +2711,9 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
machine->nvdimms_state, machine->ram_slots,
x86ms->oem_id, x86ms->oem_table_id);
}
- if (machine->cxl_devices_state->is_enabled) {
+ if (pcms->cxl_devices_state.is_enabled) {
cxl_build_cedt(table_offsets, tables_blob, tables->linker,
- x86ms->oem_id, x86ms->oem_table_id, machine->cxl_devices_state);
+ x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state);
}
acpi_add_table(table_offsets, tables_blob);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 88b5454aaf..19420b043b 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -733,7 +733,6 @@ void pc_machine_done(Notifier *notifier, void *data)
PCMachineState *pcms = container_of(notifier,
PCMachineState, machine_done);
X86MachineState *x86ms = X86_MACHINE(pcms);
- MachineState *ms = MACHINE(pcms);
PCIBus *bus = pcms->bus;
/* Walk the pci busses looking for pxb busses to hook up */
@@ -743,16 +742,16 @@ void pc_machine_done(Notifier *notifier, void *data)
continue;
}
if (pci_bus_is_cxl(bus)) {
- if (!ms->cxl_devices_state->is_enabled) {
+ if (!pcms->cxl_devices_state.is_enabled) {
error_report("CXL host bridges present, but cxl=off");
exit(EXIT_FAILURE);
}
- pxb_cxl_hook_up_registers(ms->cxl_devices_state, bus, &error_fatal);
+ pxb_cxl_hook_up_registers(&pcms->cxl_devices_state, bus, &error_fatal);
}
}
}
- if (ms->cxl_devices_state) {
- cxl_fmws_link_targets(ms->cxl_devices_state, &error_fatal);
+ if (pcms->cxl_devices_state.is_enabled) {
+ cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
}
/* set the number of CPUs */
@@ -922,8 +921,8 @@ void pc_memory_init(PCMachineState *pcms,
&machine->device_memory->mr);
}
- if (machine->cxl_devices_state->is_enabled) {
- MemoryRegion *mr = &machine->cxl_devices_state->host_mr;
+ if (pcms->cxl_devices_state.is_enabled) {
+ MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
hwaddr cxl_size = MiB;
if (pcmc->has_reserved_memory && machine->device_memory->base) {
@@ -941,12 +940,12 @@ void pc_memory_init(PCMachineState *pcms,
memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
memory_region_add_subregion(system_memory, cxl_base, mr);
cxl_resv_end = cxl_base + cxl_size;
- if (machine->cxl_devices_state->fixed_windows) {
+ if (pcms->cxl_devices_state.fixed_windows) {
hwaddr cxl_fmw_base;
GList *it;
cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
- for (it = machine->cxl_devices_state->fixed_windows; it; it = it->next) {
+ for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
CXLFixedWindow *fw = it->data;
fw->base = cxl_fmw_base;
@@ -988,7 +987,7 @@ void pc_memory_init(PCMachineState *pcms,
res_mem_end += memory_region_size(&machine->device_memory->mr);
}
- if (machine->cxl_devices_state->is_enabled) {
+ if (pcms->cxl_devices_state.is_enabled) {
res_mem_end = cxl_resv_end;
}
*val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
@@ -1024,12 +1023,12 @@ uint64_t pc_pci_hole64_start(void)
X86MachineState *x86ms = X86_MACHINE(pcms);
uint64_t hole64_start = 0;
- if (ms->cxl_devices_state->host_mr.addr) {
- hole64_start = ms->cxl_devices_state->host_mr.addr +
- memory_region_size(&ms->cxl_devices_state->host_mr);
- if (ms->cxl_devices_state->fixed_windows) {
+ if (pcms->cxl_devices_state.host_mr.addr) {
+ hole64_start = pcms->cxl_devices_state.host_mr.addr +
+ memory_region_size(&pcms->cxl_devices_state.host_mr);
+ if (pcms->cxl_devices_state.fixed_windows) {
GList *it;
- for (it = ms->cxl_devices_state->fixed_windows; it; it = it->next) {
+ for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
CXLFixedWindow *fw = it->data;
hole64_start = fw->mr.addr + memory_region_size(&fw->mr);
}
@@ -1705,7 +1704,6 @@ static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
static void pc_machine_initfn(Object *obj)
{
PCMachineState *pcms = PC_MACHINE(obj);
- MachineState *ms = MACHINE(obj);
#ifdef CONFIG_VMPORT
pcms->vmport = ON_OFF_AUTO_AUTO;
@@ -1730,7 +1728,7 @@ static void pc_machine_initfn(Object *obj)
pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
OBJECT(pcms->pcspk), "audiodev");
- cxl_machine_init(obj, ms->cxl_devices_state);
+ cxl_machine_init(obj, &pcms->cxl_devices_state);
}
static void pc_machine_reset(MachineState *machine)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index dd9fc56df2..031f5f884d 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -360,7 +360,6 @@ struct MachineState {
CPUArchIdList *possible_cpus;
CpuTopology smp;
struct NVDIMMState *nvdimms_state;
- struct CXLState *cxl_devices_state;
struct NumaState *numa_state;
CXLFixedMemoryWindowOptionsList *cfmws_list;
};
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index ffcac5121e..21be7aff26 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -14,6 +14,7 @@
#include "qom/object.h"
#include "hw/i386/sgx-epc.h"
#include "hw/firmware/smbios.h"
+#include "hw/cxl/cxl.h"
#define HPET_INTCAP "hpet-intcap"
@@ -55,6 +56,7 @@ typedef struct PCMachineState {
hwaddr memhp_io_base;
SGXEPCState sgx_epc;
+ CXLState cxl_devices_state;
} PCMachineState;
#define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
--
2.32.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 8/8] hw/machine: Drop cxl_supported flag as no longer useful
2022-05-30 13:45 ` Jonathan Cameron
@ 2022-05-30 13:45 ` Jonathan Cameron
-1 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron via @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
As all the CXL elements have moved to boards that support
CXL, there is no need to maintain a top level flag.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/i386/pc.c | 1 -
include/hw/boards.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 19420b043b..d530d9eac8 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1817,7 +1817,6 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
mc->nvdimm_supported = true;
mc->smp_props.dies_supported = true;
- mc->cxl_supported = true;
mc->default_ram_id = "pc.ram";
object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 031f5f884d..d94edcef28 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -269,7 +269,6 @@ struct MachineClass {
bool ignore_boot_device_suffixes;
bool smbus_no_migration_support;
bool nvdimm_supported;
- bool cxl_supported;
bool numa_mem_supported;
bool auto_enable_numa;
SMPCompatProps smp_props;
--
2.32.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 8/8] hw/machine: Drop cxl_supported flag as no longer useful
@ 2022-05-30 13:45 ` Jonathan Cameron
0 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron @ 2022-05-30 13:45 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
As all the CXL elements have moved to boards that support
CXL, there is no need to maintain a top level flag.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/i386/pc.c | 1 -
include/hw/boards.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 19420b043b..d530d9eac8 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1817,7 +1817,6 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
mc->nvdimm_supported = true;
mc->smp_props.dies_supported = true;
- mc->cxl_supported = true;
mc->default_ram_id = "pc.ram";
object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 031f5f884d..d94edcef28 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -269,7 +269,6 @@ struct MachineClass {
bool ignore_boot_device_suffixes;
bool smbus_no_migration_support;
bool nvdimm_supported;
- bool cxl_supported;
bool numa_mem_supported;
bool auto_enable_numa;
SMPCompatProps smp_props;
--
2.32.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 1/8] hw/cxl: Make the CXL fixed memory window setup a machine parameter.
2022-05-30 13:45 ` Jonathan Cameron
(?)
@ 2022-05-31 7:26 ` Paolo Bonzini
2022-06-06 17:24 ` Ben Widawsky
-1 siblings, 1 reply; 23+ messages in thread
From: Paolo Bonzini @ 2022-05-31 7:26 UTC (permalink / raw)
To: Jonathan Cameron, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
On 5/30/22 15:45, Jonathan Cameron via wrote:
> + object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow",
> + machine_get_cfmw, machine_set_cfmw,
> + NULL, state);
> + object_property_set_description(obj, "cxl-fmw",
> + "CXL Fixed Memory Window");
Perhaps "CML fixed memory windows (array)" or something like that?
Paolo
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 5/8] pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.
2022-05-30 13:45 ` Jonathan Cameron
(?)
@ 2022-05-31 7:26 ` Paolo Bonzini
-1 siblings, 0 replies; 23+ messages in thread
From: Paolo Bonzini @ 2022-05-31 7:26 UTC (permalink / raw)
To: Jonathan Cameron, qemu-devel, Michael S . Tsirkin
Cc: linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Ben Widawsky,
Shameerali Kolothum Thodi
On 5/30/22 15:45, Jonathan Cameron via wrote:
> + /* Walk the pci busses looking for pxb busses to hook up */
> + if (bus) {
> + QLIST_FOREACH(bus, &bus->child, sibling) {
> + if (!pci_bus_is_root(bus)) {
> + continue;
> + }
> + if (pci_bus_is_cxl(bus)) {
> + if (!ms->cxl_devices_state->is_enabled) {
> + error_report("CXL host bridges present, but cxl=off");
> + exit(EXIT_FAILURE);
> + }
> + pxb_cxl_hook_up_registers(ms->cxl_devices_state, bus, &error_fatal);
> + }
> + }
> + }
Perhaps this loop can be moved to a separate function in cxl_host.h?
Otherwise looks great, thank you very much for the quick reply!
Paolo
> if (ms->cxl_devices_state) {
> cxl_fmws_link_targets(ms->cxl_devices_state, &error_fatal);
> }
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/8] hw/cxl: Make the CXL fixed memory window setup a machine parameter.
2022-05-31 7:26 ` Paolo Bonzini
@ 2022-06-06 17:24 ` Ben Widawsky
2022-06-07 10:02 ` Jonathan Cameron via
0 siblings, 1 reply; 23+ messages in thread
From: Ben Widawsky @ 2022-06-06 17:24 UTC (permalink / raw)
To: Paolo Bonzini
Cc: Jonathan Cameron, qemu-devel, Michael S . Tsirkin, linux-cxl,
linuxarm, alex.bennee, Marcel Apfelbaum, Igor Mammedov,
Markus Armbruster, Mark Cave-Ayland, Adam Manzanares, Tong Zhang,
Shameerali Kolothum Thodi
On 22-05-31 09:26:27, Paolo Bonzini wrote:
> On 5/30/22 15:45, Jonathan Cameron via wrote:
> > + object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow",
> > + machine_get_cfmw, machine_set_cfmw,
> > + NULL, state);
> > + object_property_set_description(obj, "cxl-fmw",
> > + "CXL Fixed Memory Window");
>
> Perhaps "CML fixed memory windows (array)" or something like that?
>
> Paolo
I had a mail which I apparently never sent. I'd like to see 'fmw' renamed, since
that has no decoder ring in any spec that I'm aware of.
Why not keep cfmws nomenclature? It's well defined.
Ben
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/8] hw/cxl: Make the CXL fixed memory window setup a machine parameter.
2022-06-06 17:24 ` Ben Widawsky
@ 2022-06-07 10:02 ` Jonathan Cameron via
0 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron @ 2022-06-07 10:02 UTC (permalink / raw)
To: Ben Widawsky
Cc: Paolo Bonzini, qemu-devel, Michael S . Tsirkin, linux-cxl,
linuxarm, alex.bennee, Marcel Apfelbaum, Igor Mammedov,
Markus Armbruster, Mark Cave-Ayland, Adam Manzanares, Tong Zhang,
Shameerali Kolothum Thodi
On Mon, 6 Jun 2022 10:24:43 -0700
Ben Widawsky <bwidawsk@kernel.org> wrote:
> On 22-05-31 09:26:27, Paolo Bonzini wrote:
> > On 5/30/22 15:45, Jonathan Cameron via wrote:
> > > + object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow",
> > > + machine_get_cfmw, machine_set_cfmw,
> > > + NULL, state);
> > > + object_property_set_description(obj, "cxl-fmw",
> > > + "CXL Fixed Memory Window");
> >
> > Perhaps "CML fixed memory windows (array)" or something like that?
> >
> > Paolo
>
> I had a mail which I apparently never sent. I'd like to see 'fmw' renamed, since
> that has no decoder ring in any spec that I'm aware of.
>
> Why not keep cfmws nomenclature? It's well defined.
IIRC s is for structure and this isn't a structure, so I dropped the s.
Expanding cxl makes this a lot more meaningful outside of CXL related
specifications. I preferred the full wording as is currently upstream
but the command lines are insanely long given the new form.
Jonathan
>
> Ben
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/8] hw/cxl: Make the CXL fixed memory window setup a machine parameter.
@ 2022-06-07 10:02 ` Jonathan Cameron via
0 siblings, 0 replies; 23+ messages in thread
From: Jonathan Cameron via @ 2022-06-07 10:02 UTC (permalink / raw)
To: Ben Widawsky
Cc: Paolo Bonzini, qemu-devel, Michael S . Tsirkin, linux-cxl,
linuxarm, alex.bennee, Marcel Apfelbaum, Igor Mammedov,
Markus Armbruster, Mark Cave-Ayland, Adam Manzanares, Tong Zhang,
Shameerali Kolothum Thodi
On Mon, 6 Jun 2022 10:24:43 -0700
Ben Widawsky <bwidawsk@kernel.org> wrote:
> On 22-05-31 09:26:27, Paolo Bonzini wrote:
> > On 5/30/22 15:45, Jonathan Cameron via wrote:
> > > + object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow",
> > > + machine_get_cfmw, machine_set_cfmw,
> > > + NULL, state);
> > > + object_property_set_description(obj, "cxl-fmw",
> > > + "CXL Fixed Memory Window");
> >
> > Perhaps "CML fixed memory windows (array)" or something like that?
> >
> > Paolo
>
> I had a mail which I apparently never sent. I'd like to see 'fmw' renamed, since
> that has no decoder ring in any spec that I'm aware of.
>
> Why not keep cfmws nomenclature? It's well defined.
IIRC s is for structure and this isn't a structure, so I dropped the s.
Expanding cxl makes this a lot more meaningful outside of CXL related
specifications. I preferred the full wording as is currently upstream
but the command lines are insanely long given the new form.
Jonathan
>
> Ben
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2022-06-07 10:37 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-30 13:45 [PATCH 0/8] hw/cxl: Move CXL emulation options and state to machines Jonathan Cameron via
2022-05-30 13:45 ` Jonathan Cameron
2022-05-30 13:45 ` [PATCH 1/8] hw/cxl: Make the CXL fixed memory window setup a machine parameter Jonathan Cameron via
2022-05-30 13:45 ` Jonathan Cameron
2022-05-31 7:26 ` Paolo Bonzini
2022-06-06 17:24 ` Ben Widawsky
2022-06-07 10:02 ` Jonathan Cameron
2022-06-07 10:02 ` Jonathan Cameron via
2022-05-30 13:45 ` [PATCH 2/8] hw/acpi/cxl: Pass in the CXLState directly rather than MachineState Jonathan Cameron via
2022-05-30 13:45 ` Jonathan Cameron
2022-05-30 13:45 ` [PATCH 3/8] hw/cxl: Push linking of CXL targets into i386/pc rather than in machine.c Jonathan Cameron via
2022-05-30 13:45 ` Jonathan Cameron
2022-05-30 13:45 ` [PATCH 4/8] tests/acpi: Allow modification of q35 CXL CEDT table Jonathan Cameron via
2022-05-30 13:45 ` Jonathan Cameron
2022-05-30 13:45 ` [PATCH 5/8] pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup Jonathan Cameron via
2022-05-30 13:45 ` Jonathan Cameron
2022-05-31 7:26 ` Paolo Bonzini
2022-05-30 13:45 ` [PATCH 6/8] tests/acpi: Update q35/CEDT.cxl for new memory addresses Jonathan Cameron via
2022-05-30 13:45 ` Jonathan Cameron
2022-05-30 13:45 ` [PATCH 7/8] hw/cxl: Move the CXLState from MachineState to machine type specific state Jonathan Cameron via
2022-05-30 13:45 ` Jonathan Cameron
2022-05-30 13:45 ` [PATCH 8/8] hw/machine: Drop cxl_supported flag as no longer useful Jonathan Cameron via
2022-05-30 13:45 ` Jonathan Cameron
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