From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <bjorn.andersson@linaro.org>, Vinod Koul <vkoul@kernel.org>, Kishon Vijay Abraham I <kishon@ti.com> Cc: Philipp Zabel <p.zabel@pengutronix.de>, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, Johan Hovold <johan@kernel.org> Subject: [RFC PATCH 16/28] phy: qcom-qmp: move PCS V5 registers to separate headers Date: Fri, 10 Jun 2022 22:09:13 +0300 [thread overview] Message-ID: <20220610190925.3670081-17-dmitry.baryshkov@linaro.org> (raw) In-Reply-To: <20220610190925.3670081-1-dmitry.baryshkov@linaro.org> Move PCS V5 registers to the separate headers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 16 +++++ .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 27 ++++++++ .../phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h | 36 +++++++++++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 17 +++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 63 ++----------------- 5 files changed, 101 insertions(+), 58 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h new file mode 100644 index 000000000000..2e19fb3f051e --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h @@ -0,0 +1,16 @@ +/* Only for QMP V5 PHY - PCS_PCIE registers */ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V5_H_ + +/* Only for QMP V5 PHY - PCS_PCIE registers */ +#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 +#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 +#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 +#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h new file mode 100644 index 000000000000..bcca23493b7e --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h @@ -0,0 +1,27 @@ +/* Only for QMP V5 PHY - UFS PCS registers */ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_UFS_V5_H_ +#define QCOM_PHY_QMP_PCS_UFS_V5_H_ + +/* Only for QMP V5 PHY - UFS PCS registers */ +#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c +#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 +#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c +#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 +#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 +#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 +#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 +#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 +#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 +#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 +#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 +#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 +#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 +#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 +#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h new file mode 100644 index 000000000000..73de626223ed --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_USB_V5_H_ +#define QCOM_PHY_QMP_PCS_USB_V5_H_ + +/* Only for QMP V5 PHY - USB3 have different offsets than V4 */ +#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000 +#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 +#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 +#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c +#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 +#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 +#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 +#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c +#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 +#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 +#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028 +#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c +#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030 +#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034 +#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038 +#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c +#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040 +#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044 +#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048 +#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c +#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050 +#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054 +#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058 +#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c +#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h new file mode 100644 index 000000000000..61a44519f969 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_V5_H_ +#define QCOM_PHY_QMP_PCS_V5_H_ + +/* Only for QMP V5 PHY - USB/PCIe PCS registers */ +#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc +#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 +#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 +#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 +#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 05da0725df71..9d93ae785b16 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -30,6 +30,11 @@ #include "phy-qcom-qmp-pcs-usb-v4.h" #include "phy-qcom-qmp-pcs-ufs-v4.h" +#include "phy-qcom-qmp-pcs-v5.h" +#include "phy-qcom-qmp-pcs-pcie-v5.h" +#include "phy-qcom-qmp-pcs-usb-v5.h" +#include "phy-qcom-qmp-pcs-ufs-v5.h" + /* Only for QMP V3 & V4 PHY - DP COM registers */ #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 #define QPHY_V3_DP_COM_SW_RESET 0x04 @@ -334,20 +339,6 @@ #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 -/* Only for QMP V5 PHY - USB/PCIe PCS registers */ -#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc -#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 -#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 -#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 -#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 -#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 - -/* Only for QMP V5 PHY - PCS_PCIE registers */ -#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 -#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 -#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 -#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 - /* Only for QMP V5_20 PHY - PCIe PCS registers */ #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 @@ -356,48 +347,4 @@ #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 -/* Only for QMP V5 PHY - UFS PCS registers */ -#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c -#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 -#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c -#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 -#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 -#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 -#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 -#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 -#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 -#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 -#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 -#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 -#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 -#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 -#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 - -/* Only for QMP V5 PHY - USB3 have different offsets than V4 */ -#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000 -#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 -#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 -#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c -#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 -#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 -#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 -#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c -#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 -#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 -#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028 -#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c -#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030 -#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034 -#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038 -#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c -#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040 -#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044 -#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048 -#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c -#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050 -#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054 -#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058 -#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c -#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060 - #endif -- 2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <bjorn.andersson@linaro.org>, Vinod Koul <vkoul@kernel.org>, Kishon Vijay Abraham I <kishon@ti.com> Cc: Philipp Zabel <p.zabel@pengutronix.de>, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, Johan Hovold <johan@kernel.org> Subject: [RFC PATCH 16/28] phy: qcom-qmp: move PCS V5 registers to separate headers Date: Fri, 10 Jun 2022 22:09:13 +0300 [thread overview] Message-ID: <20220610190925.3670081-17-dmitry.baryshkov@linaro.org> (raw) In-Reply-To: <20220610190925.3670081-1-dmitry.baryshkov@linaro.org> Move PCS V5 registers to the separate headers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 16 +++++ .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 27 ++++++++ .../phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h | 36 +++++++++++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 17 +++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 63 ++----------------- 5 files changed, 101 insertions(+), 58 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h new file mode 100644 index 000000000000..2e19fb3f051e --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h @@ -0,0 +1,16 @@ +/* Only for QMP V5 PHY - PCS_PCIE registers */ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V5_H_ + +/* Only for QMP V5 PHY - PCS_PCIE registers */ +#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 +#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 +#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 +#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h new file mode 100644 index 000000000000..bcca23493b7e --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h @@ -0,0 +1,27 @@ +/* Only for QMP V5 PHY - UFS PCS registers */ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_UFS_V5_H_ +#define QCOM_PHY_QMP_PCS_UFS_V5_H_ + +/* Only for QMP V5 PHY - UFS PCS registers */ +#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c +#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 +#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c +#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 +#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 +#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 +#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 +#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 +#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 +#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 +#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 +#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 +#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 +#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 +#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h new file mode 100644 index 000000000000..73de626223ed --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v5.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_USB_V5_H_ +#define QCOM_PHY_QMP_PCS_USB_V5_H_ + +/* Only for QMP V5 PHY - USB3 have different offsets than V4 */ +#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000 +#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 +#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 +#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c +#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 +#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 +#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 +#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c +#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 +#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 +#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028 +#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c +#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030 +#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034 +#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038 +#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c +#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040 +#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044 +#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048 +#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c +#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050 +#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054 +#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058 +#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c +#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h new file mode 100644 index 000000000000..61a44519f969 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_V5_H_ +#define QCOM_PHY_QMP_PCS_V5_H_ + +/* Only for QMP V5 PHY - USB/PCIe PCS registers */ +#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc +#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 +#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 +#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 +#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 05da0725df71..9d93ae785b16 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -30,6 +30,11 @@ #include "phy-qcom-qmp-pcs-usb-v4.h" #include "phy-qcom-qmp-pcs-ufs-v4.h" +#include "phy-qcom-qmp-pcs-v5.h" +#include "phy-qcom-qmp-pcs-pcie-v5.h" +#include "phy-qcom-qmp-pcs-usb-v5.h" +#include "phy-qcom-qmp-pcs-ufs-v5.h" + /* Only for QMP V3 & V4 PHY - DP COM registers */ #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 #define QPHY_V3_DP_COM_SW_RESET 0x04 @@ -334,20 +339,6 @@ #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 -/* Only for QMP V5 PHY - USB/PCIe PCS registers */ -#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc -#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 -#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 -#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 -#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 -#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 - -/* Only for QMP V5 PHY - PCS_PCIE registers */ -#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 -#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 -#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 -#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 - /* Only for QMP V5_20 PHY - PCIe PCS registers */ #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 @@ -356,48 +347,4 @@ #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 -/* Only for QMP V5 PHY - UFS PCS registers */ -#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c -#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 -#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c -#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 -#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 -#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 -#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 -#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 -#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 -#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 -#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 -#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 -#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 -#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 -#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 - -/* Only for QMP V5 PHY - USB3 have different offsets than V4 */ -#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000 -#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 -#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 -#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c -#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 -#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 -#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 -#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c -#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 -#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 -#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028 -#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c -#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030 -#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034 -#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038 -#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c -#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040 -#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044 -#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048 -#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c -#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050 -#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054 -#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058 -#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c -#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060 - #endif -- 2.35.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2022-06-10 19:09 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-10 19:08 [RFC PATCH 00/28] phy: qcom-qmp: split register tables Dmitry Baryshkov 2022-06-10 19:08 ` Dmitry Baryshkov 2022-06-10 19:08 ` [RFC PATCH 01/28] phy: qcom-qmp: fix the QSERDES_V5_COM_CMN_MODE register Dmitry Baryshkov 2022-06-10 19:08 ` Dmitry Baryshkov 2022-06-10 19:08 ` [RFC PATCH 02/28] phy: qcom-qmp-ufs: remove spurious register write in the msm8996 table Dmitry Baryshkov 2022-06-10 19:08 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 03/28] phy: qcom-qmp-combo,usb: add support for separate PCS_USB region Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 04/28] phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3 Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 05/28] phy: qcom-qmp: drop special QMP V2 PCIE gen3 defines Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 06/28] phy: qcom-qmp: rename QMP V2 PCS registers Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 07/28] phy: qcom-qmp: use QPHY_V4_PCS for ipq6018 PCIe gen3 Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 08/28] phy: qcom-qmp: move QSERDES registers to separate header Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 09/28] phy: qcom-qmp: move QSERDES V3 registers to separate headers Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 10/28] phy: qcom-qmp: move QSERDES V4 " Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 11/28] phy: qcom-qmp: move QSERDES V5 " Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 12/28] phy: qcom-qmp: move QSERDES PLL registers to separate header Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 13/28] phy: qcom-qmp: move PCS V2 " Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 14/28] phy: qcom-qmp: move PCS V3 registers to separate headers Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 15/28] phy: qcom-qmp: move PCS V4 " Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov [this message] 2022-06-10 19:09 ` [RFC PATCH 16/28] phy: qcom-qmp: move PCS V5 " Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 17/28] phy: qcom-qmp: move PCIE QHP registers to separate header Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 18/28] phy: qcom-qmp: split allegedly 4.20 and 5.20 TX/RX registers Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 19/28] phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 20/28] phy: qcom-qmp: split PCS_UFS V3 symbols to separate header Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 21/28] phy: qcom-qmp: qserdes-com: add missing registers Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 22/28] phy: qcom-qmp: qserdes-com-v3: " Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 23/28] phy: qcom-qmp: qserdes-com-v4: " Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 24/28] phy: qcom-qmp: qserdes-com-v5: " Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 25/28] phy: qcom-qmp: pcs-v3: " Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 26/28] phy: qcom-qmp: pcs-pcie-v4: " Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 27/28] phy: qcom-qmp-usb: replace FLL layout writes for msm8996 Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-06-10 19:09 ` [RFC PATCH 28/28] phy: qcom-qmp-usb: define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME register Dmitry Baryshkov 2022-06-10 19:09 ` Dmitry Baryshkov 2022-07-05 7:05 ` [RFC PATCH 00/28] phy: qcom-qmp: split register tables Vinod Koul 2022-07-05 7:05 ` Vinod Koul
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