From: Wangseok Lee <wangseok.lee@samsung.com> To: "robh+dt@kernel.org" <robh+dt@kernel.org>, "krzk+dt@kernel.org" <krzk+dt@kernel.org>, "kishon@ti.com" <kishon@ti.com>, "vkoul@kernel.org" <vkoul@kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "jesper.nilsson@axis.com" <jesper.nilsson@axis.com>, "lars.persson@axis.com" <lars.persson@axis.com>, "bhelgaas@google.com" <bhelgaas@google.com>, "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>, "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>, "kw@linux.com" <kw@linux.com>, "linux-arm-kernel@axis.com" <linux-arm-kernel@axis.com>, "kernel@axis.com" <kernel@axis.com> Cc: Moon-Ki Jun <moonki.jun@samsung.com>, Sang Min Kim <hypmean.kim@samsung.com>, Dongjin Yang <dj76.yang@samsung.com>, Yeeun Kim <yeeun119.kim@samsung.com> Subject: [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Date: Tue, 14 Jun 2022 10:27:13 +0900 [thread overview] Message-ID: <20220614012713epcms2p810386a5137fbcf6aefc41fe086badc0b@epcms2p8> (raw) In-Reply-To: <20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7> Add description to support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC platform of Axis Communications and PCIe controller is designed based on Design-Ware PCIe controller. Signed-off-by: Wangseok Lee <wangseok.lee@samsung.com> --- v2->v3 : - modify version history to fit the linux commit rule - remove 'Device Tree Bindings' on title - remove the interrupt-names, phy-names entries - remove '_clk' suffix - add the compatible entries on required - change node name to soc from artpec8 on examples v1->v2 : -'make dt_binding_check' result improvement -Add the missing property list -Align the indentation of continued lines/entries --- .../bindings/pci/axis,artpec8-pcie-ep.yaml | 109 +++++++++++++++++++ .../devicetree/bindings/pci/axis,artpec8-pcie.yaml | 120 +++++++++++++++++++++ 2 files changed, 229 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml new file mode 100644 index 0000000..d802bba --- /dev/null +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARTPEC-8 SoC PCIe Controller + +maintainers: + - Jesper Nilsson <jesper.nilsson@axis.com> + +description: |+ + This PCIe end-point controller is based on the Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + +properties: + compatible: + const: axis,artpec8-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: Data Bus Interface (DBI2) registers. + - description: PCIe address space region. + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: addr_space + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PIPE clock, used by the controller to clock the PIPE + - description: PCIe dbi clock, ungated version + - description: PCIe master clock, ungated version + - description: PCIe slave clock, ungated version + + clock-names: + items: + - const: pipe + - const: dbi + - const: mstr + - const: slv + + phys: + maxItems: 1 + + num-lanes: + const: 2 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - samsung,fsys-sysreg + - samsung,syscon-phandle + - samsung,syscon-bus-s-fsys + - samsung,syscon-bus-p-fsys + - phys + - num-lanes + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie_ep: pcie-ep@17200000 { + compatible = "axis,artpec8-pcie-ep"; + reg = <0x0 0x17200000 0x0 0x1000>, + <0x0 0x17201000 0x0 0x1000>, + <0x2 0x00000000 0x6 0x00000000>; + reg-names = "dbi", "dbi2", "addr_space"; + #interrupt-cells = <1>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr"; + clocks = <&clock_cmu_fsys 39>, + <&clock_cmu_fsys 38>, + <&clock_cmu_fsys 37>, + <&clock_cmu_fsys 36>; + clock-names = "pipe", "dbi", "mstr", "slv"; + samsung,fsys-sysreg = <&syscon_fsys>; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,syscon-bus-s-fsys = <&syscon_bus_s_fsys>; + samsung,syscon-bus-p-fsys = <&syscon_bus_p_fsys>; + phys = <&pcie_phy>; + phy-names = "pcie_phy"; + num-lanes = <2>; + bus-range = <0x00 0xff>; + num-ib-windows = <16>; + num-ob-windows = <16>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml new file mode 100644 index 0000000..dbbe1fd --- /dev/null +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Artpec-8 SoC PCIe Controller + +maintainers: + - Jesper Nilsson <jesper.nilsson@axis.com> + +description: |+ + This PCIe host controller is based on the Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in snps,dw-pcie.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: axis,artpec8-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: External Local Bus interface (ELBI) registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: dbi + - const: elbi + - const: config + + ranges: + maxItems: 2 + + num-lanes: + const: 2 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PIPE clock, used by the controller to clock the PIPE + - description: PCIe dbi clock, ungated version + - description: PCIe master clock, ungated version + - description: PCIe slave clock, ungated version + + clock-names: + items: + - const: pipe + - const: dbi + - const: mstr + - const: slv + + phys: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - device_type + - ranges + - num-lanes + - interrupts + - interrupt-names + - clocks + - clock-names + - samsung,fsys-sysreg + - samsung,syscon-phandle + - samsung,syscon-bus-s-fsys + - samsung,syscon-bus-p-fsys + - phys + - phy-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie: pcie@17200000 { + compatible = "axis,artpec8-pcie"; + reg = <0x0 0x17200000 0x0 0x1000>, + <0x0 0x16ca0000 0x0 0x2000>, + <0x7 0x0001e000 0x0 0x2000>; + reg-names = "dbi", "elbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = </* non-prefetchable memory */ + 0x83000000 0x0 0x0000000 0x2 0x00000000 0x5 0x00000000 + /* downstream I/O */ + 0x81000000 0x0 0x0000000 0x7 0x00000000 0x0 0x00010000>; + num-lanes = <2>; + bus-range = <0x00 0xff>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr"; + #interrupt-cells = <1>; + clocks = <&cmu_fsys 39>, + <&cmu_fsys 38>, + <&cmu_fsys 37>, + <&cmu_fsys 36>; + clock-names = "pipe", "dbi", "mstr", "slv"; + samsung,fsys-sysreg = <&syscon_fsys>; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,syscon-bus-s-fsys = <&syscon_bus_s_fsys>; + samsung,syscon-bus-p-fsys = <&syscon_bus_p_fsys>; + phys = <&pcie_phy>; + phy-names = "pcie_phy"; + }; + }; +... -- 2.9.5
WARNING: multiple messages have this Message-ID (diff)
From: Wangseok Lee <wangseok.lee@samsung.com> To: "robh+dt@kernel.org" <robh+dt@kernel.org>, "krzk+dt@kernel.org" <krzk+dt@kernel.org>, "kishon@ti.com" <kishon@ti.com>, "vkoul@kernel.org" <vkoul@kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "jesper.nilsson@axis.com" <jesper.nilsson@axis.com>, "lars.persson@axis.com" <lars.persson@axis.com>, "bhelgaas@google.com" <bhelgaas@google.com>, "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>, "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>, "kw@linux.com" <kw@linux.com>, "linux-arm-kernel@axis.com" <linux-arm-kernel@axis.com>, "kernel@axis.com" <kernel@axis.com> Cc: Moon-Ki Jun <moonki.jun@samsung.com>, Sang Min Kim <hypmean.kim@samsung.com>, Dongjin Yang <dj76.yang@samsung.com>, Yeeun Kim <yeeun119.kim@samsung.com> Subject: [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Date: Tue, 14 Jun 2022 10:27:13 +0900 [thread overview] Message-ID: <20220614012713epcms2p810386a5137fbcf6aefc41fe086badc0b@epcms2p8> (raw) In-Reply-To: <20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7> Add description to support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC platform of Axis Communications and PCIe controller is designed based on Design-Ware PCIe controller. Signed-off-by: Wangseok Lee <wangseok.lee@samsung.com> --- v2->v3 : - modify version history to fit the linux commit rule - remove 'Device Tree Bindings' on title - remove the interrupt-names, phy-names entries - remove '_clk' suffix - add the compatible entries on required - change node name to soc from artpec8 on examples v1->v2 : -'make dt_binding_check' result improvement -Add the missing property list -Align the indentation of continued lines/entries --- .../bindings/pci/axis,artpec8-pcie-ep.yaml | 109 +++++++++++++++++++ .../devicetree/bindings/pci/axis,artpec8-pcie.yaml | 120 +++++++++++++++++++++ 2 files changed, 229 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml new file mode 100644 index 0000000..d802bba --- /dev/null +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARTPEC-8 SoC PCIe Controller + +maintainers: + - Jesper Nilsson <jesper.nilsson@axis.com> + +description: |+ + This PCIe end-point controller is based on the Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + +properties: + compatible: + const: axis,artpec8-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: Data Bus Interface (DBI2) registers. + - description: PCIe address space region. + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: addr_space + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PIPE clock, used by the controller to clock the PIPE + - description: PCIe dbi clock, ungated version + - description: PCIe master clock, ungated version + - description: PCIe slave clock, ungated version + + clock-names: + items: + - const: pipe + - const: dbi + - const: mstr + - const: slv + + phys: + maxItems: 1 + + num-lanes: + const: 2 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - samsung,fsys-sysreg + - samsung,syscon-phandle + - samsung,syscon-bus-s-fsys + - samsung,syscon-bus-p-fsys + - phys + - num-lanes + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie_ep: pcie-ep@17200000 { + compatible = "axis,artpec8-pcie-ep"; + reg = <0x0 0x17200000 0x0 0x1000>, + <0x0 0x17201000 0x0 0x1000>, + <0x2 0x00000000 0x6 0x00000000>; + reg-names = "dbi", "dbi2", "addr_space"; + #interrupt-cells = <1>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr"; + clocks = <&clock_cmu_fsys 39>, + <&clock_cmu_fsys 38>, + <&clock_cmu_fsys 37>, + <&clock_cmu_fsys 36>; + clock-names = "pipe", "dbi", "mstr", "slv"; + samsung,fsys-sysreg = <&syscon_fsys>; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,syscon-bus-s-fsys = <&syscon_bus_s_fsys>; + samsung,syscon-bus-p-fsys = <&syscon_bus_p_fsys>; + phys = <&pcie_phy>; + phy-names = "pcie_phy"; + num-lanes = <2>; + bus-range = <0x00 0xff>; + num-ib-windows = <16>; + num-ob-windows = <16>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml new file mode 100644 index 0000000..dbbe1fd --- /dev/null +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Artpec-8 SoC PCIe Controller + +maintainers: + - Jesper Nilsson <jesper.nilsson@axis.com> + +description: |+ + This PCIe host controller is based on the Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in snps,dw-pcie.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: axis,artpec8-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: External Local Bus interface (ELBI) registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: dbi + - const: elbi + - const: config + + ranges: + maxItems: 2 + + num-lanes: + const: 2 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PIPE clock, used by the controller to clock the PIPE + - description: PCIe dbi clock, ungated version + - description: PCIe master clock, ungated version + - description: PCIe slave clock, ungated version + + clock-names: + items: + - const: pipe + - const: dbi + - const: mstr + - const: slv + + phys: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - device_type + - ranges + - num-lanes + - interrupts + - interrupt-names + - clocks + - clock-names + - samsung,fsys-sysreg + - samsung,syscon-phandle + - samsung,syscon-bus-s-fsys + - samsung,syscon-bus-p-fsys + - phys + - phy-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie: pcie@17200000 { + compatible = "axis,artpec8-pcie"; + reg = <0x0 0x17200000 0x0 0x1000>, + <0x0 0x16ca0000 0x0 0x2000>, + <0x7 0x0001e000 0x0 0x2000>; + reg-names = "dbi", "elbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = </* non-prefetchable memory */ + 0x83000000 0x0 0x0000000 0x2 0x00000000 0x5 0x00000000 + /* downstream I/O */ + 0x81000000 0x0 0x0000000 0x7 0x00000000 0x0 0x00010000>; + num-lanes = <2>; + bus-range = <0x00 0xff>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr"; + #interrupt-cells = <1>; + clocks = <&cmu_fsys 39>, + <&cmu_fsys 38>, + <&cmu_fsys 37>, + <&cmu_fsys 36>; + clock-names = "pipe", "dbi", "mstr", "slv"; + samsung,fsys-sysreg = <&syscon_fsys>; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,syscon-bus-s-fsys = <&syscon_bus_s_fsys>; + samsung,syscon-bus-p-fsys = <&syscon_bus_p_fsys>; + phys = <&pcie_phy>; + phy-names = "pcie_phy"; + }; + }; +... -- 2.9.5 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2022-06-14 1:27 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7> 2022-06-14 1:16 ` [PATCH v3 0/5] Add support for Axis, ARTPEC-8 PCIe driver Wangseok Lee 2022-06-14 1:16 ` Wangseok Lee [not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p3> 2022-06-14 1:30 ` [PATCH v3 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver Wangseok Lee 2022-06-14 1:30 ` Wangseok Lee 2022-06-20 8:35 ` Krzysztof Kozlowski 2022-06-20 8:35 ` Krzysztof Kozlowski [not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p8> 2022-06-14 1:27 ` Wangseok Lee [this message] 2022-06-14 1:27 ` [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee 2022-06-16 22:54 ` Krzysztof Kozlowski 2022-06-16 22:54 ` Krzysztof Kozlowski 2022-06-14 1:34 ` [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee 2022-06-14 1:34 ` Wangseok Lee 2022-07-05 6:21 ` Vinod Koul 2022-07-05 6:21 ` Vinod Koul [not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p6> 2022-06-14 1:36 ` [PATCH v3 5/5] MAINTAINERS: Add Axis ARTPEC-8 PCIe PHY maintainers Wangseok Lee 2022-06-14 1:36 ` Wangseok Lee 2022-06-20 7:55 ` [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee 2022-06-20 7:55 ` Wangseok Lee 2022-06-20 8:42 ` Krzysztof Kozlowski 2022-06-20 8:42 ` Krzysztof Kozlowski [not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p2> 2022-06-21 7:42 ` Wangseok Lee 2022-06-21 7:42 ` Wangseok Lee 2022-06-21 12:44 ` Krzysztof Kozlowski 2022-06-21 12:44 ` Krzysztof Kozlowski [not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p4> 2022-06-22 7:20 ` Wangseok Lee 2022-06-22 7:20 ` Wangseok Lee 2022-07-06 5:22 ` [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee 2022-07-06 5:22 ` Wangseok Lee 2022-07-06 6:28 ` Krzysztof Kozlowski 2022-07-06 6:28 ` Krzysztof Kozlowski 2022-06-29 7:18 ` Wangseok Lee 2022-06-29 7:18 ` Wangseok Lee 2022-07-05 10:56 ` Krzysztof Kozlowski 2022-07-05 10:56 ` Krzysztof Kozlowski 2022-07-06 8:10 ` [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee 2022-07-06 8:10 ` Wangseok Lee 2022-07-06 16:51 ` Vinod Koul 2022-07-06 16:51 ` Vinod Koul [not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p5> 2022-06-14 1:29 ` [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee 2022-06-14 1:29 ` Wangseok Lee 2022-06-16 22:58 ` Krzysztof Kozlowski 2022-06-16 22:58 ` Krzysztof Kozlowski 2022-06-20 8:38 ` Wangseok Lee 2022-06-20 8:38 ` Wangseok Lee 2022-06-21 21:13 ` Bjorn Helgaas 2022-06-21 21:13 ` Bjorn Helgaas [not found] ` <CGME20220621212357epcas2p41ecf1ace5d207b154cc77dac79bc7e53@epcms2p2> 2022-06-22 7:06 ` Wangseok Lee 2022-06-22 7:06 ` Wangseok Lee 2022-06-22 7:21 ` [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee 2022-06-22 7:21 ` Wangseok Lee 2022-06-23 8:27 ` Krzysztof Kozlowski 2022-06-23 8:27 ` Krzysztof Kozlowski 2022-07-14 9:59 ` [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee 2022-07-14 9:59 ` Wangseok Lee 2022-07-15 11:33 ` Vinod Koul 2022-07-15 11:33 ` Vinod Koul 2022-06-21 7:56 ` [PATCH v3 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver Wangseok Lee 2022-06-21 7:56 ` Wangseok Lee 2022-07-06 5:20 ` [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee 2022-07-06 5:20 ` Wangseok Lee
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