From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> To: wangseok.lee@samsung.com, "robh+dt@kernel.org" <robh+dt@kernel.org>, "krzk+dt@kernel.org" <krzk+dt@kernel.org>, "kishon@ti.com" <kishon@ti.com>, "vkoul@kernel.org" <vkoul@kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "jesper.nilsson@axis.com" <jesper.nilsson@axis.com>, "lars.persson@axis.com" <lars.persson@axis.com>, "bhelgaas@google.com" <bhelgaas@google.com>, "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>, "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>, "kw@linux.com" <kw@linux.com>, "linux-arm-kernel@axis.com" <linux-arm-kernel@axis.com>, "kernel@axis.com" <kernel@axis.com> Cc: Moon-Ki Jun <moonki.jun@samsung.com>, Sang Min Kim <hypmean.kim@samsung.com>, Dongjin Yang <dj76.yang@samsung.com>, Yeeun Kim <yeeun119.kim@samsung.com> Subject: Re: [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Date: Tue, 21 Jun 2022 14:44:14 +0200 [thread overview] Message-ID: <4a58c6c4-be0e-e56c-2498-a14ba46b508d@linaro.org> (raw) In-Reply-To: <20220621074244epcms2p23cb631babfb87e5abb416467fb66e521@epcms2p2> On 21/06/2022 09:42, Wangseok Lee wrote: >>> >>> samsung,syscon-bus-s-fsys: >>> description: >>> Phandle to bus-s path of fsys block, this register >>> are used for enabling bus-s. >>> $ref: /schemas/types.yaml#/definitions/phandle >>> >>> samsung,syscon-bus-p-fsys: >>> description: >>> Phandle to bus-p path of fsys block, this register >>> are used for enabling bus-p. >>> $ref: /schemas/types.yaml#/definitions/phandle >> >> This two look unspecific and hacky workaround for missing drivers. Looks >> like instead of implementing interconnect or clock driver, you decided >> to poke some other registers. Why this cannot be an interconnect driver? >> >> > > bus-s, bus-p is a register that exists in the sysreg of the fsys block. > It is the same block as "fsys-sysreg" but is separated separately in > hardware. Two points here: 1. If it is in FSYS, why it cannot be accessed with samsung,fsys-sysreg? 2. If it is only register, shuld be described like this. You must describe item: https://elixir.bootlin.com/linux/v5.18-rc1/source/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml#L42 > So, get resource is performed separately from "fsys-sysreg". > They set pcie slave, dbi related control settings, > naming "bus-x" seems to be interconnect. > I will add this description to property. > I don't think it need to use the interconnect driver, > so please let me know your opinion. Please document both in the bindings and in the driver usage of this register. Writing there "0" or "1" is not enough. If the documentation is good, I am fine with it. If the explanation is obfuscated/not sufficient, it will look like avoiding to implement a driver, which I don't want to accept. Best regards, Krzysztof
WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> To: wangseok.lee@samsung.com, "robh+dt@kernel.org" <robh+dt@kernel.org>, "krzk+dt@kernel.org" <krzk+dt@kernel.org>, "kishon@ti.com" <kishon@ti.com>, "vkoul@kernel.org" <vkoul@kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "jesper.nilsson@axis.com" <jesper.nilsson@axis.com>, "lars.persson@axis.com" <lars.persson@axis.com>, "bhelgaas@google.com" <bhelgaas@google.com>, "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>, "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>, "kw@linux.com" <kw@linux.com>, "linux-arm-kernel@axis.com" <linux-arm-kernel@axis.com>, "kernel@axis.com" <kernel@axis.com> Cc: Moon-Ki Jun <moonki.jun@samsung.com>, Sang Min Kim <hypmean.kim@samsung.com>, Dongjin Yang <dj76.yang@samsung.com>, Yeeun Kim <yeeun119.kim@samsung.com> Subject: Re: [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Date: Tue, 21 Jun 2022 14:44:14 +0200 [thread overview] Message-ID: <4a58c6c4-be0e-e56c-2498-a14ba46b508d@linaro.org> (raw) In-Reply-To: <20220621074244epcms2p23cb631babfb87e5abb416467fb66e521@epcms2p2> On 21/06/2022 09:42, Wangseok Lee wrote: >>> >>> samsung,syscon-bus-s-fsys: >>> description: >>> Phandle to bus-s path of fsys block, this register >>> are used for enabling bus-s. >>> $ref: /schemas/types.yaml#/definitions/phandle >>> >>> samsung,syscon-bus-p-fsys: >>> description: >>> Phandle to bus-p path of fsys block, this register >>> are used for enabling bus-p. >>> $ref: /schemas/types.yaml#/definitions/phandle >> >> This two look unspecific and hacky workaround for missing drivers. Looks >> like instead of implementing interconnect or clock driver, you decided >> to poke some other registers. Why this cannot be an interconnect driver? >> >> > > bus-s, bus-p is a register that exists in the sysreg of the fsys block. > It is the same block as "fsys-sysreg" but is separated separately in > hardware. Two points here: 1. If it is in FSYS, why it cannot be accessed with samsung,fsys-sysreg? 2. If it is only register, shuld be described like this. You must describe item: https://elixir.bootlin.com/linux/v5.18-rc1/source/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml#L42 > So, get resource is performed separately from "fsys-sysreg". > They set pcie slave, dbi related control settings, > naming "bus-x" seems to be interconnect. > I will add this description to property. > I don't think it need to use the interconnect driver, > so please let me know your opinion. Please document both in the bindings and in the driver usage of this register. Writing there "0" or "1" is not enough. If the documentation is good, I am fine with it. If the explanation is obfuscated/not sufficient, it will look like avoiding to implement a driver, which I don't want to accept. Best regards, Krzysztof -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2022-06-21 12:44 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7> 2022-06-14 1:16 ` [PATCH v3 0/5] Add support for Axis, ARTPEC-8 PCIe driver Wangseok Lee 2022-06-14 1:16 ` Wangseok Lee [not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p3> 2022-06-14 1:30 ` [PATCH v3 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver Wangseok Lee 2022-06-14 1:30 ` Wangseok Lee 2022-06-20 8:35 ` Krzysztof Kozlowski 2022-06-20 8:35 ` Krzysztof Kozlowski [not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p8> 2022-06-14 1:27 ` [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee 2022-06-14 1:27 ` Wangseok Lee 2022-06-16 22:54 ` Krzysztof Kozlowski 2022-06-16 22:54 ` Krzysztof Kozlowski 2022-06-14 1:34 ` [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee 2022-06-14 1:34 ` Wangseok Lee 2022-07-05 6:21 ` Vinod Koul 2022-07-05 6:21 ` Vinod Koul [not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p6> 2022-06-14 1:36 ` [PATCH v3 5/5] MAINTAINERS: Add Axis ARTPEC-8 PCIe PHY maintainers Wangseok Lee 2022-06-14 1:36 ` Wangseok Lee 2022-06-20 7:55 ` [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee 2022-06-20 7:55 ` Wangseok Lee 2022-06-20 8:42 ` Krzysztof Kozlowski 2022-06-20 8:42 ` Krzysztof Kozlowski [not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p2> 2022-06-21 7:42 ` Wangseok Lee 2022-06-21 7:42 ` Wangseok Lee 2022-06-21 12:44 ` Krzysztof Kozlowski [this message] 2022-06-21 12:44 ` Krzysztof Kozlowski [not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p4> 2022-06-22 7:20 ` Wangseok Lee 2022-06-22 7:20 ` Wangseok Lee 2022-07-06 5:22 ` [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee 2022-07-06 5:22 ` Wangseok Lee 2022-07-06 6:28 ` Krzysztof Kozlowski 2022-07-06 6:28 ` Krzysztof Kozlowski 2022-06-29 7:18 ` Wangseok Lee 2022-06-29 7:18 ` Wangseok Lee 2022-07-05 10:56 ` Krzysztof Kozlowski 2022-07-05 10:56 ` Krzysztof Kozlowski 2022-07-06 8:10 ` [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee 2022-07-06 8:10 ` Wangseok Lee 2022-07-06 16:51 ` Vinod Koul 2022-07-06 16:51 ` Vinod Koul [not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p5> 2022-06-14 1:29 ` [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee 2022-06-14 1:29 ` Wangseok Lee 2022-06-16 22:58 ` Krzysztof Kozlowski 2022-06-16 22:58 ` Krzysztof Kozlowski 2022-06-20 8:38 ` Wangseok Lee 2022-06-20 8:38 ` Wangseok Lee 2022-06-21 21:13 ` Bjorn Helgaas 2022-06-21 21:13 ` Bjorn Helgaas [not found] ` <CGME20220621212357epcas2p41ecf1ace5d207b154cc77dac79bc7e53@epcms2p2> 2022-06-22 7:06 ` Wangseok Lee 2022-06-22 7:06 ` Wangseok Lee 2022-06-22 7:21 ` [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee 2022-06-22 7:21 ` Wangseok Lee 2022-06-23 8:27 ` Krzysztof Kozlowski 2022-06-23 8:27 ` Krzysztof Kozlowski 2022-07-14 9:59 ` [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee 2022-07-14 9:59 ` Wangseok Lee 2022-07-15 11:33 ` Vinod Koul 2022-07-15 11:33 ` Vinod Koul 2022-06-21 7:56 ` [PATCH v3 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver Wangseok Lee 2022-06-21 7:56 ` Wangseok Lee 2022-07-06 5:20 ` [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee 2022-07-06 5:20 ` Wangseok Lee
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