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From: "Paweł Anikiel" <pan@semihalf.com>
To: marex@denx.de, simon.k.r.goldschmidt@gmail.com,
	tien.fong.chee@intel.com, michal.simek@xilinx.com
Cc: u-boot@lists.denx.de, sjg@chromium.org, festevam@denx.de,
	jagan@amarulasolutions.com, andre.przywara@arm.com,
	narmstrong@baylibre.com, pbrobinson@gmail.com,
	tharvey@gateworks.com, paul.liu@linaro.org,
	christianshewitt@gmail.com, adrian.fiergolski@fastree3d.com,
	marek.behun@nic.cz, wd@denx.de, elly.siew.chin.lim@intel.com,
	upstream@semihalf.com, amstan@chromium.org,
	"Paweł Anikiel" <pan@semihalf.com>
Subject: [PATCH v3 09/11] socfpga: arria10: Improve bitstream loading speed
Date: Fri, 17 Jun 2022 12:47:24 +0200	[thread overview]
Message-ID: <20220617104726.158688-10-pan@semihalf.com> (raw)
In-Reply-To: <20220617104726.158688-1-pan@semihalf.com>

Apply some optimizations to speed up bitstream loading
(both for full and split periph/core bitstreams):

 * Change the size of the first fs read, so that all the subsequent
   reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE).
   This value was chosen so that in subsequent reads the fat fs driver
   doesn't have to allocate a temporary buffer in get_contents
   (assuming 8KiB clusters).

 * Change the buffer size to a larger value when reading to ddr
   (but not too large, because large transfers cause a stack overflow
   in the dwmmc driver).

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 drivers/fpga/socfpga_arria10.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 798e3a3f90..07bfe3060e 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -30,6 +30,14 @@
 #define FPGA_TIMEOUT_MSEC	1000  /* timeout in ms */
 #define FPGA_TIMEOUT_CNT	0x1000000
 #define DEFAULT_DDR_LOAD_ADDRESS	0x400
+#define DDR_BUFFER_SIZE		0x100000
+
+/* When reading bitstream from a filesystem, the size of the first read is
+ * changed so that the subsequent reads are aligned to this value. This value
+ * was chosen so that in subsequent reads the fat fs driver doesn't have to
+ * allocate a temporary buffer in get_contents (assuming 8KiB clusters).
+ */
+#define MAX_FIRST_LOAD_SIZE	0x2000
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -526,7 +534,8 @@ static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
 #ifdef CONFIG_FS_LOADER
 static int first_loading_rbf_to_buffer(struct udevice *dev,
 				struct fpga_loadfs_info *fpga_loadfs,
-				u32 *buffer, size_t *buffer_bsize)
+				u32 *buffer, size_t *buffer_bsize,
+				size_t *buffer_bsize_ori)
 {
 	u32 *buffer_p = (u32 *)*buffer;
 	u32 *loadable = buffer_p;
@@ -674,6 +683,7 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,
 		}
 
 		buffer_size = rbf_size;
+		*buffer_bsize_ori = DDR_BUFFER_SIZE;
 	}
 
 	debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
@@ -686,11 +696,16 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,
 	 * chunk by chunk transfer is required due to smaller buffer size
 	 * compare to bitstream
 	 */
+
+	if (buffer_size > MAX_FIRST_LOAD_SIZE)
+		buffer_size = MAX_FIRST_LOAD_SIZE;
+
 	if (rbf_size <= buffer_size) {
 		/* Loading whole bitstream into buffer */
 		buffer_size = rbf_size;
 		fpga_loadfs->remaining = 0;
 	} else {
+		buffer_size -= rbf_offset % buffer_size;
 		fpga_loadfs->remaining -= buffer_size;
 	}
 
@@ -806,7 +821,8 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
 	 * function below.
 	 */
 	ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
-					   &buffer_sizebytes);
+					   &buffer_sizebytes,
+					   &buffer_sizebytes_ori);
 	if (ret == 1) {
 		printf("FPGA: Skipping configuration ...\n");
 		return 0;
-- 
2.36.1.476.g0c4daa206d-goog


  parent reply	other threads:[~2022-06-17 10:49 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-17 10:47 [PATCH v3 00/11] Add Chameleon v3 support Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 01/11] arm: dts: Add Mercury+ AA1 devicetrees Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 02/11] arm: dts: Add Chameleonv3 handoff headers Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 03/11] arm: dts: Add Chameleonv3 devicetrees Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 04/11] board: Add Chameleonv3 board dir Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 05/11] config: Add Chameleonv3 config Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 06/11] misc: atsha204a: Increase wake delay by tWHI Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 07/11] sysreset: socfpga: Use parent device for reading base address Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg Paweł Anikiel
2022-06-20  8:40   ` Chee, Tien Fong
2022-06-20 12:13     ` Paweł Anikiel
2022-06-20 12:29       ` Chee, Tien Fong
2022-06-20 15:59         ` Paweł Anikiel
2022-06-23 11:53           ` Chee, Tien Fong
2022-06-17 10:47 ` Paweł Anikiel [this message]
2022-06-17 10:47 ` [PATCH v3 10/11] socfpga: arria10: Wait for fifo empty after writing bitstream Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 11/11] socfpga: arria10: Allow dcache_enable before relocation Paweł Anikiel

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