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From: "Paweł Anikiel" <pan@semihalf.com>
To: "Chee, Tien Fong" <tien.fong.chee@intel.com>
Cc: "Vasut, Marek" <marex@denx.de>,
	 "simon.k.r.goldschmidt@gmail.com"
	<simon.k.r.goldschmidt@gmail.com>,
	 "michal.simek@xilinx.com" <michal.simek@xilinx.com>,
	"u-boot@lists.denx.de" <u-boot@lists.denx.de>,
	 "sjg@chromium.org" <sjg@chromium.org>,
	"festevam@denx.de" <festevam@denx.de>,
	 "jagan@amarulasolutions.com" <jagan@amarulasolutions.com>,
	 "andre.przywara@arm.com" <andre.przywara@arm.com>,
	"Armstrong, Neil" <narmstrong@baylibre.com>,
	 "pbrobinson@gmail.com" <pbrobinson@gmail.com>,
	"tharvey@gateworks.com" <tharvey@gateworks.com>,
	 "paul.liu@linaro.org" <paul.liu@linaro.org>,
	 "christianshewitt@gmail.com" <christianshewitt@gmail.com>,
	 "adrian.fiergolski@fastree3d.com"
	<adrian.fiergolski@fastree3d.com>,
	"marek.behun@nic.cz" <marek.behun@nic.cz>,
	 "Denk, Wolfgang" <wd@denx.de>,
	"Lim, Elly Siew Chin" <elly.siew.chin.lim@intel.com>,
	 "upstream@semihalf.com" <upstream@semihalf.com>,
	"amstan@chromium.org" <amstan@chromium.org>
Subject: Re: [PATCH v3 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg
Date: Mon, 20 Jun 2022 14:13:53 +0200	[thread overview]
Message-ID: <CAF9_jYTRb6xGKVsKS3h5SbGQXRAMZWYUv-0Od0tXVbXwZ54C8A@mail.gmail.com> (raw)
In-Reply-To: <DM8PR11MB55920CA742467294C8450620D2B09@DM8PR11MB5592.namprd11.prod.outlook.com>

On Mon, Jun 20, 2022 at 10:40 AM Chee, Tien Fong
<tien.fong.chee@intel.com> wrote:
>
> Hi,
>
> > -----Original Message-----
> > From: Paweł Anikiel <pan@semihalf.com>
> > Sent: Friday, 17 June, 2022 6:47 PM
> > To: Vasut, Marek <marex@denx.de>; simon.k.r.goldschmidt@gmail.com;
> > Chee, Tien Fong <tien.fong.chee@intel.com>; michal.simek@xilinx.com
> > Cc: u-boot@lists.denx.de; sjg@chromium.org; festevam@denx.de;
> > jagan@amarulasolutions.com; andre.przywara@arm.com; Armstrong, Neil
> > <narmstrong@baylibre.com>; pbrobinson@gmail.com;
> > tharvey@gateworks.com; paul.liu@linaro.org; christianshewitt@gmail.com;
> > adrian.fiergolski@fastree3d.com; marek.behun@nic.cz; Denk, Wolfgang
> > <wd@denx.de>; Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>;
> > upstream@semihalf.com; amstan@chromium.org; Paweł Anikiel
> > <pan@semihalf.com>
> > Subject: [PATCH v3 08/11] socfpga: arria10: Replace delays with busy waiting
> > in cm_full_cfg
> >
> > Using udelay while the clocks aren't fully configured causes the timer system
> > to save the wrong clock rate. Use sdelay and wait_on_value instead (the
> > values used in these functions were found experimentally).
> >
> > Signed-off-by: Paweł Anikiel <pan@semihalf.com>
> > ---
> >  arch/arm/mach-socfpga/clock_manager_arria10.c | 31 +++++++++++++-----
> > -
> >  1 file changed, 22 insertions(+), 9 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > index 58d5d3fd8a..b48a2b47bc 100644
> > --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
>
> Did you try to call timer_init() after cm_basic_init() in board_init_f? If that's working, then no change is required to fix this clock issue.

Seems like timer_init() isn't implemented on Arria 10 (it defaults to
the return 0 stub). I also tried dm_timer_init(), no luck.

I did some code digging, the clock rate is read by clk_get_rate(), and
the timer rate is set by dw_apb_timer_probe()
(drivers/timer/dw-apb-timer.c:77), and there doesn't seem to be a good
way of updating that value later.

The only other function I could find that sets the timer rate is
timer_pre_probe() from drivers/timer/timer-uclass.c, which very much
looks like what we need, but it's static and the name suggests it
shouldn't be called manually anyway.

Regards,
Paweł

  reply	other threads:[~2022-06-20 12:14 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-17 10:47 [PATCH v3 00/11] Add Chameleon v3 support Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 01/11] arm: dts: Add Mercury+ AA1 devicetrees Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 02/11] arm: dts: Add Chameleonv3 handoff headers Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 03/11] arm: dts: Add Chameleonv3 devicetrees Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 04/11] board: Add Chameleonv3 board dir Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 05/11] config: Add Chameleonv3 config Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 06/11] misc: atsha204a: Increase wake delay by tWHI Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 07/11] sysreset: socfpga: Use parent device for reading base address Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg Paweł Anikiel
2022-06-20  8:40   ` Chee, Tien Fong
2022-06-20 12:13     ` Paweł Anikiel [this message]
2022-06-20 12:29       ` Chee, Tien Fong
2022-06-20 15:59         ` Paweł Anikiel
2022-06-23 11:53           ` Chee, Tien Fong
2022-06-17 10:47 ` [PATCH v3 09/11] socfpga: arria10: Improve bitstream loading speed Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 10/11] socfpga: arria10: Wait for fifo empty after writing bitstream Paweł Anikiel
2022-06-17 10:47 ` [PATCH v3 11/11] socfpga: arria10: Allow dcache_enable before relocation Paweł Anikiel

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