From: Jason Gunthorpe <jgg@nvidia.com>
To: Christoph Hellwig <hch@infradead.org>
Cc: Nicolin Chen <nicolinc@nvidia.com>,
kwankhede@nvidia.com, corbet@lwn.net, hca@linux.ibm.com,
gor@linux.ibm.com, agordeev@linux.ibm.com,
borntraeger@linux.ibm.com, svens@linux.ibm.com,
zhenyuw@linux.intel.com, zhi.a.wang@intel.com,
jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com,
rodrigo.vivi@intel.com, tvrtko.ursulin@linux.intel.com,
airlied@linux.ie, daniel@ffwll.ch, farman@linux.ibm.com,
mjrosato@linux.ibm.com, pasic@linux.ibm.com,
vneethv@linux.ibm.com, oberpar@linux.ibm.com,
freude@linux.ibm.com, akrowiak@linux.ibm.com,
jjherne@linux.ibm.com, alex.williamson@redhat.com,
cohuck@redhat.com, kevin.tian@intel.com, jchrist@linux.ibm.com,
kvm@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org,
intel-gvt-dev@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [RFT][PATCH v1 6/6] vfio: Replace phys_pfn with phys_page for vfio_pin_pages()
Date: Mon, 20 Jun 2022 00:00:46 -0300 [thread overview]
Message-ID: <20220620030046.GB5219@nvidia.com> (raw)
In-Reply-To: <YqxBLbu8yPJiwK6Z@infradead.org>
On Fri, Jun 17, 2022 at 01:54:05AM -0700, Christoph Hellwig wrote:
> There is a bunch of code an comments in the iommu type1 code that
> suggest we can pin memory that is not page backed.
AFAIK you can.. The whole follow_pte() mechanism allows raw PFNs to be
loaded into the type1 maps and the pin API will happily return
them. This happens in almost every qemu scenario because PCI MMIO BAR
memory ends up routed down this path.
Thanks,
Jason
WARNING: multiple messages have this Message-ID (diff)
From: Jason Gunthorpe <jgg@nvidia.com>
To: Christoph Hellwig <hch@infradead.org>
Cc: mjrosato@linux.ibm.com, linux-doc@vger.kernel.org,
airlied@linux.ie, kevin.tian@intel.com,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
kwankhede@nvidia.com, vneethv@linux.ibm.com,
agordeev@linux.ibm.com, linux-s390@vger.kernel.org,
kvm@vger.kernel.org, corbet@lwn.net, pasic@linux.ibm.com,
Nicolin Chen <nicolinc@nvidia.com>,
borntraeger@linux.ibm.com, intel-gfx@lists.freedesktop.org,
zhi.a.wang@intel.com, jjherne@linux.ibm.com,
farman@linux.ibm.com, jchrist@linux.ibm.com, gor@linux.ibm.com,
hca@linux.ibm.com, alex.williamson@redhat.com,
freude@linux.ibm.com, rodrigo.vivi@intel.com,
intel-gvt-dev@lists.freedesktop.org, akrowiak@linux.ibm.com,
tvrtko.ursulin@linux.intel.com, cohuck@redhat.com,
oberpar@linux.ibm.com, svens@linux.ibm.com
Subject: Re: [RFT][PATCH v1 6/6] vfio: Replace phys_pfn with phys_page for vfio_pin_pages()
Date: Mon, 20 Jun 2022 00:00:46 -0300 [thread overview]
Message-ID: <20220620030046.GB5219@nvidia.com> (raw)
In-Reply-To: <YqxBLbu8yPJiwK6Z@infradead.org>
On Fri, Jun 17, 2022 at 01:54:05AM -0700, Christoph Hellwig wrote:
> There is a bunch of code an comments in the iommu type1 code that
> suggest we can pin memory that is not page backed.
AFAIK you can.. The whole follow_pte() mechanism allows raw PFNs to be
loaded into the type1 maps and the pin API will happily return
them. This happens in almost every qemu scenario because PCI MMIO BAR
memory ends up routed down this path.
Thanks,
Jason
WARNING: multiple messages have this Message-ID (diff)
From: Jason Gunthorpe <jgg@nvidia.com>
To: Christoph Hellwig <hch@infradead.org>
Cc: mjrosato@linux.ibm.com, linux-doc@vger.kernel.org,
airlied@linux.ie, dri-devel@lists.freedesktop.org,
linux-kernel@vger.kernel.org, kwankhede@nvidia.com,
vneethv@linux.ibm.com, agordeev@linux.ibm.com,
linux-s390@vger.kernel.org, kvm@vger.kernel.org, corbet@lwn.net,
pasic@linux.ibm.com, Nicolin Chen <nicolinc@nvidia.com>,
borntraeger@linux.ibm.com, intel-gfx@lists.freedesktop.org,
jjherne@linux.ibm.com, farman@linux.ibm.com,
jchrist@linux.ibm.com, gor@linux.ibm.com, hca@linux.ibm.com,
freude@linux.ibm.com, rodrigo.vivi@intel.com,
intel-gvt-dev@lists.freedesktop.org, akrowiak@linux.ibm.com,
cohuck@redhat.com, oberpar@linux.ibm.com, svens@linux.ibm.com
Subject: Re: [Intel-gfx] [RFT][PATCH v1 6/6] vfio: Replace phys_pfn with phys_page for vfio_pin_pages()
Date: Mon, 20 Jun 2022 00:00:46 -0300 [thread overview]
Message-ID: <20220620030046.GB5219@nvidia.com> (raw)
In-Reply-To: <YqxBLbu8yPJiwK6Z@infradead.org>
On Fri, Jun 17, 2022 at 01:54:05AM -0700, Christoph Hellwig wrote:
> There is a bunch of code an comments in the iommu type1 code that
> suggest we can pin memory that is not page backed.
AFAIK you can.. The whole follow_pte() mechanism allows raw PFNs to be
loaded into the type1 maps and the pin API will happily return
them. This happens in almost every qemu scenario because PCI MMIO BAR
memory ends up routed down this path.
Thanks,
Jason
next prev parent reply other threads:[~2022-06-20 3:00 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-16 23:52 [RFT][PATCH v1 0/6] Update vfio_pin/unpin_pages API Nicolin Chen
2022-06-16 23:52 ` Nicolin Chen
2022-06-16 23:52 ` [RFT][PATCH v1 1/6] vfio/ap: Pass in physical address of ind to ap_aqic() Nicolin Chen
2022-06-16 23:52 ` Nicolin Chen
2022-06-20 10:00 ` Harald Freudenberger
2022-06-20 10:00 ` Harald Freudenberger
2022-06-21 21:01 ` Nicolin Chen
2022-06-21 21:01 ` [Intel-gfx] " Nicolin Chen
2022-06-21 21:01 ` Nicolin Chen
2022-06-16 23:52 ` [RFT][PATCH v1 2/6] vfio/ccw: Only pass in contiguous pages Nicolin Chen
2022-06-16 23:52 ` Nicolin Chen
2022-06-16 23:52 ` [RFT][PATCH v1 3/6] vfio: Pass in starting IOVA to vfio_pin/unpin_pages API Nicolin Chen
2022-06-16 23:52 ` Nicolin Chen
2022-06-17 8:42 ` Christoph Hellwig
2022-06-17 8:42 ` [Intel-gfx] " Christoph Hellwig
2022-06-17 21:57 ` Nicolin Chen
2022-06-17 21:57 ` Nicolin Chen
2022-06-22 1:18 ` Nicolin Chen
2022-06-22 1:18 ` [Intel-gfx] " Nicolin Chen
2022-06-22 1:18 ` Nicolin Chen
2022-06-16 23:52 ` [RFT][PATCH v1 4/6] vfio: Rename user_iova of vfio_dma_rw() Nicolin Chen
2022-06-16 23:52 ` Nicolin Chen
2022-06-16 23:52 ` [RFT][PATCH v1 5/6] vfio/ccw: Add kmap_local_page() for memcpy Nicolin Chen
2022-06-16 23:52 ` Nicolin Chen
2022-06-17 8:44 ` Christoph Hellwig
2022-06-17 8:44 ` [Intel-gfx] " Christoph Hellwig
2022-06-17 21:58 ` Nicolin Chen
2022-06-17 21:58 ` Nicolin Chen
2022-06-20 2:57 ` Jason Gunthorpe
2022-06-20 2:57 ` [Intel-gfx] " Jason Gunthorpe
2022-06-20 2:57 ` Jason Gunthorpe
2022-06-20 6:32 ` Christoph Hellwig
2022-06-20 6:32 ` [Intel-gfx] " Christoph Hellwig
2022-06-20 15:39 ` Jason Gunthorpe
2022-06-20 15:39 ` [Intel-gfx] " Jason Gunthorpe
2022-06-20 15:39 ` Jason Gunthorpe
2022-06-21 21:21 ` Nicolin Chen
2022-06-21 21:21 ` [Intel-gfx] " Nicolin Chen
2022-06-21 21:21 ` Nicolin Chen
2022-06-24 13:56 ` Jason Gunthorpe
2022-06-24 13:56 ` [Intel-gfx] " Jason Gunthorpe
2022-06-24 13:56 ` Jason Gunthorpe
2022-06-24 19:22 ` Nicolin Chen
2022-06-24 19:22 ` Nicolin Chen
2022-06-24 19:30 ` Jason Gunthorpe
2022-06-24 19:30 ` [Intel-gfx] " Jason Gunthorpe
2022-06-24 19:30 ` Jason Gunthorpe
2022-06-24 20:12 ` Nicolin Chen
2022-06-24 20:12 ` Nicolin Chen
2022-06-24 22:42 ` Jason Gunthorpe
2022-06-24 22:42 ` [Intel-gfx] " Jason Gunthorpe
2022-06-24 22:42 ` Jason Gunthorpe
2022-06-16 23:52 ` [RFT][PATCH v1 6/6] vfio: Replace phys_pfn with phys_page for vfio_pin_pages() Nicolin Chen
2022-06-16 23:52 ` Nicolin Chen
2022-06-17 8:54 ` Christoph Hellwig
2022-06-17 8:54 ` [Intel-gfx] " Christoph Hellwig
2022-06-17 22:06 ` Nicolin Chen
2022-06-17 22:06 ` Nicolin Chen
2022-06-19 6:18 ` Christoph Hellwig
2022-06-19 6:18 ` [Intel-gfx] " Christoph Hellwig
2022-06-19 6:41 ` Nicolin Chen
2022-06-19 6:41 ` Nicolin Chen
2022-06-20 3:00 ` Jason Gunthorpe [this message]
2022-06-20 3:00 ` [Intel-gfx] " Jason Gunthorpe
2022-06-20 3:00 ` Jason Gunthorpe
2022-06-20 5:51 ` Christoph Hellwig
2022-06-20 5:51 ` [Intel-gfx] " Christoph Hellwig
2022-06-20 6:37 ` Christoph Hellwig
2022-06-20 6:37 ` [Intel-gfx] " Christoph Hellwig
2022-06-20 15:36 ` Jason Gunthorpe
2022-06-20 15:36 ` [Intel-gfx] " Jason Gunthorpe
2022-06-20 15:36 ` Jason Gunthorpe
2022-06-21 21:47 ` Nicolin Chen
2022-06-21 21:47 ` [Intel-gfx] " Nicolin Chen
2022-06-21 21:47 ` Nicolin Chen
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