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From: Charles Keepax <ckeepax@opensource.cirrus.com>
To: <broonie@kernel.org>
Cc: <james.schulman@cirrus.com>, <david.rhodes@cirrus.com>,
	<lgirdwood@gmail.com>, <alsa-devel@alsa-project.org>,
	<patches@opensource.cirrus.com>, <linux-kernel@vger.kernel.org>
Subject: [PATCH 4/4] ASoC: core: Add new SOC_DOUBLE_SX_TLV macro
Date: Tue, 21 Jun 2022 11:20:41 +0100	[thread overview]
Message-ID: <20220621102041.1713504-4-ckeepax@opensource.cirrus.com> (raw)
In-Reply-To: <20220621102041.1713504-1-ckeepax@opensource.cirrus.com>

Currently macros only exist for SX style (implicit sign bit 2's
compliment) volume controls where the volumes for left and right
are in separate registers. Some future Cirrus devices will have
both volumes in the same register, as such add a new macro to
support this.

Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
---
 include/sound/soc.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/include/sound/soc.h b/include/sound/soc.h
index 8909cc7d311ef..76ee3c2b8b56c 100644
--- a/include/sound/soc.h
+++ b/include/sound/soc.h
@@ -136,6 +136,18 @@
 	.put = snd_soc_put_volsw, \
 	.private_value = SOC_DOUBLE_VALUE(reg, shift_left, shift_right, \
 					  max, invert, 0) }
+#define SOC_DOUBLE_SX_TLV(xname, xreg, shift_left, shift_right, xmin, xmax, tlv_array) \
+{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
+	.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
+	SNDRV_CTL_ELEM_ACCESS_READWRITE, \
+	.tlv.p  = (tlv_array), \
+	.info = snd_soc_info_volsw_sx, \
+	.get = snd_soc_get_volsw_sx, \
+	.put = snd_soc_put_volsw_sx, \
+	.private_value = (unsigned long)&(struct soc_mixer_control) \
+		{.reg = xreg, .rreg = xreg, \
+		.shift = shift_left, .rshift = shift_right, \
+		.max = xmax, .min = xmin} }
 #define SOC_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, xinvert, tlv_array) \
 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
 	.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
-- 
2.30.2


WARNING: multiple messages have this Message-ID (diff)
From: Charles Keepax <ckeepax@opensource.cirrus.com>
To: <broonie@kernel.org>
Cc: alsa-devel@alsa-project.org, patches@opensource.cirrus.com,
	lgirdwood@gmail.com, david.rhodes@cirrus.com,
	james.schulman@cirrus.com, linux-kernel@vger.kernel.org
Subject: [PATCH 4/4] ASoC: core: Add new SOC_DOUBLE_SX_TLV macro
Date: Tue, 21 Jun 2022 11:20:41 +0100	[thread overview]
Message-ID: <20220621102041.1713504-4-ckeepax@opensource.cirrus.com> (raw)
In-Reply-To: <20220621102041.1713504-1-ckeepax@opensource.cirrus.com>

Currently macros only exist for SX style (implicit sign bit 2's
compliment) volume controls where the volumes for left and right
are in separate registers. Some future Cirrus devices will have
both volumes in the same register, as such add a new macro to
support this.

Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
---
 include/sound/soc.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/include/sound/soc.h b/include/sound/soc.h
index 8909cc7d311ef..76ee3c2b8b56c 100644
--- a/include/sound/soc.h
+++ b/include/sound/soc.h
@@ -136,6 +136,18 @@
 	.put = snd_soc_put_volsw, \
 	.private_value = SOC_DOUBLE_VALUE(reg, shift_left, shift_right, \
 					  max, invert, 0) }
+#define SOC_DOUBLE_SX_TLV(xname, xreg, shift_left, shift_right, xmin, xmax, tlv_array) \
+{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
+	.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
+	SNDRV_CTL_ELEM_ACCESS_READWRITE, \
+	.tlv.p  = (tlv_array), \
+	.info = snd_soc_info_volsw_sx, \
+	.get = snd_soc_get_volsw_sx, \
+	.put = snd_soc_put_volsw_sx, \
+	.private_value = (unsigned long)&(struct soc_mixer_control) \
+		{.reg = xreg, .rreg = xreg, \
+		.shift = shift_left, .rshift = shift_right, \
+		.max = xmax, .min = xmin} }
 #define SOC_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, xinvert, tlv_array) \
 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
 	.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
-- 
2.30.2


  parent reply	other threads:[~2022-06-21 10:21 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-21 10:20 [PATCH 1/4] ASoC: wm_adsp: Fix event for preloader Charles Keepax
2022-06-21 10:20 ` Charles Keepax
2022-06-21 10:20 ` [PATCH 2/4] ASoC: wm5110: Fix DRE control Charles Keepax
2022-06-21 10:20   ` Charles Keepax
2022-06-21 10:20 ` [PATCH 3/4] ASoC: cs35l41: Correct some control names Charles Keepax
2022-06-21 10:20   ` Charles Keepax
2022-06-21 17:11   ` David Rhodes
2022-06-21 17:11     ` David Rhodes
2022-06-21 10:20 ` Charles Keepax [this message]
2022-06-21 10:20   ` [PATCH 4/4] ASoC: core: Add new SOC_DOUBLE_SX_TLV macro Charles Keepax
2022-06-21 16:59 ` [PATCH 1/4] ASoC: wm_adsp: Fix event for preloader Mark Brown
2022-06-21 16:59   ` Mark Brown

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