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From: Francesco Dolcini <francesco.dolcini@toradex.com>
To: Shawn Guo <shawnguo@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>,
	Andrejs Cainikovs <andrejs.cainikovs@toradex.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	Marcel Ziswiler <marcel.ziswiler@toradex.com>,
	Francesco Dolcini <francesco.dolcini@toradex.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1] arm64: dts: imx8mm-verdin: update CAN clock to 40MHz
Date: Tue, 21 Jun 2022 20:07:49 +0200	[thread overview]
Message-ID: <20220621180749.GA22098@francesco-nb.int.toradex.com> (raw)
In-Reply-To: <20220512104019.19725-1-andrejs.cainikovs@toradex.com>

Hello Shawn, just a ping on this.

Francesco

On Thu, May 12, 2022 at 12:40:19PM +0200, Andrejs Cainikovs wrote:
> Update SPI CAN controller clock to match current hardware design.
> 
> Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> index 0d84d29e70f1..d309bc0ab8f6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> @@ -32,10 +32,10 @@ backlight: backlight {
>  	};
>  
>  	/* Fixed clock dedicated to SPI CAN controller */
> -	clk20m: oscillator {
> +	clk40m: oscillator {
>  		compatible = "fixed-clock";
>  		#clock-cells = <0>;
> -		clock-frequency = <20000000>;
> +		clock-frequency = <40000000>;
>  	};
>  
>  	gpio-keys {
> @@ -194,7 +194,7 @@ &ecspi3 {
>  
>  	can1: can@0 {
>  		compatible = "microchip,mcp251xfd";
> -		clocks = <&clk20m>;
> +		clocks = <&clk40m>;
>  		interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>;
>  		pinctrl-names = "default";
>  		pinctrl-0 = <&pinctrl_can1_int>;
> -- 
> 2.34.1
> 


WARNING: multiple messages have this Message-ID (diff)
From: Francesco Dolcini <francesco.dolcini@toradex.com>
To: Shawn Guo <shawnguo@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>,
	Andrejs Cainikovs <andrejs.cainikovs@toradex.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	Marcel Ziswiler <marcel.ziswiler@toradex.com>,
	Francesco Dolcini <francesco.dolcini@toradex.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1] arm64: dts: imx8mm-verdin: update CAN clock to 40MHz
Date: Tue, 21 Jun 2022 20:07:49 +0200	[thread overview]
Message-ID: <20220621180749.GA22098@francesco-nb.int.toradex.com> (raw)
In-Reply-To: <20220512104019.19725-1-andrejs.cainikovs@toradex.com>

Hello Shawn, just a ping on this.

Francesco

On Thu, May 12, 2022 at 12:40:19PM +0200, Andrejs Cainikovs wrote:
> Update SPI CAN controller clock to match current hardware design.
> 
> Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> index 0d84d29e70f1..d309bc0ab8f6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> @@ -32,10 +32,10 @@ backlight: backlight {
>  	};
>  
>  	/* Fixed clock dedicated to SPI CAN controller */
> -	clk20m: oscillator {
> +	clk40m: oscillator {
>  		compatible = "fixed-clock";
>  		#clock-cells = <0>;
> -		clock-frequency = <20000000>;
> +		clock-frequency = <40000000>;
>  	};
>  
>  	gpio-keys {
> @@ -194,7 +194,7 @@ &ecspi3 {
>  
>  	can1: can@0 {
>  		compatible = "microchip,mcp251xfd";
> -		clocks = <&clk20m>;
> +		clocks = <&clk40m>;
>  		interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>;
>  		pinctrl-names = "default";
>  		pinctrl-0 = <&pinctrl_can1_int>;
> -- 
> 2.34.1
> 


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  parent reply	other threads:[~2022-06-21 18:08 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-12 10:40 [PATCH v1] arm64: dts: imx8mm-verdin: update CAN clock to 40MHz Andrejs Cainikovs
2022-05-12 10:40 ` Andrejs Cainikovs
2022-05-12 13:41 ` Marcel Ziswiler
2022-05-12 13:41   ` Marcel Ziswiler
2022-06-21 18:07 ` Francesco Dolcini [this message]
2022-06-21 18:07   ` Francesco Dolcini
2022-06-21 19:50   ` Marc Kleine-Budde
2022-06-21 19:50     ` Marc Kleine-Budde
2022-06-22  6:38     ` Andrejs Cainikovs
2022-06-22  6:38       ` Andrejs Cainikovs
2022-06-22  6:51       ` Marc Kleine-Budde
2022-06-22  6:51         ` Marc Kleine-Budde

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