From: Conor Dooley <conor.dooley@microchip.com> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, "David S . Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>, Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Palmer Dabbelt <palmer@dabbelt.com>, Conor Dooley <conor.dooley@microchip.com>, "Nicolas Ferre" <nicolas.ferre@microchip.com>, Claudiu Beznea <claudiu.beznea@microchip.com>, Philipp Zabel <p.zabel@pengutronix.de>, "Daire McNamara" <daire.mcnamara@microchip.com> Cc: Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <netdev@vger.kernel.org>, <linux-riscv@lists.infradead.org> Subject: [PATCH v1 00/14] PolarFire SoC reset controller & clock cleanups Date: Thu, 30 Jun 2022 09:05:19 +0100 [thread overview] Message-ID: <20220630080532.323731-1-conor.dooley@microchip.com> (raw) Hey all, I know I have not sat on the RFC I sent about the aux. bus parts for too long, but figured I'd just send the whole thing anyway to all lists etc. Kinda two things happening in this series, but I sent it together to ensure the second part would apply correctly. The first is the reset controller that I promised after discovering the issue triggered by CONFIG_PM & the phy not coming up correctly. I have now removed all the messing with resets from clock enable/disable functions & now use the aux bus to set up a reset controller driver. Since I needed something to test it, I hooked up the reset for the Cadence MACB on PolarFire SoC. The second part adds rate control for the MSS PLL clock, followed by some simplifications to the driver & conversions of some custom structs to the corresponding structs in the framework. Thanks, Conor. FYI, there'll be maintainers conflicts with an obvious resolution in -next, but I cannot rebase on then b/c unrelated changes have broken boot there at the moment. Conor Dooley (14): dt-bindings: clk: microchip: mpfs: add reset controller support dt-bindings: net: cdns,macb: document polarfire soc's macb clk: microchip: mpfs: add reset controller reset: add polarfire soc reset support MAINTAINERS: add polarfire soc reset controller net: macb: add polarfire soc reset support riscv: dts: microchip: add mpfs specific macb reset support clk: microchip: mpfs: add module_authors entries clk: microchip: mpfs: add MSS pll's set & round rate clk: microchip: mpfs: move id & offset out of clock structs clk: microchip: mpfs: simplify control reg access clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() clk: microchip: mpfs: convert cfg_clk to clk_divider clk: microchip: mpfs: convert periph_clk to clk_gate .../bindings/clock/microchip,mpfs.yaml | 17 +- .../devicetree/bindings/net/cdns,macb.yaml | 1 + MAINTAINERS | 1 + arch/riscv/boot/dts/microchip/mpfs.dtsi | 7 +- drivers/clk/microchip/Kconfig | 1 + drivers/clk/microchip/clk-mpfs.c | 377 +++++++++--------- drivers/net/ethernet/cadence/macb_main.c | 25 +- drivers/reset/Kconfig | 9 + drivers/reset/Makefile | 2 +- drivers/reset/reset-mpfs.c | 145 +++++++ include/soc/microchip/mpfs.h | 8 + 11 files changed, 393 insertions(+), 200 deletions(-) create mode 100644 drivers/reset/reset-mpfs.c base-commit: b13baccc3850ca8b8cccbf8ed9912dbaa0fdf7f3 -- 2.36.1
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, "David S . Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>, Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Palmer Dabbelt <palmer@dabbelt.com>, Conor Dooley <conor.dooley@microchip.com>, "Nicolas Ferre" <nicolas.ferre@microchip.com>, Claudiu Beznea <claudiu.beznea@microchip.com>, Philipp Zabel <p.zabel@pengutronix.de>, "Daire McNamara" <daire.mcnamara@microchip.com> Cc: Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <netdev@vger.kernel.org>, <linux-riscv@lists.infradead.org> Subject: [PATCH v1 00/14] PolarFire SoC reset controller & clock cleanups Date: Thu, 30 Jun 2022 09:05:19 +0100 [thread overview] Message-ID: <20220630080532.323731-1-conor.dooley@microchip.com> (raw) Hey all, I know I have not sat on the RFC I sent about the aux. bus parts for too long, but figured I'd just send the whole thing anyway to all lists etc. Kinda two things happening in this series, but I sent it together to ensure the second part would apply correctly. The first is the reset controller that I promised after discovering the issue triggered by CONFIG_PM & the phy not coming up correctly. I have now removed all the messing with resets from clock enable/disable functions & now use the aux bus to set up a reset controller driver. Since I needed something to test it, I hooked up the reset for the Cadence MACB on PolarFire SoC. The second part adds rate control for the MSS PLL clock, followed by some simplifications to the driver & conversions of some custom structs to the corresponding structs in the framework. Thanks, Conor. FYI, there'll be maintainers conflicts with an obvious resolution in -next, but I cannot rebase on then b/c unrelated changes have broken boot there at the moment. Conor Dooley (14): dt-bindings: clk: microchip: mpfs: add reset controller support dt-bindings: net: cdns,macb: document polarfire soc's macb clk: microchip: mpfs: add reset controller reset: add polarfire soc reset support MAINTAINERS: add polarfire soc reset controller net: macb: add polarfire soc reset support riscv: dts: microchip: add mpfs specific macb reset support clk: microchip: mpfs: add module_authors entries clk: microchip: mpfs: add MSS pll's set & round rate clk: microchip: mpfs: move id & offset out of clock structs clk: microchip: mpfs: simplify control reg access clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() clk: microchip: mpfs: convert cfg_clk to clk_divider clk: microchip: mpfs: convert periph_clk to clk_gate .../bindings/clock/microchip,mpfs.yaml | 17 +- .../devicetree/bindings/net/cdns,macb.yaml | 1 + MAINTAINERS | 1 + arch/riscv/boot/dts/microchip/mpfs.dtsi | 7 +- drivers/clk/microchip/Kconfig | 1 + drivers/clk/microchip/clk-mpfs.c | 377 +++++++++--------- drivers/net/ethernet/cadence/macb_main.c | 25 +- drivers/reset/Kconfig | 9 + drivers/reset/Makefile | 2 +- drivers/reset/reset-mpfs.c | 145 +++++++ include/soc/microchip/mpfs.h | 8 + 11 files changed, 393 insertions(+), 200 deletions(-) create mode 100644 drivers/reset/reset-mpfs.c base-commit: b13baccc3850ca8b8cccbf8ed9912dbaa0fdf7f3 -- 2.36.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2022-06-30 8:08 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-30 8:05 Conor Dooley [this message] 2022-06-30 8:05 ` [PATCH v1 00/14] PolarFire SoC reset controller & clock cleanups Conor Dooley 2022-06-30 8:05 ` [PATCH v1 01/14] dt-bindings: clk: microchip: mpfs: add reset controller support Conor Dooley 2022-06-30 8:05 ` Conor Dooley 2022-07-01 19:51 ` Rob Herring 2022-07-01 19:51 ` Rob Herring 2022-06-30 8:05 ` [PATCH v1 02/14] dt-bindings: net: cdns,macb: document polarfire soc's macb Conor Dooley 2022-06-30 8:05 ` Conor Dooley 2022-06-30 8:05 ` [PATCH v1 03/14] clk: microchip: mpfs: add reset controller Conor Dooley 2022-06-30 8:05 ` Conor Dooley 2022-06-30 8:05 ` [PATCH v1 04/14] reset: add polarfire soc reset support Conor Dooley 2022-06-30 8:05 ` Conor Dooley 2022-06-30 9:12 ` Philipp Zabel 2022-06-30 9:12 ` Philipp Zabel 2022-06-30 16:20 ` Conor.Dooley 2022-06-30 16:20 ` Conor.Dooley 2022-07-01 16:20 ` Conor.Dooley 2022-07-01 16:20 ` Conor.Dooley 2022-06-30 8:05 ` [PATCH v1 05/14] MAINTAINERS: add polarfire soc reset controller Conor Dooley 2022-06-30 8:05 ` Conor Dooley 2022-06-30 8:05 ` [PATCH v1 06/14] net: macb: add polarfire soc reset support Conor Dooley 2022-06-30 8:05 ` Conor Dooley 2022-06-30 16:02 ` Jakub Kicinski 2022-06-30 16:02 ` Jakub Kicinski 2022-06-30 16:14 ` Conor.Dooley 2022-06-30 16:14 ` Conor.Dooley 2022-06-30 8:05 ` [PATCH v1 07/14] riscv: dts: microchip: add mpfs specific macb " Conor Dooley 2022-06-30 8:05 ` Conor Dooley 2022-06-30 8:05 ` [PATCH v1 08/14] clk: microchip: mpfs: add module_authors entries Conor Dooley 2022-06-30 8:05 ` Conor Dooley 2022-06-30 8:05 ` [PATCH v1 09/14] clk: microchip: mpfs: add MSS pll's set & round rate Conor Dooley 2022-06-30 8:05 ` Conor Dooley 2022-06-30 8:05 ` [PATCH v1 10/14] clk: microchip: mpfs: move id & offset out of clock structs Conor Dooley 2022-06-30 8:05 ` Conor Dooley 2022-06-30 8:05 ` [PATCH v1 11/14] clk: microchip: mpfs: simplify control reg access Conor Dooley 2022-06-30 8:05 ` Conor Dooley 2022-06-30 8:05 ` [PATCH v1 12/14] clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() Conor Dooley 2022-06-30 8:05 ` Conor Dooley 2022-06-30 8:05 ` [PATCH v1 13/14] clk: microchip: mpfs: convert cfg_clk to clk_divider Conor Dooley 2022-06-30 8:05 ` Conor Dooley 2022-07-02 14:50 ` Conor.Dooley 2022-07-02 14:50 ` Conor.Dooley 2022-06-30 8:05 ` [PATCH v1 14/14] clk: microchip: mpfs: convert periph_clk to clk_gate Conor Dooley 2022-06-30 8:05 ` Conor Dooley
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