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From: Conor Dooley <conor.dooley@microchip.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	"David S . Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	"Nicolas Ferre" <nicolas.ferre@microchip.com>,
	Claudiu Beznea <claudiu.beznea@microchip.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	"Daire McNamara" <daire.mcnamara@microchip.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>, <linux-clk@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<netdev@vger.kernel.org>, <linux-riscv@lists.infradead.org>
Subject: [PATCH v1 01/14] dt-bindings: clk: microchip: mpfs: add reset controller support
Date: Thu, 30 Jun 2022 09:05:20 +0100	[thread overview]
Message-ID: <20220630080532.323731-2-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220630080532.323731-1-conor.dooley@microchip.com>

The "peripheral" devices on PolarFire SoC can be put into reset, so
update the device tree binding to reflect the presence of a reset
controller.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../bindings/clock/microchip,mpfs.yaml          | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
index 016a4f378b9b..1d0b6a4fda42 100644
--- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
+++ b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
@@ -40,8 +40,21 @@ properties:
     const: 1
     description: |
       The clock consumer should specify the desired clock by having the clock
-      ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h
-      for the full list of PolarFire clock IDs.
+      ID in its "clocks" phandle cell.
+      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
+      PolarFire clock IDs.
+
+  resets:
+    maxItems: 1
+
+  '#reset-cells':
+    description:
+      The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
+      CLK_ENVM to CLK_CFM. The reset consumer should specify the desired
+      peripheral via the clock ID in its "resets" phandle cell.
+      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
+      PolarFire clock IDs.
+    const: 1
 
 required:
   - compatible
-- 
2.36.1


WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	"David S . Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	"Nicolas Ferre" <nicolas.ferre@microchip.com>,
	Claudiu Beznea <claudiu.beznea@microchip.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	"Daire McNamara" <daire.mcnamara@microchip.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>, <linux-clk@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<netdev@vger.kernel.org>, <linux-riscv@lists.infradead.org>
Subject: [PATCH v1 01/14] dt-bindings: clk: microchip: mpfs: add reset controller support
Date: Thu, 30 Jun 2022 09:05:20 +0100	[thread overview]
Message-ID: <20220630080532.323731-2-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220630080532.323731-1-conor.dooley@microchip.com>

The "peripheral" devices on PolarFire SoC can be put into reset, so
update the device tree binding to reflect the presence of a reset
controller.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../bindings/clock/microchip,mpfs.yaml          | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
index 016a4f378b9b..1d0b6a4fda42 100644
--- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
+++ b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
@@ -40,8 +40,21 @@ properties:
     const: 1
     description: |
       The clock consumer should specify the desired clock by having the clock
-      ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h
-      for the full list of PolarFire clock IDs.
+      ID in its "clocks" phandle cell.
+      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
+      PolarFire clock IDs.
+
+  resets:
+    maxItems: 1
+
+  '#reset-cells':
+    description:
+      The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
+      CLK_ENVM to CLK_CFM. The reset consumer should specify the desired
+      peripheral via the clock ID in its "resets" phandle cell.
+      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
+      PolarFire clock IDs.
+    const: 1
 
 required:
   - compatible
-- 
2.36.1


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  reply	other threads:[~2022-06-30  8:08 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-30  8:05 [PATCH v1 00/14] PolarFire SoC reset controller & clock cleanups Conor Dooley
2022-06-30  8:05 ` Conor Dooley
2022-06-30  8:05 ` Conor Dooley [this message]
2022-06-30  8:05   ` [PATCH v1 01/14] dt-bindings: clk: microchip: mpfs: add reset controller support Conor Dooley
2022-07-01 19:51   ` Rob Herring
2022-07-01 19:51     ` Rob Herring
2022-06-30  8:05 ` [PATCH v1 02/14] dt-bindings: net: cdns,macb: document polarfire soc's macb Conor Dooley
2022-06-30  8:05   ` Conor Dooley
2022-06-30  8:05 ` [PATCH v1 03/14] clk: microchip: mpfs: add reset controller Conor Dooley
2022-06-30  8:05   ` Conor Dooley
2022-06-30  8:05 ` [PATCH v1 04/14] reset: add polarfire soc reset support Conor Dooley
2022-06-30  8:05   ` Conor Dooley
2022-06-30  9:12   ` Philipp Zabel
2022-06-30  9:12     ` Philipp Zabel
2022-06-30 16:20     ` Conor.Dooley
2022-06-30 16:20       ` Conor.Dooley
2022-07-01 16:20       ` Conor.Dooley
2022-07-01 16:20         ` Conor.Dooley
2022-06-30  8:05 ` [PATCH v1 05/14] MAINTAINERS: add polarfire soc reset controller Conor Dooley
2022-06-30  8:05   ` Conor Dooley
2022-06-30  8:05 ` [PATCH v1 06/14] net: macb: add polarfire soc reset support Conor Dooley
2022-06-30  8:05   ` Conor Dooley
2022-06-30 16:02   ` Jakub Kicinski
2022-06-30 16:02     ` Jakub Kicinski
2022-06-30 16:14     ` Conor.Dooley
2022-06-30 16:14       ` Conor.Dooley
2022-06-30  8:05 ` [PATCH v1 07/14] riscv: dts: microchip: add mpfs specific macb " Conor Dooley
2022-06-30  8:05   ` Conor Dooley
2022-06-30  8:05 ` [PATCH v1 08/14] clk: microchip: mpfs: add module_authors entries Conor Dooley
2022-06-30  8:05   ` Conor Dooley
2022-06-30  8:05 ` [PATCH v1 09/14] clk: microchip: mpfs: add MSS pll's set & round rate Conor Dooley
2022-06-30  8:05   ` Conor Dooley
2022-06-30  8:05 ` [PATCH v1 10/14] clk: microchip: mpfs: move id & offset out of clock structs Conor Dooley
2022-06-30  8:05   ` Conor Dooley
2022-06-30  8:05 ` [PATCH v1 11/14] clk: microchip: mpfs: simplify control reg access Conor Dooley
2022-06-30  8:05   ` Conor Dooley
2022-06-30  8:05 ` [PATCH v1 12/14] clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() Conor Dooley
2022-06-30  8:05   ` Conor Dooley
2022-06-30  8:05 ` [PATCH v1 13/14] clk: microchip: mpfs: convert cfg_clk to clk_divider Conor Dooley
2022-06-30  8:05   ` Conor Dooley
2022-07-02 14:50   ` Conor.Dooley
2022-07-02 14:50     ` Conor.Dooley
2022-06-30  8:05 ` [PATCH v1 14/14] clk: microchip: mpfs: convert periph_clk to clk_gate Conor Dooley
2022-06-30  8:05   ` Conor Dooley

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