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From: Andrew Davis <afd@ti.com>
To: Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,
	Tero Kristo <kristo@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: Andrew Davis <afd@ti.com>
Subject: [PATCH v2 4/4] arm64: dts: ti: k3-j7200-mcu-wakeup: Add SA2UL node
Date: Wed, 6 Jul 2022 14:08:38 -0500	[thread overview]
Message-ID: <20220706190838.26074-4-afd@ti.com> (raw)
In-Reply-To: <20220706190838.26074-1-afd@ti.com>

J7200 has an instance of SA2UL in the MCU domain.
Add DT node for the same.

The device is marked TI_SCI_PD_SHARED as parts of this IP are also
shared with the security co-processor and OP-TEE.

The RNG node is added but marked disabled as it is firewalled off for
exclusive use by OP-TEE. Any access to this device from Linux will
result in firewall errors. We add the node for completeness of the
hardware description.

Signed-off-by: Andrew Davis <afd@ti.com>
---

Changes from v1:
 - Added comment in dtsi file
 - Added extra context to commit message

 .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index 1044ec6c4b0d4..a37280200c401 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -375,4 +375,24 @@ mcu_r5fss0_core1: r5f@41400000 {
 			ti,loczrama = <1>;
 		};
 	};
+
+	mcu_crypto: crypto@40900000 {
+		compatible = "ti,j721e-sa2ul";
+		reg = <0x00 0x40900000 0x00 0x1200>;
+		power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
+		dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
+		       <&mcu_udmap 0x7503>;
+		dma-names = "tx", "rx1", "rx2";
+		dma-coherent;
+
+		rng: rng@40910000 {
+			compatible = "inside-secure,safexcel-eip76";
+			reg = <0x00 0x40910000 0x00 0x7d>;
+			interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled"; /* Used by OP-TEE */
+		};
+	};
 };
-- 
2.36.1


WARNING: multiple messages have this Message-ID (diff)
From: Andrew Davis <afd@ti.com>
To: Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,
	Tero Kristo <kristo@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: Andrew Davis <afd@ti.com>
Subject: [PATCH v2 4/4] arm64: dts: ti: k3-j7200-mcu-wakeup: Add SA2UL node
Date: Wed, 6 Jul 2022 14:08:38 -0500	[thread overview]
Message-ID: <20220706190838.26074-4-afd@ti.com> (raw)
In-Reply-To: <20220706190838.26074-1-afd@ti.com>

J7200 has an instance of SA2UL in the MCU domain.
Add DT node for the same.

The device is marked TI_SCI_PD_SHARED as parts of this IP are also
shared with the security co-processor and OP-TEE.

The RNG node is added but marked disabled as it is firewalled off for
exclusive use by OP-TEE. Any access to this device from Linux will
result in firewall errors. We add the node for completeness of the
hardware description.

Signed-off-by: Andrew Davis <afd@ti.com>
---

Changes from v1:
 - Added comment in dtsi file
 - Added extra context to commit message

 .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index 1044ec6c4b0d4..a37280200c401 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -375,4 +375,24 @@ mcu_r5fss0_core1: r5f@41400000 {
 			ti,loczrama = <1>;
 		};
 	};
+
+	mcu_crypto: crypto@40900000 {
+		compatible = "ti,j721e-sa2ul";
+		reg = <0x00 0x40900000 0x00 0x1200>;
+		power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
+		dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
+		       <&mcu_udmap 0x7503>;
+		dma-names = "tx", "rx1", "rx2";
+		dma-coherent;
+
+		rng: rng@40910000 {
+			compatible = "inside-secure,safexcel-eip76";
+			reg = <0x00 0x40910000 0x00 0x7d>;
+			interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled"; /* Used by OP-TEE */
+		};
+	};
 };
-- 
2.36.1


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  parent reply	other threads:[~2022-07-06 19:08 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-06 19:08 [PATCH v2 1/4] arm64: dts: ti: k3-am65-main: Disable RNG node Andrew Davis
2022-07-06 19:08 ` Andrew Davis
2022-07-06 19:08 ` [PATCH v2 2/4] arm64: dts: ti: k3-am65-main: Move SA2UL to unused PSI-L thread ID Andrew Davis
2022-07-06 19:08   ` Andrew Davis
2022-07-06 19:08 ` [PATCH v2 3/4] arm64: dts: ti: k3-am65-main: Do not exclusively claim SA2UL Andrew Davis
2022-07-06 19:08   ` Andrew Davis
2022-07-06 19:08 ` Andrew Davis [this message]
2022-07-06 19:08   ` [PATCH v2 4/4] arm64: dts: ti: k3-j7200-mcu-wakeup: Add SA2UL node Andrew Davis
2022-07-07 14:44 ` [PATCH v2 1/4] arm64: dts: ti: k3-am65-main: Disable RNG node Bryan Brattlof
2022-07-07 14:44   ` Bryan Brattlof
2022-07-07 15:01   ` Andrew Davis
2022-07-07 15:01     ` Andrew Davis
2022-07-07 17:17     ` Nishanth Menon
2022-07-07 17:17       ` Nishanth Menon
2022-07-07 17:36       ` Andrew Davis
2022-07-07 17:36         ` Andrew Davis
2022-07-08 22:09         ` Nishanth Menon
2022-07-08 22:09           ` Nishanth Menon
2022-08-23  0:11 Andrew Davis
2022-08-23  0:11 ` [PATCH v2 4/4] arm64: dts: ti: k3-j7200-mcu-wakeup: Add SA2UL node Andrew Davis
2022-08-23  0:11   ` Andrew Davis
2022-08-30 10:04   ` Jayesh Choudhary
2022-08-30 10:04     ` Jayesh Choudhary

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