From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 04/11] ASoC: jz4740-i2s: Handle independent FIFO flush bits Date: Thu, 7 Jul 2022 20:46:48 +0100 [thread overview] Message-ID: <20220707194655.312892-5-aidanmacdonald.0x0@gmail.com> (raw) In-Reply-To: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> On the JZ4740, there is a single bit that flushes (empties) both the transmit and receive FIFO. Later SoCs have independent flush bits for each FIFO, which allows us to flush the right FIFO when starting up a stream. This also fixes a bug: since we were only setting the JZ4740's flush bit, which corresponds to the TX FIFO flush bit on other SoCs, other SoCs were not having their RX FIFO flushed at all. Fixes: 967beb2e8777 ("ASoC: jz4740: Add jz4780 support") Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> --- sound/soc/jz4740/jz4740-i2s.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index bd73427b837e..043f100a9cfa 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -58,6 +58,9 @@ #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) +#define JZ4760_AIC_CTRL_TFLUSH BIT(8) +#define JZ4760_AIC_CTRL_RFLUSH BIT(7) + #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16 @@ -75,6 +78,8 @@ struct i2s_soc_info { struct reg_field field_tx_fifo_thresh; struct reg_field field_i2sdiv_capture; struct reg_field field_i2sdiv_playback; + + bool shared_fifo_flush; }; struct jz4740_i2s { @@ -100,10 +105,26 @@ static int jz4740_i2s_startup(struct snd_pcm_substream *substream, struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); int ret; + /* + * When we can flush FIFOs independently, only flush the + * FIFO that is starting up. + */ + if (!i2s->soc_info->shared_fifo_flush) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ4760_AIC_CTRL_TFLUSH); + else + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ4760_AIC_CTRL_RFLUSH); + } + if (snd_soc_dai_active(dai)) return 0; - regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_FLUSH); + /* + * When there is a shared flush bit for both FIFOs we can + * only flush the FIFOs if no other stream has started. + */ + if (i2s->soc_info->shared_fifo_flush) + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_FLUSH); ret = clk_prepare_enable(i2s->clk_i2s); if (ret) @@ -382,6 +403,7 @@ static const struct i2s_soc_info jz4740_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .shared_fifo_flush = true, }; static const struct i2s_soc_info jz4760_i2s_soc_info = { -- 2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: alsa-devel@alsa-project.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 04/11] ASoC: jz4740-i2s: Handle independent FIFO flush bits Date: Thu, 7 Jul 2022 20:46:48 +0100 [thread overview] Message-ID: <20220707194655.312892-5-aidanmacdonald.0x0@gmail.com> (raw) In-Reply-To: <20220707194655.312892-1-aidanmacdonald.0x0@gmail.com> On the JZ4740, there is a single bit that flushes (empties) both the transmit and receive FIFO. Later SoCs have independent flush bits for each FIFO, which allows us to flush the right FIFO when starting up a stream. This also fixes a bug: since we were only setting the JZ4740's flush bit, which corresponds to the TX FIFO flush bit on other SoCs, other SoCs were not having their RX FIFO flushed at all. Fixes: 967beb2e8777 ("ASoC: jz4740: Add jz4780 support") Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> --- sound/soc/jz4740/jz4740-i2s.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index bd73427b837e..043f100a9cfa 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -58,6 +58,9 @@ #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) +#define JZ4760_AIC_CTRL_TFLUSH BIT(8) +#define JZ4760_AIC_CTRL_RFLUSH BIT(7) + #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16 @@ -75,6 +78,8 @@ struct i2s_soc_info { struct reg_field field_tx_fifo_thresh; struct reg_field field_i2sdiv_capture; struct reg_field field_i2sdiv_playback; + + bool shared_fifo_flush; }; struct jz4740_i2s { @@ -100,10 +105,26 @@ static int jz4740_i2s_startup(struct snd_pcm_substream *substream, struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); int ret; + /* + * When we can flush FIFOs independently, only flush the + * FIFO that is starting up. + */ + if (!i2s->soc_info->shared_fifo_flush) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ4760_AIC_CTRL_TFLUSH); + else + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ4760_AIC_CTRL_RFLUSH); + } + if (snd_soc_dai_active(dai)) return 0; - regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_FLUSH); + /* + * When there is a shared flush bit for both FIFOs we can + * only flush the FIFOs if no other stream has started. + */ + if (i2s->soc_info->shared_fifo_flush) + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_FLUSH); ret = clk_prepare_enable(i2s->clk_i2s); if (ret) @@ -382,6 +403,7 @@ static const struct i2s_soc_info jz4740_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .shared_fifo_flush = true, }; static const struct i2s_soc_info jz4760_i2s_soc_info = { -- 2.35.1
next prev parent reply other threads:[~2022-07-07 19:46 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-07-07 19:46 [PATCH v2 0/11] ASoC: cleanups and improvements for jz4740-i2s Aidan MacDonald 2022-07-07 19:46 ` Aidan MacDonald 2022-07-07 19:46 ` [PATCH v2 01/11] ASoC: jz4740-i2s: Remove unused 'mem' resource Aidan MacDonald 2022-07-07 19:46 ` Aidan MacDonald 2022-07-07 20:19 ` Paul Cercueil 2022-07-07 20:19 ` Paul Cercueil 2022-07-07 19:46 ` [PATCH v2 02/11] ASoC: jz4740-i2s: Convert to regmap API Aidan MacDonald 2022-07-07 19:46 ` Aidan MacDonald 2022-07-07 19:46 ` [PATCH v2 03/11] ASoC: jz4740-i2s: Simplify using regmap fields Aidan MacDonald 2022-07-07 19:46 ` Aidan MacDonald 2022-07-07 19:46 ` Aidan MacDonald [this message] 2022-07-07 19:46 ` [PATCH v2 04/11] ASoC: jz4740-i2s: Handle independent FIFO flush bits Aidan MacDonald 2022-07-07 19:46 ` [PATCH v2 05/11] ASoC: jz4740-i2s: Use FIELD_PREP() macros in hw_params callback Aidan MacDonald 2022-07-07 19:46 ` Aidan MacDonald 2022-07-07 19:46 ` [PATCH v2 06/11] ASoC: jz4740-i2s: Align macro values and sort includes Aidan MacDonald 2022-07-07 19:46 ` Aidan MacDonald 2022-07-07 19:46 ` [PATCH v2 07/11] ASoC: jz4740-i2s: Make the PLL clock name SoC-specific Aidan MacDonald 2022-07-07 19:46 ` Aidan MacDonald 2022-07-07 19:46 ` [PATCH v2 08/11] ASoC: jz4740-i2s: Support S20_LE and S24_LE sample formats Aidan MacDonald 2022-07-07 19:46 ` Aidan MacDonald 2022-07-07 19:46 ` [PATCH v2 09/11] ASoC: jz4740-i2s: Support continuous sample rate Aidan MacDonald 2022-07-07 19:46 ` Aidan MacDonald 2022-07-07 19:46 ` [PATCH v2 10/11] ASoC: jz4740-i2s: Move component functions near the component driver Aidan MacDonald 2022-07-07 19:46 ` Aidan MacDonald 2022-07-07 19:46 ` [PATCH v2 11/11] ASoC: jz4740-i2s: Refactor DAI probe/remove ops as component ops Aidan MacDonald 2022-07-07 19:46 ` Aidan MacDonald 2022-07-08 0:43 ` kernel test robot 2022-07-08 0:43 ` kernel test robot 2022-07-08 4:48 ` kernel test robot 2022-07-08 4:48 ` kernel test robot
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