* [PATCH 5.10.y-cip 01/13] arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1
2022-08-03 16:53 [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC Biju Das
@ 2022-08-03 16:53 ` Biju Das
2022-08-03 16:53 ` [PATCH 5.10.y-cip 02/13] arm64: dts: renesas: rzg2lc-smarc: Use SW_SD0_DEV_SEL macro for eMMC/SDHI device selection Biju Das
` (12 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Biju Das @ 2022-08-03 16:53 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
commit 46da632734a5979090ef588d9da40367581fd400 upstream.
On RZ/G2LC SMARC EVK, CAN0 is not populated.
CAN1 is multiplexed with SCIF1 using SW1[3] or RSPI using SW1[4].
This patch adds support for the CAN1 interface on RZ/G2LC SMARC EVK.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220203170636.7747-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../boot/dts/renesas/r9a07g044c2-smarc.dts | 6 -----
.../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 23 +++++++++++++++++++
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 13 +++++++++++
3 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
index 50abdabc374a..5a5cea82a5d9 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
@@ -14,12 +14,6 @@ / {
compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
};
-&canfd {
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- status = "disabled";
-};
-
&ehci0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
index ec9e08ec0822..bff56d696936 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -17,6 +17,14 @@ scif0_pins: scif0 {
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
+#if SW_SCIF_CAN
+ /* SW8 should be at position 2->1 */
+ can1_pins: can1 {
+ pinmux = <RZG2L_PORT_PINMUX(40, 0, 3)>, /* TxD */
+ <RZG2L_PORT_PINMUX(40, 1, 3)>; /* RxD */
+ };
+#endif
+
scif1_pins: scif1 {
pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
@@ -24,6 +32,21 @@ scif1_pins: scif1 {
<RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
};
+#if SW_RSPI_CAN
+ /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
+ can1-stb {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(44, 3) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "can1_stb";
+ };
+
+ can1_pins: can1 {
+ pinmux = <RZG2L_PORT_PINMUX(44, 0, 3)>, /* TxD */
+ <RZG2L_PORT_PINMUX(44, 1, 3)>; /* RxD */
+ };
+#endif
+
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
index 1b59ef376296..28f21c287ba3 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -44,6 +44,19 @@ aliases {
};
};
+#if (SW_SCIF_CAN || SW_RSPI_CAN)
+&canfd {
+ pinctrl-0 = <&can1_pins>;
+ /delete-node/ channel@0;
+};
+#else
+&canfd {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+#endif
+
/*
* To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
* SW1 should be at position 2->3 so that SER0_CTS# line is activated
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 5.10.y-cip 02/13] arm64: dts: renesas: rzg2lc-smarc: Use SW_SD0_DEV_SEL macro for eMMC/SDHI device selection
2022-08-03 16:53 [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC Biju Das
2022-08-03 16:53 ` [PATCH 5.10.y-cip 01/13] arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1 Biju Das
@ 2022-08-03 16:53 ` Biju Das
2022-08-03 16:53 ` [PATCH 5.10.y-cip 03/13] arm64: dts: renesas: rzg2lc-smarc-som: Enable watchdog Biju Das
` (11 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Biju Das @ 2022-08-03 16:53 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
commit 5c65ad12785205d5c57bd92e19d0296f93c19e33 upstream.
This patch replaces EMMC/SDHI macros with SW_SD0_DEV_SEL DIP-Switch
macro for eMMC/SDHI device selection.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220204143132.3608-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 14 ++------------
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 2 ++
2 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
index 6ebda3724f2c..90cb7ec45751 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -8,16 +8,6 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
-/* SW1[2] should be at OFF position to enable 64 GB eMMC */
-#define EMMC 1
-
-/*
- * To enable uSD card on CN3,
- * SW1[2] should be at ON position.
- * Disable eMMC by setting "#define EMMC 0" above.
- */
-#define SDHI (!EMMC)
-
/ {
aliases {
ethernet0 = ð0;
@@ -185,7 +175,7 @@ sd0_mux_uhs {
};
};
-#if SDHI
+#if (!SW_SD0_DEV_SEL)
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
@@ -200,7 +190,7 @@ &sdhi0 {
};
#endif
-#if EMMC
+#if SW_SD0_DEV_SEL
&sdhi0 {
pinctrl-0 = <&sdhi0_emmc_pins>;
pinctrl-1 = <&sdhi0_emmc_pins>;
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
index 28f21c287ba3..df7631fe5fac 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -18,6 +18,8 @@
* Please change below macros according to SW1 setting
*/
+#define SW_SD0_DEV_SEL 1
+
#define SW_SCIF_CAN 0
#if (SW_SCIF_CAN)
/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 5.10.y-cip 03/13] arm64: dts: renesas: rzg2lc-smarc-som: Enable watchdog
2022-08-03 16:53 [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC Biju Das
2022-08-03 16:53 ` [PATCH 5.10.y-cip 01/13] arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1 Biju Das
2022-08-03 16:53 ` [PATCH 5.10.y-cip 02/13] arm64: dts: renesas: rzg2lc-smarc: Use SW_SD0_DEV_SEL macro for eMMC/SDHI device selection Biju Das
@ 2022-08-03 16:53 ` Biju Das
2022-08-03 16:53 ` [PATCH 5.10.y-cip 04/13] arm64: dts: renesas: Align GPIO hog names with dtschema Biju Das
` (10 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Biju Das @ 2022-08-03 16:53 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
commit d05e409e4a66f62e863b140bd1c784f2d93f2562 upstream.
Enable watchdog{0, 1, 2} interfaces on RZ/G2LC SMARC EVK.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220223165813.24833-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
index 90cb7ec45751..88a7938017aa 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -206,3 +206,17 @@ &sdhi0 {
};
#endif
+&wdt0 {
+ status = "okay";
+ timeout-sec = <60>;
+};
+
+&wdt1 {
+ status = "okay";
+ timeout-sec = <60>;
+};
+
+&wdt2 {
+ status = "okay";
+ timeout-sec = <60>;
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 5.10.y-cip 04/13] arm64: dts: renesas: Align GPIO hog names with dtschema
2022-08-03 16:53 [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC Biju Das
` (2 preceding siblings ...)
2022-08-03 16:53 ` [PATCH 5.10.y-cip 03/13] arm64: dts: renesas: rzg2lc-smarc-som: Enable watchdog Biju Das
@ 2022-08-03 16:53 ` Biju Das
2022-08-03 16:53 ` [PATCH 5.10.y-cip 05/13] arm64: dts: renesas: r9a07g044c2-smarc: Enable usb2.0 Biju Das
` (9 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Biju Das @ 2022-08-03 16:53 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit 48d8ee5b831ec8b6dbe3b4313fed0adcd752e20b upstream.
Dtschema expects GPIO hogs to end with a "hog" suffix.
Also, the convention for node names is to use hyphens, not underscores.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/baee4b9980576ffbab24122fce7147c9cbc2ea59.1645705998.git.geert+renesas@glider.be
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 2 +-
arch/arm64/boot/dts/renesas/hihope-common.dtsi | 2 +-
arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts | 2 +-
arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts | 4 ++--
arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi | 4 ++--
arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 2 +-
7 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
index 929c7910c68d..b6b6d085600a 100644
--- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
@@ -77,7 +77,7 @@ &extalr_clk {
};
&gpio6 {
- usb_hub_reset {
+ usb-hub-reset-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-high;
diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
index e8bf6f0c4c40..18f01dbb25f5 100644
--- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
@@ -140,7 +140,7 @@ &extalr_clk {
};
&gpio6 {
- usb1-reset {
+ usb1-reset-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_LOW>;
output-low;
diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi
index 40c5e8d6d841..d66d17e34694 100644
--- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi
@@ -20,7 +20,7 @@ &gpio1 {
* When GP1_20 is LOW LVDS0 is connected to the LVDS connector
* When GP1_20 is HIGH LVDS0 is connected to the LT8918L
*/
- lvds-connector-en-gpio {
+ lvds-connector-en-hog {
gpio-hog;
gpios = <20 GPIO_ACTIVE_HIGH>;
output-low;
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts
index a7b27d09f6c2..c1812d1ef06a 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts
@@ -68,7 +68,7 @@ &gpio0 {
* When GP0_17 is low LVDS[01] are connected to the LVDS connector
* When GP0_17 is high LVDS[01] are connected to the LT8918L
*/
- lvds-connector-en-gpio{
+ lvds-connector-en-hog {
gpio-hog;
gpios = <17 GPIO_ACTIVE_HIGH>;
output-low;
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
index 49d141db53f7..fc334b4c2aa4 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
@@ -18,8 +18,8 @@ / {
};
&pinctrl {
- /delete-node/ can0-stb;
- /delete-node/ can1-stb;
+ /delete-node/ can0-stb-hog;
+ /delete-node/ can1-stb-hog;
/delete-node/ gpio-sd0-pwr-en-hog;
/delete-node/ sd0-dev-sel-hog;
/delete-node/ sd1-pwr-en-hog;
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
index 2ef217445f72..9085d8c76ce1 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
@@ -18,7 +18,7 @@ can0_pins: can0 {
};
/* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
- can0-stb {
+ can0-stb-hog {
gpio-hog;
gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
output-low;
@@ -31,7 +31,7 @@ can1_pins: can1 {
};
/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
- can1-stb {
+ can1-stb-hog {
gpio-hog;
gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
output-low;
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
index bff56d696936..37ff2091582e 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -34,7 +34,7 @@ scif1_pins: scif1 {
#if SW_RSPI_CAN
/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
- can1-stb {
+ can1-stb-hog {
gpio-hog;
gpios = <RZG2L_GPIO(44, 3) GPIO_ACTIVE_HIGH>;
output-low;
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 5.10.y-cip 05/13] arm64: dts: renesas: r9a07g044c2-smarc: Enable usb2.0
2022-08-03 16:53 [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC Biju Das
` (3 preceding siblings ...)
2022-08-03 16:53 ` [PATCH 5.10.y-cip 04/13] arm64: dts: renesas: Align GPIO hog names with dtschema Biju Das
@ 2022-08-03 16:53 ` Biju Das
2022-08-03 16:53 ` [PATCH 5.10.y-cip 06/13] arm64: dts: renesas: rzg2lc-smarc-pinfunction: Sort the nodes Biju Das
` (8 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Biju Das @ 2022-08-03 16:53 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
commit 1889f4798c443dfd4993ba9bbbf4ed7bf801d94b upstream.
Enable usb2.0 host/device functionality on RZ/G2LC SMARC EVK
by deleting phyrst, usb2_phy{0,1}, ehci/ohci{0,1} and hsusb
entries from board DT, so that entries from common dtsi kick
in and make USB2.0 functionality operational.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220302074043.21525-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../boot/dts/renesas/r9a07g044c2-smarc.dts | 46 -------------------
.../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 11 +++++
2 files changed, 11 insertions(+), 46 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
index 5a5cea82a5d9..d5254b16b0b3 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
@@ -14,24 +14,6 @@ / {
compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
};
-&ehci0 {
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- status = "disabled";
-};
-
-&ehci1 {
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- status = "disabled";
-};
-
-&hsusb {
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- status = "disabled";
-};
-
&i2c0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
@@ -50,22 +32,6 @@ &i2c3 {
status = "disabled";
};
-&ohci0 {
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- status = "disabled";
-};
-
-&ohci1 {
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- status = "disabled";
-};
-
-&phyrst {
- status = "disabled";
-};
-
&spi1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
@@ -77,15 +43,3 @@ &ssi0 {
/delete-property/ pinctrl-names;
status = "disabled";
};
-
-&usb2_phy0 {
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- status = "disabled";
-};
-
-&usb2_phy1 {
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
index 37ff2091582e..5f5ec21e655c 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -90,5 +90,16 @@ sound_clk_pins: sound_clk {
pins = "AUDIO_CLK1", "AUDIO_CLK2";
input-enable;
};
+
+ usb0_pins: usb0 {
+ pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
+ <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
+ <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
+ };
+
+ usb1_pins: usb1 {
+ pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
+ <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
+ };
};
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 5.10.y-cip 06/13] arm64: dts: renesas: rzg2lc-smarc-pinfunction: Sort the nodes
2022-08-03 16:53 [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC Biju Das
` (4 preceding siblings ...)
2022-08-03 16:53 ` [PATCH 5.10.y-cip 05/13] arm64: dts: renesas: r9a07g044c2-smarc: Enable usb2.0 Biju Das
@ 2022-08-03 16:53 ` Biju Das
2022-08-03 16:53 ` [PATCH 5.10.y-cip 07/13] arm64: dts: renesas: rzg2l-smarc: Move out i2c3 and Audio codec from common dtsi Biju Das
` (7 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Biju Das @ 2022-08-03 16:53 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
commit a2b642d89e4beeddbfbd7be6108db2b7aaef78b6 upstream.
Sort the pinctrl nodes alphabetically.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220303164155.7706-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 24 +++++++++----------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
index 5f5ec21e655c..53759c3ddecb 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -12,11 +12,6 @@ &pinctrl {
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
- scif0_pins: scif0 {
- pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
- <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
- };
-
#if SW_SCIF_CAN
/* SW8 should be at position 2->1 */
can1_pins: can1 {
@@ -25,13 +20,6 @@ can1_pins: can1 {
};
#endif
- scif1_pins: scif1 {
- pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
- <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
- <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
- <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
- };
-
#if SW_RSPI_CAN
/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
can1-stb-hog {
@@ -47,6 +35,18 @@ can1_pins: can1 {
};
#endif
+ scif0_pins: scif0 {
+ pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
+ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
+ };
+
+ scif1_pins: scif1 {
+ pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
+ <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
+ <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
+ <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
+ };
+
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 5.10.y-cip 07/13] arm64: dts: renesas: rzg2l-smarc: Move out i2c3 and Audio codec from common dtsi
2022-08-03 16:53 [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC Biju Das
` (5 preceding siblings ...)
2022-08-03 16:53 ` [PATCH 5.10.y-cip 06/13] arm64: dts: renesas: rzg2lc-smarc-pinfunction: Sort the nodes Biju Das
@ 2022-08-03 16:53 ` Biju Das
2022-08-03 16:53 ` [PATCH 5.10.y-cip 08/13] arm64: dts: renesas: rzg2lc-smarc: Enable i2c{0,1,2} Biju Das
` (6 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Biju Das @ 2022-08-03 16:53 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
commit 0a7c1c888a0c0276837f2cd7190683474a136506 upstream.
On RZ/G2L SoM module, the Audio codec is connected to i2c3 bus whereas on
RZ/G2LC, it is connected to i2c2 bus. So move out i2c3 and wm8978 nodes
from common dtsi to soc specific dtsi.
While at it add wm8978 node to RZ/G2LC SoC specific dtsi to fix the
build error.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220303164155.7706-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 6 ------
arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi | 15 ---------------
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 15 +++++++++++++++
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 11 +++++++++++
4 files changed, 26 insertions(+), 21 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
index d5254b16b0b3..dc39b05e9256 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
@@ -26,12 +26,6 @@ &i2c1 {
status = "disabled";
};
-&i2c3 {
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- status = "disabled";
-};
-
&spi1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
index 588117aafaca..8dd1c69a6749 100644
--- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
@@ -26,7 +26,6 @@ aliases {
serial0 = &scif0;
i2c0 = &i2c0;
i2c1 = &i2c1;
- i2c3 = &i2c3;
};
chosen {
@@ -131,20 +130,6 @@ &i2c1 {
status = "okay";
};
-&i2c3 {
- pinctrl-0 = <&i2c3_pins>;
- pinctrl-names = "default";
- clock-frequency = <400000>;
-
- status = "okay";
-
- wm8978: codec@1a {
- compatible = "wlf,wm8978";
- #sound-dai-cells = <0>;
- reg = <0x1a>;
- };
-};
-
&ohci0 {
dr_mode = "otg";
status = "okay";
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 33ddfd18bd56..c934cd3633a4 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -14,6 +14,21 @@
/ {
aliases {
serial1 = &scif2;
+ i2c3 = &i2c3;
+ };
+};
+
+&i2c3 {
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ wm8978: codec@1a {
+ compatible = "wlf,wm8978";
+ #sound-dai-cells = <0>;
+ reg = <0x1a>;
};
};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
index df7631fe5fac..55d3b73f84e7 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -43,6 +43,7 @@
/ {
aliases {
serial1 = &scif1;
+ i2c2 = &i2c2;
};
};
@@ -59,6 +60,16 @@ &canfd {
};
#endif
+&i2c2 {
+ status = "disabled";
+
+ wm8978: codec@1a {
+ compatible = "wlf,wm8978";
+ #sound-dai-cells = <0>;
+ reg = <0x1a>;
+ };
+};
+
/*
* To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
* SW1 should be at position 2->3 so that SER0_CTS# line is activated
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 5.10.y-cip 08/13] arm64: dts: renesas: rzg2lc-smarc: Enable i2c{0,1,2}
2022-08-03 16:53 [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC Biju Das
` (6 preceding siblings ...)
2022-08-03 16:53 ` [PATCH 5.10.y-cip 07/13] arm64: dts: renesas: rzg2l-smarc: Move out i2c3 and Audio codec from common dtsi Biju Das
@ 2022-08-03 16:53 ` Biju Das
2022-08-03 16:53 ` [PATCH 5.10.y-cip 09/13] arm64: dts: renesas: rzg2lc-smarc: Enable Audio Biju Das
` (5 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Biju Das @ 2022-08-03 16:53 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
commit 4fa1edc83b2b2b467ed47bd682c7beab81a38ef5 upstream.
Enable i2c{0,1} on RZ/G2LC SMARC EVK by deleting respective
entries from board dts and adding pincontrol entries to the
soc-pinctrl dtsi. Also enable i2c2 by adding to soc dtsi.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220303164155.7706-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 12 ------------
.../dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 15 +++++++++++++++
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 6 +++++-
3 files changed, 20 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
index dc39b05e9256..52b834205126 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
@@ -14,18 +14,6 @@ / {
compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
};
-&i2c0 {
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- status = "disabled";
-};
-
-&i2c1 {
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- status = "disabled";
-};
-
&spi1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
index 53759c3ddecb..1322e5bcd456 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -35,6 +35,21 @@ can1_pins: can1 {
};
#endif
+ i2c0_pins: i2c0 {
+ pins = "RIIC0_SDA", "RIIC0_SCL";
+ input-enable;
+ };
+
+ i2c1_pins: i2c1 {
+ pins = "RIIC1_SDA", "RIIC1_SCL";
+ input-enable;
+ };
+
+ i2c2_pins: i2c2 {
+ pinmux = <RZG2L_PORT_PINMUX(42, 3, 1)>, /* SDA */
+ <RZG2L_PORT_PINMUX(42, 4, 1)>; /* SCL */
+ };
+
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
index 55d3b73f84e7..f73b4acb8f9e 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -61,7 +61,11 @@ &canfd {
#endif
&i2c2 {
- status = "disabled";
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+ clock-frequency = <400000>;
+
+ status = "okay";
wm8978: codec@1a {
compatible = "wlf,wm8978";
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 5.10.y-cip 09/13] arm64: dts: renesas: rzg2lc-smarc: Enable Audio
2022-08-03 16:53 [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC Biju Das
` (7 preceding siblings ...)
2022-08-03 16:53 ` [PATCH 5.10.y-cip 08/13] arm64: dts: renesas: rzg2lc-smarc: Enable i2c{0,1,2} Biju Das
@ 2022-08-03 16:53 ` Biju Das
2022-08-03 16:53 ` [PATCH 5.10.y-cip 10/13] arm64: dts: renesas: rzg2lc-smarc-som: Enable serial NOR flash Biju Das
` (4 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Biju Das @ 2022-08-03 16:53 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
commit 4eb6a6bb8ef31491c217167ecce2c0a26fd4f34e upstream.
Enable Audio on RZ/G2LC SMARC EVK by deleting ssi0 entries from
board DT and adding pincontrol entries to the soc-pinctrl dtsi,
so that entries from common dtsi kick in and make audio functionality
operational.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220303164155.7706-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 6 ------
arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 7 +++++++
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
index 52b834205126..74a2f2bade10 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
@@ -19,9 +19,3 @@ &spi1 {
/delete-property/ pinctrl-names;
status = "disabled";
};
-
-&ssi0 {
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
index 1322e5bcd456..d275a55333e3 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -106,6 +106,13 @@ sound_clk_pins: sound_clk {
input-enable;
};
+ ssi0_pins: ssi0 {
+ pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
+ <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
+ <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
+ <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
+ };
+
usb0_pins: usb0 {
pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
<RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 5.10.y-cip 10/13] arm64: dts: renesas: rzg2lc-smarc-som: Enable serial NOR flash
2022-08-03 16:53 [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC Biju Das
` (8 preceding siblings ...)
2022-08-03 16:53 ` [PATCH 5.10.y-cip 09/13] arm64: dts: renesas: rzg2lc-smarc: Enable Audio Biju Das
@ 2022-08-03 16:53 ` Biju Das
2022-08-03 16:53 ` [PATCH 5.10.y-cip 11/13] arm64: dts: renesas: rzg2lc-smarc-som: Enable OSTM Biju Das
` (3 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Biju Das @ 2022-08-03 16:53 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
commit 018d7b93477fbb04ba7b4bc4c355793d644e45da upstream.
Enable mt25qu512a flash connected to QSPI0.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220307192436.13237-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../boot/dts/renesas/rzg2lc-smarc-som.dtsi | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
index 88a7938017aa..80c9a1146cb7 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -110,6 +110,18 @@ gpio-sd0-pwr-en-hog {
line-name = "gpio_sd0_pwr_en";
};
+ qspi0_pins: qspi0 {
+ qspi0-data {
+ pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
+ power-source = <1800>;
+ };
+
+ qspi0-ctrl {
+ pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
+ power-source = <1800>;
+ };
+ };
+
/*
* SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
* The below switch logic can be used to select the device between
@@ -175,6 +187,34 @@ sd0_mux_uhs {
};
};
+&sbc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "micron,mt25qu512a", "jedec,spi-nor";
+ reg = <0>;
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot@0 {
+ reg = <0x00000000 0x2000000>;
+ read-only;
+ };
+ user@2000000 {
+ reg = <0x2000000 0x2000000>;
+ };
+ };
+ };
+};
+
#if (!SW_SD0_DEV_SEL)
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 5.10.y-cip 11/13] arm64: dts: renesas: rzg2lc-smarc-som: Enable OSTM
2022-08-03 16:53 [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC Biju Das
` (9 preceding siblings ...)
2022-08-03 16:53 ` [PATCH 5.10.y-cip 10/13] arm64: dts: renesas: rzg2lc-smarc-som: Enable serial NOR flash Biju Das
@ 2022-08-03 16:53 ` Biju Das
2022-08-03 16:53 ` [PATCH 5.10.y-cip 12/13] arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier board Biju Das
` (2 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Biju Das @ 2022-08-03 16:53 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
commit a081c4fe98f6662fbddb1597a6203be669641af1 upstream.
Enable OSTM{1, 2} interfaces on RZ/G2LC SMARC EVK.
OSTM0 is reserved for TF-A.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220307192436.13237-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
index 80c9a1146cb7..05b117ac414c 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -84,6 +84,14 @@ &extal_clk {
clock-frequency = <24000000>;
};
+&ostm1 {
+ status = "okay";
+};
+
+&ostm2 {
+ status = "okay";
+};
+
&pinctrl {
eth0_pins: eth0 {
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 5.10.y-cip 12/13] arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier board
2022-08-03 16:53 [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC Biju Das
` (10 preceding siblings ...)
2022-08-03 16:53 ` [PATCH 5.10.y-cip 11/13] arm64: dts: renesas: rzg2lc-smarc-som: Enable OSTM Biju Das
@ 2022-08-03 16:53 ` Biju Das
2022-08-03 16:53 ` [PATCH 5.10.y-cip 13/13] arm64: dts: renesas: rzg2l-smarc: Move gpios property of vccq_sdhi1 from common dtsi Biju Das
2022-08-04 5:03 ` [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC nobuhiro1.iwamatsu
13 siblings, 0 replies; 17+ messages in thread
From: Biju Das @ 2022-08-03 16:53 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
commit 061ba41c7449a9cf4bbf2b6930eb0ded69e5eead upstream.
RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the
carrier board. This patch adds pinmux and spi1 nodes to the carrier
board dtsi file and drops deleting pinctl* properties from DTS file.
RSPI1 interface is tested by setting the macro SW_RSPI_CAN to 0.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220401145702.17954-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 6 ------
arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 7 +++++++
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 8 ++++++++
3 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
index 74a2f2bade10..fc34058002e2 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
@@ -13,9 +13,3 @@ / {
model = "Renesas SMARC EVK based on r9a07g044c2";
compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
};
-
-&spi1 {
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
index d275a55333e3..a78a8def363e 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -106,6 +106,13 @@ sound_clk_pins: sound_clk {
input-enable;
};
+ spi1_pins: spi1 {
+ pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
+ <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
+ <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
+ <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
+ };
+
ssi0_pins: ssi0 {
pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
<RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
index f73b4acb8f9e..856c949796ff 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -90,3 +90,11 @@ &scif1 {
status = "okay";
};
#endif
+
+#if (SW_RSPI_CAN)
+&spi1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 5.10.y-cip 13/13] arm64: dts: renesas: rzg2l-smarc: Move gpios property of vccq_sdhi1 from common dtsi
2022-08-03 16:53 [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC Biju Das
` (11 preceding siblings ...)
2022-08-03 16:53 ` [PATCH 5.10.y-cip 12/13] arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier board Biju Das
@ 2022-08-03 16:53 ` Biju Das
2022-08-04 5:03 ` [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC nobuhiro1.iwamatsu
13 siblings, 0 replies; 17+ messages in thread
From: Biju Das @ 2022-08-03 16:53 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Chris Paterson, Biju Das, Prabhakar Mahadev Lad
commit f40846e7c9f50bfbba96d566c63cbdb57b817249 upstream.
On RZ/G2{L,LC} SoM module, gpio for power selection is connected to
P39_1 whereas on RZ/G2UL it is connected to P6_1. So move gpios property
of vccq_sdhi1 regulator from common dtsi to soc specific dtsi.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220401175427.19078-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi | 1 -
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 4 ++++
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 4 ++++
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
index 8dd1c69a6749..0e61b85efb43 100644
--- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
@@ -74,7 +74,6 @@ vccq_sdhi1: regulator-vccq-sdhi1 {
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
- gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index c934cd3633a4..aadc41515093 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -48,3 +48,7 @@ &scif2 {
status = "okay";
};
#endif
+
+&vccq_sdhi1 {
+ gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
index 856c949796ff..74a844ea7537 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -98,3 +98,7 @@ &spi1 {
status = "disabled";
};
#endif
+
+&vccq_sdhi1 {
+ gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* RE: [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC
2022-08-03 16:53 [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC Biju Das
` (12 preceding siblings ...)
2022-08-03 16:53 ` [PATCH 5.10.y-cip 13/13] arm64: dts: renesas: rzg2l-smarc: Move gpios property of vccq_sdhi1 from common dtsi Biju Das
@ 2022-08-04 5:03 ` nobuhiro1.iwamatsu
2022-08-04 9:16 ` Pavel Machek
13 siblings, 1 reply; 17+ messages in thread
From: nobuhiro1.iwamatsu @ 2022-08-04 5:03 UTC (permalink / raw)
To: biju.das.jz, cip-dev, pavel; +Cc: chris.paterson2, prabhakar.mahadev-lad.rj
Hi,
> -----Original Message-----
> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: Thursday, August 4, 2022 1:54 AM
> To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯Ａ
> ＣＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>
> Cc: Chris Paterson <chris.paterson2@renesas.com>; Biju Das
> <biju.das.jz@bp.renesas.com>; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC
>
> This patch series aims to add CANFD, WDT, USB2.0, AUDIO, Serial NOR Flash,
> OSTM and RSPI on SMARC EVK based on RZ/G2LC SoC.
>
> All these patches are cherry-picked from the mainline.
>
> Biju Das (12):
> arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1
> arm64: dts: renesas: rzg2lc-smarc: Use SW_SD0_DEV_SEL macro for
> eMMC/SDHI device selection
> arm64: dts: renesas: rzg2lc-smarc-som: Enable watchdog
> arm64: dts: renesas: r9a07g044c2-smarc: Enable usb2.0
> arm64: dts: renesas: rzg2lc-smarc-pinfunction: Sort the nodes
> arm64: dts: renesas: rzg2l-smarc: Move out i2c3 and Audio codec from
> common dtsi
> arm64: dts: renesas: rzg2lc-smarc: Enable i2c{0,1,2}
> arm64: dts: renesas: rzg2lc-smarc: Enable Audio
> arm64: dts: renesas: rzg2lc-smarc-som: Enable serial NOR flash
> arm64: dts: renesas: rzg2lc-smarc-som: Enable OSTM
> arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier board
> arm64: dts: renesas: rzg2l-smarc: Move gpios property of vccq_sdhi1
> from common dtsi
>
> Geert Uytterhoeven (1):
> arm64: dts: renesas: Align GPIO hog names with dtschema
>
I reviewed this series, LGTM.
I can apply this, if there are no other commands.
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/604399902
Best regards,
Nobuhiro
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC
2022-08-04 5:03 ` [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC nobuhiro1.iwamatsu
@ 2022-08-04 9:16 ` Pavel Machek
2022-08-05 0:56 ` nobuhiro1.iwamatsu
0 siblings, 1 reply; 17+ messages in thread
From: Pavel Machek @ 2022-08-04 9:16 UTC (permalink / raw)
To: nobuhiro1.iwamatsu
Cc: biju.das.jz, cip-dev, pavel, chris.paterson2, prabhakar.mahadev-lad.rj
[-- Attachment #1: Type: text/plain, Size: 415 bytes --]
Hi!
> I reviewed this series, LGTM.
> I can apply this, if there are no other commands.
> https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/604399902
Series looks good to me, too. Go ahead with the application.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC
2022-08-04 9:16 ` Pavel Machek
@ 2022-08-05 0:56 ` nobuhiro1.iwamatsu
0 siblings, 0 replies; 17+ messages in thread
From: nobuhiro1.iwamatsu @ 2022-08-05 0:56 UTC (permalink / raw)
To: pavel; +Cc: biju.das.jz, cip-dev, chris.paterson2, prabhakar.mahadev-lad.rj
Hi Pave,
> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: Thursday, August 4, 2022 6:17 PM
> To: iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>
> Cc: biju.das.jz@bp.renesas.com; cip-dev@lists.cip-project.org;
> pavel@denx.de; chris.paterson2@renesas.com;
> prabhakar.mahadev-lad.rj@bp.renesas.com
> Subject: Re: [PATCH 5.10.y-cip 00/13] Add more support to RZ/G2LC
>
> Hi!
>
> > I reviewed this series, LGTM.
> > I can apply this, if there are no other commands.
> >
> https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/604399902
>
> Series looks good to me, too. Go ahead with the application.
OK, I just pushed.
Best regards,
Nobuhiro
^ permalink raw reply [flat|nested] 17+ messages in thread