From: "Marek Behún" <kabel@kernel.org> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Bjorn Helgaas <helgaas@kernel.org> Cc: "Krzysztof Wilczyński" <kw@linux.com>, pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "Marek Behún" <kabel@kernel.org> Subject: [PATCH 10/11] PCI: aardvark: Explicitly disable Marvell strict ordering Date: Thu, 18 Aug 2022 15:51:39 +0200 [thread overview] Message-ID: <20220818135140.5996-11-kabel@kernel.org> (raw) In-Reply-To: <20220818135140.5996-1-kabel@kernel.org> Instead of implicitly disabling BIT(5) (STRICT_ORDER_ENABLE bit) of the CORE_CTRL2 by writing PCIE_CORE_CTRL2_RESERVED | PCIE_CORE_CTRL2_TD_ENABLE to it, disable it explicitly, with read-modify-write. Signed-off-by: Marek Behún <kabel@kernel.org> --- drivers/pci/controller/pci-aardvark.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index e816ab726f66..73a604f70f06 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -600,8 +600,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); /* Program PCIe Control 2 to disable strict ordering */ - reg = PCIE_CORE_CTRL2_RESERVED | - PCIE_CORE_CTRL2_TD_ENABLE; + reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); + reg &= ~PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE; advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); /* Set lane X1 */ -- 2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: "Marek Behún" <kabel@kernel.org> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Bjorn Helgaas <helgaas@kernel.org> Cc: "Krzysztof Wilczyński" <kw@linux.com>, pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "Marek Behún" <kabel@kernel.org> Subject: [PATCH 10/11] PCI: aardvark: Explicitly disable Marvell strict ordering Date: Thu, 18 Aug 2022 15:51:39 +0200 [thread overview] Message-ID: <20220818135140.5996-11-kabel@kernel.org> (raw) In-Reply-To: <20220818135140.5996-1-kabel@kernel.org> Instead of implicitly disabling BIT(5) (STRICT_ORDER_ENABLE bit) of the CORE_CTRL2 by writing PCIE_CORE_CTRL2_RESERVED | PCIE_CORE_CTRL2_TD_ENABLE to it, disable it explicitly, with read-modify-write. Signed-off-by: Marek Behún <kabel@kernel.org> --- drivers/pci/controller/pci-aardvark.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index e816ab726f66..73a604f70f06 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -600,8 +600,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); /* Program PCIe Control 2 to disable strict ordering */ - reg = PCIE_CORE_CTRL2_RESERVED | - PCIE_CORE_CTRL2_TD_ENABLE; + reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); + reg &= ~PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE; advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); /* Set lane X1 */ -- 2.35.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-08-18 13:52 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-18 13:51 [PATCH 00/11] PCI: aardvark controller changes BATCH 6 Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-08-18 13:51 ` [PATCH 01/11] PCI: pciehp: Enable DLLSC interrupt only if supported Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-08-21 12:46 ` Lukas Wunner 2022-08-22 10:37 ` Marek Behún 2022-08-22 10:37 ` Marek Behún 2022-08-18 13:51 ` [PATCH 02/11] PCI: pciehp: Enable Command Completed Interrupt " Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-08-21 15:20 ` Lukas Wunner 2022-09-28 8:39 ` Lorenzo Pieralisi 2022-09-28 8:39 ` Lorenzo Pieralisi 2022-08-18 13:51 ` [PATCH 03/11] PCI: aardvark: Add support for DLLSC and hotplug interrupt Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-09-09 14:57 ` Lorenzo Pieralisi 2022-09-09 14:57 ` Lorenzo Pieralisi 2022-09-16 16:23 ` Marek Behún 2022-09-16 16:23 ` Marek Behún 2022-09-27 8:29 ` Lorenzo Pieralisi 2022-09-27 8:29 ` Lorenzo Pieralisi 2022-09-27 11:13 ` Pali Rohár 2022-09-27 11:13 ` Pali Rohár 2022-09-27 15:57 ` Lorenzo Pieralisi 2022-09-27 15:57 ` Lorenzo Pieralisi 2022-09-17 9:05 ` Marc Zyngier 2022-09-17 9:05 ` Marc Zyngier 2022-09-26 11:49 ` Lorenzo Pieralisi 2022-09-26 11:49 ` Lorenzo Pieralisi 2022-09-26 12:35 ` Marc Zyngier 2022-09-26 12:35 ` Marc Zyngier 2022-09-26 14:00 ` Lorenzo Pieralisi 2022-09-26 14:00 ` Lorenzo Pieralisi 2022-09-27 13:40 ` Marek Behún 2022-09-27 13:40 ` Marek Behún 2022-08-18 13:51 ` [PATCH 04/11] PCI: aardvark: Send Set_Slot_Power_Limit message Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-08-18 13:51 ` [PATCH 05/11] arm64: dts: armada-3720-turris-mox: Define slot-power-limit-milliwatt for PCIe Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-08-18 13:51 ` [PATCH 06/11] PCI: aardvark: Add clock support Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-08-18 13:51 ` [PATCH 07/11] PCI: aardvark: Add suspend to RAM support Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-09-09 10:33 ` Lorenzo Pieralisi 2022-09-09 10:33 ` Lorenzo Pieralisi 2022-09-27 8:30 ` Lorenzo Pieralisi 2022-09-27 8:30 ` Lorenzo Pieralisi 2022-08-18 13:51 ` [PATCH 08/11] PCI: aardvark: Replace custom PCIE_CORE_ERR_CAPCTL_* macros by linux/pci_regs.h macros Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-08-18 13:51 ` [PATCH 09/11] PCI: aardvark: Don't write read-only bits explicitly in PCI_ERR_CAP register Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-08-18 13:51 ` Marek Behún [this message] 2022-08-18 13:51 ` [PATCH 10/11] PCI: aardvark: Explicitly disable Marvell strict ordering Marek Behún 2022-08-18 13:51 ` [PATCH 11/11] PCI: aardvark: Cleanup some register macros Marek Behún 2022-08-18 13:51 ` Marek Behún
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