From: "Marek Behún" <kabel@kernel.org> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Bjorn Helgaas <helgaas@kernel.org> Cc: "Krzysztof Wilczyński" <kw@linux.com>, pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "Marek Behún" <kabel@kernel.org> Subject: [PATCH 04/11] PCI: aardvark: Send Set_Slot_Power_Limit message Date: Thu, 18 Aug 2022 15:51:33 +0200 [thread overview] Message-ID: <20220818135140.5996-5-kabel@kernel.org> (raw) In-Reply-To: <20220818135140.5996-1-kabel@kernel.org> From: Pali Rohár <pali@kernel.org> Emulate Slot PowerLimit Scale and Value bits in the Slot Capabilities register of the emulated bridge and if slot power limit value is defined, send that Set_Slot_Power_Limit message via Message Generation Control Register in Link Up handler on link up event. Slot power limit value is read from device-tree property 'slot-power-limit-milliwatt'. If this property is not specified, we treat it as "Slot Capabilities register has not yet been initialized". According to PCIe Base specification 3.0, when transitioning from a non-DL_Up Status to a DL_Up Status, the Port must initiate the transmission of a Set_Slot_Power_Limit Message to the other component on the Link to convey the value programmed in the Slot Power Limit Scale and Value fields of the Slot Capabilities register. This transmission is optional if the Slot Capabilities register has not yet been initialized. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> --- drivers/pci/controller/pci-aardvark.c | 51 ++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 31da28ebc5d1..03e318bc171f 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -213,6 +213,11 @@ enum { }; #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) +#define PME_MSG_GEN_CTRL (LMI_BASE_ADDR + 0x220) +#define SEND_SET_SLOT_POWER_LIMIT BIT(13) +#define SEND_PME_TURN_OFF BIT(14) +#define SLOT_POWER_LIMIT_DATA_SHIFT 16 +#define SLOT_POWER_LIMIT_DATA_MASK GENMASK(25, 16) /* PCIe core controller registers */ #define CTRL_CORE_BASE_ADDR 0x18000 @@ -285,6 +290,8 @@ struct advk_pcie { raw_spinlock_t msi_irq_lock; DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); struct mutex msi_used_lock; + u8 slot_power_limit_value; + u8 slot_power_limit_scale; int link_gen; bool link_was_up; struct timer_list link_irq_timer; @@ -317,8 +324,9 @@ static inline bool advk_pcie_link_up(struct advk_pcie *pcie) { /* check if LTSSM is in normal operation - some L* state */ u8 ltssm_state = advk_pcie_ltssm_state(pcie); + u16 slotsta, slotctl; + u32 slotpwr, val; bool link_is_up; - u16 slotsta; link_is_up = ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; @@ -332,6 +340,27 @@ static inline bool advk_pcie_link_up(struct advk_pcie *pcie) pcie->bridge.pcie_conf.slotsta = cpu_to_le16(slotsta); mod_timer(&pcie->link_irq_timer, jiffies + 1); + + /* + * According to PCIe Base specification 3.0, when transitioning + * from a non-DL_Up Status to a DL_Up Status, the Port must + * initiate the transmission of a Set_Slot_Power_Limit Message + * to the other component on the Link to convey the value + * programmed in the Slot Power Limit Scale and Value fields of + * the Slot Capabilities register. This transmission is optional + * if the Slot Capabilities register has not yet been + * initialized. + */ + slotctl = le16_to_cpu(pcie->bridge.pcie_conf.slotctl); + slotpwr = FIELD_GET(PCI_EXP_SLTCAP_SPLV | PCI_EXP_SLTCAP_SPLS, + le32_to_cpu(pcie->bridge.pcie_conf.slotcap)); + if (!(slotctl & PCI_EXP_SLTCTL_ASPL_DISABLE) && slotpwr) { + val = advk_readl(pcie, PME_MSG_GEN_CTRL); + val &= ~SLOT_POWER_LIMIT_DATA_MASK; + val |= slotpwr << SLOT_POWER_LIMIT_DATA_SHIFT; + val |= SEND_SET_SLOT_POWER_LIMIT; + advk_writel(pcie, val, PME_MSG_GEN_CTRL); + } } return link_is_up; @@ -944,8 +973,9 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, case PCI_EXP_SLTCTL: { u16 slotctl = le16_to_cpu(bridge->pcie_conf.slotctl); - /* Only emulation of HPIE and DLLSCE bits is provided */ - slotctl &= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; + /* Only emulation of HPIE, DLLSCE and ASPLD bits is provided */ + slotctl &= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE | + PCI_EXP_SLTCTL_ASPL_DISABLE; bridge->pcie_conf.slotctl = cpu_to_le16(slotctl); break; } @@ -1109,9 +1139,13 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) * Set physical slot number to 1 since there is only one port and zero * value is reserved for ports within the same silicon as Root Port * which is not our case. + * + * Set slot power limit. */ slotcap = PCI_EXP_SLTCAP_NCCS | PCI_EXP_SLTCAP_HPC | - FIELD_PREP(PCI_EXP_SLTCAP_PSN, 1); + FIELD_PREP(PCI_EXP_SLTCAP_PSN, 1) | + FIELD_PREP(PCI_EXP_SLTCAP_SPLV, pcie->slot_power_limit_value) | + FIELD_PREP(PCI_EXP_SLTCAP_SPLS, pcie->slot_power_limit_scale); bridge->pcie_conf.slotcap = cpu_to_le32(slotcap); bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); @@ -1837,6 +1871,7 @@ static int advk_pcie_probe(struct platform_device *pdev) struct advk_pcie *pcie; struct pci_host_bridge *bridge; struct resource_entry *entry; + u32 slot_power_limit; int ret, irq; bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); @@ -1957,6 +1992,14 @@ static int advk_pcie_probe(struct platform_device *pdev) else pcie->link_gen = ret; + slot_power_limit = of_pci_get_slot_power_limit(dev->of_node, + &pcie->slot_power_limit_value, + &pcie->slot_power_limit_scale); + if (slot_power_limit) + dev_info(dev, "Slot Power Limit: %u.%uW\n", + slot_power_limit / 1000, + (slot_power_limit / 100) % 10); + ret = advk_pcie_setup_phy(pcie); if (ret) return ret; -- 2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: "Marek Behún" <kabel@kernel.org> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Bjorn Helgaas <helgaas@kernel.org> Cc: "Krzysztof Wilczyński" <kw@linux.com>, pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "Marek Behún" <kabel@kernel.org> Subject: [PATCH 04/11] PCI: aardvark: Send Set_Slot_Power_Limit message Date: Thu, 18 Aug 2022 15:51:33 +0200 [thread overview] Message-ID: <20220818135140.5996-5-kabel@kernel.org> (raw) In-Reply-To: <20220818135140.5996-1-kabel@kernel.org> From: Pali Rohár <pali@kernel.org> Emulate Slot PowerLimit Scale and Value bits in the Slot Capabilities register of the emulated bridge and if slot power limit value is defined, send that Set_Slot_Power_Limit message via Message Generation Control Register in Link Up handler on link up event. Slot power limit value is read from device-tree property 'slot-power-limit-milliwatt'. If this property is not specified, we treat it as "Slot Capabilities register has not yet been initialized". According to PCIe Base specification 3.0, when transitioning from a non-DL_Up Status to a DL_Up Status, the Port must initiate the transmission of a Set_Slot_Power_Limit Message to the other component on the Link to convey the value programmed in the Slot Power Limit Scale and Value fields of the Slot Capabilities register. This transmission is optional if the Slot Capabilities register has not yet been initialized. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> --- drivers/pci/controller/pci-aardvark.c | 51 ++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 31da28ebc5d1..03e318bc171f 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -213,6 +213,11 @@ enum { }; #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) +#define PME_MSG_GEN_CTRL (LMI_BASE_ADDR + 0x220) +#define SEND_SET_SLOT_POWER_LIMIT BIT(13) +#define SEND_PME_TURN_OFF BIT(14) +#define SLOT_POWER_LIMIT_DATA_SHIFT 16 +#define SLOT_POWER_LIMIT_DATA_MASK GENMASK(25, 16) /* PCIe core controller registers */ #define CTRL_CORE_BASE_ADDR 0x18000 @@ -285,6 +290,8 @@ struct advk_pcie { raw_spinlock_t msi_irq_lock; DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); struct mutex msi_used_lock; + u8 slot_power_limit_value; + u8 slot_power_limit_scale; int link_gen; bool link_was_up; struct timer_list link_irq_timer; @@ -317,8 +324,9 @@ static inline bool advk_pcie_link_up(struct advk_pcie *pcie) { /* check if LTSSM is in normal operation - some L* state */ u8 ltssm_state = advk_pcie_ltssm_state(pcie); + u16 slotsta, slotctl; + u32 slotpwr, val; bool link_is_up; - u16 slotsta; link_is_up = ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; @@ -332,6 +340,27 @@ static inline bool advk_pcie_link_up(struct advk_pcie *pcie) pcie->bridge.pcie_conf.slotsta = cpu_to_le16(slotsta); mod_timer(&pcie->link_irq_timer, jiffies + 1); + + /* + * According to PCIe Base specification 3.0, when transitioning + * from a non-DL_Up Status to a DL_Up Status, the Port must + * initiate the transmission of a Set_Slot_Power_Limit Message + * to the other component on the Link to convey the value + * programmed in the Slot Power Limit Scale and Value fields of + * the Slot Capabilities register. This transmission is optional + * if the Slot Capabilities register has not yet been + * initialized. + */ + slotctl = le16_to_cpu(pcie->bridge.pcie_conf.slotctl); + slotpwr = FIELD_GET(PCI_EXP_SLTCAP_SPLV | PCI_EXP_SLTCAP_SPLS, + le32_to_cpu(pcie->bridge.pcie_conf.slotcap)); + if (!(slotctl & PCI_EXP_SLTCTL_ASPL_DISABLE) && slotpwr) { + val = advk_readl(pcie, PME_MSG_GEN_CTRL); + val &= ~SLOT_POWER_LIMIT_DATA_MASK; + val |= slotpwr << SLOT_POWER_LIMIT_DATA_SHIFT; + val |= SEND_SET_SLOT_POWER_LIMIT; + advk_writel(pcie, val, PME_MSG_GEN_CTRL); + } } return link_is_up; @@ -944,8 +973,9 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, case PCI_EXP_SLTCTL: { u16 slotctl = le16_to_cpu(bridge->pcie_conf.slotctl); - /* Only emulation of HPIE and DLLSCE bits is provided */ - slotctl &= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; + /* Only emulation of HPIE, DLLSCE and ASPLD bits is provided */ + slotctl &= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE | + PCI_EXP_SLTCTL_ASPL_DISABLE; bridge->pcie_conf.slotctl = cpu_to_le16(slotctl); break; } @@ -1109,9 +1139,13 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) * Set physical slot number to 1 since there is only one port and zero * value is reserved for ports within the same silicon as Root Port * which is not our case. + * + * Set slot power limit. */ slotcap = PCI_EXP_SLTCAP_NCCS | PCI_EXP_SLTCAP_HPC | - FIELD_PREP(PCI_EXP_SLTCAP_PSN, 1); + FIELD_PREP(PCI_EXP_SLTCAP_PSN, 1) | + FIELD_PREP(PCI_EXP_SLTCAP_SPLV, pcie->slot_power_limit_value) | + FIELD_PREP(PCI_EXP_SLTCAP_SPLS, pcie->slot_power_limit_scale); bridge->pcie_conf.slotcap = cpu_to_le32(slotcap); bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); @@ -1837,6 +1871,7 @@ static int advk_pcie_probe(struct platform_device *pdev) struct advk_pcie *pcie; struct pci_host_bridge *bridge; struct resource_entry *entry; + u32 slot_power_limit; int ret, irq; bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); @@ -1957,6 +1992,14 @@ static int advk_pcie_probe(struct platform_device *pdev) else pcie->link_gen = ret; + slot_power_limit = of_pci_get_slot_power_limit(dev->of_node, + &pcie->slot_power_limit_value, + &pcie->slot_power_limit_scale); + if (slot_power_limit) + dev_info(dev, "Slot Power Limit: %u.%uW\n", + slot_power_limit / 1000, + (slot_power_limit / 100) % 10); + ret = advk_pcie_setup_phy(pcie); if (ret) return ret; -- 2.35.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-08-18 13:51 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-18 13:51 [PATCH 00/11] PCI: aardvark controller changes BATCH 6 Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-08-18 13:51 ` [PATCH 01/11] PCI: pciehp: Enable DLLSC interrupt only if supported Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-08-21 12:46 ` Lukas Wunner 2022-08-22 10:37 ` Marek Behún 2022-08-22 10:37 ` Marek Behún 2022-08-18 13:51 ` [PATCH 02/11] PCI: pciehp: Enable Command Completed Interrupt " Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-08-21 15:20 ` Lukas Wunner 2022-09-28 8:39 ` Lorenzo Pieralisi 2022-09-28 8:39 ` Lorenzo Pieralisi 2022-08-18 13:51 ` [PATCH 03/11] PCI: aardvark: Add support for DLLSC and hotplug interrupt Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-09-09 14:57 ` Lorenzo Pieralisi 2022-09-09 14:57 ` Lorenzo Pieralisi 2022-09-16 16:23 ` Marek Behún 2022-09-16 16:23 ` Marek Behún 2022-09-27 8:29 ` Lorenzo Pieralisi 2022-09-27 8:29 ` Lorenzo Pieralisi 2022-09-27 11:13 ` Pali Rohár 2022-09-27 11:13 ` Pali Rohár 2022-09-27 15:57 ` Lorenzo Pieralisi 2022-09-27 15:57 ` Lorenzo Pieralisi 2022-09-17 9:05 ` Marc Zyngier 2022-09-17 9:05 ` Marc Zyngier 2022-09-26 11:49 ` Lorenzo Pieralisi 2022-09-26 11:49 ` Lorenzo Pieralisi 2022-09-26 12:35 ` Marc Zyngier 2022-09-26 12:35 ` Marc Zyngier 2022-09-26 14:00 ` Lorenzo Pieralisi 2022-09-26 14:00 ` Lorenzo Pieralisi 2022-09-27 13:40 ` Marek Behún 2022-09-27 13:40 ` Marek Behún 2022-08-18 13:51 ` Marek Behún [this message] 2022-08-18 13:51 ` [PATCH 04/11] PCI: aardvark: Send Set_Slot_Power_Limit message Marek Behún 2022-08-18 13:51 ` [PATCH 05/11] arm64: dts: armada-3720-turris-mox: Define slot-power-limit-milliwatt for PCIe Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-08-18 13:51 ` [PATCH 06/11] PCI: aardvark: Add clock support Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-08-18 13:51 ` [PATCH 07/11] PCI: aardvark: Add suspend to RAM support Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-09-09 10:33 ` Lorenzo Pieralisi 2022-09-09 10:33 ` Lorenzo Pieralisi 2022-09-27 8:30 ` Lorenzo Pieralisi 2022-09-27 8:30 ` Lorenzo Pieralisi 2022-08-18 13:51 ` [PATCH 08/11] PCI: aardvark: Replace custom PCIE_CORE_ERR_CAPCTL_* macros by linux/pci_regs.h macros Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-08-18 13:51 ` [PATCH 09/11] PCI: aardvark: Don't write read-only bits explicitly in PCI_ERR_CAP register Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-08-18 13:51 ` [PATCH 10/11] PCI: aardvark: Explicitly disable Marvell strict ordering Marek Behún 2022-08-18 13:51 ` Marek Behún 2022-08-18 13:51 ` [PATCH 11/11] PCI: aardvark: Cleanup some register macros Marek Behún 2022-08-18 13:51 ` Marek Behún
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20220818135140.5996-5-kabel@kernel.org \ --to=kabel@kernel.org \ --cc=helgaas@kernel.org \ --cc=kw@linux.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-pci@vger.kernel.org \ --cc=lorenzo.pieralisi@arm.com \ --cc=pali@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.