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From: Christoph Muellner <christoph.muellner@vrull.eu>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
	"Heiko Stübner" <heiko.stuebner@vrull.eu>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Nelson Chu" <nelson@rivosinc.com>,
	"Kito Cheng" <kito.cheng@sifive.com>,
	"Cooper Qu" <cooper.qu@linux.alibaba.com>,
	"Lifang Xia" <lifang_xia@linux.alibaba.com>,
	"Yunhai Shang" <yunhai@linux.alibaba.com>,
	"Zhiwei Liu" <zhiwei_liu@linux.alibaba.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH 01/11] riscv: Add privilege level to DisasContext
Date: Tue,  6 Sep 2022 14:22:33 +0200	[thread overview]
Message-ID: <20220906122243.1243354-2-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20220906122243.1243354-1-christoph.muellner@vrull.eu>

From: Christoph Müllner <christoph.muellner@vrull.eu>

This allows privileged instructions to check the required
privilege level in the translation without calling a helper.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 target/riscv/translate.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 63b04e8a94..fd241ff667 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -59,6 +59,9 @@ typedef struct DisasContext {
     /* pc_succ_insn points to the instruction following base.pc_next */
     target_ulong pc_succ_insn;
     target_ulong priv_ver;
+#ifndef CONFIG_USER_ONLY
+    target_ulong priv;
+#endif
     RISCVMXL misa_mxl_max;
     RISCVMXL xl;
     uint32_t misa_ext;
@@ -1079,6 +1082,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
     ctx->priv_ver = env->priv_ver;
 #if !defined(CONFIG_USER_ONLY)
+    ctx->priv = env->priv;
     if (riscv_has_ext(env, RVH)) {
         ctx->virt_enabled = riscv_cpu_virt_enabled(env);
     } else {
-- 
2.37.2



  reply	other threads:[~2022-09-06 13:15 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-06 12:22 [PATCH 00/11] Add support for the T-Head vendor extensions Christoph Muellner
2022-09-06 12:22 ` Christoph Muellner [this message]
2022-09-16  2:46   ` [PATCH 01/11] riscv: Add privilege level to DisasContext LIU Zhiwei
2022-09-16  6:00   ` Richard Henderson
2022-09-16  6:05     ` Richard Henderson
2022-09-16  6:21     ` LIU Zhiwei
2022-09-06 12:22 ` [PATCH 02/11] RISC-V: Adding T-Head CMO instructions Christoph Muellner
2022-09-16  2:47   ` LIU Zhiwei
2022-09-16  6:43   ` LIU Zhiwei
2022-09-16  7:59     ` Richard Henderson
2022-09-06 12:22 ` [PATCH 03/11] RISC-V: Adding T-Head SYNC instructions Christoph Muellner
2022-09-08  7:29   ` Richard Henderson
2022-09-09 17:21     ` Christoph Müllner
2022-12-12  9:12     ` LIU Zhiwei
2022-12-12  9:21     ` LIU Zhiwei
2022-09-06 12:22 ` [PATCH 04/11] RISC-V: Adding T-Head Bitmanip instructions Christoph Muellner
2022-09-16  9:12   ` LIU Zhiwei
2022-09-06 12:22 ` [PATCH 05/11] RISC-V: Adding T-Head CondMov instructions Christoph Muellner
2022-09-06 12:22 ` [PATCH 06/11] RISC-V: Adding T-Head multiply-accumulate instructions Christoph Muellner
2022-09-06 12:22 ` [PATCH 07/11] RISC-V: Adding T-Head XMAE support Christoph Muellner
2022-09-06 12:22 ` [PATCH 08/11] RISC-V: Adding T-Head MemPair extension Christoph Muellner
2022-09-06 12:22 ` [PATCH 09/11] RISC-V: Adding T-Head MemIdx extension Christoph Muellner
2022-09-06 12:22 ` [PATCH 10/11] RISC-V: Adding T-Head FMemIdx extension Christoph Muellner
2022-09-08  7:45   ` Richard Henderson
2022-09-09 17:21     ` Christoph Müllner
2022-09-06 12:22 ` [PATCH 11/11] RISC-V: Add initial support for T-Head C906 and C910 CPUs Christoph Muellner
2022-09-08  7:46   ` Richard Henderson
2022-09-08  8:23     ` Christoph Müllner
2022-09-08  8:56       ` Richard Henderson
2022-09-08  9:01         ` Christoph Müllner

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