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From: Richard Henderson <richard.henderson@linaro.org>
To: "Christoph Muellner" <christoph.muellner@vrull.eu>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
	"Heiko Stübner" <heiko.stuebner@vrull.eu>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Nelson Chu" <nelson@rivosinc.com>,
	"Kito Cheng" <kito.cheng@sifive.com>,
	"Cooper Qu" <cooper.qu@linux.alibaba.com>,
	"Lifang Xia" <lifang_xia@linux.alibaba.com>,
	"Yunhai Shang" <yunhai@linux.alibaba.com>,
	"Zhiwei Liu" <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH 01/11] riscv: Add privilege level to DisasContext
Date: Fri, 16 Sep 2022 08:05:34 +0200	[thread overview]
Message-ID: <8e1643a0-1748-df10-4493-47323d425e32@linaro.org> (raw)
In-Reply-To: <bfff6a65-f0f7-8659-2b58-582345018868@linaro.org>

On 9/16/22 08:00, Richard Henderson wrote:
> Or, keep the field, because it's usage will be more self-documentary, but copy the value 
> from ctx->mmu_idx and add a comment.

Or, add an inline function like

static inline int priv_level(DisasContext *ctx)
{
#ifdef CONFIG_USER_ONLY
     return PRV_U;
#else
     /* Priv level equals mmu index -- see cpu_mmu_index. */
     return ctx->mmu_idx;
#endif
}

so that usages within a user-only build are compile-time constant and folded away.


r~


  reply	other threads:[~2022-09-16  6:07 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-06 12:22 [PATCH 00/11] Add support for the T-Head vendor extensions Christoph Muellner
2022-09-06 12:22 ` [PATCH 01/11] riscv: Add privilege level to DisasContext Christoph Muellner
2022-09-16  2:46   ` LIU Zhiwei
2022-09-16  6:00   ` Richard Henderson
2022-09-16  6:05     ` Richard Henderson [this message]
2022-09-16  6:21     ` LIU Zhiwei
2022-09-06 12:22 ` [PATCH 02/11] RISC-V: Adding T-Head CMO instructions Christoph Muellner
2022-09-16  2:47   ` LIU Zhiwei
2022-09-16  6:43   ` LIU Zhiwei
2022-09-16  7:59     ` Richard Henderson
2022-09-06 12:22 ` [PATCH 03/11] RISC-V: Adding T-Head SYNC instructions Christoph Muellner
2022-09-08  7:29   ` Richard Henderson
2022-09-09 17:21     ` Christoph Müllner
2022-12-12  9:12     ` LIU Zhiwei
2022-12-12  9:21     ` LIU Zhiwei
2022-09-06 12:22 ` [PATCH 04/11] RISC-V: Adding T-Head Bitmanip instructions Christoph Muellner
2022-09-16  9:12   ` LIU Zhiwei
2022-09-06 12:22 ` [PATCH 05/11] RISC-V: Adding T-Head CondMov instructions Christoph Muellner
2022-09-06 12:22 ` [PATCH 06/11] RISC-V: Adding T-Head multiply-accumulate instructions Christoph Muellner
2022-09-06 12:22 ` [PATCH 07/11] RISC-V: Adding T-Head XMAE support Christoph Muellner
2022-09-06 12:22 ` [PATCH 08/11] RISC-V: Adding T-Head MemPair extension Christoph Muellner
2022-09-06 12:22 ` [PATCH 09/11] RISC-V: Adding T-Head MemIdx extension Christoph Muellner
2022-09-06 12:22 ` [PATCH 10/11] RISC-V: Adding T-Head FMemIdx extension Christoph Muellner
2022-09-08  7:45   ` Richard Henderson
2022-09-09 17:21     ` Christoph Müllner
2022-09-06 12:22 ` [PATCH 11/11] RISC-V: Add initial support for T-Head C906 and C910 CPUs Christoph Muellner
2022-09-08  7:46   ` Richard Henderson
2022-09-08  8:23     ` Christoph Müllner
2022-09-08  8:56       ` Richard Henderson
2022-09-08  9:01         ` Christoph Müllner

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