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From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: "Richard Henderson" <richard.henderson@linaro.org>,
	"Christoph Muellner" <christoph.muellner@vrull.eu>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
	"Heiko Stübner" <heiko.stuebner@vrull.eu>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Nelson Chu" <nelson@rivosinc.com>,
	"Kito Cheng" <kito.cheng@sifive.com>,
	"Cooper Qu" <cooper.qu@linux.alibaba.com>,
	"Lifang Xia" <lifang_xia@linux.alibaba.com>,
	"Yunhai Shang" <yunhai@linux.alibaba.com>
Subject: Re: [PATCH 03/11] RISC-V: Adding T-Head SYNC instructions
Date: Mon, 12 Dec 2022 17:21:42 +0800	[thread overview]
Message-ID: <34201e65-efc5-d08d-4e3c-52c91cedcdde@linux.alibaba.com> (raw)
In-Reply-To: <f6c98fb6-38f7-5747-0db6-aec2c77edd9a@linaro.org>


On 2022/9/8 15:29, Richard Henderson wrote:
> On 9/6/22 13:22, Christoph Muellner wrote:
>> +NOP_PRIVCHECK(th_sfence_vmas, REQUIRE_PRIV_MHS)
>> +NOP_PRIVCHECK(th_sync, REQUIRE_PRIV_MHSU)
>> +NOP_PRIVCHECK(th_sync_i, REQUIRE_PRIV_MHSU)
>> +NOP_PRIVCHECK(th_sync_is, REQUIRE_PRIV_MHSU)
>> +NOP_PRIVCHECK(th_sync_s, REQUIRE_PRIV_MHSU)
>
> These should not be nops: th_sfence_vmas requires a tlb flush; 
> th.sync{,.i} needs to end the current translation block; 
> th.sync.{s,is} needs multiprocessor sync, which involves a call to 
> async_safe_run_on_cpu.
Hi Richard,

I have fixed the description of T-Head custom synchronization 
instructions according to the implementation of hardware. Sorry for the 
misleading.

https://github.com/T-head-Semi/thead-extension-spec/tree/master/xtheadsync


The fix is as below:

1)th.sync.s has the same function with th.sync.

2) th.sync.is has the same function with th.sync.i

3) th.sync has the function of memory barrier, but it is stricter than 
RISC-V fence instruction as it order all the instructions instead of 
load/store instructions.

4) th.sync.i has the function to flush the pipeline besides the function 
of th.sync.


On QEMU,  I think they should be emulated them as below:

1) th.sync should be emulated as " 'tcg_gen_mb()'  and  'end the current 
translation block'" on QEMU.

2) th.sync.i should be emulated as " 'tcg_gen_mb()'  and  'end the 
current translation block'" on QEMU because we don't have the cache 
model for guest on QEMU. Thus we don't have to synchronize between the 
icache and dcache for guest.


'tcg_gen_mb' is for the function of memory barrier. And  'end the 
current translation block' is to reflect the influence of other 
instructions, such as taking interrupts which happens only at the end of 
a translation block.
Maybe we can also just implement these instructions as 'tcg_gen_mb' 
because currently all CSR instructions which may influence the 
interrupts taking have ended the TB on QEMU.


Is it right?

Thanks,
Zhiwei
>
>
> r~


  parent reply	other threads:[~2022-12-12  9:26 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-06 12:22 [PATCH 00/11] Add support for the T-Head vendor extensions Christoph Muellner
2022-09-06 12:22 ` [PATCH 01/11] riscv: Add privilege level to DisasContext Christoph Muellner
2022-09-16  2:46   ` LIU Zhiwei
2022-09-16  6:00   ` Richard Henderson
2022-09-16  6:05     ` Richard Henderson
2022-09-16  6:21     ` LIU Zhiwei
2022-09-06 12:22 ` [PATCH 02/11] RISC-V: Adding T-Head CMO instructions Christoph Muellner
2022-09-16  2:47   ` LIU Zhiwei
2022-09-16  6:43   ` LIU Zhiwei
2022-09-16  7:59     ` Richard Henderson
2022-09-06 12:22 ` [PATCH 03/11] RISC-V: Adding T-Head SYNC instructions Christoph Muellner
2022-09-08  7:29   ` Richard Henderson
2022-09-09 17:21     ` Christoph Müllner
2022-12-12  9:12     ` LIU Zhiwei
2022-12-12  9:21     ` LIU Zhiwei [this message]
2022-09-06 12:22 ` [PATCH 04/11] RISC-V: Adding T-Head Bitmanip instructions Christoph Muellner
2022-09-16  9:12   ` LIU Zhiwei
2022-09-06 12:22 ` [PATCH 05/11] RISC-V: Adding T-Head CondMov instructions Christoph Muellner
2022-09-06 12:22 ` [PATCH 06/11] RISC-V: Adding T-Head multiply-accumulate instructions Christoph Muellner
2022-09-06 12:22 ` [PATCH 07/11] RISC-V: Adding T-Head XMAE support Christoph Muellner
2022-09-06 12:22 ` [PATCH 08/11] RISC-V: Adding T-Head MemPair extension Christoph Muellner
2022-09-06 12:22 ` [PATCH 09/11] RISC-V: Adding T-Head MemIdx extension Christoph Muellner
2022-09-06 12:22 ` [PATCH 10/11] RISC-V: Adding T-Head FMemIdx extension Christoph Muellner
2022-09-08  7:45   ` Richard Henderson
2022-09-09 17:21     ` Christoph Müllner
2022-09-06 12:22 ` [PATCH 11/11] RISC-V: Add initial support for T-Head C906 and C910 CPUs Christoph Muellner
2022-09-08  7:46   ` Richard Henderson
2022-09-08  8:23     ` Christoph Müllner
2022-09-08  8:56       ` Richard Henderson
2022-09-08  9:01         ` Christoph Müllner

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