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From: Pavle Kotarac <pavle.kotarac@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com, Duncan Ma <duncan.ma@amd.com>,
	solomon.chiu@amd.com, Aurabindo.Pillai@amd.com,
	wayne.lin@amd.com, Jun Lei <Jun.Lei@amd.com>,
	Bhawanpreet.Lakha@amd.com,
	Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>,
	agustin.gutierrez@amd.com, Pavle Kotarac <Pavle.Kotarac@amd.com>
Subject: [PATCH 10/21] drm/amd/display: Correct dram channel width for dcn314
Date: Wed, 7 Sep 2022 14:11:49 -0400	[thread overview]
Message-ID: <20220907181200.54726-10-pavle.kotarac@amd.com> (raw)
In-Reply-To: <20220907181200.54726-1-pavle.kotarac@amd.com>

From: Duncan Ma <duncan.ma@amd.com>

[Why]
The interpretation of the number of memory channels
differ by memory type, and this affects channel width
for the DML input.

[How]
Set dram channel width according to memory type for
dcn314.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c | 2 ++
 drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c         | 3 +++
 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h                | 1 +
 3 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
index 171c38fac6a3..cd86aa912e3c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
@@ -677,6 +677,8 @@ static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *cl
 	}
 	ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
 	bw_params->vram_type = bios_info->memory_type;
+
+	bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
 	bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
 
 	for (i = 0; i < WM_SET_COUNT; i++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
index fc5529fa51b3..4bb3b31ea7e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
@@ -194,6 +194,9 @@ void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p
 		dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
 		dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count;
 
+		if (bw_params->dram_channel_width_bytes > 0)
+			dcn3_14_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes;
+
 		if (bw_params->num_channels > 0)
 			dcn3_14_soc.num_chans = bw_params->num_channels;
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 5d2b028e5dad..d9f1b0a4fbd4 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -214,6 +214,7 @@ struct dummy_pstate_entry {
 struct clk_bw_params {
 	unsigned int vram_type;
 	unsigned int num_channels;
+	unsigned int dram_channel_width_bytes;
  	unsigned int dispclk_vco_khz;
 	unsigned int dc_mode_softmax_memclk;
 	struct clk_limit_table clk_table;
-- 
2.34.1


  parent reply	other threads:[~2022-09-07 18:12 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-07 18:11 [PATCH 01/21] drm/amd/display: Reverted DSC programming sequence change Pavle Kotarac
2022-09-07 18:11 ` [PATCH 02/21] drm/amd/display: Assign link type before check dsc workaround Pavle Kotarac
2022-09-07 18:11 ` [PATCH 03/21] drm/amd/display: SW cursor fallback for SubVP Pavle Kotarac
2022-09-07 18:11 ` [PATCH 04/21] drm/amd/display: Fixing DIG FIFO Error Pavle Kotarac
2022-09-07 18:11 ` [PATCH 05/21] drm/amd/display: Fix divide by zero in DML Pavle Kotarac
2022-09-07 18:11 ` [PATCH 06/21] drm/amd/display: Fix compilation errors on DCN314 Pavle Kotarac
2022-09-07 18:11 ` [PATCH 07/21] drm/amd/display: Enable dlg and vba compilation for dcn314 Pavle Kotarac
2022-09-07 21:08   ` Li, Roman
2022-09-07 18:11 ` [PATCH 08/21] drm/amd/display: Hook up DCN314 specific dml implementation Pavle Kotarac
2022-09-07 18:11 ` [PATCH 09/21] drm/amd/display: Relax swizzle checks for video non-RGB formats on DCN314 Pavle Kotarac
2022-09-07 18:11 ` Pavle Kotarac [this message]
2022-09-07 18:11 ` [PATCH 11/21] drm/amd/display: Round cursor width up for MALL allocation Pavle Kotarac
2022-09-08  9:17   ` Christian König
2022-09-07 18:11 ` [PATCH 12/21] drm/amd/display: Update viewport position for phantom pipes Pavle Kotarac
2022-09-07 18:11 ` [PATCH 13/21] drm/amd/display: Added debug option for forcing subvp num ways Pavle Kotarac
2022-09-07 18:11 ` [PATCH 14/21] drm/amd/display: add workaround for subvp cursor corruption for DCN32/321 Pavle Kotarac
2022-09-07 18:11 ` [PATCH 15/21] drm/amd/display: Limit user regamma to a valid value Pavle Kotarac
2022-09-07 18:11 ` [PATCH 16/21] drm/amd/display: Adding log for spread_spectrum_info Pavle Kotarac
2022-09-07 18:11 ` [PATCH 17/21] drm/amd/display: Don't adjust VRR unnecessarily Pavle Kotarac
2022-09-07 18:11 ` [PATCH 18/21] drm/amd/display: Avoid force minimal transaction in case of surface_count equal to 0 Pavle Kotarac
2022-09-07 18:11 ` [PATCH 19/21] drm/amd/display: Refactor SubVP calculation to remove FPU Pavle Kotarac
2022-09-07 18:11 ` [PATCH 20/21] drm/amd/display: Fix register definitions for DCN32/321 Pavle Kotarac
2022-09-07 18:12 ` [PATCH 21/21] drm/amd/display: 3.2.202 Pavle Kotarac

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