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From: Pavle Kotarac <pavle.kotarac@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Aric Cyr <aric.cyr@amd.com>,
	Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com,
	Alvin Lee <Alvin.Lee2@amd.com>,
	wayne.lin@amd.com, Jun Lei <Jun.Lei@amd.com>,
	Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com,
	Pavle Kotarac <Pavle.Kotarac@amd.com>
Subject: [PATCH 05/21] drm/amd/display: Fix divide by zero in DML
Date: Wed, 7 Sep 2022 14:11:44 -0400	[thread overview]
Message-ID: <20220907181200.54726-5-pavle.kotarac@amd.com> (raw)
In-Reply-To: <20220907181200.54726-1-pavle.kotarac@amd.com>

From: Aric Cyr <aric.cyr@amd.com>

[why]
Incorrectly using MicroTileWidth instead of MacroTileWidth for
calculations.

[how]
Remove all unused references to MicroTile and change them to MacroTile.

Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
 .../dc/dml/dcn32/display_mode_vba_32.c        | 24 +++++++++----------
 .../drm/amd/display/dc/dml/display_mode_vba.h | 10 ++++----
 2 files changed, 16 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index d8014bfbc3fe..cd6bf67035d4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -1806,10 +1806,10 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 				&mode_lib->vba.Read256BlockHeightC[k],
 				&mode_lib->vba.Read256BlockWidthY[k],
 				&mode_lib->vba.Read256BlockWidthC[k],
-				&mode_lib->vba.MicroTileHeightY[k],
-				&mode_lib->vba.MicroTileHeightC[k],
-				&mode_lib->vba.MicroTileWidthY[k],
-				&mode_lib->vba.MicroTileWidthC[k]);
+				&mode_lib->vba.MacroTileHeightY[k],
+				&mode_lib->vba.MacroTileHeightC[k],
+				&mode_lib->vba.MacroTileWidthY[k],
+				&mode_lib->vba.MacroTileWidthC[k]);
 	}
 
 	/*Bandwidth Support Check*/
@@ -2661,10 +2661,10 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 			mode_lib->vba.Read256BlockWidthC,
 			mode_lib->vba.Read256BlockHeightY,
 			mode_lib->vba.Read256BlockHeightC,
-			mode_lib->vba.MicroTileWidthY,
-			mode_lib->vba.MicroTileWidthC,
-			mode_lib->vba.MicroTileHeightY,
-			mode_lib->vba.MicroTileHeightC,
+			mode_lib->vba.MacroTileWidthY,
+			mode_lib->vba.MacroTileWidthC,
+			mode_lib->vba.MacroTileHeightY,
+			mode_lib->vba.MacroTileHeightC,
 
 			/* Output */
 			mode_lib->vba.SurfaceSizeInMALL,
@@ -2711,10 +2711,10 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesY = mode_lib->vba.Read256BlockHeightY[k];
 				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidth256BytesC = mode_lib->vba.Read256BlockWidthC[k];
 				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesC = mode_lib->vba.Read256BlockHeightC[k];
-				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthY = mode_lib->vba.MicroTileWidthY[k];
-				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightY = mode_lib->vba.MicroTileHeightY[k];
-				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthC = mode_lib->vba.MicroTileWidthC[k];
-				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightC = mode_lib->vba.MicroTileHeightC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthY = mode_lib->vba.MacroTileWidthY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightY = mode_lib->vba.MacroTileHeightY[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthC = mode_lib->vba.MacroTileWidthC[k];
+				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightC = mode_lib->vba.MacroTileHeightC[k];
 				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k];
 				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].HTotal = mode_lib->vba.HTotal[k];
 				v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k];
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index da8acf59ccac..630f3395e90a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -652,10 +652,10 @@ struct vba_vars_st {
 
 	unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 	double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
-	unsigned int MicroTileHeightY[DC__NUM_DPP__MAX];
-	unsigned int MicroTileHeightC[DC__NUM_DPP__MAX];
-	unsigned int MicroTileWidthY[DC__NUM_DPP__MAX];
-	unsigned int MicroTileWidthC[DC__NUM_DPP__MAX];
+	unsigned int MacroTileHeightY[DC__NUM_DPP__MAX];
+	unsigned int MacroTileHeightC[DC__NUM_DPP__MAX];
+	unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
+	unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
 	bool ImmediateFlipRequiredFinal;
 	bool DCCProgrammingAssumesScanDirectionUnknownFinal;
 	bool EnoughWritebackUnits;
@@ -801,8 +801,6 @@ struct vba_vars_st {
 	double PSCL_FACTOR[DC__NUM_DPP__MAX];
 	double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
 	double MaximumVStartup[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
-	unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
-	unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
 	double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
 	double AlignedYPitch[DC__NUM_DPP__MAX];
 	double AlignedCPitch[DC__NUM_DPP__MAX];
-- 
2.34.1


  parent reply	other threads:[~2022-09-07 18:12 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-07 18:11 [PATCH 01/21] drm/amd/display: Reverted DSC programming sequence change Pavle Kotarac
2022-09-07 18:11 ` [PATCH 02/21] drm/amd/display: Assign link type before check dsc workaround Pavle Kotarac
2022-09-07 18:11 ` [PATCH 03/21] drm/amd/display: SW cursor fallback for SubVP Pavle Kotarac
2022-09-07 18:11 ` [PATCH 04/21] drm/amd/display: Fixing DIG FIFO Error Pavle Kotarac
2022-09-07 18:11 ` Pavle Kotarac [this message]
2022-09-07 18:11 ` [PATCH 06/21] drm/amd/display: Fix compilation errors on DCN314 Pavle Kotarac
2022-09-07 18:11 ` [PATCH 07/21] drm/amd/display: Enable dlg and vba compilation for dcn314 Pavle Kotarac
2022-09-07 21:08   ` Li, Roman
2022-09-07 18:11 ` [PATCH 08/21] drm/amd/display: Hook up DCN314 specific dml implementation Pavle Kotarac
2022-09-07 18:11 ` [PATCH 09/21] drm/amd/display: Relax swizzle checks for video non-RGB formats on DCN314 Pavle Kotarac
2022-09-07 18:11 ` [PATCH 10/21] drm/amd/display: Correct dram channel width for dcn314 Pavle Kotarac
2022-09-07 18:11 ` [PATCH 11/21] drm/amd/display: Round cursor width up for MALL allocation Pavle Kotarac
2022-09-08  9:17   ` Christian König
2022-09-07 18:11 ` [PATCH 12/21] drm/amd/display: Update viewport position for phantom pipes Pavle Kotarac
2022-09-07 18:11 ` [PATCH 13/21] drm/amd/display: Added debug option for forcing subvp num ways Pavle Kotarac
2022-09-07 18:11 ` [PATCH 14/21] drm/amd/display: add workaround for subvp cursor corruption for DCN32/321 Pavle Kotarac
2022-09-07 18:11 ` [PATCH 15/21] drm/amd/display: Limit user regamma to a valid value Pavle Kotarac
2022-09-07 18:11 ` [PATCH 16/21] drm/amd/display: Adding log for spread_spectrum_info Pavle Kotarac
2022-09-07 18:11 ` [PATCH 17/21] drm/amd/display: Don't adjust VRR unnecessarily Pavle Kotarac
2022-09-07 18:11 ` [PATCH 18/21] drm/amd/display: Avoid force minimal transaction in case of surface_count equal to 0 Pavle Kotarac
2022-09-07 18:11 ` [PATCH 19/21] drm/amd/display: Refactor SubVP calculation to remove FPU Pavle Kotarac
2022-09-07 18:11 ` [PATCH 20/21] drm/amd/display: Fix register definitions for DCN32/321 Pavle Kotarac
2022-09-07 18:12 ` [PATCH 21/21] drm/amd/display: 3.2.202 Pavle Kotarac

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