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From: Pavle Kotarac <pavle.kotarac@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com,
	"Lee, Alvin" <Alvin.Lee2@amd.com>,
	wayne.lin@amd.com, Jun Lei <Jun.Lei@amd.com>,
	Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com,
	Pavle Kotarac <Pavle.Kotarac@amd.com>
Subject: [PATCH 12/21] drm/amd/display: Update viewport position for phantom pipes
Date: Wed, 7 Sep 2022 14:11:51 -0400	[thread overview]
Message-ID: <20220907181200.54726-12-pavle.kotarac@amd.com> (raw)
In-Reply-To: <20220907181200.54726-1-pavle.kotarac@amd.com>

From: "Lee, Alvin" <Alvin.Lee2@amd.com>

[Description]
In some cases the viewport position of the
main pipes can change without triggering a full update.
In this case the subvp phantom viewports must be updated accordingly.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
---
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  7 ++--
 .../drm/amd/display/dc/dcn32/dcn32_hwseq.c    | 32 +++++++++++++++++++
 .../drm/amd/display/dc/dcn32/dcn32_hwseq.h    |  4 +++
 .../gpu/drm/amd/display/dc/dcn32/dcn32_init.c |  1 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  5 +++
 5 files changed, 47 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 6271caca4d9a..6f8c344e321d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1898,8 +1898,11 @@ void dcn20_post_unlock_program_front_end(
 			 * can underflow due to HUBP_VTG_SEL programming if done in the regular front end
 			 * programming sequence).
 			 */
-			if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)
-					dcn20_program_pipe(dc, pipe, context);
+			if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
+				if (dc->hwss.update_phantom_vp_position)
+					dc->hwss.update_phantom_vp_position(dc, context, pipe);
+				dcn20_program_pipe(dc, pipe, context);
+			}
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index dbf2d7cc96c5..449459ca5a72 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1301,3 +1301,35 @@ void dcn32_update_phy_state(struct dc_state *state, struct pipe_ctx *pipe_ctx,
 	} else
 		BREAK_TO_DEBUGGER();
 }
+
+/* For SubVP the main pipe can have a viewport position change
+ * without a full update. In this case we must also update the
+ * viewport positions for the phantom pipe accordingly.
+ */
+void dcn32_update_phantom_vp_position(struct dc *dc,
+		struct dc_state *context,
+		struct pipe_ctx *phantom_pipe)
+{
+	uint8_t i;
+	struct dc_plane_state *phantom_plane = phantom_pipe->plane_state;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+		if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN &&
+				pipe->stream->mall_stream_config.paired_stream == phantom_pipe->stream) {
+			if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) {
+
+				phantom_plane->src_rect.x = pipe->plane_state->src_rect.x;
+				phantom_plane->src_rect.y = pipe->plane_state->src_rect.y;
+				phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x;
+				phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x;
+				phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y;
+
+				phantom_pipe->plane_state->update_flags.bits.position_change = 1;
+				resource_build_scaling_params(phantom_pipe);
+				return;
+			}
+		}
+	}
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
index 221e31144d50..150d541f35b4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
@@ -87,4 +87,8 @@ bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
 void dcn32_update_phy_state(struct dc_state *state, struct pipe_ctx *pipe_ctx,
 		enum phy_state target_state);
 
+void dcn32_update_phantom_vp_position(struct dc *dc,
+		struct dc_state *context,
+		struct pipe_ctx *phantom_pipe);
+
 #endif /* __DC_HWSS_DCN32_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
index 28d220218133..c554929471af 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
@@ -105,6 +105,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = {
 	.subvp_pipe_control_lock = dcn32_subvp_pipe_control_lock,
 	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
 	.update_phy_state = dcn32_update_phy_state,
+	.update_phantom_vp_position = dcn32_update_phantom_vp_position,
 };
 
 static const struct hwseq_private_funcs dcn32_private_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 52b4350c9cd8..d7a7b2790143 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -247,6 +247,11 @@ struct hw_sequencer_funcs {
 
 	void (*update_phy_state)(struct dc_state *state, struct pipe_ctx *pipe_ctx, enum phy_state target_state);
 
+
+	void (*update_phantom_vp_position)(struct dc *dc,
+			struct dc_state *context,
+			struct pipe_ctx *phantom_pipe);
+
 	void (*commit_subvp_config)(struct dc *dc, struct dc_state *context);
 	void (*subvp_pipe_control_lock)(struct dc *dc,
 			struct dc_state *context,
-- 
2.34.1


  parent reply	other threads:[~2022-09-07 18:13 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-07 18:11 [PATCH 01/21] drm/amd/display: Reverted DSC programming sequence change Pavle Kotarac
2022-09-07 18:11 ` [PATCH 02/21] drm/amd/display: Assign link type before check dsc workaround Pavle Kotarac
2022-09-07 18:11 ` [PATCH 03/21] drm/amd/display: SW cursor fallback for SubVP Pavle Kotarac
2022-09-07 18:11 ` [PATCH 04/21] drm/amd/display: Fixing DIG FIFO Error Pavle Kotarac
2022-09-07 18:11 ` [PATCH 05/21] drm/amd/display: Fix divide by zero in DML Pavle Kotarac
2022-09-07 18:11 ` [PATCH 06/21] drm/amd/display: Fix compilation errors on DCN314 Pavle Kotarac
2022-09-07 18:11 ` [PATCH 07/21] drm/amd/display: Enable dlg and vba compilation for dcn314 Pavle Kotarac
2022-09-07 21:08   ` Li, Roman
2022-09-07 18:11 ` [PATCH 08/21] drm/amd/display: Hook up DCN314 specific dml implementation Pavle Kotarac
2022-09-07 18:11 ` [PATCH 09/21] drm/amd/display: Relax swizzle checks for video non-RGB formats on DCN314 Pavle Kotarac
2022-09-07 18:11 ` [PATCH 10/21] drm/amd/display: Correct dram channel width for dcn314 Pavle Kotarac
2022-09-07 18:11 ` [PATCH 11/21] drm/amd/display: Round cursor width up for MALL allocation Pavle Kotarac
2022-09-08  9:17   ` Christian König
2022-09-07 18:11 ` Pavle Kotarac [this message]
2022-09-07 18:11 ` [PATCH 13/21] drm/amd/display: Added debug option for forcing subvp num ways Pavle Kotarac
2022-09-07 18:11 ` [PATCH 14/21] drm/amd/display: add workaround for subvp cursor corruption for DCN32/321 Pavle Kotarac
2022-09-07 18:11 ` [PATCH 15/21] drm/amd/display: Limit user regamma to a valid value Pavle Kotarac
2022-09-07 18:11 ` [PATCH 16/21] drm/amd/display: Adding log for spread_spectrum_info Pavle Kotarac
2022-09-07 18:11 ` [PATCH 17/21] drm/amd/display: Don't adjust VRR unnecessarily Pavle Kotarac
2022-09-07 18:11 ` [PATCH 18/21] drm/amd/display: Avoid force minimal transaction in case of surface_count equal to 0 Pavle Kotarac
2022-09-07 18:11 ` [PATCH 19/21] drm/amd/display: Refactor SubVP calculation to remove FPU Pavle Kotarac
2022-09-07 18:11 ` [PATCH 20/21] drm/amd/display: Fix register definitions for DCN32/321 Pavle Kotarac
2022-09-07 18:12 ` [PATCH 21/21] drm/amd/display: 3.2.202 Pavle Kotarac

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