* [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
@ 2022-09-27 17:45 Animesh Manna
2022-09-27 17:45 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Animesh Manna @ 2022-09-27 17:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Simplified pps_get_register() which use get_pps_idx() hook to derive the
pps instance and get_pps_idx() will be initialized at pps_init().
v1: Initial version. Got r-b from Jani.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
.../gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_pps.c | 15 ++++++++++-----
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0da9b208d56e..b78b29951241 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1693,6 +1693,7 @@ struct intel_dp {
u8 (*preemph_max)(struct intel_dp *intel_dp);
u8 (*voltage_max)(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
+ int (*get_pps_idx)(struct intel_dp *intel_dp);
/* Displayport compliance testing */
struct intel_dp_compliance compliance;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 21944f5bf3a8..b972fa6ec00d 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -364,12 +364,10 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
int pps_idx = 0;
- memset(regs, 0, sizeof(*regs));
+ if (intel_dp->get_pps_idx)
+ pps_idx = intel_dp->get_pps_idx(intel_dp);
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- pps_idx = bxt_power_sequencer_idx(intel_dp);
- else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- pps_idx = vlv_power_sequencer_pipe(intel_dp);
+ memset(regs, 0, sizeof(*regs));
regs->pp_ctrl = PP_CONTROL(pps_idx);
regs->pp_stat = PP_STATUS(pps_idx);
@@ -1432,6 +1430,13 @@ void intel_pps_init(struct intel_dp *intel_dp)
intel_dp->pps.initializing = true;
INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
+ if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+ intel_dp->get_pps_idx = bxt_power_sequencer_idx;
+ else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
+ else
+ intel_dp->get_pps_idx = NULL;
+
pps_init_timestamps(intel_dp);
with_intel_pps_lock(intel_dp, wakeref) {
--
2.29.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario
2022-09-27 17:45 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna
@ 2022-09-27 17:45 ` Animesh Manna
2022-10-04 7:48 ` Jani Nikula
2022-09-28 2:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Patchwork
2022-09-28 19:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2 siblings, 1 reply; 10+ messages in thread
From: Animesh Manna @ 2022-09-27 17:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From display gen12 onwards to support dual EDP two instances of pps added.
Currently backlight controller and pps instance can be mapped together
for a specific panel. Extended support for gen12 for dual EDP usage.
v1: Iniital revision.
v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. [Jani]
v3: Set pps_id to -1 for pnpid type of panel which will be used by
bxt_power_sequencer_idx() to set 2nd pps instance as default for
2nd EDP panel. [Jani]
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++--
drivers/gpu/drm/i915/display/intel_bios.h | 2 +-
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++---
drivers/gpu/drm/i915/display/intel_pps.c | 12 +++++++++++-
5 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 28bdb936cd1f..2015b6592754 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -3175,13 +3175,14 @@ void intel_bios_init(struct drm_i915_private *i915)
kfree(oprom_vbt);
}
-void intel_bios_init_panel(struct drm_i915_private *i915,
+bool intel_bios_init_panel(struct drm_i915_private *i915,
struct intel_panel *panel,
const struct intel_bios_encoder_data *devdata,
const struct edid *edid)
{
- init_vbt_panel_defaults(panel);
+ bool retry = false;
+ init_vbt_panel_defaults(panel);
panel->vbt.panel_type = get_panel_type(i915, devdata, edid);
parse_panel_options(i915, panel);
@@ -3195,6 +3196,14 @@ void intel_bios_init_panel(struct drm_i915_private *i915,
parse_psr(i915, panel);
parse_mipi_config(i915, panel);
parse_mipi_sequence(i915, panel);
+
+ if (panel->vbt.panel_type == PANEL_TYPE_PNPID ||
+ panel->vbt.panel_type == PANEL_TYPE_FALLBACK) {
+ panel->vbt.edp.pps_id = -1;
+ retry = true;
+ }
+
+ return retry;
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index e375405a7828..f8ef0274f3ee 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -232,7 +232,7 @@ struct mipi_pps_data {
} __packed;
void intel_bios_init(struct drm_i915_private *dev_priv);
-void intel_bios_init_panel(struct drm_i915_private *dev_priv,
+bool intel_bios_init_panel(struct drm_i915_private *dev_priv,
struct intel_panel *panel,
const struct intel_bios_encoder_data *devdata,
const struct edid *edid);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b78b29951241..0edc0b8f3743 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -307,6 +307,7 @@ struct intel_vbt_panel_data {
int preemphasis;
int vswing;
int bpp;
+ int pps_id;
struct edp_power_seq pps;
u8 drrs_msa_timing_delay;
bool low_vswing;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c19e99ee06b6..a94fc947cdb3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5203,6 +5203,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
bool has_dpcd;
enum pipe pipe = INVALID_PIPE;
struct edid *edid;
+ bool retry;
if (!intel_dp_is_edp(intel_dp))
return true;
@@ -5222,6 +5223,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
return false;
}
+ retry = intel_bios_init_panel(dev_priv, &intel_connector->panel,
+ encoder->devdata, NULL);
+
intel_pps_init(intel_dp);
/* Cache DPCD and EDID for edp. */
@@ -5255,9 +5259,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
edid = ERR_PTR(-ENOENT);
}
intel_connector->edid = edid;
-
- intel_bios_init_panel(dev_priv, &intel_connector->panel,
- encoder->devdata, IS_ERR(edid) ? NULL : edid);
+ if (retry)
+ intel_bios_init_panel(dev_priv, &intel_connector->panel,
+ encoder->devdata, IS_ERR(edid) ? NULL : edid);
intel_panel_add_edid_fixed_modes(intel_connector,
intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE,
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index b972fa6ec00d..da98b180639a 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -218,6 +218,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
/* We should never land here with regular DP ports */
drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
+ if (connector->panel.vbt.edp.pps_id == -1) {
+ /*
+ * Use 2nd PPS instance as default for 2nd EDP panel.
+ */
+ if (connector->encoder->port == PORT_A)
+ return 0;
+ else
+ return 1;
+ }
+
if (!intel_dp->pps.pps_reset)
return backlight_controller;
@@ -1430,7 +1440,7 @@ void intel_pps_init(struct intel_dp *intel_dp)
intel_dp->pps.initializing = true;
INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
- if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+ if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >= 12)
intel_dp->get_pps_idx = bxt_power_sequencer_idx;
else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
--
2.29.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
2022-09-27 17:45 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna
2022-09-27 17:45 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna
@ 2022-09-28 2:51 ` Patchwork
2022-09-28 19:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2022-09-28 2:51 UTC (permalink / raw)
To: Manna, Animesh; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6740 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
URL : https://patchwork.freedesktop.org/series/109135/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12193 -> Patchwork_109135v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/index.html
Participating hosts (44 -> 44)
------------------------------
Additional (2): fi-rkl-11600 fi-tgl-dsi
Missing (2): fi-bdw-samus bat-jsl-3
Known issues
------------
Here are the changes found in Patchwork_109135v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-rkl-11600: NOTRUN -> [SKIP][1] ([i915#2190])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-rkl-11600: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/fi-rkl-11600/igt@gem_lmem_swapping@basic.html
* igt@gem_tiled_pread_basic:
- fi-rkl-11600: NOTRUN -> [SKIP][3] ([i915#3282])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600: NOTRUN -> [SKIP][4] ([i915#3012])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][5] ([i915#5982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-rkl-11600: NOTRUN -> [SKIP][6] ([fdo#111827]) +7 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/fi-rkl-11600/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-rkl-11600: NOTRUN -> [SKIP][7] ([i915#4103])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-rkl-11600: NOTRUN -> [SKIP][8] ([fdo#109285] / [i915#4098])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@primary_page_flip:
- fi-rkl-11600: NOTRUN -> [SKIP][9] ([i915#1072]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/fi-rkl-11600/igt@kms_psr@primary_page_flip.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-rkl-11600: NOTRUN -> [SKIP][10] ([i915#3555] / [i915#4098])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-read:
- fi-rkl-11600: NOTRUN -> [SKIP][11] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/fi-rkl-11600/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-userptr:
- fi-rkl-11600: NOTRUN -> [SKIP][12] ([fdo#109295] / [i915#3301] / [i915#3708])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/fi-rkl-11600/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-adlm-1}: [DMESG-WARN][13] ([i915#2867]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/bat-adlm-1/igt@gem_exec_suspend@basic-s3@smem.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/bat-adlm-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-dp-2:
- {bat-dg2-11}: [FAIL][15] ([i915#6818]) -> [PASS][16] +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-dp-2.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-dp-2.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5134]: https://gitlab.freedesktop.org/drm/intel/issues/5134
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
[i915#6818]: https://gitlab.freedesktop.org/drm/intel/issues/6818
[i915#6856]: https://gitlab.freedesktop.org/drm/intel/issues/6856
Build changes
-------------
* Linux: CI_DRM_12193 -> Patchwork_109135v1
CI-20190529: 20190529
CI_DRM_12193: 0f0716dcfd8446cde4391475c9c3656ca670b55f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6666: 1e3ecbaa3c56f4c52c62047707eb4942d3a39c44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109135v1: 0f0716dcfd8446cde4391475c9c3656ca670b55f @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
20d53520e4b8 drm/i915/pps: Enable 2nd pps for dual EDP scenario
c7b8a2b7e243 drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/index.html
[-- Attachment #2: Type: text/html, Size: 7565 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
2022-09-27 17:45 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna
2022-09-27 17:45 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna
2022-09-28 2:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Patchwork
@ 2022-09-28 19:36 ` Patchwork
2 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2022-09-28 19:36 UTC (permalink / raw)
To: Manna, Animesh; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 13504 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
URL : https://patchwork.freedesktop.org/series/109135/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12193_full -> Patchwork_109135v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_109135v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][1] -> [SKIP][2] ([i915#4525])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-iclb2/igt@gem_exec_balancer@parallel-balancer.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-iclb6/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-iclb5/igt@gem_exec_fair@basic-pace@vcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][5] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][6] ([i915#4991])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-apl8/igt@gem_userptr_blits@input-checking.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#5566] / [i915#716])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-glk1/igt@gen9_exec_parse@allowed-single.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-glk5/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#3989] / [i915#454])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-iclb8/igt@i915_pm_dc@dc6-dpms.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-apl1/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_chamelium@dp-hpd-storm-disable:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-apl8/igt@kms_chamelium@dp-hpd-storm-disable.html
* igt@kms_concurrent@pipe-b:
- shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-snb2/igt@kms_concurrent@pipe-b.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][15] ([fdo#109271])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-glk7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#2672]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#2672] / [i915#3555])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271]) +46 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-apl2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][19] ([fdo#108145] / [i915#265])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [PASS][20] -> [SKIP][21] ([i915#5235]) +5 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-iclb3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_properties@crtc-properties-legacy:
- shard-snb: [PASS][22] -> [SKIP][23] ([fdo#109271])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-snb6/igt@kms_properties@crtc-properties-legacy.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-snb2/igt@kms_properties@crtc-properties-legacy.html
* igt@kms_psr@psr2_primary_render:
- shard-iclb: [PASS][24] -> [SKIP][25] ([fdo#109441])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-iclb2/igt@kms_psr@psr2_primary_render.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-iclb7/igt@kms_psr@psr2_primary_render.html
* igt@sysfs_clients@sema-50:
- shard-apl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#2994]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-apl2/igt@sysfs_clients@sema-50.html
#### Possible fixes ####
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [SKIP][27] ([i915#4525]) -> [PASS][28] +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-iclb3/igt@gem_exec_balancer@parallel-contexts.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-iclb1/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][29] ([i915#2842]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [DMESG-WARN][31] ([i915#180]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-apl3/igt@gem_workarounds@suspend-resume.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-apl2/igt@gem_workarounds@suspend-resume.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [DMESG-WARN][33] ([i915#5566] / [i915#716]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-apl1/igt@gen9_exec_parse@allowed-single.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-apl8/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][35] ([i915#3989] / [i915#454]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
- shard-glk: [FAIL][37] ([i915#79]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [SKIP][39] ([i915#5235]) -> [PASS][40] +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-iclb6/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][41] ([fdo#109441]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-tglb: [SKIP][43] ([i915#5519]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-tglb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-tglb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
#### Warnings ####
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-iclb: [SKIP][45] ([i915#2920]) -> [SKIP][46] ([i915#658]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@runner@aborted:
- shard-apl: ([FAIL][47], [FAIL][48], [FAIL][49]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][50], [FAIL][51], [FAIL][52], [FAIL][53], [FAIL][54], [FAIL][55]) ([i915#180] / [i915#3002] / [i915#4312])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-apl1/igt@runner@aborted.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-apl3/igt@runner@aborted.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12193/shard-apl1/igt@runner@aborted.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-apl8/igt@runner@aborted.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-apl8/igt@runner@aborted.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-apl6/igt@runner@aborted.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-apl1/igt@runner@aborted.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-apl3/igt@runner@aborted.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/shard-apl2/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12193 -> Patchwork_109135v1
CI-20190529: 20190529
CI_DRM_12193: 0f0716dcfd8446cde4391475c9c3656ca670b55f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6666: 1e3ecbaa3c56f4c52c62047707eb4942d3a39c44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109135v1: 0f0716dcfd8446cde4391475c9c3656ca670b55f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109135v1/index.html
[-- Attachment #2: Type: text/html, Size: 16428 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario
2022-09-27 17:45 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna
@ 2022-10-04 7:48 ` Jani Nikula
2022-10-10 16:03 ` Manna, Animesh
0 siblings, 1 reply; 10+ messages in thread
From: Jani Nikula @ 2022-10-04 7:48 UTC (permalink / raw)
To: Animesh Manna, intel-gfx
On Tue, 27 Sep 2022, Animesh Manna <animesh.manna@intel.com> wrote:
> From display gen12 onwards to support dual EDP two instances of pps added.
> Currently backlight controller and pps instance can be mapped together
> for a specific panel. Extended support for gen12 for dual EDP usage.
Frankly the dual PPS support was there already, but broken. This fixes
it, and enables it for display 12+.
>
> v1: Iniital revision.
> v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. [Jani]
> v3: Set pps_id to -1 for pnpid type of panel which will be used by
> bxt_power_sequencer_idx() to set 2nd pps instance as default for
> 2nd EDP panel. [Jani]
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++--
> drivers/gpu/drm/i915/display/intel_bios.h | 2 +-
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++---
> drivers/gpu/drm/i915/display/intel_pps.c | 12 +++++++++++-
> 5 files changed, 31 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 28bdb936cd1f..2015b6592754 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -3175,13 +3175,14 @@ void intel_bios_init(struct drm_i915_private *i915)
> kfree(oprom_vbt);
> }
>
> -void intel_bios_init_panel(struct drm_i915_private *i915,
> +bool intel_bios_init_panel(struct drm_i915_private *i915,
> struct intel_panel *panel,
> const struct intel_bios_encoder_data *devdata,
> const struct edid *edid)
> {
> - init_vbt_panel_defaults(panel);
> + bool retry = false;
>
> + init_vbt_panel_defaults(panel);
> panel->vbt.panel_type = get_panel_type(i915, devdata, edid);
>
> parse_panel_options(i915, panel);
> @@ -3195,6 +3196,14 @@ void intel_bios_init_panel(struct drm_i915_private *i915,
> parse_psr(i915, panel);
> parse_mipi_config(i915, panel);
> parse_mipi_sequence(i915, panel);
> +
> + if (panel->vbt.panel_type == PANEL_TYPE_PNPID ||
> + panel->vbt.panel_type == PANEL_TYPE_FALLBACK) {
> + panel->vbt.edp.pps_id = -1;
> + retry = true;
> + }
Why do you initialize everything above if you know the panel type is
garbage and we need to retry? I don't think the above functions were
designed with the idea they could be called multiple times for the same
panel.
Return early if you know it's wrong. Also, don't return true if the EDID
is provided.
BR,
Jani.
> +
> + return retry;
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
> index e375405a7828..f8ef0274f3ee 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.h
> +++ b/drivers/gpu/drm/i915/display/intel_bios.h
> @@ -232,7 +232,7 @@ struct mipi_pps_data {
> } __packed;
>
> void intel_bios_init(struct drm_i915_private *dev_priv);
> -void intel_bios_init_panel(struct drm_i915_private *dev_priv,
> +bool intel_bios_init_panel(struct drm_i915_private *dev_priv,
> struct intel_panel *panel,
> const struct intel_bios_encoder_data *devdata,
> const struct edid *edid);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b78b29951241..0edc0b8f3743 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -307,6 +307,7 @@ struct intel_vbt_panel_data {
> int preemphasis;
> int vswing;
> int bpp;
> + int pps_id;
> struct edp_power_seq pps;
> u8 drrs_msa_timing_delay;
> bool low_vswing;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index c19e99ee06b6..a94fc947cdb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5203,6 +5203,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> bool has_dpcd;
> enum pipe pipe = INVALID_PIPE;
> struct edid *edid;
> + bool retry;
>
> if (!intel_dp_is_edp(intel_dp))
> return true;
> @@ -5222,6 +5223,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> return false;
> }
>
> + retry = intel_bios_init_panel(dev_priv, &intel_connector->panel,
> + encoder->devdata, NULL);
> +
> intel_pps_init(intel_dp);
>
> /* Cache DPCD and EDID for edp. */
> @@ -5255,9 +5259,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> edid = ERR_PTR(-ENOENT);
> }
> intel_connector->edid = edid;
> -
> - intel_bios_init_panel(dev_priv, &intel_connector->panel,
> - encoder->devdata, IS_ERR(edid) ? NULL : edid);
> + if (retry)
> + intel_bios_init_panel(dev_priv, &intel_connector->panel,
> + encoder->devdata, IS_ERR(edid) ? NULL : edid);
>
> intel_panel_add_edid_fixed_modes(intel_connector,
> intel_connector->panel.vbt.drrs_type != DRRS_TYPE_NONE,
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index b972fa6ec00d..da98b180639a 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -218,6 +218,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
> /* We should never land here with regular DP ports */
> drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
>
> + if (connector->panel.vbt.edp.pps_id == -1) {
> + /*
> + * Use 2nd PPS instance as default for 2nd EDP panel.
> + */
> + if (connector->encoder->port == PORT_A)
> + return 0;
> + else
> + return 1;
> + }
> +
> if (!intel_dp->pps.pps_reset)
> return backlight_controller;
>
> @@ -1430,7 +1440,7 @@ void intel_pps_init(struct intel_dp *intel_dp)
> intel_dp->pps.initializing = true;
> INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
>
> - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
> + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >= 12)
> intel_dp->get_pps_idx = bxt_power_sequencer_idx;
> else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario
2022-10-04 7:48 ` Jani Nikula
@ 2022-10-10 16:03 ` Manna, Animesh
0 siblings, 0 replies; 10+ messages in thread
From: Manna, Animesh @ 2022-10-10 16:03 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, October 4, 2022 1:19 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Ville Syrjälä
> <ville.syrjala@linux.intel.com>; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario
>
> On Tue, 27 Sep 2022, Animesh Manna <animesh.manna@intel.com> wrote:
> > From display gen12 onwards to support dual EDP two instances of pps added.
> > Currently backlight controller and pps instance can be mapped together
> > for a specific panel. Extended support for gen12 for dual EDP usage.
>
> Frankly the dual PPS support was there already, but broken. This fixes it, and
> enables it for display 12+.
>
> >
> > v1: Iniital revision.
> > v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init.
> > [Jani]
> > v3: Set pps_id to -1 for pnpid type of panel which will be used by
> > bxt_power_sequencer_idx() to set 2nd pps instance as default for 2nd
> > EDP panel. [Jani]
> >
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++--
> > drivers/gpu/drm/i915/display/intel_bios.h | 2 +-
> > drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++---
> > drivers/gpu/drm/i915/display/intel_pps.c | 12 +++++++++++-
> > 5 files changed, 31 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index 28bdb936cd1f..2015b6592754 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -3175,13 +3175,14 @@ void intel_bios_init(struct drm_i915_private
> *i915)
> > kfree(oprom_vbt);
> > }
> >
> > -void intel_bios_init_panel(struct drm_i915_private *i915,
> > +bool intel_bios_init_panel(struct drm_i915_private *i915,
> > struct intel_panel *panel,
> > const struct intel_bios_encoder_data *devdata,
> > const struct edid *edid)
> > {
> > - init_vbt_panel_defaults(panel);
> > + bool retry = false;
> >
> > + init_vbt_panel_defaults(panel);
> > panel->vbt.panel_type = get_panel_type(i915, devdata, edid);
> >
> > parse_panel_options(i915, panel);
> > @@ -3195,6 +3196,14 @@ void intel_bios_init_panel(struct drm_i915_private
> *i915,
> > parse_psr(i915, panel);
> > parse_mipi_config(i915, panel);
> > parse_mipi_sequence(i915, panel);
> > +
> > + if (panel->vbt.panel_type == PANEL_TYPE_PNPID ||
> > + panel->vbt.panel_type == PANEL_TYPE_FALLBACK) {
> > + panel->vbt.edp.pps_id = -1;
> > + retry = true;
> > + }
>
> Why do you initialize everything above if you know the panel type is garbage and
> we need to retry? I don't think the above functions were designed with the idea
> they could be called multiple times for the same panel.
>
> Return early if you know it's wrong. Also, don't return true if the EDID is
> provided.
Thanks Jani for review, have sent the v4 after addressing the above comments.
Regards,
Animesh
>
> BR,
> Jani.
>
> > +
> > + return retry;
> > }
> >
> > /**
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.h
> > b/drivers/gpu/drm/i915/display/intel_bios.h
> > index e375405a7828..f8ef0274f3ee 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.h
> > @@ -232,7 +232,7 @@ struct mipi_pps_data { } __packed;
> >
> > void intel_bios_init(struct drm_i915_private *dev_priv); -void
> > intel_bios_init_panel(struct drm_i915_private *dev_priv,
> > +bool intel_bios_init_panel(struct drm_i915_private *dev_priv,
> > struct intel_panel *panel,
> > const struct intel_bios_encoder_data *devdata,
> > const struct edid *edid);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index b78b29951241..0edc0b8f3743 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -307,6 +307,7 @@ struct intel_vbt_panel_data {
> > int preemphasis;
> > int vswing;
> > int bpp;
> > + int pps_id;
> > struct edp_power_seq pps;
> > u8 drrs_msa_timing_delay;
> > bool low_vswing;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index c19e99ee06b6..a94fc947cdb3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -5203,6 +5203,7 @@ static bool intel_edp_init_connector(struct intel_dp
> *intel_dp,
> > bool has_dpcd;
> > enum pipe pipe = INVALID_PIPE;
> > struct edid *edid;
> > + bool retry;
> >
> > if (!intel_dp_is_edp(intel_dp))
> > return true;
> > @@ -5222,6 +5223,9 @@ static bool intel_edp_init_connector(struct intel_dp
> *intel_dp,
> > return false;
> > }
> >
> > + retry = intel_bios_init_panel(dev_priv, &intel_connector->panel,
> > + encoder->devdata, NULL);
> > +
> > intel_pps_init(intel_dp);
> >
> > /* Cache DPCD and EDID for edp. */
> > @@ -5255,9 +5259,9 @@ static bool intel_edp_init_connector(struct intel_dp
> *intel_dp,
> > edid = ERR_PTR(-ENOENT);
> > }
> > intel_connector->edid = edid;
> > -
> > - intel_bios_init_panel(dev_priv, &intel_connector->panel,
> > - encoder->devdata, IS_ERR(edid) ? NULL : edid);
> > + if (retry)
> > + intel_bios_init_panel(dev_priv, &intel_connector->panel,
> > + encoder->devdata, IS_ERR(edid) ? NULL :
> edid);
> >
> > intel_panel_add_edid_fixed_modes(intel_connector,
> > intel_connector->panel.vbt.drrs_type
> != DRRS_TYPE_NONE, diff
> > --git a/drivers/gpu/drm/i915/display/intel_pps.c
> > b/drivers/gpu/drm/i915/display/intel_pps.c
> > index b972fa6ec00d..da98b180639a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> > @@ -218,6 +218,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
> > /* We should never land here with regular DP ports */
> > drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
> >
> > + if (connector->panel.vbt.edp.pps_id == -1) {
> > + /*
> > + * Use 2nd PPS instance as default for 2nd EDP panel.
> > + */
> > + if (connector->encoder->port == PORT_A)
> > + return 0;
> > + else
> > + return 1;
> > + }
> > +
> > if (!intel_dp->pps.pps_reset)
> > return backlight_controller;
> >
> > @@ -1430,7 +1440,7 @@ void intel_pps_init(struct intel_dp *intel_dp)
> > intel_dp->pps.initializing = true;
> > INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work,
> > edp_panel_vdd_work);
> >
> > - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
> > + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >=
> > +12)
> > intel_dp->get_pps_idx = bxt_power_sequencer_idx;
> > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> > intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
@ 2022-10-18 8:39 Animesh Manna
0 siblings, 0 replies; 10+ messages in thread
From: Animesh Manna @ 2022-10-18 8:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Simplified pps_get_register() which use get_pps_idx() hook to derive the
pps instance and get_pps_idx() will be initialized at pps_init().
v1: Initial version. Got r-b from Jani.
v2: Corrected unintentional change around memset() call. [Jani]
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_pps.c | 14 +++++++++-----
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e2b853e9e51d..44ab296c1f04 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1694,6 +1694,7 @@ struct intel_dp {
u8 (*preemph_max)(struct intel_dp *intel_dp);
u8 (*voltage_max)(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
+ int (*get_pps_idx)(struct intel_dp *intel_dp);
/* Displayport compliance testing */
struct intel_dp_compliance compliance;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 21944f5bf3a8..9ed62c891b8c 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -365,11 +365,8 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
int pps_idx = 0;
memset(regs, 0, sizeof(*regs));
-
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- pps_idx = bxt_power_sequencer_idx(intel_dp);
- else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- pps_idx = vlv_power_sequencer_pipe(intel_dp);
+ if (intel_dp->get_pps_idx)
+ pps_idx = intel_dp->get_pps_idx(intel_dp);
regs->pp_ctrl = PP_CONTROL(pps_idx);
regs->pp_stat = PP_STATUS(pps_idx);
@@ -1432,6 +1429,13 @@ void intel_pps_init(struct intel_dp *intel_dp)
intel_dp->pps.initializing = true;
INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
+ if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+ intel_dp->get_pps_idx = bxt_power_sequencer_idx;
+ else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
+ else
+ intel_dp->get_pps_idx = NULL;
+
pps_init_timestamps(intel_dp);
with_intel_pps_lock(intel_dp, wakeref) {
--
2.29.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
2022-10-10 15:54 Animesh Manna
@ 2022-10-17 12:20 ` Jani Nikula
0 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2022-10-17 12:20 UTC (permalink / raw)
To: Animesh Manna, intel-gfx
On Mon, 10 Oct 2022, Animesh Manna <animesh.manna@intel.com> wrote:
> Simplified pps_get_register() which use get_pps_idx() hook to derive the
> pps instance and get_pps_idx() will be initialized at pps_init().
>
> v1: Initial version. Got r-b from Jani.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_pps.c | 15 ++++++++++-----
> 2 files changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e2b853e9e51d..44ab296c1f04 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1694,6 +1694,7 @@ struct intel_dp {
> u8 (*preemph_max)(struct intel_dp *intel_dp);
> u8 (*voltage_max)(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> + int (*get_pps_idx)(struct intel_dp *intel_dp);
>
> /* Displayport compliance testing */
> struct intel_dp_compliance compliance;
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index 21944f5bf3a8..b972fa6ec00d 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -364,12 +364,10 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> int pps_idx = 0;
>
> - memset(regs, 0, sizeof(*regs));
> + if (intel_dp->get_pps_idx)
> + pps_idx = intel_dp->get_pps_idx(intel_dp);
>
> - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> - pps_idx = bxt_power_sequencer_idx(intel_dp);
> - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - pps_idx = vlv_power_sequencer_pipe(intel_dp);
> + memset(regs, 0, sizeof(*regs));
It's benign and I've approved this already, but since I keep having to
look at the patch over and over, it has really started bugging me that
the memset() and ->get_pps_idx() calls change their order for no obvious
reason. When you do refactoring, just don't do accidental functional
changes at the same time.
BR,
Jani.
>
> regs->pp_ctrl = PP_CONTROL(pps_idx);
> regs->pp_stat = PP_STATUS(pps_idx);
> @@ -1432,6 +1430,13 @@ void intel_pps_init(struct intel_dp *intel_dp)
> intel_dp->pps.initializing = true;
> INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
>
> + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
> + intel_dp->get_pps_idx = bxt_power_sequencer_idx;
> + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> + intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
> + else
> + intel_dp->get_pps_idx = NULL;
> +
> pps_init_timestamps(intel_dp);
>
> with_intel_pps_lock(intel_dp, wakeref) {
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
@ 2022-10-10 15:54 Animesh Manna
2022-10-17 12:20 ` Jani Nikula
0 siblings, 1 reply; 10+ messages in thread
From: Animesh Manna @ 2022-10-10 15:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Simplified pps_get_register() which use get_pps_idx() hook to derive the
pps instance and get_pps_idx() will be initialized at pps_init().
v1: Initial version. Got r-b from Jani.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
.../gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_pps.c | 15 ++++++++++-----
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e2b853e9e51d..44ab296c1f04 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1694,6 +1694,7 @@ struct intel_dp {
u8 (*preemph_max)(struct intel_dp *intel_dp);
u8 (*voltage_max)(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
+ int (*get_pps_idx)(struct intel_dp *intel_dp);
/* Displayport compliance testing */
struct intel_dp_compliance compliance;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 21944f5bf3a8..b972fa6ec00d 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -364,12 +364,10 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
int pps_idx = 0;
- memset(regs, 0, sizeof(*regs));
+ if (intel_dp->get_pps_idx)
+ pps_idx = intel_dp->get_pps_idx(intel_dp);
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- pps_idx = bxt_power_sequencer_idx(intel_dp);
- else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- pps_idx = vlv_power_sequencer_pipe(intel_dp);
+ memset(regs, 0, sizeof(*regs));
regs->pp_ctrl = PP_CONTROL(pps_idx);
regs->pp_stat = PP_STATUS(pps_idx);
@@ -1432,6 +1430,13 @@ void intel_pps_init(struct intel_dp *intel_dp)
intel_dp->pps.initializing = true;
INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
+ if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+ intel_dp->get_pps_idx = bxt_power_sequencer_idx;
+ else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
+ else
+ intel_dp->get_pps_idx = NULL;
+
pps_init_timestamps(intel_dp);
with_intel_pps_lock(intel_dp, wakeref) {
--
2.29.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
@ 2022-09-16 8:31 Animesh Manna
0 siblings, 0 replies; 10+ messages in thread
From: Animesh Manna @ 2022-09-16 8:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Simplified pps_get_register() which use get_pps_idx() hook to derive the
pps instance and get_pps_idx() will be initialized at pps_init().
v1: Initial version. Got r-b from Jani.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
.../gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_pps.c | 15 ++++++++++-----
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0da9b208d56e..b78b29951241 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1693,6 +1693,7 @@ struct intel_dp {
u8 (*preemph_max)(struct intel_dp *intel_dp);
u8 (*voltage_max)(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
+ int (*get_pps_idx)(struct intel_dp *intel_dp);
/* Displayport compliance testing */
struct intel_dp_compliance compliance;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 21944f5bf3a8..b972fa6ec00d 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -364,12 +364,10 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
int pps_idx = 0;
- memset(regs, 0, sizeof(*regs));
+ if (intel_dp->get_pps_idx)
+ pps_idx = intel_dp->get_pps_idx(intel_dp);
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- pps_idx = bxt_power_sequencer_idx(intel_dp);
- else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- pps_idx = vlv_power_sequencer_pipe(intel_dp);
+ memset(regs, 0, sizeof(*regs));
regs->pp_ctrl = PP_CONTROL(pps_idx);
regs->pp_stat = PP_STATUS(pps_idx);
@@ -1432,6 +1430,13 @@ void intel_pps_init(struct intel_dp *intel_dp)
intel_dp->pps.initializing = true;
INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
+ if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+ intel_dp->get_pps_idx = bxt_power_sequencer_idx;
+ else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
+ else
+ intel_dp->get_pps_idx = NULL;
+
pps_init_timestamps(intel_dp);
with_intel_pps_lock(intel_dp, wakeref) {
--
2.29.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-10-18 8:44 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-27 17:45 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna
2022-09-27 17:45 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna
2022-10-04 7:48 ` Jani Nikula
2022-10-10 16:03 ` Manna, Animesh
2022-09-28 2:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Patchwork
2022-09-28 19:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2022-10-18 8:39 [Intel-gfx] [PATCH 1/2] " Animesh Manna
2022-10-10 15:54 Animesh Manna
2022-10-17 12:20 ` Jani Nikula
2022-09-16 8:31 Animesh Manna
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