* [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
@ 2022-10-10 15:54 Animesh Manna
2022-10-10 15:54 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Animesh Manna @ 2022-10-10 15:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Simplified pps_get_register() which use get_pps_idx() hook to derive the
pps instance and get_pps_idx() will be initialized at pps_init().
v1: Initial version. Got r-b from Jani.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
.../gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_pps.c | 15 ++++++++++-----
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e2b853e9e51d..44ab296c1f04 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1694,6 +1694,7 @@ struct intel_dp {
u8 (*preemph_max)(struct intel_dp *intel_dp);
u8 (*voltage_max)(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
+ int (*get_pps_idx)(struct intel_dp *intel_dp);
/* Displayport compliance testing */
struct intel_dp_compliance compliance;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 21944f5bf3a8..b972fa6ec00d 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -364,12 +364,10 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
int pps_idx = 0;
- memset(regs, 0, sizeof(*regs));
+ if (intel_dp->get_pps_idx)
+ pps_idx = intel_dp->get_pps_idx(intel_dp);
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- pps_idx = bxt_power_sequencer_idx(intel_dp);
- else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- pps_idx = vlv_power_sequencer_pipe(intel_dp);
+ memset(regs, 0, sizeof(*regs));
regs->pp_ctrl = PP_CONTROL(pps_idx);
regs->pp_stat = PP_STATUS(pps_idx);
@@ -1432,6 +1430,13 @@ void intel_pps_init(struct intel_dp *intel_dp)
intel_dp->pps.initializing = true;
INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
+ if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+ intel_dp->get_pps_idx = bxt_power_sequencer_idx;
+ else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
+ else
+ intel_dp->get_pps_idx = NULL;
+
pps_init_timestamps(intel_dp);
with_intel_pps_lock(intel_dp, wakeref) {
--
2.29.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario
2022-10-10 15:54 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna
@ 2022-10-10 15:54 ` Animesh Manna
2022-10-17 13:08 ` Jani Nikula
2022-10-10 16:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Patchwork
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Animesh Manna @ 2022-10-10 15:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From display gen12 onwards to support dual EDP two instances of pps added.
Currently backlight controller and pps instance can be mapped together
for a specific panel. Currently dual PPS support is broken. This patch fixes
it and enables for display 12+.
v1: Iniital revision.
v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. [Jani]
v3: Set pps_id to -1 for pnpid type of panel which will be used by
bxt_power_sequencer_idx() to set 2nd pps instance as default for
2nd EDP panel. [Jani]
v4: Early return for PANEL_TYPE_FALLBACK. [Jani]
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++--
drivers/gpu/drm/i915/display/intel_bios.h | 2 +-
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++---
drivers/gpu/drm/i915/display/intel_pps.c | 12 +++++++++++-
5 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index c2987f2c2b2e..dd3cd2ca815d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -3183,15 +3183,22 @@ void intel_bios_init(struct drm_i915_private *i915)
kfree(oprom_vbt);
}
-void intel_bios_init_panel(struct drm_i915_private *i915,
+bool intel_bios_init_panel(struct drm_i915_private *i915,
struct intel_panel *panel,
const struct intel_bios_encoder_data *devdata,
const struct edid *edid)
{
init_vbt_panel_defaults(panel);
-
panel->vbt.panel_type = get_panel_type(i915, devdata, edid);
+ if (panel->vbt.panel_type == PANEL_TYPE_PNPID ||
+ panel->vbt.panel_type == PANEL_TYPE_FALLBACK) {
+ panel->vbt.edp.pps_id = -1;
+
+ if (!edid && intel_bios_encoder_supports_edp(devdata))
+ return true;
+ }
+
parse_panel_options(i915, panel);
parse_generic_dtd(i915, panel);
parse_lfp_data(i915, panel);
@@ -3203,6 +3210,8 @@ void intel_bios_init_panel(struct drm_i915_private *i915,
parse_psr(i915, panel);
parse_mipi_config(i915, panel);
parse_mipi_sequence(i915, panel);
+
+ return false;
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index e375405a7828..f8ef0274f3ee 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -232,7 +232,7 @@ struct mipi_pps_data {
} __packed;
void intel_bios_init(struct drm_i915_private *dev_priv);
-void intel_bios_init_panel(struct drm_i915_private *dev_priv,
+bool intel_bios_init_panel(struct drm_i915_private *dev_priv,
struct intel_panel *panel,
const struct intel_bios_encoder_data *devdata,
const struct edid *edid);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 44ab296c1f04..37e8309207bf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -307,6 +307,7 @@ struct intel_vbt_panel_data {
int preemphasis;
int vswing;
int bpp;
+ int pps_id;
struct edp_power_seq pps;
u8 drrs_msa_timing_delay;
bool low_vswing;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 70b06806ec0d..50d9223562e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5235,6 +5235,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
bool has_dpcd;
struct edid *edid;
+ bool retry;
if (!intel_dp_is_edp(intel_dp))
return true;
@@ -5254,6 +5255,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
return false;
}
+ retry = intel_bios_init_panel(dev_priv, &intel_connector->panel,
+ encoder->devdata, NULL);
+
intel_pps_init(intel_dp);
/* Cache DPCD and EDID for edp. */
@@ -5288,9 +5292,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
edid = ERR_PTR(-ENOENT);
}
intel_connector->edid = edid;
-
- intel_bios_init_panel(dev_priv, &intel_connector->panel,
- encoder->devdata, IS_ERR(edid) ? NULL : edid);
+ if (retry)
+ intel_bios_init_panel(dev_priv, &intel_connector->panel,
+ encoder->devdata, IS_ERR(edid) ? NULL : edid);
intel_panel_add_edid_fixed_modes(intel_connector, true);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index b972fa6ec00d..da98b180639a 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -218,6 +218,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
/* We should never land here with regular DP ports */
drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
+ if (connector->panel.vbt.edp.pps_id == -1) {
+ /*
+ * Use 2nd PPS instance as default for 2nd EDP panel.
+ */
+ if (connector->encoder->port == PORT_A)
+ return 0;
+ else
+ return 1;
+ }
+
if (!intel_dp->pps.pps_reset)
return backlight_controller;
@@ -1430,7 +1440,7 @@ void intel_pps_init(struct intel_dp *intel_dp)
intel_dp->pps.initializing = true;
INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
- if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+ if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >= 12)
intel_dp->get_pps_idx = bxt_power_sequencer_idx;
else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
--
2.29.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
2022-10-10 15:54 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna
2022-10-10 15:54 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna
@ 2022-10-10 16:37 ` Patchwork
2022-10-10 16:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2022-10-10 16:37 UTC (permalink / raw)
To: Manna, Animesh; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
URL : https://patchwork.freedesktop.org/series/109547/
State : warning
== Summary ==
Error: dim checkpatch failed
25167c11f19e drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
f59d1e59c801 drm/i915/pps: Enable 2nd pps for dual EDP scenario
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#11:
for a specific panel. Currently dual PPS support is broken. This patch fixes
total: 0 errors, 1 warnings, 0 checks, 99 lines checked
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
2022-10-10 15:54 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna
2022-10-10 15:54 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna
2022-10-10 16:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Patchwork
@ 2022-10-10 16:56 ` Patchwork
2022-10-10 21:56 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-10-17 12:20 ` [Intel-gfx] [PATCH 1/2] " Jani Nikula
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2022-10-10 16:56 UTC (permalink / raw)
To: Manna, Animesh; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5096 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
URL : https://patchwork.freedesktop.org/series/109547/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12230 -> Patchwork_109547v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/index.html
Participating hosts (47 -> 42)
------------------------------
Missing (5): fi-cml-u2 fi-tgl-dsi fi-icl-u2 fi-ctg-p8600 bat-atsm-1
Known issues
------------
Here are the changes found in Patchwork_109547v1 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}: [DMESG-WARN][1] ([i915#2867]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-rpls-1}: [DMESG-WARN][3] ([i915#6687]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u: [DMESG-FAIL][5] ([i915#62]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u: [DMESG-WARN][7] ([i915#5904]) -> [PASS][8] +30 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
* igt@i915_selftest@live@reset:
- {bat-rpls-2}: [DMESG-FAIL][9] ([i915#5828]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/bat-rpls-2/igt@i915_selftest@live@reset.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/bat-rpls-2/igt@i915_selftest@live@reset.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u: [DMESG-WARN][11] ([i915#5904] / [i915#62]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [DMESG-WARN][13] ([i915#62]) -> [PASS][14] +13 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#5278]: https://gitlab.freedesktop.org/drm/intel/issues/5278
[i915#5828]: https://gitlab.freedesktop.org/drm/intel/issues/5828
[i915#5904]: https://gitlab.freedesktop.org/drm/intel/issues/5904
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
[i915#6559]: https://gitlab.freedesktop.org/drm/intel/issues/6559
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7029]: https://gitlab.freedesktop.org/drm/intel/issues/7029
[i915#7031]: https://gitlab.freedesktop.org/drm/intel/issues/7031
Build changes
-------------
* Linux: CI_DRM_12230 -> Patchwork_109547v1
CI-20190529: 20190529
CI_DRM_12230: 345932c390f8b2e97a89749633e2c3c523f6f740 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7006: ea6d73b73b88de85d921cbc2680ae8979a2c3ce9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109547v1: 345932c390f8b2e97a89749633e2c3c523f6f740 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
50a968ea67ae drm/i915/pps: Enable 2nd pps for dual EDP scenario
3c9fa63be777 drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/index.html
[-- Attachment #2: Type: text/html, Size: 5399 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
2022-10-10 15:54 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna
` (2 preceding siblings ...)
2022-10-10 16:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-10-10 21:56 ` Patchwork
2022-10-17 12:20 ` [Intel-gfx] [PATCH 1/2] " Jani Nikula
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2022-10-10 21:56 UTC (permalink / raw)
To: Manna, Animesh; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30794 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
URL : https://patchwork.freedesktop.org/series/109547/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12230_full -> Patchwork_109547v1_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_109547v1_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_109547v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_109547v1_full:
### IGT changes ###
#### Warnings ####
* igt@kms_content_protection@atomic@pipe-a-dp-1:
- shard-apl: [INCOMPLETE][1] ([i915#1982]) -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-apl2/igt@kms_content_protection@atomic@pipe-a-dp-1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-apl1/igt@kms_content_protection@atomic@pipe-a-dp-1.html
* igt@perf@non-zero-reason:
- shard-skl: [TIMEOUT][3] ([i915#6943] / [i915#7065]) -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-skl6/igt@perf@non-zero-reason.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl6/igt@perf@non-zero-reason.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_psr2_su@page_flip-nv12@pipe-b-edp-1}:
- shard-iclb: NOTRUN -> [FAIL][5] +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb2/igt@kms_psr2_su@page_flip-nv12@pipe-b-edp-1.html
Known issues
------------
Here are the changes found in Patchwork_109547v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@dmabuf@all@dma_fence_chain:
- shard-skl: NOTRUN -> [INCOMPLETE][6] ([i915#6949])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl4/igt@dmabuf@all@dma_fence_chain.html
* igt@drm_fdinfo@all-busy-check-all:
- shard-skl: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#5608])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl4/igt@drm_fdinfo@all-busy-check-all.html
* igt@gem_ccs@suspend-resume:
- shard-tglb: NOTRUN -> [SKIP][8] ([i915#5325])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@gem_ccs@suspend-resume.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#6268])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-tglb7/igt@gem_ctx_exec@basic-nohangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb8/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-tglb: [PASS][11] -> [TIMEOUT][12] ([i915#3063])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-tglb7/igt@gem_eio@in-flight-contexts-1us.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb7/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_eio@in-flight-suspend:
- shard-skl: [PASS][13] -> [INCOMPLETE][14] ([i915#7112])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-skl9/igt@gem_eio@in-flight-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl10/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-tglb: NOTRUN -> [FAIL][15] ([i915#6117])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][16] -> [FAIL][17] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][18] ([i915#2842])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb2/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglb: NOTRUN -> [FAIL][19] ([i915#2842])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][20] -> [FAIL][21] ([i915#2842])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-glk2/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_fence@basic-wait:
- shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271]) +140 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl4/igt@gem_exec_fence@basic-wait.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-skl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#4613]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl4/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_pread@exhaustion:
- shard-skl: NOTRUN -> [WARN][24] ([i915#2658])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl4/igt@gem_pread@exhaustion.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-tglb: NOTRUN -> [SKIP][25] ([i915#3297])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][26] -> [DMESG-WARN][27] ([i915#5566] / [i915#716])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-glk9/igt@gen9_exec_parse@allowed-all.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-glk1/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][28] -> [DMESG-WARN][29] ([i915#5566] / [i915#716])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-apl6/igt@gen9_exec_parse@allowed-single.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-apl8/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-chained:
- shard-tglb: NOTRUN -> [SKIP][30] ([i915#2527] / [i915#2856])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@gen9_exec_parse@bb-chained.html
* igt@i915_query@hwconfig_table:
- shard-tglb: NOTRUN -> [SKIP][31] ([i915#6245])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@i915_query@hwconfig_table.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-skl: [PASS][32] -> [DMESG-FAIL][33] ([i915#5334])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-skl7/igt@i915_selftest@live@gt_heartbeat.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl5/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@mock@vma:
- shard-skl: NOTRUN -> [INCOMPLETE][34] ([i915#6950] / [i915#7065])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl4/igt@i915_selftest@mock@vma.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][35] -> [DMESG-WARN][36] ([i915#180])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-apl8/igt@i915_suspend@fence-restore-tiled2untiled.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-apl3/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
- shard-skl: [PASS][37] -> [FAIL][38] ([i915#2521]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-skl4/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl3/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-180:
- shard-tglb: NOTRUN -> [SKIP][39] ([i915#5286])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@kms_big_fb@4-tiled-16bpp-rotate-180.html
* igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_dg2_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][40] ([i915#3689] / [i915#6095])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#3886]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl4/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][42] ([i915#3689] / [i915#3886]) +2 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][43] ([i915#3689])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_ccs.html
* igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs:
- shard-tglb: NOTRUN -> [SKIP][44] ([i915#6095]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs.html
* igt@kms_chamelium@dp-edid-change-during-suspend:
- shard-skl: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl5/igt@kms_chamelium@dp-edid-change-during-suspend.html
* igt@kms_chamelium@vga-hpd-with-enabled-mode:
- shard-tglb: NOTRUN -> [SKIP][46] ([fdo#109284] / [fdo#111827]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@kms_chamelium@vga-hpd-with-enabled-mode.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x32:
- shard-tglb: NOTRUN -> [SKIP][47] ([i915#3555])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
* igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1:
- shard-tglb: [PASS][48] -> [INCOMPLETE][49] ([i915#6021]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-tglb7/igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb8/igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1.html
* igt@kms_cursor_legacy@flip-vs-cursor@toggle:
- shard-iclb: [PASS][50] -> [FAIL][51] ([i915#2346]) +2 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-iclb1/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: [PASS][52] -> [FAIL][53] ([i915#4767])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-skl10/igt@kms_fbcon_fbt@psr-suspend.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl6/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-tglb: NOTRUN -> [SKIP][54] ([fdo#109274] / [fdo#111825] / [i915#3637])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-skl: [PASS][55] -> [FAIL][56] ([i915#2122]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][57] ([i915#6375])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][58] ([i915#2672]) +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][59] ([i915#2672] / [i915#3555])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode:
- shard-tglb: NOTRUN -> [SKIP][60] ([i915#2587] / [i915#2672])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode:
- shard-iclb: [PASS][61] -> [SKIP][62] ([i915#3555])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][63] ([i915#2587] / [i915#2672]) +3 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
- shard-tglb: NOTRUN -> [SKIP][64] ([i915#6497]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite:
- shard-tglb: NOTRUN -> [SKIP][65] ([fdo#109280] / [fdo#111825]) +7 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-edp-1:
- shard-tglb: NOTRUN -> [SKIP][66] ([i915#5235]) +3 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-edp-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1:
- shard-iclb: [PASS][67] -> [SKIP][68] ([i915#5235]) +2 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-iclb7/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-tglb: NOTRUN -> [SKIP][69] ([i915#2920])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr@psr2_basic:
- shard-tglb: NOTRUN -> [FAIL][70] ([i915#132] / [i915#3467]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb5/igt@kms_psr@psr2_basic.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][71] -> [SKIP][72] ([fdo#109441]) +3 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_writeback@writeback-check-output:
- shard-skl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#2437])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl4/igt@kms_writeback@writeback-check-output.html
* igt@perf@stress-open-close:
- shard-glk: [PASS][74] -> [INCOMPLETE][75] ([i915#5213])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-glk6/igt@perf@stress-open-close.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-glk3/igt@perf@stress-open-close.html
* igt@sysfs_clients@fair-0:
- shard-skl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#2994])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl4/igt@sysfs_clients@fair-0.html
#### Possible fixes ####
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][77] ([i915#4525]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-iclb8/igt@gem_exec_balancer@parallel-out-fence.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-glk: [FAIL][79] ([i915#2842]) -> [PASS][80] +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-glk6/igt@gem_exec_fair@basic-none@vcs0.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-glk1/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [FAIL][81] ([i915#2842]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-apl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-apl2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@kms_addfb_basic@legacy-format:
- shard-tglb: [INCOMPLETE][83] ([i915#6987]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-tglb5/igt@kms_addfb_basic@legacy-format.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-tglb7/igt@kms_addfb_basic@legacy-format.html
* igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1:
- shard-skl: [INCOMPLETE][85] ([i915#4939]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-skl10/igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl4/igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1.html
* igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions:
- shard-iclb: [FAIL][87] ([i915#5072]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb1/igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [FAIL][89] ([i915#2346]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_flip@plain-flip-ts-check@c-edp1:
- shard-skl: [FAIL][91] ([i915#2122]) -> [PASS][92] +2 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-skl1/igt@kms_flip@plain-flip-ts-check@c-edp1.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl10/igt@kms_flip@plain-flip-ts-check@c-edp1.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1:
- shard-iclb: [SKIP][93] ([i915#5176]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-iclb3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb2/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [SKIP][95] ([i915#5235]) -> [PASS][96] +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb5/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [SKIP][97] ([fdo#109441]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_cpu.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@perf@polling-parameterized:
- shard-glk: [FAIL][99] ([i915#5639]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-glk8/igt@perf@polling-parameterized.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-glk6/igt@perf@polling-parameterized.html
* igt@perf@stress-open-close:
- shard-skl: [INCOMPLETE][101] ([i915#5213]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-skl10/igt@perf@stress-open-close.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-skl5/igt@perf@stress-open-close.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [FAIL][103] ([i915#6117]) -> [SKIP][104] ([i915#4525])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb7/igt@gem_exec_balancer@parallel-ordering.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-iclb: [SKIP][105] ([i915#658]) -> [SKIP][106] ([i915#2920])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-iclb3/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-iclb: [SKIP][107] ([i915#2920]) -> [SKIP][108] ([fdo#111068] / [i915#658])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][109] ([fdo#111068] / [i915#658]) -> [SKIP][110] ([i915#2920]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@runner@aborted:
- shard-apl: ([FAIL][111], [FAIL][112], [FAIL][113]) ([i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-apl3/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-apl6/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12230/shard-apl6/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-apl6/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-apl3/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-apl7/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/shard-apl8/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#5072]: https://gitlab.freedesktop.org/drm/intel/issues/5072
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#6021]: https://gitlab.freedesktop.org/drm/intel/issues/6021
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6375]: https://gitlab.freedesktop.org/drm/intel/issues/6375
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6943]: https://gitlab.freedesktop.org/drm/intel/issues/6943
[i915#6949]: https://gitlab.freedesktop.org/drm/intel/issues/6949
[i915#6950]: https://gitlab.freedesktop.org/drm/intel/issues/6950
[i915#6987]: https://gitlab.freedesktop.org/drm/intel/issues/6987
[i915#7065]: https://gitlab.freedesktop.org/drm/intel/issues/7065
[i915#7112]: https://gitlab.freedesktop.org/drm/intel/issues/7112
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
Build changes
-------------
* Linux: CI_DRM_12230 -> Patchwork_109547v1
CI-20190529: 20190529
CI_DRM_12230: 345932c390f8b2e97a89749633e2c3c523f6f740 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7006: ea6d73b73b88de85d921cbc2680ae8979a2c3ce9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109547v1: 345932c390f8b2e97a89749633e2c3c523f6f740 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109547v1/index.html
[-- Attachment #2: Type: text/html, Size: 36725 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
2022-10-10 15:54 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna
` (3 preceding siblings ...)
2022-10-10 21:56 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2022-10-17 12:20 ` Jani Nikula
4 siblings, 0 replies; 11+ messages in thread
From: Jani Nikula @ 2022-10-17 12:20 UTC (permalink / raw)
To: Animesh Manna, intel-gfx
On Mon, 10 Oct 2022, Animesh Manna <animesh.manna@intel.com> wrote:
> Simplified pps_get_register() which use get_pps_idx() hook to derive the
> pps instance and get_pps_idx() will be initialized at pps_init().
>
> v1: Initial version. Got r-b from Jani.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_pps.c | 15 ++++++++++-----
> 2 files changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e2b853e9e51d..44ab296c1f04 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1694,6 +1694,7 @@ struct intel_dp {
> u8 (*preemph_max)(struct intel_dp *intel_dp);
> u8 (*voltage_max)(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> + int (*get_pps_idx)(struct intel_dp *intel_dp);
>
> /* Displayport compliance testing */
> struct intel_dp_compliance compliance;
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index 21944f5bf3a8..b972fa6ec00d 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -364,12 +364,10 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> int pps_idx = 0;
>
> - memset(regs, 0, sizeof(*regs));
> + if (intel_dp->get_pps_idx)
> + pps_idx = intel_dp->get_pps_idx(intel_dp);
>
> - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> - pps_idx = bxt_power_sequencer_idx(intel_dp);
> - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - pps_idx = vlv_power_sequencer_pipe(intel_dp);
> + memset(regs, 0, sizeof(*regs));
It's benign and I've approved this already, but since I keep having to
look at the patch over and over, it has really started bugging me that
the memset() and ->get_pps_idx() calls change their order for no obvious
reason. When you do refactoring, just don't do accidental functional
changes at the same time.
BR,
Jani.
>
> regs->pp_ctrl = PP_CONTROL(pps_idx);
> regs->pp_stat = PP_STATUS(pps_idx);
> @@ -1432,6 +1430,13 @@ void intel_pps_init(struct intel_dp *intel_dp)
> intel_dp->pps.initializing = true;
> INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
>
> + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
> + intel_dp->get_pps_idx = bxt_power_sequencer_idx;
> + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> + intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
> + else
> + intel_dp->get_pps_idx = NULL;
> +
> pps_init_timestamps(intel_dp);
>
> with_intel_pps_lock(intel_dp, wakeref) {
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario
2022-10-10 15:54 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna
@ 2022-10-17 13:08 ` Jani Nikula
2022-10-18 8:50 ` Manna, Animesh
0 siblings, 1 reply; 11+ messages in thread
From: Jani Nikula @ 2022-10-17 13:08 UTC (permalink / raw)
To: Animesh Manna, intel-gfx
On Mon, 10 Oct 2022, Animesh Manna <animesh.manna@intel.com> wrote:
> From display gen12 onwards to support dual EDP two instances of pps added.
> Currently backlight controller and pps instance can be mapped together
> for a specific panel. Currently dual PPS support is broken. This patch fixes
> it and enables for display 12+.
>
> v1: Iniital revision.
> v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init. [Jani]
> v3: Set pps_id to -1 for pnpid type of panel which will be used by
> bxt_power_sequencer_idx() to set 2nd pps instance as default for
> 2nd EDP panel. [Jani]
> v4: Early return for PANEL_TYPE_FALLBACK. [Jani]
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++--
> drivers/gpu/drm/i915/display/intel_bios.h | 2 +-
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++---
> drivers/gpu/drm/i915/display/intel_pps.c | 12 +++++++++++-
> 5 files changed, 31 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index c2987f2c2b2e..dd3cd2ca815d 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -3183,15 +3183,22 @@ void intel_bios_init(struct drm_i915_private *i915)
> kfree(oprom_vbt);
> }
>
> -void intel_bios_init_panel(struct drm_i915_private *i915,
> +bool intel_bios_init_panel(struct drm_i915_private *i915,
> struct intel_panel *panel,
> const struct intel_bios_encoder_data *devdata,
> const struct edid *edid)
> {
> init_vbt_panel_defaults(panel);
> -
Please don't do superfluous whitespace changes.
> panel->vbt.panel_type = get_panel_type(i915, devdata, edid);
>
> + if (panel->vbt.panel_type == PANEL_TYPE_PNPID ||
> + panel->vbt.panel_type == PANEL_TYPE_FALLBACK) {
> + panel->vbt.edp.pps_id = -1;
> +
> + if (!edid && intel_bios_encoder_supports_edp(devdata))
> + return true;
> + }
> +
if (panel->vbt.panel_type == PANEL_TYPE_FALLBACK && !edid) {
panel->vbt.backlight.controller = -1;
return true;
}
> parse_panel_options(i915, panel);
> parse_generic_dtd(i915, panel);
> parse_lfp_data(i915, panel);
> @@ -3203,6 +3210,8 @@ void intel_bios_init_panel(struct drm_i915_private *i915,
> parse_psr(i915, panel);
> parse_mipi_config(i915, panel);
> parse_mipi_sequence(i915, panel);
> +
> + return false;
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
> index e375405a7828..f8ef0274f3ee 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.h
> +++ b/drivers/gpu/drm/i915/display/intel_bios.h
> @@ -232,7 +232,7 @@ struct mipi_pps_data {
> } __packed;
>
> void intel_bios_init(struct drm_i915_private *dev_priv);
> -void intel_bios_init_panel(struct drm_i915_private *dev_priv,
> +bool intel_bios_init_panel(struct drm_i915_private *dev_priv,
> struct intel_panel *panel,
> const struct intel_bios_encoder_data *devdata,
> const struct edid *edid);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 44ab296c1f04..37e8309207bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -307,6 +307,7 @@ struct intel_vbt_panel_data {
> int preemphasis;
> int vswing;
> int bpp;
> + int pps_id;
Unnecessary.
> struct edp_power_seq pps;
> u8 drrs_msa_timing_delay;
> bool low_vswing;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 70b06806ec0d..50d9223562e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5235,6 +5235,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> bool has_dpcd;
> struct edid *edid;
> + bool retry;
>
> if (!intel_dp_is_edp(intel_dp))
> return true;
> @@ -5254,6 +5255,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> return false;
> }
>
> + retry = intel_bios_init_panel(dev_priv, &intel_connector->panel,
> + encoder->devdata, NULL);
> +
> intel_pps_init(intel_dp);
>
> /* Cache DPCD and EDID for edp. */
> @@ -5288,9 +5292,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> edid = ERR_PTR(-ENOENT);
> }
> intel_connector->edid = edid;
> -
> - intel_bios_init_panel(dev_priv, &intel_connector->panel,
> - encoder->devdata, IS_ERR(edid) ? NULL : edid);
> + if (retry)
> + intel_bios_init_panel(dev_priv, &intel_connector->panel,
> + encoder->devdata, IS_ERR(edid) ? NULL : edid);
>
> intel_panel_add_edid_fixed_modes(intel_connector, true);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index b972fa6ec00d..da98b180639a 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -218,6 +218,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
> /* We should never land here with regular DP ports */
> drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
>
> + if (connector->panel.vbt.edp.pps_id == -1) {
if (backlight_controller == -1)
backlight_controller = connector->encoder->port == PORT_A ? 0 : 1;
> + /*
> + * Use 2nd PPS instance as default for 2nd EDP panel.
> + */
> + if (connector->encoder->port == PORT_A)
> + return 0;
> + else
> + return 1;
> + }
> +
> if (!intel_dp->pps.pps_reset)
> return backlight_controller;
>
> @@ -1430,7 +1440,7 @@ void intel_pps_init(struct intel_dp *intel_dp)
> intel_dp->pps.initializing = true;
> INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
>
> - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
> + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >= 12)
> intel_dp->get_pps_idx = bxt_power_sequencer_idx;
> else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario
2022-10-17 13:08 ` Jani Nikula
@ 2022-10-18 8:50 ` Manna, Animesh
0 siblings, 0 replies; 11+ messages in thread
From: Manna, Animesh @ 2022-10-18 8:50 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx
Thanks Jani for review.
Floated a new version after addressing the review comments in this series.
https://patchwork.freedesktop.org/series/109820/
Regards,
Animesh
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Monday, October 17, 2022 6:39 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Ville Syrjälä
> <ville.syrjala@linux.intel.com>; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario
>
> On Mon, 10 Oct 2022, Animesh Manna <animesh.manna@intel.com> wrote:
> > From display gen12 onwards to support dual EDP two instances of pps added.
> > Currently backlight controller and pps instance can be mapped together
> > for a specific panel. Currently dual PPS support is broken. This patch
> > fixes it and enables for display 12+.
> >
> > v1: Iniital revision.
> > v2: Called intel_bios_panel_init w/o PNPID before intel_pps_init.
> > [Jani]
> > v3: Set pps_id to -1 for pnpid type of panel which will be used by
> > bxt_power_sequencer_idx() to set 2nd pps instance as default for 2nd
> > EDP panel. [Jani]
> > v4: Early return for PANEL_TYPE_FALLBACK. [Jani]
> >
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++--
> > drivers/gpu/drm/i915/display/intel_bios.h | 2 +-
> > drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++---
> > drivers/gpu/drm/i915/display/intel_pps.c | 12 +++++++++++-
> > 5 files changed, 31 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index c2987f2c2b2e..dd3cd2ca815d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -3183,15 +3183,22 @@ void intel_bios_init(struct drm_i915_private
> *i915)
> > kfree(oprom_vbt);
> > }
> >
> > -void intel_bios_init_panel(struct drm_i915_private *i915,
> > +bool intel_bios_init_panel(struct drm_i915_private *i915,
> > struct intel_panel *panel,
> > const struct intel_bios_encoder_data *devdata,
> > const struct edid *edid)
> > {
> > init_vbt_panel_defaults(panel);
> > -
>
> Please don't do superfluous whitespace changes.
>
> > panel->vbt.panel_type = get_panel_type(i915, devdata, edid);
> >
> > + if (panel->vbt.panel_type == PANEL_TYPE_PNPID ||
> > + panel->vbt.panel_type == PANEL_TYPE_FALLBACK) {
> > + panel->vbt.edp.pps_id = -1;
> > +
> > + if (!edid && intel_bios_encoder_supports_edp(devdata))
> > + return true;
> > + }
> > +
>
> if (panel->vbt.panel_type == PANEL_TYPE_FALLBACK && !edid) {
> panel->vbt.backlight.controller = -1;
> return true;
> }
>
> > parse_panel_options(i915, panel);
> > parse_generic_dtd(i915, panel);
> > parse_lfp_data(i915, panel);
> > @@ -3203,6 +3210,8 @@ void intel_bios_init_panel(struct drm_i915_private
> *i915,
> > parse_psr(i915, panel);
> > parse_mipi_config(i915, panel);
> > parse_mipi_sequence(i915, panel);
> > +
> > + return false;
> > }
> >
> > /**
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.h
> > b/drivers/gpu/drm/i915/display/intel_bios.h
> > index e375405a7828..f8ef0274f3ee 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.h
> > @@ -232,7 +232,7 @@ struct mipi_pps_data { } __packed;
> >
> > void intel_bios_init(struct drm_i915_private *dev_priv); -void
> > intel_bios_init_panel(struct drm_i915_private *dev_priv,
> > +bool intel_bios_init_panel(struct drm_i915_private *dev_priv,
> > struct intel_panel *panel,
> > const struct intel_bios_encoder_data *devdata,
> > const struct edid *edid);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 44ab296c1f04..37e8309207bf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -307,6 +307,7 @@ struct intel_vbt_panel_data {
> > int preemphasis;
> > int vswing;
> > int bpp;
> > + int pps_id;
>
> Unnecessary.
>
> > struct edp_power_seq pps;
> > u8 drrs_msa_timing_delay;
> > bool low_vswing;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 70b06806ec0d..50d9223562e2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -5235,6 +5235,7 @@ static bool intel_edp_init_connector(struct intel_dp
> *intel_dp,
> > struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> > bool has_dpcd;
> > struct edid *edid;
> > + bool retry;
> >
> > if (!intel_dp_is_edp(intel_dp))
> > return true;
> > @@ -5254,6 +5255,9 @@ static bool intel_edp_init_connector(struct intel_dp
> *intel_dp,
> > return false;
> > }
> >
> > + retry = intel_bios_init_panel(dev_priv, &intel_connector->panel,
> > + encoder->devdata, NULL);
> > +
> > intel_pps_init(intel_dp);
> >
> > /* Cache DPCD and EDID for edp. */
> > @@ -5288,9 +5292,9 @@ static bool intel_edp_init_connector(struct intel_dp
> *intel_dp,
> > edid = ERR_PTR(-ENOENT);
> > }
> > intel_connector->edid = edid;
> > -
> > - intel_bios_init_panel(dev_priv, &intel_connector->panel,
> > - encoder->devdata, IS_ERR(edid) ? NULL : edid);
> > + if (retry)
> > + intel_bios_init_panel(dev_priv, &intel_connector->panel,
> > + encoder->devdata, IS_ERR(edid) ? NULL :
> edid);
> >
> > intel_panel_add_edid_fixed_modes(intel_connector, true);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
> > b/drivers/gpu/drm/i915/display/intel_pps.c
> > index b972fa6ec00d..da98b180639a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> > @@ -218,6 +218,16 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
> > /* We should never land here with regular DP ports */
> > drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
> >
> > + if (connector->panel.vbt.edp.pps_id == -1) {
>
> if (backlight_controller == -1)
> backlight_controller = connector->encoder->port == PORT_A ? 0 : 1;
>
> > + /*
> > + * Use 2nd PPS instance as default for 2nd EDP panel.
> > + */
> > + if (connector->encoder->port == PORT_A)
> > + return 0;
> > + else
> > + return 1;
> > + }
> > +
> > if (!intel_dp->pps.pps_reset)
> > return backlight_controller;
> >
> > @@ -1430,7 +1440,7 @@ void intel_pps_init(struct intel_dp *intel_dp)
> > intel_dp->pps.initializing = true;
> > INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work,
> > edp_panel_vdd_work);
> >
> > - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
> > + if (IS_GEMINILAKE(i915) || IS_BROXTON(i915) || DISPLAY_VER(i915) >=
> > +12)
> > intel_dp->get_pps_idx = bxt_power_sequencer_idx;
> > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> > intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
@ 2022-10-18 8:39 Animesh Manna
0 siblings, 0 replies; 11+ messages in thread
From: Animesh Manna @ 2022-10-18 8:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Simplified pps_get_register() which use get_pps_idx() hook to derive the
pps instance and get_pps_idx() will be initialized at pps_init().
v1: Initial version. Got r-b from Jani.
v2: Corrected unintentional change around memset() call. [Jani]
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_pps.c | 14 +++++++++-----
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e2b853e9e51d..44ab296c1f04 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1694,6 +1694,7 @@ struct intel_dp {
u8 (*preemph_max)(struct intel_dp *intel_dp);
u8 (*voltage_max)(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
+ int (*get_pps_idx)(struct intel_dp *intel_dp);
/* Displayport compliance testing */
struct intel_dp_compliance compliance;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 21944f5bf3a8..9ed62c891b8c 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -365,11 +365,8 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
int pps_idx = 0;
memset(regs, 0, sizeof(*regs));
-
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- pps_idx = bxt_power_sequencer_idx(intel_dp);
- else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- pps_idx = vlv_power_sequencer_pipe(intel_dp);
+ if (intel_dp->get_pps_idx)
+ pps_idx = intel_dp->get_pps_idx(intel_dp);
regs->pp_ctrl = PP_CONTROL(pps_idx);
regs->pp_stat = PP_STATUS(pps_idx);
@@ -1432,6 +1429,13 @@ void intel_pps_init(struct intel_dp *intel_dp)
intel_dp->pps.initializing = true;
INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
+ if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+ intel_dp->get_pps_idx = bxt_power_sequencer_idx;
+ else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
+ else
+ intel_dp->get_pps_idx = NULL;
+
pps_init_timestamps(intel_dp);
with_intel_pps_lock(intel_dp, wakeref) {
--
2.29.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
@ 2022-09-27 17:45 Animesh Manna
0 siblings, 0 replies; 11+ messages in thread
From: Animesh Manna @ 2022-09-27 17:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Simplified pps_get_register() which use get_pps_idx() hook to derive the
pps instance and get_pps_idx() will be initialized at pps_init().
v1: Initial version. Got r-b from Jani.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
.../gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_pps.c | 15 ++++++++++-----
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0da9b208d56e..b78b29951241 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1693,6 +1693,7 @@ struct intel_dp {
u8 (*preemph_max)(struct intel_dp *intel_dp);
u8 (*voltage_max)(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
+ int (*get_pps_idx)(struct intel_dp *intel_dp);
/* Displayport compliance testing */
struct intel_dp_compliance compliance;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 21944f5bf3a8..b972fa6ec00d 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -364,12 +364,10 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
int pps_idx = 0;
- memset(regs, 0, sizeof(*regs));
+ if (intel_dp->get_pps_idx)
+ pps_idx = intel_dp->get_pps_idx(intel_dp);
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- pps_idx = bxt_power_sequencer_idx(intel_dp);
- else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- pps_idx = vlv_power_sequencer_pipe(intel_dp);
+ memset(regs, 0, sizeof(*regs));
regs->pp_ctrl = PP_CONTROL(pps_idx);
regs->pp_stat = PP_STATUS(pps_idx);
@@ -1432,6 +1430,13 @@ void intel_pps_init(struct intel_dp *intel_dp)
intel_dp->pps.initializing = true;
INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
+ if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+ intel_dp->get_pps_idx = bxt_power_sequencer_idx;
+ else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
+ else
+ intel_dp->get_pps_idx = NULL;
+
pps_init_timestamps(intel_dp);
with_intel_pps_lock(intel_dp, wakeref) {
--
2.29.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup
@ 2022-09-16 8:31 Animesh Manna
0 siblings, 0 replies; 11+ messages in thread
From: Animesh Manna @ 2022-09-16 8:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Simplified pps_get_register() which use get_pps_idx() hook to derive the
pps instance and get_pps_idx() will be initialized at pps_init().
v1: Initial version. Got r-b from Jani.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
.../gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_pps.c | 15 ++++++++++-----
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0da9b208d56e..b78b29951241 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1693,6 +1693,7 @@ struct intel_dp {
u8 (*preemph_max)(struct intel_dp *intel_dp);
u8 (*voltage_max)(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
+ int (*get_pps_idx)(struct intel_dp *intel_dp);
/* Displayport compliance testing */
struct intel_dp_compliance compliance;
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 21944f5bf3a8..b972fa6ec00d 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -364,12 +364,10 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
int pps_idx = 0;
- memset(regs, 0, sizeof(*regs));
+ if (intel_dp->get_pps_idx)
+ pps_idx = intel_dp->get_pps_idx(intel_dp);
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- pps_idx = bxt_power_sequencer_idx(intel_dp);
- else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- pps_idx = vlv_power_sequencer_pipe(intel_dp);
+ memset(regs, 0, sizeof(*regs));
regs->pp_ctrl = PP_CONTROL(pps_idx);
regs->pp_stat = PP_STATUS(pps_idx);
@@ -1432,6 +1430,13 @@ void intel_pps_init(struct intel_dp *intel_dp)
intel_dp->pps.initializing = true;
INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
+ if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+ intel_dp->get_pps_idx = bxt_power_sequencer_idx;
+ else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ intel_dp->get_pps_idx = vlv_power_sequencer_pipe;
+ else
+ intel_dp->get_pps_idx = NULL;
+
pps_init_timestamps(intel_dp);
with_intel_pps_lock(intel_dp, wakeref) {
--
2.29.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2022-10-18 8:51 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
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2022-10-10 15:54 [Intel-gfx] [PATCH 1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Animesh Manna
2022-10-10 15:54 ` [Intel-gfx] [PATCH 2/2] drm/i915/pps: Enable 2nd pps for dual EDP scenario Animesh Manna
2022-10-17 13:08 ` Jani Nikula
2022-10-18 8:50 ` Manna, Animesh
2022-10-10 16:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part of pps_get_register() cleanup Patchwork
2022-10-10 16:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-10 21:56 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-10-17 12:20 ` [Intel-gfx] [PATCH 1/2] " Jani Nikula
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2022-10-18 8:39 Animesh Manna
2022-09-27 17:45 Animesh Manna
2022-09-16 8:31 Animesh Manna
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