From: Hal Feng <hal.feng@linux.starfivetech.com> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Linus Walleij <linus.walleij@linaro.org>, Emil Renner Berthing <kernel@esmil.dk>, Hal Feng <hal.feng@linux.starfivetech.com>, linux-kernel@vger.kernel.org Subject: [PATCH v1 06/30] soc: sifive: l2 cache: Add StarFive JH71x0 support Date: Thu, 29 Sep 2022 22:32:01 +0800 [thread overview] Message-ID: <20220929143225.17907-7-hal.feng@linux.starfivetech.com> (raw) In-Reply-To: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> From: Emil Renner Berthing <kernel@esmil.dk> This adds support for the StarFive JH7100 and JH7110 SoCs which also feature this SiFive cache controller. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com> --- arch/riscv/Kconfig.socs | 1 + drivers/soc/Makefile | 2 +- drivers/soc/sifive/Kconfig | 2 +- drivers/soc/sifive/sifive_l2_cache.c | 7 +++++++ 4 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 69774bb362d6..10f68a4359f9 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -22,6 +22,7 @@ config SOC_STARFIVE bool "StarFive SoCs" select PINCTRL select RESET_CONTROLLER + select SIFIVE_L2 select SIFIVE_PLIC help This enables support for StarFive SoC platform hardware. diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 69ba6508cf2c..534669840858 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -26,7 +26,7 @@ obj-y += qcom/ obj-y += renesas/ obj-y += rockchip/ obj-$(CONFIG_SOC_SAMSUNG) += samsung/ -obj-$(CONFIG_SOC_SIFIVE) += sifive/ +obj-y += sifive/ obj-y += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig index 58cf8c40d08d..776b30723c04 100644 --- a/drivers/soc/sifive/Kconfig +++ b/drivers/soc/sifive/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 -if SOC_SIFIVE +if SOC_SIFIVE || SOC_STARFIVE config SIFIVE_L2 bool "Sifive L2 Cache controller" diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c index 010d612f7420..d6637254977f 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_l2_cache.c @@ -10,6 +10,7 @@ #include <linux/io.h> #include <linux/mod_devicetable.h> #include <linux/platform_device.h> +#include <linux/property.h> #include <asm/cacheinfo.h> #include <soc/sifive/sifive_l2_cache.h> @@ -189,6 +190,7 @@ static irqreturn_t l2_int_handler(int irq, void *device) static int __init sifive_l2_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + unsigned long quirks = (uintptr_t)device_get_match_data(dev); int nirqs; int ret; int i; @@ -206,6 +208,9 @@ static int __init sifive_l2_probe(struct platform_device *pdev) if (g_irq[i] < 0) return g_irq[i]; + if (quirks & BIT(i)) + continue; + ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL); if (ret) return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]); @@ -225,6 +230,8 @@ static int __init sifive_l2_probe(struct platform_device *pdev) static const struct of_device_id sifive_l2_match[] = { { .compatible = "sifive,fu540-c000-ccache" }, { .compatible = "sifive,fu740-c000-ccache" }, + { .compatible = "starfive,jh7100-ccache", .data = (void *)BIT(DATA_UNCORR) }, + { .compatible = "starfive,jh7110-ccache" }, { /* sentinel */ } }; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Hal Feng <hal.feng@linux.starfivetech.com> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Linus Walleij <linus.walleij@linaro.org>, Emil Renner Berthing <kernel@esmil.dk>, Hal Feng <hal.feng@linux.starfivetech.com>, linux-kernel@vger.kernel.org Subject: [PATCH v1 06/30] soc: sifive: l2 cache: Add StarFive JH71x0 support Date: Thu, 29 Sep 2022 22:32:01 +0800 [thread overview] Message-ID: <20220929143225.17907-7-hal.feng@linux.starfivetech.com> (raw) In-Reply-To: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> From: Emil Renner Berthing <kernel@esmil.dk> This adds support for the StarFive JH7100 and JH7110 SoCs which also feature this SiFive cache controller. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com> --- arch/riscv/Kconfig.socs | 1 + drivers/soc/Makefile | 2 +- drivers/soc/sifive/Kconfig | 2 +- drivers/soc/sifive/sifive_l2_cache.c | 7 +++++++ 4 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 69774bb362d6..10f68a4359f9 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -22,6 +22,7 @@ config SOC_STARFIVE bool "StarFive SoCs" select PINCTRL select RESET_CONTROLLER + select SIFIVE_L2 select SIFIVE_PLIC help This enables support for StarFive SoC platform hardware. diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 69ba6508cf2c..534669840858 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -26,7 +26,7 @@ obj-y += qcom/ obj-y += renesas/ obj-y += rockchip/ obj-$(CONFIG_SOC_SAMSUNG) += samsung/ -obj-$(CONFIG_SOC_SIFIVE) += sifive/ +obj-y += sifive/ obj-y += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig index 58cf8c40d08d..776b30723c04 100644 --- a/drivers/soc/sifive/Kconfig +++ b/drivers/soc/sifive/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 -if SOC_SIFIVE +if SOC_SIFIVE || SOC_STARFIVE config SIFIVE_L2 bool "Sifive L2 Cache controller" diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c index 010d612f7420..d6637254977f 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_l2_cache.c @@ -10,6 +10,7 @@ #include <linux/io.h> #include <linux/mod_devicetable.h> #include <linux/platform_device.h> +#include <linux/property.h> #include <asm/cacheinfo.h> #include <soc/sifive/sifive_l2_cache.h> @@ -189,6 +190,7 @@ static irqreturn_t l2_int_handler(int irq, void *device) static int __init sifive_l2_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + unsigned long quirks = (uintptr_t)device_get_match_data(dev); int nirqs; int ret; int i; @@ -206,6 +208,9 @@ static int __init sifive_l2_probe(struct platform_device *pdev) if (g_irq[i] < 0) return g_irq[i]; + if (quirks & BIT(i)) + continue; + ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL); if (ret) return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]); @@ -225,6 +230,8 @@ static int __init sifive_l2_probe(struct platform_device *pdev) static const struct of_device_id sifive_l2_match[] = { { .compatible = "sifive,fu540-c000-ccache" }, { .compatible = "sifive,fu740-c000-ccache" }, + { .compatible = "starfive,jh7100-ccache", .data = (void *)BIT(DATA_UNCORR) }, + { .compatible = "starfive,jh7110-ccache" }, { /* sentinel */ } }; -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-09-29 15:51 UTC|newest] Thread overview: 210+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-09-29 14:31 [PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support Hal Feng 2022-09-29 14:31 ` Hal Feng 2022-09-29 14:31 ` [PATCH v1 01/30] dt-bindings: riscv: Add StarFive JH7110 bindings Hal Feng 2022-09-29 14:31 ` Hal Feng 2022-09-29 14:34 ` Krzysztof Kozlowski 2022-09-29 14:34 ` Krzysztof Kozlowski 2022-10-08 3:44 ` Hal Feng 2022-10-08 3:44 ` Hal Feng 2022-09-29 14:31 ` [PATCH v1 02/30] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng 2022-09-29 14:31 ` Hal Feng 2022-09-29 14:34 ` Krzysztof Kozlowski 2022-09-29 14:34 ` Krzysztof Kozlowski 2022-09-29 14:31 ` [PATCH v1 03/30] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng 2022-09-29 14:31 ` Hal Feng 2022-09-29 14:35 ` Krzysztof Kozlowski 2022-09-29 14:35 ` Krzysztof Kozlowski 2022-09-29 14:31 ` [PATCH v1 04/30] dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs Hal Feng 2022-09-29 14:31 ` Hal Feng 2022-09-29 14:36 ` Krzysztof Kozlowski 2022-09-29 14:36 ` Krzysztof Kozlowski 2022-09-29 15:33 ` Conor Dooley 2022-09-29 15:33 ` Conor Dooley 2022-10-03 9:26 ` Ben Dooks 2022-10-03 9:26 ` Ben Dooks 2022-10-08 18:54 ` Hal Feng 2022-10-08 18:54 ` Hal Feng 2022-09-29 14:32 ` [PATCH v1 05/30] soc: sifive: l2 cache: Convert to platform driver Hal Feng 2022-09-29 14:32 ` Hal Feng 2022-09-29 15:32 ` Conor Dooley 2022-09-29 15:32 ` Conor Dooley 2022-09-29 17:57 ` Ben Dooks 2022-09-29 17:57 ` Ben Dooks 2022-10-05 13:44 ` Emil Renner Berthing 2022-10-05 13:44 ` Emil Renner Berthing 2022-10-05 13:48 ` Ben Dooks 2022-10-05 13:48 ` Ben Dooks 2022-10-05 13:55 ` Emil Renner Berthing 2022-10-05 13:55 ` Emil Renner Berthing 2022-10-05 14:05 ` Conor Dooley 2022-10-05 14:05 ` Conor Dooley 2022-10-08 18:07 ` Hal Feng 2022-10-08 18:07 ` Hal Feng 2022-09-29 14:32 ` Hal Feng [this message] 2022-09-29 14:32 ` [PATCH v1 06/30] soc: sifive: l2 cache: Add StarFive JH71x0 support Hal Feng 2022-09-29 14:32 ` [PATCH v1 07/30] reset: starfive: jh7100: Use 32bit I/O on 32bit registers Hal Feng 2022-09-29 14:32 ` Hal Feng 2022-09-29 14:32 ` [PATCH v1 08/30] reset: starfive: jh7100: Use regmap APIs to operate registers Hal Feng 2022-09-29 14:32 ` Hal Feng 2022-09-29 14:32 ` [PATCH v1 09/30] reset: starfive: jh7100: Move necessary properties to device tree Hal Feng 2022-09-29 14:32 ` Hal Feng 2022-09-30 20:49 ` Rob Herring 2022-09-30 20:49 ` Rob Herring 2022-10-05 13:20 ` Emil Renner Berthing 2022-10-05 13:20 ` Emil Renner Berthing 2022-09-29 14:32 ` [PATCH v1 10/30] reset: starfive: Rename 'reset-starfive-jh7100.c' to 'reset-starfive.c' Hal Feng 2022-09-29 14:32 ` Hal Feng 2022-09-29 14:45 ` [PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support Krzysztof Kozlowski 2022-09-29 14:45 ` Krzysztof Kozlowski 2022-09-29 17:59 ` Conor Dooley 2022-09-29 17:59 ` Conor Dooley 2022-10-01 1:13 ` hal.feng 2022-10-01 1:13 ` hal.feng 2022-09-29 16:35 ` [PATCH v1 11/30] dt-bindings: reset: Add StarFive JH7110 reset definitions Hal Feng 2022-09-29 16:35 ` Hal Feng 2022-09-29 17:51 ` [PATCH v1 12/30] dt-bindings: reset: Add starfive,jh7110-reset bindings Hal Feng 2022-09-29 17:51 ` Hal Feng 2022-09-29 18:21 ` Rob Herring 2022-09-29 18:21 ` Rob Herring 2022-09-29 18:40 ` Rob Herring 2022-09-29 18:40 ` Rob Herring 2022-09-29 18:43 ` Rob Herring 2022-09-29 18:43 ` Rob Herring 2022-10-11 15:30 ` Hal Feng 2022-10-11 15:30 ` Hal Feng 2022-10-11 16:36 ` Krzysztof Kozlowski 2022-10-11 16:36 ` Krzysztof Kozlowski 2022-10-12 13:16 ` Hal Feng 2022-10-12 13:16 ` Hal Feng 2022-10-12 13:33 ` Krzysztof Kozlowski 2022-10-12 13:33 ` Krzysztof Kozlowski 2022-10-12 14:05 ` Conor Dooley 2022-10-12 14:05 ` Conor Dooley 2022-10-12 15:21 ` Hal Feng 2022-10-12 15:21 ` Hal Feng 2022-10-12 14:53 ` Hal Feng 2022-10-12 14:53 ` Hal Feng 2022-10-12 8:01 ` Emil Renner Berthing 2022-10-12 8:01 ` Emil Renner Berthing 2022-09-29 17:53 ` [PATCH v1 13/30] reset: starfive: Add StarFive JH7110 SoC support Hal Feng 2022-09-29 17:53 ` Hal Feng 2022-09-29 17:54 ` [PATCH v1 14/30] clk: starfive: Factor out common clock driver code Hal Feng 2022-09-29 17:54 ` Hal Feng 2022-09-30 21:43 ` Stephen Boyd 2022-09-30 21:43 ` Stephen Boyd 2022-09-29 17:56 ` [PATCH v1 15/30] clk: starfive: Use regmap APIs to operate registers Hal Feng 2022-09-29 17:56 ` Hal Feng 2022-09-30 21:48 ` Stephen Boyd 2022-09-30 21:48 ` Stephen Boyd 2022-10-05 13:14 ` Emil Renner Berthing 2022-10-05 13:14 ` Emil Renner Berthing 2022-10-12 23:05 ` Stephen Boyd 2022-10-12 23:05 ` Stephen Boyd 2022-10-23 4:11 ` Hal Feng 2022-10-23 4:11 ` Hal Feng 2022-10-23 10:25 ` Conor Dooley 2022-10-23 10:25 ` Conor Dooley 2022-10-28 3:16 ` Hal Feng 2022-10-28 3:16 ` Hal Feng 2022-10-27 1:26 ` Stephen Boyd 2022-10-27 1:26 ` Stephen Boyd 2022-10-28 2:46 ` Hal Feng 2022-10-28 2:46 ` Hal Feng 2022-09-29 17:56 ` [PATCH v1 16/30] dt-bindings: clock: Add StarFive JH7110 system clock definitions Hal Feng 2022-09-29 17:56 ` Hal Feng 2022-09-29 22:26 ` [PATCH v1 17/30] dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings Hal Feng 2022-09-29 22:26 ` Hal Feng 2022-09-30 1:55 ` Rob Herring 2022-09-30 1:55 ` Rob Herring 2022-09-30 10:58 ` Krzysztof Kozlowski 2022-09-30 10:58 ` Krzysztof Kozlowski 2022-10-11 17:52 ` Hal Feng 2022-10-11 17:52 ` Hal Feng 2022-09-30 1:50 ` [PATCH v1 18/30] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng 2022-09-30 1:50 ` Hal Feng 2022-09-30 5:49 ` [PATCH v1 19/30] dt-bindings: clock: Add StarFive JH7110 always-on definitions Hal Feng 2022-09-30 5:49 ` Hal Feng 2022-09-30 5:56 ` [PATCH v1 20/30] dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings Hal Feng 2022-09-30 5:56 ` Hal Feng 2022-09-30 10:59 ` Krzysztof Kozlowski 2022-09-30 10:59 ` Krzysztof Kozlowski 2022-10-11 18:01 ` Hal Feng 2022-10-11 18:01 ` Hal Feng 2022-09-30 12:51 ` Rob Herring 2022-09-30 12:51 ` Rob Herring 2022-09-30 6:03 ` [PATCH v1 21/30] clk: starfive: Add StarFive JH7110 always-on clock driver Hal Feng 2022-09-30 6:03 ` Hal Feng 2022-09-30 6:08 ` [PATCH v1 22/30] pinctrl: Create subdirectory for StarFive drivers Hal Feng 2022-09-30 6:08 ` Hal Feng 2022-10-04 8:43 ` Linus Walleij 2022-10-04 8:43 ` Linus Walleij 2022-09-30 6:14 ` [PATCH v1 23/30] pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100" Hal Feng 2022-09-30 6:14 ` Hal Feng 2022-09-30 21:28 ` Rob Herring 2022-09-30 21:28 ` Rob Herring 2022-10-04 8:48 ` Linus Walleij 2022-10-04 8:48 ` Linus Walleij 2022-10-04 8:58 ` Conor Dooley 2022-10-04 8:58 ` Conor Dooley 2022-10-04 9:13 ` Linus Walleij 2022-10-04 9:13 ` Linus Walleij 2022-10-04 9:21 ` Conor Dooley 2022-10-04 9:21 ` Conor Dooley 2022-10-04 9:24 ` Conor Dooley 2022-10-04 9:24 ` Conor Dooley 2022-10-06 9:07 ` Geert Uytterhoeven 2022-10-06 9:07 ` Geert Uytterhoeven 2022-09-30 7:33 ` [PATCH v1 24/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions Hal Feng 2022-09-30 7:33 ` Hal Feng 2022-09-30 11:00 ` Krzysztof Kozlowski 2022-09-30 11:00 ` Krzysztof Kozlowski 2022-09-30 7:38 ` [PATCH v1 25/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl bindings Hal Feng 2022-09-30 7:38 ` Hal Feng 2022-09-30 11:05 ` Krzysztof Kozlowski 2022-09-30 11:05 ` Krzysztof Kozlowski 2022-09-30 12:16 ` Rob Herring 2022-09-30 12:16 ` Rob Herring 2022-10-20 7:28 ` Icenowy Zheng 2022-10-20 7:28 ` Icenowy Zheng 2022-09-30 7:43 ` [PATCH v1 26/30] pinctrl: starfive: Add StarFive JH7110 driver Hal Feng 2022-09-30 7:43 ` Hal Feng 2022-10-01 14:35 ` kernel test robot 2022-10-01 14:35 ` kernel test robot 2022-10-04 8:56 ` Linus Walleij 2022-10-04 8:56 ` Linus Walleij 2022-10-05 13:31 ` Emil Renner Berthing 2022-10-05 13:31 ` Emil Renner Berthing 2022-10-14 2:05 ` Hal Feng 2022-10-14 2:05 ` Hal Feng 2022-09-30 7:49 ` [PATCH v1 27/30] RISC-V: Add initial StarFive JH7110 device tree Hal Feng 2022-09-30 7:49 ` Hal Feng 2022-10-01 10:52 ` Conor Dooley 2022-10-01 10:52 ` Conor Dooley 2022-10-03 7:45 ` Krzysztof Kozlowski 2022-10-03 7:45 ` Krzysztof Kozlowski 2022-10-14 9:41 ` Hal Feng 2022-10-14 9:41 ` Hal Feng 2022-09-30 7:53 ` [PATCH v1 28/30] RISC-V: Add StarFive JH7110 VisionFive2 board " Hal Feng 2022-09-30 7:53 ` Hal Feng 2022-10-01 11:14 ` Conor Dooley 2022-10-01 11:14 ` Conor Dooley 2022-10-29 8:18 ` Hal Feng 2022-10-29 8:18 ` Hal Feng 2022-09-30 9:06 ` [PATCH v1 29/30] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW Hal Feng 2022-09-30 9:06 ` Hal Feng 2022-09-30 20:54 ` Ben Dooks 2022-09-30 20:54 ` Ben Dooks 2022-09-30 21:41 ` Conor Dooley 2022-09-30 21:41 ` Conor Dooley 2022-10-14 3:24 ` Hal Feng 2022-10-14 3:24 ` Hal Feng 2022-09-30 12:23 ` [PATCH v1 30/30] RISC-V: Add StarFive JH7100 and JH7110 SoC Kconfig options Hal Feng 2022-09-30 12:23 ` Hal Feng 2022-09-30 12:37 ` Conor Dooley 2022-09-30 12:37 ` Conor Dooley 2022-10-11 18:32 ` Hal Feng 2022-10-11 18:32 ` Hal Feng 2022-10-05 13:05 ` [PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support Emil Renner Berthing 2022-10-05 13:05 ` Emil Renner Berthing 2022-10-08 3:18 ` Hal Feng 2022-10-08 3:18 ` Hal Feng
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