* [PATCH v2 0/3] Add driver nodes for MT8195 SoC @ 2022-10-20 11:19 ` Tinghan Shen 0 siblings, 0 replies; 12+ messages in thread From: Tinghan Shen @ 2022-10-20 11:19 UTC (permalink / raw) To: Ryder Lee, Jianjun Wang, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Matthias Brugger Cc: linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, Tinghan Shen Add pcie and venc nodes for MT8195 SoC. This series is based on linux-next/next-20221020. Depends on https://lore.kernel.org/all/20221001030752.14486-1-irui.wang@mediatek.com/ v1 -> v2: - remove 8195 example from pcie yaml - update reset-names of pcie yaml - add resets and reset-names to pcie node - rename venc node --- Jianjun Wang (1): dt-bindings: PCI: mediatek-gen3: Add iommu and power-domain support Tinghan Shen (2): arm64: dts: mt8195: Add pcie and pcie phy nodes arm64: dts: mt8195: Add venc node .../bindings/pci/mediatek-pcie-gen3.yaml | 16 +- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 174 ++++++++++++++++++ 2 files changed, 187 insertions(+), 3 deletions(-) -- 2.18.0 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 0/3] Add driver nodes for MT8195 SoC @ 2022-10-20 11:19 ` Tinghan Shen 0 siblings, 0 replies; 12+ messages in thread From: Tinghan Shen @ 2022-10-20 11:19 UTC (permalink / raw) To: Ryder Lee, Jianjun Wang, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Matthias Brugger Cc: linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, Tinghan Shen Add pcie and venc nodes for MT8195 SoC. This series is based on linux-next/next-20221020. Depends on https://lore.kernel.org/all/20221001030752.14486-1-irui.wang@mediatek.com/ v1 -> v2: - remove 8195 example from pcie yaml - update reset-names of pcie yaml - add resets and reset-names to pcie node - rename venc node --- Jianjun Wang (1): dt-bindings: PCI: mediatek-gen3: Add iommu and power-domain support Tinghan Shen (2): arm64: dts: mt8195: Add pcie and pcie phy nodes arm64: dts: mt8195: Add venc node .../bindings/pci/mediatek-pcie-gen3.yaml | 16 +- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 174 ++++++++++++++++++ 2 files changed, 187 insertions(+), 3 deletions(-) -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 1/3] dt-bindings: PCI: mediatek-gen3: Support mt8195 2022-10-20 11:19 ` Tinghan Shen @ 2022-10-20 11:19 ` Tinghan Shen -1 siblings, 0 replies; 12+ messages in thread From: Tinghan Shen @ 2022-10-20 11:19 UTC (permalink / raw) To: Ryder Lee, Jianjun Wang, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Matthias Brugger Cc: linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, TingHan Shen From: Jianjun Wang <jianjun.wang@mediatek.com> In order to support mt8195 pcie node, update the yaml to support new properties of iommu and power-domain, and update the reset-names property to allow only one 'mac' name. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Signed-off-by: TingHan Shen <tinghan.shen@mediatek.com> --- .../bindings/pci/mediatek-pcie-gen3.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index c00be39af64e..af271018b134 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -70,14 +70,21 @@ properties: minItems: 1 maxItems: 8 + iommu-map: + maxItems: 1 + + iommu-map-mask: + maxItems: 1 + resets: minItems: 1 maxItems: 2 reset-names: - minItems: 1 - items: - - const: phy + oneOf: + - items: + - const: phy + - const: mac - const: mac clocks: @@ -107,6 +114,9 @@ properties: items: - const: pcie-phy + power-domains: + maxItems: 1 + '#interrupt-cells': const: 1 -- 2.18.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 1/3] dt-bindings: PCI: mediatek-gen3: Support mt8195 @ 2022-10-20 11:19 ` Tinghan Shen 0 siblings, 0 replies; 12+ messages in thread From: Tinghan Shen @ 2022-10-20 11:19 UTC (permalink / raw) To: Ryder Lee, Jianjun Wang, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Matthias Brugger Cc: linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, TingHan Shen From: Jianjun Wang <jianjun.wang@mediatek.com> In order to support mt8195 pcie node, update the yaml to support new properties of iommu and power-domain, and update the reset-names property to allow only one 'mac' name. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Signed-off-by: TingHan Shen <tinghan.shen@mediatek.com> --- .../bindings/pci/mediatek-pcie-gen3.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index c00be39af64e..af271018b134 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -70,14 +70,21 @@ properties: minItems: 1 maxItems: 8 + iommu-map: + maxItems: 1 + + iommu-map-mask: + maxItems: 1 + resets: minItems: 1 maxItems: 2 reset-names: - minItems: 1 - items: - - const: phy + oneOf: + - items: + - const: phy + - const: mac - const: mac clocks: @@ -107,6 +114,9 @@ properties: items: - const: pcie-phy + power-domains: + maxItems: 1 + '#interrupt-cells': const: 1 -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: PCI: mediatek-gen3: Support mt8195 2022-10-20 11:19 ` Tinghan Shen @ 2022-10-21 2:26 ` Rob Herring -1 siblings, 0 replies; 12+ messages in thread From: Rob Herring @ 2022-10-21 2:26 UTC (permalink / raw) To: Tinghan Shen Cc: Ryder Lee, Jianjun Wang, Bjorn Helgaas, Krzysztof Kozlowski, Matthias Brugger, linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group On Thu, Oct 20, 2022 at 07:19:23PM +0800, Tinghan Shen wrote: > From: Jianjun Wang <jianjun.wang@mediatek.com> > > In order to support mt8195 pcie node, update the yaml to support new > properties of iommu and power-domain, and update the reset-names > property to allow only one 'mac' name. > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > Signed-off-by: TingHan Shen <tinghan.shen@mediatek.com> > --- > .../bindings/pci/mediatek-pcie-gen3.yaml | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > index c00be39af64e..af271018b134 100644 > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > @@ -70,14 +70,21 @@ properties: > minItems: 1 > maxItems: 8 > > + iommu-map: > + maxItems: 1 > + > + iommu-map-mask: > + maxItems: 1 This is not a array. It needs a value. Must be 0 if iommu-map only has 1 entry? Or you only support 1 downstream device? > + > resets: > minItems: 1 > maxItems: 2 > > reset-names: > - minItems: 1 > - items: > - - const: phy > + oneOf: > + - items: > + - const: phy > + - const: mac > - const: mac > > clocks: > @@ -107,6 +114,9 @@ properties: > items: > - const: pcie-phy > > + power-domains: > + maxItems: 1 > + > '#interrupt-cells': > const: 1 > > -- > 2.18.0 > > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: PCI: mediatek-gen3: Support mt8195 @ 2022-10-21 2:26 ` Rob Herring 0 siblings, 0 replies; 12+ messages in thread From: Rob Herring @ 2022-10-21 2:26 UTC (permalink / raw) To: Tinghan Shen Cc: Ryder Lee, Jianjun Wang, Bjorn Helgaas, Krzysztof Kozlowski, Matthias Brugger, linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group On Thu, Oct 20, 2022 at 07:19:23PM +0800, Tinghan Shen wrote: > From: Jianjun Wang <jianjun.wang@mediatek.com> > > In order to support mt8195 pcie node, update the yaml to support new > properties of iommu and power-domain, and update the reset-names > property to allow only one 'mac' name. > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > Signed-off-by: TingHan Shen <tinghan.shen@mediatek.com> > --- > .../bindings/pci/mediatek-pcie-gen3.yaml | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > index c00be39af64e..af271018b134 100644 > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > @@ -70,14 +70,21 @@ properties: > minItems: 1 > maxItems: 8 > > + iommu-map: > + maxItems: 1 > + > + iommu-map-mask: > + maxItems: 1 This is not a array. It needs a value. Must be 0 if iommu-map only has 1 entry? Or you only support 1 downstream device? > + > resets: > minItems: 1 > maxItems: 2 > > reset-names: > - minItems: 1 > - items: > - - const: phy > + oneOf: > + - items: > + - const: phy > + - const: mac > - const: mac > > clocks: > @@ -107,6 +114,9 @@ properties: > items: > - const: pcie-phy > > + power-domains: > + maxItems: 1 > + > '#interrupt-cells': > const: 1 > > -- > 2.18.0 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: PCI: mediatek-gen3: Support mt8195 2022-10-21 2:26 ` Rob Herring @ 2022-10-21 3:27 ` Jianjun Wang -1 siblings, 0 replies; 12+ messages in thread From: Jianjun Wang @ 2022-10-21 3:27 UTC (permalink / raw) To: Rob Herring, Tinghan Shen Cc: Ryder Lee, Bjorn Helgaas, Krzysztof Kozlowski, Matthias Brugger, linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group Hi Rob, Thanks for your review. On Thu, 2022-10-20 at 21:26 -0500, Rob Herring wrote: > On Thu, Oct 20, 2022 at 07:19:23PM +0800, Tinghan Shen wrote: > > From: Jianjun Wang <jianjun.wang@mediatek.com> > > > > In order to support mt8195 pcie node, update the yaml to support > > new > > properties of iommu and power-domain, and update the reset-names > > property to allow only one 'mac' name. > > > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > > Signed-off-by: TingHan Shen <tinghan.shen@mediatek.com> > > --- > > .../bindings/pci/mediatek-pcie-gen3.yaml | 16 > > +++++++++++++--- > > 1 file changed, 13 insertions(+), 3 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie- > > gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie- > > gen3.yaml > > index c00be39af64e..af271018b134 100644 > > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > @@ -70,14 +70,21 @@ properties: > > minItems: 1 > > maxItems: 8 > > > > + iommu-map: > > + maxItems: 1 > > + > > + iommu-map-mask: > > + maxItems: 1 > > This is not a array. It needs a value. Must be 0 if iommu-map only > has 1 > entry? Or you only support 1 downstream device? We only has 1 entry for iommu-map, we'll change it to 0 in the next version. Thanks. > > > + > > resets: > > minItems: 1 > > maxItems: 2 > > > > reset-names: > > - minItems: 1 > > - items: > > - - const: phy > > + oneOf: > > + - items: > > + - const: phy > > + - const: mac > > - const: mac > > > > clocks: > > @@ -107,6 +114,9 @@ properties: > > items: > > - const: pcie-phy > > > > + power-domains: > > + maxItems: 1 > > + > > '#interrupt-cells': > > const: 1 > > > > -- > > 2.18.0 > > > > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: PCI: mediatek-gen3: Support mt8195 @ 2022-10-21 3:27 ` Jianjun Wang 0 siblings, 0 replies; 12+ messages in thread From: Jianjun Wang @ 2022-10-21 3:27 UTC (permalink / raw) To: Rob Herring, Tinghan Shen Cc: Ryder Lee, Bjorn Helgaas, Krzysztof Kozlowski, Matthias Brugger, linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group Hi Rob, Thanks for your review. On Thu, 2022-10-20 at 21:26 -0500, Rob Herring wrote: > On Thu, Oct 20, 2022 at 07:19:23PM +0800, Tinghan Shen wrote: > > From: Jianjun Wang <jianjun.wang@mediatek.com> > > > > In order to support mt8195 pcie node, update the yaml to support > > new > > properties of iommu and power-domain, and update the reset-names > > property to allow only one 'mac' name. > > > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > > Signed-off-by: TingHan Shen <tinghan.shen@mediatek.com> > > --- > > .../bindings/pci/mediatek-pcie-gen3.yaml | 16 > > +++++++++++++--- > > 1 file changed, 13 insertions(+), 3 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie- > > gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie- > > gen3.yaml > > index c00be39af64e..af271018b134 100644 > > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > @@ -70,14 +70,21 @@ properties: > > minItems: 1 > > maxItems: 8 > > > > + iommu-map: > > + maxItems: 1 > > + > > + iommu-map-mask: > > + maxItems: 1 > > This is not a array. It needs a value. Must be 0 if iommu-map only > has 1 > entry? Or you only support 1 downstream device? We only has 1 entry for iommu-map, we'll change it to 0 in the next version. Thanks. > > > + > > resets: > > minItems: 1 > > maxItems: 2 > > > > reset-names: > > - minItems: 1 > > - items: > > - - const: phy > > + oneOf: > > + - items: > > + - const: phy > > + - const: mac > > - const: mac > > > > clocks: > > @@ -107,6 +114,9 @@ properties: > > items: > > - const: pcie-phy > > > > + power-domains: > > + maxItems: 1 > > + > > '#interrupt-cells': > > const: 1 > > > > -- > > 2.18.0 > > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 2/3] arm64: dts: mt8195: Add pcie and pcie phy nodes 2022-10-20 11:19 ` Tinghan Shen @ 2022-10-20 11:19 ` Tinghan Shen -1 siblings, 0 replies; 12+ messages in thread From: Tinghan Shen @ 2022-10-20 11:19 UTC (permalink / raw) To: Ryder Lee, Jianjun Wang, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Matthias Brugger Cc: linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, Tinghan Shen Add pcie and pcie phy nodes for mt8195. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 150 +++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index d03f0c2b8233..2128fa007480 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/phy/phy.h> #include <dt-bindings/pinctrl/mt8195-pinfunc.h> #include <dt-bindings/power/mt8195-power.h> +#include <dt-bindings/reset/mt8195-resets.h> / { compatible = "mediatek,mt8195"; @@ -1182,6 +1183,110 @@ status = "disabled"; }; + pcie0: pcie@112f0000 { + compatible = "mediatek,mt8195-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x112f0000 0 0x4000>; + reg-names = "pcie-mac"; + interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x20000000 + 0x0 0x20000000 0 0x200000>, + <0x82000000 0 0x20200000 + 0x0 0x20200000 0 0x3e00000>; + + iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; + iommu-map-mask = <0x0>; + + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + clock-names = "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + assigned-clocks = <&topckgen CLK_TOP_TL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; + + phys = <&pciephy>; + phy-names = "pcie-phy"; + + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; + + resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; + reset-names = "mac"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + status = "disabled"; + + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@112f8000 { + compatible = "mediatek,mt8195-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x112f8000 0 0x4000>; + reg-names = "pcie-mac"; + interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x24000000 + 0x0 0x24000000 0 0x200000>, + <0x82000000 0 0x24200000 + 0x0 0x24200000 0 0x3e00000>; + + iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; + iommu-map-mask = <0x0>; + + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + /* Designer has connect pcie1 with peri_mem_p0 clock */ + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + clock-names = "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + assigned-clocks = <&topckgen CLK_TOP_TL_P1>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; + + phys = <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; + + resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; + reset-names = "mac"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + status = "disabled"; + + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + nor_flash: spi@1132c000 { compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor"; @@ -1241,6 +1346,34 @@ reg = <0x189 0x2>; bits = <7 5>; }; + pciephy_rx_ln1: pciephy-rx-ln1@190 { + reg = <0x190 0x1>; + bits = <0 4>; + }; + pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190 { + reg = <0x190 0x1>; + bits = <4 4>; + }; + pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191 { + reg = <0x191 0x1>; + bits = <0 4>; + }; + pciephy_rx_ln0: pciephy-rx-ln0@191 { + reg = <0x191 0x1>; + bits = <4 4>; + }; + pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { + reg = <0x192 0x1>; + bits = <0 4>; + }; + pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { + reg = <0x192 0x1>; + bits = <4 4>; + }; + pciephy_glb_intr: pciephy-glb-intr@193 { + reg = <0x193 0x1>; + bits = <0 4>; + }; }; u3phy2: t-phy@11c40000 { @@ -1461,6 +1594,23 @@ }; }; + pciephy: phy@11e80000 { + compatible = "mediatek,mt8195-pcie-phy"; + reg = <0 0x11e80000 0 0x10000>; + reg-names = "sif"; + nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, + <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, + <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, + <&pciephy_rx_ln1>; + nvmem-cell-names = "glb_intr", "tx_ln0_pmos", + "tx_ln0_nmos", "rx_ln0", + "tx_ln1_pmos", "tx_ln1_nmos", + "rx_ln1"; + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; + #phy-cells = <0>; + status = "disabled"; + }; + ufsphy: ufs-phy@11fa0000 { compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; reg = <0 0x11fa0000 0 0xc000>; -- 2.18.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 2/3] arm64: dts: mt8195: Add pcie and pcie phy nodes @ 2022-10-20 11:19 ` Tinghan Shen 0 siblings, 0 replies; 12+ messages in thread From: Tinghan Shen @ 2022-10-20 11:19 UTC (permalink / raw) To: Ryder Lee, Jianjun Wang, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Matthias Brugger Cc: linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, Tinghan Shen Add pcie and pcie phy nodes for mt8195. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 150 +++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index d03f0c2b8233..2128fa007480 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/phy/phy.h> #include <dt-bindings/pinctrl/mt8195-pinfunc.h> #include <dt-bindings/power/mt8195-power.h> +#include <dt-bindings/reset/mt8195-resets.h> / { compatible = "mediatek,mt8195"; @@ -1182,6 +1183,110 @@ status = "disabled"; }; + pcie0: pcie@112f0000 { + compatible = "mediatek,mt8195-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x112f0000 0 0x4000>; + reg-names = "pcie-mac"; + interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x20000000 + 0x0 0x20000000 0 0x200000>, + <0x82000000 0 0x20200000 + 0x0 0x20200000 0 0x3e00000>; + + iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; + iommu-map-mask = <0x0>; + + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + clock-names = "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + assigned-clocks = <&topckgen CLK_TOP_TL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; + + phys = <&pciephy>; + phy-names = "pcie-phy"; + + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; + + resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; + reset-names = "mac"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + status = "disabled"; + + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@112f8000 { + compatible = "mediatek,mt8195-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x112f8000 0 0x4000>; + reg-names = "pcie-mac"; + interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x24000000 + 0x0 0x24000000 0 0x200000>, + <0x82000000 0 0x24200000 + 0x0 0x24200000 0 0x3e00000>; + + iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; + iommu-map-mask = <0x0>; + + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + /* Designer has connect pcie1 with peri_mem_p0 clock */ + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + clock-names = "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + assigned-clocks = <&topckgen CLK_TOP_TL_P1>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; + + phys = <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; + + resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; + reset-names = "mac"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + status = "disabled"; + + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + nor_flash: spi@1132c000 { compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor"; @@ -1241,6 +1346,34 @@ reg = <0x189 0x2>; bits = <7 5>; }; + pciephy_rx_ln1: pciephy-rx-ln1@190 { + reg = <0x190 0x1>; + bits = <0 4>; + }; + pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190 { + reg = <0x190 0x1>; + bits = <4 4>; + }; + pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191 { + reg = <0x191 0x1>; + bits = <0 4>; + }; + pciephy_rx_ln0: pciephy-rx-ln0@191 { + reg = <0x191 0x1>; + bits = <4 4>; + }; + pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { + reg = <0x192 0x1>; + bits = <0 4>; + }; + pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { + reg = <0x192 0x1>; + bits = <4 4>; + }; + pciephy_glb_intr: pciephy-glb-intr@193 { + reg = <0x193 0x1>; + bits = <0 4>; + }; }; u3phy2: t-phy@11c40000 { @@ -1461,6 +1594,23 @@ }; }; + pciephy: phy@11e80000 { + compatible = "mediatek,mt8195-pcie-phy"; + reg = <0 0x11e80000 0 0x10000>; + reg-names = "sif"; + nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, + <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, + <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, + <&pciephy_rx_ln1>; + nvmem-cell-names = "glb_intr", "tx_ln0_pmos", + "tx_ln0_nmos", "rx_ln0", + "tx_ln1_pmos", "tx_ln1_nmos", + "rx_ln1"; + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; + #phy-cells = <0>; + status = "disabled"; + }; + ufsphy: ufs-phy@11fa0000 { compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; reg = <0 0x11fa0000 0 0xc000>; -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 3/3] arm64: dts: mt8195: Add venc node 2022-10-20 11:19 ` Tinghan Shen @ 2022-10-20 11:19 ` Tinghan Shen -1 siblings, 0 replies; 12+ messages in thread From: Tinghan Shen @ 2022-10-20 11:19 UTC (permalink / raw) To: Ryder Lee, Jianjun Wang, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Matthias Brugger Cc: linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, Tinghan Shen, Irui Wang Add venc node for mt8195 SoC. Signed-off-by: Irui Wang <irui.wang@mediatek.com> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 2128fa007480..0779666c187c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2170,6 +2170,30 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; }; + venc: video-codec@1a020000 { + compatible = "mediatek,mt8195-vcodec-enc"; + reg = <0 0x1a020000 0 0x10000>; + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, + <&iommu_vdo M4U_PORT_L19_VENC_REC>, + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,scp = <&scp>; + clocks = <&vencsys CLK_VENC_VENC>; + clock-names = "venc_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + }; + vencsys_core1: clock-controller@1b000000 { compatible = "mediatek,mt8195-vencsys_core1"; reg = <0 0x1b000000 0 0x1000>; -- 2.18.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 3/3] arm64: dts: mt8195: Add venc node @ 2022-10-20 11:19 ` Tinghan Shen 0 siblings, 0 replies; 12+ messages in thread From: Tinghan Shen @ 2022-10-20 11:19 UTC (permalink / raw) To: Ryder Lee, Jianjun Wang, Bjorn Helgaas, Rob Herring, Krzysztof Kozlowski, Matthias Brugger Cc: linux-pci, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, Tinghan Shen, Irui Wang Add venc node for mt8195 SoC. Signed-off-by: Irui Wang <irui.wang@mediatek.com> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 2128fa007480..0779666c187c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2170,6 +2170,30 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; }; + venc: video-codec@1a020000 { + compatible = "mediatek,mt8195-vcodec-enc"; + reg = <0 0x1a020000 0 0x10000>; + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, + <&iommu_vdo M4U_PORT_L19_VENC_REC>, + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,scp = <&scp>; + clocks = <&vencsys CLK_VENC_VENC>; + clock-names = "venc_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + }; + vencsys_core1: clock-controller@1b000000 { compatible = "mediatek,mt8195-vencsys_core1"; reg = <0 0x1b000000 0 0x1000>; -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-10-21 3:29 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-10-20 11:19 [PATCH v2 0/3] Add driver nodes for MT8195 SoC Tinghan Shen 2022-10-20 11:19 ` Tinghan Shen 2022-10-20 11:19 ` [PATCH v2 1/3] dt-bindings: PCI: mediatek-gen3: Support mt8195 Tinghan Shen 2022-10-20 11:19 ` Tinghan Shen 2022-10-21 2:26 ` Rob Herring 2022-10-21 2:26 ` Rob Herring 2022-10-21 3:27 ` Jianjun Wang 2022-10-21 3:27 ` Jianjun Wang 2022-10-20 11:19 ` [PATCH v2 2/3] arm64: dts: mt8195: Add pcie and pcie phy nodes Tinghan Shen 2022-10-20 11:19 ` Tinghan Shen 2022-10-20 11:19 ` [PATCH v2 3/3] arm64: dts: mt8195: Add venc node Tinghan Shen 2022-10-20 11:19 ` Tinghan Shen
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