* [PATCH 00/26] target/s390x: pc-relative translation blocks
@ 2022-10-06 3:43 Richard Henderson
2022-10-06 3:43 ` [PATCH 01/26] target/s390x: Use tcg_constant_* in local contexts Richard Henderson
` (26 more replies)
0 siblings, 27 replies; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:43 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
This is the S390 specific changes required to reduce the
amount of translation for address space randomization.
Begin with some generic cleanups, then prepare by using
displacements instead of addresses when possible, then
add some tcg infrastructure to avoid a code gen ugly,
then finalize the conversion.
r~
Richard Henderson (26):
target/s390x: Use tcg_constant_* in local contexts
target/s390x: Use tcg_constant_* for DisasCompare
target/s390x: Use tcg_constant_i32 for fpinst_extract_m34
target/s390x: Use tcg_constant_* in translate_vx.c.inc
target/s390x: Change help_goto_direct to work on displacements
target/s390x: Introduce gen_psw_addr_disp
target/s390x: Remove pc argument to pc_to_link_into
target/s390x: Use gen_psw_addr_disp in pc_to_link_info
target/s390x: Use gen_psw_addr_disp in save_link_info
target/s390x: Use gen_psw_addr_disp in op_sam
target/s390x: Use ilen instead in branches
target/s390x: Move masking of psw.addr to cpu_get_tb_cpu_state
target/s390x: Add disp argument to update_psw_addr
target/s390x: Don't set gbea for user-only
target/s390x: Introduce per_enabled
target/s390x: Disable conditional branch-to-next for PER
target/s390x: Introduce help_goto_indirect
target/s390x: Split per_branch
target/s390x: Simplify help_branch
target/s390x: Split per_breaking_event from per_branch_*
target/s390x: Remove PER check from use_goto_tb
target/s390x: Pass original r2 register to BCR
tcg: Pass TCGTempKind to tcg_temp_new_internal
tcg: Introduce tcg_temp_ebb_new_*
tcg: Introduce tcg_temp_is_normal_*
target/s390x: Enable TARGET_TB_PCREL
include/tcg/tcg-op.h | 4 +
include/tcg/tcg.h | 49 +-
target/s390x/cpu-param.h | 1 +
target/s390x/cpu.h | 13 +-
target/s390x/cpu.c | 12 +
target/s390x/tcg/translate.c | 858 ++++++++++++----------------
tcg/tcg.c | 14 +-
target/s390x/tcg/translate_vx.c.inc | 45 +-
target/s390x/tcg/insn-data.def | 2 +-
9 files changed, 461 insertions(+), 537 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 63+ messages in thread
* [PATCH 01/26] target/s390x: Use tcg_constant_* in local contexts
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
@ 2022-10-06 3:43 ` Richard Henderson
2022-11-03 10:38 ` Ilya Leoshkevich
2022-10-06 3:43 ` [PATCH 02/26] target/s390x: Use tcg_constant_* for DisasCompare Richard Henderson
` (25 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:43 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x, Philippe Mathieu-Daudé
Replace tcg_const_* with tcg_constant_* in contexts
where the free to remove is nearby.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 408 +++++++++++++----------------------
1 file changed, 145 insertions(+), 263 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 1d2dddab1c..890d1f1db3 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -171,8 +171,6 @@ static uint64_t inline_branch_miss[CC_OP_MAX];
static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc)
{
- TCGv_i64 tmp;
-
if (s->base.tb->flags & FLAG_MASK_32) {
if (s->base.tb->flags & FLAG_MASK_64) {
tcg_gen_movi_i64(out, pc);
@@ -181,9 +179,7 @@ static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc)
pc |= 0x80000000;
}
assert(!(s->base.tb->flags & FLAG_MASK_64));
- tmp = tcg_const_i64(pc);
- tcg_gen_deposit_i64(out, out, tmp, 0, 32);
- tcg_temp_free_i64(tmp);
+ tcg_gen_deposit_i64(out, out, tcg_constant_i64(pc), 0, 32);
}
static TCGv_i64 psw_addr;
@@ -348,11 +344,8 @@ static void per_branch(DisasContext *s, bool to_next)
tcg_gen_movi_i64(gbea, s->base.pc_next);
if (s->base.tb->flags & FLAG_MASK_PER) {
- TCGv_i64 next_pc = to_next ? tcg_const_i64(s->pc_tmp) : psw_addr;
+ TCGv_i64 next_pc = to_next ? tcg_constant_i64(s->pc_tmp) : psw_addr;
gen_helper_per_branch(cpu_env, gbea, next_pc);
- if (to_next) {
- tcg_temp_free_i64(next_pc);
- }
}
#endif
}
@@ -370,9 +363,8 @@ static void per_branch_cond(DisasContext *s, TCGCond cond,
gen_set_label(lab);
} else {
- TCGv_i64 pc = tcg_const_i64(s->base.pc_next);
+ TCGv_i64 pc = tcg_constant_i64(s->base.pc_next);
tcg_gen_movcond_i64(cond, gbea, arg1, arg2, gbea, pc);
- tcg_temp_free_i64(pc);
}
#endif
}
@@ -426,23 +418,17 @@ static int get_mem_index(DisasContext *s)
static void gen_exception(int excp)
{
- TCGv_i32 tmp = tcg_const_i32(excp);
- gen_helper_exception(cpu_env, tmp);
- tcg_temp_free_i32(tmp);
+ gen_helper_exception(cpu_env, tcg_constant_i32(excp));
}
static void gen_program_exception(DisasContext *s, int code)
{
- TCGv_i32 tmp;
-
/* Remember what pgm exeption this was. */
- tmp = tcg_const_i32(code);
- tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
- tcg_temp_free_i32(tmp);
+ tcg_gen_st_i32(tcg_constant_i32(code), cpu_env,
+ offsetof(CPUS390XState, int_pgm_code));
- tmp = tcg_const_i32(s->ilen);
- tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen));
- tcg_temp_free_i32(tmp);
+ tcg_gen_st_i32(tcg_constant_i32(s->ilen), cpu_env,
+ offsetof(CPUS390XState, int_pgm_ilen));
/* update the psw */
update_psw_addr(s);
@@ -461,9 +447,7 @@ static inline void gen_illegal_opcode(DisasContext *s)
static inline void gen_data_exception(uint8_t dxc)
{
- TCGv_i32 tmp = tcg_const_i32(dxc);
- gen_helper_data_exception(cpu_env, tmp);
- tcg_temp_free_i32(tmp);
+ gen_helper_data_exception(cpu_env, tcg_constant_i32(dxc));
}
static inline void gen_trap(DisasContext *s)
@@ -584,13 +568,13 @@ static void gen_op_calc_cc(DisasContext *s)
switch (s->cc_op) {
default:
- dummy = tcg_const_i64(0);
+ dummy = tcg_constant_i64(0);
/* FALLTHRU */
case CC_OP_ADD_64:
case CC_OP_SUB_64:
case CC_OP_ADD_32:
case CC_OP_SUB_32:
- local_cc_op = tcg_const_i32(s->cc_op);
+ local_cc_op = tcg_constant_i32(s->cc_op);
break;
case CC_OP_CONST0:
case CC_OP_CONST1:
@@ -660,13 +644,6 @@ static void gen_op_calc_cc(DisasContext *s)
tcg_abort();
}
- if (local_cc_op) {
- tcg_temp_free_i32(local_cc_op);
- }
- if (dummy) {
- tcg_temp_free_i64(dummy);
- }
-
/* We now have cc in cc_op as constant */
set_cc_static(s);
}
@@ -1284,9 +1261,9 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
Most commonly we're single-stepping or some other condition that
disables all use of goto_tb. Just update the PC and exit. */
- TCGv_i64 next = tcg_const_i64(s->pc_tmp);
+ TCGv_i64 next = tcg_constant_i64(s->pc_tmp);
if (is_imm) {
- cdest = tcg_const_i64(dest);
+ cdest = tcg_constant_i64(dest);
}
if (c->is_64) {
@@ -1296,21 +1273,15 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
} else {
TCGv_i32 t0 = tcg_temp_new_i32();
TCGv_i64 t1 = tcg_temp_new_i64();
- TCGv_i64 z = tcg_const_i64(0);
+ TCGv_i64 z = tcg_constant_i64(0);
tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
tcg_gen_extu_i32_i64(t1, t0);
tcg_temp_free_i32(t0);
tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
per_branch_cond(s, TCG_COND_NE, t1, z);
tcg_temp_free_i64(t1);
- tcg_temp_free_i64(z);
}
- if (is_imm) {
- tcg_temp_free_i64(cdest);
- }
- tcg_temp_free_i64(next);
-
ret = DISAS_PC_UPDATED;
}
@@ -1394,10 +1365,9 @@ static DisasJumpType op_addc64(DisasContext *s, DisasOps *o)
{
compute_carry(s);
- TCGv_i64 zero = tcg_const_i64(0);
+ TCGv_i64 zero = tcg_constant_i64(0);
tcg_gen_add2_i64(o->out, cc_src, o->in1, zero, cc_src, zero);
tcg_gen_add2_i64(o->out, cc_src, o->out, cc_src, o->in2, zero);
- tcg_temp_free_i64(zero);
return DISAS_NEXT;
}
@@ -2077,9 +2047,8 @@ static DisasJumpType op_clc(DisasContext *s, DisasOps *o)
tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
break;
default:
- vl = tcg_const_i32(l);
+ vl = tcg_constant_i32(l);
gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
- tcg_temp_free_i32(vl);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -2099,11 +2068,9 @@ static DisasJumpType op_clcl(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
- t1 = tcg_const_i32(r1);
- t2 = tcg_const_i32(r2);
+ t1 = tcg_constant_i32(r1);
+ t2 = tcg_constant_i32(r2);
gen_helper_clcl(cc_op, cpu_env, t1, t2);
- tcg_temp_free_i32(t1);
- tcg_temp_free_i32(t2);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -2120,11 +2087,9 @@ static DisasJumpType op_clcle(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
- t1 = tcg_const_i32(r1);
- t3 = tcg_const_i32(r3);
+ t1 = tcg_constant_i32(r1);
+ t3 = tcg_constant_i32(r3);
gen_helper_clcle(cc_op, cpu_env, t1, o->in2, t3);
- tcg_temp_free_i32(t1);
- tcg_temp_free_i32(t3);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -2141,24 +2106,22 @@ static DisasJumpType op_clclu(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
- t1 = tcg_const_i32(r1);
- t3 = tcg_const_i32(r3);
+ t1 = tcg_constant_i32(r1);
+ t3 = tcg_constant_i32(r3);
gen_helper_clclu(cc_op, cpu_env, t1, o->in2, t3);
- tcg_temp_free_i32(t1);
- tcg_temp_free_i32(t3);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_clm(DisasContext *s, DisasOps *o)
{
- TCGv_i32 m3 = tcg_const_i32(get_field(s, m3));
+ TCGv_i32 m3 = tcg_constant_i32(get_field(s, m3));
TCGv_i32 t1 = tcg_temp_new_i32();
+
tcg_gen_extrl_i64_i32(t1, o->in1);
gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
set_cc_static(s);
tcg_temp_free_i32(t1);
- tcg_temp_free_i32(m3);
return DISAS_NEXT;
}
@@ -2217,8 +2180,8 @@ static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o)
/* Note that R1:R1+1 = expected value and R3:R3+1 = new value. */
addr = get_address(s, 0, b2, d2);
- t_r1 = tcg_const_i32(r1);
- t_r3 = tcg_const_i32(r3);
+ t_r1 = tcg_constant_i32(r1);
+ t_r3 = tcg_constant_i32(r3);
if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
gen_helper_cdsg(cpu_env, addr, t_r1, t_r3);
} else if (HAVE_CMPXCHG128) {
@@ -2228,8 +2191,6 @@ static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o)
ret = DISAS_NORETURN;
}
tcg_temp_free_i64(addr);
- tcg_temp_free_i32(t_r1);
- tcg_temp_free_i32(t_r3);
set_cc_static(s);
return ret;
@@ -2238,14 +2199,13 @@ static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o)
static DisasJumpType op_csst(DisasContext *s, DisasOps *o)
{
int r3 = get_field(s, r3);
- TCGv_i32 t_r3 = tcg_const_i32(r3);
+ TCGv_i32 t_r3 = tcg_constant_i32(r3);
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_csst_parallel(cc_op, cpu_env, t_r3, o->addr1, o->in2);
} else {
gen_helper_csst(cc_op, cpu_env, t_r3, o->addr1, o->in2);
}
- tcg_temp_free_i32(t_r3);
set_cc_static(s);
return DISAS_NEXT;
@@ -2343,9 +2303,9 @@ static DisasJumpType op_cuXX(DisasContext *s, DisasOps *o)
m3 = 0;
}
- tr1 = tcg_const_i32(r1);
- tr2 = tcg_const_i32(r2);
- chk = tcg_const_i32(m3);
+ tr1 = tcg_constant_i32(r1);
+ tr2 = tcg_constant_i32(r2);
+ chk = tcg_constant_i32(m3);
switch (s->insn->data) {
case 12:
@@ -2370,9 +2330,6 @@ static DisasJumpType op_cuXX(DisasContext *s, DisasOps *o)
g_assert_not_reached();
}
- tcg_temp_free_i32(tr1);
- tcg_temp_free_i32(tr2);
- tcg_temp_free_i32(chk);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -2380,15 +2337,11 @@ static DisasJumpType op_cuXX(DisasContext *s, DisasOps *o)
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_diag(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
- TCGv_i32 func_code = tcg_const_i32(get_field(s, i2));
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
+ TCGv_i32 func_code = tcg_constant_i32(get_field(s, i2));
gen_helper_diag(cpu_env, r1, r3, func_code);
-
- tcg_temp_free_i32(func_code);
- tcg_temp_free_i32(r3);
- tcg_temp_free_i32(r1);
return DISAS_NEXT;
}
#endif
@@ -2494,18 +2447,13 @@ static DisasJumpType op_ex(DisasContext *s, DisasOps *o)
update_cc_op(s);
if (r1 == 0) {
- v1 = tcg_const_i64(0);
+ v1 = tcg_constant_i64(0);
} else {
v1 = regs[r1];
}
- ilen = tcg_const_i32(s->ilen);
+ ilen = tcg_constant_i32(s->ilen);
gen_helper_ex(cpu_env, ilen, v1, o->in2);
- tcg_temp_free_i32(ilen);
-
- if (r1 == 0) {
- tcg_temp_free_i64(v1);
- }
return DISAS_PC_CC_UPDATED;
}
@@ -2657,12 +2605,11 @@ static DisasJumpType op_idte(DisasContext *s, DisasOps *o)
TCGv_i32 m4;
if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) {
- m4 = tcg_const_i32(get_field(s, m4));
+ m4 = tcg_constant_i32(get_field(s, m4));
} else {
- m4 = tcg_const_i32(0);
+ m4 = tcg_constant_i32(0);
}
gen_helper_idte(cpu_env, o->in1, o->in2, m4);
- tcg_temp_free_i32(m4);
return DISAS_NEXT;
}
@@ -2671,12 +2618,11 @@ static DisasJumpType op_ipte(DisasContext *s, DisasOps *o)
TCGv_i32 m4;
if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) {
- m4 = tcg_const_i32(get_field(s, m4));
+ m4 = tcg_constant_i32(get_field(s, m4));
} else {
- m4 = tcg_const_i32(0);
+ m4 = tcg_constant_i32(0);
}
gen_helper_ipte(cpu_env, o->in1, o->in2, m4);
- tcg_temp_free_i32(m4);
return DISAS_NEXT;
}
@@ -2732,16 +2678,12 @@ static DisasJumpType op_msa(DisasContext *s, DisasOps *o)
g_assert_not_reached();
};
- t_r1 = tcg_const_i32(r1);
- t_r2 = tcg_const_i32(r2);
- t_r3 = tcg_const_i32(r3);
- type = tcg_const_i32(s->insn->data);
+ t_r1 = tcg_constant_i32(r1);
+ t_r2 = tcg_constant_i32(r2);
+ t_r3 = tcg_constant_i32(r3);
+ type = tcg_constant_i32(s->insn->data);
gen_helper_msa(cc_op, cpu_env, t_r1, t_r2, t_r3, type);
set_cc_static(s);
- tcg_temp_free_i32(t_r1);
- tcg_temp_free_i32(t_r2);
- tcg_temp_free_i32(t_r3);
- tcg_temp_free_i32(type);
return DISAS_NEXT;
}
@@ -3002,10 +2944,9 @@ static DisasJumpType op_loc(DisasContext *s, DisasOps *o)
tcg_gen_extu_i32_i64(t, t32);
tcg_temp_free_i32(t32);
- z = tcg_const_i64(0);
+ z = tcg_constant_i64(0);
tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1);
tcg_temp_free_i64(t);
- tcg_temp_free_i64(z);
}
return DISAS_NEXT;
@@ -3014,11 +2955,10 @@ static DisasJumpType op_loc(DisasContext *s, DisasOps *o)
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_lctl(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
+
gen_helper_lctl(cpu_env, r1, o->in2, r3);
- tcg_temp_free_i32(r1);
- tcg_temp_free_i32(r3);
/* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
s->exit_to_mainloop = true;
return DISAS_TOO_MANY;
@@ -3026,11 +2966,10 @@ static DisasJumpType op_lctl(DisasContext *s, DisasOps *o)
static DisasJumpType op_lctlg(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
+
gen_helper_lctlg(cpu_env, r1, o->in2, r3);
- tcg_temp_free_i32(r1);
- tcg_temp_free_i32(r3);
/* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
s->exit_to_mainloop = true;
return DISAS_TOO_MANY;
@@ -3090,11 +3029,10 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o)
static DisasJumpType op_lam(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
+
gen_helper_lam(cpu_env, r1, o->in2, r3);
- tcg_temp_free_i32(r1);
- tcg_temp_free_i32(r3);
return DISAS_NEXT;
}
@@ -3304,9 +3242,6 @@ static DisasJumpType op_lcbb(DisasContext *s, DisasOps *o)
static DisasJumpType op_mc(DisasContext *s, DisasOps *o)
{
-#if !defined(CONFIG_USER_ONLY)
- TCGv_i32 i2;
-#endif
const uint16_t monitor_class = get_field(s, i2);
if (monitor_class & 0xff00) {
@@ -3315,9 +3250,8 @@ static DisasJumpType op_mc(DisasContext *s, DisasOps *o)
}
#if !defined(CONFIG_USER_ONLY)
- i2 = tcg_const_i32(monitor_class);
- gen_helper_monitor_call(cpu_env, o->addr1, i2);
- tcg_temp_free_i32(i2);
+ gen_helper_monitor_call(cpu_env, o->addr1,
+ tcg_constant_i32(monitor_class));
#endif
/* Defaults to a NOP. */
return DISAS_NEXT;
@@ -3381,9 +3315,9 @@ static DisasJumpType op_movx(DisasContext *s, DisasOps *o)
static DisasJumpType op_mvc(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s, l1));
+ TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
+
gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
- tcg_temp_free_i32(l);
return DISAS_NEXT;
}
@@ -3395,9 +3329,9 @@ static DisasJumpType op_mvcrl(DisasContext *s, DisasOps *o)
static DisasJumpType op_mvcin(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s, l1));
+ TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
+
gen_helper_mvcin(cpu_env, l, o->addr1, o->in2);
- tcg_temp_free_i32(l);
return DISAS_NEXT;
}
@@ -3413,11 +3347,9 @@ static DisasJumpType op_mvcl(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
- t1 = tcg_const_i32(r1);
- t2 = tcg_const_i32(r2);
+ t1 = tcg_constant_i32(r1);
+ t2 = tcg_constant_i32(r2);
gen_helper_mvcl(cc_op, cpu_env, t1, t2);
- tcg_temp_free_i32(t1);
- tcg_temp_free_i32(t2);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -3434,11 +3366,9 @@ static DisasJumpType op_mvcle(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
- t1 = tcg_const_i32(r1);
- t3 = tcg_const_i32(r3);
+ t1 = tcg_constant_i32(r1);
+ t3 = tcg_constant_i32(r3);
gen_helper_mvcle(cc_op, cpu_env, t1, o->in2, t3);
- tcg_temp_free_i32(t1);
- tcg_temp_free_i32(t3);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -3455,11 +3385,9 @@ static DisasJumpType op_mvclu(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
- t1 = tcg_const_i32(r1);
- t3 = tcg_const_i32(r3);
+ t1 = tcg_constant_i32(r1);
+ t3 = tcg_constant_i32(r3);
gen_helper_mvclu(cc_op, cpu_env, t1, o->in2, t3);
- tcg_temp_free_i32(t1);
- tcg_temp_free_i32(t3);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -3492,49 +3420,45 @@ static DisasJumpType op_mvcs(DisasContext *s, DisasOps *o)
static DisasJumpType op_mvn(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s, l1));
+ TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
+
gen_helper_mvn(cpu_env, l, o->addr1, o->in2);
- tcg_temp_free_i32(l);
return DISAS_NEXT;
}
static DisasJumpType op_mvo(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s, l1));
+ TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
+
gen_helper_mvo(cpu_env, l, o->addr1, o->in2);
- tcg_temp_free_i32(l);
return DISAS_NEXT;
}
static DisasJumpType op_mvpg(DisasContext *s, DisasOps *o)
{
- TCGv_i32 t1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 t2 = tcg_const_i32(get_field(s, r2));
+ TCGv_i32 t1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 t2 = tcg_constant_i32(get_field(s, r2));
gen_helper_mvpg(cc_op, cpu_env, regs[0], t1, t2);
- tcg_temp_free_i32(t1);
- tcg_temp_free_i32(t2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_mvst(DisasContext *s, DisasOps *o)
{
- TCGv_i32 t1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 t2 = tcg_const_i32(get_field(s, r2));
+ TCGv_i32 t1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 t2 = tcg_constant_i32(get_field(s, r2));
gen_helper_mvst(cc_op, cpu_env, t1, t2);
- tcg_temp_free_i32(t1);
- tcg_temp_free_i32(t2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_mvz(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s, l1));
+ TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
+
gen_helper_mvz(cpu_env, l, o->addr1, o->in2);
- tcg_temp_free_i32(l);
return DISAS_NEXT;
}
@@ -3622,13 +3546,12 @@ static DisasJumpType op_msdb(DisasContext *s, DisasOps *o)
static DisasJumpType op_nabs(DisasContext *s, DisasOps *o)
{
- TCGv_i64 z, n;
- z = tcg_const_i64(0);
- n = tcg_temp_new_i64();
+ TCGv_i64 z = tcg_constant_i64(0);
+ TCGv_i64 n = tcg_temp_new_i64();
+
tcg_gen_neg_i64(n, o->in2);
tcg_gen_movcond_i64(TCG_COND_GE, o->out, o->in2, z, n, o->in2);
tcg_temp_free_i64(n);
- tcg_temp_free_i64(z);
return DISAS_NEXT;
}
@@ -3653,9 +3576,9 @@ static DisasJumpType op_nabsf128(DisasContext *s, DisasOps *o)
static DisasJumpType op_nc(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s, l1));
+ TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
+
gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
- tcg_temp_free_i32(l);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -3687,9 +3610,9 @@ static DisasJumpType op_negf128(DisasContext *s, DisasOps *o)
static DisasJumpType op_oc(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s, l1));
+ TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
+
gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
- tcg_temp_free_i32(l);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -3739,9 +3662,9 @@ static DisasJumpType op_oi(DisasContext *s, DisasOps *o)
static DisasJumpType op_pack(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s, l1));
+ TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
+
gen_helper_pack(cpu_env, l, o->addr1, o->in2);
- tcg_temp_free_i32(l);
return DISAS_NEXT;
}
@@ -3755,9 +3678,8 @@ static DisasJumpType op_pka(DisasContext *s, DisasOps *o)
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- l = tcg_const_i32(l2);
+ l = tcg_constant_i32(l2);
gen_helper_pka(cpu_env, o->addr1, o->in2, l);
- tcg_temp_free_i32(l);
return DISAS_NEXT;
}
@@ -3771,9 +3693,8 @@ static DisasJumpType op_pku(DisasContext *s, DisasOps *o)
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- l = tcg_const_i32(l2);
+ l = tcg_constant_i32(l2);
gen_helper_pku(cpu_env, o->addr1, o->in2, l);
- tcg_temp_free_i32(l);
return DISAS_NEXT;
}
@@ -4020,9 +3941,8 @@ static DisasJumpType op_sam(DisasContext *s, DisasOps *o)
}
s->pc_tmp &= mask;
- tsam = tcg_const_i64(sam);
+ tsam = tcg_constant_i64(sam);
tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2);
- tcg_temp_free_i64(tsam);
/* Always exit the TB, since we (may have) changed execution mode. */
return DISAS_TOO_MANY;
@@ -4083,12 +4003,11 @@ static DisasJumpType op_servc(DisasContext *s, DisasOps *o)
static DisasJumpType op_sigp(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
+
gen_helper_sigp(cc_op, cpu_env, o->in2, r1, r3);
set_cc_static(s);
- tcg_temp_free_i32(r1);
- tcg_temp_free_i32(r3);
return DISAS_NEXT;
}
#endif
@@ -4357,21 +4276,19 @@ static DisasJumpType op_stckc(DisasContext *s, DisasOps *o)
static DisasJumpType op_stctg(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
+
gen_helper_stctg(cpu_env, r1, o->in2, r3);
- tcg_temp_free_i32(r1);
- tcg_temp_free_i32(r3);
return DISAS_NEXT;
}
static DisasJumpType op_stctl(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
+
gen_helper_stctl(cpu_env, r1, o->in2, r3);
- tcg_temp_free_i32(r1);
- tcg_temp_free_i32(r3);
return DISAS_NEXT;
}
@@ -4598,11 +4515,10 @@ static DisasJumpType op_st64(DisasContext *s, DisasOps *o)
static DisasJumpType op_stam(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
+
gen_helper_stam(cpu_env, r1, o->in2, r3);
- tcg_temp_free_i32(r1);
- tcg_temp_free_i32(r3);
return DISAS_NEXT;
}
@@ -4660,7 +4576,7 @@ static DisasJumpType op_stm(DisasContext *s, DisasOps *o)
int r1 = get_field(s, r1);
int r3 = get_field(s, r3);
int size = s->insn->data;
- TCGv_i64 tsize = tcg_const_i64(size);
+ TCGv_i64 tsize = tcg_constant_i64(size);
while (1) {
if (size == 8) {
@@ -4675,7 +4591,6 @@ static DisasJumpType op_stm(DisasContext *s, DisasOps *o)
r1 = (r1 + 1) & 15;
}
- tcg_temp_free_i64(tsize);
return DISAS_NEXT;
}
@@ -4684,8 +4599,8 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o)
int r1 = get_field(s, r1);
int r3 = get_field(s, r3);
TCGv_i64 t = tcg_temp_new_i64();
- TCGv_i64 t4 = tcg_const_i64(4);
- TCGv_i64 t32 = tcg_const_i64(32);
+ TCGv_i64 t4 = tcg_constant_i64(4);
+ TCGv_i64 t32 = tcg_constant_i64(32);
while (1) {
tcg_gen_shl_i64(t, regs[r1], t32);
@@ -4698,8 +4613,6 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o)
}
tcg_temp_free_i64(t);
- tcg_temp_free_i64(t4);
- tcg_temp_free_i64(t32);
return DISAS_NEXT;
}
@@ -4718,26 +4631,20 @@ static DisasJumpType op_stpq(DisasContext *s, DisasOps *o)
static DisasJumpType op_srst(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 r2 = tcg_const_i32(get_field(s, r2));
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
gen_helper_srst(cpu_env, r1, r2);
-
- tcg_temp_free_i32(r1);
- tcg_temp_free_i32(r2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_srstu(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 r2 = tcg_const_i32(get_field(s, r2));
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
gen_helper_srstu(cpu_env, r1, r2);
-
- tcg_temp_free_i32(r1);
- tcg_temp_free_i32(r2);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -4795,10 +4702,9 @@ static DisasJumpType op_subb64(DisasContext *s, DisasOps *o)
* Borrow is {0, -1}, so add to subtract; replicate the
* borrow input to produce 128-bit -1 for the addition.
*/
- TCGv_i64 zero = tcg_const_i64(0);
+ TCGv_i64 zero = tcg_constant_i64(0);
tcg_gen_add2_i64(o->out, cc_src, o->in1, zero, cc_src, cc_src);
tcg_gen_sub2_i64(o->out, cc_src, o->out, cc_src, o->in2, zero);
- tcg_temp_free_i64(zero);
return DISAS_NEXT;
}
@@ -4810,13 +4716,11 @@ static DisasJumpType op_svc(DisasContext *s, DisasOps *o)
update_psw_addr(s);
update_cc_op(s);
- t = tcg_const_i32(get_field(s, i1) & 0xff);
+ t = tcg_constant_i32(get_field(s, i1) & 0xff);
tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
- tcg_temp_free_i32(t);
- t = tcg_const_i32(s->ilen);
+ t = tcg_constant_i32(s->ilen);
tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
- tcg_temp_free_i32(t);
gen_exception(EXCP_SVC);
return DISAS_NORETURN;
@@ -4873,18 +4777,18 @@ static DisasJumpType op_tprot(DisasContext *s, DisasOps *o)
static DisasJumpType op_tp(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l1 = tcg_const_i32(get_field(s, l1) + 1);
+ TCGv_i32 l1 = tcg_constant_i32(get_field(s, l1) + 1);
+
gen_helper_tp(cc_op, cpu_env, o->addr1, l1);
- tcg_temp_free_i32(l1);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_tr(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s, l1));
+ TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
+
gen_helper_tr(cpu_env, l, o->addr1, o->in2);
- tcg_temp_free_i32(l);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -4899,27 +4803,27 @@ static DisasJumpType op_tre(DisasContext *s, DisasOps *o)
static DisasJumpType op_trt(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s, l1));
+ TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
+
gen_helper_trt(cc_op, cpu_env, l, o->addr1, o->in2);
- tcg_temp_free_i32(l);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_trtr(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s, l1));
+ TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
+
gen_helper_trtr(cc_op, cpu_env, l, o->addr1, o->in2);
- tcg_temp_free_i32(l);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_trXX(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 r2 = tcg_const_i32(get_field(s, r2));
- TCGv_i32 sizes = tcg_const_i32(s->insn->opc & 3);
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
+ TCGv_i32 sizes = tcg_constant_i32(s->insn->opc & 3);
TCGv_i32 tst = tcg_temp_new_i32();
int m3 = get_field(s, m3);
@@ -4938,9 +4842,6 @@ static DisasJumpType op_trXX(DisasContext *s, DisasOps *o)
}
gen_helper_trXX(cc_op, cpu_env, r1, r2, tst, sizes);
- tcg_temp_free_i32(r1);
- tcg_temp_free_i32(r2);
- tcg_temp_free_i32(sizes);
tcg_temp_free_i32(tst);
set_cc_static(s);
return DISAS_NEXT;
@@ -4948,19 +4849,19 @@ static DisasJumpType op_trXX(DisasContext *s, DisasOps *o)
static DisasJumpType op_ts(DisasContext *s, DisasOps *o)
{
- TCGv_i32 t1 = tcg_const_i32(0xff);
+ TCGv_i32 t1 = tcg_constant_i32(0xff);
+
tcg_gen_atomic_xchg_i32(t1, o->in2, t1, get_mem_index(s), MO_UB);
tcg_gen_extract_i32(cc_op, t1, 7, 1);
- tcg_temp_free_i32(t1);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_unpk(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s, l1));
+ TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
+
gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
- tcg_temp_free_i32(l);
return DISAS_NEXT;
}
@@ -4974,9 +4875,8 @@ static DisasJumpType op_unpka(DisasContext *s, DisasOps *o)
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- l = tcg_const_i32(l1);
+ l = tcg_constant_i32(l1);
gen_helper_unpka(cc_op, cpu_env, o->addr1, l, o->in2);
- tcg_temp_free_i32(l);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -4991,9 +4891,8 @@ static DisasJumpType op_unpku(DisasContext *s, DisasOps *o)
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- l = tcg_const_i32(l1);
+ l = tcg_constant_i32(l1);
gen_helper_unpku(cc_op, cpu_env, o->addr1, l, o->in2);
- tcg_temp_free_i32(l);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -5012,7 +4911,7 @@ static DisasJumpType op_xc(DisasContext *s, DisasOps *o)
/* If the addresses are identical, this is a store/memset of zero. */
if (b1 == b2 && d1 == d2 && (l + 1) <= 32) {
- o->in2 = tcg_const_i64(0);
+ o->in2 = tcg_constant_i64(0);
l++;
while (l >= 8) {
@@ -5045,9 +4944,8 @@ static DisasJumpType op_xc(DisasContext *s, DisasOps *o)
/* But in general we'll defer to a helper. */
o->in2 = get_address(s, 0, b2, d2);
- t32 = tcg_const_i32(l);
+ t32 = tcg_constant_i32(l);
gen_helper_xc(cc_op, cpu_env, t32, o->addr1, o->in2);
- tcg_temp_free_i32(t32);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -5112,46 +5010,39 @@ static DisasJumpType op_zero2(DisasContext *s, DisasOps *o)
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_clp(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r2 = tcg_const_i32(get_field(s, r2));
+ TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
gen_helper_clp(cpu_env, r2);
- tcg_temp_free_i32(r2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_pcilg(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 r2 = tcg_const_i32(get_field(s, r2));
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
gen_helper_pcilg(cpu_env, r1, r2);
- tcg_temp_free_i32(r1);
- tcg_temp_free_i32(r2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_pcistg(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 r2 = tcg_const_i32(get_field(s, r2));
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
gen_helper_pcistg(cpu_env, r1, r2);
- tcg_temp_free_i32(r1);
- tcg_temp_free_i32(r2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_stpcifc(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 ar = tcg_const_i32(get_field(s, b2));
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 ar = tcg_constant_i32(get_field(s, b2));
gen_helper_stpcifc(cpu_env, r1, o->addr1, ar);
- tcg_temp_free_i32(ar);
- tcg_temp_free_i32(r1);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -5164,38 +5055,31 @@ static DisasJumpType op_sic(DisasContext *s, DisasOps *o)
static DisasJumpType op_rpcit(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 r2 = tcg_const_i32(get_field(s, r2));
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
gen_helper_rpcit(cpu_env, r1, r2);
- tcg_temp_free_i32(r1);
- tcg_temp_free_i32(r2);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_pcistb(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
- TCGv_i32 ar = tcg_const_i32(get_field(s, b2));
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
+ TCGv_i32 ar = tcg_constant_i32(get_field(s, b2));
gen_helper_pcistb(cpu_env, r1, r3, o->addr1, ar);
- tcg_temp_free_i32(ar);
- tcg_temp_free_i32(r1);
- tcg_temp_free_i32(r3);
set_cc_static(s);
return DISAS_NEXT;
}
static DisasJumpType op_mpcifc(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
- TCGv_i32 ar = tcg_const_i32(get_field(s, b2));
+ TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
+ TCGv_i32 ar = tcg_constant_i32(get_field(s, b2));
gen_helper_mpcifc(cpu_env, r1, o->addr1, ar);
- tcg_temp_free_i32(ar);
- tcg_temp_free_i32(r1);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -6316,9 +6200,8 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s)
if (unlikely(s->ex_value)) {
/* Drop the EX data now, so that it's clear on exception paths. */
- TCGv_i64 zero = tcg_const_i64(0);
- tcg_gen_st_i64(zero, cpu_env, offsetof(CPUS390XState, ex_value));
- tcg_temp_free_i64(zero);
+ tcg_gen_st_i64(tcg_constant_i64(0), cpu_env,
+ offsetof(CPUS390XState, ex_value));
/* Extract the values saved by EXECUTE. */
insn = s->ex_value & 0xffffffffffff0000ull;
@@ -6444,9 +6327,8 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
#ifndef CONFIG_USER_ONLY
if (s->base.tb->flags & FLAG_MASK_PER) {
- TCGv_i64 addr = tcg_const_i64(s->base.pc_next);
+ TCGv_i64 addr = tcg_constant_i64(s->base.pc_next);
gen_helper_per_ifetch(cpu_env, addr);
- tcg_temp_free_i64(addr);
}
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 02/26] target/s390x: Use tcg_constant_* for DisasCompare
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
2022-10-06 3:43 ` [PATCH 01/26] target/s390x: Use tcg_constant_* in local contexts Richard Henderson
@ 2022-10-06 3:43 ` Richard Henderson
2022-11-03 10:54 ` Ilya Leoshkevich
2022-10-06 3:43 ` [PATCH 03/26] target/s390x: Use tcg_constant_i32 for fpinst_extract_m34 Richard Henderson
` (24 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:43 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
The a and b fields are not modified by the consumer,
and while we need not free a constant, tcg will quietly
ignore such frees, so free_compare need not be changed.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 44 ++++++++++++++++++------------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 890d1f1db3..ec43bd7a1f 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -830,7 +830,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
c->is_64 = false;
c->u.s32.a = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(c->u.s32.a, cc_dst);
- c->u.s32.b = tcg_const_i32(0);
+ c->u.s32.b = tcg_constant_i32(0);
break;
case CC_OP_LTGT_32:
case CC_OP_LTUGTU_32:
@@ -845,7 +845,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
case CC_OP_NZ:
case CC_OP_FLOGR:
c->u.s64.a = cc_dst;
- c->u.s64.b = tcg_const_i64(0);
+ c->u.s64.b = tcg_constant_i64(0);
c->g1 = true;
break;
case CC_OP_LTGT_64:
@@ -859,14 +859,14 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
case CC_OP_TM_64:
case CC_OP_ICM:
c->u.s64.a = tcg_temp_new_i64();
- c->u.s64.b = tcg_const_i64(0);
+ c->u.s64.b = tcg_constant_i64(0);
tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
break;
case CC_OP_ADDU:
case CC_OP_SUBU:
c->is_64 = true;
- c->u.s64.b = tcg_const_i64(0);
+ c->u.s64.b = tcg_constant_i64(0);
c->g1 = true;
switch (mask) {
case 8 | 2:
@@ -889,65 +889,65 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
switch (mask) {
case 0x8 | 0x4 | 0x2: /* cc != 3 */
cond = TCG_COND_NE;
- c->u.s32.b = tcg_const_i32(3);
+ c->u.s32.b = tcg_constant_i32(3);
break;
case 0x8 | 0x4 | 0x1: /* cc != 2 */
cond = TCG_COND_NE;
- c->u.s32.b = tcg_const_i32(2);
+ c->u.s32.b = tcg_constant_i32(2);
break;
case 0x8 | 0x2 | 0x1: /* cc != 1 */
cond = TCG_COND_NE;
- c->u.s32.b = tcg_const_i32(1);
+ c->u.s32.b = tcg_constant_i32(1);
break;
case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
cond = TCG_COND_EQ;
c->g1 = false;
c->u.s32.a = tcg_temp_new_i32();
- c->u.s32.b = tcg_const_i32(0);
+ c->u.s32.b = tcg_constant_i32(0);
tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
break;
case 0x8 | 0x4: /* cc < 2 */
cond = TCG_COND_LTU;
- c->u.s32.b = tcg_const_i32(2);
+ c->u.s32.b = tcg_constant_i32(2);
break;
case 0x8: /* cc == 0 */
cond = TCG_COND_EQ;
- c->u.s32.b = tcg_const_i32(0);
+ c->u.s32.b = tcg_constant_i32(0);
break;
case 0x4 | 0x2 | 0x1: /* cc != 0 */
cond = TCG_COND_NE;
- c->u.s32.b = tcg_const_i32(0);
+ c->u.s32.b = tcg_constant_i32(0);
break;
case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
cond = TCG_COND_NE;
c->g1 = false;
c->u.s32.a = tcg_temp_new_i32();
- c->u.s32.b = tcg_const_i32(0);
+ c->u.s32.b = tcg_constant_i32(0);
tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
break;
case 0x4: /* cc == 1 */
cond = TCG_COND_EQ;
- c->u.s32.b = tcg_const_i32(1);
+ c->u.s32.b = tcg_constant_i32(1);
break;
case 0x2 | 0x1: /* cc > 1 */
cond = TCG_COND_GTU;
- c->u.s32.b = tcg_const_i32(1);
+ c->u.s32.b = tcg_constant_i32(1);
break;
case 0x2: /* cc == 2 */
cond = TCG_COND_EQ;
- c->u.s32.b = tcg_const_i32(2);
+ c->u.s32.b = tcg_constant_i32(2);
break;
case 0x1: /* cc == 3 */
cond = TCG_COND_EQ;
- c->u.s32.b = tcg_const_i32(3);
+ c->u.s32.b = tcg_constant_i32(3);
break;
default:
/* CC is masked by something else: (8 >> cc) & mask. */
cond = TCG_COND_NE;
c->g1 = false;
- c->u.s32.a = tcg_const_i32(8);
- c->u.s32.b = tcg_const_i32(0);
- tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
+ c->u.s32.a = tcg_temp_new_i32();
+ c->u.s32.b = tcg_constant_i32(0);
+ tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op);
tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
break;
}
@@ -1604,7 +1604,7 @@ static DisasJumpType op_bct32(DisasContext *s, DisasOps *o)
tcg_gen_subi_i64(t, regs[r1], 1);
store_reg32_i64(r1, t);
c.u.s32.a = tcg_temp_new_i32();
- c.u.s32.b = tcg_const_i32(0);
+ c.u.s32.b = tcg_constant_i32(0);
tcg_gen_extrl_i64_i32(c.u.s32.a, t);
tcg_temp_free_i64(t);
@@ -1628,7 +1628,7 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOps *o)
tcg_gen_subi_i64(t, t, 1);
store_reg32h_i64(r1, t);
c.u.s32.a = tcg_temp_new_i32();
- c.u.s32.b = tcg_const_i32(0);
+ c.u.s32.b = tcg_constant_i32(0);
tcg_gen_extrl_i64_i32(c.u.s32.a, t);
tcg_temp_free_i64(t);
@@ -1649,7 +1649,7 @@ static DisasJumpType op_bct64(DisasContext *s, DisasOps *o)
tcg_gen_subi_i64(regs[r1], regs[r1], 1);
c.u.s64.a = regs[r1];
- c.u.s64.b = tcg_const_i64(0);
+ c.u.s64.b = tcg_constant_i64(0);
return help_branch(s, &c, is_imm, imm, o->in2);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 03/26] target/s390x: Use tcg_constant_i32 for fpinst_extract_m34
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
2022-10-06 3:43 ` [PATCH 01/26] target/s390x: Use tcg_constant_* in local contexts Richard Henderson
2022-10-06 3:43 ` [PATCH 02/26] target/s390x: Use tcg_constant_* for DisasCompare Richard Henderson
@ 2022-10-06 3:43 ` Richard Henderson
2022-11-03 10:56 ` Ilya Leoshkevich
2022-10-06 3:43 ` [PATCH 04/26] target/s390x: Use tcg_constant_* in translate_vx.c.inc Richard Henderson
` (23 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:43 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
Return a constant or NULL, which means the free may be
removed from all callers of fpinst_extract_m34.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 26 +-------------------------
1 file changed, 1 insertion(+), 25 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index ec43bd7a1f..f8cfddc181 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -1775,7 +1775,7 @@ static TCGv_i32 fpinst_extract_m34(DisasContext *s, bool m3_with_fpe,
return NULL;
}
- return tcg_const_i32(deposit32(m3, 4, 4, m4));
+ return tcg_constant_i32(deposit32(m3, 4, 4, m4));
}
static DisasJumpType op_cfeb(DisasContext *s, DisasOps *o)
@@ -1786,7 +1786,6 @@ static DisasJumpType op_cfeb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_cfeb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -1799,7 +1798,6 @@ static DisasJumpType op_cfdb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_cfdb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -1812,7 +1810,6 @@ static DisasJumpType op_cfxb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m34);
- tcg_temp_free_i32(m34);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -1825,7 +1822,6 @@ static DisasJumpType op_cgeb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_cgeb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -1838,7 +1834,6 @@ static DisasJumpType op_cgdb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_cgdb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -1851,7 +1846,6 @@ static DisasJumpType op_cgxb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m34);
- tcg_temp_free_i32(m34);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -1864,7 +1858,6 @@ static DisasJumpType op_clfeb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_clfeb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -1877,7 +1870,6 @@ static DisasJumpType op_clfdb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_clfdb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -1890,7 +1882,6 @@ static DisasJumpType op_clfxb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_clfxb(o->out, cpu_env, o->in1, o->in2, m34);
- tcg_temp_free_i32(m34);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -1903,7 +1894,6 @@ static DisasJumpType op_clgeb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_clgeb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -1916,7 +1906,6 @@ static DisasJumpType op_clgdb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_clgdb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -1929,7 +1918,6 @@ static DisasJumpType op_clgxb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_clgxb(o->out, cpu_env, o->in1, o->in2, m34);
- tcg_temp_free_i32(m34);
set_cc_static(s);
return DISAS_NEXT;
}
@@ -1942,7 +1930,6 @@ static DisasJumpType op_cegb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_cegb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
return DISAS_NEXT;
}
@@ -1954,7 +1941,6 @@ static DisasJumpType op_cdgb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_cdgb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
return DISAS_NEXT;
}
@@ -1966,7 +1952,6 @@ static DisasJumpType op_cxgb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_cxgb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
return_low128(o->out2);
return DISAS_NEXT;
}
@@ -1979,7 +1964,6 @@ static DisasJumpType op_celgb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_celgb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
return DISAS_NEXT;
}
@@ -1991,7 +1975,6 @@ static DisasJumpType op_cdlgb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_cdlgb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
return DISAS_NEXT;
}
@@ -2003,7 +1986,6 @@ static DisasJumpType op_cxlgb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_cxlgb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
return_low128(o->out2);
return DISAS_NEXT;
}
@@ -2466,7 +2448,6 @@ static DisasJumpType op_fieb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_fieb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
return DISAS_NEXT;
}
@@ -2478,7 +2459,6 @@ static DisasJumpType op_fidb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_fidb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
return DISAS_NEXT;
}
@@ -2491,7 +2471,6 @@ static DisasJumpType op_fixb(DisasContext *s, DisasOps *o)
}
gen_helper_fixb(o->out, cpu_env, o->in1, o->in2, m34);
return_low128(o->out2);
- tcg_temp_free_i32(m34);
return DISAS_NEXT;
}
@@ -2766,7 +2745,6 @@ static DisasJumpType op_ledb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_ledb(o->out, cpu_env, o->in2, m34);
- tcg_temp_free_i32(m34);
return DISAS_NEXT;
}
@@ -2778,7 +2756,6 @@ static DisasJumpType op_ldxb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2, m34);
- tcg_temp_free_i32(m34);
return DISAS_NEXT;
}
@@ -2790,7 +2767,6 @@ static DisasJumpType op_lexb(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
gen_helper_lexb(o->out, cpu_env, o->in1, o->in2, m34);
- tcg_temp_free_i32(m34);
return DISAS_NEXT;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 04/26] target/s390x: Use tcg_constant_* in translate_vx.c.inc
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (2 preceding siblings ...)
2022-10-06 3:43 ` [PATCH 03/26] target/s390x: Use tcg_constant_i32 for fpinst_extract_m34 Richard Henderson
@ 2022-10-06 3:43 ` Richard Henderson
2022-11-03 11:04 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 05/26] target/s390x: Change help_goto_direct to work on displacements Richard Henderson
` (22 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:43 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
In most cases, this is a simple local allocate and free
replaced by tcg_constant_*. In three cases, a variable
temp was initialized with a constant value -- reorg to
localize the constant.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate_vx.c.inc | 45 +++++++++++++----------------
1 file changed, 20 insertions(+), 25 deletions(-)
diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/translate_vx.c.inc
index 3526ba3e3b..cdb192454f 100644
--- a/target/s390x/tcg/translate_vx.c.inc
+++ b/target/s390x/tcg/translate_vx.c.inc
@@ -319,12 +319,10 @@ static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a,
static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
uint64_t b)
{
- TCGv_i64 bl = tcg_const_i64(b);
- TCGv_i64 bh = tcg_const_i64(0);
+ TCGv_i64 bl = tcg_constant_i64(b);
+ TCGv_i64 bh = tcg_constant_i64(0);
tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
- tcg_temp_free_i64(bl);
- tcg_temp_free_i64(bh);
}
static DisasJumpType op_vbperm(DisasContext *s, DisasOps *o)
@@ -609,9 +607,8 @@ static DisasJumpType op_vlei(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
- tmp = tcg_const_i64((int16_t)get_field(s, i2));
+ tmp = tcg_constant_i64((int16_t)get_field(s, i2));
write_vec_element_i64(tmp, get_field(s, v1), enr, es);
- tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
@@ -1107,11 +1104,13 @@ static DisasJumpType op_vseg(DisasContext *s, DisasOps *o)
static DisasJumpType op_vst(DisasContext *s, DisasOps *o)
{
- TCGv_i64 tmp = tcg_const_i64(16);
+ TCGv_i64 tmp;
/* Probe write access before actually modifying memory */
- gen_helper_probe_write_access(cpu_env, o->addr1, tmp);
+ gen_helper_probe_write_access(cpu_env, o->addr1,
+ tcg_constant_i64(16));
+ tmp = tcg_temp_new_i64();
read_vec_element_i64(tmp, get_field(s, v1), 0, ES_64);
tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ);
gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
@@ -1270,9 +1269,10 @@ static DisasJumpType op_vstm(DisasContext *s, DisasOps *o)
}
/* Probe write access before actually modifying memory */
- tmp = tcg_const_i64((v3 - v1 + 1) * 16);
- gen_helper_probe_write_access(cpu_env, o->addr1, tmp);
+ gen_helper_probe_write_access(cpu_env, o->addr1,
+ tcg_constant_i64((v3 - v1 + 1) * 16));
+ tmp = tcg_temp_new_i64();
for (;; v1++) {
read_vec_element_i64(tmp, v1, 0, ES_64);
tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ);
@@ -1359,7 +1359,7 @@ static DisasJumpType op_va(DisasContext *s, DisasOps *o)
static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es)
{
const uint8_t msb_bit_nr = NUM_VEC_ELEMENT_BITS(es) - 1;
- TCGv_i64 msb_mask = tcg_const_i64(dup_const(es, 1ull << msb_bit_nr));
+ TCGv_i64 msb_mask = tcg_constant_i64(dup_const(es, 1ull << msb_bit_nr));
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
@@ -1416,7 +1416,7 @@ static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
{
TCGv_i64 th = tcg_temp_new_i64();
TCGv_i64 tl = tcg_temp_new_i64();
- TCGv_i64 zero = tcg_const_i64(0);
+ TCGv_i64 zero = tcg_constant_i64(0);
tcg_gen_add2_i64(tl, th, al, zero, bl, zero);
tcg_gen_add2_i64(tl, th, th, zero, ah, zero);
@@ -1425,7 +1425,6 @@ static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
tcg_temp_free_i64(th);
tcg_temp_free_i64(tl);
- tcg_temp_free_i64(zero);
}
static DisasJumpType op_vacc(DisasContext *s, DisasOps *o)
@@ -1455,15 +1454,14 @@ static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
{
TCGv_i64 tl = tcg_temp_new_i64();
- TCGv_i64 th = tcg_const_i64(0);
+ TCGv_i64 zero = tcg_constant_i64(0);
/* extract the carry only */
tcg_gen_extract_i64(tl, cl, 0, 1);
tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
- tcg_gen_add2_i64(dl, dh, dl, dh, tl, th);
+ tcg_gen_add2_i64(dl, dh, dl, dh, tl, zero);
tcg_temp_free_i64(tl);
- tcg_temp_free_i64(th);
}
static DisasJumpType op_vac(DisasContext *s, DisasOps *o)
@@ -1484,7 +1482,7 @@ static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
{
TCGv_i64 tl = tcg_temp_new_i64();
TCGv_i64 th = tcg_temp_new_i64();
- TCGv_i64 zero = tcg_const_i64(0);
+ TCGv_i64 zero = tcg_constant_i64(0);
tcg_gen_andi_i64(tl, cl, 1);
tcg_gen_add2_i64(tl, th, tl, zero, al, zero);
@@ -1495,7 +1493,6 @@ static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
tcg_temp_free_i64(tl);
tcg_temp_free_i64(th);
- tcg_temp_free_i64(zero);
}
static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o)
@@ -1597,14 +1594,13 @@ static void gen_avgl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
{
TCGv_i64 dh = tcg_temp_new_i64();
- TCGv_i64 zero = tcg_const_i64(0);
+ TCGv_i64 zero = tcg_constant_i64(0);
tcg_gen_add2_i64(dl, dh, al, zero, bl, zero);
gen_addi2_i64(dl, dh, dl, dh, 1);
tcg_gen_extract2_i64(dl, dl, dh, 1);
tcg_temp_free_i64(dh);
- tcg_temp_free_i64(zero);
}
static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o)
@@ -2440,7 +2436,7 @@ static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
{
TCGv_i64 th = tcg_temp_new_i64();
TCGv_i64 tl = tcg_temp_new_i64();
- TCGv_i64 zero = tcg_const_i64(0);
+ TCGv_i64 zero = tcg_constant_i64(0);
tcg_gen_sub2_i64(tl, th, al, zero, bl, zero);
tcg_gen_andi_i64(th, th, 1);
@@ -2452,7 +2448,6 @@ static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
tcg_temp_free_i64(th);
tcg_temp_free_i64(tl);
- tcg_temp_free_i64(zero);
}
static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o)
@@ -2572,11 +2567,12 @@ static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
- sumh = tcg_const_i64(0);
+ sumh = tcg_temp_new_i64();
suml = tcg_temp_new_i64();
- zero = tcg_const_i64(0);
+ zero = tcg_constant_i64(0);
tmpl = tcg_temp_new_i64();
+ tcg_gen_mov_i64(sumh, zero);
read_vec_element_i64(suml, get_field(s, v3), max_idx, es);
for (idx = 0; idx <= max_idx; idx++) {
read_vec_element_i64(tmpl, get_field(s, v2), idx, es);
@@ -2587,7 +2583,6 @@ static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(sumh);
tcg_temp_free_i64(suml);
- tcg_temp_free_i64(zero);
tcg_temp_free_i64(tmpl);
return DISAS_NEXT;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 05/26] target/s390x: Change help_goto_direct to work on displacements
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (3 preceding siblings ...)
2022-10-06 3:43 ` [PATCH 04/26] target/s390x: Use tcg_constant_* in translate_vx.c.inc Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-03 11:13 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 06/26] target/s390x: Introduce gen_psw_addr_disp Richard Henderson
` (21 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index f8cfddc181..b6e4005670 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -1145,8 +1145,10 @@ struct DisasInsn {
/* ====================================================================== */
/* Miscellaneous helpers, used by several operations. */
-static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest)
+static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp)
{
+ uint64_t dest = s->base.pc_next + disp;
+
if (dest == s->pc_tmp) {
per_branch(s, true);
return DISAS_NEXT;
@@ -1169,7 +1171,8 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
bool is_imm, int imm, TCGv_i64 cdest)
{
DisasJumpType ret;
- uint64_t dest = s->base.pc_next + (int64_t)imm * 2;
+ int64_t disp = (int64_t)imm * 2;
+ uint64_t dest = s->base.pc_next + disp;
TCGLabel *lab;
/* Take care of the special cases first. */
@@ -1185,7 +1188,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
goto egress;
}
if (c->cond == TCG_COND_ALWAYS) {
- ret = help_goto_direct(s, dest);
+ ret = help_goto_direct(s, disp);
goto egress;
}
} else {
@@ -1558,7 +1561,7 @@ static DisasJumpType op_bal(DisasContext *s, DisasOps *o)
static DisasJumpType op_basi(DisasContext *s, DisasOps *o)
{
pc_to_link_info(o->out, s, s->pc_tmp);
- return help_goto_direct(s, s->base.pc_next + (int64_t)get_field(s, i2) * 2);
+ return help_goto_direct(s, (int64_t)get_field(s, i2) * 2);
}
static DisasJumpType op_bc(DisasContext *s, DisasOps *o)
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 06/26] target/s390x: Introduce gen_psw_addr_disp
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (4 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 05/26] target/s390x: Change help_goto_direct to work on displacements Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-03 11:22 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 07/26] target/s390x: Remove pc argument to pc_to_link_into Richard Henderson
` (20 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 69 ++++++++++++++++++++++++------------
1 file changed, 46 insertions(+), 23 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index b6e4005670..47a9d87416 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -169,6 +169,11 @@ static uint64_t inline_branch_hit[CC_OP_MAX];
static uint64_t inline_branch_miss[CC_OP_MAX];
#endif
+static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp)
+{
+ tcg_gen_movi_i64(dest, s->base.pc_next + disp);
+}
+
static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc)
{
if (s->base.tb->flags & FLAG_MASK_32) {
@@ -334,18 +339,24 @@ static void return_low128(TCGv_i64 dest)
static void update_psw_addr(DisasContext *s)
{
- /* psw.addr */
- tcg_gen_movi_i64(psw_addr, s->base.pc_next);
+ gen_psw_addr_disp(s, psw_addr, 0);
}
static void per_branch(DisasContext *s, bool to_next)
{
#ifndef CONFIG_USER_ONLY
- tcg_gen_movi_i64(gbea, s->base.pc_next);
+ gen_psw_addr_disp(s, gbea, 0);
if (s->base.tb->flags & FLAG_MASK_PER) {
- TCGv_i64 next_pc = to_next ? tcg_constant_i64(s->pc_tmp) : psw_addr;
- gen_helper_per_branch(cpu_env, gbea, next_pc);
+ if (to_next) {
+ TCGv_i64 next_pc = tcg_temp_new_i64();
+
+ gen_psw_addr_disp(s, next_pc, s->ilen);
+ gen_helper_per_branch(cpu_env, gbea, next_pc);
+ tcg_temp_free_i64(next_pc);
+ } else {
+ gen_helper_per_branch(cpu_env, gbea, psw_addr);
+ }
}
#endif
}
@@ -358,20 +369,23 @@ static void per_branch_cond(DisasContext *s, TCGCond cond,
TCGLabel *lab = gen_new_label();
tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab);
- tcg_gen_movi_i64(gbea, s->base.pc_next);
+ gen_psw_addr_disp(s, gbea, 0);
gen_helper_per_branch(cpu_env, gbea, psw_addr);
gen_set_label(lab);
} else {
- TCGv_i64 pc = tcg_constant_i64(s->base.pc_next);
+ TCGv_i64 pc = tcg_temp_new_i64();
+
+ gen_psw_addr_disp(s, pc, 0);
tcg_gen_movcond_i64(cond, gbea, arg1, arg2, gbea, pc);
+ tcg_temp_free_i64(pc);
}
#endif
}
static void per_breaking_event(DisasContext *s)
{
- tcg_gen_movi_i64(gbea, s->base.pc_next);
+ gen_psw_addr_disp(s, gbea, 0);
}
static void update_cc_op(DisasContext *s)
@@ -1147,21 +1161,19 @@ struct DisasInsn {
static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp)
{
- uint64_t dest = s->base.pc_next + disp;
-
- if (dest == s->pc_tmp) {
+ if (disp == s->ilen) {
per_branch(s, true);
return DISAS_NEXT;
}
- if (use_goto_tb(s, dest)) {
+ if (use_goto_tb(s, s->base.pc_next + disp)) {
update_cc_op(s);
per_breaking_event(s);
tcg_gen_goto_tb(0);
- tcg_gen_movi_i64(psw_addr, dest);
+ gen_psw_addr_disp(s, psw_addr, disp);
tcg_gen_exit_tb(s->base.tb, 0);
return DISAS_NORETURN;
} else {
- tcg_gen_movi_i64(psw_addr, dest);
+ gen_psw_addr_disp(s, psw_addr, disp);
per_branch(s, false);
return DISAS_PC_UPDATED;
}
@@ -1219,14 +1231,14 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
/* Branch not taken. */
tcg_gen_goto_tb(0);
- tcg_gen_movi_i64(psw_addr, s->pc_tmp);
+ gen_psw_addr_disp(s, psw_addr, s->ilen);
tcg_gen_exit_tb(s->base.tb, 0);
/* Branch taken. */
gen_set_label(lab);
per_breaking_event(s);
tcg_gen_goto_tb(1);
- tcg_gen_movi_i64(psw_addr, dest);
+ gen_psw_addr_disp(s, psw_addr, disp);
tcg_gen_exit_tb(s->base.tb, 1);
ret = DISAS_NORETURN;
@@ -1249,12 +1261,12 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
/* Branch not taken. */
update_cc_op(s);
tcg_gen_goto_tb(0);
- tcg_gen_movi_i64(psw_addr, s->pc_tmp);
+ gen_psw_addr_disp(s, psw_addr, s->ilen);
tcg_gen_exit_tb(s->base.tb, 0);
gen_set_label(lab);
if (is_imm) {
- tcg_gen_movi_i64(psw_addr, dest);
+ gen_psw_addr_disp(s, psw_addr, disp);
}
per_breaking_event(s);
ret = DISAS_PC_UPDATED;
@@ -1264,9 +1276,12 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
Most commonly we're single-stepping or some other condition that
disables all use of goto_tb. Just update the PC and exit. */
- TCGv_i64 next = tcg_constant_i64(s->pc_tmp);
+ TCGv_i64 next = tcg_temp_new_i64();
+
+ gen_psw_addr_disp(s, next, s->ilen);
if (is_imm) {
- cdest = tcg_constant_i64(dest);
+ cdest = tcg_temp_new_i64();
+ gen_psw_addr_disp(s, cdest, disp);
}
if (c->is_64) {
@@ -1285,6 +1300,10 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
tcg_temp_free_i64(t1);
}
+ tcg_temp_free_i64(next);
+ if (is_imm) {
+ tcg_temp_free_i64(cdest);
+ }
ret = DISAS_PC_UPDATED;
}
@@ -5827,7 +5846,8 @@ static void in2_a2(DisasContext *s, DisasOps *o)
static void in2_ri2(DisasContext *s, DisasOps *o)
{
- o->in2 = tcg_const_i64(s->base.pc_next + (int64_t)get_field(s, i2) * 2);
+ o->in2 = tcg_temp_new_i64();
+ gen_psw_addr_disp(s, o->in2, (int64_t)get_field(s, i2) * 2);
}
#define SPEC_in2_ri2 0
@@ -6306,8 +6326,11 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
#ifndef CONFIG_USER_ONLY
if (s->base.tb->flags & FLAG_MASK_PER) {
- TCGv_i64 addr = tcg_constant_i64(s->base.pc_next);
+ TCGv_i64 addr = tcg_temp_new_i64();
+
+ gen_psw_addr_disp(s, addr, 0);
gen_helper_per_ifetch(cpu_env, addr);
+ tcg_temp_free_i64(addr);
}
#endif
@@ -6428,7 +6451,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
if (s->base.tb->flags & FLAG_MASK_PER) {
/* An exception might be triggered, save PSW if not already done. */
if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) {
- tcg_gen_movi_i64(psw_addr, s->pc_tmp);
+ gen_psw_addr_disp(s, psw_addr, s->ilen);
}
/* Call the helper to check for a possible PER exception. */
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 07/26] target/s390x: Remove pc argument to pc_to_link_into
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (5 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 06/26] target/s390x: Introduce gen_psw_addr_disp Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-03 11:23 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 08/26] target/s390x: Use gen_psw_addr_disp in pc_to_link_info Richard Henderson
` (19 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x, Philippe Mathieu-Daudé
All callers pass s->pc_tmp.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 47a9d87416..7c98a72ddd 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -174,8 +174,10 @@ static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp)
tcg_gen_movi_i64(dest, s->base.pc_next + disp);
}
-static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc)
+static void pc_to_link_info(TCGv_i64 out, DisasContext *s)
{
+ uint64_t pc = s->pc_tmp;
+
if (s->base.tb->flags & FLAG_MASK_32) {
if (s->base.tb->flags & FLAG_MASK_64) {
tcg_gen_movi_i64(out, pc);
@@ -1534,7 +1536,7 @@ static DisasJumpType op_ni(DisasContext *s, DisasOps *o)
static DisasJumpType op_bas(DisasContext *s, DisasOps *o)
{
- pc_to_link_info(o->out, s, s->pc_tmp);
+ pc_to_link_info(o->out, s);
if (o->in2) {
tcg_gen_mov_i64(psw_addr, o->in2);
per_branch(s, false);
@@ -1549,7 +1551,7 @@ static void save_link_info(DisasContext *s, DisasOps *o)
TCGv_i64 t;
if (s->base.tb->flags & (FLAG_MASK_32 | FLAG_MASK_64)) {
- pc_to_link_info(o->out, s, s->pc_tmp);
+ pc_to_link_info(o->out, s);
return;
}
gen_op_calc_cc(s);
@@ -1579,7 +1581,7 @@ static DisasJumpType op_bal(DisasContext *s, DisasOps *o)
static DisasJumpType op_basi(DisasContext *s, DisasOps *o)
{
- pc_to_link_info(o->out, s, s->pc_tmp);
+ pc_to_link_info(o->out, s);
return help_goto_direct(s, (int64_t)get_field(s, i2) * 2);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 08/26] target/s390x: Use gen_psw_addr_disp in pc_to_link_info
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (6 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 07/26] target/s390x: Remove pc argument to pc_to_link_into Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-03 11:26 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 09/26] target/s390x: Use gen_psw_addr_disp in save_link_info Richard Henderson
` (18 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
This is slightly more complicated that a straight displacement
for 31 and 24-bit modes. Dont bother with a cant-happen assert.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 7c98a72ddd..4c3ea958d7 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -176,17 +176,20 @@ static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp)
static void pc_to_link_info(TCGv_i64 out, DisasContext *s)
{
- uint64_t pc = s->pc_tmp;
+ TCGv_i64 tmp;
- if (s->base.tb->flags & FLAG_MASK_32) {
- if (s->base.tb->flags & FLAG_MASK_64) {
- tcg_gen_movi_i64(out, pc);
- return;
- }
- pc |= 0x80000000;
+ if (s->base.tb->flags & FLAG_MASK_64) {
+ gen_psw_addr_disp(s, out, s->ilen);
+ return;
}
- assert(!(s->base.tb->flags & FLAG_MASK_64));
- tcg_gen_deposit_i64(out, out, tcg_constant_i64(pc), 0, 32);
+
+ tmp = tcg_temp_new_i64();
+ gen_psw_addr_disp(s, tmp, s->ilen);
+ if (s->base.tb->flags & FLAG_MASK_32) {
+ tcg_gen_ori_i64(tmp, tmp, 0x80000000);
+ }
+ tcg_gen_deposit_i64(out, out, tmp, 0, 32);
+ tcg_temp_free_i64(tmp);
}
static TCGv_i64 psw_addr;
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 09/26] target/s390x: Use gen_psw_addr_disp in save_link_info
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (7 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 08/26] target/s390x: Use gen_psw_addr_disp in pc_to_link_info Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-03 12:52 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 10/26] target/s390x: Use gen_psw_addr_disp in op_sam Richard Henderson
` (17 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x, Philippe Mathieu-Daudé
Trivial but non-mechanical conversion away from pc_tmp.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 4c3ea958d7..ad73a64b05 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -1558,9 +1558,11 @@ static void save_link_info(DisasContext *s, DisasOps *o)
return;
}
gen_op_calc_cc(s);
- tcg_gen_andi_i64(o->out, o->out, 0xffffffff00000000ull);
- tcg_gen_ori_i64(o->out, o->out, ((s->ilen / 2) << 30) | s->pc_tmp);
t = tcg_temp_new_i64();
+ tcg_gen_andi_i64(o->out, o->out, 0xffffffff00000000ull);
+ gen_psw_addr_disp(s, t, s->ilen);
+ tcg_gen_or_i64(o->out, o->out, t);
+ tcg_gen_ori_i64(o->out, o->out, (s->ilen / 2) << 30);
tcg_gen_shri_i64(t, psw_mask, 16);
tcg_gen_andi_i64(t, t, 0x0f000000);
tcg_gen_or_i64(o->out, o->out, t);
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 10/26] target/s390x: Use gen_psw_addr_disp in op_sam
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (8 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 09/26] target/s390x: Use gen_psw_addr_disp in save_link_info Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-03 13:11 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 11/26] target/s390x: Use ilen instead in branches Richard Henderson
` (16 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
Complicated because we may now require a runtime jump.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 40 +++++++++++++++++++++++++-----------
1 file changed, 28 insertions(+), 12 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index ad73a64b05..2ea3feb803 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -3922,7 +3922,7 @@ static DisasJumpType op_sacf(DisasContext *s, DisasOps *o)
static DisasJumpType op_sam(DisasContext *s, DisasOps *o)
{
int sam = s->insn->data;
- TCGv_i64 tsam;
+ TCGLabel *fault = NULL;
uint64_t mask;
switch (sam) {
@@ -3937,20 +3937,36 @@ static DisasJumpType op_sam(DisasContext *s, DisasOps *o)
break;
}
- /* Bizarre but true, we check the address of the current insn for the
- specification exception, not the next to be executed. Thus the PoO
- documents that Bad Things Happen two bytes before the end. */
- if (s->base.pc_next & ~mask) {
- gen_program_exception(s, PGM_SPECIFICATION);
- return DISAS_NORETURN;
- }
- s->pc_tmp &= mask;
+ /*
+ * Bizarre but true, we check the address of the current insn for the
+ * specification exception, not the next to be executed. Thus the PoO
+ * documents that Bad Things Happen two bytes before the end.
+ */
+ if (mask != -1) {
+ TCGv_i64 t = tcg_temp_new_i64();
+ fault = gen_new_label();
- tsam = tcg_constant_i64(sam);
- tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2);
+ gen_psw_addr_disp(s, t, 0);
+ tcg_gen_andi_i64(t, t, ~mask);
+ tcg_gen_brcondi_i64(TCG_COND_NE, t, 0, fault);
+ tcg_temp_free_i64(t);
+ }
+
+ update_cc_op(s);
+
+ tcg_gen_deposit_i64(psw_mask, psw_mask, tcg_constant_i64(sam), 31, 2);
+
+ gen_psw_addr_disp(s, psw_addr, s->ilen);
+ tcg_gen_andi_i64(psw_addr, psw_addr, mask);
/* Always exit the TB, since we (may have) changed execution mode. */
- return DISAS_TOO_MANY;
+ tcg_gen_lookup_and_goto_ptr();
+
+ if (mask != -1) {
+ gen_set_label(fault);
+ gen_program_exception(s, PGM_SPECIFICATION);
+ }
+ return DISAS_NORETURN;
}
static DisasJumpType op_sar(DisasContext *s, DisasOps *o)
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 11/26] target/s390x: Use ilen instead in branches
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (9 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 10/26] target/s390x: Use gen_psw_addr_disp in op_sam Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-03 13:13 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 12/26] target/s390x: Move masking of psw.addr to cpu_get_tb_cpu_state Richard Henderson
` (15 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
Remove the remaining uses of pc_tmp, and remove the variable.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 13 +++----------
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 2ea3feb803..67c86996e9 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -141,12 +141,6 @@ struct DisasContext {
TCGOp *insn_start;
DisasFields fields;
uint64_t ex_value;
- /*
- * During translate_one(), pc_tmp is used to determine the instruction
- * to be executed after base.pc_next - e.g. next sequential instruction
- * or a branch target.
- */
- uint64_t pc_tmp;
uint32_t ilen;
enum cc_op cc_op;
bool exit_to_mainloop;
@@ -1198,7 +1192,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
goto egress;
}
if (is_imm) {
- if (dest == s->pc_tmp) {
+ if (disp == s->ilen) {
/* Branch to next. */
per_branch(s, true);
ret = DISAS_NEXT;
@@ -1222,7 +1216,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
}
}
- if (use_goto_tb(s, s->pc_tmp)) {
+ if (use_goto_tb(s, s->base.pc_next + s->ilen)) {
if (is_imm && use_goto_tb(s, dest)) {
/* Both exits can use goto_tb. */
update_cc_op(s);
@@ -6247,7 +6241,6 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s)
g_assert_not_reached();
}
}
- s->pc_tmp = s->base.pc_next + ilen;
s->ilen = ilen;
/* We can't actually determine the insn format until we've looked up
@@ -6484,7 +6477,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
out:
/* Advance to the next instruction. */
- s->base.pc_next = s->pc_tmp;
+ s->base.pc_next += s->ilen;
return ret;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 12/26] target/s390x: Move masking of psw.addr to cpu_get_tb_cpu_state
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (10 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 11/26] target/s390x: Use ilen instead in branches Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-03 13:42 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 13/26] target/s390x: Add disp argument to update_psw_addr Richard Henderson
` (14 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
Masking after the fact in s390x_tr_init_disas_context
provides incorrect information to tb_lookup.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/cpu.h | 13 +++++++------
target/s390x/tcg/translate.c | 6 ------
2 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 7d6d01325b..b5c99bc694 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -379,17 +379,18 @@ static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
}
static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
- target_ulong *cs_base, uint32_t *flags)
+ target_ulong *cs_base, uint32_t *pflags)
{
- *pc = env->psw.addr;
- *cs_base = env->ex_value;
- *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
+ int flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
if (env->cregs[0] & CR0_AFP) {
- *flags |= FLAG_MASK_AFP;
+ flags |= FLAG_MASK_AFP;
}
if (env->cregs[0] & CR0_VECTOR) {
- *flags |= FLAG_MASK_VECTOR;
+ flags |= FLAG_MASK_VECTOR;
}
+ *pflags = flags;
+ *cs_base = env->ex_value;
+ *pc = (flags & FLAG_MASK_64 ? env->psw.addr : env->psw.addr & 0x7fffffff);
}
/* PER bits from control register 9 */
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 67c86996e9..9ee8146b87 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -6485,12 +6485,6 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- /* 31-bit mode */
- if (!(dc->base.tb->flags & FLAG_MASK_64)) {
- dc->base.pc_first &= 0x7fffffff;
- dc->base.pc_next = dc->base.pc_first;
- }
-
dc->cc_op = CC_OP_DYNAMIC;
dc->ex_value = dc->base.tb->cs_base;
dc->exit_to_mainloop = (dc->base.tb->flags & FLAG_MASK_PER) || dc->ex_value;
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 13/26] target/s390x: Add disp argument to update_psw_addr
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (11 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 12/26] target/s390x: Move masking of psw.addr to cpu_get_tb_cpu_state Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-03 13:44 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 14/26] target/s390x: Don't set gbea for user-only Richard Henderson
` (13 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
Rename to update_psw_addr_disp at the same time.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 9ee8146b87..a20c3bc4f0 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -336,9 +336,9 @@ static void return_low128(TCGv_i64 dest)
tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
}
-static void update_psw_addr(DisasContext *s)
+static void update_psw_addr_disp(DisasContext *s, int64_t disp)
{
- gen_psw_addr_disp(s, psw_addr, 0);
+ gen_psw_addr_disp(s, psw_addr, disp);
}
static void per_branch(DisasContext *s, bool to_next)
@@ -444,7 +444,7 @@ static void gen_program_exception(DisasContext *s, int code)
offsetof(CPUS390XState, int_pgm_ilen));
/* update the psw */
- update_psw_addr(s);
+ update_psw_addr_disp(s, 0);
/* Save off cc. */
update_cc_op(s);
@@ -1168,11 +1168,11 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp)
update_cc_op(s);
per_breaking_event(s);
tcg_gen_goto_tb(0);
- gen_psw_addr_disp(s, psw_addr, disp);
+ update_psw_addr_disp(s, disp);
tcg_gen_exit_tb(s->base.tb, 0);
return DISAS_NORETURN;
} else {
- gen_psw_addr_disp(s, psw_addr, disp);
+ update_psw_addr_disp(s, disp);
per_branch(s, false);
return DISAS_PC_UPDATED;
}
@@ -2448,7 +2448,7 @@ static DisasJumpType op_ex(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
- update_psw_addr(s);
+ update_psw_addr_disp(s, 0);
update_cc_op(s);
if (r1 == 0) {
@@ -3175,7 +3175,7 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOps *o)
/* In a parallel context, stop the world and single step. */
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
- update_psw_addr(s);
+ update_psw_addr_disp(s, 0);
update_cc_op(s);
gen_exception(EXCP_ATOMIC);
return DISAS_NORETURN;
@@ -4490,7 +4490,7 @@ static DisasJumpType op_stura(DisasContext *s, DisasOps *o)
tcg_gen_qemu_st_tl(o->in1, o->in2, MMU_REAL_IDX, s->insn->data);
if (s->base.tb->flags & FLAG_MASK_PER) {
- update_psw_addr(s);
+ update_psw_addr_disp(s, 0);
gen_helper_per_store_real(cpu_env);
}
return DISAS_NEXT;
@@ -4728,7 +4728,7 @@ static DisasJumpType op_svc(DisasContext *s, DisasOps *o)
{
TCGv_i32 t;
- update_psw_addr(s);
+ update_psw_addr_disp(s, 0);
update_cc_op(s);
t = tcg_constant_i32(get_field(s, i1) & 0xff);
@@ -6467,7 +6467,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
if (s->base.tb->flags & FLAG_MASK_PER) {
/* An exception might be triggered, save PSW if not already done. */
if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) {
- gen_psw_addr_disp(s, psw_addr, s->ilen);
+ update_psw_addr_disp(s, s->ilen);
}
/* Call the helper to check for a possible PER exception. */
@@ -6534,7 +6534,7 @@ static void s390x_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
case DISAS_NORETURN:
break;
case DISAS_TOO_MANY:
- update_psw_addr(dc);
+ update_psw_addr_disp(dc, 0);
/* FALLTHRU */
case DISAS_PC_UPDATED:
/* Next TB starts off with CC_OP_DYNAMIC, so make sure the
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 14/26] target/s390x: Don't set gbea for user-only
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (12 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 13/26] target/s390x: Add disp argument to update_psw_addr Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-03 13:46 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 15/26] target/s390x: Introduce per_enabled Richard Henderson
` (12 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
The rest of the per_* functions have this ifdef;
this one seemed to be missing.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index a20c3bc4f0..868895b9ae 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -384,7 +384,9 @@ static void per_branch_cond(DisasContext *s, TCGCond cond,
static void per_breaking_event(DisasContext *s)
{
+#ifndef CONFIG_USER_ONLY
gen_psw_addr_disp(s, gbea, 0);
+#endif
}
static void update_cc_op(DisasContext *s)
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 15/26] target/s390x: Introduce per_enabled
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (13 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 14/26] target/s390x: Don't set gbea for user-only Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-03 13:47 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 16/26] target/s390x: Disable conditional branch-to-next for PER Richard Henderson
` (11 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
Hoist the test of FLAG_MASK_PER to a helper.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 23 ++++++++++++++++-------
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 868895b9ae..cd311b4b2a 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -341,12 +341,21 @@ static void update_psw_addr_disp(DisasContext *s, int64_t disp)
gen_psw_addr_disp(s, psw_addr, disp);
}
+static inline bool per_enabled(DisasContext *s)
+{
+#ifdef CONFIG_USER_ONLY
+ return false;
+#else
+ return unlikely(s->base.tb->flags & FLAG_MASK_PER);
+#endif
+}
+
static void per_branch(DisasContext *s, bool to_next)
{
#ifndef CONFIG_USER_ONLY
gen_psw_addr_disp(s, gbea, 0);
- if (s->base.tb->flags & FLAG_MASK_PER) {
+ if (per_enabled(s)) {
if (to_next) {
TCGv_i64 next_pc = tcg_temp_new_i64();
@@ -364,7 +373,7 @@ static void per_branch_cond(DisasContext *s, TCGCond cond,
TCGv_i64 arg1, TCGv_i64 arg2)
{
#ifndef CONFIG_USER_ONLY
- if (s->base.tb->flags & FLAG_MASK_PER) {
+ if (per_enabled(s)) {
TCGLabel *lab = gen_new_label();
tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab);
@@ -665,7 +674,7 @@ static void gen_op_calc_cc(DisasContext *s)
static bool use_goto_tb(DisasContext *s, uint64_t dest)
{
- if (unlikely(s->base.tb->flags & FLAG_MASK_PER)) {
+ if (per_enabled(s)) {
return false;
}
return translator_use_goto_tb(&s->base, dest);
@@ -4491,7 +4500,7 @@ static DisasJumpType op_stura(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_st_tl(o->in1, o->in2, MMU_REAL_IDX, s->insn->data);
- if (s->base.tb->flags & FLAG_MASK_PER) {
+ if (per_enabled(s)) {
update_psw_addr_disp(s, 0);
gen_helper_per_store_real(cpu_env);
}
@@ -6343,7 +6352,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
}
#ifndef CONFIG_USER_ONLY
- if (s->base.tb->flags & FLAG_MASK_PER) {
+ if (per_enabled(s)) {
TCGv_i64 addr = tcg_temp_new_i64();
gen_psw_addr_disp(s, addr, 0);
@@ -6466,7 +6475,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
}
#ifndef CONFIG_USER_ONLY
- if (s->base.tb->flags & FLAG_MASK_PER) {
+ if (per_enabled(s)) {
/* An exception might be triggered, save PSW if not already done. */
if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) {
update_psw_addr_disp(s, s->ilen);
@@ -6489,7 +6498,7 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
dc->cc_op = CC_OP_DYNAMIC;
dc->ex_value = dc->base.tb->cs_base;
- dc->exit_to_mainloop = (dc->base.tb->flags & FLAG_MASK_PER) || dc->ex_value;
+ dc->exit_to_mainloop = per_enabled(dc) || dc->ex_value;
}
static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs)
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 16/26] target/s390x: Disable conditional branch-to-next for PER
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (14 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 15/26] target/s390x: Introduce per_enabled Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-03 14:32 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 17/26] target/s390x: Introduce help_goto_indirect Richard Henderson
` (10 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
For PER, we require a conditional call to helper_per_branch
for the conditional branch. Fold the remaining optimization
into a call to helper_goto_direct, which will take care of
the remaining gbea adjustment.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index cd311b4b2a..fc6b04e23e 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -1203,13 +1203,12 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
goto egress;
}
if (is_imm) {
- if (disp == s->ilen) {
- /* Branch to next. */
- per_branch(s, true);
- ret = DISAS_NEXT;
- goto egress;
- }
- if (c->cond == TCG_COND_ALWAYS) {
+ /*
+ * Do not optimize a conditional branch if PER enabled, because we
+ * still need a conditional call to helper_per_branch.
+ */
+ if (c->cond == TCG_COND_ALWAYS
+ || (disp == s->ilen && !per_enabled(s))) {
ret = help_goto_direct(s, disp);
goto egress;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 17/26] target/s390x: Introduce help_goto_indirect
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (15 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 16/26] target/s390x: Disable conditional branch-to-next for PER Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-30 10:15 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 18/26] target/s390x: Split per_branch Richard Henderson
` (9 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
Add a small helper to handle unconditional indirect jumps.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index fc6b04e23e..712f6d5795 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -1189,6 +1189,13 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp)
}
}
+static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest)
+{
+ tcg_gen_mov_i64(psw_addr, dest);
+ per_branch(s, false);
+ return DISAS_PC_UPDATED;
+}
+
static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
bool is_imm, int imm, TCGv_i64 cdest)
{
@@ -1219,9 +1226,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
goto egress;
}
if (c->cond == TCG_COND_ALWAYS) {
- tcg_gen_mov_i64(psw_addr, cdest);
- per_branch(s, false);
- ret = DISAS_PC_UPDATED;
+ ret = help_goto_indirect(s, cdest);
goto egress;
}
}
@@ -1545,9 +1550,7 @@ static DisasJumpType op_bas(DisasContext *s, DisasOps *o)
{
pc_to_link_info(o->out, s);
if (o->in2) {
- tcg_gen_mov_i64(psw_addr, o->in2);
- per_branch(s, false);
- return DISAS_PC_UPDATED;
+ return help_goto_indirect(s, o->in2);
} else {
return DISAS_NEXT;
}
@@ -1580,9 +1583,7 @@ static DisasJumpType op_bal(DisasContext *s, DisasOps *o)
{
save_link_info(s, o);
if (o->in2) {
- tcg_gen_mov_i64(psw_addr, o->in2);
- per_branch(s, false);
- return DISAS_PC_UPDATED;
+ return help_goto_indirect(s, o->in2);
} else {
return DISAS_NEXT;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 18/26] target/s390x: Split per_branch
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (16 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 17/26] target/s390x: Introduce help_goto_indirect Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-03 14:45 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 19/26] target/s390x: Simplify help_branch Richard Henderson
` (8 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
Split into per_branch_dest and per_branch_disp, which can be
used for direct and indirect. In preperation for TARGET_TB_PCREL,
call per_branch_* before indirect branches.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 32 ++++++++++++++++++--------------
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 712f6d5795..bd2ee1c96e 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -350,21 +350,25 @@ static inline bool per_enabled(DisasContext *s)
#endif
}
-static void per_branch(DisasContext *s, bool to_next)
+static void per_branch_dest(DisasContext *s, TCGv_i64 dest)
{
#ifndef CONFIG_USER_ONLY
gen_psw_addr_disp(s, gbea, 0);
+ if (s->base.tb->flags & FLAG_MASK_PER) {
+ gen_helper_per_branch(cpu_env, gbea, dest);
+ }
+#endif
+}
- if (per_enabled(s)) {
- if (to_next) {
- TCGv_i64 next_pc = tcg_temp_new_i64();
-
- gen_psw_addr_disp(s, next_pc, s->ilen);
- gen_helper_per_branch(cpu_env, gbea, next_pc);
- tcg_temp_free_i64(next_pc);
- } else {
- gen_helper_per_branch(cpu_env, gbea, psw_addr);
- }
+static void per_branch_disp(DisasContext *s, int64_t disp)
+{
+#ifndef CONFIG_USER_ONLY
+ gen_psw_addr_disp(s, gbea, 0);
+ if (s->base.tb->flags & FLAG_MASK_PER) {
+ TCGv_i64 dest = tcg_temp_new_i64();
+ gen_psw_addr_disp(s, dest, disp);
+ gen_helper_per_branch(cpu_env, gbea, dest);
+ tcg_temp_free_i64(dest);
}
#endif
}
@@ -1172,7 +1176,7 @@ struct DisasInsn {
static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp)
{
if (disp == s->ilen) {
- per_branch(s, true);
+ per_branch_disp(s, disp);
return DISAS_NEXT;
}
if (use_goto_tb(s, s->base.pc_next + disp)) {
@@ -1184,7 +1188,7 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp)
return DISAS_NORETURN;
} else {
update_psw_addr_disp(s, disp);
- per_branch(s, false);
+ per_branch_dest(s, psw_addr);
return DISAS_PC_UPDATED;
}
}
@@ -1192,7 +1196,7 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp)
static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest)
{
tcg_gen_mov_i64(psw_addr, dest);
- per_branch(s, false);
+ per_branch_dest(s, psw_addr);
return DISAS_PC_UPDATED;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 19/26] target/s390x: Simplify help_branch
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (17 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 18/26] target/s390x: Split per_branch Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-30 12:06 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 20/26] target/s390x: Split per_breaking_event from per_branch_* Richard Henderson
` (7 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
Always use a tcg branch, instead of movcond. The movcond
was not a bad idea before PER was added, but since then
we have either 2 or 3 actions to perform on each leg of
the branch, and multiple movcond is inefficient.
Reorder the taken branch to be fallthrough of the tcg branch.
This will be helpful later with TARGET_TB_PCREL.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 154 ++++++++++-------------------------
1 file changed, 44 insertions(+), 110 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index bd2ee1c96e..498dc2930d 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -373,28 +373,6 @@ static void per_branch_disp(DisasContext *s, int64_t disp)
#endif
}
-static void per_branch_cond(DisasContext *s, TCGCond cond,
- TCGv_i64 arg1, TCGv_i64 arg2)
-{
-#ifndef CONFIG_USER_ONLY
- if (per_enabled(s)) {
- TCGLabel *lab = gen_new_label();
- tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab);
-
- gen_psw_addr_disp(s, gbea, 0);
- gen_helper_per_branch(cpu_env, gbea, psw_addr);
-
- gen_set_label(lab);
- } else {
- TCGv_i64 pc = tcg_temp_new_i64();
-
- gen_psw_addr_disp(s, pc, 0);
- tcg_gen_movcond_i64(cond, gbea, arg1, arg2, gbea, pc);
- tcg_temp_free_i64(pc);
- }
-#endif
-}
-
static void per_breaking_event(DisasContext *s)
{
#ifndef CONFIG_USER_ONLY
@@ -1205,7 +1183,6 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
{
DisasJumpType ret;
int64_t disp = (int64_t)imm * 2;
- uint64_t dest = s->base.pc_next + disp;
TCGLabel *lab;
/* Take care of the special cases first. */
@@ -1235,96 +1212,53 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
}
}
- if (use_goto_tb(s, s->base.pc_next + s->ilen)) {
- if (is_imm && use_goto_tb(s, dest)) {
- /* Both exits can use goto_tb. */
- update_cc_op(s);
+ update_cc_op(s);
- lab = gen_new_label();
- if (c->is_64) {
- tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
- } else {
- tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
- }
-
- /* Branch not taken. */
- tcg_gen_goto_tb(0);
- gen_psw_addr_disp(s, psw_addr, s->ilen);
- tcg_gen_exit_tb(s->base.tb, 0);
-
- /* Branch taken. */
- gen_set_label(lab);
- per_breaking_event(s);
- tcg_gen_goto_tb(1);
- gen_psw_addr_disp(s, psw_addr, disp);
- tcg_gen_exit_tb(s->base.tb, 1);
-
- ret = DISAS_NORETURN;
- } else {
- /* Fallthru can use goto_tb, but taken branch cannot. */
- /* Store taken branch destination before the brcond. This
- avoids having to allocate a new local temp to hold it.
- We'll overwrite this in the not taken case anyway. */
- if (!is_imm) {
- tcg_gen_mov_i64(psw_addr, cdest);
- }
-
- lab = gen_new_label();
- if (c->is_64) {
- tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
- } else {
- tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
- }
-
- /* Branch not taken. */
- update_cc_op(s);
- tcg_gen_goto_tb(0);
- gen_psw_addr_disp(s, psw_addr, s->ilen);
- tcg_gen_exit_tb(s->base.tb, 0);
-
- gen_set_label(lab);
- if (is_imm) {
- gen_psw_addr_disp(s, psw_addr, disp);
- }
- per_breaking_event(s);
- ret = DISAS_PC_UPDATED;
- }
- } else {
- /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
- Most commonly we're single-stepping or some other condition that
- disables all use of goto_tb. Just update the PC and exit. */
-
- TCGv_i64 next = tcg_temp_new_i64();
-
- gen_psw_addr_disp(s, next, s->ilen);
- if (is_imm) {
- cdest = tcg_temp_new_i64();
- gen_psw_addr_disp(s, cdest, disp);
- }
-
- if (c->is_64) {
- tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
- cdest, next);
- per_branch_cond(s, c->cond, c->u.s64.a, c->u.s64.b);
- } else {
- TCGv_i32 t0 = tcg_temp_new_i32();
- TCGv_i64 t1 = tcg_temp_new_i64();
- TCGv_i64 z = tcg_constant_i64(0);
- tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
- tcg_gen_extu_i32_i64(t1, t0);
- tcg_temp_free_i32(t0);
- tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
- per_branch_cond(s, TCG_COND_NE, t1, z);
- tcg_temp_free_i64(t1);
- }
-
- tcg_temp_free_i64(next);
- if (is_imm) {
- tcg_temp_free_i64(cdest);
- }
- ret = DISAS_PC_UPDATED;
+ /*
+ * Store taken branch destination before the brcond. This
+ * avoids having to allocate a new local temp to hold it.
+ * We'll overwrite this in the not taken case anyway.
+ */
+ if (!is_imm) {
+ tcg_gen_mov_i64(psw_addr, cdest);
}
+ lab = gen_new_label();
+ if (c->is_64) {
+ tcg_gen_brcond_i64(tcg_invert_cond(c->cond),
+ c->u.s64.a, c->u.s64.b, lab);
+ } else {
+ tcg_gen_brcond_i32(tcg_invert_cond(c->cond),
+ c->u.s32.a, c->u.s32.b, lab);
+ }
+
+ /* Branch taken. */
+ if (is_imm) {
+ gen_psw_addr_disp(s, psw_addr, disp);
+ }
+ per_branch_dest(s, psw_addr);
+
+ if (is_imm && use_goto_tb(s, s->base.pc_next + disp)) {
+ tcg_gen_goto_tb(0);
+ tcg_gen_exit_tb(s->base.tb, 0);
+ } else {
+ tcg_gen_lookup_and_goto_ptr();
+ }
+
+ gen_set_label(lab);
+
+ /* Branch not taken. */
+ if (use_goto_tb(s, s->base.pc_next + s->ilen)) {
+ tcg_gen_goto_tb(1);
+ gen_psw_addr_disp(s, psw_addr, s->ilen);
+ tcg_gen_exit_tb(s->base.tb, 1);
+ } else {
+ gen_psw_addr_disp(s, psw_addr, s->ilen);
+ tcg_gen_lookup_and_goto_ptr();
+ }
+
+ ret = DISAS_NORETURN;
+
egress:
free_compare(c);
return ret;
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 20/26] target/s390x: Split per_breaking_event from per_branch_*
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (18 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 19/26] target/s390x: Simplify help_branch Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-30 12:14 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 21/26] target/s390x: Remove PER check from use_goto_tb Richard Henderson
` (6 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
This allows us to update gbea before other updates to psw_addr,
which will be important for TARGET_TB_PCREL.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 498dc2930d..a2315ac73e 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -353,7 +353,6 @@ static inline bool per_enabled(DisasContext *s)
static void per_branch_dest(DisasContext *s, TCGv_i64 dest)
{
#ifndef CONFIG_USER_ONLY
- gen_psw_addr_disp(s, gbea, 0);
if (s->base.tb->flags & FLAG_MASK_PER) {
gen_helper_per_branch(cpu_env, gbea, dest);
}
@@ -363,7 +362,6 @@ static void per_branch_dest(DisasContext *s, TCGv_i64 dest)
static void per_branch_disp(DisasContext *s, int64_t disp)
{
#ifndef CONFIG_USER_ONLY
- gen_psw_addr_disp(s, gbea, 0);
if (s->base.tb->flags & FLAG_MASK_PER) {
TCGv_i64 dest = tcg_temp_new_i64();
gen_psw_addr_disp(s, dest, disp);
@@ -1153,13 +1151,14 @@ struct DisasInsn {
static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp)
{
+ per_breaking_event(s);
+
if (disp == s->ilen) {
per_branch_disp(s, disp);
return DISAS_NEXT;
}
if (use_goto_tb(s, s->base.pc_next + disp)) {
update_cc_op(s);
- per_breaking_event(s);
tcg_gen_goto_tb(0);
update_psw_addr_disp(s, disp);
tcg_gen_exit_tb(s->base.tb, 0);
@@ -1173,6 +1172,7 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp)
static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest)
{
+ per_breaking_event(s);
tcg_gen_mov_i64(psw_addr, dest);
per_branch_dest(s, psw_addr);
return DISAS_PC_UPDATED;
@@ -1233,6 +1233,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
}
/* Branch taken. */
+ per_breaking_event(s);
if (is_imm) {
gen_psw_addr_disp(s, psw_addr, disp);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 21/26] target/s390x: Remove PER check from use_goto_tb
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (19 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 20/26] target/s390x: Split per_breaking_event from per_branch_* Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-30 17:33 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 22/26] target/s390x: Pass original r2 register to BCR Richard Henderson
` (5 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
While it is common for the PC update to happen in the
shadow of a goto_tb, it is not required to be there.
By moving it before the goto_tb, we can also place the
call to helper_per_branch there, and then afterward
chain to the next tb.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index a2315ac73e..e6c7c2a6ae 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -654,9 +654,6 @@ static void gen_op_calc_cc(DisasContext *s)
static bool use_goto_tb(DisasContext *s, uint64_t dest)
{
- if (per_enabled(s)) {
- return false;
- }
return translator_use_goto_tb(&s->base, dest);
}
@@ -1157,15 +1154,16 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp)
per_branch_disp(s, disp);
return DISAS_NEXT;
}
+
+ update_psw_addr_disp(s, disp);
+ per_branch_dest(s, psw_addr);
+
if (use_goto_tb(s, s->base.pc_next + disp)) {
update_cc_op(s);
tcg_gen_goto_tb(0);
- update_psw_addr_disp(s, disp);
tcg_gen_exit_tb(s->base.tb, 0);
return DISAS_NORETURN;
} else {
- update_psw_addr_disp(s, disp);
- per_branch_dest(s, psw_addr);
return DISAS_PC_UPDATED;
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 22/26] target/s390x: Pass original r2 register to BCR
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (20 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 21/26] target/s390x: Remove PER check from use_goto_tb Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-30 17:53 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 23/26] tcg: Pass TCGTempKind to tcg_temp_new_internal Richard Henderson
` (4 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
We do not modify any general-purpose registers in BCR,
which means that we may be able to avoid saving the
value across a branch.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/translate.c | 10 ++++++++++
target/s390x/tcg/insn-data.def | 2 +-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index e6c7c2a6ae..b27e34f712 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -5704,6 +5704,16 @@ static void in2_r2_nz(DisasContext *s, DisasOps *o)
}
#define SPEC_in2_r2_nz 0
+static void in2_r2_o_nz(DisasContext *s, DisasOps *o)
+{
+ int r2 = get_field(s, r2);
+ if (r2 != 0) {
+ o->in2 = regs[r2];
+ o->g_in2 = true;
+ }
+}
+#define SPEC_in2_r2_o_nz 0
+
static void in2_r2_8s(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
diff --git a/target/s390x/tcg/insn-data.def b/target/s390x/tcg/insn-data.def
index 6382ceabfc..79f9202ab2 100644
--- a/target/s390x/tcg/insn-data.def
+++ b/target/s390x/tcg/insn-data.def
@@ -121,7 +121,7 @@
/* BRANCH INDIRECT ON CONDITION */
C(0xe347, BIC, RXY_b, MIE2,0, m2_64w, 0, 0, bc, 0)
/* BRANCH ON CONDITION */
- C(0x0700, BCR, RR_b, Z, 0, r2_nz, 0, 0, bc, 0)
+ C(0x0700, BCR, RR_b, Z, 0, r2_o_nz, 0, 0, bc, 0)
C(0x4700, BC, RX_b, Z, 0, a2, 0, 0, bc, 0)
/* BRANCH RELATIVE ON CONDITION */
C(0xa704, BRC, RI_c, Z, 0, 0, 0, 0, bc, 0)
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 23/26] tcg: Pass TCGTempKind to tcg_temp_new_internal
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (21 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 22/26] target/s390x: Pass original r2 register to BCR Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-30 17:56 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 24/26] tcg: Introduce tcg_temp_ebb_new_* Richard Henderson
` (3 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x, Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 14 +++++++-------
tcg/tcg.c | 20 +++++++++++++++-----
2 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index d84bae6e3f..e01a47ec20 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -846,7 +846,7 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
intptr_t, const char *);
-TCGTemp *tcg_temp_new_internal(TCGType, bool);
+TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind kind);
void tcg_temp_free_internal(TCGTemp *);
TCGv_vec tcg_temp_new_vec(TCGType type);
TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
@@ -880,13 +880,13 @@ static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
static inline TCGv_i32 tcg_temp_new_i32(void)
{
- TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false);
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_NORMAL);
return temp_tcgv_i32(t);
}
static inline TCGv_i32 tcg_temp_local_new_i32(void)
{
- TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true);
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_LOCAL);
return temp_tcgv_i32(t);
}
@@ -899,13 +899,13 @@ static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
static inline TCGv_i64 tcg_temp_new_i64(void)
{
- TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false);
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_NORMAL);
return temp_tcgv_i64(t);
}
static inline TCGv_i64 tcg_temp_local_new_i64(void)
{
- TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true);
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_LOCAL);
return temp_tcgv_i64(t);
}
@@ -918,13 +918,13 @@ static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
static inline TCGv_ptr tcg_temp_new_ptr(void)
{
- TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false);
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_NORMAL);
return temp_tcgv_ptr(t);
}
static inline TCGv_ptr tcg_temp_local_new_ptr(void)
{
- TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true);
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_LOCAL);
return temp_tcgv_ptr(t);
}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 612a12f58f..acdbd5a9a2 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -942,14 +942,24 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
return ts;
}
-TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local)
+TCGTemp *tcg_temp_new_internal(TCGType type, TCGTempKind kind)
{
TCGContext *s = tcg_ctx;
- TCGTempKind kind = temp_local ? TEMP_LOCAL : TEMP_NORMAL;
TCGTemp *ts;
int idx, k;
- k = type + (temp_local ? TCG_TYPE_COUNT : 0);
+ switch (kind) {
+ case TEMP_NORMAL:
+ k = 0;
+ break;
+ case TEMP_LOCAL:
+ k = TCG_TYPE_COUNT;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ k += type;
+
idx = find_first_bit(s->free_temps[k].l, TCG_MAX_TEMPS);
if (idx < TCG_MAX_TEMPS) {
/* There is already an available temp with the right type. */
@@ -1008,7 +1018,7 @@ TCGv_vec tcg_temp_new_vec(TCGType type)
}
#endif
- t = tcg_temp_new_internal(type, 0);
+ t = tcg_temp_new_internal(type, TEMP_NORMAL);
return temp_tcgv_vec(t);
}
@@ -1019,7 +1029,7 @@ TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match)
tcg_debug_assert(t->temp_allocated != 0);
- t = tcg_temp_new_internal(t->base_type, 0);
+ t = tcg_temp_new_internal(t->base_type, TEMP_NORMAL);
return temp_tcgv_vec(t);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 24/26] tcg: Introduce tcg_temp_ebb_new_*
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (22 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 23/26] tcg: Pass TCGTempKind to tcg_temp_new_internal Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-30 18:07 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 25/26] tcg: Introduce tcg_temp_is_normal_* Richard Henderson
` (2 subsequent siblings)
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
Allow targets to allocate extended-basic-block temps.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op.h | 2 ++
include/tcg/tcg.h | 20 +++++++++++++++++++-
tcg/tcg.c | 16 ++++------------
3 files changed, 25 insertions(+), 13 deletions(-)
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 209e168305..0ebbee6e24 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -848,6 +848,7 @@ static inline void tcg_gen_plugin_cb_end(void)
#define tcg_temp_new() tcg_temp_new_i32()
#define tcg_global_mem_new tcg_global_mem_new_i32
#define tcg_temp_local_new() tcg_temp_local_new_i32()
+#define tcg_temp_ebb_new() tcg_temp_ebb_new_i32()
#define tcg_temp_free tcg_temp_free_i32
#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
@@ -855,6 +856,7 @@ static inline void tcg_gen_plugin_cb_end(void)
#define tcg_temp_new() tcg_temp_new_i64()
#define tcg_global_mem_new tcg_global_mem_new_i64
#define tcg_temp_local_new() tcg_temp_local_new_i64()
+#define tcg_temp_ebb_new() tcg_temp_ebb_new_i64()
#define tcg_temp_free tcg_temp_free_i64
#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index e01a47ec20..3835711d52 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -609,7 +609,7 @@ struct TCGContext {
#endif
GHashTable *const_table[TCG_TYPE_COUNT];
- TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
+ TCGTempSet free_temps[TCG_TYPE_COUNT * 3];
TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
QTAILQ_HEAD(, TCGOp) ops, free_ops;
@@ -890,6 +890,12 @@ static inline TCGv_i32 tcg_temp_local_new_i32(void)
return temp_tcgv_i32(t);
}
+static inline TCGv_i32 tcg_temp_ebb_new_i32(void)
+{
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB);
+ return temp_tcgv_i32(t);
+}
+
static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
const char *name)
{
@@ -909,6 +915,12 @@ static inline TCGv_i64 tcg_temp_local_new_i64(void)
return temp_tcgv_i64(t);
}
+static inline TCGv_i64 tcg_temp_ebb_new_i64(void)
+{
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB);
+ return temp_tcgv_i64(t);
+}
+
static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
const char *name)
{
@@ -928,6 +940,12 @@ static inline TCGv_ptr tcg_temp_local_new_ptr(void)
return temp_tcgv_ptr(t);
}
+static inline TCGv_ptr tcg_temp_ebb_new_ptr(void)
+{
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB);
+ return temp_tcgv_ptr(t);
+}
+
#if defined(CONFIG_DEBUG_TCG)
/* If you call tcg_clear_temp_count() at the start of a section of
* code which is not supposed to leak any TCG temporaries, then
diff --git a/tcg/tcg.c b/tcg/tcg.c
index acdbd5a9a2..7aa6cc3451 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -948,17 +948,8 @@ TCGTemp *tcg_temp_new_internal(TCGType type, TCGTempKind kind)
TCGTemp *ts;
int idx, k;
- switch (kind) {
- case TEMP_NORMAL:
- k = 0;
- break;
- case TEMP_LOCAL:
- k = TCG_TYPE_COUNT;
- break;
- default:
- g_assert_not_reached();
- }
- k += type;
+ assert(kind >= TEMP_NORMAL && kind <= TEMP_LOCAL);
+ k = TCG_TYPE_COUNT * kind + type;
idx = find_first_bit(s->free_temps[k].l, TCG_MAX_TEMPS);
if (idx < TCG_MAX_TEMPS) {
@@ -1046,6 +1037,7 @@ void tcg_temp_free_internal(TCGTemp *ts)
*/
return;
case TEMP_NORMAL:
+ case TEMP_EBB:
case TEMP_LOCAL:
break;
default:
@@ -1063,7 +1055,7 @@ void tcg_temp_free_internal(TCGTemp *ts)
ts->temp_allocated = 0;
idx = temp_idx(ts);
- k = ts->base_type + (ts->kind == TEMP_NORMAL ? 0 : TCG_TYPE_COUNT);
+ k = ts->base_type + ts->kind * TCG_TYPE_COUNT;
set_bit(idx, s->free_temps[k].l);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 25/26] tcg: Introduce tcg_temp_is_normal_*
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (23 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 24/26] tcg: Introduce tcg_temp_ebb_new_* Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-11-30 18:07 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 26/26] target/s390x: Enable TARGET_TB_PCREL Richard Henderson
2022-10-24 23:04 ` [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
26 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x, Philippe Mathieu-Daudé
Allow targets to determine if a given temp will die across a branch.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op.h | 2 ++
include/tcg/tcg.h | 15 +++++++++++++++
2 files changed, 17 insertions(+)
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 0ebbee6e24..4b06895a32 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -850,6 +850,7 @@ static inline void tcg_gen_plugin_cb_end(void)
#define tcg_temp_local_new() tcg_temp_local_new_i32()
#define tcg_temp_ebb_new() tcg_temp_ebb_new_i32()
#define tcg_temp_free tcg_temp_free_i32
+#define tcg_temp_is_normal tcg_temp_is_normal_i32
#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
#else
@@ -858,6 +859,7 @@ static inline void tcg_gen_plugin_cb_end(void)
#define tcg_temp_local_new() tcg_temp_local_new_i64()
#define tcg_temp_ebb_new() tcg_temp_ebb_new_i64()
#define tcg_temp_free tcg_temp_free_i64
+#define tcg_temp_is_normal tcg_temp_is_normal_i64
#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
#endif
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 3835711d52..0659c465da 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -871,6 +871,21 @@ static inline void tcg_temp_free_vec(TCGv_vec arg)
tcg_temp_free_internal(tcgv_vec_temp(arg));
}
+static inline bool tcg_temp_is_normal_i32(TCGv_i32 arg)
+{
+ return tcgv_i32_temp(arg)->kind == TEMP_NORMAL;
+}
+
+static inline bool tcg_temp_is_normal_i64(TCGv_i64 arg)
+{
+ return tcgv_i64_temp(arg)->kind == TEMP_NORMAL;
+}
+
+static inline bool tcg_temp_is_normal_ptr(TCGv_ptr arg)
+{
+ return tcgv_ptr_temp(arg)->kind == TEMP_NORMAL;
+}
+
static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
const char *name)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 26/26] target/s390x: Enable TARGET_TB_PCREL
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (24 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 25/26] tcg: Introduce tcg_temp_is_normal_* Richard Henderson
@ 2022-10-06 3:44 ` Richard Henderson
2022-10-24 23:04 ` [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
26 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2022-10-06 3:44 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/cpu-param.h | 1 +
target/s390x/cpu.c | 12 +++++
target/s390x/tcg/translate.c | 88 +++++++++++++++++++++++-------------
3 files changed, 69 insertions(+), 32 deletions(-)
diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h
index bf951a002e..467ecade8c 100644
--- a/target/s390x/cpu-param.h
+++ b/target/s390x/cpu-param.h
@@ -13,5 +13,6 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 64
#define TARGET_VIRT_ADDR_SPACE_BITS 64
#define NB_MMU_MODES 4
+#define TARGET_TB_PCREL 1
#endif
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index df00040e95..e77849dd50 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -35,6 +35,7 @@
#include "fpu/softfloat-helpers.h"
#include "disas/capstone.h"
#include "sysemu/tcg.h"
+#include "exec/exec-all.h"
#define CR0_RESET 0xE0UL
#define CR14_RESET 0xC2000000UL;
@@ -81,6 +82,16 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env)
return r;
}
+static void s390_cpu_synchronize_from_tb(CPUState *cs,
+ const TranslationBlock *tb)
+{
+ /* The program counter is always up to date with TARGET_TB_PCREL. */
+ if (!TARGET_TB_PCREL) {
+ S390CPU *cpu = S390_CPU(cs);
+ cpu->env.psw.addr = tb_pc(tb);
+ }
+}
+
static void s390_cpu_set_pc(CPUState *cs, vaddr value)
{
S390CPU *cpu = S390_CPU(cs);
@@ -272,6 +283,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
static const struct TCGCPUOps s390_tcg_ops = {
.initialize = s390x_translate_init,
+ .synchronize_from_tb = s390_cpu_synchronize_from_tb,
#ifdef CONFIG_USER_ONLY
.record_sigsegv = s390_cpu_record_sigsegv,
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index b27e34f712..c33dcc115d 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -139,6 +139,7 @@ struct DisasContext {
DisasContextBase base;
const DisasInsn *insn;
TCGOp *insn_start;
+ target_ulong pc_save;
DisasFields fields;
uint64_t ex_value;
uint32_t ilen;
@@ -163,29 +164,6 @@ static uint64_t inline_branch_hit[CC_OP_MAX];
static uint64_t inline_branch_miss[CC_OP_MAX];
#endif
-static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp)
-{
- tcg_gen_movi_i64(dest, s->base.pc_next + disp);
-}
-
-static void pc_to_link_info(TCGv_i64 out, DisasContext *s)
-{
- TCGv_i64 tmp;
-
- if (s->base.tb->flags & FLAG_MASK_64) {
- gen_psw_addr_disp(s, out, s->ilen);
- return;
- }
-
- tmp = tcg_temp_new_i64();
- gen_psw_addr_disp(s, tmp, s->ilen);
- if (s->base.tb->flags & FLAG_MASK_32) {
- tcg_gen_ori_i64(tmp, tmp, 0x80000000);
- }
- tcg_gen_deposit_i64(out, out, tmp, 0, 32);
- tcg_temp_free_i64(tmp);
-}
-
static TCGv_i64 psw_addr;
static TCGv_i64 psw_mask;
static TCGv_i64 gbea;
@@ -336,9 +314,39 @@ static void return_low128(TCGv_i64 dest)
tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
}
+static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp)
+{
+ assert(s->pc_save != -1);
+ if (TARGET_TB_PCREL) {
+ disp += s->base.pc_next - s->pc_save;
+ tcg_gen_addi_i64(dest, psw_addr, disp);
+ } else {
+ tcg_gen_movi_i64(dest, s->base.pc_next + disp);
+ }
+}
+
+static void pc_to_link_info(TCGv_i64 out, DisasContext *s)
+{
+ TCGv_i64 tmp;
+
+ if (s->base.tb->flags & FLAG_MASK_64) {
+ gen_psw_addr_disp(s, out, s->ilen);
+ return;
+ }
+
+ tmp = tcg_temp_new_i64();
+ gen_psw_addr_disp(s, tmp, s->ilen);
+ if (s->base.tb->flags & FLAG_MASK_32) {
+ tcg_gen_ori_i64(tmp, tmp, 0x80000000);
+ }
+ tcg_gen_deposit_i64(out, out, tmp, 0, 32);
+ tcg_temp_free_i64(tmp);
+}
+
static void update_psw_addr_disp(DisasContext *s, int64_t disp)
{
gen_psw_addr_disp(s, psw_addr, disp);
+ s->pc_save = s->base.pc_next + disp;
}
static inline bool per_enabled(DisasContext *s)
@@ -1172,6 +1180,7 @@ static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest)
{
per_breaking_event(s);
tcg_gen_mov_i64(psw_addr, dest);
+ s->pc_save = -1;
per_branch_dest(s, psw_addr);
return DISAS_PC_UPDATED;
}
@@ -1181,6 +1190,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
{
DisasJumpType ret;
int64_t disp = (int64_t)imm * 2;
+ TCGv_i64 cdest_save = NULL;
TCGLabel *lab;
/* Take care of the special cases first. */
@@ -1213,12 +1223,12 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
update_cc_op(s);
/*
- * Store taken branch destination before the brcond. This
- * avoids having to allocate a new local temp to hold it.
- * We'll overwrite this in the not taken case anyway.
+ * Save taken branch destination across the brcond if required.
*/
- if (!is_imm) {
- tcg_gen_mov_i64(psw_addr, cdest);
+ if (!is_imm && tcg_temp_is_normal_i64(cdest)) {
+ cdest_save = tcg_temp_ebb_new_i64();
+ tcg_gen_mov_i64(cdest_save, cdest);
+ cdest = cdest_save;
}
lab = gen_new_label();
@@ -1234,6 +1244,11 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
per_breaking_event(s);
if (is_imm) {
gen_psw_addr_disp(s, psw_addr, disp);
+ } else {
+ tcg_gen_mov_i64(psw_addr, cdest);
+ }
+ if (cdest_save) {
+ tcg_temp_free_i64(cdest_save);
}
per_branch_dest(s, psw_addr);
@@ -1247,15 +1262,15 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
gen_set_label(lab);
/* Branch not taken. */
+ gen_psw_addr_disp(s, psw_addr, s->ilen);
if (use_goto_tb(s, s->base.pc_next + s->ilen)) {
tcg_gen_goto_tb(1);
- gen_psw_addr_disp(s, psw_addr, s->ilen);
tcg_gen_exit_tb(s->base.tb, 1);
} else {
- gen_psw_addr_disp(s, psw_addr, s->ilen);
tcg_gen_lookup_and_goto_ptr();
}
+ s->pc_save = -1;
ret = DISAS_NORETURN;
egress:
@@ -6443,6 +6458,7 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
+ dc->pc_save = dc->base.pc_first;
dc->cc_op = CC_OP_DYNAMIC;
dc->ex_value = dc->base.tb->cs_base;
dc->exit_to_mainloop = per_enabled(dc) || dc->ex_value;
@@ -6455,9 +6471,13 @@ static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs)
static void s390x_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
+ target_ulong pc_arg = dc->base.pc_next;
+ if (TARGET_TB_PCREL) {
+ pc_arg &= ~TARGET_PAGE_MASK;
+ }
/* Delay the set of ilen until we've read the insn. */
- tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0);
+ tcg_gen_insn_start(pc_arg, dc->cc_op, 0);
dc->insn_start = tcg_last_op();
}
@@ -6548,7 +6568,11 @@ void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb,
{
int cc_op = data[1];
- env->psw.addr = data[0];
+ if (TARGET_TB_PCREL) {
+ env->psw.addr = (env->psw.addr & TARGET_PAGE_MASK) | data[0];
+ } else {
+ env->psw.addr = data[0];
+ }
/* Update the CC opcode if it is not already up-to-date. */
if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
--
2.34.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* Re: [PATCH 00/26] target/s390x: pc-relative translation blocks
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
` (25 preceding siblings ...)
2022-10-06 3:44 ` [PATCH 26/26] target/s390x: Enable TARGET_TB_PCREL Richard Henderson
@ 2022-10-24 23:04 ` Richard Henderson
26 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2022-10-24 23:04 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
Ping.
On 10/6/22 13:43, Richard Henderson wrote:
> This is the S390 specific changes required to reduce the
> amount of translation for address space randomization.
>
> Begin with some generic cleanups, then prepare by using
> displacements instead of addresses when possible, then
> add some tcg infrastructure to avoid a code gen ugly,
> then finalize the conversion.
>
>
> r~
>
>
> Richard Henderson (26):
> target/s390x: Use tcg_constant_* in local contexts
> target/s390x: Use tcg_constant_* for DisasCompare
> target/s390x: Use tcg_constant_i32 for fpinst_extract_m34
> target/s390x: Use tcg_constant_* in translate_vx.c.inc
> target/s390x: Change help_goto_direct to work on displacements
> target/s390x: Introduce gen_psw_addr_disp
> target/s390x: Remove pc argument to pc_to_link_into
> target/s390x: Use gen_psw_addr_disp in pc_to_link_info
> target/s390x: Use gen_psw_addr_disp in save_link_info
> target/s390x: Use gen_psw_addr_disp in op_sam
> target/s390x: Use ilen instead in branches
> target/s390x: Move masking of psw.addr to cpu_get_tb_cpu_state
> target/s390x: Add disp argument to update_psw_addr
> target/s390x: Don't set gbea for user-only
> target/s390x: Introduce per_enabled
> target/s390x: Disable conditional branch-to-next for PER
> target/s390x: Introduce help_goto_indirect
> target/s390x: Split per_branch
> target/s390x: Simplify help_branch
> target/s390x: Split per_breaking_event from per_branch_*
> target/s390x: Remove PER check from use_goto_tb
> target/s390x: Pass original r2 register to BCR
> tcg: Pass TCGTempKind to tcg_temp_new_internal
> tcg: Introduce tcg_temp_ebb_new_*
> tcg: Introduce tcg_temp_is_normal_*
> target/s390x: Enable TARGET_TB_PCREL
>
> include/tcg/tcg-op.h | 4 +
> include/tcg/tcg.h | 49 +-
> target/s390x/cpu-param.h | 1 +
> target/s390x/cpu.h | 13 +-
> target/s390x/cpu.c | 12 +
> target/s390x/tcg/translate.c | 858 ++++++++++++----------------
> tcg/tcg.c | 14 +-
> target/s390x/tcg/translate_vx.c.inc | 45 +-
> target/s390x/tcg/insn-data.def | 2 +-
> 9 files changed, 461 insertions(+), 537 deletions(-)
>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 01/26] target/s390x: Use tcg_constant_* in local contexts
2022-10-06 3:43 ` [PATCH 01/26] target/s390x: Use tcg_constant_* in local contexts Richard Henderson
@ 2022-11-03 10:38 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 10:38 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x, Philippe Mathieu-Daudé
On Wed, Oct 05, 2022 at 08:43:56PM -0700, Richard Henderson wrote:
> Replace tcg_const_* with tcg_constant_* in contexts
> where the free to remove is nearby.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 408 +++++++++++++----------------------
> 1 file changed, 145 insertions(+), 263 deletions(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 02/26] target/s390x: Use tcg_constant_* for DisasCompare
2022-10-06 3:43 ` [PATCH 02/26] target/s390x: Use tcg_constant_* for DisasCompare Richard Henderson
@ 2022-11-03 10:54 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 10:54 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:43:57PM -0700, Richard Henderson wrote:
> The a and b fields are not modified by the consumer,
> and while we need not free a constant, tcg will quietly
> ignore such frees, so free_compare need not be changed.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 44 ++++++++++++++++++------------------
> 1 file changed, 22 insertions(+), 22 deletions(-)
I did not check all the code paths in the consumer, but if there is a
bug and a or b ends up being modified, one of the temp_readonly()
assertions will catch it.
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 03/26] target/s390x: Use tcg_constant_i32 for fpinst_extract_m34
2022-10-06 3:43 ` [PATCH 03/26] target/s390x: Use tcg_constant_i32 for fpinst_extract_m34 Richard Henderson
@ 2022-11-03 10:56 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 10:56 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:43:58PM -0700, Richard Henderson wrote:
> Return a constant or NULL, which means the free may be
> removed from all callers of fpinst_extract_m34.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 26 +-------------------------
> 1 file changed, 1 insertion(+), 25 deletions(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 04/26] target/s390x: Use tcg_constant_* in translate_vx.c.inc
2022-10-06 3:43 ` [PATCH 04/26] target/s390x: Use tcg_constant_* in translate_vx.c.inc Richard Henderson
@ 2022-11-03 11:04 ` Ilya Leoshkevich
2022-11-03 23:05 ` Richard Henderson
0 siblings, 1 reply; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 11:04 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:43:59PM -0700, Richard Henderson wrote:
> In most cases, this is a simple local allocate and free
> replaced by tcg_constant_*. In three cases, a variable
> temp was initialized with a constant value -- reorg to
> localize the constant.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate_vx.c.inc | 45 +++++++++++++----------------
> 1 file changed, 20 insertions(+), 25 deletions(-)
...
> @@ -1359,7 +1359,7 @@ static DisasJumpType op_va(DisasContext *s, DisasOps *o)
> static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es)
> {
> const uint8_t msb_bit_nr = NUM_VEC_ELEMENT_BITS(es) - 1;
> - TCGv_i64 msb_mask = tcg_const_i64(dup_const(es, 1ull << msb_bit_nr));
> + TCGv_i64 msb_mask = tcg_constant_i64(dup_const(es, 1ull << msb_bit_nr));
> TCGv_i64 t1 = tcg_temp_new_i64();
> TCGv_i64 t2 = tcg_temp_new_i64();
> TCGv_i64 t3 = tcg_temp_new_i64();
This also fixes a leak, right?
...
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 05/26] target/s390x: Change help_goto_direct to work on displacements
2022-10-06 3:44 ` [PATCH 05/26] target/s390x: Change help_goto_direct to work on displacements Richard Henderson
@ 2022-11-03 11:13 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 11:13 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:00PM -0700, Richard Henderson wrote:
> In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 06/26] target/s390x: Introduce gen_psw_addr_disp
2022-10-06 3:44 ` [PATCH 06/26] target/s390x: Introduce gen_psw_addr_disp Richard Henderson
@ 2022-11-03 11:22 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 11:22 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:01PM -0700, Richard Henderson wrote:
> In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 69 ++++++++++++++++++++++++------------
> 1 file changed, 46 insertions(+), 23 deletions(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 07/26] target/s390x: Remove pc argument to pc_to_link_into
2022-10-06 3:44 ` [PATCH 07/26] target/s390x: Remove pc argument to pc_to_link_into Richard Henderson
@ 2022-11-03 11:23 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 11:23 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x, Philippe Mathieu-Daudé
On Wed, Oct 05, 2022 at 08:44:02PM -0700, Richard Henderson wrote:
> All callers pass s->pc_tmp.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 08/26] target/s390x: Use gen_psw_addr_disp in pc_to_link_info
2022-10-06 3:44 ` [PATCH 08/26] target/s390x: Use gen_psw_addr_disp in pc_to_link_info Richard Henderson
@ 2022-11-03 11:26 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 11:26 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:03PM -0700, Richard Henderson wrote:
> This is slightly more complicated that a straight displacement
> for 31 and 24-bit modes. Dont bother with a cant-happen assert.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 21 ++++++++++++---------
> 1 file changed, 12 insertions(+), 9 deletions(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 09/26] target/s390x: Use gen_psw_addr_disp in save_link_info
2022-10-06 3:44 ` [PATCH 09/26] target/s390x: Use gen_psw_addr_disp in save_link_info Richard Henderson
@ 2022-11-03 12:52 ` Ilya Leoshkevich
2022-11-03 13:00 ` [PATCH] tests/tcg/s390x: Add bal.S Ilya Leoshkevich
0 siblings, 1 reply; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 12:52 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x, Philippe Mathieu-Daudé
On Wed, Oct 05, 2022 at 08:44:04PM -0700, Richard Henderson wrote:
> Trivial but non-mechanical conversion away from pc_tmp.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
I was a bit worried about this sequence and wrote a regression test.
It did not find any issues, but I will post it here, might prove useful
some day.
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* [PATCH] tests/tcg/s390x: Add bal.S
2022-11-03 12:52 ` Ilya Leoshkevich
@ 2022-11-03 13:00 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 13:00 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Ilya Leoshkevich
Add a small test to prevent regressions.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
---
tests/tcg/s390x/Makefile.softmmu-target | 1 +
tests/tcg/s390x/bal.S | 24 ++++++++++++++++++++++++
2 files changed, 25 insertions(+)
create mode 100644 tests/tcg/s390x/bal.S
diff --git a/tests/tcg/s390x/Makefile.softmmu-target b/tests/tcg/s390x/Makefile.softmmu-target
index a34fa68473e..295df084919 100644
--- a/tests/tcg/s390x/Makefile.softmmu-target
+++ b/tests/tcg/s390x/Makefile.softmmu-target
@@ -7,3 +7,4 @@ QEMU_OPTS=-action panic=exit-failure -kernel
-Wl,--build-id=none $< -o $@
TESTS += unaligned-lowcore
+TESTS += bal
diff --git a/tests/tcg/s390x/bal.S b/tests/tcg/s390x/bal.S
new file mode 100644
index 00000000000..e54d8874ff9
--- /dev/null
+++ b/tests/tcg/s390x/bal.S
@@ -0,0 +1,24 @@
+ .org 0x200 /* lowcore padding */
+ .globl _start
+_start:
+ lpswe start24_psw
+_start24:
+ lgrl %r0,initial_r0
+ lgrl %r1,expected_r0
+ bal %r0,0f
+0:
+ cgrjne %r0,%r1,1f
+ lpswe success_psw
+1:
+ lpswe failure_psw
+ .align 8
+start24_psw:
+ .quad 0x160000000000,_start24 /* 24-bit mode, cc = 1, pm = 6 */
+initial_r0:
+ .quad 0x1234567887654321
+expected_r0:
+ .quad 0x1234567896000000 + 0b /* ilc = 2, cc = 1, pm = 6 */
+success_psw:
+ .quad 0x2000000000000,0xfff /* see is_special_wait_psw() */
+failure_psw:
+ .quad 0x2000000000000,0 /* disabled wait */
--
2.37.2
^ permalink raw reply related [flat|nested] 63+ messages in thread
* Re: [PATCH 10/26] target/s390x: Use gen_psw_addr_disp in op_sam
2022-10-06 3:44 ` [PATCH 10/26] target/s390x: Use gen_psw_addr_disp in op_sam Richard Henderson
@ 2022-11-03 13:11 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 13:11 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:05PM -0700, Richard Henderson wrote:
> Complicated because we may now require a runtime jump.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 40 +++++++++++++++++++++++++-----------
> 1 file changed, 28 insertions(+), 12 deletions(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 11/26] target/s390x: Use ilen instead in branches
2022-10-06 3:44 ` [PATCH 11/26] target/s390x: Use ilen instead in branches Richard Henderson
@ 2022-11-03 13:13 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 13:13 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:06PM -0700, Richard Henderson wrote:
> Remove the remaining uses of pc_tmp, and remove the variable.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 13 +++----------
> 1 file changed, 3 insertions(+), 10 deletions(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 12/26] target/s390x: Move masking of psw.addr to cpu_get_tb_cpu_state
2022-10-06 3:44 ` [PATCH 12/26] target/s390x: Move masking of psw.addr to cpu_get_tb_cpu_state Richard Henderson
@ 2022-11-03 13:42 ` Ilya Leoshkevich
2022-11-04 22:27 ` Richard Henderson
0 siblings, 1 reply; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 13:42 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:07PM -0700, Richard Henderson wrote:
> Masking after the fact in s390x_tr_init_disas_context
> provides incorrect information to tb_lookup.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/cpu.h | 13 +++++++------
> target/s390x/tcg/translate.c | 6 ------
> 2 files changed, 7 insertions(+), 12 deletions(-)
How can we end up in a situation where this matters? E.g. if we are in
64-bit mode and execute
0xa12345678: sam31
we will get a specification exception, and cpu_get_tb_cpu_state() will
not run. And for valid 31-bit addresses masking should be a no-op.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 13/26] target/s390x: Add disp argument to update_psw_addr
2022-10-06 3:44 ` [PATCH 13/26] target/s390x: Add disp argument to update_psw_addr Richard Henderson
@ 2022-11-03 13:44 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 13:44 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:08PM -0700, Richard Henderson wrote:
> Rename to update_psw_addr_disp at the same time.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 22 +++++++++++-----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 14/26] target/s390x: Don't set gbea for user-only
2022-10-06 3:44 ` [PATCH 14/26] target/s390x: Don't set gbea for user-only Richard Henderson
@ 2022-11-03 13:46 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 13:46 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:09PM -0700, Richard Henderson wrote:
> The rest of the per_* functions have this ifdef;
> this one seemed to be missing.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 15/26] target/s390x: Introduce per_enabled
2022-10-06 3:44 ` [PATCH 15/26] target/s390x: Introduce per_enabled Richard Henderson
@ 2022-11-03 13:47 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 13:47 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:10PM -0700, Richard Henderson wrote:
> Hoist the test of FLAG_MASK_PER to a helper.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 23 ++++++++++++++++-------
> 1 file changed, 16 insertions(+), 7 deletions(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 16/26] target/s390x: Disable conditional branch-to-next for PER
2022-10-06 3:44 ` [PATCH 16/26] target/s390x: Disable conditional branch-to-next for PER Richard Henderson
@ 2022-11-03 14:32 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 14:32 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:11PM -0700, Richard Henderson wrote:
> For PER, we require a conditional call to helper_per_branch
> for the conditional branch. Fold the remaining optimization
> into a call to helper_goto_direct, which will take care of
> the remaining gbea adjustment.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 13 ++++++-------
> 1 file changed, 6 insertions(+), 7 deletions(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 18/26] target/s390x: Split per_branch
2022-10-06 3:44 ` [PATCH 18/26] target/s390x: Split per_branch Richard Henderson
@ 2022-11-03 14:45 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-03 14:45 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:13PM -0700, Richard Henderson wrote:
> Split into per_branch_dest and per_branch_disp, which can be
> used for direct and indirect. In preperation for TARGET_TB_PCREL,
> call per_branch_* before indirect branches.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 32 ++++++++++++++++++--------------
> 1 file changed, 18 insertions(+), 14 deletions(-)
>
> diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
> index 712f6d5795..bd2ee1c96e 100644
> --- a/target/s390x/tcg/translate.c
> +++ b/target/s390x/tcg/translate.c
> @@ -350,21 +350,25 @@ static inline bool per_enabled(DisasContext *s)
> #endif
> }
>
> -static void per_branch(DisasContext *s, bool to_next)
> +static void per_branch_dest(DisasContext *s, TCGv_i64 dest)
> {
> #ifndef CONFIG_USER_ONLY
> gen_psw_addr_disp(s, gbea, 0);
> + if (s->base.tb->flags & FLAG_MASK_PER) {
> + gen_helper_per_branch(cpu_env, gbea, dest);
> + }
> +#endif
> +}
>
> - if (per_enabled(s)) {
> - if (to_next) {
> - TCGv_i64 next_pc = tcg_temp_new_i64();
> -
> - gen_psw_addr_disp(s, next_pc, s->ilen);
> - gen_helper_per_branch(cpu_env, gbea, next_pc);
> - tcg_temp_free_i64(next_pc);
> - } else {
> - gen_helper_per_branch(cpu_env, gbea, psw_addr);
> - }
> +static void per_branch_disp(DisasContext *s, int64_t disp)
> +{
> +#ifndef CONFIG_USER_ONLY
> + gen_psw_addr_disp(s, gbea, 0);
> + if (s->base.tb->flags & FLAG_MASK_PER) {
> + TCGv_i64 dest = tcg_temp_new_i64();
> + gen_psw_addr_disp(s, dest, disp);
> + gen_helper_per_branch(cpu_env, gbea, dest);
> + tcg_temp_free_i64(dest);
> }
> #endif
> }
...
Nit: maybe use per_enabled(s) instead of testing the mask manually?
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 04/26] target/s390x: Use tcg_constant_* in translate_vx.c.inc
2022-11-03 11:04 ` Ilya Leoshkevich
@ 2022-11-03 23:05 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2022-11-03 23:05 UTC (permalink / raw)
To: Ilya Leoshkevich, qemu-devel; +Cc: qemu-s390x
On 11/3/22 22:04, Ilya Leoshkevich wrote:
> On Wed, Oct 05, 2022 at 08:43:59PM -0700, Richard Henderson wrote:
>> In most cases, this is a simple local allocate and free
>> replaced by tcg_constant_*. In three cases, a variable
>> temp was initialized with a constant value -- reorg to
>> localize the constant.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/s390x/tcg/translate_vx.c.inc | 45 +++++++++++++----------------
>> 1 file changed, 20 insertions(+), 25 deletions(-)
>
> ...
>
>> @@ -1359,7 +1359,7 @@ static DisasJumpType op_va(DisasContext *s, DisasOps *o)
>> static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es)
>> {
>> const uint8_t msb_bit_nr = NUM_VEC_ELEMENT_BITS(es) - 1;
>> - TCGv_i64 msb_mask = tcg_const_i64(dup_const(es, 1ull << msb_bit_nr));
>> + TCGv_i64 msb_mask = tcg_constant_i64(dup_const(es, 1ull << msb_bit_nr));
>> TCGv_i64 t1 = tcg_temp_new_i64();
>> TCGv_i64 t2 = tcg_temp_new_i64();
>> TCGv_i64 t3 = tcg_temp_new_i64();
>
> This also fixes a leak, right?
Yes.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 12/26] target/s390x: Move masking of psw.addr to cpu_get_tb_cpu_state
2022-11-03 13:42 ` Ilya Leoshkevich
@ 2022-11-04 22:27 ` Richard Henderson
2022-11-29 1:49 ` Ilya Leoshkevich
0 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-11-04 22:27 UTC (permalink / raw)
To: Ilya Leoshkevich, qemu-devel; +Cc: qemu-s390x
On 11/4/22 00:42, Ilya Leoshkevich wrote:
> On Wed, Oct 05, 2022 at 08:44:07PM -0700, Richard Henderson wrote:
>> Masking after the fact in s390x_tr_init_disas_context
>> provides incorrect information to tb_lookup.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/s390x/cpu.h | 13 +++++++------
>> target/s390x/tcg/translate.c | 6 ------
>> 2 files changed, 7 insertions(+), 12 deletions(-)
>
> How can we end up in a situation where this matters? E.g. if we are in
> 64-bit mode and execute
>
> 0xa12345678: sam31
>
> we will get a specification exception, and cpu_get_tb_cpu_state() will
> not run. And for valid 31-bit addresses masking should be a no-op.
Ah, true. I was mislead by the presence of the code in s390x_tr_init_disas_context.
Perhaps a tcg_debug_assert or just a comment?
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 12/26] target/s390x: Move masking of psw.addr to cpu_get_tb_cpu_state
2022-11-04 22:27 ` Richard Henderson
@ 2022-11-29 1:49 ` Ilya Leoshkevich
2022-11-29 1:53 ` [PATCH] tests/tcg/s390x: Add sam.S Ilya Leoshkevich
0 siblings, 1 reply; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-29 1:49 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Sat, Nov 05, 2022 at 09:27:07AM +1100, Richard Henderson wrote:
> On 11/4/22 00:42, Ilya Leoshkevich wrote:
> > On Wed, Oct 05, 2022 at 08:44:07PM -0700, Richard Henderson wrote:
> > > Masking after the fact in s390x_tr_init_disas_context
> > > provides incorrect information to tb_lookup.
> > >
> > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> > > ---
> > > target/s390x/cpu.h | 13 +++++++------
> > > target/s390x/tcg/translate.c | 6 ------
> > > 2 files changed, 7 insertions(+), 12 deletions(-)
> >
> > How can we end up in a situation where this matters? E.g. if we are in
> > 64-bit mode and execute
> >
> > 0xa12345678: sam31
> >
> > we will get a specification exception, and cpu_get_tb_cpu_state() will
> > not run. And for valid 31-bit addresses masking should be a no-op.
>
> Ah, true. I was mislead by the presence of the code in
> s390x_tr_init_disas_context. Perhaps a tcg_debug_assert or just a comment?
An assert sounds good to me.
I tried the following diff with the attached test and it worked:
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -390,7 +390,12 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
}
*pflags = flags;
*cs_base = env->ex_value;
- *pc = (flags & FLAG_MASK_64 ? env->psw.addr : env->psw.addr & 0x7fffffff);
+ if (!(flags & FLAG_MASK_32)) {
+ g_assert(env->psw.addr <= 0xffffff);
+ } else if (!(flags & FLAG_MASK_64)) {
+ g_assert(env->psw.addr <= 0x7fffffff);
+ }
+ *pc = env->psw.addr;
}
/* PER bits from control register 9 */
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 24dc57a8816..a50453dd0d4 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -6464,6 +6464,12 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
+ if (!(dc->base.tb->flags & FLAG_MASK_32)) {
+ tcg_debug_assert(dc->base.pc_first <= 0xffffff);
+ } else if (!(dc->base.tb->flags & FLAG_MASK_64)) {
+ tcg_debug_assert(dc->base.pc_first <= 0x7fffffff);
+ }
+
dc->pc_save = dc->base.pc_first;
dc->cc_op = CC_OP_DYNAMIC;
dc->ex_value = dc->base.tb->cs_base;
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH] tests/tcg/s390x: Add sam.S
2022-11-29 1:49 ` Ilya Leoshkevich
@ 2022-11-29 1:53 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-29 1:53 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-s390x, qemu-devel, Ilya Leoshkevich
Add a small test to prevent regressions.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
---
tests/tcg/s390x/Makefile.softmmu-target | 1 +
tests/tcg/s390x/sam.S | 67 +++++++++++++++++++++++++
2 files changed, 68 insertions(+)
create mode 100644 tests/tcg/s390x/sam.S
diff --git a/tests/tcg/s390x/Makefile.softmmu-target b/tests/tcg/s390x/Makefile.softmmu-target
index a34fa68473e..738b04530fc 100644
--- a/tests/tcg/s390x/Makefile.softmmu-target
+++ b/tests/tcg/s390x/Makefile.softmmu-target
@@ -7,3 +7,4 @@ QEMU_OPTS=-action panic=exit-failure -kernel
-Wl,--build-id=none $< -o $@
TESTS += unaligned-lowcore
+TESTS += sam
diff --git a/tests/tcg/s390x/sam.S b/tests/tcg/s390x/sam.S
new file mode 100644
index 00000000000..4cab2dd2007
--- /dev/null
+++ b/tests/tcg/s390x/sam.S
@@ -0,0 +1,67 @@
+/* DAT on, home-space mode, 64-bit mode */
+#define DAT_PSWM 0x400c00180000000
+#define VIRTUAL_BASE 0x123456789abcd000
+
+ .org 0x8e
+program_interruption_code:
+ .org 0x150
+program_old_psw:
+ .org 0x1d0 /* program new PSW */
+ .quad 0,pgm_handler
+ .org 0x200 /* lowcore padding */
+
+ .globl _start
+_start:
+ lctlg %c13,%c13,hasce
+ lpswe dat_psw
+start_dat:
+ sam24
+sam24_suppressed:
+ /* sam24 should fail */
+fail:
+ basr %r12,%r0
+ lpswe failure_psw-.(%r12)
+pgm_handler:
+ chhsi program_interruption_code,6 /* specification exception? */
+ jne fail
+ clc suppressed_psw(16),program_old_psw /* correct location? */
+ jne fail
+ lpswe success_psw
+
+ .align 8
+dat_psw:
+ .quad DAT_PSWM,VIRTUAL_BASE+start_dat
+suppressed_psw:
+ .quad DAT_PSWM,VIRTUAL_BASE+sam24_suppressed
+success_psw:
+ .quad 0x2000000000000,0xfff /* see is_special_wait_psw() */
+failure_psw:
+ .quad 0x2000000000000,0 /* disabled wait */
+hasce:
+ /* DT = 0b11 (region-first-table), TL = 3 (2k entries) */
+ .quad region_first_table + (3 << 2) + 3
+ .align 0x1000
+region_first_table:
+ .org region_first_table + ((VIRTUAL_BASE >> 53) & 0x7ff) * 8
+ /* TT = 0b11 (region-first-table), TL = 3 (2k entries) */
+ .quad region_second_table + (3 << 2) + 3
+ .org region_first_table + 0x800 * 8
+region_second_table:
+ .org region_second_table + ((VIRTUAL_BASE >> 42) & 0x7ff) * 8
+ /* TT = 0b10 (region-second-table), TL = 3 (2k entries) */
+ .quad region_third_table + (2 << 2) + 3
+ .org region_second_table + 0x800 * 8
+region_third_table:
+ .org region_third_table + ((VIRTUAL_BASE >> 31) & 0x7ff) * 8
+ /* TT = 0b01 (region-third-table), TL = 3 (2k entries) */
+ .quad segment_table + (1 << 2) + 3
+ .org region_third_table + 0x800 * 8
+segment_table:
+ .org segment_table + ((VIRTUAL_BASE >> 20) & 0x7ff) * 8
+ /* TT = 0b00 (segment-table) */
+ .quad page_table
+ .org segment_table + 0x800 * 8
+page_table:
+ .org page_table + ((VIRTUAL_BASE >> 12) & 0xff) * 8
+ .quad 0
+ .org page_table + 0x100 * 8
--
2.38.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* Re: [PATCH 17/26] target/s390x: Introduce help_goto_indirect
2022-10-06 3:44 ` [PATCH 17/26] target/s390x: Introduce help_goto_indirect Richard Henderson
@ 2022-11-30 10:15 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-30 10:15 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:12PM -0700, Richard Henderson wrote:
> Add a small helper to handle unconditional indirect jumps.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 19 ++++++++++---------
> 1 file changed, 10 insertions(+), 9 deletions(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 19/26] target/s390x: Simplify help_branch
2022-10-06 3:44 ` [PATCH 19/26] target/s390x: Simplify help_branch Richard Henderson
@ 2022-11-30 12:06 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-30 12:06 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:14PM -0700, Richard Henderson wrote:
> Always use a tcg branch, instead of movcond. The movcond
> was not a bad idea before PER was added, but since then
> we have either 2 or 3 actions to perform on each leg of
> the branch, and multiple movcond is inefficient.
>
> Reorder the taken branch to be fallthrough of the tcg branch.
> This will be helpful later with TARGET_TB_PCREL.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 154 ++++++++++-------------------------
> 1 file changed, 44 insertions(+), 110 deletions(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 20/26] target/s390x: Split per_breaking_event from per_branch_*
2022-10-06 3:44 ` [PATCH 20/26] target/s390x: Split per_breaking_event from per_branch_* Richard Henderson
@ 2022-11-30 12:14 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-30 12:14 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:15PM -0700, Richard Henderson wrote:
> This allows us to update gbea before other updates to psw_addr,
> which will be important for TARGET_TB_PCREL.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 21/26] target/s390x: Remove PER check from use_goto_tb
2022-10-06 3:44 ` [PATCH 21/26] target/s390x: Remove PER check from use_goto_tb Richard Henderson
@ 2022-11-30 17:33 ` Ilya Leoshkevich
2022-11-30 17:46 ` [PATCH 1/2] target/s390x: Fix successful-branch PER events Ilya Leoshkevich
0 siblings, 1 reply; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-30 17:33 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:16PM -0700, Richard Henderson wrote:
> While it is common for the PC update to happen in the
> shadow of a goto_tb, it is not required to be there.
> By moving it before the goto_tb, we can also place the
> call to helper_per_branch there, and then afterward
> chain to the next tb.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
> index a2315ac73e..e6c7c2a6ae 100644
> --- a/target/s390x/tcg/translate.c
> +++ b/target/s390x/tcg/translate.c
> @@ -654,9 +654,6 @@ static void gen_op_calc_cc(DisasContext *s)
>
> static bool use_goto_tb(DisasContext *s, uint64_t dest)
> {
> - if (per_enabled(s)) {
> - return false;
> - }
> return translator_use_goto_tb(&s->base, dest);
> }
>
> @@ -1157,15 +1154,16 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp)
> per_branch_disp(s, disp);
> return DISAS_NEXT;
> }
> +
> + update_psw_addr_disp(s, disp);
> + per_branch_dest(s, psw_addr);
> +
> if (use_goto_tb(s, s->base.pc_next + disp)) {
> update_cc_op(s);
> tcg_gen_goto_tb(0);
> - update_psw_addr_disp(s, disp);
> tcg_gen_exit_tb(s->base.tb, 0);
> return DISAS_NORETURN;
> } else {
> - update_psw_addr_disp(s, disp);
> - per_branch_dest(s, psw_addr);
> return DISAS_PC_UPDATED;
> }
> }
> --
> 2.34.1
While looking at this, I had a hard time convincing myself that
successful-branch PER events work at all. The code does set
per_perc_atmid, but afterwards it does goto_tb/exit_tb, and does
not reach per_check_exception() added by translate_one().
I wrote a small test for this theory by turning on PER for
successful-branch events and looping 10 times. It passes in KVM, but
fails in TCG. Here is the relevant IR fragment:
IN:
0x00000212: a706 0000 brct %r0, 0x212
OP:
ld_i32 tmp0,env,$0xfffffffffffffff0
brcond_i32 tmp0,$0x0,lt,$L0
---- 0000000000000212 0000000000000004 0000000000000004
mov_i64 tmp2,psw_addr
call per_ifetch,$0x1,$0,env,tmp2
sub_i64 tmp2,r0,$0x1
extract2_i64 r0,r0,tmp2,$0x20
rotl_i64 r0,r0,$0x20
mov_i32 tmp0,tmp2
brcond_i32 tmp0,$0x0,eq,$L1
/* branch taken: set per_perc_atmid and exit */
mov_i64 gbea,psw_addr
call per_branch,$0x1,$0,env,gbea,psw_addr
goto_tb $0x0
exit_tb $0x7f73fc000400
set_label $L1
add_i64 psw_addr,psw_addr,$0x4
goto_tb $0x1
exit_tb $0x7f73fc000401
/* check per_perc_atmid */
call per_check_exception,$0x0,$0,env
set_label $L0
exit_tb $0x7f73fc000403
I will post the proposed fix and the test itself shortly.
That said, the patch makes sense to me and does not make things worse,
so:
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* [PATCH 1/2] target/s390x: Fix successful-branch PER events
2022-11-30 17:33 ` Ilya Leoshkevich
@ 2022-11-30 17:46 ` Ilya Leoshkevich
2022-11-30 17:46 ` [PATCH 2/2] tests/tcg/s390x: Add per.S Ilya Leoshkevich
0 siblings, 1 reply; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-30 17:46 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-s390x, Ilya Leoshkevich
The branching code sets per_perc_atmid, but afterwards it does
goto_tb/exit_tb, so per_check_exception() added by translate_one() is
not reached.
Fix by raising PER exception in per_branch().
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
---
target/s390x/tcg/misc_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c
index 71388a71197..b7220cef44b 100644
--- a/target/s390x/tcg/misc_helper.c
+++ b/target/s390x/tcg/misc_helper.c
@@ -619,6 +619,7 @@ void HELPER(per_branch)(CPUS390XState *env, uint64_t from, uint64_t to)
|| get_per_in_range(env, to)) {
env->per_address = from;
env->per_perc_atmid = PER_CODE_EVENT_BRANCH | get_per_atmid(env);
+ tcg_s390_program_interrupt(env, PGM_PER, GETPC());
}
}
}
--
2.38.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [PATCH 2/2] tests/tcg/s390x: Add per.S
2022-11-30 17:46 ` [PATCH 1/2] target/s390x: Fix successful-branch PER events Ilya Leoshkevich
@ 2022-11-30 17:46 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-30 17:46 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-s390x, Ilya Leoshkevich
Add a small test to avoid regressions.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
---
tests/tcg/s390x/Makefile.softmmu-target | 1 +
tests/tcg/s390x/per.S | 55 +++++++++++++++++++++++++
2 files changed, 56 insertions(+)
create mode 100644 tests/tcg/s390x/per.S
diff --git a/tests/tcg/s390x/Makefile.softmmu-target b/tests/tcg/s390x/Makefile.softmmu-target
index a34fa68473e..1d649753f4e 100644
--- a/tests/tcg/s390x/Makefile.softmmu-target
+++ b/tests/tcg/s390x/Makefile.softmmu-target
@@ -7,3 +7,4 @@ QEMU_OPTS=-action panic=exit-failure -kernel
-Wl,--build-id=none $< -o $@
TESTS += unaligned-lowcore
+TESTS += per
diff --git a/tests/tcg/s390x/per.S b/tests/tcg/s390x/per.S
new file mode 100644
index 00000000000..02f8422c44d
--- /dev/null
+++ b/tests/tcg/s390x/per.S
@@ -0,0 +1,55 @@
+#define N_ITERATIONS 10
+
+ .org 0x8d
+ilc:
+ .org 0x8e
+program_interruption_code:
+ .org 0x96
+per_code:
+ .org 0x150
+program_old_psw:
+ .org 0x1d0 /* program new PSW */
+ .quad 0,pgm_handler
+ .org 0x200 /* lowcore padding */
+
+ .globl _start
+_start:
+ lpswe per_on_psw
+start_per:
+ lghi %r0,N_ITERATIONS
+ xgr %r1,%r1
+ lctlg %c9,%c11,per_on_regs
+loop:
+ brct %r0,loop
+ lctlg %c9,%c11,per_off_regs
+ cgijne %r1,N_ITERATIONS-1,fail /* expected number of events? */
+ lpswe success_psw
+fail:
+ lpswe failure_psw
+
+pgm_handler:
+ chhsi program_interruption_code,0x80 /* PER event? */
+ jne fail
+ cli per_code,0x80 /* successful-branching event? */
+ jne fail
+ la %r1,1(%r1) /* increment event counter */
+ mvc return_psw(8),program_old_psw
+ lg %r3,program_old_psw+8
+ llgc %r2,ilc
+ sgr %r3,%r2 /* rewind PSW */
+ stg %r3,return_psw+8
+ lpswe return_psw
+
+ .align 8
+per_on_psw:
+ .quad 0x4000000000000000,start_per
+per_on_regs:
+ .quad 0x80000000,0,-1 /* successful-branching everywhere */
+per_off_regs:
+ .quad 0,0,0
+return_psw:
+ .quad 0,0
+success_psw:
+ .quad 0x2000000000000,0xfff /* see is_special_wait_psw() */
+failure_psw:
+ .quad 0x2000000000000,0 /* disabled wait */
--
2.38.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* Re: [PATCH 22/26] target/s390x: Pass original r2 register to BCR
2022-10-06 3:44 ` [PATCH 22/26] target/s390x: Pass original r2 register to BCR Richard Henderson
@ 2022-11-30 17:53 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-30 17:53 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:17PM -0700, Richard Henderson wrote:
> We do not modify any general-purpose registers in BCR,
> which means that we may be able to avoid saving the
> value across a branch.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/translate.c | 10 ++++++++++
> target/s390x/tcg/insn-data.def | 2 +-
> 2 files changed, 11 insertions(+), 1 deletion(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 23/26] tcg: Pass TCGTempKind to tcg_temp_new_internal
2022-10-06 3:44 ` [PATCH 23/26] tcg: Pass TCGTempKind to tcg_temp_new_internal Richard Henderson
@ 2022-11-30 17:56 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-30 17:56 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x, Philippe Mathieu-Daudé
On Wed, Oct 05, 2022 at 08:44:18PM -0700, Richard Henderson wrote:
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg.h | 14 +++++++-------
> tcg/tcg.c | 20 +++++++++++++++-----
> 2 files changed, 22 insertions(+), 12 deletions(-)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 24/26] tcg: Introduce tcg_temp_ebb_new_*
2022-10-06 3:44 ` [PATCH 24/26] tcg: Introduce tcg_temp_ebb_new_* Richard Henderson
@ 2022-11-30 18:07 ` Ilya Leoshkevich
2022-11-30 21:09 ` Richard Henderson
0 siblings, 1 reply; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-30 18:07 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On Wed, Oct 05, 2022 at 08:44:19PM -0700, Richard Henderson wrote:
> Allow targets to allocate extended-basic-block temps.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-op.h | 2 ++
> include/tcg/tcg.h | 20 +++++++++++++++++++-
> tcg/tcg.c | 16 ++++------------
> 3 files changed, 25 insertions(+), 13 deletions(-)
>
> diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
> index 209e168305..0ebbee6e24 100644
> --- a/include/tcg/tcg-op.h
> +++ b/include/tcg/tcg-op.h
> @@ -848,6 +848,7 @@ static inline void tcg_gen_plugin_cb_end(void)
> #define tcg_temp_new() tcg_temp_new_i32()
> #define tcg_global_mem_new tcg_global_mem_new_i32
> #define tcg_temp_local_new() tcg_temp_local_new_i32()
> +#define tcg_temp_ebb_new() tcg_temp_ebb_new_i32()
> #define tcg_temp_free tcg_temp_free_i32
> #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
> #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
> @@ -855,6 +856,7 @@ static inline void tcg_gen_plugin_cb_end(void)
> #define tcg_temp_new() tcg_temp_new_i64()
> #define tcg_global_mem_new tcg_global_mem_new_i64
> #define tcg_temp_local_new() tcg_temp_local_new_i64()
> +#define tcg_temp_ebb_new() tcg_temp_ebb_new_i64()
> #define tcg_temp_free tcg_temp_free_i64
> #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
> #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
> diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
> index e01a47ec20..3835711d52 100644
> --- a/include/tcg/tcg.h
> +++ b/include/tcg/tcg.h
> @@ -609,7 +609,7 @@ struct TCGContext {
> #endif
>
> GHashTable *const_table[TCG_TYPE_COUNT];
> - TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
> + TCGTempSet free_temps[TCG_TYPE_COUNT * 3];
> TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
>
> QTAILQ_HEAD(, TCGOp) ops, free_ops;
> @@ -890,6 +890,12 @@ static inline TCGv_i32 tcg_temp_local_new_i32(void)
> return temp_tcgv_i32(t);
> }
>
> +static inline TCGv_i32 tcg_temp_ebb_new_i32(void)
> +{
> + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB);
> + return temp_tcgv_i32(t);
> +}
> +
> static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
> const char *name)
> {
> @@ -909,6 +915,12 @@ static inline TCGv_i64 tcg_temp_local_new_i64(void)
> return temp_tcgv_i64(t);
> }
>
> +static inline TCGv_i64 tcg_temp_ebb_new_i64(void)
> +{
> + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB);
> + return temp_tcgv_i64(t);
> +}
> +
> static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
> const char *name)
> {
> @@ -928,6 +940,12 @@ static inline TCGv_ptr tcg_temp_local_new_ptr(void)
> return temp_tcgv_ptr(t);
> }
>
> +static inline TCGv_ptr tcg_temp_ebb_new_ptr(void)
> +{
> + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB);
> + return temp_tcgv_ptr(t);
> +}
> +
> #if defined(CONFIG_DEBUG_TCG)
> /* If you call tcg_clear_temp_count() at the start of a section of
> * code which is not supposed to leak any TCG temporaries, then
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index acdbd5a9a2..7aa6cc3451 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -948,17 +948,8 @@ TCGTemp *tcg_temp_new_internal(TCGType type, TCGTempKind kind)
> TCGTemp *ts;
> int idx, k;
>
> - switch (kind) {
> - case TEMP_NORMAL:
> - k = 0;
> - break;
> - case TEMP_LOCAL:
> - k = TCG_TYPE_COUNT;
> - break;
> - default:
> - g_assert_not_reached();
> - }
> - k += type;
> + assert(kind >= TEMP_NORMAL && kind <= TEMP_LOCAL);
Nit: maybe also add QEMU_BUILD_BUG_ON(TEMP_NORMAL != 0)
and QEMU_BUILD_BUG_ON(TEMP_LOCAL != 2), since we are using this for
0-based array indexing here? Alternatively, subtract TEMP_NORMAL
from kind.
> + k = TCG_TYPE_COUNT * kind + type;
>
> idx = find_first_bit(s->free_temps[k].l, TCG_MAX_TEMPS);
> if (idx < TCG_MAX_TEMPS) {
> @@ -1046,6 +1037,7 @@ void tcg_temp_free_internal(TCGTemp *ts)
> */
> return;
> case TEMP_NORMAL:
> + case TEMP_EBB:
> case TEMP_LOCAL:
> break;
> default:
> @@ -1063,7 +1055,7 @@ void tcg_temp_free_internal(TCGTemp *ts)
> ts->temp_allocated = 0;
>
> idx = temp_idx(ts);
> - k = ts->base_type + (ts->kind == TEMP_NORMAL ? 0 : TCG_TYPE_COUNT);
> + k = ts->base_type + ts->kind * TCG_TYPE_COUNT;
> set_bit(idx, s->free_temps[k].l);
> }
>
> --
> 2.34.1
>
>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
While not directly related to this patch, it would be good to update
tcg/README with all the new kinds of temporaries. E.g. the EBB ones are
not mentioned there:
TCG instructions operate on variables which are temporaries, local
temporaries or globals.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 25/26] tcg: Introduce tcg_temp_is_normal_*
2022-10-06 3:44 ` [PATCH 25/26] tcg: Introduce tcg_temp_is_normal_* Richard Henderson
@ 2022-11-30 18:07 ` Ilya Leoshkevich
0 siblings, 0 replies; 63+ messages in thread
From: Ilya Leoshkevich @ 2022-11-30 18:07 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x, Philippe Mathieu-Daudé
On Wed, Oct 05, 2022 at 08:44:20PM -0700, Richard Henderson wrote:
> Allow targets to determine if a given temp will die across a branch.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-op.h | 2 ++
> include/tcg/tcg.h | 15 +++++++++++++++
> 2 files changed, 17 insertions(+)
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 24/26] tcg: Introduce tcg_temp_ebb_new_*
2022-11-30 18:07 ` Ilya Leoshkevich
@ 2022-11-30 21:09 ` Richard Henderson
2022-12-01 19:13 ` Alex Bennée
0 siblings, 1 reply; 63+ messages in thread
From: Richard Henderson @ 2022-11-30 21:09 UTC (permalink / raw)
To: Ilya Leoshkevich, qemu-devel; +Cc: qemu-s390x
On 11/30/22 10:07, Ilya Leoshkevich wrote:
> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
>
> While not directly related to this patch, it would be good to update
> tcg/README with all the new kinds of temporaries. E.g. the EBB ones are
> not mentioned there:
>
> TCG instructions operate on variables which are temporaries, local
> temporaries or globals.
Thanks for the review on this.
I'm not sure I want to take this anymore. It's confusing to use. I really think what I
should do instead is improve the TCG register allocator.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 24/26] tcg: Introduce tcg_temp_ebb_new_*
2022-11-30 21:09 ` Richard Henderson
@ 2022-12-01 19:13 ` Alex Bennée
2022-12-01 20:34 ` Richard Henderson
0 siblings, 1 reply; 63+ messages in thread
From: Alex Bennée @ 2022-12-01 19:13 UTC (permalink / raw)
To: Richard Henderson; +Cc: Ilya Leoshkevich, qemu-s390x, qemu-devel
Richard Henderson <richard.henderson@linaro.org> writes:
> On 11/30/22 10:07, Ilya Leoshkevich wrote:
>> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
>> While not directly related to this patch, it would be good to update
>> tcg/README with all the new kinds of temporaries. E.g. the EBB ones are
>> not mentioned there:
>> TCG instructions operate on variables which are temporaries,
>> local
>> temporaries or globals.
>
> Thanks for the review on this.
>
> I'm not sure I want to take this anymore. It's confusing to use. I
> really think what I should do instead is improve the TCG register
> allocator.
Whats the ultimate aim for the rewrite? Hold values in target registers
over the extended block? What about avoid spills between potential fault
points?
>
>
> r~
--
Alex Bennée
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 24/26] tcg: Introduce tcg_temp_ebb_new_*
2022-12-01 19:13 ` Alex Bennée
@ 2022-12-01 20:34 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2022-12-01 20:34 UTC (permalink / raw)
To: Alex Bennée; +Cc: Ilya Leoshkevich, qemu-s390x, qemu-devel
On 12/1/22 11:13, Alex Bennée wrote:
>> I'm not sure I want to take this anymore. It's confusing to use. I
>> really think what I should do instead is improve the TCG register
>> allocator.
>
> Whats the ultimate aim for the rewrite? Hold values in target registers
> over the extended block? What about avoid spills between potential fault
> points?
Primary goal is to handle register allocation across basic blocks without front end
translators needing to consider "local" vs "temporary". Which would also allow any use of
branches in the middle-end, where we currently have to worry about accidentally killing
temporaries held by the front end. That's where this patch fails, in that it makes the
current situation even more complicated.
Secondary goal would be proper register allocation across basic blocks.
Tertiary goal would be single-assignment form, to allow better optimizations.
I'll have to do some research before committing to do anything in this area.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
end of thread, other threads:[~2022-12-01 20:34 UTC | newest]
Thread overview: 63+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-06 3:43 [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
2022-10-06 3:43 ` [PATCH 01/26] target/s390x: Use tcg_constant_* in local contexts Richard Henderson
2022-11-03 10:38 ` Ilya Leoshkevich
2022-10-06 3:43 ` [PATCH 02/26] target/s390x: Use tcg_constant_* for DisasCompare Richard Henderson
2022-11-03 10:54 ` Ilya Leoshkevich
2022-10-06 3:43 ` [PATCH 03/26] target/s390x: Use tcg_constant_i32 for fpinst_extract_m34 Richard Henderson
2022-11-03 10:56 ` Ilya Leoshkevich
2022-10-06 3:43 ` [PATCH 04/26] target/s390x: Use tcg_constant_* in translate_vx.c.inc Richard Henderson
2022-11-03 11:04 ` Ilya Leoshkevich
2022-11-03 23:05 ` Richard Henderson
2022-10-06 3:44 ` [PATCH 05/26] target/s390x: Change help_goto_direct to work on displacements Richard Henderson
2022-11-03 11:13 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 06/26] target/s390x: Introduce gen_psw_addr_disp Richard Henderson
2022-11-03 11:22 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 07/26] target/s390x: Remove pc argument to pc_to_link_into Richard Henderson
2022-11-03 11:23 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 08/26] target/s390x: Use gen_psw_addr_disp in pc_to_link_info Richard Henderson
2022-11-03 11:26 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 09/26] target/s390x: Use gen_psw_addr_disp in save_link_info Richard Henderson
2022-11-03 12:52 ` Ilya Leoshkevich
2022-11-03 13:00 ` [PATCH] tests/tcg/s390x: Add bal.S Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 10/26] target/s390x: Use gen_psw_addr_disp in op_sam Richard Henderson
2022-11-03 13:11 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 11/26] target/s390x: Use ilen instead in branches Richard Henderson
2022-11-03 13:13 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 12/26] target/s390x: Move masking of psw.addr to cpu_get_tb_cpu_state Richard Henderson
2022-11-03 13:42 ` Ilya Leoshkevich
2022-11-04 22:27 ` Richard Henderson
2022-11-29 1:49 ` Ilya Leoshkevich
2022-11-29 1:53 ` [PATCH] tests/tcg/s390x: Add sam.S Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 13/26] target/s390x: Add disp argument to update_psw_addr Richard Henderson
2022-11-03 13:44 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 14/26] target/s390x: Don't set gbea for user-only Richard Henderson
2022-11-03 13:46 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 15/26] target/s390x: Introduce per_enabled Richard Henderson
2022-11-03 13:47 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 16/26] target/s390x: Disable conditional branch-to-next for PER Richard Henderson
2022-11-03 14:32 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 17/26] target/s390x: Introduce help_goto_indirect Richard Henderson
2022-11-30 10:15 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 18/26] target/s390x: Split per_branch Richard Henderson
2022-11-03 14:45 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 19/26] target/s390x: Simplify help_branch Richard Henderson
2022-11-30 12:06 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 20/26] target/s390x: Split per_breaking_event from per_branch_* Richard Henderson
2022-11-30 12:14 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 21/26] target/s390x: Remove PER check from use_goto_tb Richard Henderson
2022-11-30 17:33 ` Ilya Leoshkevich
2022-11-30 17:46 ` [PATCH 1/2] target/s390x: Fix successful-branch PER events Ilya Leoshkevich
2022-11-30 17:46 ` [PATCH 2/2] tests/tcg/s390x: Add per.S Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 22/26] target/s390x: Pass original r2 register to BCR Richard Henderson
2022-11-30 17:53 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 23/26] tcg: Pass TCGTempKind to tcg_temp_new_internal Richard Henderson
2022-11-30 17:56 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 24/26] tcg: Introduce tcg_temp_ebb_new_* Richard Henderson
2022-11-30 18:07 ` Ilya Leoshkevich
2022-11-30 21:09 ` Richard Henderson
2022-12-01 19:13 ` Alex Bennée
2022-12-01 20:34 ` Richard Henderson
2022-10-06 3:44 ` [PATCH 25/26] tcg: Introduce tcg_temp_is_normal_* Richard Henderson
2022-11-30 18:07 ` Ilya Leoshkevich
2022-10-06 3:44 ` [PATCH 26/26] target/s390x: Enable TARGET_TB_PCREL Richard Henderson
2022-10-24 23:04 ` [PATCH 00/26] target/s390x: pc-relative translation blocks Richard Henderson
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