* [PATCH 00/12] Add support for the Cirrus Logic CS48L32 audio codecs @ 2022-11-09 16:53 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches The CS48L32 is a high-performance low-power audio DSP for smartphones and other portable audio devices. It has various digital audio I/O, a programmable Halo Core DSP, fixed-function audio processors, configurable GPIO and microphone bias regulators. The CS48L31 and CS48L33 were derivatives of the CS48L32. Piotr Stankiewicz (2): mfd: cs48l32: Add support for CS48L31/32/33 codecs pinctrl: cirrus: Add support for CS48L31/32/33 codecs Richard Fitzgerald (9): dt-bindings: mfd: Add Cirrus Logic CS48L32 audio codec mfd: cs48l32: Add register definitions for Cirrus Logic CS48L31/32/33 dt-bindings: pinctrl: Add Cirrus Logic CS48L31/32/33 regulator: arizona-micsupp: Don't hardcode use of ARIZONA defines regulator: arizona-micsupp: Don't use a common regulator name regulator: arizona-micsupp: Support Cirrus Logic CS48L31/32/33 irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs ASoC: wm_adsp: Allow client to hook into pre_run callback dt-bindings: sound: Add Cirrus Logic CS48L31/32/33 codecs Stuart Henderson (1): ASoC: cs48l32: Add codec driver for Cirrus Logic CS48L31/32/33 .../bindings/mfd/cirrus,cs48l32.yaml | 166 + .../bindings/pinctrl/cirrus,cs48l32.yaml | 98 + .../bindings/sound/cirrus,cs48l32.yaml | 96 + MAINTAINERS | 12 +- drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-cirrus-cs48l32.c | 281 ++ drivers/irqchip/irq-cirrus-cs48l32.h | 74 + drivers/mfd/Kconfig | 13 + drivers/mfd/Makefile | 2 + drivers/mfd/cs48l32-tables.c | 541 ++++ drivers/mfd/cs48l32.c | 434 +++ drivers/mfd/cs48l32.h | 28 + drivers/pinctrl/cirrus/Kconfig | 5 + drivers/pinctrl/cirrus/Makefile | 2 + drivers/pinctrl/cirrus/pinctrl-cs48l32.c | 932 ++++++ drivers/pinctrl/cirrus/pinctrl-cs48l32.h | 62 + drivers/regulator/Kconfig | 8 +- drivers/regulator/arizona-micsupp.c | 78 +- include/dt-bindings/sound/cs48l32.h | 25 + include/linux/irqchip/irq-cirrus-cs48l32.h | 101 + include/linux/mfd/cs48l32/core.h | 49 + include/linux/mfd/cs48l32/registers.h | 509 +++ include/sound/cs48l32.h | 89 + sound/soc/codecs/Kconfig | 9 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/cs48l32-core.c | 2782 +++++++++++++++++ sound/soc/codecs/cs48l32.c | 1211 +++++++ sound/soc/codecs/cs48l32.h | 386 +++ sound/soc/codecs/wm_adsp.c | 11 + sound/soc/codecs/wm_adsp.h | 1 + 31 files changed, 7997 insertions(+), 14 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml create mode 100644 Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml create mode 100644 drivers/irqchip/irq-cirrus-cs48l32.c create mode 100644 drivers/irqchip/irq-cirrus-cs48l32.h create mode 100644 drivers/mfd/cs48l32-tables.c create mode 100644 drivers/mfd/cs48l32.c create mode 100644 drivers/mfd/cs48l32.h create mode 100644 drivers/pinctrl/cirrus/pinctrl-cs48l32.c create mode 100644 drivers/pinctrl/cirrus/pinctrl-cs48l32.h create mode 100644 include/dt-bindings/sound/cs48l32.h create mode 100644 include/linux/irqchip/irq-cirrus-cs48l32.h create mode 100644 include/linux/mfd/cs48l32/core.h create mode 100644 include/linux/mfd/cs48l32/registers.h create mode 100644 include/sound/cs48l32.h create mode 100644 sound/soc/codecs/cs48l32-core.c create mode 100644 sound/soc/codecs/cs48l32.c create mode 100644 sound/soc/codecs/cs48l32.h -- 2.30.2 ^ permalink raw reply [flat|nested] 98+ messages in thread
* [PATCH 00/12] Add support for the Cirrus Logic CS48L32 audio codecs @ 2022-11-09 16:53 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio The CS48L32 is a high-performance low-power audio DSP for smartphones and other portable audio devices. It has various digital audio I/O, a programmable Halo Core DSP, fixed-function audio processors, configurable GPIO and microphone bias regulators. The CS48L31 and CS48L33 were derivatives of the CS48L32. Piotr Stankiewicz (2): mfd: cs48l32: Add support for CS48L31/32/33 codecs pinctrl: cirrus: Add support for CS48L31/32/33 codecs Richard Fitzgerald (9): dt-bindings: mfd: Add Cirrus Logic CS48L32 audio codec mfd: cs48l32: Add register definitions for Cirrus Logic CS48L31/32/33 dt-bindings: pinctrl: Add Cirrus Logic CS48L31/32/33 regulator: arizona-micsupp: Don't hardcode use of ARIZONA defines regulator: arizona-micsupp: Don't use a common regulator name regulator: arizona-micsupp: Support Cirrus Logic CS48L31/32/33 irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs ASoC: wm_adsp: Allow client to hook into pre_run callback dt-bindings: sound: Add Cirrus Logic CS48L31/32/33 codecs Stuart Henderson (1): ASoC: cs48l32: Add codec driver for Cirrus Logic CS48L31/32/33 .../bindings/mfd/cirrus,cs48l32.yaml | 166 + .../bindings/pinctrl/cirrus,cs48l32.yaml | 98 + .../bindings/sound/cirrus,cs48l32.yaml | 96 + MAINTAINERS | 12 +- drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-cirrus-cs48l32.c | 281 ++ drivers/irqchip/irq-cirrus-cs48l32.h | 74 + drivers/mfd/Kconfig | 13 + drivers/mfd/Makefile | 2 + drivers/mfd/cs48l32-tables.c | 541 ++++ drivers/mfd/cs48l32.c | 434 +++ drivers/mfd/cs48l32.h | 28 + drivers/pinctrl/cirrus/Kconfig | 5 + drivers/pinctrl/cirrus/Makefile | 2 + drivers/pinctrl/cirrus/pinctrl-cs48l32.c | 932 ++++++ drivers/pinctrl/cirrus/pinctrl-cs48l32.h | 62 + drivers/regulator/Kconfig | 8 +- drivers/regulator/arizona-micsupp.c | 78 +- include/dt-bindings/sound/cs48l32.h | 25 + include/linux/irqchip/irq-cirrus-cs48l32.h | 101 + include/linux/mfd/cs48l32/core.h | 49 + include/linux/mfd/cs48l32/registers.h | 509 +++ include/sound/cs48l32.h | 89 + sound/soc/codecs/Kconfig | 9 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/cs48l32-core.c | 2782 +++++++++++++++++ sound/soc/codecs/cs48l32.c | 1211 +++++++ sound/soc/codecs/cs48l32.h | 386 +++ sound/soc/codecs/wm_adsp.c | 11 + sound/soc/codecs/wm_adsp.h | 1 + 31 files changed, 7997 insertions(+), 14 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml create mode 100644 Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml create mode 100644 drivers/irqchip/irq-cirrus-cs48l32.c create mode 100644 drivers/irqchip/irq-cirrus-cs48l32.h create mode 100644 drivers/mfd/cs48l32-tables.c create mode 100644 drivers/mfd/cs48l32.c create mode 100644 drivers/mfd/cs48l32.h create mode 100644 drivers/pinctrl/cirrus/pinctrl-cs48l32.c create mode 100644 drivers/pinctrl/cirrus/pinctrl-cs48l32.h create mode 100644 include/dt-bindings/sound/cs48l32.h create mode 100644 include/linux/irqchip/irq-cirrus-cs48l32.h create mode 100644 include/linux/mfd/cs48l32/core.h create mode 100644 include/linux/mfd/cs48l32/registers.h create mode 100644 include/sound/cs48l32.h create mode 100644 sound/soc/codecs/cs48l32-core.c create mode 100644 sound/soc/codecs/cs48l32.c create mode 100644 sound/soc/codecs/cs48l32.h -- 2.30.2 ^ permalink raw reply [flat|nested] 98+ messages in thread
* [PATCH 01/12] dt-bindings: mfd: Add Cirrus Logic CS48L32 audio codec 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-09 16:53 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches, Richard Fitzgerald The CS48L32 has multiple digital and analog audio I/O, a high-performance low-power programmable audio DSP, and a variety of power-efficient fixed-function audio processors, with digital mixing and routing. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- .../bindings/mfd/cirrus,cs48l32.yaml | 166 ++++++++++++++++++ 1 file changed, 166 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml diff --git a/Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml new file mode 100644 index 000000000000..d128600c0b72 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/cirrus,cs48l32.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CS48L32 audio CODECs Multi-Functional Device + +maintainers: + - patches@opensource.cirrus.com + +description: | + The CS48L32 is an audio SoC with extensive digital capabilities + and a range of digital and analogue I/O. + + See also the child driver bindings in: + + bindings/pinctrl/cirrus,cs48l32.yaml + bindings/regulator/wlf,arizona.yaml + bindings/sound/cirrus,cs48l32.yaml + +allOf: + - $ref: /schemas/pinctrl/cirrus,cs48l32.yaml# + - $ref: /schemas/regulator/wlf,arizona.yaml# + - $ref: /schemas/sound/cirrus,cs48l32.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - cirrus,cs48l31 + - cirrus,cs48l32 + - cirrus,cs48l33 + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + description: + The first cell is the pin number. The second cell is reserved for + future use and must be zero + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + description: + The first cell is the IRQ number. + The second cell is the flags, encoded as the trigger masks from + bindings/interrupt-controller/interrupts.txt + const: 2 + + interrupts: + maxItems: 1 + + reset-gpios: + description: + One entry specifying the GPIO controlling /RESET. As defined in + bindings/gpio.txt. Although optional, it is strongly recommended + to use a hardware reset. + maxItems: 1 + + clocks: + description: + Should reference the clocks supplied on MCLK1 + minItems: 1 + maxItems: 1 + + clock-names: + description: | + Must be "mclk1" + const: mclk1 + + VDD_A-supply: + description: + Analogue power supply. + + VDD_D-supply: + description: + Digital core power supply. + + VDD_IO-supply: + description: + Digital buffer (I/O) supply. + + VDD_CP-supply: + description: + Charge pump power supply. + + VOUT_MIC-supply: + description: + Microphone power supply, normally supplied internally. + + pinctrl-0: + description: + A phandle to the node containing the subnodes containing pinctrl + configurations. + + pinctrl-1: + description: + A phandle to the node containing the subnodes containing pinctrl + configurations. + + pinctrl-names: + items: + - const: init + - const: default + +required: + - compatible + - interrupt-parent + - interrupts + - VDD_A-supply + - VDD_D-supply + - VDD_IO-supply + - VDD_CP-supply + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/sound/cs48l32.h> + &spi1 { + cs48l32: cs48l32@1 { + compatible = "cirrus,cs48l32"; + reg = <0x1>; + + spi-max-frequency = <25000000>; + + interrupts = <56 8>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio0>; + gpio-controller; + #gpio-cells = <2>; + #sound-dai-cells = <1>; + + VDD_A-supply = <®ulator_1v8>; + VDD_D-supply = <&lochnagar_1v2>; + VDD_IO-supply = <®ulator_1v8>; + VDD_CP-supply = <®ulator_1v8>; + + reset-gpios = <&gpio 0 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&cs48l32_defaults>; + + cs48l32_pinctrl: pinctrl { + compatible = "cirrus,cs48l32-pinctrl"; + + cs48l32_defaults: defaults { + asp1 { + groups = "asp1"; + function = "asp1"; + bias-bus-hold; + }; + asp2 { + groups = "asp2"; + function = "asp2"; + bias-bus-hold; + }; + }; + }; + }; -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 01/12] dt-bindings: mfd: Add Cirrus Logic CS48L32 audio codec @ 2022-11-09 16:53 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio, Richard Fitzgerald The CS48L32 has multiple digital and analog audio I/O, a high-performance low-power programmable audio DSP, and a variety of power-efficient fixed-function audio processors, with digital mixing and routing. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- .../bindings/mfd/cirrus,cs48l32.yaml | 166 ++++++++++++++++++ 1 file changed, 166 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml diff --git a/Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml new file mode 100644 index 000000000000..d128600c0b72 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/cirrus,cs48l32.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CS48L32 audio CODECs Multi-Functional Device + +maintainers: + - patches@opensource.cirrus.com + +description: | + The CS48L32 is an audio SoC with extensive digital capabilities + and a range of digital and analogue I/O. + + See also the child driver bindings in: + + bindings/pinctrl/cirrus,cs48l32.yaml + bindings/regulator/wlf,arizona.yaml + bindings/sound/cirrus,cs48l32.yaml + +allOf: + - $ref: /schemas/pinctrl/cirrus,cs48l32.yaml# + - $ref: /schemas/regulator/wlf,arizona.yaml# + - $ref: /schemas/sound/cirrus,cs48l32.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - cirrus,cs48l31 + - cirrus,cs48l32 + - cirrus,cs48l33 + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + description: + The first cell is the pin number. The second cell is reserved for + future use and must be zero + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + description: + The first cell is the IRQ number. + The second cell is the flags, encoded as the trigger masks from + bindings/interrupt-controller/interrupts.txt + const: 2 + + interrupts: + maxItems: 1 + + reset-gpios: + description: + One entry specifying the GPIO controlling /RESET. As defined in + bindings/gpio.txt. Although optional, it is strongly recommended + to use a hardware reset. + maxItems: 1 + + clocks: + description: + Should reference the clocks supplied on MCLK1 + minItems: 1 + maxItems: 1 + + clock-names: + description: | + Must be "mclk1" + const: mclk1 + + VDD_A-supply: + description: + Analogue power supply. + + VDD_D-supply: + description: + Digital core power supply. + + VDD_IO-supply: + description: + Digital buffer (I/O) supply. + + VDD_CP-supply: + description: + Charge pump power supply. + + VOUT_MIC-supply: + description: + Microphone power supply, normally supplied internally. + + pinctrl-0: + description: + A phandle to the node containing the subnodes containing pinctrl + configurations. + + pinctrl-1: + description: + A phandle to the node containing the subnodes containing pinctrl + configurations. + + pinctrl-names: + items: + - const: init + - const: default + +required: + - compatible + - interrupt-parent + - interrupts + - VDD_A-supply + - VDD_D-supply + - VDD_IO-supply + - VDD_CP-supply + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/sound/cs48l32.h> + &spi1 { + cs48l32: cs48l32@1 { + compatible = "cirrus,cs48l32"; + reg = <0x1>; + + spi-max-frequency = <25000000>; + + interrupts = <56 8>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio0>; + gpio-controller; + #gpio-cells = <2>; + #sound-dai-cells = <1>; + + VDD_A-supply = <®ulator_1v8>; + VDD_D-supply = <&lochnagar_1v2>; + VDD_IO-supply = <®ulator_1v8>; + VDD_CP-supply = <®ulator_1v8>; + + reset-gpios = <&gpio 0 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&cs48l32_defaults>; + + cs48l32_pinctrl: pinctrl { + compatible = "cirrus,cs48l32-pinctrl"; + + cs48l32_defaults: defaults { + asp1 { + groups = "asp1"; + function = "asp1"; + bias-bus-hold; + }; + asp2 { + groups = "asp2"; + function = "asp2"; + bias-bus-hold; + }; + }; + }; + }; -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* Re: [PATCH 01/12] dt-bindings: mfd: Add Cirrus Logic CS48L32 audio codec 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-09 21:09 ` Rob Herring -1 siblings, 0 replies; 98+ messages in thread From: Rob Herring @ 2022-11-09 21:09 UTC (permalink / raw) To: Richard Fitzgerald Cc: lee, patches, maz, krzysztof.kozlowski+dt, alsa-devel, linux-gpio, devicetree, broonie, linus.walleij, robh+dt, tglx, linux-kernel On Wed, 09 Nov 2022 16:53:20 +0000, Richard Fitzgerald wrote: > The CS48L32 has multiple digital and analog audio I/O, a > high-performance low-power programmable audio DSP, and a variety of > power-efficient fixed-function audio processors, with digital > mixing and routing. > > Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> > --- > .../bindings/mfd/cirrus,cs48l32.yaml | 166 ++++++++++++++++++ > 1 file changed, 166 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml:107:7: [warning] wrong indentation: expected 4 but found 6 (indentation) ./Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml:108:7: [warning] wrong indentation: expected 8 but found 6 (indentation) dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml: properties:clocks: 'oneOf' conditional failed, one must be fixed: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml: properties:clocks: 'anyOf' conditional failed, one must be fixed: 'minItems' is not one of ['maxItems', 'description', 'deprecated'] hint: Only "maxItems" is required for a single entry if there are no constraints defined for the values. 'minItems' is not one of ['description', 'deprecated', 'const', 'enum', 'minimum', 'maximum', 'multipleOf', 'default', '$ref', 'oneOf'] 'maxItems' is not one of ['description', 'deprecated', 'const', 'enum', 'minimum', 'maximum', 'multipleOf', 'default', '$ref', 'oneOf'] 1 is less than the minimum of 2 hint: Arrays must be described with a combination of minItems/maxItems/items hint: cell array properties must define how many entries and what the entries are when there is more than one entry. from schema $id: http://devicetree.org/meta-schemas/clocks.yaml# 'minItems' is not one of ['type', 'description', 'dependencies', 'dependentRequired', 'dependentSchemas', 'properties', 'patternProperties', 'additionalProperties', 'unevaluatedProperties', 'deprecated', 'required', 'allOf', 'anyOf', 'oneOf', '$ref'] 'maxItems' is not one of ['type', 'description', 'dependencies', 'dependentRequired', 'dependentSchemas', 'properties', 'patternProperties', 'additionalProperties', 'unevaluatedProperties', 'deprecated', 'required', 'allOf', 'anyOf', 'oneOf', '$ref'] 'type' is a required property hint: DT nodes ("object" type in schemas) can only use a subset of json-schema keywords from schema $id: http://devicetree.org/meta-schemas/clocks.yaml# ./Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/pinctrl/cirrus,cs48l32.yaml Documentation/devicetree/bindings/mfd/cirrus,cs48l32.example.dts:21:18: fatal error: dt-bindings/sound/cs48l32.h: No such file or directory 21 | #include <dt-bindings/sound/cs48l32.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:406: Documentation/devicetree/bindings/mfd/cirrus,cs48l32.example.dtb] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1492: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 01/12] dt-bindings: mfd: Add Cirrus Logic CS48L32 audio codec @ 2022-11-09 21:09 ` Rob Herring 0 siblings, 0 replies; 98+ messages in thread From: Rob Herring @ 2022-11-09 21:09 UTC (permalink / raw) To: Richard Fitzgerald Cc: devicetree, alsa-devel, patches, linus.walleij, lee, linux-kernel, robh+dt, linux-gpio, broonie, krzysztof.kozlowski+dt, maz, tglx On Wed, 09 Nov 2022 16:53:20 +0000, Richard Fitzgerald wrote: > The CS48L32 has multiple digital and analog audio I/O, a > high-performance low-power programmable audio DSP, and a variety of > power-efficient fixed-function audio processors, with digital > mixing and routing. > > Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> > --- > .../bindings/mfd/cirrus,cs48l32.yaml | 166 ++++++++++++++++++ > 1 file changed, 166 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml:107:7: [warning] wrong indentation: expected 4 but found 6 (indentation) ./Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml:108:7: [warning] wrong indentation: expected 8 but found 6 (indentation) dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml: properties:clocks: 'oneOf' conditional failed, one must be fixed: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml: properties:clocks: 'anyOf' conditional failed, one must be fixed: 'minItems' is not one of ['maxItems', 'description', 'deprecated'] hint: Only "maxItems" is required for a single entry if there are no constraints defined for the values. 'minItems' is not one of ['description', 'deprecated', 'const', 'enum', 'minimum', 'maximum', 'multipleOf', 'default', '$ref', 'oneOf'] 'maxItems' is not one of ['description', 'deprecated', 'const', 'enum', 'minimum', 'maximum', 'multipleOf', 'default', '$ref', 'oneOf'] 1 is less than the minimum of 2 hint: Arrays must be described with a combination of minItems/maxItems/items hint: cell array properties must define how many entries and what the entries are when there is more than one entry. from schema $id: http://devicetree.org/meta-schemas/clocks.yaml# 'minItems' is not one of ['type', 'description', 'dependencies', 'dependentRequired', 'dependentSchemas', 'properties', 'patternProperties', 'additionalProperties', 'unevaluatedProperties', 'deprecated', 'required', 'allOf', 'anyOf', 'oneOf', '$ref'] 'maxItems' is not one of ['type', 'description', 'dependencies', 'dependentRequired', 'dependentSchemas', 'properties', 'patternProperties', 'additionalProperties', 'unevaluatedProperties', 'deprecated', 'required', 'allOf', 'anyOf', 'oneOf', '$ref'] 'type' is a required property hint: DT nodes ("object" type in schemas) can only use a subset of json-schema keywords from schema $id: http://devicetree.org/meta-schemas/clocks.yaml# ./Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/pinctrl/cirrus,cs48l32.yaml Documentation/devicetree/bindings/mfd/cirrus,cs48l32.example.dts:21:18: fatal error: dt-bindings/sound/cs48l32.h: No such file or directory 21 | #include <dt-bindings/sound/cs48l32.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:406: Documentation/devicetree/bindings/mfd/cirrus,cs48l32.example.dtb] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1492: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 01/12] dt-bindings: mfd: Add Cirrus Logic CS48L32 audio codec 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-14 8:36 ` Krzysztof Kozlowski -1 siblings, 0 replies; 98+ messages in thread From: Krzysztof Kozlowski @ 2022-11-14 8:36 UTC (permalink / raw) To: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches On 09/11/2022 17:53, Richard Fitzgerald wrote: > The CS48L32 has multiple digital and analog audio I/O, a > high-performance low-power programmable audio DSP, and a variety of > power-efficient fixed-function audio processors, with digital > mixing and routing. > > Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> > --- > .../bindings/mfd/cirrus,cs48l32.yaml | 166 ++++++++++++++++++ > 1 file changed, 166 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml > > diff --git a/Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml > new file mode 100644 > index 000000000000..d128600c0b72 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml > @@ -0,0 +1,166 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mfd/cirrus,cs48l32.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Cirrus Logic CS48L32 audio CODECs Multi-Functional Device > + > +maintainers: > + - patches@opensource.cirrus.com > + > +description: | > + The CS48L32 is an audio SoC with extensive digital capabilities > + and a range of digital and analogue I/O. > + > + See also the child driver bindings in: > + > + bindings/pinctrl/cirrus,cs48l32.yaml > + bindings/regulator/wlf,arizona.yaml > + bindings/sound/cirrus,cs48l32.yaml > + > +allOf: > + - $ref: /schemas/pinctrl/cirrus,cs48l32.yaml# There is no such file. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 01/12] dt-bindings: mfd: Add Cirrus Logic CS48L32 audio codec @ 2022-11-14 8:36 ` Krzysztof Kozlowski 0 siblings, 0 replies; 98+ messages in thread From: Krzysztof Kozlowski @ 2022-11-14 8:36 UTC (permalink / raw) To: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio On 09/11/2022 17:53, Richard Fitzgerald wrote: > The CS48L32 has multiple digital and analog audio I/O, a > high-performance low-power programmable audio DSP, and a variety of > power-efficient fixed-function audio processors, with digital > mixing and routing. > > Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> > --- > .../bindings/mfd/cirrus,cs48l32.yaml | 166 ++++++++++++++++++ > 1 file changed, 166 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml > > diff --git a/Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml > new file mode 100644 > index 000000000000..d128600c0b72 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml > @@ -0,0 +1,166 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mfd/cirrus,cs48l32.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Cirrus Logic CS48L32 audio CODECs Multi-Functional Device > + > +maintainers: > + - patches@opensource.cirrus.com > + > +description: | > + The CS48L32 is an audio SoC with extensive digital capabilities > + and a range of digital and analogue I/O. > + > + See also the child driver bindings in: > + > + bindings/pinctrl/cirrus,cs48l32.yaml > + bindings/regulator/wlf,arizona.yaml > + bindings/sound/cirrus,cs48l32.yaml > + > +allOf: > + - $ref: /schemas/pinctrl/cirrus,cs48l32.yaml# There is no such file. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 98+ messages in thread
* [PATCH 02/12] mfd: cs48l32: Add register definitions for Cirrus Logic CS48L31/32/33 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-09 16:53 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches, Richard Fitzgerald This adds the register definitions for the CS48L31/32/33. The CS48L31/32/33 audio codecs are multi-function devices containing gpios, irq controller and regulators in addition to the core audio functionality. Signed-off-by: Piotr Stankiewicz <piotrs@opensource.cirrus.com> Signed-off-by: Stuart Henderson <stuarth@opensource.cirrus.com> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- include/linux/mfd/cs48l32/registers.h | 509 ++++++++++++++++++++++++++ 1 file changed, 509 insertions(+) create mode 100644 include/linux/mfd/cs48l32/registers.h diff --git a/include/linux/mfd/cs48l32/registers.h b/include/linux/mfd/cs48l32/registers.h new file mode 100644 index 000000000000..b8125950d74c --- /dev/null +++ b/include/linux/mfd/cs48l32/registers.h @@ -0,0 +1,509 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Register definitions for Cirrus Logic CS48L32 + * + * Copyright (C) 2017-2018, 2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef CS48L32_REGISTERS_H +#define CS48L32_REGISTERS_H + +/* Register Addresses. */ +#define CS48L32_DEVID 0x0 +#define CS48L32_REVID 0x4 +#define CS48L32_OTPID 0x10 +#define CS48L32_SFT_RESET 0x20 +#define CS48L32_CTRL_IF_DEBUG3 0xA8 +#define CS48L32_MCU_CTRL1 0x804 +#define CS48L32_GPIO1_CTRL1 0xc08 +#define CS48L32_GPIO16_CTRL1 0xc44 +#define CS48L32_OUTPUT_SYS_CLK 0x1020 +#define CS48L32_AUXPDM_CTRL 0x1044 +#define CS48L32_AUXPDM_CTRL2 0x105c +#define CS48L32_CLOCK32K 0x1400 +#define CS48L32_SYSTEM_CLOCK1 0x1404 +#define CS48L32_SYSTEM_CLOCK2 0x1408 +#define CS48L32_SAMPLE_RATE1 0x1420 +#define CS48L32_SAMPLE_RATE2 0x1424 +#define CS48L32_SAMPLE_RATE3 0x1428 +#define CS48L32_SAMPLE_RATE4 0x142c +#define CS48L32_DSP_CLOCK1 0x1510 +#define CS48L32_FLL1_CONTROL1 0x1c00 +#define CS48L32_FLL1_CONTROL5 0x1c10 +#define CS48L32_FLL1_CONTROL6 0x1c14 +#define CS48L32_FLL1_GPIO_CLOCK 0x1ca0 +#define CS48L32_CHARGE_PUMP1 0x2000 +#define CS48L32_LDO2_CTRL1 0x2408 +#define CS48L32_MICBIAS_CTRL1 0x2410 +#define CS48L32_MICBIAS_CTRL5 0x2418 +#define CS48L32_IRQ1_CTRL_AOD 0x2710 +#define CS48L32_AOD_PAD_CTRL 0x2718 +#define CS48L32_INPUT_CONTROL 0x4000 +#define CS48L32_INPUT_STATUS 0x4004 +#define CS48L32_INPUT_RATE_CONTROL 0x4008 +#define CS48L32_INPUT_CONTROL2 0x400c +#define CS48L32_INPUT_CONTROL3 0x4014 +#define CS48L32_INPUT1_CONTROL1 0x4020 +#define CS48L32_IN1L_CONTROL1 0x4024 +#define CS48L32_IN1L_CONTROL2 0x4028 +#define CS48L32_IN1R_CONTROL1 0x4044 +#define CS48L32_IN1R_CONTROL2 0x4048 +#define CS48L32_INPUT2_CONTROL1 0x4060 +#define CS48L32_IN2L_CONTROL1 0x4064 +#define CS48L32_IN2L_CONTROL2 0x4068 +#define CS48L32_IN2R_CONTROL1 0x4084 +#define CS48L32_IN2R_CONTROL2 0x4088 +#define CS48L32_INPUT_HPF_CONTROL 0x4244 +#define CS48L32_INPUT_VOL_CONTROL 0x4248 +#define CS48L32_AUXPDM_CONTROL1 0x4300 +#define CS48L32_AUXPDM_CONTROL2 0x4304 +#define CS48L32_AUXPDM1_CONTROL1 0x4308 +#define CS48L32_AUXPDM2_CONTROL1 0x4310 +#define CS48L32_ADC1L_ANA_CONTROL1 0x4688 +#define CS48L32_ADC1R_ANA_CONTROL1 0x468c +#define CS48L32_ASP1_ENABLES1 0x6000 +#define CS48L32_ASP1_DATA_CONTROL5 0x6040 +#define CS48L32_ASP2_ENABLES1 0x6080 +#define CS48L32_ASP2_DATA_CONTROL5 0x60c0 +#define CS48L32_ASP1TX1_INPUT1 0x8200 +#define CS48L32_ASP1TX2_INPUT1 0x8210 +#define CS48L32_ASP1TX3_INPUT1 0x8220 +#define CS48L32_ASP1TX4_INPUT1 0x8230 +#define CS48L32_ASP1TX5_INPUT1 0x8240 +#define CS48L32_ASP1TX6_INPUT1 0x8250 +#define CS48L32_ASP1TX7_INPUT1 0x8260 +#define CS48L32_ASP1TX8_INPUT1 0x8270 +#define CS48L32_ASP1TX8_INPUT4 0x827c +#define CS48L32_ASP2TX1_INPUT1 0x8300 +#define CS48L32_ASP2TX2_INPUT1 0x8310 +#define CS48L32_ASP2TX3_INPUT1 0x8320 +#define CS48L32_ASP2TX4_INPUT1 0x8330 +#define CS48L32_ASP2TX4_INPUT4 0x833c +#define CS48L32_ISRC1INT1_INPUT1 0x8980 +#define CS48L32_ISRC1INT2_INPUT1 0x8990 +#define CS48L32_ISRC1INT3_INPUT1 0x89a0 +#define CS48L32_ISRC1INT4_INPUT1 0x89b0 +#define CS48L32_ISRC1DEC1_INPUT1 0x89c0 +#define CS48L32_ISRC1DEC2_INPUT1 0x89d0 +#define CS48L32_ISRC1DEC3_INPUT1 0x89e0 +#define CS48L32_ISRC1DEC4_INPUT1 0x89f0 +#define CS48L32_ISRC2INT1_INPUT1 0x8a00 +#define CS48L32_ISRC2INT2_INPUT1 0x8a10 +#define CS48L32_ISRC2DEC1_INPUT1 0x8a40 +#define CS48L32_ISRC2DEC2_INPUT1 0x8a50 +#define CS48L32_ISRC3INT1_INPUT1 0x8a80 +#define CS48L32_ISRC3INT2_INPUT1 0x8a90 +#define CS48L32_ISRC3DEC1_INPUT1 0x8ac0 +#define CS48L32_ISRC3DEC2_INPUT1 0x8ad0 +#define CS48L32_EQ1_INPUT1 0x8b80 +#define CS48L32_EQ2_INPUT1 0x8b90 +#define CS48L32_EQ3_INPUT1 0x8ba0 +#define CS48L32_EQ4_INPUT1 0x8bb0 +#define CS48L32_EQ4_INPUT4 0x8bbc +#define CS48L32_DRC1L_INPUT1 0x8c00 +#define CS48L32_DRC1R_INPUT1 0x8c10 +#define CS48L32_DRC1R_INPUT4 0x8c1c +#define CS48L32_DRC2L_INPUT1 0x8c20 +#define CS48L32_DRC2R_INPUT1 0x8c30 +#define CS48L32_DRC2R_INPUT4 0x8c3c +#define CS48L32_LHPF1_INPUT1 0x8c80 +#define CS48L32_LHPF1_INPUT4 0x8c8c +#define CS48L32_LHPF2_INPUT1 0x8c90 +#define CS48L32_LHPF2_INPUT4 0x8c9c +#define CS48L32_LHPF3_INPUT1 0x8ca0 +#define CS48L32_LHPF3_INPUT4 0x8cac +#define CS48L32_LHPF4_INPUT1 0x8cb0 +#define CS48L32_LHPF4_INPUT4 0x8cbc +#define CS48L32_DSP1RX1_INPUT1 0x9000 +#define CS48L32_DSP1RX2_INPUT1 0x9010 +#define CS48L32_DSP1RX3_INPUT1 0x9020 +#define CS48L32_DSP1RX4_INPUT1 0x9030 +#define CS48L32_DSP1RX5_INPUT1 0x9040 +#define CS48L32_DSP1RX6_INPUT1 0x9050 +#define CS48L32_DSP1RX7_INPUT1 0x9060 +#define CS48L32_DSP1RX8_INPUT1 0x9070 +#define CS48L32_DSP1RX8_INPUT4 0x907c +#define CS48L32_ISRC1_CONTROL1 0xa400 +#define CS48L32_ISRC1_CONTROL2 0xa404 +#define CS48L32_ISRC2_CONTROL1 0xa510 +#define CS48L32_ISRC2_CONTROL2 0xa514 +#define CS48L32_ISRC3_CONTROL1 0xa620 +#define CS48L32_ISRC3_CONTROL2 0xa624 +#define CS48L32_FX_SAMPLE_RATE 0xa800 +#define CS48L32_EQ_CONTROL1 0xa808 +#define CS48L32_EQ_CONTROL2 0xa80c +#define CS48L32_EQ1_GAIN1 0xa810 +#define CS48L32_EQ1_GAIN2 0xa814 +#define CS48L32_EQ1_BAND1_COEFF1 0xa818 +#define CS48L32_EQ1_BAND1_COEFF2 0xa81c +#define CS48L32_EQ1_BAND1_PG 0xa820 +#define CS48L32_EQ1_BAND2_COEFF1 0xa824 +#define CS48L32_EQ1_BAND2_COEFF2 0xa828 +#define CS48L32_EQ1_BAND2_PG 0xa82c +#define CS48L32_EQ1_BAND3_COEFF1 0xa830 +#define CS48L32_EQ1_BAND3_COEFF2 0xa834 +#define CS48L32_EQ1_BAND3_PG 0xa838 +#define CS48L32_EQ1_BAND4_COEFF1 0xa83c +#define CS48L32_EQ1_BAND4_COEFF2 0xa840 +#define CS48L32_EQ1_BAND4_PG 0xa844 +#define CS48L32_EQ1_BAND5_COEFF1 0xa848 +#define CS48L32_EQ1_BAND5_PG 0xa850 +#define CS48L32_EQ2_GAIN1 0xa854 +#define CS48L32_EQ2_GAIN2 0xa858 +#define CS48L32_EQ2_BAND1_COEFF1 0xa85c +#define CS48L32_EQ2_BAND1_COEFF2 0xa860 +#define CS48L32_EQ2_BAND1_PG 0xa864 +#define CS48L32_EQ2_BAND2_COEFF1 0xa868 +#define CS48L32_EQ2_BAND2_COEFF2 0xa86c +#define CS48L32_EQ2_BAND2_PG 0xa870 +#define CS48L32_EQ2_BAND3_COEFF1 0xa874 +#define CS48L32_EQ2_BAND3_COEFF2 0xa878 +#define CS48L32_EQ2_BAND3_PG 0xa87c +#define CS48L32_EQ2_BAND4_COEFF1 0xa880 +#define CS48L32_EQ2_BAND4_COEFF2 0xa884 +#define CS48L32_EQ2_BAND4_PG 0xa888 +#define CS48L32_EQ2_BAND5_COEFF1 0xa88c +#define CS48L32_EQ2_BAND5_PG 0xa894 +#define CS48L32_EQ3_GAIN1 0xa898 +#define CS48L32_EQ3_GAIN2 0xa89c +#define CS48L32_EQ3_BAND1_COEFF1 0xa8a0 +#define CS48L32_EQ3_BAND1_COEFF2 0xa8a4 +#define CS48L32_EQ3_BAND1_PG 0xa8a8 +#define CS48L32_EQ3_BAND2_COEFF1 0xa8ac +#define CS48L32_EQ3_BAND2_COEFF2 0xa8b0 +#define CS48L32_EQ3_BAND2_PG 0xa8b4 +#define CS48L32_EQ3_BAND3_COEFF1 0xa8b8 +#define CS48L32_EQ3_BAND3_COEFF2 0xa8bc +#define CS48L32_EQ3_BAND3_PG 0xa8c0 +#define CS48L32_EQ3_BAND4_COEFF1 0xa8c4 +#define CS48L32_EQ3_BAND4_COEFF2 0xa8c8 +#define CS48L32_EQ3_BAND4_PG 0xa8cc +#define CS48L32_EQ3_BAND5_COEFF1 0xa8d0 +#define CS48L32_EQ3_BAND5_PG 0xa8d8 +#define CS48L32_EQ4_GAIN1 0xa8dc +#define CS48L32_EQ4_GAIN2 0xa8e0 +#define CS48L32_EQ4_BAND1_COEFF1 0xa8e4 +#define CS48L32_EQ4_BAND1_COEFF2 0xa8e8 +#define CS48L32_EQ4_BAND1_PG 0xa8ec +#define CS48L32_EQ4_BAND2_COEFF1 0xa8f0 +#define CS48L32_EQ4_BAND2_COEFF2 0xa8f4 +#define CS48L32_EQ4_BAND2_PG 0xa8f8 +#define CS48L32_EQ4_BAND3_COEFF1 0xa8fc +#define CS48L32_EQ4_BAND3_COEFF2 0xa900 +#define CS48L32_EQ4_BAND3_PG 0xa904 +#define CS48L32_EQ4_BAND4_COEFF1 0xa908 +#define CS48L32_EQ4_BAND4_COEFF2 0xa90c +#define CS48L32_EQ4_BAND4_PG 0xa910 +#define CS48L32_EQ4_BAND5_COEFF1 0xa914 +#define CS48L32_EQ4_BAND5_PG 0xa91c +#define CS48L32_LHPF_CONTROL1 0xaa30 +#define CS48L32_LHPF_CONTROL2 0xaa34 +#define CS48L32_LHPF1_COEFF 0xaa38 +#define CS48L32_LHPF2_COEFF 0xaa3c +#define CS48L32_LHPF3_COEFF 0xaa40 +#define CS48L32_LHPF4_COEFF 0xaa44 +#define CS48L32_DRC1_CONTROL1 0xab00 +#define CS48L32_DRC1_CONTROL4 0xab0c +#define CS48L32_DRC2_CONTROL1 0xab14 +#define CS48L32_DRC2_CONTROL4 0xab20 +#define CS48L32_TONE_GENERATOR1 0xb000 +#define CS48L32_TONE_GENERATOR2 0xb004 +#define CS48L32_COMFORT_NOISE_GENERATOR 0xb400 +#define CS48L32_US_CONTROL 0xb800 +#define CS48L32_US1_CONTROL 0xb804 +#define CS48L32_US1_DET_CONTROL 0xb808 +#define CS48L32_US2_CONTROL 0xb814 +#define CS48L32_US2_DET_CONTROL 0xb818 +#define CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 0x1700c +#define CS48L32_DSP1_XM_SRAM_IBUS_SETUP_1 0x17010 +#define CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24 0x1706c +#define CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 0x17070 +#define CS48L32_DSP1_YM_SRAM_IBUS_SETUP_1 0x17074 +#define CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8 0x17090 +#define CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 0x17094 +#define CS48L32_DSP1_PM_SRAM_IBUS_SETUP_1 0x17098 +#define CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7 0x170b0 +#define CS48L32_IRQ1_STATUS 0x18004 +#define CS48L32_IRQ1_EINT_1 0x18010 +#define CS48L32_IRQ1_EINT_2 0x18014 +#define CS48L32_IRQ1_EINT_5 0x18020 +#define CS48L32_IRQ1_EINT_6 0x18024 +#define CS48L32_IRQ1_EINT_7 0x18028 +#define CS48L32_IRQ1_EINT_9 0x18030 +#define CS48L32_IRQ1_EINT_11 0x18038 +#define CS48L32_IRQ1_STS_1 0x18090 +#define CS48L32_IRQ1_STS_6 0x180a4 +#define CS48L32_IRQ1_STS_11 0x180b8 +#define CS48L32_IRQ1_MASK_1 0x18110 +#define CS48L32_IRQ1_MASK_11 0x18138 +#define CS48L32_DSP1_XMEM_PACKED_0 0x2000000 +#define CS48L32_DSP1_XMEM_PACKED_147455 0x208fffc +#define CS48L32_DSP1_SYS_INFO_ID 0x25e0000 +#define CS48L32_DSP1_AHBM_WINDOW_DEBUG_1 0x25e2044 +#define CS48L32_DSP1_XMEM_UNPACKED24_0 0x2800000 +#define CS48L32_DSP1_XMEM_UNPACKED24_196607 0x28bfffc +#define CS48L32_DSP1_CLOCK_FREQ 0x2b80000 +#define CS48L32_DSP1_SAMPLE_RATE_TX8 0x2b802b8 +#define CS48L32_DSP1_SCRATCH1 0x2b805c0 +#define CS48L32_DSP1_SCRATCH4 0x2b805d8 +#define CS48L32_DSP1_CCM_CORE_CONTROL 0x2bc1000 +#define CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1 0x2bc5a00 +#define CS48L32_DSP1_YMEM_PACKED_0 0x2c00000 +#define CS48L32_DSP1_YMEM_PACKED_49151 0x2c2fffc +#define CS48L32_DSP1_YMEM_UNPACKED24_0 0x3400000 +#define CS48L32_DSP1_YMEM_UNPACKED24_65535 0x343fffc +#define CS48L32_DSP1_PMEM_0 0x3800000 +#define CS48L32_DSP1_PMEM_71679 0x3845ffc + +/* (0x0) DEVID */ +#define CS48L32_DEVID_MASK 0x00ffffff +#define CS48L32_DEVID_SHIFT 0 + +/* (0x4) REVID */ +#define CS48L32_AREVID_MASK 0x000000f0 +#define CS48L32_AREVID_SHIFT 4 +#define CS48L32_MTLREVID_MASK 0x0000000f +#define CS48L32_MTLREVID_SHIFT 0 + +/* (0x10) OTPID */ +#define CS48L32_OTPID_MASK 0x0000000f + +/* (0x0804) MCU_CTRL1 */ +#define CS48L32_MCU_STS_MASK 0x0000ff00 +#define CS48L32_MCU_STS_SHIFT 8 + +/* (0x1020) OUTPUT_SYS_CLK */ +#define CS48L32_OPCLK_EN_SHIFT 15 +#define CS48L32_OPCLK_DIV_MASK 0x000000f8 +#define CS48L32_OPCLK_DIV_SHIFT 3 +#define CS48L32_OPCLK_SEL_MASK 0x00000007 + +/* (0x105c) AUXPDM_CTRL2 */ +#define CS48L32_AUXPDMDAT2_SRC_SHIFT 4 +#define CS48L32_AUXPDMDAT1_SRC_SHIFT 0 + +/* (0x1400) CLOCK32K */ +#define CS48L32_CLK_32K_EN_MASK 0x00000040 +#define CS48L32_CLK_32K_SRC_MASK 0x00000003 + +/* (0x1404) SYSTEM_CLOCK1 */ +#define CS48L32_SYSCLK_FRAC_MASK 0x00008000 +#define CS48L32_SYSCLK_FREQ_MASK 0x00000700 +#define CS48L32_SYSCLK_FREQ_SHIFT 8 +#define CS48L32_SYSCLK_EN_SHIFT 6 +#define CS48L32_SYSCLK_SRC_MASK 0x0000001f +#define CS48L32_SYSCLK_SRC_SHIFT 0 + +/* (0x1408) SYSTEM_CLOCK2 */ +#define CS48L32_SYSCLK_FREQ_STS_MASK 0x00000700 +#define CS48L32_SYSCLK_FREQ_STS_SHIFT 8 + +/* (0x1420) SAMPLE_RATE1 */ +#define CS48L32_SAMPLE_RATE_1_MASK 0x0000001f +#define CS48L32_SAMPLE_RATE_1_SHIFT 0 + +/* (0x1510) DSP_CLOCK1 */ +#define CS48L32_DSP_CLK_FREQ_MASK 0xffff0000 +#define CS48L32_DSP_CLK_FREQ_SHIFT 16 + +/* (0x1c00) FLL_CONTROL1 */ +#define CS48L32_FLL_CTRL_UPD_MASK 0x00000004 +#define CS48L32_FLL_HOLD_MASK 0x00000002 +#define CS48L32_FLL_EN_MASK 0x00000001 + +/* (0x1c04) FLL_CONTROL2 */ +#define CS48L32_FLL_LOCKDET_THR_MASK 0xf0000000 +#define CS48L32_FLL_LOCKDET_THR_SHIFT 28 +#define CS48L32_FLL_LOCKDET_MASK 0x08000000 +#define CS48L32_FLL_PHASEDET_MASK 0x00400000 +#define CS48L32_FLL_PHASEDET_SHIFT 22 +#define CS48L32_FLL_REFCLK_DIV_MASK 0x00030000 +#define CS48L32_FLL_REFCLK_DIV_SHIFT 16 +#define CS48L32_FLL_REFCLK_SRC_MASK 0x0000f000 +#define CS48L32_FLL_REFCLK_SRC_SHIFT 12 +#define CS48L32_FLL_N_MASK 0x000003ff +#define CS48L32_FLL_N_SHIFT 0 + +/* (0x1c08) FLL_CONTROL3 */ +#define CS48L32_FLL_LAMBDA_MASK 0xffff0000 +#define CS48L32_FLL_LAMBDA_SHIFT 16 +#define CS48L32_FLL_THETA_MASK 0x0000ffff +#define CS48L32_FLL_THETA_SHIFT 0 + +/* (0x1c0c) FLL_CONTROL4 */ +#define CS48L32_FLL_FD_GAIN_COARSE_SHIFT 16 +#define CS48L32_FLL_HP_MASK 0x00003000 +#define CS48L32_FLL_HP_SHIFT 12 +#define CS48L32_FLL_FB_DIV_MASK 0x000003ff +#define CS48L32_FLL_FB_DIV_SHIFT 0 + +/* (0x1c10) FLL_CONTROL5 */ +#define CS48L32_FLL_FRC_INTEG_UPD_MASK 0x00008000 + +/* (0x2000) CHARGE_PUMP1 */ +#define CS48L32_CP2_BYPASS_MASK 0x00000002 +#define CS48L32_CP2_EN_MASK 0x00000001 + +/* (0x2408) LDO2_CTRL1 */ +#define CS48L32_LDO2_VSEL_MASK 0x000007e0 + +/* (0x2410) MICBIAS_CTRL1 */ +#define CS48L32_MICB1_EN_SHIFT 0 + +/* (0x2418) MICBIAS_CTRL5 */ +#define CS48L32_MICB1C_EN_SHIFT 8 +#define CS48L32_MICB1B_EN_SHIFT 4 +#define CS48L32_MICB1A_EN_SHIFT 0 + +/* (0x2710) IRQ1_CTRL_AOD */ +#define CS48L32_IRQ_POL_MASK 0x00000400 + +/* (0x4000) INPUT_CONTROL */ +#define CS48L32_IN2L_EN_SHIFT 3 +#define CS48L32_IN2R_EN_SHIFT 2 +#define CS48L32_IN1L_EN_SHIFT 1 +#define CS48L32_IN1R_EN_SHIFT 0 + +/* (0x400c) INPUT_CONTROL2 */ +#define CS48L32_PDM_FLLCLK_SRC_MASK 0x0000000f +#define CS48L32_PDM_FLLCLK_SRC_SHIFT 0 + +/* (0x4014) INPUT_CONTROL3 */ +#define CS48L32_IN_VU 0x20000000 +#define CS48L32_IN_VU_MASK 0x20000000 +#define CS48L32_IN_VU_SHIFT 29 +#define CS48L32_IN_VU_WIDTH 1 + +/* (0x4020) INPUT1_CONTROL1 */ +#define CS48L32_IN1_OSR_SHIFT 16 +#define CS48L32_IN1_PDM_SUP_MASK 0x00000300 +#define CS48L32_IN1_PDM_SUP_SHIFT 8 +#define CS48L32_IN1_MODE_SHIFT 0 + +/* + * (0x4024) IN1L_CONTROL1 + * (0x4044) IN1R_CONTROL1 + */ +#define CS48L32_INx_SRC_MASK 0x30000000 +#define CS48L32_INx_SRC_SHIFT 28 +#define CS48L32_INx_RATE_MASK 0x0000f800 +#define CS48L32_INx_RATE_SHIFT 11 +#define CS48L32_INx_HPF_SHIFT 2 +#define CS48L32_INx_LP_MODE_SHIFT 0 + +/* + * (0x4028) IN1L_CONTROL2 + * (0x4048) IN1R_CONTROL2 + */ +#define CS48L32_INx_MUTE_MASK 0x10000000 +#define CS48L32_INx_VOL_SHIFT 16 +#define CS48L32_INx_PGA_VOL_SHIFT 1 + +/* (0x4244) INPUT_HPF_CONTROL */ +#define CS48L32_IN_HPF_CUT_SHIFT 0 + +/* (0x4248) INPUT_VOL_CONTROL */ +#define CS48L32_IN_VD_RAMP_SHIFT 4 +#define CS48L32_IN_VI_RAMP_SHIFT 0 + +/* (0x4308) AUXPDM1_CONTROL1 */ +#define CS48L32_AUXPDM1_FREQ_SHIFT 16 +#define CS48L32_AUXPDM1_SRC_MASK 0x00000f00 +#define CS48L32_AUXPDM1_SRC_SHIFT 8 + +/* (0x4688) ADC1L_ANA_CONTROL1 */ +/* (0x468c) ADC1R_ANA_CONTROL1 */ +#define CS48L32_ADC1x_INT_ENA_FRC_MASK 0x00000002 + +/* (0x6004) ASPn_CONTROL1 */ +#define CS48L32_ASP_RATE_MASK 0x00001f00 +#define CS48L32_ASP_RATE_SHIFT 8 +#define CS48L32_ASP_BCLK_FREQ_MASK 0x0000003f + +/* (0x6008) ASPn_CONTROL2 */ +#define CS48L32_ASP_RX_WIDTH_MASK 0xff000000 +#define CS48L32_ASP_RX_WIDTH_SHIFT 24 +#define CS48L32_ASP_TX_WIDTH_MASK 0x00ff0000 +#define CS48L32_ASP_TX_WIDTH_SHIFT 16 +#define CS48L32_ASP_FMT_MASK 0x00000700 +#define CS48L32_ASP_FMT_SHIFT 8 +#define CS48L32_ASP_BCLK_INV_MASK 0x00000040 +#define CS48L32_ASP_BCLK_MSTR_MASK 0x00000010 +#define CS48L32_ASP_FSYNC_INV_MASK 0x00000004 +#define CS48L32_ASP_FSYNC_MSTR_MASK 0x00000001 + +/* (0x6030) ASPn_DATA_CONTROL1 */ +#define CS48L32_ASP_TX_WL_MASK 0x0000003f + +/* (0x6040) ASPn_DATA_CONTROL5 */ +#define CS48L32_ASP_RX_WL_MASK 0x0000003f + +/* (0x82xx - 0x90xx) *_INPUT[1-4] */ +#define CS48L32_MIXER_VOL_MASK 0x00FE0000 +#define CS48L32_MIXER_VOL_SHIFT 17 +#define CS48L32_MIXER_VOL_WIDTH 7 +#define CS48L32_MIXER_SRC_MASK 0x000001ff +#define CS48L32_MIXER_SRC_SHIFT 0 +#define CS48L32_MIXER_SRC_WIDTH 9 + +/* (0xa400) ISRC1_CONTROL1 */ +#define CS48L32_ISRC1_FSL_MASK 0xf8000000 +#define CS48L32_ISRC1_FSL_SHIFT 27 +#define CS48L32_ISRC1_FSH_MASK 0x0000f800 +#define CS48L32_ISRC1_FSH_SHIFT 11 + +/* (0xa404) ISRC1_CONTROL2 */ +#define CS48L32_ISRC1_INT4_EN_SHIFT 11 +#define CS48L32_ISRC1_INT3_EN_SHIFT 10 +#define CS48L32_ISRC1_INT2_EN_SHIFT 9 +#define CS48L32_ISRC1_INT1_EN_SHIFT 8 +#define CS48L32_ISRC1_DEC4_EN_SHIFT 3 +#define CS48L32_ISRC1_DEC3_EN_SHIFT 2 +#define CS48L32_ISRC1_DEC2_EN_SHIFT 1 +#define CS48L32_ISRC1_DEC1_EN_SHIFT 0 + +/* (0xa800) FX_SAMPLE_RATE */ +#define CS48L32_FX_RATE_MASK 0x0000f800 +#define CS48L32_FX_RATE_SHIFT 11 + +/* (0xab00) DRC1_CONTROL1 */ +#define CS48L32_DRC1L_EN_SHIFT 1 +#define CS48L32_DRC1R_EN_SHIFT 0 + +/* (0xb400) Comfort_Noise_Generator */ +#define CS48L32_NOISE_GEN_RATE_MASK 0x0000f800 +#define CS48L32_NOISE_GEN_RATE_SHIFT 11 +#define CS48L32_NOISE_GEN_EN_SHIFT 5 +#define CS48L32_NOISE_GEN_GAIN_SHIFT 0 + +/* (0xb800) US_CONTROL */ +#define CS48L32_US1_DET_EN_SHIFT 8 + +/* (0xb804) US1_CONTROL */ +#define CS48L32_US1_RATE_MASK 0xf8000000 +#define CS48L32_US1_RATE_SHIFT 27 +#define CS48L32_US1_GAIN_SHIFT 12 +#define CS48L32_US1_SRC_MASK 0x00000f00 +#define CS48L32_US1_SRC_SHIFT 8 +#define CS48L32_US1_FREQ_MASK 0x00000070 +#define CS48L32_US1_FREQ_SHIFT 4 + +/* (0xb808) US1_DET_CONTROL */ +#define CS48L32_US1_DET_DCY_SHIFT 28 +#define CS48L32_US1_DET_HOLD_SHIFT 24 +#define CS48L32_US1_DET_NUM_SHIFT 20 +#define CS48L32_US1_DET_THR_SHIFT 16 +#define CS48L32_US1_DET_LPF_CUT_SHIFT 5 +#define CS48L32_US1_DET_LPF_SHIFT 4 + +/* (0x18004) IRQ1_STATUS */ +#define CS48L32_IRQ1_STS_MASK 0x00000001 + +/* (0x18014) IRQ1_EINT_2 */ +#define CS48L32_BOOT_DONE_EINT1_MASK 0x00000008 + +/* (0x180a4) IRQ1_STS_6 */ +#define CS48L32_FLL1_LOCK_STS1_MASK 0x00000001 + +#endif -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 02/12] mfd: cs48l32: Add register definitions for Cirrus Logic CS48L31/32/33 @ 2022-11-09 16:53 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio, Richard Fitzgerald This adds the register definitions for the CS48L31/32/33. The CS48L31/32/33 audio codecs are multi-function devices containing gpios, irq controller and regulators in addition to the core audio functionality. Signed-off-by: Piotr Stankiewicz <piotrs@opensource.cirrus.com> Signed-off-by: Stuart Henderson <stuarth@opensource.cirrus.com> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- include/linux/mfd/cs48l32/registers.h | 509 ++++++++++++++++++++++++++ 1 file changed, 509 insertions(+) create mode 100644 include/linux/mfd/cs48l32/registers.h diff --git a/include/linux/mfd/cs48l32/registers.h b/include/linux/mfd/cs48l32/registers.h new file mode 100644 index 000000000000..b8125950d74c --- /dev/null +++ b/include/linux/mfd/cs48l32/registers.h @@ -0,0 +1,509 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Register definitions for Cirrus Logic CS48L32 + * + * Copyright (C) 2017-2018, 2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef CS48L32_REGISTERS_H +#define CS48L32_REGISTERS_H + +/* Register Addresses. */ +#define CS48L32_DEVID 0x0 +#define CS48L32_REVID 0x4 +#define CS48L32_OTPID 0x10 +#define CS48L32_SFT_RESET 0x20 +#define CS48L32_CTRL_IF_DEBUG3 0xA8 +#define CS48L32_MCU_CTRL1 0x804 +#define CS48L32_GPIO1_CTRL1 0xc08 +#define CS48L32_GPIO16_CTRL1 0xc44 +#define CS48L32_OUTPUT_SYS_CLK 0x1020 +#define CS48L32_AUXPDM_CTRL 0x1044 +#define CS48L32_AUXPDM_CTRL2 0x105c +#define CS48L32_CLOCK32K 0x1400 +#define CS48L32_SYSTEM_CLOCK1 0x1404 +#define CS48L32_SYSTEM_CLOCK2 0x1408 +#define CS48L32_SAMPLE_RATE1 0x1420 +#define CS48L32_SAMPLE_RATE2 0x1424 +#define CS48L32_SAMPLE_RATE3 0x1428 +#define CS48L32_SAMPLE_RATE4 0x142c +#define CS48L32_DSP_CLOCK1 0x1510 +#define CS48L32_FLL1_CONTROL1 0x1c00 +#define CS48L32_FLL1_CONTROL5 0x1c10 +#define CS48L32_FLL1_CONTROL6 0x1c14 +#define CS48L32_FLL1_GPIO_CLOCK 0x1ca0 +#define CS48L32_CHARGE_PUMP1 0x2000 +#define CS48L32_LDO2_CTRL1 0x2408 +#define CS48L32_MICBIAS_CTRL1 0x2410 +#define CS48L32_MICBIAS_CTRL5 0x2418 +#define CS48L32_IRQ1_CTRL_AOD 0x2710 +#define CS48L32_AOD_PAD_CTRL 0x2718 +#define CS48L32_INPUT_CONTROL 0x4000 +#define CS48L32_INPUT_STATUS 0x4004 +#define CS48L32_INPUT_RATE_CONTROL 0x4008 +#define CS48L32_INPUT_CONTROL2 0x400c +#define CS48L32_INPUT_CONTROL3 0x4014 +#define CS48L32_INPUT1_CONTROL1 0x4020 +#define CS48L32_IN1L_CONTROL1 0x4024 +#define CS48L32_IN1L_CONTROL2 0x4028 +#define CS48L32_IN1R_CONTROL1 0x4044 +#define CS48L32_IN1R_CONTROL2 0x4048 +#define CS48L32_INPUT2_CONTROL1 0x4060 +#define CS48L32_IN2L_CONTROL1 0x4064 +#define CS48L32_IN2L_CONTROL2 0x4068 +#define CS48L32_IN2R_CONTROL1 0x4084 +#define CS48L32_IN2R_CONTROL2 0x4088 +#define CS48L32_INPUT_HPF_CONTROL 0x4244 +#define CS48L32_INPUT_VOL_CONTROL 0x4248 +#define CS48L32_AUXPDM_CONTROL1 0x4300 +#define CS48L32_AUXPDM_CONTROL2 0x4304 +#define CS48L32_AUXPDM1_CONTROL1 0x4308 +#define CS48L32_AUXPDM2_CONTROL1 0x4310 +#define CS48L32_ADC1L_ANA_CONTROL1 0x4688 +#define CS48L32_ADC1R_ANA_CONTROL1 0x468c +#define CS48L32_ASP1_ENABLES1 0x6000 +#define CS48L32_ASP1_DATA_CONTROL5 0x6040 +#define CS48L32_ASP2_ENABLES1 0x6080 +#define CS48L32_ASP2_DATA_CONTROL5 0x60c0 +#define CS48L32_ASP1TX1_INPUT1 0x8200 +#define CS48L32_ASP1TX2_INPUT1 0x8210 +#define CS48L32_ASP1TX3_INPUT1 0x8220 +#define CS48L32_ASP1TX4_INPUT1 0x8230 +#define CS48L32_ASP1TX5_INPUT1 0x8240 +#define CS48L32_ASP1TX6_INPUT1 0x8250 +#define CS48L32_ASP1TX7_INPUT1 0x8260 +#define CS48L32_ASP1TX8_INPUT1 0x8270 +#define CS48L32_ASP1TX8_INPUT4 0x827c +#define CS48L32_ASP2TX1_INPUT1 0x8300 +#define CS48L32_ASP2TX2_INPUT1 0x8310 +#define CS48L32_ASP2TX3_INPUT1 0x8320 +#define CS48L32_ASP2TX4_INPUT1 0x8330 +#define CS48L32_ASP2TX4_INPUT4 0x833c +#define CS48L32_ISRC1INT1_INPUT1 0x8980 +#define CS48L32_ISRC1INT2_INPUT1 0x8990 +#define CS48L32_ISRC1INT3_INPUT1 0x89a0 +#define CS48L32_ISRC1INT4_INPUT1 0x89b0 +#define CS48L32_ISRC1DEC1_INPUT1 0x89c0 +#define CS48L32_ISRC1DEC2_INPUT1 0x89d0 +#define CS48L32_ISRC1DEC3_INPUT1 0x89e0 +#define CS48L32_ISRC1DEC4_INPUT1 0x89f0 +#define CS48L32_ISRC2INT1_INPUT1 0x8a00 +#define CS48L32_ISRC2INT2_INPUT1 0x8a10 +#define CS48L32_ISRC2DEC1_INPUT1 0x8a40 +#define CS48L32_ISRC2DEC2_INPUT1 0x8a50 +#define CS48L32_ISRC3INT1_INPUT1 0x8a80 +#define CS48L32_ISRC3INT2_INPUT1 0x8a90 +#define CS48L32_ISRC3DEC1_INPUT1 0x8ac0 +#define CS48L32_ISRC3DEC2_INPUT1 0x8ad0 +#define CS48L32_EQ1_INPUT1 0x8b80 +#define CS48L32_EQ2_INPUT1 0x8b90 +#define CS48L32_EQ3_INPUT1 0x8ba0 +#define CS48L32_EQ4_INPUT1 0x8bb0 +#define CS48L32_EQ4_INPUT4 0x8bbc +#define CS48L32_DRC1L_INPUT1 0x8c00 +#define CS48L32_DRC1R_INPUT1 0x8c10 +#define CS48L32_DRC1R_INPUT4 0x8c1c +#define CS48L32_DRC2L_INPUT1 0x8c20 +#define CS48L32_DRC2R_INPUT1 0x8c30 +#define CS48L32_DRC2R_INPUT4 0x8c3c +#define CS48L32_LHPF1_INPUT1 0x8c80 +#define CS48L32_LHPF1_INPUT4 0x8c8c +#define CS48L32_LHPF2_INPUT1 0x8c90 +#define CS48L32_LHPF2_INPUT4 0x8c9c +#define CS48L32_LHPF3_INPUT1 0x8ca0 +#define CS48L32_LHPF3_INPUT4 0x8cac +#define CS48L32_LHPF4_INPUT1 0x8cb0 +#define CS48L32_LHPF4_INPUT4 0x8cbc +#define CS48L32_DSP1RX1_INPUT1 0x9000 +#define CS48L32_DSP1RX2_INPUT1 0x9010 +#define CS48L32_DSP1RX3_INPUT1 0x9020 +#define CS48L32_DSP1RX4_INPUT1 0x9030 +#define CS48L32_DSP1RX5_INPUT1 0x9040 +#define CS48L32_DSP1RX6_INPUT1 0x9050 +#define CS48L32_DSP1RX7_INPUT1 0x9060 +#define CS48L32_DSP1RX8_INPUT1 0x9070 +#define CS48L32_DSP1RX8_INPUT4 0x907c +#define CS48L32_ISRC1_CONTROL1 0xa400 +#define CS48L32_ISRC1_CONTROL2 0xa404 +#define CS48L32_ISRC2_CONTROL1 0xa510 +#define CS48L32_ISRC2_CONTROL2 0xa514 +#define CS48L32_ISRC3_CONTROL1 0xa620 +#define CS48L32_ISRC3_CONTROL2 0xa624 +#define CS48L32_FX_SAMPLE_RATE 0xa800 +#define CS48L32_EQ_CONTROL1 0xa808 +#define CS48L32_EQ_CONTROL2 0xa80c +#define CS48L32_EQ1_GAIN1 0xa810 +#define CS48L32_EQ1_GAIN2 0xa814 +#define CS48L32_EQ1_BAND1_COEFF1 0xa818 +#define CS48L32_EQ1_BAND1_COEFF2 0xa81c +#define CS48L32_EQ1_BAND1_PG 0xa820 +#define CS48L32_EQ1_BAND2_COEFF1 0xa824 +#define CS48L32_EQ1_BAND2_COEFF2 0xa828 +#define CS48L32_EQ1_BAND2_PG 0xa82c +#define CS48L32_EQ1_BAND3_COEFF1 0xa830 +#define CS48L32_EQ1_BAND3_COEFF2 0xa834 +#define CS48L32_EQ1_BAND3_PG 0xa838 +#define CS48L32_EQ1_BAND4_COEFF1 0xa83c +#define CS48L32_EQ1_BAND4_COEFF2 0xa840 +#define CS48L32_EQ1_BAND4_PG 0xa844 +#define CS48L32_EQ1_BAND5_COEFF1 0xa848 +#define CS48L32_EQ1_BAND5_PG 0xa850 +#define CS48L32_EQ2_GAIN1 0xa854 +#define CS48L32_EQ2_GAIN2 0xa858 +#define CS48L32_EQ2_BAND1_COEFF1 0xa85c +#define CS48L32_EQ2_BAND1_COEFF2 0xa860 +#define CS48L32_EQ2_BAND1_PG 0xa864 +#define CS48L32_EQ2_BAND2_COEFF1 0xa868 +#define CS48L32_EQ2_BAND2_COEFF2 0xa86c +#define CS48L32_EQ2_BAND2_PG 0xa870 +#define CS48L32_EQ2_BAND3_COEFF1 0xa874 +#define CS48L32_EQ2_BAND3_COEFF2 0xa878 +#define CS48L32_EQ2_BAND3_PG 0xa87c +#define CS48L32_EQ2_BAND4_COEFF1 0xa880 +#define CS48L32_EQ2_BAND4_COEFF2 0xa884 +#define CS48L32_EQ2_BAND4_PG 0xa888 +#define CS48L32_EQ2_BAND5_COEFF1 0xa88c +#define CS48L32_EQ2_BAND5_PG 0xa894 +#define CS48L32_EQ3_GAIN1 0xa898 +#define CS48L32_EQ3_GAIN2 0xa89c +#define CS48L32_EQ3_BAND1_COEFF1 0xa8a0 +#define CS48L32_EQ3_BAND1_COEFF2 0xa8a4 +#define CS48L32_EQ3_BAND1_PG 0xa8a8 +#define CS48L32_EQ3_BAND2_COEFF1 0xa8ac +#define CS48L32_EQ3_BAND2_COEFF2 0xa8b0 +#define CS48L32_EQ3_BAND2_PG 0xa8b4 +#define CS48L32_EQ3_BAND3_COEFF1 0xa8b8 +#define CS48L32_EQ3_BAND3_COEFF2 0xa8bc +#define CS48L32_EQ3_BAND3_PG 0xa8c0 +#define CS48L32_EQ3_BAND4_COEFF1 0xa8c4 +#define CS48L32_EQ3_BAND4_COEFF2 0xa8c8 +#define CS48L32_EQ3_BAND4_PG 0xa8cc +#define CS48L32_EQ3_BAND5_COEFF1 0xa8d0 +#define CS48L32_EQ3_BAND5_PG 0xa8d8 +#define CS48L32_EQ4_GAIN1 0xa8dc +#define CS48L32_EQ4_GAIN2 0xa8e0 +#define CS48L32_EQ4_BAND1_COEFF1 0xa8e4 +#define CS48L32_EQ4_BAND1_COEFF2 0xa8e8 +#define CS48L32_EQ4_BAND1_PG 0xa8ec +#define CS48L32_EQ4_BAND2_COEFF1 0xa8f0 +#define CS48L32_EQ4_BAND2_COEFF2 0xa8f4 +#define CS48L32_EQ4_BAND2_PG 0xa8f8 +#define CS48L32_EQ4_BAND3_COEFF1 0xa8fc +#define CS48L32_EQ4_BAND3_COEFF2 0xa900 +#define CS48L32_EQ4_BAND3_PG 0xa904 +#define CS48L32_EQ4_BAND4_COEFF1 0xa908 +#define CS48L32_EQ4_BAND4_COEFF2 0xa90c +#define CS48L32_EQ4_BAND4_PG 0xa910 +#define CS48L32_EQ4_BAND5_COEFF1 0xa914 +#define CS48L32_EQ4_BAND5_PG 0xa91c +#define CS48L32_LHPF_CONTROL1 0xaa30 +#define CS48L32_LHPF_CONTROL2 0xaa34 +#define CS48L32_LHPF1_COEFF 0xaa38 +#define CS48L32_LHPF2_COEFF 0xaa3c +#define CS48L32_LHPF3_COEFF 0xaa40 +#define CS48L32_LHPF4_COEFF 0xaa44 +#define CS48L32_DRC1_CONTROL1 0xab00 +#define CS48L32_DRC1_CONTROL4 0xab0c +#define CS48L32_DRC2_CONTROL1 0xab14 +#define CS48L32_DRC2_CONTROL4 0xab20 +#define CS48L32_TONE_GENERATOR1 0xb000 +#define CS48L32_TONE_GENERATOR2 0xb004 +#define CS48L32_COMFORT_NOISE_GENERATOR 0xb400 +#define CS48L32_US_CONTROL 0xb800 +#define CS48L32_US1_CONTROL 0xb804 +#define CS48L32_US1_DET_CONTROL 0xb808 +#define CS48L32_US2_CONTROL 0xb814 +#define CS48L32_US2_DET_CONTROL 0xb818 +#define CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 0x1700c +#define CS48L32_DSP1_XM_SRAM_IBUS_SETUP_1 0x17010 +#define CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24 0x1706c +#define CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 0x17070 +#define CS48L32_DSP1_YM_SRAM_IBUS_SETUP_1 0x17074 +#define CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8 0x17090 +#define CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 0x17094 +#define CS48L32_DSP1_PM_SRAM_IBUS_SETUP_1 0x17098 +#define CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7 0x170b0 +#define CS48L32_IRQ1_STATUS 0x18004 +#define CS48L32_IRQ1_EINT_1 0x18010 +#define CS48L32_IRQ1_EINT_2 0x18014 +#define CS48L32_IRQ1_EINT_5 0x18020 +#define CS48L32_IRQ1_EINT_6 0x18024 +#define CS48L32_IRQ1_EINT_7 0x18028 +#define CS48L32_IRQ1_EINT_9 0x18030 +#define CS48L32_IRQ1_EINT_11 0x18038 +#define CS48L32_IRQ1_STS_1 0x18090 +#define CS48L32_IRQ1_STS_6 0x180a4 +#define CS48L32_IRQ1_STS_11 0x180b8 +#define CS48L32_IRQ1_MASK_1 0x18110 +#define CS48L32_IRQ1_MASK_11 0x18138 +#define CS48L32_DSP1_XMEM_PACKED_0 0x2000000 +#define CS48L32_DSP1_XMEM_PACKED_147455 0x208fffc +#define CS48L32_DSP1_SYS_INFO_ID 0x25e0000 +#define CS48L32_DSP1_AHBM_WINDOW_DEBUG_1 0x25e2044 +#define CS48L32_DSP1_XMEM_UNPACKED24_0 0x2800000 +#define CS48L32_DSP1_XMEM_UNPACKED24_196607 0x28bfffc +#define CS48L32_DSP1_CLOCK_FREQ 0x2b80000 +#define CS48L32_DSP1_SAMPLE_RATE_TX8 0x2b802b8 +#define CS48L32_DSP1_SCRATCH1 0x2b805c0 +#define CS48L32_DSP1_SCRATCH4 0x2b805d8 +#define CS48L32_DSP1_CCM_CORE_CONTROL 0x2bc1000 +#define CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1 0x2bc5a00 +#define CS48L32_DSP1_YMEM_PACKED_0 0x2c00000 +#define CS48L32_DSP1_YMEM_PACKED_49151 0x2c2fffc +#define CS48L32_DSP1_YMEM_UNPACKED24_0 0x3400000 +#define CS48L32_DSP1_YMEM_UNPACKED24_65535 0x343fffc +#define CS48L32_DSP1_PMEM_0 0x3800000 +#define CS48L32_DSP1_PMEM_71679 0x3845ffc + +/* (0x0) DEVID */ +#define CS48L32_DEVID_MASK 0x00ffffff +#define CS48L32_DEVID_SHIFT 0 + +/* (0x4) REVID */ +#define CS48L32_AREVID_MASK 0x000000f0 +#define CS48L32_AREVID_SHIFT 4 +#define CS48L32_MTLREVID_MASK 0x0000000f +#define CS48L32_MTLREVID_SHIFT 0 + +/* (0x10) OTPID */ +#define CS48L32_OTPID_MASK 0x0000000f + +/* (0x0804) MCU_CTRL1 */ +#define CS48L32_MCU_STS_MASK 0x0000ff00 +#define CS48L32_MCU_STS_SHIFT 8 + +/* (0x1020) OUTPUT_SYS_CLK */ +#define CS48L32_OPCLK_EN_SHIFT 15 +#define CS48L32_OPCLK_DIV_MASK 0x000000f8 +#define CS48L32_OPCLK_DIV_SHIFT 3 +#define CS48L32_OPCLK_SEL_MASK 0x00000007 + +/* (0x105c) AUXPDM_CTRL2 */ +#define CS48L32_AUXPDMDAT2_SRC_SHIFT 4 +#define CS48L32_AUXPDMDAT1_SRC_SHIFT 0 + +/* (0x1400) CLOCK32K */ +#define CS48L32_CLK_32K_EN_MASK 0x00000040 +#define CS48L32_CLK_32K_SRC_MASK 0x00000003 + +/* (0x1404) SYSTEM_CLOCK1 */ +#define CS48L32_SYSCLK_FRAC_MASK 0x00008000 +#define CS48L32_SYSCLK_FREQ_MASK 0x00000700 +#define CS48L32_SYSCLK_FREQ_SHIFT 8 +#define CS48L32_SYSCLK_EN_SHIFT 6 +#define CS48L32_SYSCLK_SRC_MASK 0x0000001f +#define CS48L32_SYSCLK_SRC_SHIFT 0 + +/* (0x1408) SYSTEM_CLOCK2 */ +#define CS48L32_SYSCLK_FREQ_STS_MASK 0x00000700 +#define CS48L32_SYSCLK_FREQ_STS_SHIFT 8 + +/* (0x1420) SAMPLE_RATE1 */ +#define CS48L32_SAMPLE_RATE_1_MASK 0x0000001f +#define CS48L32_SAMPLE_RATE_1_SHIFT 0 + +/* (0x1510) DSP_CLOCK1 */ +#define CS48L32_DSP_CLK_FREQ_MASK 0xffff0000 +#define CS48L32_DSP_CLK_FREQ_SHIFT 16 + +/* (0x1c00) FLL_CONTROL1 */ +#define CS48L32_FLL_CTRL_UPD_MASK 0x00000004 +#define CS48L32_FLL_HOLD_MASK 0x00000002 +#define CS48L32_FLL_EN_MASK 0x00000001 + +/* (0x1c04) FLL_CONTROL2 */ +#define CS48L32_FLL_LOCKDET_THR_MASK 0xf0000000 +#define CS48L32_FLL_LOCKDET_THR_SHIFT 28 +#define CS48L32_FLL_LOCKDET_MASK 0x08000000 +#define CS48L32_FLL_PHASEDET_MASK 0x00400000 +#define CS48L32_FLL_PHASEDET_SHIFT 22 +#define CS48L32_FLL_REFCLK_DIV_MASK 0x00030000 +#define CS48L32_FLL_REFCLK_DIV_SHIFT 16 +#define CS48L32_FLL_REFCLK_SRC_MASK 0x0000f000 +#define CS48L32_FLL_REFCLK_SRC_SHIFT 12 +#define CS48L32_FLL_N_MASK 0x000003ff +#define CS48L32_FLL_N_SHIFT 0 + +/* (0x1c08) FLL_CONTROL3 */ +#define CS48L32_FLL_LAMBDA_MASK 0xffff0000 +#define CS48L32_FLL_LAMBDA_SHIFT 16 +#define CS48L32_FLL_THETA_MASK 0x0000ffff +#define CS48L32_FLL_THETA_SHIFT 0 + +/* (0x1c0c) FLL_CONTROL4 */ +#define CS48L32_FLL_FD_GAIN_COARSE_SHIFT 16 +#define CS48L32_FLL_HP_MASK 0x00003000 +#define CS48L32_FLL_HP_SHIFT 12 +#define CS48L32_FLL_FB_DIV_MASK 0x000003ff +#define CS48L32_FLL_FB_DIV_SHIFT 0 + +/* (0x1c10) FLL_CONTROL5 */ +#define CS48L32_FLL_FRC_INTEG_UPD_MASK 0x00008000 + +/* (0x2000) CHARGE_PUMP1 */ +#define CS48L32_CP2_BYPASS_MASK 0x00000002 +#define CS48L32_CP2_EN_MASK 0x00000001 + +/* (0x2408) LDO2_CTRL1 */ +#define CS48L32_LDO2_VSEL_MASK 0x000007e0 + +/* (0x2410) MICBIAS_CTRL1 */ +#define CS48L32_MICB1_EN_SHIFT 0 + +/* (0x2418) MICBIAS_CTRL5 */ +#define CS48L32_MICB1C_EN_SHIFT 8 +#define CS48L32_MICB1B_EN_SHIFT 4 +#define CS48L32_MICB1A_EN_SHIFT 0 + +/* (0x2710) IRQ1_CTRL_AOD */ +#define CS48L32_IRQ_POL_MASK 0x00000400 + +/* (0x4000) INPUT_CONTROL */ +#define CS48L32_IN2L_EN_SHIFT 3 +#define CS48L32_IN2R_EN_SHIFT 2 +#define CS48L32_IN1L_EN_SHIFT 1 +#define CS48L32_IN1R_EN_SHIFT 0 + +/* (0x400c) INPUT_CONTROL2 */ +#define CS48L32_PDM_FLLCLK_SRC_MASK 0x0000000f +#define CS48L32_PDM_FLLCLK_SRC_SHIFT 0 + +/* (0x4014) INPUT_CONTROL3 */ +#define CS48L32_IN_VU 0x20000000 +#define CS48L32_IN_VU_MASK 0x20000000 +#define CS48L32_IN_VU_SHIFT 29 +#define CS48L32_IN_VU_WIDTH 1 + +/* (0x4020) INPUT1_CONTROL1 */ +#define CS48L32_IN1_OSR_SHIFT 16 +#define CS48L32_IN1_PDM_SUP_MASK 0x00000300 +#define CS48L32_IN1_PDM_SUP_SHIFT 8 +#define CS48L32_IN1_MODE_SHIFT 0 + +/* + * (0x4024) IN1L_CONTROL1 + * (0x4044) IN1R_CONTROL1 + */ +#define CS48L32_INx_SRC_MASK 0x30000000 +#define CS48L32_INx_SRC_SHIFT 28 +#define CS48L32_INx_RATE_MASK 0x0000f800 +#define CS48L32_INx_RATE_SHIFT 11 +#define CS48L32_INx_HPF_SHIFT 2 +#define CS48L32_INx_LP_MODE_SHIFT 0 + +/* + * (0x4028) IN1L_CONTROL2 + * (0x4048) IN1R_CONTROL2 + */ +#define CS48L32_INx_MUTE_MASK 0x10000000 +#define CS48L32_INx_VOL_SHIFT 16 +#define CS48L32_INx_PGA_VOL_SHIFT 1 + +/* (0x4244) INPUT_HPF_CONTROL */ +#define CS48L32_IN_HPF_CUT_SHIFT 0 + +/* (0x4248) INPUT_VOL_CONTROL */ +#define CS48L32_IN_VD_RAMP_SHIFT 4 +#define CS48L32_IN_VI_RAMP_SHIFT 0 + +/* (0x4308) AUXPDM1_CONTROL1 */ +#define CS48L32_AUXPDM1_FREQ_SHIFT 16 +#define CS48L32_AUXPDM1_SRC_MASK 0x00000f00 +#define CS48L32_AUXPDM1_SRC_SHIFT 8 + +/* (0x4688) ADC1L_ANA_CONTROL1 */ +/* (0x468c) ADC1R_ANA_CONTROL1 */ +#define CS48L32_ADC1x_INT_ENA_FRC_MASK 0x00000002 + +/* (0x6004) ASPn_CONTROL1 */ +#define CS48L32_ASP_RATE_MASK 0x00001f00 +#define CS48L32_ASP_RATE_SHIFT 8 +#define CS48L32_ASP_BCLK_FREQ_MASK 0x0000003f + +/* (0x6008) ASPn_CONTROL2 */ +#define CS48L32_ASP_RX_WIDTH_MASK 0xff000000 +#define CS48L32_ASP_RX_WIDTH_SHIFT 24 +#define CS48L32_ASP_TX_WIDTH_MASK 0x00ff0000 +#define CS48L32_ASP_TX_WIDTH_SHIFT 16 +#define CS48L32_ASP_FMT_MASK 0x00000700 +#define CS48L32_ASP_FMT_SHIFT 8 +#define CS48L32_ASP_BCLK_INV_MASK 0x00000040 +#define CS48L32_ASP_BCLK_MSTR_MASK 0x00000010 +#define CS48L32_ASP_FSYNC_INV_MASK 0x00000004 +#define CS48L32_ASP_FSYNC_MSTR_MASK 0x00000001 + +/* (0x6030) ASPn_DATA_CONTROL1 */ +#define CS48L32_ASP_TX_WL_MASK 0x0000003f + +/* (0x6040) ASPn_DATA_CONTROL5 */ +#define CS48L32_ASP_RX_WL_MASK 0x0000003f + +/* (0x82xx - 0x90xx) *_INPUT[1-4] */ +#define CS48L32_MIXER_VOL_MASK 0x00FE0000 +#define CS48L32_MIXER_VOL_SHIFT 17 +#define CS48L32_MIXER_VOL_WIDTH 7 +#define CS48L32_MIXER_SRC_MASK 0x000001ff +#define CS48L32_MIXER_SRC_SHIFT 0 +#define CS48L32_MIXER_SRC_WIDTH 9 + +/* (0xa400) ISRC1_CONTROL1 */ +#define CS48L32_ISRC1_FSL_MASK 0xf8000000 +#define CS48L32_ISRC1_FSL_SHIFT 27 +#define CS48L32_ISRC1_FSH_MASK 0x0000f800 +#define CS48L32_ISRC1_FSH_SHIFT 11 + +/* (0xa404) ISRC1_CONTROL2 */ +#define CS48L32_ISRC1_INT4_EN_SHIFT 11 +#define CS48L32_ISRC1_INT3_EN_SHIFT 10 +#define CS48L32_ISRC1_INT2_EN_SHIFT 9 +#define CS48L32_ISRC1_INT1_EN_SHIFT 8 +#define CS48L32_ISRC1_DEC4_EN_SHIFT 3 +#define CS48L32_ISRC1_DEC3_EN_SHIFT 2 +#define CS48L32_ISRC1_DEC2_EN_SHIFT 1 +#define CS48L32_ISRC1_DEC1_EN_SHIFT 0 + +/* (0xa800) FX_SAMPLE_RATE */ +#define CS48L32_FX_RATE_MASK 0x0000f800 +#define CS48L32_FX_RATE_SHIFT 11 + +/* (0xab00) DRC1_CONTROL1 */ +#define CS48L32_DRC1L_EN_SHIFT 1 +#define CS48L32_DRC1R_EN_SHIFT 0 + +/* (0xb400) Comfort_Noise_Generator */ +#define CS48L32_NOISE_GEN_RATE_MASK 0x0000f800 +#define CS48L32_NOISE_GEN_RATE_SHIFT 11 +#define CS48L32_NOISE_GEN_EN_SHIFT 5 +#define CS48L32_NOISE_GEN_GAIN_SHIFT 0 + +/* (0xb800) US_CONTROL */ +#define CS48L32_US1_DET_EN_SHIFT 8 + +/* (0xb804) US1_CONTROL */ +#define CS48L32_US1_RATE_MASK 0xf8000000 +#define CS48L32_US1_RATE_SHIFT 27 +#define CS48L32_US1_GAIN_SHIFT 12 +#define CS48L32_US1_SRC_MASK 0x00000f00 +#define CS48L32_US1_SRC_SHIFT 8 +#define CS48L32_US1_FREQ_MASK 0x00000070 +#define CS48L32_US1_FREQ_SHIFT 4 + +/* (0xb808) US1_DET_CONTROL */ +#define CS48L32_US1_DET_DCY_SHIFT 28 +#define CS48L32_US1_DET_HOLD_SHIFT 24 +#define CS48L32_US1_DET_NUM_SHIFT 20 +#define CS48L32_US1_DET_THR_SHIFT 16 +#define CS48L32_US1_DET_LPF_CUT_SHIFT 5 +#define CS48L32_US1_DET_LPF_SHIFT 4 + +/* (0x18004) IRQ1_STATUS */ +#define CS48L32_IRQ1_STS_MASK 0x00000001 + +/* (0x18014) IRQ1_EINT_2 */ +#define CS48L32_BOOT_DONE_EINT1_MASK 0x00000008 + +/* (0x180a4) IRQ1_STS_6 */ +#define CS48L32_FLL1_LOCK_STS1_MASK 0x00000001 + +#endif -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 03/12] mfd: cs48l32: Add support for CS48L31/32/33 codecs 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-09 16:53 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio, Richard Fitzgerald From: Piotr Stankiewicz <piotrs@opensource.cirrus.com> The CS48L31/32/33 audio codecs are multi-function devices containing gpios, irq controller and regulators in addition to the core audio functionality. Signed-off-by: Piotr Stankiewicz <piotrs@opensource.cirrus.com> Signed-off-by: Qi Zhou <qi.zhou@cirrus.com> Signed-off-by: Stuart Henderson <stuarth@opensource.cirrus.com> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- MAINTAINERS | 5 +- drivers/mfd/Kconfig | 13 + drivers/mfd/Makefile | 2 + drivers/mfd/cs48l32-tables.c | 541 +++++++++++++++++++++++++++++++ drivers/mfd/cs48l32.c | 434 +++++++++++++++++++++++++ drivers/mfd/cs48l32.h | 28 ++ include/linux/mfd/cs48l32/core.h | 49 +++ 7 files changed, 1071 insertions(+), 1 deletion(-) create mode 100644 drivers/mfd/cs48l32-tables.c create mode 100644 drivers/mfd/cs48l32.c create mode 100644 drivers/mfd/cs48l32.h create mode 100644 include/linux/mfd/cs48l32/core.h diff --git a/MAINTAINERS b/MAINTAINERS index 3f94ed38089b..f1d696f29f11 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5001,7 +5001,7 @@ F: include/dt-bindings/pinctrl/lochnagar.h F: include/linux/mfd/lochnagar* F: sound/soc/codecs/lochnagar-sc.c -CIRRUS LOGIC MADERA CODEC DRIVERS +CIRRUS LOGIC MADERA/CS48L32 CODEC DRIVERS M: Charles Keepax <ckeepax@opensource.cirrus.com> M: Richard Fitzgerald <rf@opensource.cirrus.com> L: alsa-devel@alsa-project.org (moderated for non-subscribers) @@ -5009,16 +5009,19 @@ L: patches@opensource.cirrus.com S: Supported W: https://github.com/CirrusLogic/linux-drivers/wiki T: git https://github.com/CirrusLogic/linux-drivers.git +F: Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml F: Documentation/devicetree/bindings/mfd/cirrus,madera.yaml F: Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml F: Documentation/devicetree/bindings/sound/cirrus,madera.yaml F: drivers/gpio/gpio-madera* F: drivers/irqchip/irq-madera* F: drivers/mfd/cs47l* +F: drivers/mfd/cs48l* F: drivers/mfd/madera* F: drivers/pinctrl/cirrus/* F: include/dt-bindings/sound/madera* F: include/linux/irqchip/irq-madera* +F: include/linux/mfd/cs48l32/* F: include/linux/mfd/madera/* F: include/sound/madera* F: sound/soc/codecs/cs47l* diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 6653d03e0fe3..2be52ba23c7a 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -300,6 +300,19 @@ config MFD_CS47L92 help Support for Cirrus Logic CS42L92, CS47L92 and CS47L93 Smart Codecs +config MFD_CS48L32 + bool "Cirrus Logic CS48L31/32/33" + depends on SPI_MASTER + select MFD_CORE + select REGMAP + select REGMAP_SPI + select REGMAP_IRQ + select CIRRUS_CS48L32_IRQ + select PINCTRL + select PINCTRL_CS48L32 + help + Support for Cirrus Logic CS48L31, CS48L32 and CS48L33 Smart Codecs. + config MFD_ASIC3 bool "Compaq ASIC3" depends on GPIOLIB diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 4dd479212b3a..4edbeb9b7a31 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -91,6 +91,8 @@ obj-$(CONFIG_MFD_MADERA) += madera.o obj-$(CONFIG_MFD_MADERA_I2C) += madera-i2c.o obj-$(CONFIG_MFD_MADERA_SPI) += madera-spi.o +obj-$(CONFIG_MFD_CS48L32) += cs48l32.o cs48l32-tables.o + obj-$(CONFIG_TPS6105X) += tps6105x.o obj-$(CONFIG_TPS65010) += tps65010.o obj-$(CONFIG_TPS6507X) += tps6507x.o diff --git a/drivers/mfd/cs48l32-tables.c b/drivers/mfd/cs48l32-tables.c new file mode 100644 index 000000000000..5dab9753deb0 --- /dev/null +++ b/drivers/mfd/cs48l32-tables.c @@ -0,0 +1,541 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Regmap tables for Cirrus Logic CS48L32 audio codec. + * + * Copyright (C) 2018, 2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#include <linux/device.h> +#include <linux/module.h> +#include <linux/mfd/cs48l32/core.h> +#include <linux/mfd/cs48l32/registers.h> + +#include "cs48l32.h" + +static const struct reg_sequence cs48l32_reva_patch[] = { + { 0x00001044, 0x0005000f }, + { 0x00001c34, 0x000037e8 }, + { 0x000046d8, 0x00000fe0 }, +}; + +int cs48l32_patch(struct cs48l32_mfd *cs48l32) +{ + int ret; + + ret = regmap_register_patch(cs48l32->regmap, cs48l32_reva_patch, + ARRAY_SIZE(cs48l32_reva_patch)); + if (ret < 0) + dev_err(cs48l32->dev, "Error applying patch: %d\n", ret); + + return ret; +} + +static const struct reg_default cs48l32_reg_default[] = { + { 0x00000c08, 0xe1000001 }, /* GPIO1_CTRL1 */ + { 0x00000c0c, 0xe1000001 }, /* GPIO2_CTRL1 */ + { 0x00000c10, 0xe1000001 }, /* GPIO3_CTRL1 */ + { 0x00000c14, 0xe1000001 }, /* GPIO4_CTRL1 */ + { 0x00000c18, 0xe1000001 }, /* GPIO5_CTRL1 */ + { 0x00000c1c, 0xe1000001 }, /* GPIO6_CTRL1 */ + { 0x00000c20, 0xe1000001 }, /* GPIO7_CTRL1 */ + { 0x00000c24, 0xe1000001 }, /* GPIO8_CTRL1 */ + { 0x00000c28, 0xe1000001 }, /* GPIO9_CTRL1 */ + { 0x00000c2c, 0xe1000001 }, /* GPIO10_CTRL1 */ + { 0x00000c30, 0xe1000001 }, /* GPIO11_CTRL1 */ + { 0x00000c34, 0xe1000001 }, /* GPIO12_CTRL1 */ + { 0x00000c38, 0xe1000001 }, /* GPIO13_CTRL1 */ + { 0x00000c3c, 0xe1000001 }, /* GPIO14_CTRL1 */ + { 0x00000c40, 0xe1000001 }, /* GPIO15_CTRL1 */ + { 0x00000c44, 0xe1000001 }, /* GPIO16_CTRL1 */ + { 0x00001020, 0x00000000 }, /* OUTPUT_SYS_CLK */ + { 0x00001044, 0x0005000f }, /* AUXPDM_CTRL */ + { 0x0000105c, 0x00000000 }, /* AUXPDM_CTRL2 */ + { 0x00001400, 0x00000002 }, /* CLOCK32K */ + { 0x00001404, 0x00000404 }, /* SYSTEM_CLOCK1 */ + { 0x00001420, 0x00000003 }, /* SAMPLE_RATE1 */ + { 0x00001424, 0x00000003 }, /* SAMPLE_RATE2 */ + { 0x00001428, 0x00000003 }, /* SAMPLE_RATE3 */ + { 0x0000142c, 0x00000003 }, /* SAMPLE_RATE4 */ + { 0x00001c00, 0x00000002 }, /* FLL1_CONTROL1 */ + { 0x00001c04, 0x88203004 }, /* FLL1_CONTROL2 */ + { 0x00001c08, 0x00000000 }, /* FLL1_CONTROL3 */ + { 0x00001c0c, 0x21f05001 }, /* FLL1_CONTROL4 */ + { 0x00001ca0, 0x00000c04 }, /* FLL1_GPIO_CLOCK */ + { 0x00002000, 0x00000006 }, /* CHARGE_PUMP1 */ + { 0x00002408, 0x000003e4 }, /* LDO2_CTRL1 */ + { 0x00002410, 0x000000e6 }, /* MICBIAS_CTRL1 */ + { 0x00002418, 0x00000222 }, /* MICBIAS_CTRL5 */ + { 0x00002710, 0x00004600 }, /* IRQ1_CTRL_AOD */ + { 0x00004000, 0x00000000 }, /* INPUT_CONTROL */ + { 0x00004008, 0x00000400 }, /* INPUT_RATE_CONTROL */ + { 0x0000400c, 0x00000000 }, /* INPUT_CONTROL2 */ + { 0x00004020, 0x00050020 }, /* INPUT1_CONTROL1 */ + { 0x00004024, 0x00000000 }, /* IN1L_CONTROL1 */ + { 0x00004028, 0x10800080 }, /* IN1L_CONTROL2 */ + { 0x00004044, 0x00000000 }, /* IN1R_CONTROL1 */ + { 0x00004048, 0x10800080 }, /* IN1R_CONTROL2 */ + { 0x00004060, 0x00050020 }, /* INPUT2_CONTROL1 */ + { 0x00004064, 0x00000000 }, /* IN2L_CONTROL1 */ + { 0x00004068, 0x10800000 }, /* IN2L_CONTROL2 */ + { 0x00004084, 0x00000000 }, /* IN2R_CONTROL1 */ + { 0x00004088, 0x10800000 }, /* IN2R_CONTROL2 */ + { 0x00004244, 0x00000002 }, /* INPUT_HPF_CONTROL */ + { 0x00004248, 0x00000022 }, /* INPUT_VOL_CONTROL */ + { 0x00004300, 0x00000000 }, /* AUXPDM_CONTROL1 */ + { 0x00004304, 0x00000000 }, /* AUXPDM_CONTROL2 */ + { 0x00004308, 0x00010008 }, /* AUXPDM1_CONTROL1 */ + { 0x00004310, 0x00010008 }, /* AUXPDM2_CONTROL1 */ + { 0x00004688, 0x00000000 }, /* ADC1L_ANA_CONTROL1 */ + { 0x0000468c, 0x00000000 }, /* ADC1R_ANA_CONTROL1 */ + { 0x00006000, 0x00000000 }, /* ASP1_ENABLES1 */ + { 0x00006004, 0x00000028 }, /* ASP1_CONTROL1 */ + { 0x00006008, 0x18180200 }, /* ASP1_CONTROL2 */ + { 0x0000600c, 0x00000002 }, /* ASP1_CONTROL3 */ + { 0x00006010, 0x03020100 }, /* ASP1_FRAME_CONTROL1 */ + { 0x00006014, 0x07060504 }, /* ASP1_FRAME_CONTROL2 */ + { 0x00006020, 0x03020100 }, /* ASP1_FRAME_CONTROL5 */ + { 0x00006024, 0x07060504 }, /* ASP1_FRAME_CONTROL6 */ + { 0x00006030, 0x00000020 }, /* ASP1_DATA_CONTROL1 */ + { 0x00006040, 0x00000020 }, /* ASP1_DATA_CONTROL5 */ + { 0x00006080, 0x00000000 }, /* ASP2_ENABLES1 */ + { 0x00006084, 0x00000028 }, /* ASP2_CONTROL1 */ + { 0x00006088, 0x18180200 }, /* ASP2_CONTROL2 */ + { 0x0000608c, 0x00000002 }, /* ASP2_CONTROL3 */ + { 0x00006090, 0x03020100 }, /* ASP2_FRAME_CONTROL1 */ + { 0x000060a0, 0x03020100 }, /* ASP2_FRAME_CONTROL5 */ + { 0x000060b0, 0x00000020 }, /* ASP2_DATA_CONTROL1 */ + { 0x000060c0, 0x00000020 }, /* ASP2_DATA_CONTROL5 */ + { 0x00008200, 0x00800000 }, /* ASP1TX1_INPUT1 */ + { 0x00008204, 0x00800000 }, /* ASP1TX1_INPUT2 */ + { 0x00008208, 0x00800000 }, /* ASP1TX1_INPUT3 */ + { 0x0000820c, 0x00800000 }, /* ASP1TX1_INPUT4 */ + { 0x00008210, 0x00800000 }, /* ASP1TX2_INPUT1 */ + { 0x00008214, 0x00800000 }, /* ASP1TX2_INPUT2 */ + { 0x00008218, 0x00800000 }, /* ASP1TX2_INPUT3 */ + { 0x0000821c, 0x00800000 }, /* ASP1TX2_INPUT4 */ + { 0x00008220, 0x00800000 }, /* ASP1TX3_INPUT1 */ + { 0x00008224, 0x00800000 }, /* ASP1TX3_INPUT2 */ + { 0x00008228, 0x00800000 }, /* ASP1TX3_INPUT3 */ + { 0x0000822c, 0x00800000 }, /* ASP1TX3_INPUT4 */ + { 0x00008230, 0x00800000 }, /* ASP1TX4_INPUT1 */ + { 0x00008234, 0x00800000 }, /* ASP1TX4_INPUT2 */ + { 0x00008238, 0x00800000 }, /* ASP1TX4_INPUT3 */ + { 0x0000823c, 0x00800000 }, /* ASP1TX4_INPUT4 */ + { 0x00008240, 0x00800000 }, /* ASP1TX5_INPUT1 */ + { 0x00008244, 0x00800000 }, /* ASP1TX5_INPUT2 */ + { 0x00008248, 0x00800000 }, /* ASP1TX5_INPUT3 */ + { 0x0000824c, 0x00800000 }, /* ASP1TX5_INPUT4 */ + { 0x00008250, 0x00800000 }, /* ASP1TX6_INPUT1 */ + { 0x00008254, 0x00800000 }, /* ASP1TX6_INPUT2 */ + { 0x00008258, 0x00800000 }, /* ASP1TX6_INPUT3 */ + { 0x0000825c, 0x00800000 }, /* ASP1TX6_INPUT4 */ + { 0x00008260, 0x00800000 }, /* ASP1TX7_INPUT1 */ + { 0x00008264, 0x00800000 }, /* ASP1TX7_INPUT2 */ + { 0x00008268, 0x00800000 }, /* ASP1TX7_INPUT3 */ + { 0x0000826c, 0x00800000 }, /* ASP1TX7_INPUT4 */ + { 0x00008270, 0x00800000 }, /* ASP1TX8_INPUT1 */ + { 0x00008274, 0x00800000 }, /* ASP1TX8_INPUT2 */ + { 0x00008278, 0x00800000 }, /* ASP1TX8_INPUT3 */ + { 0x0000827c, 0x00800000 }, /* ASP1TX8_INPUT4 */ + { 0x00008300, 0x00800000 }, /* ASP2TX1_INPUT1 */ + { 0x00008304, 0x00800000 }, /* ASP2TX1_INPUT2 */ + { 0x00008308, 0x00800000 }, /* ASP2TX1_INPUT3 */ + { 0x0000830c, 0x00800000 }, /* ASP2TX1_INPUT4 */ + { 0x00008310, 0x00800000 }, /* ASP2TX2_INPUT1 */ + { 0x00008314, 0x00800000 }, /* ASP2TX2_INPUT2 */ + { 0x00008318, 0x00800000 }, /* ASP2TX2_INPUT3 */ + { 0x0000831c, 0x00800000 }, /* ASP2TX2_INPUT4 */ + { 0x00008320, 0x00800000 }, /* ASP2TX3_INPUT1 */ + { 0x00008324, 0x00800000 }, /* ASP2TX3_INPUT2 */ + { 0x00008328, 0x00800000 }, /* ASP2TX3_INPUT3 */ + { 0x0000832c, 0x00800000 }, /* ASP2TX3_INPUT4 */ + { 0x00008330, 0x00800000 }, /* ASP2TX4_INPUT1 */ + { 0x00008334, 0x00800000 }, /* ASP2TX4_INPUT2 */ + { 0x00008338, 0x00800000 }, /* ASP2TX4_INPUT3 */ + { 0x0000833c, 0x00800000 }, /* ASP2TX4_INPUT4 */ + { 0x00008980, 0x00000000 }, /* ISRC1INT1_INPUT1 */ + { 0x00008990, 0x00000000 }, /* ISRC1INT2_INPUT1 */ + { 0x000089a0, 0x00000000 }, /* ISRC1INT3_INPUT1 */ + { 0x000089b0, 0x00000000 }, /* ISRC1INT4_INPUT1 */ + { 0x000089c0, 0x00000000 }, /* ISRC1DEC1_INPUT1 */ + { 0x000089d0, 0x00000000 }, /* ISRC1DEC2_INPUT1 */ + { 0x000089e0, 0x00000000 }, /* ISRC1DEC3_INPUT1 */ + { 0x000089f0, 0x00000000 }, /* ISRC1DEC4_INPUT1 */ + { 0x00008a00, 0x00000000 }, /* ISRC2INT1_INPUT1 */ + { 0x00008a10, 0x00000000 }, /* ISRC2INT2_INPUT1 */ + { 0x00008a40, 0x00000000 }, /* ISRC2DEC1_INPUT1 */ + { 0x00008a50, 0x00000000 }, /* ISRC2DEC2_INPUT1 */ + { 0x00008a80, 0x00000000 }, /* ISRC3INT1_INPUT1 */ + { 0x00008a90, 0x00000000 }, /* ISRC3INT2_INPUT1 */ + { 0x00008ac0, 0x00000000 }, /* ISRC3DEC1_INPUT1 */ + { 0x00008ad0, 0x00000000 }, /* ISRC3DEC2_INPUT1 */ + { 0x00008b80, 0x00800000 }, /* EQ1_INPUT1 */ + { 0x00008b84, 0x00800000 }, /* EQ1_INPUT2 */ + { 0x00008b88, 0x00800000 }, /* EQ1_INPUT3 */ + { 0x00008b8c, 0x00800000 }, /* EQ1_INPUT4 */ + { 0x00008b90, 0x00800000 }, /* EQ2_INPUT1 */ + { 0x00008b94, 0x00800000 }, /* EQ2_INPUT2 */ + { 0x00008b98, 0x00800000 }, /* EQ2_INPUT3 */ + { 0x00008b9c, 0x00800000 }, /* EQ2_INPUT4 */ + { 0x00008ba0, 0x00800000 }, /* EQ3_INPUT1 */ + { 0x00008ba4, 0x00800000 }, /* EQ3_INPUT2 */ + { 0x00008ba8, 0x00800000 }, /* EQ3_INPUT3 */ + { 0x00008bac, 0x00800000 }, /* EQ3_INPUT4 */ + { 0x00008bb0, 0x00800000 }, /* EQ4_INPUT1 */ + { 0x00008bb4, 0x00800000 }, /* EQ4_INPUT2 */ + { 0x00008bb8, 0x00800000 }, /* EQ4_INPUT3 */ + { 0x00008bbc, 0x00800000 }, /* EQ4_INPUT4 */ + { 0x00008c00, 0x00800000 }, /* DRC1L_INPUT1 */ + { 0x00008c04, 0x00800000 }, /* DRC1L_INPUT2 */ + { 0x00008c08, 0x00800000 }, /* DRC1L_INPUT3 */ + { 0x00008c0c, 0x00800000 }, /* DRC1L_INPUT4 */ + { 0x00008c10, 0x00800000 }, /* DRC1R_INPUT1 */ + { 0x00008c14, 0x00800000 }, /* DRC1R_INPUT2 */ + { 0x00008c18, 0x00800000 }, /* DRC1R_INPUT3 */ + { 0x00008c1c, 0x00800000 }, /* DRC1R_INPUT4 */ + { 0x00008c20, 0x00800000 }, /* DRC2L_INPUT1 */ + { 0x00008c24, 0x00800000 }, /* DRC2L_INPUT2 */ + { 0x00008c28, 0x00800000 }, /* DRC2L_INPUT3 */ + { 0x00008c2c, 0x00800000 }, /* DRC2L_INPUT4 */ + { 0x00008c30, 0x00800000 }, /* DRC2R_INPUT1 */ + { 0x00008c34, 0x00800000 }, /* DRC2R_INPUT2 */ + { 0x00008c38, 0x00800000 }, /* DRC2R_INPUT3 */ + { 0x00008c3c, 0x00800000 }, /* DRC2R_INPUT4 */ + { 0x00008c80, 0x00800000 }, /* LHPF1_INPUT1 */ + { 0x00008c84, 0x00800000 }, /* LHPF1_INPUT2 */ + { 0x00008c88, 0x00800000 }, /* LHPF1_INPUT3 */ + { 0x00008c8c, 0x00800000 }, /* LHPF1_INPUT4 */ + { 0x00008c90, 0x00800000 }, /* LHPF2_INPUT1 */ + { 0x00008c94, 0x00800000 }, /* LHPF2_INPUT2 */ + { 0x00008c98, 0x00800000 }, /* LHPF2_INPUT3 */ + { 0x00008c9c, 0x00800000 }, /* LHPF2_INPUT4 */ + { 0x00008ca0, 0x00800000 }, /* LHPF3_INPUT1 */ + { 0x00008ca4, 0x00800000 }, /* LHPF3_INPUT2 */ + { 0x00008ca8, 0x00800000 }, /* LHPF3_INPUT3 */ + { 0x00008cac, 0x00800000 }, /* LHPF3_INPUT4 */ + { 0x00008cb0, 0x00800000 }, /* LHPF4_INPUT1 */ + { 0x00008cb4, 0x00800000 }, /* LHPF4_INPUT2 */ + { 0x00008cb8, 0x00800000 }, /* LHPF4_INPUT3 */ + { 0x00008cbc, 0x00800000 }, /* LHPF4_INPUT4 */ + { 0x00009000, 0x00800000 }, /* DSP1RX1_INPUT1 */ + { 0x00009004, 0x00800000 }, /* DSP1RX1_INPUT2 */ + { 0x00009008, 0x00800000 }, /* DSP1RX1_INPUT3 */ + { 0x0000900c, 0x00800000 }, /* DSP1RX1_INPUT4 */ + { 0x00009010, 0x00800000 }, /* DSP1RX2_INPUT1 */ + { 0x00009014, 0x00800000 }, /* DSP1RX2_INPUT2 */ + { 0x00009018, 0x00800000 }, /* DSP1RX2_INPUT3 */ + { 0x0000901c, 0x00800000 }, /* DSP1RX2_INPUT4 */ + { 0x00009020, 0x00800000 }, /* DSP1RX3_INPUT1 */ + { 0x00009024, 0x00800000 }, /* DSP1RX3_INPUT2 */ + { 0x00009028, 0x00800000 }, /* DSP1RX3_INPUT3 */ + { 0x0000902c, 0x00800000 }, /* DSP1RX3_INPUT4 */ + { 0x00009030, 0x00800000 }, /* DSP1RX4_INPUT1 */ + { 0x00009034, 0x00800000 }, /* DSP1RX4_INPUT2 */ + { 0x00009038, 0x00800000 }, /* DSP1RX4_INPUT3 */ + { 0x0000903c, 0x00800000 }, /* DSP1RX4_INPUT4 */ + { 0x00009040, 0x00800000 }, /* DSP1RX5_INPUT1 */ + { 0x00009044, 0x00800000 }, /* DSP1RX5_INPUT2 */ + { 0x00009048, 0x00800000 }, /* DSP1RX5_INPUT3 */ + { 0x0000904c, 0x00800000 }, /* DSP1RX5_INPUT4 */ + { 0x00009050, 0x00800000 }, /* DSP1RX6_INPUT1 */ + { 0x00009054, 0x00800000 }, /* DSP1RX6_INPUT2 */ + { 0x00009058, 0x00800000 }, /* DSP1RX6_INPUT3 */ + { 0x0000905c, 0x00800000 }, /* DSP1RX6_INPUT4 */ + { 0x00009060, 0x00800000 }, /* DSP1RX7_INPUT1 */ + { 0x00009064, 0x00800000 }, /* DSP1RX7_INPUT2 */ + { 0x00009068, 0x00800000 }, /* DSP1RX7_INPUT3 */ + { 0x0000906c, 0x00800000 }, /* DSP1RX7_INPUT4 */ + { 0x00009070, 0x00800000 }, /* DSP1RX8_INPUT1 */ + { 0x00009074, 0x00800000 }, /* DSP1RX8_INPUT2 */ + { 0x00009078, 0x00800000 }, /* DSP1RX8_INPUT3 */ + { 0x0000907c, 0x00800000 }, /* DSP1RX8_INPUT4 */ + { 0x0000a400, 0x00000000 }, /* ISRC1_CONTROL1 */ + { 0x0000a404, 0x00000000 }, /* ISRC1_CONTROL2 */ + { 0x0000a510, 0x00000000 }, /* ISRC2_CONTROL1 */ + { 0x0000a514, 0x00000000 }, /* ISRC2_CONTROL2 */ + { 0x0000a620, 0x00000000 }, /* ISRC3_CONTROL1 */ + { 0x0000a624, 0x00000000 }, /* ISRC3_CONTROL2 */ + { 0x0000a800, 0x00000000 }, /* FX_SAMPLE_RATE */ + { 0x0000a808, 0x00000000 }, /* EQ_CONTROL1 */ + { 0x0000a80c, 0x00000000 }, /* EQ_CONTROL2 */ + { 0x0000a810, 0x0c0c0c0c }, /* EQ1_GAIN1 */ + { 0x0000a814, 0x0000000c }, /* EQ1_GAIN2 */ + { 0x0000a818, 0x03fe0fc8 }, /* EQ1_BAND1_COEFF1 */ + { 0x0000a81c, 0x00000b75 }, /* EQ1_BAND1_COEFF2 */ + { 0x0000a820, 0x000000e0 }, /* EQ1_BAND1_PG */ + { 0x0000a824, 0xf1361ec4 }, /* EQ1_BAND2_COEFF1 */ + { 0x0000a828, 0x00000409 }, /* EQ1_BAND2_COEFF2 */ + { 0x0000a82c, 0x000004cc }, /* EQ1_BAND2_PG */ + { 0x0000a830, 0xf3371c9b }, /* EQ1_BAND3_COEFF1 */ + { 0x0000a834, 0x0000040b }, /* EQ1_BAND3_COEFF2 */ + { 0x0000a838, 0x00000cbb }, /* EQ1_BAND3_PG */ + { 0x0000a83c, 0xf7d916f8 }, /* EQ1_BAND4_COEFF1 */ + { 0x0000a840, 0x0000040a }, /* EQ1_BAND4_COEFF2 */ + { 0x0000a844, 0x00001f14 }, /* EQ1_BAND4_PG */ + { 0x0000a848, 0x0563058c }, /* EQ1_BAND5_COEFF1 */ + { 0x0000a84c, 0x00000000 }, /* EQ1_BAND5_COEFF1 + 4 */ + { 0x0000a850, 0x00004000 }, /* EQ1_BAND5_PG */ + { 0x0000a854, 0x0c0c0c0c }, /* EQ2_GAIN1 */ + { 0x0000a858, 0x0000000c }, /* EQ2_GAIN2 */ + { 0x0000a85c, 0x03fe0fc8 }, /* EQ2_BAND1_COEFF1 */ + { 0x0000a860, 0x00000b75 }, /* EQ2_BAND1_COEFF2 */ + { 0x0000a864, 0x000000e0 }, /* EQ2_BAND1_PG */ + { 0x0000a868, 0xf1361ec4 }, /* EQ2_BAND2_COEFF1 */ + { 0x0000a86c, 0x00000409 }, /* EQ2_BAND2_COEFF2 */ + { 0x0000a870, 0x000004cc }, /* EQ2_BAND2_PG */ + { 0x0000a874, 0xf3371c9b }, /* EQ2_BAND3_COEFF1 */ + { 0x0000a878, 0x0000040b }, /* EQ2_BAND3_COEFF2 */ + { 0x0000a87c, 0x00000cbb }, /* EQ2_BAND3_PG */ + { 0x0000a880, 0xf7d916f8 }, /* EQ2_BAND4_COEFF1 */ + { 0x0000a884, 0x0000040a }, /* EQ2_BAND4_COEFF2 */ + { 0x0000a888, 0x00001f14 }, /* EQ2_BAND4_PG */ + { 0x0000a88c, 0x0563058c }, /* EQ2_BAND5_COEFF1 */ + { 0x0000a890, 0x00000000 }, /* EQ2_BAND5_COEFF1 + 4 */ + { 0x0000a894, 0x00004000 }, /* EQ2_BAND5_PG */ + { 0x0000a898, 0x0c0c0c0c }, /* EQ3_GAIN1 */ + { 0x0000a89c, 0x0000000c }, /* EQ3_GAIN2 */ + { 0x0000a8a0, 0x03fe0fc8 }, /* EQ3_BAND1_COEFF1 */ + { 0x0000a8a4, 0x00000b75 }, /* EQ3_BAND1_COEFF2 */ + { 0x0000a8a8, 0x000000e0 }, /* EQ3_BAND1_PG */ + { 0x0000a8ac, 0xf1361ec4 }, /* EQ3_BAND2_COEFF1 */ + { 0x0000a8b0, 0x00000409 }, /* EQ3_BAND2_COEFF2 */ + { 0x0000a8b4, 0x000004cc }, /* EQ3_BAND2_PG */ + { 0x0000a8b8, 0xf3371c9b }, /* EQ3_BAND3_COEFF1 */ + { 0x0000a8bc, 0x0000040b }, /* EQ3_BAND3_COEFF2 */ + { 0x0000a8c0, 0x00000cbb }, /* EQ3_BAND3_PG */ + { 0x0000a8c4, 0xf7d916f8 }, /* EQ3_BAND4_COEFF1 */ + { 0x0000a8c8, 0x0000040a }, /* EQ3_BAND4_COEFF2 */ + { 0x0000a8cc, 0x00001f14 }, /* EQ3_BAND4_PG */ + { 0x0000a8d0, 0x0563058c }, /* EQ3_BAND5_COEFF1 */ + { 0x0000a8d4, 0x00000000 }, /* EQ3_BAND5_COEFF1 + 4 */ + { 0x0000a8d8, 0x00004000 }, /* EQ3_BAND5_PG */ + { 0x0000a8dc, 0x0c0c0c0c }, /* EQ4_GAIN1 */ + { 0x0000a8e0, 0x0000000c }, /* EQ4_GAIN2 */ + { 0x0000a8e4, 0x03fe0fc8 }, /* EQ4_BAND1_COEFF1 */ + { 0x0000a8e8, 0x00000b75 }, /* EQ4_BAND1_COEFF2 */ + { 0x0000a8ec, 0x000000e0 }, /* EQ4_BAND1_PG */ + { 0x0000a8f0, 0xf1361ec4 }, /* EQ4_BAND2_COEFF1 */ + { 0x0000a8f4, 0x00000409 }, /* EQ4_BAND2_COEFF2 */ + { 0x0000a8f8, 0x000004cc }, /* EQ4_BAND2_PG */ + { 0x0000a8fc, 0xf3371c9b }, /* EQ4_BAND3_COEFF1 */ + { 0x0000a900, 0x0000040b }, /* EQ4_BAND3_COEFF2 */ + { 0x0000a904, 0x00000cbb }, /* EQ4_BAND3_PG */ + { 0x0000a908, 0xf7d916f8 }, /* EQ4_BAND4_COEFF1 */ + { 0x0000a90c, 0x0000040a }, /* EQ4_BAND4_COEFF2 */ + { 0x0000a910, 0x00001f14 }, /* EQ4_BAND4_PG */ + { 0x0000a914, 0x0563058c }, /* EQ4_BAND5_COEFF1 */ + { 0x0000a918, 0x00000000 }, /* EQ4_BAND5_COEFF1 + 4 */ + { 0x0000a91c, 0x00004000 }, /* EQ4_BAND5_PG */ + { 0x0000aa30, 0x00000000 }, /* LHPF_CONTROL1 */ + { 0x0000aa34, 0x00000000 }, /* LHPF_CONTROL2 */ + { 0x0000aa38, 0x00000000 }, /* LHPF1_COEFF */ + { 0x0000aa3c, 0x00000000 }, /* LHPF2_COEFF */ + { 0x0000aa40, 0x00000000 }, /* LHPF3_COEFF */ + { 0x0000aa44, 0x00000000 }, /* LHPF4_COEFF */ + { 0x0000ab00, 0x00000000 }, /* DRC1_CONTROL1 */ + { 0x0000ab04, 0x49130018 }, /* DRC1_CONTROL2 */ + { 0x0000ab08, 0x00000018 }, /* DRC1_CONTROL3 */ + { 0x0000ab0c, 0x00000000 }, /* DRC1_CONTROL4 */ + { 0x0000ab14, 0x00000000 }, /* DRC2_CONTROL1 */ + { 0x0000ab18, 0x49130018 }, /* DRC2_CONTROL2 */ + { 0x0000ab1c, 0x00000018 }, /* DRC2_CONTROL3 */ + { 0x0000ab20, 0x00000000 }, /* DRC2_CONTROL4 */ + { 0x0000b000, 0x00000000 }, /* TONE_GENERATOR1 */ + { 0x0000b004, 0x00100000 }, /* TONE_GENERATOR2 */ + { 0x0000b400, 0x00000000 }, /* COMFORT_NOISE_GENERATOR */ + { 0x0000b800, 0x00000000 }, /* US_CONTROL */ + { 0x0000b804, 0x00002020 }, /* US1_CONTROL */ + { 0x0000b808, 0x00000000 }, /* US1_DET_CONTROL */ + { 0x0000b814, 0x00002020 }, /* US2_CONTROL */ + { 0x0000b818, 0x00000000 }, /* US2_DET_CONTROL */ + { 0x00018110, 0xffffffff }, /* IRQ1_MASK_1 */ + { 0x00018114, 0xfffffff7 }, /* IRQ1_MASK_2 */ + { 0x00018118, 0xffffffff }, /* IRQ1_MASK_3 */ + { 0x0001811c, 0xffffffff }, /* IRQ1_MASK_4 */ + { 0x00018120, 0xffffffff }, /* IRQ1_MASK_5 */ + { 0x00018124, 0xffffffff }, /* IRQ1_MASK_6 */ + { 0x00018128, 0xffffffff }, /* IRQ1_MASK_7 */ + { 0x0001812c, 0xffffffff }, /* IRQ1_MASK_8 */ + { 0x00018130, 0xffffffff }, /* IRQ1_MASK_9 */ + { 0x00018134, 0xffffffff }, /* IRQ1_MASK_10 */ + { 0x00018138, 0xffffffff }, /* IRQ1_MASK_11 */ +}; + +static bool cs48l32_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS48L32_DEVID: + case CS48L32_REVID: + case CS48L32_OTPID: + case CS48L32_SFT_RESET: + case CS48L32_CTRL_IF_DEBUG3: + case CS48L32_MCU_CTRL1: + case CS48L32_GPIO1_CTRL1 ... CS48L32_GPIO16_CTRL1: + case CS48L32_OUTPUT_SYS_CLK: + case CS48L32_AUXPDM_CTRL: + case CS48L32_AUXPDM_CTRL2: + case CS48L32_CLOCK32K: + case CS48L32_SYSTEM_CLOCK1 ... CS48L32_SYSTEM_CLOCK2: + case CS48L32_SAMPLE_RATE1 ... CS48L32_SAMPLE_RATE4: + case CS48L32_FLL1_CONTROL1 ... CS48L32_FLL1_GPIO_CLOCK: + case CS48L32_CHARGE_PUMP1: + case CS48L32_LDO2_CTRL1: + case CS48L32_MICBIAS_CTRL1: + case CS48L32_MICBIAS_CTRL5: + case CS48L32_IRQ1_CTRL_AOD: + case CS48L32_INPUT_CONTROL: + case CS48L32_INPUT_STATUS: + case CS48L32_INPUT_RATE_CONTROL: + case CS48L32_INPUT_CONTROL2: + case CS48L32_INPUT_CONTROL3: + case CS48L32_INPUT1_CONTROL1: + case CS48L32_IN1L_CONTROL1 ... CS48L32_IN1L_CONTROL2: + case CS48L32_IN1R_CONTROL1 ... CS48L32_IN1R_CONTROL2: + case CS48L32_INPUT2_CONTROL1: + case CS48L32_IN2L_CONTROL1 ... CS48L32_IN2L_CONTROL2: + case CS48L32_IN2R_CONTROL1 ... CS48L32_IN2R_CONTROL2: + case CS48L32_INPUT_HPF_CONTROL: + case CS48L32_INPUT_VOL_CONTROL: + case CS48L32_AUXPDM_CONTROL1: + case CS48L32_AUXPDM_CONTROL2: + case CS48L32_AUXPDM1_CONTROL1: + case CS48L32_AUXPDM2_CONTROL1: + case CS48L32_ADC1L_ANA_CONTROL1: + case CS48L32_ADC1R_ANA_CONTROL1: + case CS48L32_ASP1_ENABLES1 ... CS48L32_ASP1_DATA_CONTROL5: + case CS48L32_ASP2_ENABLES1 ... CS48L32_ASP2_DATA_CONTROL5: + case CS48L32_ASP1TX1_INPUT1 ... CS48L32_ASP1TX8_INPUT4: + case CS48L32_ASP2TX1_INPUT1 ... CS48L32_ASP2TX4_INPUT4: + case CS48L32_ISRC1INT1_INPUT1 ... CS48L32_ISRC1DEC4_INPUT1: + case CS48L32_ISRC2INT1_INPUT1 ... CS48L32_ISRC2DEC2_INPUT1: + case CS48L32_ISRC3INT1_INPUT1 ... CS48L32_ISRC3DEC2_INPUT1: + case CS48L32_EQ1_INPUT1 ... CS48L32_EQ4_INPUT4: + case CS48L32_DRC1L_INPUT1 ... CS48L32_DRC1R_INPUT4: + case CS48L32_DRC2L_INPUT1 ... CS48L32_DRC2R_INPUT4: + case CS48L32_LHPF1_INPUT1 ... CS48L32_LHPF1_INPUT4: + case CS48L32_LHPF2_INPUT1 ... CS48L32_LHPF2_INPUT4: + case CS48L32_LHPF3_INPUT1 ... CS48L32_LHPF3_INPUT4: + case CS48L32_LHPF4_INPUT1 ... CS48L32_LHPF4_INPUT4: + case CS48L32_DSP1RX1_INPUT1 ... CS48L32_DSP1RX8_INPUT4: + case CS48L32_ISRC1_CONTROL1 ... CS48L32_ISRC1_CONTROL2: + case CS48L32_ISRC2_CONTROL1 ... CS48L32_ISRC2_CONTROL2: + case CS48L32_ISRC3_CONTROL1 ... CS48L32_ISRC3_CONTROL2: + case CS48L32_FX_SAMPLE_RATE: + case CS48L32_EQ_CONTROL1 ... CS48L32_EQ_CONTROL2: + case CS48L32_EQ1_GAIN1 ... CS48L32_EQ1_BAND5_PG: + case CS48L32_EQ2_GAIN1 ... CS48L32_EQ2_BAND5_PG: + case CS48L32_EQ3_GAIN1 ... CS48L32_EQ3_BAND5_PG: + case CS48L32_EQ4_GAIN1 ... CS48L32_EQ4_BAND5_PG: + case CS48L32_LHPF_CONTROL1 ... CS48L32_LHPF_CONTROL2: + case CS48L32_LHPF1_COEFF ... CS48L32_LHPF4_COEFF: + case CS48L32_DRC1_CONTROL1 ... CS48L32_DRC1_CONTROL4: + case CS48L32_DRC2_CONTROL1 ... CS48L32_DRC2_CONTROL4: + case CS48L32_TONE_GENERATOR1 ... CS48L32_TONE_GENERATOR2: + case CS48L32_COMFORT_NOISE_GENERATOR: + case CS48L32_US_CONTROL: + case CS48L32_US1_CONTROL: + case CS48L32_US1_DET_CONTROL: + case CS48L32_US2_CONTROL: + case CS48L32_US2_DET_CONTROL: + case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24: + case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8: + case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7: + case CS48L32_IRQ1_STATUS: + case CS48L32_IRQ1_EINT_1 ... CS48L32_IRQ1_EINT_11: + case CS48L32_IRQ1_STS_1 ... CS48L32_IRQ1_STS_11: + case CS48L32_IRQ1_MASK_1 ... CS48L32_IRQ1_MASK_11: + case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_147455: + case CS48L32_DSP1_SYS_INFO_ID ... CS48L32_DSP1_AHBM_WINDOW_DEBUG_1: + case CS48L32_DSP1_XMEM_UNPACKED24_0 ... CS48L32_DSP1_XMEM_UNPACKED24_196607: + case CS48L32_DSP1_CLOCK_FREQ ... CS48L32_DSP1_SAMPLE_RATE_TX8: + case CS48L32_DSP1_SCRATCH1 ... CS48L32_DSP1_SCRATCH4: + case CS48L32_DSP1_CCM_CORE_CONTROL ... CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1: + case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_49151: + case CS48L32_DSP1_YMEM_UNPACKED24_0 ... CS48L32_DSP1_YMEM_UNPACKED24_65535: + case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_71679: + return true; + default: + return false; + } +} + +static bool cs48l32_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS48L32_DEVID: + case CS48L32_REVID: + case CS48L32_OTPID: + case CS48L32_SFT_RESET: + case CS48L32_CTRL_IF_DEBUG3: + case CS48L32_MCU_CTRL1: + case CS48L32_SYSTEM_CLOCK2: + case CS48L32_FLL1_CONTROL5: + case CS48L32_FLL1_CONTROL6: + case CS48L32_INPUT_STATUS: + case CS48L32_INPUT_CONTROL3: + case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24: + case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8: + case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7: + case CS48L32_IRQ1_STATUS: + case CS48L32_IRQ1_EINT_1 ... CS48L32_IRQ1_EINT_11: + case CS48L32_IRQ1_STS_1 ... CS48L32_IRQ1_STS_11: + case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_147455: + case CS48L32_DSP1_SYS_INFO_ID ... CS48L32_DSP1_AHBM_WINDOW_DEBUG_1: + case CS48L32_DSP1_XMEM_UNPACKED24_0 ... CS48L32_DSP1_XMEM_UNPACKED24_196607: + case CS48L32_DSP1_CLOCK_FREQ ... CS48L32_DSP1_SAMPLE_RATE_TX8: + case CS48L32_DSP1_SCRATCH1 ... CS48L32_DSP1_SCRATCH4: + case CS48L32_DSP1_CCM_CORE_CONTROL ... CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1: + case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_49151: + case CS48L32_DSP1_YMEM_UNPACKED24_0 ... CS48L32_DSP1_YMEM_UNPACKED24_65535: + case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_71679: + return true; + default: + return false; + } +} + +/* + * The bus bridge requires DSP packed memory registers to be accessed in + * aligned block multiples. + * Mark precious to prevent regmap debugfs causing an illegal bus transaction. + */ +static bool cs48l32_precious_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_147455: + case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_49151: + case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_71679: + return true; + default: + return false; + } +} + +static const struct regmap_config cs48l32_spi_regmap = { + .name = "cs48l32", + .reg_bits = 32, + .reg_stride = 4, + .pad_bits = 32, + .val_bits = 32, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .val_format_endian = REGMAP_ENDIAN_BIG, + + .max_register = CS48L32_DSP1_PMEM_71679, + .readable_reg = &cs48l32_readable_register, + .volatile_reg = &cs48l32_volatile_register, + .precious_reg = &cs48l32_precious_register, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = cs48l32_reg_default, + .num_reg_defaults = ARRAY_SIZE(cs48l32_reg_default), +}; + +int cs48l32_init_regmap(struct spi_device *spi, struct cs48l32_mfd *cs48l32) +{ + cs48l32->regmap = devm_regmap_init_spi(spi, &cs48l32_spi_regmap); + if (IS_ERR(cs48l32->regmap)) + return PTR_ERR(cs48l32->regmap); + + return 0; +} diff --git a/drivers/mfd/cs48l32.c b/drivers/mfd/cs48l32.c new file mode 100644 index 000000000000..9506a1e0560b --- /dev/null +++ b/drivers/mfd/cs48l32.c @@ -0,0 +1,434 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MFD for Cirrus Logic CS48L32 audio codec. + * + * Copyright (C) 2016-2018, 2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/gpio/consumer.h> +#include <linux/mfd/core.h> +#include <linux/mfd/cs48l32/core.h> +#include <linux/mfd/cs48l32/registers.h> +#include <linux/module.h> +#include <linux/notifier.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/consumer.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/property.h> +#include <linux/regmap.h> +#include <linux/regulator/consumer.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/of_regulator.h> +#include <linux/spi/spi.h> + +#include "cs48l32.h" + +static const char * const cs48l32_core_supplies[] = { + "VDD_A", + "VDD_IO", +}; + +static const char * const cs48l32_supplies[] = { + "VOUT_MIC", + "VDD_CP", +}; + +static const struct mfd_cell cs48l32_devs[] = { + { .name = "cs48l32-pinctrl", }, + { .name = "cs48l32-irq", }, + { .name = "cs48l32-micsupp", }, + { + .name = "cs48l32-codec", + .parent_supplies = cs48l32_supplies, + .num_parent_supplies = ARRAY_SIZE(cs48l32_supplies), + }, +}; + +static int cs48l32_wait_for_boot(struct cs48l32_mfd *cs48l32) +{ + unsigned int val; + int i, ret; + + /* regmap_read_poll_timeout would fail on read errors so roll our own */ + for (i = 0; i < CS48L32_BOOT_TIMEOUT_MS; ++i) { + val = 0; + regmap_read(cs48l32->regmap, CS48L32_IRQ1_EINT_2, &val); + if (val & CS48L32_BOOT_DONE_EINT1_MASK) + break; + + usleep_range(1000, 2000); + } + if (i == CS48L32_BOOT_TIMEOUT_MS) { + dev_err(cs48l32->dev, "BOOT_DONE timed out\n"); + return -ETIMEDOUT; + } + + ret = regmap_read(cs48l32->regmap, CS48L32_MCU_CTRL1, &val); + if (ret) { + dev_err(cs48l32->dev, "Failed to read MCU_CTRL1: %d\n", ret); + return ret; + } + + if (val & BIT(CS48L32_MCU_STS_SHIFT)) { + dev_err(cs48l32->dev, "MCU boot failed\n"); + return -EIO; + } + + ret = regmap_set_bits(cs48l32->regmap, CS48L32_CTRL_IF_DEBUG3, CS48L32_SEEN_BOOT_DONE); + if (ret) { + dev_err(cs48l32->dev, "Failed to write CTRL_IF_DEBUG3: %d\n", ret); + return ret; + } + + pm_runtime_mark_last_busy(cs48l32->dev); + + return 0; +} + +static int cs48l32_soft_reset(struct cs48l32_mfd *cs48l32) +{ + int ret; + + ret = regmap_write(cs48l32->regmap, CS48L32_SFT_RESET, CS48L32_SFT_RESET_MAGIC); + if (ret != 0) { + dev_err(cs48l32->dev, "Failed to write soft reset: %d\n", ret); + return ret; + } + + usleep_range(2000, 3000); + + return 0; +} + +static void cs48l32_enable_hard_reset(struct cs48l32_mfd *cs48l32) +{ + if (cs48l32->reset_gpio) + gpiod_set_value_cansleep(cs48l32->reset_gpio, 0); +} + +static void cs48l32_disable_hard_reset(struct cs48l32_mfd *cs48l32) +{ + if (cs48l32->reset_gpio) { + gpiod_set_value_cansleep(cs48l32->reset_gpio, 1); + usleep_range(2000, 3000); + } +} + +static int __maybe_unused cs48l32_runtime_resume(struct device *dev) +{ + struct cs48l32_mfd *cs48l32 = dev_get_drvdata(dev); + unsigned int val; + int ret; + + dev_dbg(cs48l32->dev, "Leaving sleep mode\n"); + + ret = regulator_enable(cs48l32->vdd_d); + if (ret) { + dev_err(cs48l32->dev, "Failed to enable VDD_D: %d\n", ret); + return ret; + } + + usleep_range(2000, 3000); + + regcache_cache_only(cs48l32->regmap, false); + + /* Did it power down during suspend? */ + ret = regmap_read(cs48l32->regmap, CS48L32_CTRL_IF_DEBUG3, &val); + if ((ret == 0) && (val & CS48L32_SEEN_BOOT_DONE)) { + dev_dbg(cs48l32->dev, "VDD_D didn't power off during suspend\n"); + } else { + ret = cs48l32_wait_for_boot(cs48l32); + if (ret) + goto err; + + /* Flag that the registers have reset to defaults */ + regcache_mark_dirty(cs48l32->regmap); + } + + ret = regcache_sync(cs48l32->regmap); + if (ret) { + dev_err(cs48l32->dev, "Failed to restore register cache\n"); + goto err; + } + + return 0; + +err: + regcache_cache_only(cs48l32->regmap, true); + regulator_disable(cs48l32->vdd_d); + return ret; +} + +static int __maybe_unused cs48l32_runtime_suspend(struct device *dev) +{ + struct cs48l32_mfd *cs48l32 = dev_get_drvdata(dev); + + dev_dbg(cs48l32->dev, "Entering sleep mode\n"); + + regcache_cache_only(cs48l32->regmap, true); + regulator_disable(cs48l32->vdd_d); + + return 0; +} + +static const struct dev_pm_ops cs48l32_pm_ops = { + SET_RUNTIME_PM_OPS(cs48l32_runtime_suspend, cs48l32_runtime_resume, NULL) +}; + +static const struct __maybe_unused of_device_id cs48l32_of_match[] = { + { .compatible = "cirrus,cs48l31", }, + { .compatible = "cirrus,cs48l32", }, + { .compatible = "cirrus,cs48l33", }, + {}, +}; + +static int cs48l32_configure_clk32k(struct cs48l32_mfd *cs48l32) +{ + int ret = 0; + + ret = clk_prepare_enable(cs48l32->mclk1); + if (ret) { + dev_err(cs48l32->dev, "Failed to enable 32k clock: %d\n", ret); + return ret; + } + + ret = regmap_update_bits(cs48l32->regmap, CS48L32_CLOCK32K, + CS48L32_CLK_32K_EN_MASK | CS48L32_CLK_32K_SRC_MASK, + CS48L32_CLK_32K_EN_MASK | CS48L32_32K_MCLK1); + if (ret) { + dev_err(cs48l32->dev, "Failed to init 32k clock: %d\n", ret); + clk_disable_unprepare(cs48l32->mclk1); + return ret; + } + + return 0; +} + +static int cs48l32_get_clocks(struct cs48l32_mfd *cs48l32) +{ + cs48l32->mclk1 = devm_clk_get_optional(cs48l32->dev, "mclk1"); + if (IS_ERR(cs48l32->mclk1)) + return dev_err_probe(cs48l32->dev, PTR_ERR(cs48l32->mclk1), + "Failed to get mclk1\n"); + + return 0; +} + +static int cs48l32_get_reset_gpio(struct cs48l32_mfd *cs48l32) +{ + struct gpio_desc *reset; + + reset = devm_gpiod_get_optional(cs48l32->dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(reset)) + return dev_err_probe(cs48l32->dev, PTR_ERR(reset), "Failed to request /RESET\n"); + + /* + * A hard reset is needed for full reset of the chip. We allow running + * without hard reset only because it can be useful for early + * prototyping and some debugging, but we need to warn it's not ideal. + */ + if (!reset) + dev_warn(cs48l32->dev, "Running without reset GPIO is not recommended\n"); + + cs48l32->reset_gpio = reset; + + return 0; +} + +static int cs48l32_spi_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct cs48l32_mfd *cs48l32; + unsigned int hwid, rev, otp_rev; + int i, ret; + + cs48l32 = devm_kzalloc(&spi->dev, sizeof(*cs48l32), GFP_KERNEL); + if (!cs48l32) + return -ENOMEM; + + ret = cs48l32_init_regmap(spi, cs48l32); + if (ret) + return dev_err_probe(&spi->dev, ret, "Failed to allocate regmap\n"); + + cs48l32->dev = dev; + cs48l32->irq = spi->irq; + + dev_set_drvdata(cs48l32->dev, cs48l32); + + BLOCKING_INIT_NOTIFIER_HEAD(&cs48l32->notifier); + + regcache_cache_only(cs48l32->regmap, true); + + ret = cs48l32_get_reset_gpio(cs48l32); + if (ret) + return ret; + + ret = cs48l32_get_clocks(cs48l32); + if (ret) + return ret; + + for (i = 0; i < ARRAY_SIZE(cs48l32_core_supplies); i++) + cs48l32->core_supplies[i].supply = cs48l32_core_supplies[i]; + + cs48l32->num_core_supplies = ARRAY_SIZE(cs48l32_core_supplies); + + ret = devm_regulator_bulk_get(dev, cs48l32->num_core_supplies, cs48l32->core_supplies); + if (ret) + return dev_err_probe(dev, ret, "Failed to request core supplies\n"); + + cs48l32->vdd_d = devm_regulator_get(cs48l32->dev, "VDD_D"); + if (IS_ERR(cs48l32->vdd_d)) + return dev_err_probe(dev, PTR_ERR(cs48l32->vdd_d), "Failed to request VDD_D\n"); + + ret = regulator_set_voltage(cs48l32->vdd_d, 1200000, 1200000); + if (ret) + return dev_err_probe(dev, ret, "Failed to request VDD_D=1.2v\n"); + + ret = regulator_bulk_enable(cs48l32->num_core_supplies, cs48l32->core_supplies); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable core supplies\n"); + + ret = regulator_enable(cs48l32->vdd_d); + if (ret) { + dev_err(dev, "Failed to enable VDD_D: %d\n", ret); + goto err_enable; + } + + cs48l32_disable_hard_reset(cs48l32); + + regcache_cache_only(cs48l32->regmap, false); + + /* If we don't have a reset GPIO use a soft reset */ + if (!cs48l32->reset_gpio) { + ret = cs48l32_soft_reset(cs48l32); + if (ret) + goto err_reset; + } + + ret = cs48l32_wait_for_boot(cs48l32); + if (ret) { + dev_err(cs48l32->dev, "Device failed initial boot: %d\n", ret); + goto err_reset; + } + + ret = regmap_read(cs48l32->regmap, CS48L32_DEVID, &hwid); + if (ret) { + dev_err(dev, "Failed to read ID register: %d\n", ret); + goto err_reset; + } + hwid &= CS48L32_DEVID_MASK; + + switch (hwid) { + case CS48L31_SILICON_ID: + case CS48L32_SILICON_ID: + case CS48L33_SILICON_ID: + break; + default: + dev_err(cs48l32->dev, "Unknown device ID: %x\n", hwid); + ret = -EINVAL; + goto err_reset; + } + + ret = regmap_read(cs48l32->regmap, CS48L32_REVID, &rev); + if (ret) { + dev_err(dev, "Failed to read revision register: %d\n", ret); + goto err_reset; + } + rev &= CS48L32_AREVID_MASK | CS48L32_MTLREVID_MASK; + + ret = regmap_read(cs48l32->regmap, CS48L32_OTPID, &otp_rev); + if (ret) { + dev_err(dev, "Failed to read OTP revision register: %d\n", ret); + goto err_reset; + } + otp_rev &= CS48L32_OTPID_MASK; + + cs48l32->part = hwid & 0xff; + + dev_info(dev, "CS48L%x revision %X%u.%u\n", cs48l32->part, + rev >> CS48L32_AREVID_SHIFT, rev & CS48L32_MTLREVID_MASK, otp_rev); + + /* Apply hardware patch */ + ret = cs48l32_patch(cs48l32); + if (ret) { + dev_err(cs48l32->dev, "Failed to apply patch %d\n", ret); + goto err_reset; + } + + ret = cs48l32_configure_clk32k(cs48l32); + if (ret) + goto err_reset; + + pm_runtime_set_active(cs48l32->dev); + pm_runtime_enable(cs48l32->dev); + pm_runtime_set_autosuspend_delay(cs48l32->dev, 100); + pm_runtime_use_autosuspend(cs48l32->dev); + + ret = mfd_add_devices(cs48l32->dev, PLATFORM_DEVID_NONE, + cs48l32_devs, ARRAY_SIZE(cs48l32_devs), NULL, 0, NULL); + if (ret) { + dev_err(cs48l32->dev, "Failed to add subdevices: %d\n", ret); + goto err_clk32k; + } + + return 0; + +err_clk32k: + clk_disable_unprepare(cs48l32->mclk1); +err_reset: + cs48l32_enable_hard_reset(cs48l32); + regulator_disable(cs48l32->vdd_d); +err_enable: + regulator_bulk_disable(cs48l32->num_core_supplies, cs48l32->core_supplies); + + return ret; +} + +static void cs48l32_spi_remove(struct spi_device *spi) +{ + struct cs48l32_mfd *cs48l32 = spi_get_drvdata(spi); + + /* Prevent any IRQs being serviced while we clean up */ + disable_irq(cs48l32->irq); + + mfd_remove_devices(cs48l32->dev); + + pm_runtime_disable(cs48l32->dev); + regulator_disable(cs48l32->vdd_d); + clk_disable_unprepare(cs48l32->mclk1); + cs48l32_enable_hard_reset(cs48l32); + regulator_bulk_disable(cs48l32->num_core_supplies, cs48l32->core_supplies); +} + +static const struct spi_device_id cs48l32_spi_ids[] = { + { "cs48l31", }, + { "cs48l32", }, + { "cs48l33", }, + { }, +}; +MODULE_DEVICE_TABLE(spi, cs48l32_spi_ids); + +static struct spi_driver cs48l32_spi_driver = { + .driver = { + .name = "cs48l32", + .owner = THIS_MODULE, + .pm = &cs48l32_pm_ops, + .of_match_table = of_match_ptr(cs48l32_of_match), + }, + .probe = &cs48l32_spi_probe, + .remove = &cs48l32_spi_remove, + .id_table = cs48l32_spi_ids, +}; + +module_spi_driver(cs48l32_spi_driver); + +MODULE_SOFTDEP("pre: pinctrl-cs48l32 irq-cirrus-cs48l32"); +MODULE_DESCRIPTION("CS48L32 MFD driver"); +MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/cs48l32.h b/drivers/mfd/cs48l32.h new file mode 100644 index 000000000000..36020c0cd686 --- /dev/null +++ b/drivers/mfd/cs48l32.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * MFD for Cirrus Logic CS48L32 audio codec. + * + * Copyright (C) 2016-2018, 2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef CS48L32_MFD_H +#define CS48L32_MFD_H + +#include <linux/bits.h> + +#define CS48L31_SILICON_ID 0x48a31 +#define CS48L32_SILICON_ID 0x48a32 +#define CS48L33_SILICON_ID 0x48a33 + +#define CS48L32_32K_MCLK1 0 + +#define CS48L32_SFT_RESET_MAGIC 0x5a000000 +#define CS48L32_SEEN_BOOT_DONE BIT(0) + +#define CS48L32_BOOT_TIMEOUT_MS 25 + +int cs48l32_init_regmap(struct spi_device *spi, struct cs48l32_mfd *cs48l32); +int cs48l32_patch(struct cs48l32_mfd *cs48l32); + +#endif diff --git a/include/linux/mfd/cs48l32/core.h b/include/linux/mfd/cs48l32/core.h new file mode 100644 index 000000000000..1c4269d70c8c --- /dev/null +++ b/include/linux/mfd/cs48l32/core.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * MFD for Cirrus Logic CS48L32 audio codec. + * + * Copyright (C) 2016-2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef CS48L32_CORE_H +#define CS48L32_CORE_H + +#include <linux/clk.h> +#include <linux/gpio/consumer.h> +#include <linux/interrupt.h> +#include <linux/notifier.h> +#include <linux/regmap.h> +#include <linux/regulator/consumer.h> + +#define CS48L32_MAX_CORE_SUPPLIES 2 + +struct snd_soc_dapm_context; + +struct cs48l32_mfd { + struct regmap *regmap; + struct device *dev; + struct gpio_desc *reset_gpio; + struct clk *mclk1; + struct snd_soc_dapm_context *dapm; + + int num_core_supplies; + struct regulator_bulk_data core_supplies[CS48L32_MAX_CORE_SUPPLIES]; + struct regulator *vdd_d; + + struct device *irq_dev; + struct regmap_irq_chip_data *irq_data; + int irq; + + u8 part; + + struct blocking_notifier_head notifier; +}; + +static inline int cs48l32_call_notifiers(struct cs48l32_mfd *mfd, + unsigned long event, + void *data) +{ + return blocking_notifier_call_chain(&mfd->notifier, event, data); +} +#endif -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 03/12] mfd: cs48l32: Add support for CS48L31/32/33 codecs @ 2022-11-09 16:53 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches, Richard Fitzgerald From: Piotr Stankiewicz <piotrs@opensource.cirrus.com> The CS48L31/32/33 audio codecs are multi-function devices containing gpios, irq controller and regulators in addition to the core audio functionality. Signed-off-by: Piotr Stankiewicz <piotrs@opensource.cirrus.com> Signed-off-by: Qi Zhou <qi.zhou@cirrus.com> Signed-off-by: Stuart Henderson <stuarth@opensource.cirrus.com> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- MAINTAINERS | 5 +- drivers/mfd/Kconfig | 13 + drivers/mfd/Makefile | 2 + drivers/mfd/cs48l32-tables.c | 541 +++++++++++++++++++++++++++++++ drivers/mfd/cs48l32.c | 434 +++++++++++++++++++++++++ drivers/mfd/cs48l32.h | 28 ++ include/linux/mfd/cs48l32/core.h | 49 +++ 7 files changed, 1071 insertions(+), 1 deletion(-) create mode 100644 drivers/mfd/cs48l32-tables.c create mode 100644 drivers/mfd/cs48l32.c create mode 100644 drivers/mfd/cs48l32.h create mode 100644 include/linux/mfd/cs48l32/core.h diff --git a/MAINTAINERS b/MAINTAINERS index 3f94ed38089b..f1d696f29f11 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5001,7 +5001,7 @@ F: include/dt-bindings/pinctrl/lochnagar.h F: include/linux/mfd/lochnagar* F: sound/soc/codecs/lochnagar-sc.c -CIRRUS LOGIC MADERA CODEC DRIVERS +CIRRUS LOGIC MADERA/CS48L32 CODEC DRIVERS M: Charles Keepax <ckeepax@opensource.cirrus.com> M: Richard Fitzgerald <rf@opensource.cirrus.com> L: alsa-devel@alsa-project.org (moderated for non-subscribers) @@ -5009,16 +5009,19 @@ L: patches@opensource.cirrus.com S: Supported W: https://github.com/CirrusLogic/linux-drivers/wiki T: git https://github.com/CirrusLogic/linux-drivers.git +F: Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml F: Documentation/devicetree/bindings/mfd/cirrus,madera.yaml F: Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml F: Documentation/devicetree/bindings/sound/cirrus,madera.yaml F: drivers/gpio/gpio-madera* F: drivers/irqchip/irq-madera* F: drivers/mfd/cs47l* +F: drivers/mfd/cs48l* F: drivers/mfd/madera* F: drivers/pinctrl/cirrus/* F: include/dt-bindings/sound/madera* F: include/linux/irqchip/irq-madera* +F: include/linux/mfd/cs48l32/* F: include/linux/mfd/madera/* F: include/sound/madera* F: sound/soc/codecs/cs47l* diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 6653d03e0fe3..2be52ba23c7a 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -300,6 +300,19 @@ config MFD_CS47L92 help Support for Cirrus Logic CS42L92, CS47L92 and CS47L93 Smart Codecs +config MFD_CS48L32 + bool "Cirrus Logic CS48L31/32/33" + depends on SPI_MASTER + select MFD_CORE + select REGMAP + select REGMAP_SPI + select REGMAP_IRQ + select CIRRUS_CS48L32_IRQ + select PINCTRL + select PINCTRL_CS48L32 + help + Support for Cirrus Logic CS48L31, CS48L32 and CS48L33 Smart Codecs. + config MFD_ASIC3 bool "Compaq ASIC3" depends on GPIOLIB diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 4dd479212b3a..4edbeb9b7a31 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -91,6 +91,8 @@ obj-$(CONFIG_MFD_MADERA) += madera.o obj-$(CONFIG_MFD_MADERA_I2C) += madera-i2c.o obj-$(CONFIG_MFD_MADERA_SPI) += madera-spi.o +obj-$(CONFIG_MFD_CS48L32) += cs48l32.o cs48l32-tables.o + obj-$(CONFIG_TPS6105X) += tps6105x.o obj-$(CONFIG_TPS65010) += tps65010.o obj-$(CONFIG_TPS6507X) += tps6507x.o diff --git a/drivers/mfd/cs48l32-tables.c b/drivers/mfd/cs48l32-tables.c new file mode 100644 index 000000000000..5dab9753deb0 --- /dev/null +++ b/drivers/mfd/cs48l32-tables.c @@ -0,0 +1,541 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Regmap tables for Cirrus Logic CS48L32 audio codec. + * + * Copyright (C) 2018, 2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#include <linux/device.h> +#include <linux/module.h> +#include <linux/mfd/cs48l32/core.h> +#include <linux/mfd/cs48l32/registers.h> + +#include "cs48l32.h" + +static const struct reg_sequence cs48l32_reva_patch[] = { + { 0x00001044, 0x0005000f }, + { 0x00001c34, 0x000037e8 }, + { 0x000046d8, 0x00000fe0 }, +}; + +int cs48l32_patch(struct cs48l32_mfd *cs48l32) +{ + int ret; + + ret = regmap_register_patch(cs48l32->regmap, cs48l32_reva_patch, + ARRAY_SIZE(cs48l32_reva_patch)); + if (ret < 0) + dev_err(cs48l32->dev, "Error applying patch: %d\n", ret); + + return ret; +} + +static const struct reg_default cs48l32_reg_default[] = { + { 0x00000c08, 0xe1000001 }, /* GPIO1_CTRL1 */ + { 0x00000c0c, 0xe1000001 }, /* GPIO2_CTRL1 */ + { 0x00000c10, 0xe1000001 }, /* GPIO3_CTRL1 */ + { 0x00000c14, 0xe1000001 }, /* GPIO4_CTRL1 */ + { 0x00000c18, 0xe1000001 }, /* GPIO5_CTRL1 */ + { 0x00000c1c, 0xe1000001 }, /* GPIO6_CTRL1 */ + { 0x00000c20, 0xe1000001 }, /* GPIO7_CTRL1 */ + { 0x00000c24, 0xe1000001 }, /* GPIO8_CTRL1 */ + { 0x00000c28, 0xe1000001 }, /* GPIO9_CTRL1 */ + { 0x00000c2c, 0xe1000001 }, /* GPIO10_CTRL1 */ + { 0x00000c30, 0xe1000001 }, /* GPIO11_CTRL1 */ + { 0x00000c34, 0xe1000001 }, /* GPIO12_CTRL1 */ + { 0x00000c38, 0xe1000001 }, /* GPIO13_CTRL1 */ + { 0x00000c3c, 0xe1000001 }, /* GPIO14_CTRL1 */ + { 0x00000c40, 0xe1000001 }, /* GPIO15_CTRL1 */ + { 0x00000c44, 0xe1000001 }, /* GPIO16_CTRL1 */ + { 0x00001020, 0x00000000 }, /* OUTPUT_SYS_CLK */ + { 0x00001044, 0x0005000f }, /* AUXPDM_CTRL */ + { 0x0000105c, 0x00000000 }, /* AUXPDM_CTRL2 */ + { 0x00001400, 0x00000002 }, /* CLOCK32K */ + { 0x00001404, 0x00000404 }, /* SYSTEM_CLOCK1 */ + { 0x00001420, 0x00000003 }, /* SAMPLE_RATE1 */ + { 0x00001424, 0x00000003 }, /* SAMPLE_RATE2 */ + { 0x00001428, 0x00000003 }, /* SAMPLE_RATE3 */ + { 0x0000142c, 0x00000003 }, /* SAMPLE_RATE4 */ + { 0x00001c00, 0x00000002 }, /* FLL1_CONTROL1 */ + { 0x00001c04, 0x88203004 }, /* FLL1_CONTROL2 */ + { 0x00001c08, 0x00000000 }, /* FLL1_CONTROL3 */ + { 0x00001c0c, 0x21f05001 }, /* FLL1_CONTROL4 */ + { 0x00001ca0, 0x00000c04 }, /* FLL1_GPIO_CLOCK */ + { 0x00002000, 0x00000006 }, /* CHARGE_PUMP1 */ + { 0x00002408, 0x000003e4 }, /* LDO2_CTRL1 */ + { 0x00002410, 0x000000e6 }, /* MICBIAS_CTRL1 */ + { 0x00002418, 0x00000222 }, /* MICBIAS_CTRL5 */ + { 0x00002710, 0x00004600 }, /* IRQ1_CTRL_AOD */ + { 0x00004000, 0x00000000 }, /* INPUT_CONTROL */ + { 0x00004008, 0x00000400 }, /* INPUT_RATE_CONTROL */ + { 0x0000400c, 0x00000000 }, /* INPUT_CONTROL2 */ + { 0x00004020, 0x00050020 }, /* INPUT1_CONTROL1 */ + { 0x00004024, 0x00000000 }, /* IN1L_CONTROL1 */ + { 0x00004028, 0x10800080 }, /* IN1L_CONTROL2 */ + { 0x00004044, 0x00000000 }, /* IN1R_CONTROL1 */ + { 0x00004048, 0x10800080 }, /* IN1R_CONTROL2 */ + { 0x00004060, 0x00050020 }, /* INPUT2_CONTROL1 */ + { 0x00004064, 0x00000000 }, /* IN2L_CONTROL1 */ + { 0x00004068, 0x10800000 }, /* IN2L_CONTROL2 */ + { 0x00004084, 0x00000000 }, /* IN2R_CONTROL1 */ + { 0x00004088, 0x10800000 }, /* IN2R_CONTROL2 */ + { 0x00004244, 0x00000002 }, /* INPUT_HPF_CONTROL */ + { 0x00004248, 0x00000022 }, /* INPUT_VOL_CONTROL */ + { 0x00004300, 0x00000000 }, /* AUXPDM_CONTROL1 */ + { 0x00004304, 0x00000000 }, /* AUXPDM_CONTROL2 */ + { 0x00004308, 0x00010008 }, /* AUXPDM1_CONTROL1 */ + { 0x00004310, 0x00010008 }, /* AUXPDM2_CONTROL1 */ + { 0x00004688, 0x00000000 }, /* ADC1L_ANA_CONTROL1 */ + { 0x0000468c, 0x00000000 }, /* ADC1R_ANA_CONTROL1 */ + { 0x00006000, 0x00000000 }, /* ASP1_ENABLES1 */ + { 0x00006004, 0x00000028 }, /* ASP1_CONTROL1 */ + { 0x00006008, 0x18180200 }, /* ASP1_CONTROL2 */ + { 0x0000600c, 0x00000002 }, /* ASP1_CONTROL3 */ + { 0x00006010, 0x03020100 }, /* ASP1_FRAME_CONTROL1 */ + { 0x00006014, 0x07060504 }, /* ASP1_FRAME_CONTROL2 */ + { 0x00006020, 0x03020100 }, /* ASP1_FRAME_CONTROL5 */ + { 0x00006024, 0x07060504 }, /* ASP1_FRAME_CONTROL6 */ + { 0x00006030, 0x00000020 }, /* ASP1_DATA_CONTROL1 */ + { 0x00006040, 0x00000020 }, /* ASP1_DATA_CONTROL5 */ + { 0x00006080, 0x00000000 }, /* ASP2_ENABLES1 */ + { 0x00006084, 0x00000028 }, /* ASP2_CONTROL1 */ + { 0x00006088, 0x18180200 }, /* ASP2_CONTROL2 */ + { 0x0000608c, 0x00000002 }, /* ASP2_CONTROL3 */ + { 0x00006090, 0x03020100 }, /* ASP2_FRAME_CONTROL1 */ + { 0x000060a0, 0x03020100 }, /* ASP2_FRAME_CONTROL5 */ + { 0x000060b0, 0x00000020 }, /* ASP2_DATA_CONTROL1 */ + { 0x000060c0, 0x00000020 }, /* ASP2_DATA_CONTROL5 */ + { 0x00008200, 0x00800000 }, /* ASP1TX1_INPUT1 */ + { 0x00008204, 0x00800000 }, /* ASP1TX1_INPUT2 */ + { 0x00008208, 0x00800000 }, /* ASP1TX1_INPUT3 */ + { 0x0000820c, 0x00800000 }, /* ASP1TX1_INPUT4 */ + { 0x00008210, 0x00800000 }, /* ASP1TX2_INPUT1 */ + { 0x00008214, 0x00800000 }, /* ASP1TX2_INPUT2 */ + { 0x00008218, 0x00800000 }, /* ASP1TX2_INPUT3 */ + { 0x0000821c, 0x00800000 }, /* ASP1TX2_INPUT4 */ + { 0x00008220, 0x00800000 }, /* ASP1TX3_INPUT1 */ + { 0x00008224, 0x00800000 }, /* ASP1TX3_INPUT2 */ + { 0x00008228, 0x00800000 }, /* ASP1TX3_INPUT3 */ + { 0x0000822c, 0x00800000 }, /* ASP1TX3_INPUT4 */ + { 0x00008230, 0x00800000 }, /* ASP1TX4_INPUT1 */ + { 0x00008234, 0x00800000 }, /* ASP1TX4_INPUT2 */ + { 0x00008238, 0x00800000 }, /* ASP1TX4_INPUT3 */ + { 0x0000823c, 0x00800000 }, /* ASP1TX4_INPUT4 */ + { 0x00008240, 0x00800000 }, /* ASP1TX5_INPUT1 */ + { 0x00008244, 0x00800000 }, /* ASP1TX5_INPUT2 */ + { 0x00008248, 0x00800000 }, /* ASP1TX5_INPUT3 */ + { 0x0000824c, 0x00800000 }, /* ASP1TX5_INPUT4 */ + { 0x00008250, 0x00800000 }, /* ASP1TX6_INPUT1 */ + { 0x00008254, 0x00800000 }, /* ASP1TX6_INPUT2 */ + { 0x00008258, 0x00800000 }, /* ASP1TX6_INPUT3 */ + { 0x0000825c, 0x00800000 }, /* ASP1TX6_INPUT4 */ + { 0x00008260, 0x00800000 }, /* ASP1TX7_INPUT1 */ + { 0x00008264, 0x00800000 }, /* ASP1TX7_INPUT2 */ + { 0x00008268, 0x00800000 }, /* ASP1TX7_INPUT3 */ + { 0x0000826c, 0x00800000 }, /* ASP1TX7_INPUT4 */ + { 0x00008270, 0x00800000 }, /* ASP1TX8_INPUT1 */ + { 0x00008274, 0x00800000 }, /* ASP1TX8_INPUT2 */ + { 0x00008278, 0x00800000 }, /* ASP1TX8_INPUT3 */ + { 0x0000827c, 0x00800000 }, /* ASP1TX8_INPUT4 */ + { 0x00008300, 0x00800000 }, /* ASP2TX1_INPUT1 */ + { 0x00008304, 0x00800000 }, /* ASP2TX1_INPUT2 */ + { 0x00008308, 0x00800000 }, /* ASP2TX1_INPUT3 */ + { 0x0000830c, 0x00800000 }, /* ASP2TX1_INPUT4 */ + { 0x00008310, 0x00800000 }, /* ASP2TX2_INPUT1 */ + { 0x00008314, 0x00800000 }, /* ASP2TX2_INPUT2 */ + { 0x00008318, 0x00800000 }, /* ASP2TX2_INPUT3 */ + { 0x0000831c, 0x00800000 }, /* ASP2TX2_INPUT4 */ + { 0x00008320, 0x00800000 }, /* ASP2TX3_INPUT1 */ + { 0x00008324, 0x00800000 }, /* ASP2TX3_INPUT2 */ + { 0x00008328, 0x00800000 }, /* ASP2TX3_INPUT3 */ + { 0x0000832c, 0x00800000 }, /* ASP2TX3_INPUT4 */ + { 0x00008330, 0x00800000 }, /* ASP2TX4_INPUT1 */ + { 0x00008334, 0x00800000 }, /* ASP2TX4_INPUT2 */ + { 0x00008338, 0x00800000 }, /* ASP2TX4_INPUT3 */ + { 0x0000833c, 0x00800000 }, /* ASP2TX4_INPUT4 */ + { 0x00008980, 0x00000000 }, /* ISRC1INT1_INPUT1 */ + { 0x00008990, 0x00000000 }, /* ISRC1INT2_INPUT1 */ + { 0x000089a0, 0x00000000 }, /* ISRC1INT3_INPUT1 */ + { 0x000089b0, 0x00000000 }, /* ISRC1INT4_INPUT1 */ + { 0x000089c0, 0x00000000 }, /* ISRC1DEC1_INPUT1 */ + { 0x000089d0, 0x00000000 }, /* ISRC1DEC2_INPUT1 */ + { 0x000089e0, 0x00000000 }, /* ISRC1DEC3_INPUT1 */ + { 0x000089f0, 0x00000000 }, /* ISRC1DEC4_INPUT1 */ + { 0x00008a00, 0x00000000 }, /* ISRC2INT1_INPUT1 */ + { 0x00008a10, 0x00000000 }, /* ISRC2INT2_INPUT1 */ + { 0x00008a40, 0x00000000 }, /* ISRC2DEC1_INPUT1 */ + { 0x00008a50, 0x00000000 }, /* ISRC2DEC2_INPUT1 */ + { 0x00008a80, 0x00000000 }, /* ISRC3INT1_INPUT1 */ + { 0x00008a90, 0x00000000 }, /* ISRC3INT2_INPUT1 */ + { 0x00008ac0, 0x00000000 }, /* ISRC3DEC1_INPUT1 */ + { 0x00008ad0, 0x00000000 }, /* ISRC3DEC2_INPUT1 */ + { 0x00008b80, 0x00800000 }, /* EQ1_INPUT1 */ + { 0x00008b84, 0x00800000 }, /* EQ1_INPUT2 */ + { 0x00008b88, 0x00800000 }, /* EQ1_INPUT3 */ + { 0x00008b8c, 0x00800000 }, /* EQ1_INPUT4 */ + { 0x00008b90, 0x00800000 }, /* EQ2_INPUT1 */ + { 0x00008b94, 0x00800000 }, /* EQ2_INPUT2 */ + { 0x00008b98, 0x00800000 }, /* EQ2_INPUT3 */ + { 0x00008b9c, 0x00800000 }, /* EQ2_INPUT4 */ + { 0x00008ba0, 0x00800000 }, /* EQ3_INPUT1 */ + { 0x00008ba4, 0x00800000 }, /* EQ3_INPUT2 */ + { 0x00008ba8, 0x00800000 }, /* EQ3_INPUT3 */ + { 0x00008bac, 0x00800000 }, /* EQ3_INPUT4 */ + { 0x00008bb0, 0x00800000 }, /* EQ4_INPUT1 */ + { 0x00008bb4, 0x00800000 }, /* EQ4_INPUT2 */ + { 0x00008bb8, 0x00800000 }, /* EQ4_INPUT3 */ + { 0x00008bbc, 0x00800000 }, /* EQ4_INPUT4 */ + { 0x00008c00, 0x00800000 }, /* DRC1L_INPUT1 */ + { 0x00008c04, 0x00800000 }, /* DRC1L_INPUT2 */ + { 0x00008c08, 0x00800000 }, /* DRC1L_INPUT3 */ + { 0x00008c0c, 0x00800000 }, /* DRC1L_INPUT4 */ + { 0x00008c10, 0x00800000 }, /* DRC1R_INPUT1 */ + { 0x00008c14, 0x00800000 }, /* DRC1R_INPUT2 */ + { 0x00008c18, 0x00800000 }, /* DRC1R_INPUT3 */ + { 0x00008c1c, 0x00800000 }, /* DRC1R_INPUT4 */ + { 0x00008c20, 0x00800000 }, /* DRC2L_INPUT1 */ + { 0x00008c24, 0x00800000 }, /* DRC2L_INPUT2 */ + { 0x00008c28, 0x00800000 }, /* DRC2L_INPUT3 */ + { 0x00008c2c, 0x00800000 }, /* DRC2L_INPUT4 */ + { 0x00008c30, 0x00800000 }, /* DRC2R_INPUT1 */ + { 0x00008c34, 0x00800000 }, /* DRC2R_INPUT2 */ + { 0x00008c38, 0x00800000 }, /* DRC2R_INPUT3 */ + { 0x00008c3c, 0x00800000 }, /* DRC2R_INPUT4 */ + { 0x00008c80, 0x00800000 }, /* LHPF1_INPUT1 */ + { 0x00008c84, 0x00800000 }, /* LHPF1_INPUT2 */ + { 0x00008c88, 0x00800000 }, /* LHPF1_INPUT3 */ + { 0x00008c8c, 0x00800000 }, /* LHPF1_INPUT4 */ + { 0x00008c90, 0x00800000 }, /* LHPF2_INPUT1 */ + { 0x00008c94, 0x00800000 }, /* LHPF2_INPUT2 */ + { 0x00008c98, 0x00800000 }, /* LHPF2_INPUT3 */ + { 0x00008c9c, 0x00800000 }, /* LHPF2_INPUT4 */ + { 0x00008ca0, 0x00800000 }, /* LHPF3_INPUT1 */ + { 0x00008ca4, 0x00800000 }, /* LHPF3_INPUT2 */ + { 0x00008ca8, 0x00800000 }, /* LHPF3_INPUT3 */ + { 0x00008cac, 0x00800000 }, /* LHPF3_INPUT4 */ + { 0x00008cb0, 0x00800000 }, /* LHPF4_INPUT1 */ + { 0x00008cb4, 0x00800000 }, /* LHPF4_INPUT2 */ + { 0x00008cb8, 0x00800000 }, /* LHPF4_INPUT3 */ + { 0x00008cbc, 0x00800000 }, /* LHPF4_INPUT4 */ + { 0x00009000, 0x00800000 }, /* DSP1RX1_INPUT1 */ + { 0x00009004, 0x00800000 }, /* DSP1RX1_INPUT2 */ + { 0x00009008, 0x00800000 }, /* DSP1RX1_INPUT3 */ + { 0x0000900c, 0x00800000 }, /* DSP1RX1_INPUT4 */ + { 0x00009010, 0x00800000 }, /* DSP1RX2_INPUT1 */ + { 0x00009014, 0x00800000 }, /* DSP1RX2_INPUT2 */ + { 0x00009018, 0x00800000 }, /* DSP1RX2_INPUT3 */ + { 0x0000901c, 0x00800000 }, /* DSP1RX2_INPUT4 */ + { 0x00009020, 0x00800000 }, /* DSP1RX3_INPUT1 */ + { 0x00009024, 0x00800000 }, /* DSP1RX3_INPUT2 */ + { 0x00009028, 0x00800000 }, /* DSP1RX3_INPUT3 */ + { 0x0000902c, 0x00800000 }, /* DSP1RX3_INPUT4 */ + { 0x00009030, 0x00800000 }, /* DSP1RX4_INPUT1 */ + { 0x00009034, 0x00800000 }, /* DSP1RX4_INPUT2 */ + { 0x00009038, 0x00800000 }, /* DSP1RX4_INPUT3 */ + { 0x0000903c, 0x00800000 }, /* DSP1RX4_INPUT4 */ + { 0x00009040, 0x00800000 }, /* DSP1RX5_INPUT1 */ + { 0x00009044, 0x00800000 }, /* DSP1RX5_INPUT2 */ + { 0x00009048, 0x00800000 }, /* DSP1RX5_INPUT3 */ + { 0x0000904c, 0x00800000 }, /* DSP1RX5_INPUT4 */ + { 0x00009050, 0x00800000 }, /* DSP1RX6_INPUT1 */ + { 0x00009054, 0x00800000 }, /* DSP1RX6_INPUT2 */ + { 0x00009058, 0x00800000 }, /* DSP1RX6_INPUT3 */ + { 0x0000905c, 0x00800000 }, /* DSP1RX6_INPUT4 */ + { 0x00009060, 0x00800000 }, /* DSP1RX7_INPUT1 */ + { 0x00009064, 0x00800000 }, /* DSP1RX7_INPUT2 */ + { 0x00009068, 0x00800000 }, /* DSP1RX7_INPUT3 */ + { 0x0000906c, 0x00800000 }, /* DSP1RX7_INPUT4 */ + { 0x00009070, 0x00800000 }, /* DSP1RX8_INPUT1 */ + { 0x00009074, 0x00800000 }, /* DSP1RX8_INPUT2 */ + { 0x00009078, 0x00800000 }, /* DSP1RX8_INPUT3 */ + { 0x0000907c, 0x00800000 }, /* DSP1RX8_INPUT4 */ + { 0x0000a400, 0x00000000 }, /* ISRC1_CONTROL1 */ + { 0x0000a404, 0x00000000 }, /* ISRC1_CONTROL2 */ + { 0x0000a510, 0x00000000 }, /* ISRC2_CONTROL1 */ + { 0x0000a514, 0x00000000 }, /* ISRC2_CONTROL2 */ + { 0x0000a620, 0x00000000 }, /* ISRC3_CONTROL1 */ + { 0x0000a624, 0x00000000 }, /* ISRC3_CONTROL2 */ + { 0x0000a800, 0x00000000 }, /* FX_SAMPLE_RATE */ + { 0x0000a808, 0x00000000 }, /* EQ_CONTROL1 */ + { 0x0000a80c, 0x00000000 }, /* EQ_CONTROL2 */ + { 0x0000a810, 0x0c0c0c0c }, /* EQ1_GAIN1 */ + { 0x0000a814, 0x0000000c }, /* EQ1_GAIN2 */ + { 0x0000a818, 0x03fe0fc8 }, /* EQ1_BAND1_COEFF1 */ + { 0x0000a81c, 0x00000b75 }, /* EQ1_BAND1_COEFF2 */ + { 0x0000a820, 0x000000e0 }, /* EQ1_BAND1_PG */ + { 0x0000a824, 0xf1361ec4 }, /* EQ1_BAND2_COEFF1 */ + { 0x0000a828, 0x00000409 }, /* EQ1_BAND2_COEFF2 */ + { 0x0000a82c, 0x000004cc }, /* EQ1_BAND2_PG */ + { 0x0000a830, 0xf3371c9b }, /* EQ1_BAND3_COEFF1 */ + { 0x0000a834, 0x0000040b }, /* EQ1_BAND3_COEFF2 */ + { 0x0000a838, 0x00000cbb }, /* EQ1_BAND3_PG */ + { 0x0000a83c, 0xf7d916f8 }, /* EQ1_BAND4_COEFF1 */ + { 0x0000a840, 0x0000040a }, /* EQ1_BAND4_COEFF2 */ + { 0x0000a844, 0x00001f14 }, /* EQ1_BAND4_PG */ + { 0x0000a848, 0x0563058c }, /* EQ1_BAND5_COEFF1 */ + { 0x0000a84c, 0x00000000 }, /* EQ1_BAND5_COEFF1 + 4 */ + { 0x0000a850, 0x00004000 }, /* EQ1_BAND5_PG */ + { 0x0000a854, 0x0c0c0c0c }, /* EQ2_GAIN1 */ + { 0x0000a858, 0x0000000c }, /* EQ2_GAIN2 */ + { 0x0000a85c, 0x03fe0fc8 }, /* EQ2_BAND1_COEFF1 */ + { 0x0000a860, 0x00000b75 }, /* EQ2_BAND1_COEFF2 */ + { 0x0000a864, 0x000000e0 }, /* EQ2_BAND1_PG */ + { 0x0000a868, 0xf1361ec4 }, /* EQ2_BAND2_COEFF1 */ + { 0x0000a86c, 0x00000409 }, /* EQ2_BAND2_COEFF2 */ + { 0x0000a870, 0x000004cc }, /* EQ2_BAND2_PG */ + { 0x0000a874, 0xf3371c9b }, /* EQ2_BAND3_COEFF1 */ + { 0x0000a878, 0x0000040b }, /* EQ2_BAND3_COEFF2 */ + { 0x0000a87c, 0x00000cbb }, /* EQ2_BAND3_PG */ + { 0x0000a880, 0xf7d916f8 }, /* EQ2_BAND4_COEFF1 */ + { 0x0000a884, 0x0000040a }, /* EQ2_BAND4_COEFF2 */ + { 0x0000a888, 0x00001f14 }, /* EQ2_BAND4_PG */ + { 0x0000a88c, 0x0563058c }, /* EQ2_BAND5_COEFF1 */ + { 0x0000a890, 0x00000000 }, /* EQ2_BAND5_COEFF1 + 4 */ + { 0x0000a894, 0x00004000 }, /* EQ2_BAND5_PG */ + { 0x0000a898, 0x0c0c0c0c }, /* EQ3_GAIN1 */ + { 0x0000a89c, 0x0000000c }, /* EQ3_GAIN2 */ + { 0x0000a8a0, 0x03fe0fc8 }, /* EQ3_BAND1_COEFF1 */ + { 0x0000a8a4, 0x00000b75 }, /* EQ3_BAND1_COEFF2 */ + { 0x0000a8a8, 0x000000e0 }, /* EQ3_BAND1_PG */ + { 0x0000a8ac, 0xf1361ec4 }, /* EQ3_BAND2_COEFF1 */ + { 0x0000a8b0, 0x00000409 }, /* EQ3_BAND2_COEFF2 */ + { 0x0000a8b4, 0x000004cc }, /* EQ3_BAND2_PG */ + { 0x0000a8b8, 0xf3371c9b }, /* EQ3_BAND3_COEFF1 */ + { 0x0000a8bc, 0x0000040b }, /* EQ3_BAND3_COEFF2 */ + { 0x0000a8c0, 0x00000cbb }, /* EQ3_BAND3_PG */ + { 0x0000a8c4, 0xf7d916f8 }, /* EQ3_BAND4_COEFF1 */ + { 0x0000a8c8, 0x0000040a }, /* EQ3_BAND4_COEFF2 */ + { 0x0000a8cc, 0x00001f14 }, /* EQ3_BAND4_PG */ + { 0x0000a8d0, 0x0563058c }, /* EQ3_BAND5_COEFF1 */ + { 0x0000a8d4, 0x00000000 }, /* EQ3_BAND5_COEFF1 + 4 */ + { 0x0000a8d8, 0x00004000 }, /* EQ3_BAND5_PG */ + { 0x0000a8dc, 0x0c0c0c0c }, /* EQ4_GAIN1 */ + { 0x0000a8e0, 0x0000000c }, /* EQ4_GAIN2 */ + { 0x0000a8e4, 0x03fe0fc8 }, /* EQ4_BAND1_COEFF1 */ + { 0x0000a8e8, 0x00000b75 }, /* EQ4_BAND1_COEFF2 */ + { 0x0000a8ec, 0x000000e0 }, /* EQ4_BAND1_PG */ + { 0x0000a8f0, 0xf1361ec4 }, /* EQ4_BAND2_COEFF1 */ + { 0x0000a8f4, 0x00000409 }, /* EQ4_BAND2_COEFF2 */ + { 0x0000a8f8, 0x000004cc }, /* EQ4_BAND2_PG */ + { 0x0000a8fc, 0xf3371c9b }, /* EQ4_BAND3_COEFF1 */ + { 0x0000a900, 0x0000040b }, /* EQ4_BAND3_COEFF2 */ + { 0x0000a904, 0x00000cbb }, /* EQ4_BAND3_PG */ + { 0x0000a908, 0xf7d916f8 }, /* EQ4_BAND4_COEFF1 */ + { 0x0000a90c, 0x0000040a }, /* EQ4_BAND4_COEFF2 */ + { 0x0000a910, 0x00001f14 }, /* EQ4_BAND4_PG */ + { 0x0000a914, 0x0563058c }, /* EQ4_BAND5_COEFF1 */ + { 0x0000a918, 0x00000000 }, /* EQ4_BAND5_COEFF1 + 4 */ + { 0x0000a91c, 0x00004000 }, /* EQ4_BAND5_PG */ + { 0x0000aa30, 0x00000000 }, /* LHPF_CONTROL1 */ + { 0x0000aa34, 0x00000000 }, /* LHPF_CONTROL2 */ + { 0x0000aa38, 0x00000000 }, /* LHPF1_COEFF */ + { 0x0000aa3c, 0x00000000 }, /* LHPF2_COEFF */ + { 0x0000aa40, 0x00000000 }, /* LHPF3_COEFF */ + { 0x0000aa44, 0x00000000 }, /* LHPF4_COEFF */ + { 0x0000ab00, 0x00000000 }, /* DRC1_CONTROL1 */ + { 0x0000ab04, 0x49130018 }, /* DRC1_CONTROL2 */ + { 0x0000ab08, 0x00000018 }, /* DRC1_CONTROL3 */ + { 0x0000ab0c, 0x00000000 }, /* DRC1_CONTROL4 */ + { 0x0000ab14, 0x00000000 }, /* DRC2_CONTROL1 */ + { 0x0000ab18, 0x49130018 }, /* DRC2_CONTROL2 */ + { 0x0000ab1c, 0x00000018 }, /* DRC2_CONTROL3 */ + { 0x0000ab20, 0x00000000 }, /* DRC2_CONTROL4 */ + { 0x0000b000, 0x00000000 }, /* TONE_GENERATOR1 */ + { 0x0000b004, 0x00100000 }, /* TONE_GENERATOR2 */ + { 0x0000b400, 0x00000000 }, /* COMFORT_NOISE_GENERATOR */ + { 0x0000b800, 0x00000000 }, /* US_CONTROL */ + { 0x0000b804, 0x00002020 }, /* US1_CONTROL */ + { 0x0000b808, 0x00000000 }, /* US1_DET_CONTROL */ + { 0x0000b814, 0x00002020 }, /* US2_CONTROL */ + { 0x0000b818, 0x00000000 }, /* US2_DET_CONTROL */ + { 0x00018110, 0xffffffff }, /* IRQ1_MASK_1 */ + { 0x00018114, 0xfffffff7 }, /* IRQ1_MASK_2 */ + { 0x00018118, 0xffffffff }, /* IRQ1_MASK_3 */ + { 0x0001811c, 0xffffffff }, /* IRQ1_MASK_4 */ + { 0x00018120, 0xffffffff }, /* IRQ1_MASK_5 */ + { 0x00018124, 0xffffffff }, /* IRQ1_MASK_6 */ + { 0x00018128, 0xffffffff }, /* IRQ1_MASK_7 */ + { 0x0001812c, 0xffffffff }, /* IRQ1_MASK_8 */ + { 0x00018130, 0xffffffff }, /* IRQ1_MASK_9 */ + { 0x00018134, 0xffffffff }, /* IRQ1_MASK_10 */ + { 0x00018138, 0xffffffff }, /* IRQ1_MASK_11 */ +}; + +static bool cs48l32_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS48L32_DEVID: + case CS48L32_REVID: + case CS48L32_OTPID: + case CS48L32_SFT_RESET: + case CS48L32_CTRL_IF_DEBUG3: + case CS48L32_MCU_CTRL1: + case CS48L32_GPIO1_CTRL1 ... CS48L32_GPIO16_CTRL1: + case CS48L32_OUTPUT_SYS_CLK: + case CS48L32_AUXPDM_CTRL: + case CS48L32_AUXPDM_CTRL2: + case CS48L32_CLOCK32K: + case CS48L32_SYSTEM_CLOCK1 ... CS48L32_SYSTEM_CLOCK2: + case CS48L32_SAMPLE_RATE1 ... CS48L32_SAMPLE_RATE4: + case CS48L32_FLL1_CONTROL1 ... CS48L32_FLL1_GPIO_CLOCK: + case CS48L32_CHARGE_PUMP1: + case CS48L32_LDO2_CTRL1: + case CS48L32_MICBIAS_CTRL1: + case CS48L32_MICBIAS_CTRL5: + case CS48L32_IRQ1_CTRL_AOD: + case CS48L32_INPUT_CONTROL: + case CS48L32_INPUT_STATUS: + case CS48L32_INPUT_RATE_CONTROL: + case CS48L32_INPUT_CONTROL2: + case CS48L32_INPUT_CONTROL3: + case CS48L32_INPUT1_CONTROL1: + case CS48L32_IN1L_CONTROL1 ... CS48L32_IN1L_CONTROL2: + case CS48L32_IN1R_CONTROL1 ... CS48L32_IN1R_CONTROL2: + case CS48L32_INPUT2_CONTROL1: + case CS48L32_IN2L_CONTROL1 ... CS48L32_IN2L_CONTROL2: + case CS48L32_IN2R_CONTROL1 ... CS48L32_IN2R_CONTROL2: + case CS48L32_INPUT_HPF_CONTROL: + case CS48L32_INPUT_VOL_CONTROL: + case CS48L32_AUXPDM_CONTROL1: + case CS48L32_AUXPDM_CONTROL2: + case CS48L32_AUXPDM1_CONTROL1: + case CS48L32_AUXPDM2_CONTROL1: + case CS48L32_ADC1L_ANA_CONTROL1: + case CS48L32_ADC1R_ANA_CONTROL1: + case CS48L32_ASP1_ENABLES1 ... CS48L32_ASP1_DATA_CONTROL5: + case CS48L32_ASP2_ENABLES1 ... CS48L32_ASP2_DATA_CONTROL5: + case CS48L32_ASP1TX1_INPUT1 ... CS48L32_ASP1TX8_INPUT4: + case CS48L32_ASP2TX1_INPUT1 ... CS48L32_ASP2TX4_INPUT4: + case CS48L32_ISRC1INT1_INPUT1 ... CS48L32_ISRC1DEC4_INPUT1: + case CS48L32_ISRC2INT1_INPUT1 ... CS48L32_ISRC2DEC2_INPUT1: + case CS48L32_ISRC3INT1_INPUT1 ... CS48L32_ISRC3DEC2_INPUT1: + case CS48L32_EQ1_INPUT1 ... CS48L32_EQ4_INPUT4: + case CS48L32_DRC1L_INPUT1 ... CS48L32_DRC1R_INPUT4: + case CS48L32_DRC2L_INPUT1 ... CS48L32_DRC2R_INPUT4: + case CS48L32_LHPF1_INPUT1 ... CS48L32_LHPF1_INPUT4: + case CS48L32_LHPF2_INPUT1 ... CS48L32_LHPF2_INPUT4: + case CS48L32_LHPF3_INPUT1 ... CS48L32_LHPF3_INPUT4: + case CS48L32_LHPF4_INPUT1 ... CS48L32_LHPF4_INPUT4: + case CS48L32_DSP1RX1_INPUT1 ... CS48L32_DSP1RX8_INPUT4: + case CS48L32_ISRC1_CONTROL1 ... CS48L32_ISRC1_CONTROL2: + case CS48L32_ISRC2_CONTROL1 ... CS48L32_ISRC2_CONTROL2: + case CS48L32_ISRC3_CONTROL1 ... CS48L32_ISRC3_CONTROL2: + case CS48L32_FX_SAMPLE_RATE: + case CS48L32_EQ_CONTROL1 ... CS48L32_EQ_CONTROL2: + case CS48L32_EQ1_GAIN1 ... CS48L32_EQ1_BAND5_PG: + case CS48L32_EQ2_GAIN1 ... CS48L32_EQ2_BAND5_PG: + case CS48L32_EQ3_GAIN1 ... CS48L32_EQ3_BAND5_PG: + case CS48L32_EQ4_GAIN1 ... CS48L32_EQ4_BAND5_PG: + case CS48L32_LHPF_CONTROL1 ... CS48L32_LHPF_CONTROL2: + case CS48L32_LHPF1_COEFF ... CS48L32_LHPF4_COEFF: + case CS48L32_DRC1_CONTROL1 ... CS48L32_DRC1_CONTROL4: + case CS48L32_DRC2_CONTROL1 ... CS48L32_DRC2_CONTROL4: + case CS48L32_TONE_GENERATOR1 ... CS48L32_TONE_GENERATOR2: + case CS48L32_COMFORT_NOISE_GENERATOR: + case CS48L32_US_CONTROL: + case CS48L32_US1_CONTROL: + case CS48L32_US1_DET_CONTROL: + case CS48L32_US2_CONTROL: + case CS48L32_US2_DET_CONTROL: + case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24: + case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8: + case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7: + case CS48L32_IRQ1_STATUS: + case CS48L32_IRQ1_EINT_1 ... CS48L32_IRQ1_EINT_11: + case CS48L32_IRQ1_STS_1 ... CS48L32_IRQ1_STS_11: + case CS48L32_IRQ1_MASK_1 ... CS48L32_IRQ1_MASK_11: + case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_147455: + case CS48L32_DSP1_SYS_INFO_ID ... CS48L32_DSP1_AHBM_WINDOW_DEBUG_1: + case CS48L32_DSP1_XMEM_UNPACKED24_0 ... CS48L32_DSP1_XMEM_UNPACKED24_196607: + case CS48L32_DSP1_CLOCK_FREQ ... CS48L32_DSP1_SAMPLE_RATE_TX8: + case CS48L32_DSP1_SCRATCH1 ... CS48L32_DSP1_SCRATCH4: + case CS48L32_DSP1_CCM_CORE_CONTROL ... CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1: + case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_49151: + case CS48L32_DSP1_YMEM_UNPACKED24_0 ... CS48L32_DSP1_YMEM_UNPACKED24_65535: + case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_71679: + return true; + default: + return false; + } +} + +static bool cs48l32_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS48L32_DEVID: + case CS48L32_REVID: + case CS48L32_OTPID: + case CS48L32_SFT_RESET: + case CS48L32_CTRL_IF_DEBUG3: + case CS48L32_MCU_CTRL1: + case CS48L32_SYSTEM_CLOCK2: + case CS48L32_FLL1_CONTROL5: + case CS48L32_FLL1_CONTROL6: + case CS48L32_INPUT_STATUS: + case CS48L32_INPUT_CONTROL3: + case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24: + case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8: + case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7: + case CS48L32_IRQ1_STATUS: + case CS48L32_IRQ1_EINT_1 ... CS48L32_IRQ1_EINT_11: + case CS48L32_IRQ1_STS_1 ... CS48L32_IRQ1_STS_11: + case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_147455: + case CS48L32_DSP1_SYS_INFO_ID ... CS48L32_DSP1_AHBM_WINDOW_DEBUG_1: + case CS48L32_DSP1_XMEM_UNPACKED24_0 ... CS48L32_DSP1_XMEM_UNPACKED24_196607: + case CS48L32_DSP1_CLOCK_FREQ ... CS48L32_DSP1_SAMPLE_RATE_TX8: + case CS48L32_DSP1_SCRATCH1 ... CS48L32_DSP1_SCRATCH4: + case CS48L32_DSP1_CCM_CORE_CONTROL ... CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1: + case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_49151: + case CS48L32_DSP1_YMEM_UNPACKED24_0 ... CS48L32_DSP1_YMEM_UNPACKED24_65535: + case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_71679: + return true; + default: + return false; + } +} + +/* + * The bus bridge requires DSP packed memory registers to be accessed in + * aligned block multiples. + * Mark precious to prevent regmap debugfs causing an illegal bus transaction. + */ +static bool cs48l32_precious_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_147455: + case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_49151: + case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_71679: + return true; + default: + return false; + } +} + +static const struct regmap_config cs48l32_spi_regmap = { + .name = "cs48l32", + .reg_bits = 32, + .reg_stride = 4, + .pad_bits = 32, + .val_bits = 32, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .val_format_endian = REGMAP_ENDIAN_BIG, + + .max_register = CS48L32_DSP1_PMEM_71679, + .readable_reg = &cs48l32_readable_register, + .volatile_reg = &cs48l32_volatile_register, + .precious_reg = &cs48l32_precious_register, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = cs48l32_reg_default, + .num_reg_defaults = ARRAY_SIZE(cs48l32_reg_default), +}; + +int cs48l32_init_regmap(struct spi_device *spi, struct cs48l32_mfd *cs48l32) +{ + cs48l32->regmap = devm_regmap_init_spi(spi, &cs48l32_spi_regmap); + if (IS_ERR(cs48l32->regmap)) + return PTR_ERR(cs48l32->regmap); + + return 0; +} diff --git a/drivers/mfd/cs48l32.c b/drivers/mfd/cs48l32.c new file mode 100644 index 000000000000..9506a1e0560b --- /dev/null +++ b/drivers/mfd/cs48l32.c @@ -0,0 +1,434 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MFD for Cirrus Logic CS48L32 audio codec. + * + * Copyright (C) 2016-2018, 2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/gpio/consumer.h> +#include <linux/mfd/core.h> +#include <linux/mfd/cs48l32/core.h> +#include <linux/mfd/cs48l32/registers.h> +#include <linux/module.h> +#include <linux/notifier.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/consumer.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/property.h> +#include <linux/regmap.h> +#include <linux/regulator/consumer.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/of_regulator.h> +#include <linux/spi/spi.h> + +#include "cs48l32.h" + +static const char * const cs48l32_core_supplies[] = { + "VDD_A", + "VDD_IO", +}; + +static const char * const cs48l32_supplies[] = { + "VOUT_MIC", + "VDD_CP", +}; + +static const struct mfd_cell cs48l32_devs[] = { + { .name = "cs48l32-pinctrl", }, + { .name = "cs48l32-irq", }, + { .name = "cs48l32-micsupp", }, + { + .name = "cs48l32-codec", + .parent_supplies = cs48l32_supplies, + .num_parent_supplies = ARRAY_SIZE(cs48l32_supplies), + }, +}; + +static int cs48l32_wait_for_boot(struct cs48l32_mfd *cs48l32) +{ + unsigned int val; + int i, ret; + + /* regmap_read_poll_timeout would fail on read errors so roll our own */ + for (i = 0; i < CS48L32_BOOT_TIMEOUT_MS; ++i) { + val = 0; + regmap_read(cs48l32->regmap, CS48L32_IRQ1_EINT_2, &val); + if (val & CS48L32_BOOT_DONE_EINT1_MASK) + break; + + usleep_range(1000, 2000); + } + if (i == CS48L32_BOOT_TIMEOUT_MS) { + dev_err(cs48l32->dev, "BOOT_DONE timed out\n"); + return -ETIMEDOUT; + } + + ret = regmap_read(cs48l32->regmap, CS48L32_MCU_CTRL1, &val); + if (ret) { + dev_err(cs48l32->dev, "Failed to read MCU_CTRL1: %d\n", ret); + return ret; + } + + if (val & BIT(CS48L32_MCU_STS_SHIFT)) { + dev_err(cs48l32->dev, "MCU boot failed\n"); + return -EIO; + } + + ret = regmap_set_bits(cs48l32->regmap, CS48L32_CTRL_IF_DEBUG3, CS48L32_SEEN_BOOT_DONE); + if (ret) { + dev_err(cs48l32->dev, "Failed to write CTRL_IF_DEBUG3: %d\n", ret); + return ret; + } + + pm_runtime_mark_last_busy(cs48l32->dev); + + return 0; +} + +static int cs48l32_soft_reset(struct cs48l32_mfd *cs48l32) +{ + int ret; + + ret = regmap_write(cs48l32->regmap, CS48L32_SFT_RESET, CS48L32_SFT_RESET_MAGIC); + if (ret != 0) { + dev_err(cs48l32->dev, "Failed to write soft reset: %d\n", ret); + return ret; + } + + usleep_range(2000, 3000); + + return 0; +} + +static void cs48l32_enable_hard_reset(struct cs48l32_mfd *cs48l32) +{ + if (cs48l32->reset_gpio) + gpiod_set_value_cansleep(cs48l32->reset_gpio, 0); +} + +static void cs48l32_disable_hard_reset(struct cs48l32_mfd *cs48l32) +{ + if (cs48l32->reset_gpio) { + gpiod_set_value_cansleep(cs48l32->reset_gpio, 1); + usleep_range(2000, 3000); + } +} + +static int __maybe_unused cs48l32_runtime_resume(struct device *dev) +{ + struct cs48l32_mfd *cs48l32 = dev_get_drvdata(dev); + unsigned int val; + int ret; + + dev_dbg(cs48l32->dev, "Leaving sleep mode\n"); + + ret = regulator_enable(cs48l32->vdd_d); + if (ret) { + dev_err(cs48l32->dev, "Failed to enable VDD_D: %d\n", ret); + return ret; + } + + usleep_range(2000, 3000); + + regcache_cache_only(cs48l32->regmap, false); + + /* Did it power down during suspend? */ + ret = regmap_read(cs48l32->regmap, CS48L32_CTRL_IF_DEBUG3, &val); + if ((ret == 0) && (val & CS48L32_SEEN_BOOT_DONE)) { + dev_dbg(cs48l32->dev, "VDD_D didn't power off during suspend\n"); + } else { + ret = cs48l32_wait_for_boot(cs48l32); + if (ret) + goto err; + + /* Flag that the registers have reset to defaults */ + regcache_mark_dirty(cs48l32->regmap); + } + + ret = regcache_sync(cs48l32->regmap); + if (ret) { + dev_err(cs48l32->dev, "Failed to restore register cache\n"); + goto err; + } + + return 0; + +err: + regcache_cache_only(cs48l32->regmap, true); + regulator_disable(cs48l32->vdd_d); + return ret; +} + +static int __maybe_unused cs48l32_runtime_suspend(struct device *dev) +{ + struct cs48l32_mfd *cs48l32 = dev_get_drvdata(dev); + + dev_dbg(cs48l32->dev, "Entering sleep mode\n"); + + regcache_cache_only(cs48l32->regmap, true); + regulator_disable(cs48l32->vdd_d); + + return 0; +} + +static const struct dev_pm_ops cs48l32_pm_ops = { + SET_RUNTIME_PM_OPS(cs48l32_runtime_suspend, cs48l32_runtime_resume, NULL) +}; + +static const struct __maybe_unused of_device_id cs48l32_of_match[] = { + { .compatible = "cirrus,cs48l31", }, + { .compatible = "cirrus,cs48l32", }, + { .compatible = "cirrus,cs48l33", }, + {}, +}; + +static int cs48l32_configure_clk32k(struct cs48l32_mfd *cs48l32) +{ + int ret = 0; + + ret = clk_prepare_enable(cs48l32->mclk1); + if (ret) { + dev_err(cs48l32->dev, "Failed to enable 32k clock: %d\n", ret); + return ret; + } + + ret = regmap_update_bits(cs48l32->regmap, CS48L32_CLOCK32K, + CS48L32_CLK_32K_EN_MASK | CS48L32_CLK_32K_SRC_MASK, + CS48L32_CLK_32K_EN_MASK | CS48L32_32K_MCLK1); + if (ret) { + dev_err(cs48l32->dev, "Failed to init 32k clock: %d\n", ret); + clk_disable_unprepare(cs48l32->mclk1); + return ret; + } + + return 0; +} + +static int cs48l32_get_clocks(struct cs48l32_mfd *cs48l32) +{ + cs48l32->mclk1 = devm_clk_get_optional(cs48l32->dev, "mclk1"); + if (IS_ERR(cs48l32->mclk1)) + return dev_err_probe(cs48l32->dev, PTR_ERR(cs48l32->mclk1), + "Failed to get mclk1\n"); + + return 0; +} + +static int cs48l32_get_reset_gpio(struct cs48l32_mfd *cs48l32) +{ + struct gpio_desc *reset; + + reset = devm_gpiod_get_optional(cs48l32->dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(reset)) + return dev_err_probe(cs48l32->dev, PTR_ERR(reset), "Failed to request /RESET\n"); + + /* + * A hard reset is needed for full reset of the chip. We allow running + * without hard reset only because it can be useful for early + * prototyping and some debugging, but we need to warn it's not ideal. + */ + if (!reset) + dev_warn(cs48l32->dev, "Running without reset GPIO is not recommended\n"); + + cs48l32->reset_gpio = reset; + + return 0; +} + +static int cs48l32_spi_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct cs48l32_mfd *cs48l32; + unsigned int hwid, rev, otp_rev; + int i, ret; + + cs48l32 = devm_kzalloc(&spi->dev, sizeof(*cs48l32), GFP_KERNEL); + if (!cs48l32) + return -ENOMEM; + + ret = cs48l32_init_regmap(spi, cs48l32); + if (ret) + return dev_err_probe(&spi->dev, ret, "Failed to allocate regmap\n"); + + cs48l32->dev = dev; + cs48l32->irq = spi->irq; + + dev_set_drvdata(cs48l32->dev, cs48l32); + + BLOCKING_INIT_NOTIFIER_HEAD(&cs48l32->notifier); + + regcache_cache_only(cs48l32->regmap, true); + + ret = cs48l32_get_reset_gpio(cs48l32); + if (ret) + return ret; + + ret = cs48l32_get_clocks(cs48l32); + if (ret) + return ret; + + for (i = 0; i < ARRAY_SIZE(cs48l32_core_supplies); i++) + cs48l32->core_supplies[i].supply = cs48l32_core_supplies[i]; + + cs48l32->num_core_supplies = ARRAY_SIZE(cs48l32_core_supplies); + + ret = devm_regulator_bulk_get(dev, cs48l32->num_core_supplies, cs48l32->core_supplies); + if (ret) + return dev_err_probe(dev, ret, "Failed to request core supplies\n"); + + cs48l32->vdd_d = devm_regulator_get(cs48l32->dev, "VDD_D"); + if (IS_ERR(cs48l32->vdd_d)) + return dev_err_probe(dev, PTR_ERR(cs48l32->vdd_d), "Failed to request VDD_D\n"); + + ret = regulator_set_voltage(cs48l32->vdd_d, 1200000, 1200000); + if (ret) + return dev_err_probe(dev, ret, "Failed to request VDD_D=1.2v\n"); + + ret = regulator_bulk_enable(cs48l32->num_core_supplies, cs48l32->core_supplies); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable core supplies\n"); + + ret = regulator_enable(cs48l32->vdd_d); + if (ret) { + dev_err(dev, "Failed to enable VDD_D: %d\n", ret); + goto err_enable; + } + + cs48l32_disable_hard_reset(cs48l32); + + regcache_cache_only(cs48l32->regmap, false); + + /* If we don't have a reset GPIO use a soft reset */ + if (!cs48l32->reset_gpio) { + ret = cs48l32_soft_reset(cs48l32); + if (ret) + goto err_reset; + } + + ret = cs48l32_wait_for_boot(cs48l32); + if (ret) { + dev_err(cs48l32->dev, "Device failed initial boot: %d\n", ret); + goto err_reset; + } + + ret = regmap_read(cs48l32->regmap, CS48L32_DEVID, &hwid); + if (ret) { + dev_err(dev, "Failed to read ID register: %d\n", ret); + goto err_reset; + } + hwid &= CS48L32_DEVID_MASK; + + switch (hwid) { + case CS48L31_SILICON_ID: + case CS48L32_SILICON_ID: + case CS48L33_SILICON_ID: + break; + default: + dev_err(cs48l32->dev, "Unknown device ID: %x\n", hwid); + ret = -EINVAL; + goto err_reset; + } + + ret = regmap_read(cs48l32->regmap, CS48L32_REVID, &rev); + if (ret) { + dev_err(dev, "Failed to read revision register: %d\n", ret); + goto err_reset; + } + rev &= CS48L32_AREVID_MASK | CS48L32_MTLREVID_MASK; + + ret = regmap_read(cs48l32->regmap, CS48L32_OTPID, &otp_rev); + if (ret) { + dev_err(dev, "Failed to read OTP revision register: %d\n", ret); + goto err_reset; + } + otp_rev &= CS48L32_OTPID_MASK; + + cs48l32->part = hwid & 0xff; + + dev_info(dev, "CS48L%x revision %X%u.%u\n", cs48l32->part, + rev >> CS48L32_AREVID_SHIFT, rev & CS48L32_MTLREVID_MASK, otp_rev); + + /* Apply hardware patch */ + ret = cs48l32_patch(cs48l32); + if (ret) { + dev_err(cs48l32->dev, "Failed to apply patch %d\n", ret); + goto err_reset; + } + + ret = cs48l32_configure_clk32k(cs48l32); + if (ret) + goto err_reset; + + pm_runtime_set_active(cs48l32->dev); + pm_runtime_enable(cs48l32->dev); + pm_runtime_set_autosuspend_delay(cs48l32->dev, 100); + pm_runtime_use_autosuspend(cs48l32->dev); + + ret = mfd_add_devices(cs48l32->dev, PLATFORM_DEVID_NONE, + cs48l32_devs, ARRAY_SIZE(cs48l32_devs), NULL, 0, NULL); + if (ret) { + dev_err(cs48l32->dev, "Failed to add subdevices: %d\n", ret); + goto err_clk32k; + } + + return 0; + +err_clk32k: + clk_disable_unprepare(cs48l32->mclk1); +err_reset: + cs48l32_enable_hard_reset(cs48l32); + regulator_disable(cs48l32->vdd_d); +err_enable: + regulator_bulk_disable(cs48l32->num_core_supplies, cs48l32->core_supplies); + + return ret; +} + +static void cs48l32_spi_remove(struct spi_device *spi) +{ + struct cs48l32_mfd *cs48l32 = spi_get_drvdata(spi); + + /* Prevent any IRQs being serviced while we clean up */ + disable_irq(cs48l32->irq); + + mfd_remove_devices(cs48l32->dev); + + pm_runtime_disable(cs48l32->dev); + regulator_disable(cs48l32->vdd_d); + clk_disable_unprepare(cs48l32->mclk1); + cs48l32_enable_hard_reset(cs48l32); + regulator_bulk_disable(cs48l32->num_core_supplies, cs48l32->core_supplies); +} + +static const struct spi_device_id cs48l32_spi_ids[] = { + { "cs48l31", }, + { "cs48l32", }, + { "cs48l33", }, + { }, +}; +MODULE_DEVICE_TABLE(spi, cs48l32_spi_ids); + +static struct spi_driver cs48l32_spi_driver = { + .driver = { + .name = "cs48l32", + .owner = THIS_MODULE, + .pm = &cs48l32_pm_ops, + .of_match_table = of_match_ptr(cs48l32_of_match), + }, + .probe = &cs48l32_spi_probe, + .remove = &cs48l32_spi_remove, + .id_table = cs48l32_spi_ids, +}; + +module_spi_driver(cs48l32_spi_driver); + +MODULE_SOFTDEP("pre: pinctrl-cs48l32 irq-cirrus-cs48l32"); +MODULE_DESCRIPTION("CS48L32 MFD driver"); +MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/cs48l32.h b/drivers/mfd/cs48l32.h new file mode 100644 index 000000000000..36020c0cd686 --- /dev/null +++ b/drivers/mfd/cs48l32.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * MFD for Cirrus Logic CS48L32 audio codec. + * + * Copyright (C) 2016-2018, 2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef CS48L32_MFD_H +#define CS48L32_MFD_H + +#include <linux/bits.h> + +#define CS48L31_SILICON_ID 0x48a31 +#define CS48L32_SILICON_ID 0x48a32 +#define CS48L33_SILICON_ID 0x48a33 + +#define CS48L32_32K_MCLK1 0 + +#define CS48L32_SFT_RESET_MAGIC 0x5a000000 +#define CS48L32_SEEN_BOOT_DONE BIT(0) + +#define CS48L32_BOOT_TIMEOUT_MS 25 + +int cs48l32_init_regmap(struct spi_device *spi, struct cs48l32_mfd *cs48l32); +int cs48l32_patch(struct cs48l32_mfd *cs48l32); + +#endif diff --git a/include/linux/mfd/cs48l32/core.h b/include/linux/mfd/cs48l32/core.h new file mode 100644 index 000000000000..1c4269d70c8c --- /dev/null +++ b/include/linux/mfd/cs48l32/core.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * MFD for Cirrus Logic CS48L32 audio codec. + * + * Copyright (C) 2016-2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef CS48L32_CORE_H +#define CS48L32_CORE_H + +#include <linux/clk.h> +#include <linux/gpio/consumer.h> +#include <linux/interrupt.h> +#include <linux/notifier.h> +#include <linux/regmap.h> +#include <linux/regulator/consumer.h> + +#define CS48L32_MAX_CORE_SUPPLIES 2 + +struct snd_soc_dapm_context; + +struct cs48l32_mfd { + struct regmap *regmap; + struct device *dev; + struct gpio_desc *reset_gpio; + struct clk *mclk1; + struct snd_soc_dapm_context *dapm; + + int num_core_supplies; + struct regulator_bulk_data core_supplies[CS48L32_MAX_CORE_SUPPLIES]; + struct regulator *vdd_d; + + struct device *irq_dev; + struct regmap_irq_chip_data *irq_data; + int irq; + + u8 part; + + struct blocking_notifier_head notifier; +}; + +static inline int cs48l32_call_notifiers(struct cs48l32_mfd *mfd, + unsigned long event, + void *data) +{ + return blocking_notifier_call_chain(&mfd->notifier, event, data); +} +#endif -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* Re: [PATCH 03/12] mfd: cs48l32: Add support for CS48L31/32/33 codecs 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-11 23:07 ` kernel test robot -1 siblings, 0 replies; 98+ messages in thread From: kernel test robot @ 2022-11-11 23:07 UTC (permalink / raw) To: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: llvm, oe-kbuild-all, devicetree, alsa-devel, patches, linux-kernel, linux-gpio, Richard Fitzgerald [-- Attachment #1: Type: text/plain, Size: 2953 bytes --] Hi Richard, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on broonie-sound/for-next] [also build test WARNING on lee-mfd/for-mfd-next linusw-pinctrl/devel linusw-pinctrl/for-next broonie-regulator/for-next linus/master v6.1-rc4 next-20221111] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Richard-Fitzgerald/Add-support-for-the-Cirrus-Logic-CS48L32-audio-codecs/20221110-005630 base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next patch link: https://lore.kernel.org/r/20221109165331.29332-4-rf%40opensource.cirrus.com patch subject: [PATCH 03/12] mfd: cs48l32: Add support for CS48L31/32/33 codecs config: arm-randconfig-c002-20221111 compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 463da45892e2d2a262277b91b96f5f8c05dc25d0) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm cross compiling tool for clang build # apt-get install binutils-arm-linux-gnueabi # https://github.com/intel-lab-lkp/linux/commit/e5417b42692fa57b7987ecb90833e01e67186d0e git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Richard-Fitzgerald/Add-support-for-the-Cirrus-Logic-CS48L32-audio-codecs/20221110-005630 git checkout e5417b42692fa57b7987ecb90833e01e67186d0e # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/mfd/ If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot <lkp@intel.com> All warnings (new ones prefixed by >>): >> drivers/mfd/cs48l32.c:184:21: warning: attribute declaration must precede definition [-Wignored-attributes] static const struct __maybe_unused of_device_id cs48l32_of_match[] = { ^ include/linux/compiler_attributes.h:326:56: note: expanded from macro '__maybe_unused' #define __maybe_unused __attribute__((__unused__)) ^ include/linux/mod_devicetable.h:268:8: note: previous definition is here struct of_device_id { ^ 1 warning generated. vim +184 drivers/mfd/cs48l32.c 183 > 184 static const struct __maybe_unused of_device_id cs48l32_of_match[] = { 185 { .compatible = "cirrus,cs48l31", }, 186 { .compatible = "cirrus,cs48l32", }, 187 { .compatible = "cirrus,cs48l33", }, 188 {}, 189 }; 190 -- 0-DAY CI Kernel Test Service https://01.org/lkp [-- Attachment #2: config --] [-- Type: text/plain, Size: 144279 bytes --] # # Automatically generated file; DO NOT EDIT. # Linux/arm 6.1.0-rc1 Kernel Configuration # CONFIG_CC_VERSION_TEXT="clang version 16.0.0 (git://gitmirror/llvm_project 463da45892e2d2a262277b91b96f5f8c05dc25d0)" CONFIG_GCC_VERSION=0 CONFIG_CC_IS_CLANG=y CONFIG_CLANG_VERSION=160000 CONFIG_AS_IS_LLVM=y CONFIG_AS_VERSION=160000 CONFIG_LD_VERSION=0 CONFIG_LD_IS_LLD=y CONFIG_LLD_VERSION=160000 CONFIG_RUST_IS_AVAILABLE=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_TOOLS_SUPPORT_RELR=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=123 CONFIG_IRQ_WORK=y CONFIG_THREAD_INFO_IN_TASK=y # # General setup # CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_COMPILE_TEST=y # CONFIG_WERROR is not set CONFIG_LOCALVERSION="" CONFIG_BUILD_SALT="" CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_XZ=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_HAVE_KERNEL_LZ4=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_LZMA is not set # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set CONFIG_WATCH_QUEUE=y CONFIG_USELIB=y # CONFIG_AUDIT is not set CONFIG_HAVE_ARCH_AUDITSYSCALL=y # # IRQ subsystem # CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y CONFIG_GENERIC_IRQ_INJECTION=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_CHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_SIM=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y CONFIG_GENERIC_IRQ_DEBUGFS=y # end of IRQ subsystem CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_TIME_KUNIT_TEST=m CONFIG_CONTEXT_TRACKING=y CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem # CONFIG_TICK_ONESHOT=y CONFIG_HZ_PERIODIC=y # CONFIG_NO_HZ_IDLE is not set # CONFIG_NO_HZ is not set CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem CONFIG_BPF=y CONFIG_HAVE_EBPF_JIT=y # # BPF subsystem # CONFIG_BPF_SYSCALL=y # CONFIG_BPF_JIT is not set # CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set # end of BPF subsystem CONFIG_PREEMPT_BUILD=y # CONFIG_PREEMPT_NONE is not set # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y CONFIG_PREEMPT_COUNT=y CONFIG_PREEMPTION=y # # CPU/Task time and stats accounting # CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_PSI=y CONFIG_PSI_DEFAULT_DISABLED=y # end of CPU/Task time and stats accounting CONFIG_CPU_ISOLATION=y # # RCU Subsystem # CONFIG_TREE_RCU=y CONFIG_PREEMPT_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU_GENERIC=y CONFIG_TASKS_RCU=y CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y # end of RCU Subsystem CONFIG_IKCONFIG=y CONFIG_IKHEADERS=m CONFIG_GENERIC_SCHED_CLOCK=y # # Scheduler features # # end of Scheduler features CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough" CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_CGROUPS=y # CONFIG_CGROUP_FAVOR_DYNMODS is not set # CONFIG_MEMCG is not set CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y # CONFIG_CFS_BANDWIDTH is not set # CONFIG_RT_GROUP_SCHED is not set CONFIG_CGROUP_PIDS=y # CONFIG_CGROUP_RDMA is not set # CONFIG_CGROUP_FREEZER is not set CONFIG_CGROUP_DEVICE=y # CONFIG_CGROUP_CPUACCT is not set # CONFIG_CGROUP_PERF is not set CONFIG_CGROUP_BPF=y CONFIG_CGROUP_MISC=y CONFIG_CGROUP_DEBUG=y CONFIG_SOCK_CGROUP_DATA=y CONFIG_SCHED_AUTOGROUP=y # CONFIG_SYSFS_DEPRECATED is not set CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" # CONFIG_RD_GZIP is not set CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y CONFIG_RD_XZ=y CONFIG_RD_LZO=y # CONFIG_RD_LZ4 is not set # CONFIG_RD_ZSTD is not set # CONFIG_BOOT_CONFIG is not set CONFIG_INITRAMFS_PRESERVE_MTIME=y # CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_LD_ORPHAN_WARN=y CONFIG_HAVE_UID16=y CONFIG_EXPERT=y # CONFIG_MULTIUSER is not set CONFIG_SGETMASK_SYSCALL=y CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y # CONFIG_PRINTK is not set CONFIG_BUG=y # CONFIG_ELF_CORE is not set # CONFIG_BASE_FULL is not set CONFIG_FUTEX=y CONFIG_FUTEX_PI=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y # CONFIG_TIMERFD is not set CONFIG_EVENTFD=y # CONFIG_AIO is not set CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y # CONFIG_MEMBARRIER is not set CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y # CONFIG_KCMP is not set # CONFIG_RSEQ is not set CONFIG_EMBEDDED=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_PERF_USE_VMALLOC=y # CONFIG_PC104 is not set # # Kernel Performance Events And Counters # CONFIG_PERF_EVENTS=y # CONFIG_DEBUG_PERF_USE_VMALLOC is not set # end of Kernel Performance Events And Counters CONFIG_SYSTEM_DATA_VERIFICATION=y CONFIG_PROFILING=y # end of General setup CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_NO_IOPORT_MAP=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_PHYS_OFFSET=0x00800000 CONFIG_GENERIC_BUG=y CONFIG_PGTABLE_LEVELS=2 # # System Type # # CONFIG_MMU is not set CONFIG_ARM_SINGLE_ARMV7M=y CONFIG_ARCH_MMAP_RND_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=16 CONFIG_ARCH_AT91=y CONFIG_SOC_SAMV7=y # # Clocksource driver selection # # CONFIG_ATMEL_CLOCKSOURCE_TCB is not set CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y CONFIG_COMMON_CLK_AT91=y CONFIG_ARCH_MXC=y # # Cortex-A/Cortex-M asymmetric multiprocessing platforms # CONFIG_SOC_IMX7D_CM4=y CONFIG_SOC_IMX7D=y CONFIG_SOC_IMX7ULP=y CONFIG_SOC_IMXRT=y # CONFIG_SOC_VF610 is not set # CONFIG_ARCH_STM32 is not set # CONFIG_ARCH_LPC18XX is not set # CONFIG_ARCH_MPS2 is not set # # Processor Type # CONFIG_CPU_V7M=y CONFIG_CPU_THUMBONLY=y CONFIG_CPU_THUMB_CAPABLE=y CONFIG_CPU_32v7M=y CONFIG_CPU_ABRT_NOMMU=y CONFIG_CPU_PABRT_LEGACY=y CONFIG_CPU_CACHE_NOP=y CONFIG_CPU_CACHE_V7M=y CONFIG_CPU_V7M_NUM_IRQ=240 # # Processor Features # CONFIG_ARM_THUMB=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_ICACHE_DISABLE=y CONFIG_CPU_DCACHE_DISABLE=y CONFIG_CPU_BPREDICT_DISABLE=y CONFIG_ARM_L1_CACHE_SHIFT=5 # CONFIG_ARM_DMA_MEM_BUFFERABLE is not set # CONFIG_SET_MEM_PARAM is not set CONFIG_DRAM_BASE=0x00800000 CONFIG_DRAM_SIZE=0x00800000 # CONFIG_REMAP_VECTORS_TO_RAM is not set # CONFIG_ARM_MPU is not set # end of System Type # # Bus support # # end of Bus support # # Kernel Features # CONFIG_IRQSTACKS=y CONFIG_PAGE_OFFSET=0x00800000 CONFIG_ARCH_NR_GPIO=0 CONFIG_HZ_FIXED=0 # CONFIG_HZ_100 is not set # CONFIG_HZ_200 is not set # CONFIG_HZ_250 is not set # CONFIG_HZ_300 is not set CONFIG_HZ_500=y # CONFIG_HZ_1000 is not set CONFIG_HZ=500 CONFIG_SCHED_HRTICK=y CONFIG_THUMB2_KERNEL=y CONFIG_AEABI=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y # CONFIG_ARM_MODULE_PLTS is not set CONFIG_ARCH_FORCE_MAX_ORDER=11 CONFIG_PARAVIRT=y CONFIG_PARAVIRT_TIME_ACCOUNTING=y CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y # end of Kernel Features # # Boot options # CONFIG_USE_OF=y CONFIG_ATAGS=y # CONFIG_UNUSED_BOARD_FILES is not set CONFIG_DEPRECATED_PARAM_STRUCT=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y # CONFIG_ARM_ATAG_DTB_COMPAT is not set CONFIG_CMDLINE="" # CONFIG_XIP_KERNEL is not set # CONFIG_CRASH_DUMP is not set # CONFIG_AUTO_ZRELADDR is not set # end of Boot options # # CPU Power Management # # # CPU Frequency scaling # # CONFIG_CPU_FREQ is not set # end of CPU Frequency scaling # # CPU Idle # CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y # CONFIG_CPU_IDLE_GOV_TEO is not set CONFIG_DT_IDLE_STATES=y # # ARM CPU Idle Drivers # CONFIG_ARM_CPUIDLE=y # CONFIG_ARM_CLPS711X_CPUIDLE is not set # CONFIG_ARM_KIRKWOOD_CPUIDLE is not set # CONFIG_ARM_ZYNQ_CPUIDLE is not set # CONFIG_ARM_AT91_CPUIDLE is not set # CONFIG_ARM_EXYNOS_CPUIDLE is not set # CONFIG_ARM_MVEBU_V7_CPUIDLE is not set # end of ARM CPU Idle Drivers # end of CPU Idle # end of CPU Power Management # # Floating point emulation # # # At least one emulation must be selected # # end of Floating point emulation # # Power management options # CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y CONFIG_SUSPEND_SKIP_SYNC=y CONFIG_PM_SLEEP=y # CONFIG_PM_AUTOSLEEP is not set CONFIG_PM_USERSPACE_AUTOSLEEP=y # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y CONFIG_PM_DEBUG=y CONFIG_PM_ADVANCED_DEBUG=y # CONFIG_PM_TEST_SUSPEND is not set CONFIG_PM_SLEEP_DEBUG=y CONFIG_APM_EMULATION=y CONFIG_PM_CLK=y CONFIG_PM_GENERIC_DOMAINS=y CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y CONFIG_PM_GENERIC_DOMAINS_SLEEP=y CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_CPU_PM=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARM_CPU_SUSPEND=y # end of Power management options CONFIG_AS_VFP_VMRS_FPINST=y # # General architecture-dependent options # CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_HAVE_NMI=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_ARCH_HAS_FORTIFY_SOURCE=y CONFIG_ARCH_HAS_KEEPINITRD=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y CONFIG_ARCH_32BIT_OFF_T=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y # CONFIG_SECCOMP is not set CONFIG_HAVE_STACKPROTECTOR=y # CONFIG_STACKPROTECTOR is not set CONFIG_LTO_NONE=y CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_LOCK_EVENT_COUNTS=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_HAVE_ARCH_PFN_VALID=y # # GCOV-based kernel profiling # # CONFIG_GCOV_KERNEL is not set CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling CONFIG_HAVE_GCC_PLUGINS=y # end of General architecture-dependent options CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=1 CONFIG_MODULE_SIG_FORMAT=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y # CONFIG_MODULE_UNLOAD is not set CONFIG_MODVERSIONS=y # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_MODULE_SIG=y CONFIG_MODULE_SIG_FORCE=y # CONFIG_MODULE_SIG_ALL is not set # # Do not forget to sign required modules with scripts/sign-file # # CONFIG_MODULE_SIG_SHA1 is not set # CONFIG_MODULE_SIG_SHA224 is not set # CONFIG_MODULE_SIG_SHA256 is not set # CONFIG_MODULE_SIG_SHA384 is not set CONFIG_MODULE_SIG_SHA512=y CONFIG_MODULE_SIG_HASH="sha512" CONFIG_MODULE_COMPRESS_NONE=y # CONFIG_MODULE_COMPRESS_GZIP is not set # CONFIG_MODULE_COMPRESS_XZ is not set # CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y # CONFIG_BLOCK is not set CONFIG_ASN1=y CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y CONFIG_FREEZER=y # # Executable file formats # # CONFIG_BINFMT_ELF_FDPIC is not set # CONFIG_BINFMT_SCRIPT is not set CONFIG_ARCH_HAS_BINFMT_FLAT=y CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y # CONFIG_BINFMT_FLAT_OLD is not set CONFIG_BINFMT_ZFLAT=y CONFIG_BINFMT_MISC=m CONFIG_COREDUMP=y # end of Executable file formats # # Memory Management options # # # SLAB allocator options # # CONFIG_SLAB is not set # CONFIG_SLUB is not set CONFIG_SLOB=y # end of SLAB allocator options # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set CONFIG_COMPAT_BRK=y # CONFIG_MMAP_ALLOW_UNINITIALIZED is not set CONFIG_SELECT_MEMORY_MODEL=y # CONFIG_FLATMEM_MANUAL is not set CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_STATIC=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_SPLIT_PTLOCK_CPUS=999999 # CONFIG_PAGE_REPORTING is not set CONFIG_NOMMU_INITIAL_TRIM_EXCESS=1 CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_NEED_PER_CPU_KM=y CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y # CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_PERCPU_STATS is not set CONFIG_GUP_TEST=y # # Data Access Monitoring # CONFIG_DAMON=y # CONFIG_DAMON_SYSFS is not set # end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y CONFIG_NET_INGRESS=y CONFIG_NET_EGRESS=y CONFIG_SKB_EXTENSIONS=y # # Networking options # # CONFIG_PACKET is not set CONFIG_UNIX=y CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y CONFIG_UNIX_DIAG=m # CONFIG_TLS is not set CONFIG_XFRM=y CONFIG_XFRM_OFFLOAD=y CONFIG_XFRM_ALGO=y CONFIG_XFRM_USER=m # CONFIG_XFRM_INTERFACE is not set CONFIG_XFRM_SUB_POLICY=y # CONFIG_XFRM_MIGRATE is not set CONFIG_XFRM_AH=y CONFIG_XFRM_ESP=m CONFIG_XFRM_IPCOMP=m # CONFIG_NET_KEY is not set CONFIG_XFRM_ESPINTCP=y # CONFIG_XDP_SOCKETS is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y # CONFIG_IP_PNP_BOOTP is not set # CONFIG_IP_PNP_RARP is not set CONFIG_NET_IPIP=y # CONFIG_NET_IPGRE_DEMUX is not set CONFIG_NET_IP_TUNNEL=y CONFIG_IP_MROUTE_COMMON=y CONFIG_IP_MROUTE=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_SYN_COOKIES=y # CONFIG_NET_IPVTI is not set CONFIG_NET_UDP_TUNNEL=y CONFIG_NET_FOU=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_INET_AH=y CONFIG_INET_ESP=m CONFIG_INET_ESP_OFFLOAD=m CONFIG_INET_ESPINTCP=y # CONFIG_INET_IPCOMP is not set CONFIG_INET_TUNNEL=y CONFIG_INET_DIAG=m CONFIG_INET_TCP_DIAG=m CONFIG_INET_UDP_DIAG=m CONFIG_INET_RAW_DIAG=m CONFIG_INET_DIAG_DESTROY=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set CONFIG_IPV6=y CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTE_INFO=y CONFIG_IPV6_OPTIMISTIC_DAD=y # CONFIG_INET6_AH is not set # CONFIG_INET6_ESP is not set CONFIG_INET6_IPCOMP=m CONFIG_IPV6_MIP6=m CONFIG_IPV6_ILA=m CONFIG_INET6_XFRM_TUNNEL=m CONFIG_INET6_TUNNEL=y CONFIG_IPV6_VTI=y # CONFIG_IPV6_SIT is not set CONFIG_IPV6_TUNNEL=y CONFIG_IPV6_FOU=y CONFIG_IPV6_FOU_TUNNEL=y CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y # CONFIG_IPV6_MROUTE is not set # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set # CONFIG_IPV6_RPL_LWTUNNEL is not set # CONFIG_IPV6_IOAM6_LWTUNNEL is not set CONFIG_MPTCP=y CONFIG_INET_MPTCP_DIAG=m # CONFIG_MPTCP_IPV6 is not set CONFIG_MPTCP_KUNIT_TEST=m CONFIG_NETWORK_SECMARK=y CONFIG_NET_PTP_CLASSIFY=y CONFIG_NETWORK_PHY_TIMESTAMPING=y CONFIG_NETFILTER=y # CONFIG_NETFILTER_ADVANCED is not set # # Core Netfilter Configuration # CONFIG_NETFILTER_INGRESS=y CONFIG_NETFILTER_EGRESS=y CONFIG_NETFILTER_NETLINK=y CONFIG_NETFILTER_NETLINK_LOG=y # CONFIG_NF_CONNTRACK is not set CONFIG_NF_LOG_SYSLOG=y # CONFIG_NF_TABLES is not set CONFIG_NETFILTER_XTABLES=y # # Xtables combined modules # CONFIG_NETFILTER_XT_MARK=y # # Xtables targets # CONFIG_NETFILTER_XT_TARGET_LOG=y CONFIG_NETFILTER_XT_TARGET_NFLOG=m # CONFIG_NETFILTER_XT_TARGET_SECMARK is not set # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set # # Xtables matches # CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y CONFIG_NETFILTER_XT_MATCH_POLICY=m # end of Core Netfilter Configuration # CONFIG_IP_SET is not set # CONFIG_IP_VS is not set # # IP: Netfilter Configuration # CONFIG_NF_SOCKET_IPV4=m CONFIG_NF_TPROXY_IPV4=m CONFIG_NF_DUP_IPV4=m CONFIG_NF_LOG_ARP=m CONFIG_NF_LOG_IPV4=m CONFIG_NF_REJECT_IPV4=m CONFIG_IP_NF_IPTABLES=y CONFIG_IP_NF_FILTER=y # CONFIG_IP_NF_TARGET_REJECT is not set # CONFIG_IP_NF_MANGLE is not set CONFIG_IP_NF_RAW=y # end of IP: Netfilter Configuration # # IPv6: Netfilter Configuration # CONFIG_NF_SOCKET_IPV6=m # CONFIG_NF_TPROXY_IPV6 is not set CONFIG_NF_DUP_IPV6=y CONFIG_NF_REJECT_IPV6=y CONFIG_NF_LOG_IPV6=y CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m # CONFIG_IP6_NF_FILTER is not set CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m # end of IPv6: Netfilter Configuration # CONFIG_BPFILTER is not set # CONFIG_IP_DCCP is not set CONFIG_IP_SCTP=y CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set CONFIG_SCTP_COOKIE_HMAC_MD5=y # CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set CONFIG_INET_SCTP_DIAG=m CONFIG_RDS=m # CONFIG_RDS_TCP is not set # CONFIG_RDS_DEBUG is not set CONFIG_TIPC=y # CONFIG_TIPC_MEDIA_UDP is not set # CONFIG_TIPC_CRYPTO is not set CONFIG_TIPC_DIAG=m # CONFIG_ATM is not set CONFIG_L2TP=y # CONFIG_L2TP_DEBUGFS is not set # CONFIG_L2TP_V3 is not set # CONFIG_BRIDGE is not set # CONFIG_VLAN_8021Q is not set CONFIG_LLC=y # CONFIG_LLC2 is not set CONFIG_ATALK=y # CONFIG_DEV_APPLETALK is not set CONFIG_X25=m CONFIG_LAPB=m CONFIG_PHONET=m # CONFIG_6LOWPAN is not set CONFIG_IEEE802154=y # CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set # CONFIG_IEEE802154_SOCKET is not set CONFIG_MAC802154=m # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set CONFIG_DNS_RESOLVER=y # CONFIG_BATMAN_ADV is not set CONFIG_OPENVSWITCH=m # CONFIG_VSOCKETS is not set # CONFIG_NETLINK_DIAG is not set CONFIG_MPLS=y CONFIG_NET_MPLS_GSO=m CONFIG_NET_NSH=m CONFIG_HSR=m CONFIG_NET_SWITCHDEV=y CONFIG_NET_L3_MASTER_DEV=y CONFIG_QRTR=y # CONFIG_QRTR_SMD is not set # CONFIG_QRTR_TUN is not set # CONFIG_QRTR_MHI is not set CONFIG_NET_NCSI=y # CONFIG_NCSI_OEM_CMD_GET_MAC is not set CONFIG_NCSI_OEM_CMD_KEEP_PHY=y # CONFIG_CGROUP_NET_PRIO is not set # CONFIG_CGROUP_NET_CLASSID is not set CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y # CONFIG_BPF_STREAM_PARSER is not set # # Network testing # # end of Network testing # end of Networking options # CONFIG_HAMRADIO is not set CONFIG_CAN=m CONFIG_CAN_RAW=m CONFIG_CAN_BCM=m CONFIG_CAN_GW=m CONFIG_CAN_J1939=m CONFIG_CAN_ISOTP=m CONFIG_BT=m CONFIG_BT_BREDR=y # CONFIG_BT_RFCOMM is not set CONFIG_BT_BNEP=y # CONFIG_BT_BNEP_MC_FILTER is not set # CONFIG_BT_BNEP_PROTO_FILTER is not set # CONFIG_BT_HS is not set CONFIG_BT_LE=y # CONFIG_BT_LEDS is not set CONFIG_BT_MSFTEXT=y CONFIG_BT_AOSPEXT=y CONFIG_BT_DEBUGFS=y CONFIG_BT_SELFTEST=y # CONFIG_BT_SELFTEST_ECDH is not set # CONFIG_BT_SELFTEST_SMP is not set CONFIG_BT_FEATURE_DEBUG=y # # Bluetooth device drivers # CONFIG_BT_INTEL=m CONFIG_BT_HCIBTUSB=m CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y # CONFIG_BT_HCIBTUSB_BCM is not set # CONFIG_BT_HCIBTUSB_MTK is not set # CONFIG_BT_HCIBTUSB_RTL is not set CONFIG_BT_HCIBTSDIO=m # CONFIG_BT_HCIUART is not set # CONFIG_BT_HCIBCM203X is not set CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m # CONFIG_BT_HCIDTL1 is not set CONFIG_BT_HCIBT3C=m # CONFIG_BT_HCIBLUECARD is not set # CONFIG_BT_HCIVHCI is not set CONFIG_BT_MRVL=m # CONFIG_BT_MRVL_SDIO is not set CONFIG_BT_ATH3K=m # CONFIG_BT_MTKSDIO is not set # CONFIG_BT_MTKUART is not set # CONFIG_BT_QCOMSMD is not set # CONFIG_BT_VIRTIO is not set # end of Bluetooth device drivers # CONFIG_AF_RXRPC is not set CONFIG_AF_KCM=m CONFIG_STREAM_PARSER=y CONFIG_MCTP=y CONFIG_FIB_RULES=y # CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set CONFIG_NET_9P=y CONFIG_NET_9P_FD=y CONFIG_NET_9P_VIRTIO=m CONFIG_NET_9P_DEBUG=y CONFIG_CAIF=m # CONFIG_CAIF_DEBUG is not set CONFIG_CAIF_NETDEV=m CONFIG_CAIF_USB=m CONFIG_CEPH_LIB=y # CONFIG_CEPH_LIB_PRETTYDEBUG is not set CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y CONFIG_NFC=y CONFIG_NFC_DIGITAL=y # CONFIG_NFC_NCI is not set CONFIG_NFC_HCI=m # CONFIG_NFC_SHDLC is not set # # Near Field Communication (NFC) devices # CONFIG_NFC_TRF7970A=m CONFIG_NFC_SIM=y # CONFIG_NFC_PORT100 is not set CONFIG_NFC_PN533=m CONFIG_NFC_PN533_USB=m CONFIG_NFC_PN533_I2C=m CONFIG_NFC_PN532_UART=m CONFIG_NFC_ST95HF=y # end of Near Field Communication (NFC) devices # CONFIG_PSAMPLE is not set # CONFIG_NET_IFE is not set CONFIG_LWTUNNEL=y CONFIG_LWTUNNEL_BPF=y CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y CONFIG_NET_SOCK_MSG=y CONFIG_PAGE_POOL=y CONFIG_PAGE_POOL_STATS=y # CONFIG_FAILOVER is not set # CONFIG_ETHTOOL_NETLINK is not set CONFIG_NETDEV_ADDR_LIST_TEST=m # # Device Drivers # CONFIG_ARM_AMBA=y CONFIG_PCCARD=m CONFIG_PCMCIA=m CONFIG_PCMCIA_LOAD_CIS=y # # PC-card bridges # # CONFIG_OMAP_CF is not set # # Generic Driver Options # CONFIG_AUXILIARY_BUS=y # CONFIG_UEVENT_HELPER is not set # CONFIG_DEVTMPFS is not set # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set # # Firmware loader # CONFIG_FW_LOADER=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_FW_LOADER_SYSFS=y CONFIG_EXTRA_FIRMWARE="" CONFIG_FW_LOADER_USER_HELPER=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y # CONFIG_FW_LOADER_COMPRESS is not set CONFIG_FW_CACHE=y CONFIG_FW_UPLOAD=y # end of Firmware loader CONFIG_ALLOW_DEV_COREDUMP=y CONFIG_DEBUG_DRIVER=y # CONFIG_DEBUG_DEVRES is not set # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set CONFIG_TEST_ASYNC_DRIVER_PROBE=m CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_SOC_BUS=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=m CONFIG_REGMAP_SPI=y CONFIG_REGMAP_SPMI=m CONFIG_REGMAP_W1=m CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_IRQ=y # end of Generic Driver Options # # Bus devices # # CONFIG_ARM_INTEGRATOR_LM is not set # CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_BT1_APB is not set # CONFIG_BT1_AXI is not set CONFIG_MOXTET=m # CONFIG_HISILICON_LPC is not set CONFIG_IMX_WEIM=y # CONFIG_INTEL_IXP4XX_EB is not set # CONFIG_QCOM_EBI2 is not set CONFIG_VEXPRESS_CONFIG=y # CONFIG_FSL_MC_BUS is not set CONFIG_MHI_BUS=m # CONFIG_MHI_BUS_DEBUG is not set CONFIG_MHI_BUS_EP=y # end of Bus devices # CONFIG_CONNECTOR is not set # # Firmware Drivers # # # ARM System Control and Management Interface Protocol # # CONFIG_ARM_SCMI_PROTOCOL is not set CONFIG_ARM_SCMI_POWER_DOMAIN=y # CONFIG_ARM_SCMI_POWER_CONTROL is not set # end of ARM System Control and Management Interface Protocol # CONFIG_ARM_SCPI_PROTOCOL is not set CONFIG_ARM_SCPI_POWER_DOMAIN=y # CONFIG_FIRMWARE_MEMMAP is not set # CONFIG_TURRIS_MOX_RWTM is not set # CONFIG_BCM47XX_NVRAM is not set CONFIG_GOOGLE_FIRMWARE=y CONFIG_GOOGLE_COREBOOT_TABLE=m CONFIG_GOOGLE_MEMCONSOLE=m CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=m CONFIG_GOOGLE_VPD=m CONFIG_IMX_DSP=m CONFIG_IMX_SCU=y CONFIG_IMX_SCU_PD=y # # Tegra firmware driver # # end of Tegra firmware driver # end of Firmware Drivers CONFIG_GNSS=m CONFIG_GNSS_SERIAL=m CONFIG_GNSS_MTK_SERIAL=m # CONFIG_GNSS_SIRF_SERIAL is not set # CONFIG_GNSS_UBX_SERIAL is not set CONFIG_GNSS_USB=m # CONFIG_MTD is not set CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set # CONFIG_OF_ALL_DTBS is not set CONFIG_OF_FLATTREE=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_KOBJ=y CONFIG_OF_ADDRESS=y CONFIG_OF_IRQ=y CONFIG_OF_RESERVED_MEM=y # CONFIG_OF_OVERLAY is not set CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_PARPORT=y CONFIG_PARPORT_PC=m # CONFIG_PARPORT_PC_FIFO is not set # CONFIG_PARPORT_PC_SUPERIO is not set CONFIG_PARPORT_PC_PCMCIA=m # CONFIG_PARPORT_AX88796 is not set # CONFIG_PARPORT_1284 is not set # # NVME Support # # end of NVME Support # # Misc devices # CONFIG_AD525X_DPOT=m CONFIG_AD525X_DPOT_I2C=m CONFIG_AD525X_DPOT_SPI=m CONFIG_DUMMY_IRQ=y # CONFIG_ICS932S401 is not set # CONFIG_ATMEL_SSC is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_GEHC_ACHC is not set CONFIG_HI6421V600_IRQ=m # CONFIG_QCOM_COINCELL is not set # CONFIG_QCOM_FASTRPC is not set # CONFIG_APDS9802ALS is not set # CONFIG_ISL29003 is not set CONFIG_ISL29020=m CONFIG_SENSORS_TSL2550=m # CONFIG_SENSORS_BH1770 is not set CONFIG_SENSORS_APDS990X=m CONFIG_HMC6352=m # CONFIG_DS1682 is not set CONFIG_LATTICE_ECP3_CONFIG=m CONFIG_SRAM=y CONFIG_SRAM_EXEC=y CONFIG_XILINX_SDFEC=y # CONFIG_HISI_HIKEY_USB is not set # CONFIG_OPEN_DICE is not set CONFIG_VCPU_STALL_DETECTOR=m # CONFIG_C2PORT is not set # # EEPROM support # CONFIG_EEPROM_AT24=m CONFIG_EEPROM_AT25=y CONFIG_EEPROM_LEGACY=m CONFIG_EEPROM_MAX6875=m CONFIG_EEPROM_93CX6=m # CONFIG_EEPROM_93XX46 is not set CONFIG_EEPROM_IDT_89HPESX=m CONFIG_EEPROM_EE1004=m # end of EEPROM support # # Texas Instruments shared transport line discipline # CONFIG_TI_ST=m # end of Texas Instruments shared transport line discipline # # Altera FPGA firmware download module (requires I2C) # CONFIG_ALTERA_STAPL=m # CONFIG_ECHO is not set # CONFIG_MISC_RTSX_USB is not set CONFIG_UACCE=y # CONFIG_PVPANIC is not set # end of Misc devices # # SCSI device support # # end of SCSI device support # # IEEE 1394 (FireWire) support # # CONFIG_FIREWIRE is not set # end of IEEE 1394 (FireWire) support # CONFIG_NETDEVICES is not set # # Input device support # # CONFIG_INPUT is not set # # Hardware I/O ports # CONFIG_SERIO=y CONFIG_SERIO_SERPORT=y CONFIG_SERIO_PARKBD=m CONFIG_SERIO_AMBAKMI=m CONFIG_SERIO_LIBPS2=m CONFIG_SERIO_RAW=m CONFIG_SERIO_ALTERA_PS2=y # CONFIG_SERIO_PS2MULT is not set CONFIG_SERIO_ARC_PS2=y CONFIG_SERIO_APBPS2=y # CONFIG_SERIO_OLPC_APSP is not set # CONFIG_SERIO_SUN4I_PS2 is not set # CONFIG_SERIO_GPIO_PS2 is not set # CONFIG_USERIO is not set # CONFIG_GAMEPORT is not set # end of Hardware I/O ports # end of Input device support # # Character devices # CONFIG_TTY=y # CONFIG_VT is not set CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set # CONFIG_LDISC_AUTOLOAD is not set # # Serial drivers # CONFIG_SERIAL_EARLYCON=y # CONFIG_SERIAL_8250 is not set # # Non-8250 serial port support # # CONFIG_SERIAL_AMBA_PL010 is not set CONFIG_SERIAL_AMBA_PL011=m # CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set # CONFIG_SERIAL_ATMEL is not set # CONFIG_SERIAL_MESON is not set # CONFIG_SERIAL_CLPS711X is not set # CONFIG_SERIAL_SAMSUNG is not set # CONFIG_SERIAL_TEGRA is not set # CONFIG_SERIAL_TEGRA_TCU is not set # CONFIG_SERIAL_MAX3100 is not set # CONFIG_SERIAL_MAX310X is not set CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=m CONFIG_SERIAL_IMX_EARLYCON=y CONFIG_SERIAL_UARTLITE=y # CONFIG_SERIAL_UARTLITE_CONSOLE is not set CONFIG_SERIAL_UARTLITE_NR_UARTS=1 # CONFIG_SERIAL_SH_SCI is not set # CONFIG_SERIAL_HS_LPC32XX is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_MSM is not set # CONFIG_SERIAL_VT8500 is not set # CONFIG_SERIAL_OMAP is not set CONFIG_SERIAL_SIFIVE=y # CONFIG_SERIAL_SIFIVE_CONSOLE is not set # CONFIG_SERIAL_LANTIQ is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set # CONFIG_SERIAL_TIMBERDALE is not set # CONFIG_SERIAL_BCM63XX is not set CONFIG_SERIAL_ALTERA_JTAGUART=m CONFIG_SERIAL_ALTERA_UART=y CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4 CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200 CONFIG_SERIAL_ALTERA_UART_CONSOLE=y # CONFIG_SERIAL_MXS_AUART is not set # CONFIG_SERIAL_XILINX_PS_UART is not set # CONFIG_SERIAL_MPS2_UART is not set CONFIG_SERIAL_ARC=m CONFIG_SERIAL_ARC_NR_PORTS=1 CONFIG_SERIAL_FSL_LPUART=m # CONFIG_SERIAL_FSL_LPUART_CONSOLE is not set # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set # CONFIG_SERIAL_ST_ASC is not set CONFIG_SERIAL_MEN_Z135=y CONFIG_SERIAL_SPRD=y CONFIG_SERIAL_SPRD_CONSOLE=y # CONFIG_SERIAL_STM32 is not set # CONFIG_SERIAL_MVEBU_UART is not set # CONFIG_SERIAL_OWL is not set # CONFIG_SERIAL_RDA is not set # CONFIG_SERIAL_MILBEAUT_USIO is not set CONFIG_SERIAL_LITEUART=y CONFIG_SERIAL_LITEUART_MAX_PORTS=1 # CONFIG_SERIAL_LITEUART_CONSOLE is not set # CONFIG_SERIAL_SUNPLUS is not set # end of Serial drivers CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_NONSTANDARD=y # CONFIG_N_HDLC is not set # CONFIG_N_GSM is not set CONFIG_NULL_TTY=y # CONFIG_HVC_DCC is not set CONFIG_RPMSG_TTY=m CONFIG_SERIAL_DEV_BUS=y # CONFIG_SERIAL_DEV_CTRL_TTYPORT is not set CONFIG_TTY_PRINTK=y CONFIG_TTY_PRINTK_LEVEL=6 # CONFIG_PRINTER is not set CONFIG_PPDEV=m # CONFIG_VIRTIO_CONSOLE is not set CONFIG_IPMI_HANDLER=y CONFIG_IPMI_PLAT_DATA=y # CONFIG_IPMI_PANIC_EVENT is not set CONFIG_IPMI_DEVICE_INTERFACE=y CONFIG_IPMI_SI=m # CONFIG_IPMI_SSIF is not set CONFIG_IPMI_IPMB=m CONFIG_IPMI_WATCHDOG=m CONFIG_IPMI_POWEROFF=y # CONFIG_ASPEED_KCS_IPMI_BMC is not set # CONFIG_NPCM7XX_KCS_IPMI_BMC is not set # CONFIG_ASPEED_BT_IPMI_BMC is not set # CONFIG_IPMB_DEVICE_INTERFACE is not set CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_TIMERIOMEM=m CONFIG_HW_RANDOM_ATMEL=y # CONFIG_HW_RANDOM_BA431 is not set CONFIG_HW_RANDOM_BCM2835=y CONFIG_HW_RANDOM_IPROC_RNG200=y CONFIG_HW_RANDOM_IXP4XX=y CONFIG_HW_RANDOM_OMAP=y CONFIG_HW_RANDOM_OMAP3_ROM=y CONFIG_HW_RANDOM_VIRTIO=m CONFIG_HW_RANDOM_IMX_RNGC=y CONFIG_HW_RANDOM_NOMADIK=y CONFIG_HW_RANDOM_STM32=y CONFIG_HW_RANDOM_MESON=y CONFIG_HW_RANDOM_MTK=y CONFIG_HW_RANDOM_EXYNOS=y CONFIG_HW_RANDOM_NPCM=y CONFIG_HW_RANDOM_KEYSTONE=y # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set # # PCMCIA character devices # CONFIG_SYNCLINK_CS=m CONFIG_CARDMAN_4000=m CONFIG_CARDMAN_4040=m # CONFIG_SCR24X is not set # end of PCMCIA character devices CONFIG_DEVMEM=y CONFIG_TCG_TPM=y # CONFIG_HW_RANDOM_TPM is not set CONFIG_TCG_TIS_CORE=m CONFIG_TCG_TIS=m # CONFIG_TCG_TIS_SPI is not set # CONFIG_TCG_TIS_I2C is not set # CONFIG_TCG_TIS_SYNQUACER is not set CONFIG_TCG_TIS_I2C_CR50=m # CONFIG_TCG_TIS_I2C_ATMEL is not set # CONFIG_TCG_TIS_I2C_INFINEON is not set # CONFIG_TCG_TIS_I2C_NUVOTON is not set CONFIG_TCG_VTPM_PROXY=y CONFIG_TCG_TIS_ST33ZP24=m CONFIG_TCG_TIS_ST33ZP24_I2C=m # CONFIG_TCG_TIS_ST33ZP24_SPI is not set CONFIG_XILLYBUS_CLASS=y CONFIG_XILLYBUS=m CONFIG_XILLYBUS_OF=m CONFIG_XILLYUSB=y CONFIG_RANDOM_TRUST_CPU=y CONFIG_RANDOM_TRUST_BOOTLOADER=y # end of Character devices # # I2C support # CONFIG_I2C=m CONFIG_I2C_BOARDINFO=y # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=m # CONFIG_I2C_MUX is not set CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_SMBUS=m CONFIG_I2C_ALGOBIT=m CONFIG_I2C_ALGOPCA=m # # I2C Hardware Bus support # # CONFIG_I2C_HIX5HD2 is not set # # I2C system bus drivers (mostly embedded / system-on-chip) # # CONFIG_I2C_ALTERA is not set # CONFIG_I2C_ASPEED is not set # CONFIG_I2C_AT91 is not set # CONFIG_I2C_AXXIA is not set # CONFIG_I2C_BCM2835 is not set # CONFIG_I2C_BCM_IPROC is not set # CONFIG_I2C_BCM_KONA is not set CONFIG_I2C_BRCMSTB=m # CONFIG_I2C_CADENCE is not set CONFIG_I2C_CBUS_GPIO=m # CONFIG_I2C_DAVINCI is not set # CONFIG_I2C_DESIGNWARE_PLATFORM is not set # CONFIG_I2C_DIGICOLOR is not set # CONFIG_I2C_EMEV2 is not set # CONFIG_I2C_EXYNOS5 is not set # CONFIG_I2C_GPIO is not set # CONFIG_I2C_HIGHLANDER is not set # CONFIG_I2C_HISI is not set # CONFIG_I2C_IMG is not set CONFIG_I2C_IMX=m # CONFIG_I2C_IMX_LPI2C is not set # CONFIG_I2C_IOP3XX is not set # CONFIG_I2C_JZ4780 is not set CONFIG_I2C_KEMPLD=m # CONFIG_I2C_LPC2K is not set # CONFIG_I2C_MESON is not set # CONFIG_I2C_MICROCHIP_CORE is not set # CONFIG_I2C_MT65XX is not set # CONFIG_I2C_MT7621 is not set # CONFIG_I2C_MV64XXX is not set # CONFIG_I2C_MXS is not set CONFIG_I2C_NOMADIK=m # CONFIG_I2C_NPCM is not set CONFIG_I2C_OCORES=m # CONFIG_I2C_OMAP is not set # CONFIG_I2C_OWL is not set # CONFIG_I2C_APPLE is not set CONFIG_I2C_PCA_PLATFORM=m # CONFIG_I2C_PNX is not set # CONFIG_I2C_PXA is not set # CONFIG_I2C_QCOM_CCI is not set # CONFIG_I2C_QUP is not set # CONFIG_I2C_RIIC is not set CONFIG_I2C_RK3X=m # CONFIG_I2C_RZV2M is not set # CONFIG_I2C_S3C2410 is not set # CONFIG_I2C_SH_MOBILE is not set CONFIG_I2C_SIMTEC=m # CONFIG_I2C_ST is not set # CONFIG_I2C_STM32F4 is not set # CONFIG_I2C_STM32F7 is not set # CONFIG_I2C_SUN6I_P2WI is not set # CONFIG_I2C_SYNQUACER is not set # CONFIG_I2C_TEGRA is not set # CONFIG_I2C_TEGRA_BPMP is not set # CONFIG_I2C_UNIPHIER is not set # CONFIG_I2C_UNIPHIER_F is not set # CONFIG_I2C_VERSATILE is not set # CONFIG_I2C_WMT is not set CONFIG_I2C_XILINX=m # CONFIG_I2C_XLP9XX is not set # CONFIG_I2C_RCAR is not set # # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set CONFIG_I2C_DLN2=m CONFIG_I2C_CP2615=m CONFIG_I2C_PARPORT=m CONFIG_I2C_ROBOTFUZZ_OSIF=m CONFIG_I2C_TAOS_EVM=m CONFIG_I2C_TINY_USB=m CONFIG_I2C_VIPERBOARD=m # # Other I2C/SMBus bus drivers # # CONFIG_I2C_MLXCPLD is not set # CONFIG_I2C_FSI is not set CONFIG_I2C_VIRTIO=m # end of I2C Hardware Bus support CONFIG_I2C_STUB=m CONFIG_I2C_SLAVE=y CONFIG_I2C_SLAVE_EEPROM=m CONFIG_I2C_SLAVE_TESTUNIT=m # CONFIG_I2C_DEBUG_CORE is not set CONFIG_I2C_DEBUG_ALGO=y # CONFIG_I2C_DEBUG_BUS is not set # end of I2C support CONFIG_I3C=m CONFIG_CDNS_I3C_MASTER=m CONFIG_DW_I3C_MASTER=m # CONFIG_SVC_I3C_MASTER is not set # CONFIG_MIPI_I3C_HCI is not set CONFIG_SPI=y # CONFIG_SPI_DEBUG is not set CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y # # SPI Master Controller Drivers # CONFIG_SPI_ALTERA=m CONFIG_SPI_ALTERA_CORE=m # CONFIG_SPI_AR934X is not set # CONFIG_SPI_ATH79 is not set # CONFIG_SPI_ARMADA_3700 is not set # CONFIG_SPI_ASPEED_SMC is not set CONFIG_SPI_ATMEL=y # CONFIG_SPI_AT91_USART is not set # CONFIG_SPI_ATMEL_QUADSPI is not set # CONFIG_SPI_AXI_SPI_ENGINE is not set # CONFIG_SPI_BCM2835 is not set # CONFIG_SPI_BCM2835AUX is not set # CONFIG_SPI_BCM63XX is not set # CONFIG_SPI_BCM63XX_HSSPI is not set # CONFIG_SPI_BCM_QSPI is not set CONFIG_SPI_BITBANG=m CONFIG_SPI_BUTTERFLY=m CONFIG_SPI_CADENCE=y CONFIG_SPI_CADENCE_QUADSPI=m # CONFIG_SPI_CADENCE_XSPI is not set # CONFIG_SPI_CLPS711X is not set CONFIG_SPI_DESIGNWARE=m CONFIG_SPI_DW_DMA=y CONFIG_SPI_DW_MMIO=m # CONFIG_SPI_DW_BT1 is not set CONFIG_SPI_DLN2=m # CONFIG_SPI_EP93XX is not set CONFIG_SPI_FSI=m CONFIG_SPI_FSL_LPSPI=m CONFIG_SPI_FSL_QUADSPI=y # CONFIG_SPI_GXP is not set # CONFIG_SPI_HISI_KUNPENG is not set # CONFIG_SPI_HISI_SFC_V3XX is not set CONFIG_SPI_NXP_FLEXSPI=y CONFIG_SPI_GPIO=m # CONFIG_SPI_IMG_SPFI is not set CONFIG_SPI_IMX=m # CONFIG_SPI_INGENIC is not set # CONFIG_SPI_INTEL_PLATFORM is not set # CONFIG_SPI_JCORE is not set CONFIG_SPI_LM70_LLP=m # CONFIG_SPI_LP8841_RTC is not set # CONFIG_SPI_FSL_SPI is not set # CONFIG_SPI_FSL_DSPI is not set # CONFIG_SPI_MESON_SPICC is not set # CONFIG_SPI_MESON_SPIFC is not set # CONFIG_SPI_MICROCHIP_CORE is not set CONFIG_SPI_MICROCHIP_CORE_QSPI=m # CONFIG_SPI_MT65XX is not set # CONFIG_SPI_MT7621 is not set # CONFIG_SPI_MTK_NOR is not set # CONFIG_SPI_NPCM_FIU is not set # CONFIG_SPI_NPCM_PSPI is not set # CONFIG_SPI_LANTIQ_SSC is not set # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_OMAP_UWIRE is not set # CONFIG_SPI_OMAP24XX is not set # CONFIG_SPI_TI_QSPI is not set # CONFIG_SPI_OMAP_100K is not set # CONFIG_SPI_ORION is not set # CONFIG_SPI_PIC32 is not set # CONFIG_SPI_PIC32_SQI is not set CONFIG_SPI_PL022=m # CONFIG_SPI_PXA2XX is not set CONFIG_SPI_ROCKCHIP=y # CONFIG_SPI_ROCKCHIP_SFC is not set # CONFIG_SPI_RSPI is not set # CONFIG_SPI_QUP is not set # CONFIG_SPI_S3C64XX is not set CONFIG_SPI_SC18IS602=m # CONFIG_SPI_SH_MSIOF is not set # CONFIG_SPI_SH is not set # CONFIG_SPI_SH_HSPI is not set CONFIG_SPI_SIFIVE=m # CONFIG_SPI_SPRD is not set # CONFIG_SPI_SPRD_ADI is not set # CONFIG_SPI_STM32 is not set # CONFIG_SPI_STM32_QSPI is not set # CONFIG_SPI_ST_SSC4 is not set # CONFIG_SPI_SUN4I is not set # CONFIG_SPI_SUN6I is not set # CONFIG_SPI_SUNPLUS_SP7021 is not set # CONFIG_SPI_SYNQUACER is not set # CONFIG_SPI_MXIC is not set # CONFIG_SPI_TEGRA210_QUAD is not set # CONFIG_SPI_TEGRA114 is not set # CONFIG_SPI_TEGRA20_SFLASH is not set # CONFIG_SPI_TEGRA20_SLINK is not set # CONFIG_SPI_UNIPHIER is not set CONFIG_SPI_XCOMM=m CONFIG_SPI_XILINX=m # CONFIG_SPI_XLP is not set # CONFIG_SPI_XTENSA_XTFPGA is not set # CONFIG_SPI_ZYNQ_QSPI is not set CONFIG_SPI_ZYNQMP_GQSPI=y CONFIG_SPI_AMD=m # # SPI Multiplexer support # CONFIG_SPI_MUX=y # # SPI Protocol Masters # CONFIG_SPI_SPIDEV=y CONFIG_SPI_LOOPBACK_TEST=m CONFIG_SPI_TLE62X0=m # CONFIG_SPI_SLAVE is not set CONFIG_SPMI=m CONFIG_SPMI_HISI3670=m # CONFIG_SPMI_MSM_PMIC_ARB is not set # CONFIG_SPMI_MTK_PMIF is not set CONFIG_HSI=m CONFIG_HSI_BOARDINFO=y # # HSI controllers # # CONFIG_OMAP_SSI is not set # # HSI clients # # CONFIG_HSI_CHAR is not set CONFIG_PPS=m # CONFIG_PPS_DEBUG is not set # CONFIG_NTP_PPS is not set # # PPS clients support # CONFIG_PPS_CLIENT_KTIMER=m CONFIG_PPS_CLIENT_LDISC=m # CONFIG_PPS_CLIENT_PARPORT is not set # CONFIG_PPS_CLIENT_GPIO is not set # # PPS generators support # # # PTP clock support # # CONFIG_PTP_1588_CLOCK is not set CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # # end of PTP clock support CONFIG_PINCTRL=y CONFIG_GENERIC_PINCTRL_GROUPS=y CONFIG_PINMUX=y CONFIG_GENERIC_PINMUX_FUNCTIONS=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set # CONFIG_PINCTRL_AMD is not set CONFIG_PINCTRL_AT91=y CONFIG_PINCTRL_AT91PIO4=y CONFIG_PINCTRL_AXP209=m # CONFIG_PINCTRL_BM1880 is not set CONFIG_PINCTRL_CY8C95X0=m # CONFIG_PINCTRL_DA850_PUPD is not set CONFIG_PINCTRL_DA9062=m # CONFIG_PINCTRL_EQUILIBRIUM is not set # CONFIG_PINCTRL_INGENIC is not set # CONFIG_PINCTRL_LPC18XX is not set CONFIG_PINCTRL_MCP23S08_I2C=m CONFIG_PINCTRL_MCP23S08_SPI=m CONFIG_PINCTRL_MCP23S08=m CONFIG_PINCTRL_MICROCHIP_SGPIO=m # CONFIG_PINCTRL_OCELOT is not set # CONFIG_PINCTRL_PISTACHIO is not set # CONFIG_PINCTRL_ROCKCHIP is not set # CONFIG_PINCTRL_SINGLE is not set CONFIG_PINCTRL_STMFX=m # CONFIG_PINCTRL_OWL is not set # CONFIG_PINCTRL_ASPEED_G4 is not set # CONFIG_PINCTRL_ASPEED_G5 is not set # CONFIG_PINCTRL_ASPEED_G6 is not set # CONFIG_PINCTRL_BCM281XX is not set # CONFIG_PINCTRL_BCM2835 is not set # CONFIG_PINCTRL_BCM4908 is not set # CONFIG_PINCTRL_BCM6318 is not set # CONFIG_PINCTRL_BCM6328 is not set # CONFIG_PINCTRL_BCM6358 is not set # CONFIG_PINCTRL_BCM6362 is not set # CONFIG_PINCTRL_BCM6368 is not set # CONFIG_PINCTRL_BCM63268 is not set # CONFIG_PINCTRL_IPROC_GPIO is not set # CONFIG_PINCTRL_CYGNUS_MUX is not set # CONFIG_PINCTRL_NS is not set # CONFIG_PINCTRL_NSP_GPIO is not set # CONFIG_PINCTRL_NS2_MUX is not set # CONFIG_PINCTRL_NSP_MUX is not set # CONFIG_PINCTRL_AS370 is not set # CONFIG_PINCTRL_BERLIN_BG4CT is not set CONFIG_PINCTRL_MADERA=m CONFIG_PINCTRL_CS47L15=y CONFIG_PINCTRL_CS47L85=y CONFIG_PINCTRL_IMX=y CONFIG_PINCTRL_IMX7D=y CONFIG_PINCTRL_IMX7ULP=y # CONFIG_PINCTRL_IMX8MM is not set CONFIG_PINCTRL_IMX8MN=y CONFIG_PINCTRL_IMX8MP=m CONFIG_PINCTRL_IMX8MQ=m CONFIG_PINCTRL_IMX8ULP=m CONFIG_PINCTRL_IMXRT1050=y CONFIG_PINCTRL_IMX93=m # CONFIG_PINCTRL_IMXRT1170 is not set # # Intel pinctrl drivers # # end of Intel pinctrl drivers # # MediaTek pinctrl drivers # CONFIG_EINT_MTK=y CONFIG_PINCTRL_MTK=y # CONFIG_PINCTRL_MT2701 is not set # CONFIG_PINCTRL_MT7623 is not set # CONFIG_PINCTRL_MT7629 is not set # CONFIG_PINCTRL_MT8135 is not set # CONFIG_PINCTRL_MT8127 is not set # CONFIG_PINCTRL_MT2712 is not set # CONFIG_PINCTRL_MT6765 is not set # CONFIG_PINCTRL_MT6779 is not set # CONFIG_PINCTRL_MT6795 is not set # CONFIG_PINCTRL_MT6797 is not set # CONFIG_PINCTRL_MT7622 is not set # CONFIG_PINCTRL_MT7986 is not set # CONFIG_PINCTRL_MT8167 is not set # CONFIG_PINCTRL_MT8173 is not set # CONFIG_PINCTRL_MT8183 is not set # CONFIG_PINCTRL_MT8186 is not set # CONFIG_PINCTRL_MT8188 is not set # CONFIG_PINCTRL_MT8192 is not set # CONFIG_PINCTRL_MT8195 is not set # CONFIG_PINCTRL_MT8365 is not set # CONFIG_PINCTRL_MT8516 is not set CONFIG_PINCTRL_MT6397=y # end of MediaTek pinctrl drivers CONFIG_PINCTRL_MESON=y CONFIG_PINCTRL_MESON8=y CONFIG_PINCTRL_MESON8B=y CONFIG_PINCTRL_MESON8_PMX=y # CONFIG_PINCTRL_WPCM450 is not set # CONFIG_PINCTRL_NPCM7XX is not set # CONFIG_PINCTRL_PXA25X is not set # CONFIG_PINCTRL_PXA27X is not set # CONFIG_PINCTRL_MSM is not set # CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set # CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set # CONFIG_PINCTRL_LPASS_LPI is not set # # Renesas pinctrl drivers # # CONFIG_PINCTRL_RENESAS is not set # CONFIG_PINCTRL_PFC_EMEV2 is not set # CONFIG_PINCTRL_PFC_R8A77995 is not set # CONFIG_PINCTRL_PFC_R8A7794 is not set # CONFIG_PINCTRL_PFC_R8A77990 is not set # CONFIG_PINCTRL_PFC_R8A7779 is not set # CONFIG_PINCTRL_PFC_R8A7790 is not set # CONFIG_PINCTRL_PFC_R8A77950 is not set # CONFIG_PINCTRL_PFC_R8A77951 is not set # CONFIG_PINCTRL_PFC_R8A7778 is not set # CONFIG_PINCTRL_PFC_R8A7793 is not set # CONFIG_PINCTRL_PFC_R8A7791 is not set # CONFIG_PINCTRL_PFC_R8A77965 is not set # CONFIG_PINCTRL_PFC_R8A77960 is not set # CONFIG_PINCTRL_PFC_R8A77961 is not set # CONFIG_PINCTRL_PFC_R8A779F0 is not set # CONFIG_PINCTRL_PFC_R8A7792 is not set # CONFIG_PINCTRL_PFC_R8A77980 is not set # CONFIG_PINCTRL_PFC_R8A77970 is not set # CONFIG_PINCTRL_PFC_R8A779A0 is not set # CONFIG_PINCTRL_PFC_R8A779G0 is not set # CONFIG_PINCTRL_PFC_R8A7740 is not set # CONFIG_PINCTRL_PFC_R8A73A4 is not set # CONFIG_PINCTRL_RZA1 is not set # CONFIG_PINCTRL_RZA2 is not set # CONFIG_PINCTRL_RZG2L is not set # CONFIG_PINCTRL_PFC_R8A77470 is not set # CONFIG_PINCTRL_PFC_R8A7745 is not set # CONFIG_PINCTRL_PFC_R8A7742 is not set # CONFIG_PINCTRL_PFC_R8A7743 is not set # CONFIG_PINCTRL_PFC_R8A7744 is not set # CONFIG_PINCTRL_PFC_R8A774C0 is not set # CONFIG_PINCTRL_PFC_R8A774E1 is not set # CONFIG_PINCTRL_PFC_R8A774A1 is not set # CONFIG_PINCTRL_PFC_R8A774B1 is not set # CONFIG_PINCTRL_RZN1 is not set # CONFIG_PINCTRL_RZV2M is not set # CONFIG_PINCTRL_PFC_SH7203 is not set # CONFIG_PINCTRL_PFC_SH7264 is not set # CONFIG_PINCTRL_PFC_SH7269 is not set # CONFIG_PINCTRL_PFC_SH7720 is not set # CONFIG_PINCTRL_PFC_SH7722 is not set # CONFIG_PINCTRL_PFC_SH7734 is not set # CONFIG_PINCTRL_PFC_SH7757 is not set # CONFIG_PINCTRL_PFC_SH7785 is not set # CONFIG_PINCTRL_PFC_SH7786 is not set # CONFIG_PINCTRL_PFC_SH73A0 is not set # CONFIG_PINCTRL_PFC_SH7723 is not set # CONFIG_PINCTRL_PFC_SH7724 is not set # CONFIG_PINCTRL_PFC_SHX3 is not set # end of Renesas pinctrl drivers # CONFIG_PINCTRL_EXYNOS is not set # CONFIG_PINCTRL_S3C24XX is not set # CONFIG_PINCTRL_S3C64XX is not set # CONFIG_PINCTRL_SPRD_SC9860 is not set # CONFIG_PINCTRL_STARFIVE_JH7100 is not set # CONFIG_PINCTRL_STM32F429 is not set # CONFIG_PINCTRL_STM32F469 is not set # CONFIG_PINCTRL_STM32F746 is not set # CONFIG_PINCTRL_STM32F769 is not set # CONFIG_PINCTRL_STM32H743 is not set # CONFIG_PINCTRL_STM32MP135 is not set # CONFIG_PINCTRL_STM32MP157 is not set # CONFIG_PINCTRL_TI_IODELAY is not set CONFIG_PINCTRL_UNIPHIER=y CONFIG_PINCTRL_UNIPHIER_LD4=y CONFIG_PINCTRL_UNIPHIER_PRO4=y CONFIG_PINCTRL_UNIPHIER_SLD8=y CONFIG_PINCTRL_UNIPHIER_PRO5=y CONFIG_PINCTRL_UNIPHIER_PXS2=y CONFIG_PINCTRL_UNIPHIER_LD6B=y # CONFIG_PINCTRL_UNIPHIER_LD11 is not set # CONFIG_PINCTRL_UNIPHIER_LD20 is not set # CONFIG_PINCTRL_UNIPHIER_PXS3 is not set # CONFIG_PINCTRL_UNIPHIER_NX1 is not set # CONFIG_PINCTRL_TMPV7700 is not set CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIOLIB_IRQCHIP=y CONFIG_DEBUG_GPIO=y # CONFIG_GPIO_SYSFS is not set CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y # # Memory mapped GPIO drivers # CONFIG_GPIO_74XX_MMIO=y # CONFIG_GPIO_ALTERA is not set # CONFIG_GPIO_ASPEED is not set # CONFIG_GPIO_ASPEED_SGPIO is not set # CONFIG_GPIO_ATH79 is not set # CONFIG_GPIO_RASPBERRYPI_EXP is not set # CONFIG_GPIO_BCM_KONA is not set # CONFIG_GPIO_BCM_XGS_IPROC is not set # CONFIG_GPIO_BRCMSTB is not set CONFIG_GPIO_CADENCE=m # CONFIG_GPIO_CLPS711X is not set # CONFIG_GPIO_DWAPB is not set # CONFIG_GPIO_EIC_SPRD is not set # CONFIG_GPIO_EM is not set # CONFIG_GPIO_FTGPIO010 is not set CONFIG_GPIO_GENERIC_PLATFORM=y # CONFIG_GPIO_GRGPIO is not set # CONFIG_GPIO_HISI is not set CONFIG_GPIO_HLWD=y CONFIG_GPIO_IMX_SCU=y # CONFIG_GPIO_IOP is not set CONFIG_GPIO_LOGICVC=m # CONFIG_GPIO_LPC18XX is not set # CONFIG_GPIO_LPC32XX is not set # CONFIG_GPIO_MB86S7X is not set CONFIG_GPIO_MENZ127=y CONFIG_GPIO_MPC8XXX=y # CONFIG_GPIO_MT7621 is not set CONFIG_GPIO_MXC=y # CONFIG_GPIO_MXS is not set # CONFIG_GPIO_OMAP is not set # CONFIG_GPIO_PL061 is not set # CONFIG_GPIO_PMIC_EIC_SPRD is not set # CONFIG_GPIO_PXA is not set # CONFIG_GPIO_RCAR is not set # CONFIG_GPIO_RDA is not set # CONFIG_GPIO_ROCKCHIP is not set # CONFIG_GPIO_SAMA5D2_PIOBU is not set CONFIG_GPIO_SIFIVE=y CONFIG_GPIO_SIOX=m # CONFIG_GPIO_SNPS_CREG is not set # CONFIG_GPIO_SPRD is not set # CONFIG_GPIO_STP_XWAY is not set CONFIG_GPIO_SYSCON=y # CONFIG_GPIO_TEGRA is not set # CONFIG_GPIO_TEGRA186 is not set # CONFIG_GPIO_TS4800 is not set # CONFIG_GPIO_UNIPHIER is not set CONFIG_GPIO_VF610=y # CONFIG_GPIO_VISCONTI is not set # CONFIG_GPIO_XGENE_SB is not set CONFIG_GPIO_XILINX=y # CONFIG_GPIO_XLP is not set CONFIG_GPIO_ZEVIO=y CONFIG_GPIO_AMD_FCH=y # CONFIG_GPIO_IDT3243X is not set # end of Memory mapped GPIO drivers # # I2C GPIO expanders # CONFIG_GPIO_ADNP=m CONFIG_GPIO_GW_PLD=m # CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set CONFIG_GPIO_PCA953X=m CONFIG_GPIO_PCA953X_IRQ=y # CONFIG_GPIO_PCA9570 is not set CONFIG_GPIO_PCF857X=m CONFIG_GPIO_TPIC2810=m # CONFIG_GPIO_TS4900 is not set # end of I2C GPIO expanders # # MFD GPIO expanders # CONFIG_GPIO_ARIZONA=m CONFIG_GPIO_DLN2=m CONFIG_HTC_EGPIO=y CONFIG_GPIO_KEMPLD=m CONFIG_GPIO_LP3943=m # CONFIG_GPIO_LP87565 is not set CONFIG_GPIO_MADERA=m CONFIG_GPIO_MAX77650=m # CONFIG_GPIO_SL28CPLD is not set # CONFIG_GPIO_TPS65086 is not set CONFIG_GPIO_TPS65218=m CONFIG_GPIO_TPS65912=m # end of MFD GPIO expanders # # SPI GPIO expanders # CONFIG_GPIO_74X164=y CONFIG_GPIO_MAX3191X=y # CONFIG_GPIO_MAX7301 is not set CONFIG_GPIO_MC33880=y # CONFIG_GPIO_PISOSR is not set CONFIG_GPIO_XRA1403=m CONFIG_GPIO_MOXTET=m # end of SPI GPIO expanders # # USB GPIO expanders # CONFIG_GPIO_VIPERBOARD=m # end of USB GPIO expanders # # Virtual GPIO drivers # CONFIG_GPIO_AGGREGATOR=y CONFIG_GPIO_MOCKUP=m CONFIG_GPIO_VIRTIO=m CONFIG_GPIO_SIM=y # end of Virtual GPIO drivers CONFIG_W1=m # # 1-wire Bus Masters # CONFIG_W1_MASTER_DS2490=m # CONFIG_W1_MASTER_DS2482 is not set # CONFIG_W1_MASTER_MXC is not set CONFIG_W1_MASTER_DS1WM=m CONFIG_W1_MASTER_GPIO=m CONFIG_W1_MASTER_SGI=m # end of 1-wire Bus Masters # # 1-wire Slaves # CONFIG_W1_SLAVE_THERM=m CONFIG_W1_SLAVE_SMEM=m # CONFIG_W1_SLAVE_DS2405 is not set # CONFIG_W1_SLAVE_DS2408 is not set CONFIG_W1_SLAVE_DS2413=m CONFIG_W1_SLAVE_DS2406=m CONFIG_W1_SLAVE_DS2423=m CONFIG_W1_SLAVE_DS2805=m # CONFIG_W1_SLAVE_DS2430 is not set # CONFIG_W1_SLAVE_DS2431 is not set CONFIG_W1_SLAVE_DS2433=m CONFIG_W1_SLAVE_DS2433_CRC=y # CONFIG_W1_SLAVE_DS2438 is not set CONFIG_W1_SLAVE_DS250X=m # CONFIG_W1_SLAVE_DS2780 is not set CONFIG_W1_SLAVE_DS2781=m # CONFIG_W1_SLAVE_DS28E04 is not set # CONFIG_W1_SLAVE_DS28E17 is not set # end of 1-wire Slaves # CONFIG_POWER_RESET is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_PDA_POWER=m CONFIG_APM_POWER=m CONFIG_GENERIC_ADC_BATTERY=m CONFIG_IP5XXX_POWER=m CONFIG_TEST_POWER=m CONFIG_CHARGER_ADP5061=m # CONFIG_BATTERY_ACT8945A is not set CONFIG_BATTERY_CW2015=m CONFIG_BATTERY_DS2760=m # CONFIG_BATTERY_DS2780 is not set CONFIG_BATTERY_DS2781=m CONFIG_BATTERY_DS2782=m # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set CONFIG_BATTERY_SBS=m # CONFIG_CHARGER_SBS is not set CONFIG_BATTERY_BQ27XXX=y CONFIG_BATTERY_BQ27XXX_I2C=m CONFIG_BATTERY_BQ27XXX_HDQ=m # CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set CONFIG_CHARGER_DA9150=m # CONFIG_BATTERY_DA9150 is not set CONFIG_CHARGER_AXP20X=m # CONFIG_BATTERY_AXP20X is not set CONFIG_AXP20X_POWER=m CONFIG_BATTERY_MAX17040=m CONFIG_BATTERY_MAX17042=m CONFIG_BATTERY_MAX1721X=m CONFIG_CHARGER_PCF50633=m # CONFIG_CHARGER_ISP1704 is not set CONFIG_CHARGER_MAX8903=y CONFIG_CHARGER_LP8727=m CONFIG_CHARGER_GPIO=m # CONFIG_CHARGER_MANAGER is not set CONFIG_CHARGER_LT3651=y CONFIG_CHARGER_LTC4162L=m CONFIG_CHARGER_MAX14577=m # CONFIG_CHARGER_DETECTOR_MAX14656 is not set CONFIG_CHARGER_MAX77650=m CONFIG_CHARGER_MAX77693=m CONFIG_CHARGER_MAX77976=m CONFIG_CHARGER_MP2629=m CONFIG_CHARGER_MT6360=m CONFIG_CHARGER_MT6370=m # CONFIG_CHARGER_QCOM_SMBB is not set # CONFIG_CHARGER_BQ2415X is not set CONFIG_CHARGER_BQ24190=m CONFIG_CHARGER_BQ24257=m CONFIG_CHARGER_BQ24735=m CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ25890=m CONFIG_CHARGER_BQ25980=m # CONFIG_CHARGER_BQ256XX is not set CONFIG_CHARGER_SMB347=m # CONFIG_CHARGER_TPS65217 is not set CONFIG_BATTERY_GAUGE_LTC2941=m CONFIG_BATTERY_GOLDFISH=m CONFIG_BATTERY_RT5033=m # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_SC2731 is not set # CONFIG_FUEL_GAUGE_SC27XX is not set CONFIG_CHARGER_UCS1002=m # CONFIG_CHARGER_BD99954 is not set CONFIG_RN5T618_POWER=m # CONFIG_BATTERY_UG3105 is not set CONFIG_HWMON=y CONFIG_HWMON_VID=y CONFIG_HWMON_DEBUG_CHIP=y # # Native drivers # # CONFIG_SENSORS_AD7314 is not set CONFIG_SENSORS_AD7414=m CONFIG_SENSORS_AD7418=m CONFIG_SENSORS_ADM1021=m CONFIG_SENSORS_ADM1025=m CONFIG_SENSORS_ADM1026=m # CONFIG_SENSORS_ADM1029 is not set CONFIG_SENSORS_ADM1031=m CONFIG_SENSORS_ADM1177=m CONFIG_SENSORS_ADM9240=m CONFIG_SENSORS_ADT7X10=y CONFIG_SENSORS_ADT7310=y CONFIG_SENSORS_ADT7410=m # CONFIG_SENSORS_ADT7411 is not set CONFIG_SENSORS_ADT7462=m CONFIG_SENSORS_ADT7470=m # CONFIG_SENSORS_ADT7475 is not set CONFIG_SENSORS_AHT10=m # CONFIG_SENSORS_AS370 is not set CONFIG_SENSORS_ASC7621=m CONFIG_SENSORS_AXI_FAN_CONTROL=y # CONFIG_SENSORS_ASB100 is not set # CONFIG_SENSORS_ASPEED is not set CONFIG_SENSORS_ATXP1=m # CONFIG_SENSORS_BT1_PVT is not set CONFIG_SENSORS_DS620=m CONFIG_SENSORS_DS1621=m # CONFIG_SENSORS_SPARX5 is not set CONFIG_SENSORS_F71805F=y # CONFIG_SENSORS_F71882FG is not set CONFIG_SENSORS_F75375S=m CONFIG_SENSORS_GSC=m # CONFIG_SENSORS_MC13783_ADC is not set # CONFIG_SENSORS_FSCHMD is not set # CONFIG_SENSORS_FTSTEUTATES is not set # CONFIG_SENSORS_GL518SM is not set CONFIG_SENSORS_GL520SM=m CONFIG_SENSORS_G760A=m CONFIG_SENSORS_G762=m CONFIG_SENSORS_GPIO_FAN=m CONFIG_SENSORS_HIH6130=m # CONFIG_SENSORS_IBMAEM is not set # CONFIG_SENSORS_IBMPEX is not set CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_JC42 is not set # CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LAN966X is not set CONFIG_SENSORS_LINEAGE=m # CONFIG_SENSORS_LTC2945 is not set CONFIG_SENSORS_LTC2947=m CONFIG_SENSORS_LTC2947_I2C=m # CONFIG_SENSORS_LTC2947_SPI is not set CONFIG_SENSORS_LTC2990=m # CONFIG_SENSORS_LTC2992 is not set CONFIG_SENSORS_LTC4151=m CONFIG_SENSORS_LTC4215=m # CONFIG_SENSORS_LTC4222 is not set CONFIG_SENSORS_LTC4245=m # CONFIG_SENSORS_LTC4260 is not set CONFIG_SENSORS_LTC4261=m # CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set CONFIG_SENSORS_MAX1619=m CONFIG_SENSORS_MAX1668=m CONFIG_SENSORS_MAX197=m CONFIG_SENSORS_MAX31722=m CONFIG_SENSORS_MAX31730=m # CONFIG_SENSORS_MAX31760 is not set CONFIG_SENSORS_MAX6620=m # CONFIG_SENSORS_MAX6621 is not set CONFIG_SENSORS_MAX6639=m CONFIG_SENSORS_MAX6642=m # CONFIG_SENSORS_MAX6650 is not set CONFIG_SENSORS_MAX6697=m CONFIG_SENSORS_MAX31790=m CONFIG_SENSORS_MCP3021=m # CONFIG_SENSORS_MLXREG_FAN is not set CONFIG_SENSORS_TC654=m # CONFIG_SENSORS_TPS23861 is not set CONFIG_SENSORS_MR75203=y CONFIG_SENSORS_ADCXX=y CONFIG_SENSORS_LM63=m CONFIG_SENSORS_LM70=y CONFIG_SENSORS_LM73=m # CONFIG_SENSORS_LM75 is not set # CONFIG_SENSORS_LM77 is not set CONFIG_SENSORS_LM78=m CONFIG_SENSORS_LM80=m # CONFIG_SENSORS_LM83 is not set CONFIG_SENSORS_LM85=m CONFIG_SENSORS_LM87=m # CONFIG_SENSORS_LM90 is not set CONFIG_SENSORS_LM92=m CONFIG_SENSORS_LM93=m # CONFIG_SENSORS_LM95234 is not set # CONFIG_SENSORS_LM95241 is not set CONFIG_SENSORS_LM95245=m CONFIG_SENSORS_PC87360=y CONFIG_SENSORS_PC87427=y CONFIG_SENSORS_NTC_THERMISTOR=m # CONFIG_SENSORS_NCT6683 is not set CONFIG_SENSORS_NCT6775_CORE=m # CONFIG_SENSORS_NCT6775 is not set CONFIG_SENSORS_NCT6775_I2C=m CONFIG_SENSORS_NCT7802=m CONFIG_SENSORS_NCT7904=m CONFIG_SENSORS_NPCM7XX=m # CONFIG_SENSORS_NSA320 is not set CONFIG_SENSORS_OCC_P8_I2C=m CONFIG_SENSORS_OCC=m CONFIG_SENSORS_PCF8591=m # CONFIG_SENSORS_PECI_CPUTEMP is not set # CONFIG_SENSORS_PECI_DIMMTEMP is not set # CONFIG_PMBUS is not set # CONFIG_SENSORS_PWM_FAN is not set # CONFIG_SENSORS_RASPBERRYPI_HWMON is not set # CONFIG_SENSORS_SL28CPLD is not set # CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SBRMI is not set # CONFIG_SENSORS_SHT15 is not set CONFIG_SENSORS_SHT21=m CONFIG_SENSORS_SHT3x=m # CONFIG_SENSORS_SHT4x is not set # CONFIG_SENSORS_SHTC1 is not set CONFIG_SENSORS_SY7636A=m CONFIG_SENSORS_DME1737=m # CONFIG_SENSORS_EMC1403 is not set CONFIG_SENSORS_EMC2103=m CONFIG_SENSORS_EMC2305=m CONFIG_SENSORS_EMC6W201=m # CONFIG_SENSORS_SMSC47M1 is not set CONFIG_SENSORS_SMSC47M192=m # CONFIG_SENSORS_SMSC47B397 is not set CONFIG_SENSORS_SCH56XX_COMMON=y CONFIG_SENSORS_SCH5627=y CONFIG_SENSORS_SCH5636=y CONFIG_SENSORS_STTS751=m CONFIG_SENSORS_SMM665=m # CONFIG_SENSORS_ADC128D818 is not set CONFIG_SENSORS_ADS7828=m CONFIG_SENSORS_ADS7871=y CONFIG_SENSORS_AMC6821=m CONFIG_SENSORS_INA209=m CONFIG_SENSORS_INA2XX=m # CONFIG_SENSORS_INA238 is not set CONFIG_SENSORS_INA3221=m CONFIG_SENSORS_TC74=m CONFIG_SENSORS_THMC50=m CONFIG_SENSORS_TMP102=m CONFIG_SENSORS_TMP103=m # CONFIG_SENSORS_TMP108 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set CONFIG_SENSORS_TMP464=m CONFIG_SENSORS_TMP513=m CONFIG_SENSORS_VEXPRESS=m CONFIG_SENSORS_VT1211=y # CONFIG_SENSORS_W83773G is not set # CONFIG_SENSORS_W83781D is not set CONFIG_SENSORS_W83791D=m CONFIG_SENSORS_W83792D=m CONFIG_SENSORS_W83793=m CONFIG_SENSORS_W83795=m CONFIG_SENSORS_W83795_FANCTRL=y # CONFIG_SENSORS_W83L785TS is not set CONFIG_SENSORS_W83L786NG=m # CONFIG_SENSORS_W83627HF is not set CONFIG_SENSORS_W83627EHF=y # CONFIG_THERMAL is not set CONFIG_WATCHDOG=y CONFIG_WATCHDOG_CORE=y CONFIG_WATCHDOG_NOWAYOUT=y CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set # CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set # # Watchdog Pretimeout Governors # # CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set # # Watchdog Device Drivers # CONFIG_SOFT_WATCHDOG=m # CONFIG_DA9052_WATCHDOG is not set # CONFIG_DA9055_WATCHDOG is not set CONFIG_DA9063_WATCHDOG=m CONFIG_DA9062_WATCHDOG=m CONFIG_GPIO_WATCHDOG=y CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y # CONFIG_MENF21BMC_WATCHDOG is not set CONFIG_MENZ069_WATCHDOG=m # CONFIG_XILINX_WATCHDOG is not set CONFIG_ZIIRAVE_WATCHDOG=m # CONFIG_MLX_WDT is not set # CONFIG_SL28CPLD_WATCHDOG is not set CONFIG_ARM_SP805_WATCHDOG=y # CONFIG_ARMADA_37XX_WATCHDOG is not set # CONFIG_ASM9260_WATCHDOG is not set # CONFIG_AT91RM9200_WATCHDOG is not set CONFIG_AT91SAM9X_WATCHDOG=m CONFIG_SAMA5D4_WATCHDOG=m # CONFIG_CADENCE_WATCHDOG is not set # CONFIG_977_WATCHDOG is not set CONFIG_FTWDT010_WATCHDOG=m # CONFIG_S3C2410_WATCHDOG is not set CONFIG_DW_WATCHDOG=y # CONFIG_EP93XX_WATCHDOG is not set # CONFIG_OMAP_WATCHDOG is not set # CONFIG_PNX4008_WATCHDOG is not set # CONFIG_DAVINCI_WATCHDOG is not set # CONFIG_K3_RTI_WATCHDOG is not set # CONFIG_ORION_WATCHDOG is not set # CONFIG_RN5T618_WATCHDOG is not set # CONFIG_SUNXI_WATCHDOG is not set # CONFIG_NPCM7XX_WATCHDOG is not set # CONFIG_STMP3XXX_RTC_WATCHDOG is not set # CONFIG_TS4800_WATCHDOG is not set # CONFIG_TS72XX_WATCHDOG is not set # CONFIG_MAX63XX_WATCHDOG is not set # CONFIG_MAX77620_WATCHDOG is not set # CONFIG_IMX2_WDT is not set # CONFIG_IMX7ULP_WDT is not set # CONFIG_RETU_WATCHDOG is not set # CONFIG_MOXART_WDT is not set # CONFIG_ST_LPC_WATCHDOG is not set # CONFIG_TEGRA_WATCHDOG is not set # CONFIG_QCOM_WDT is not set # CONFIG_MESON_GXBB_WATCHDOG is not set # CONFIG_MESON_WATCHDOG is not set # CONFIG_MEDIATEK_WATCHDOG is not set # CONFIG_DIGICOLOR_WATCHDOG is not set # CONFIG_LPC18XX_WATCHDOG is not set # CONFIG_RENESAS_WDT is not set # CONFIG_RENESAS_RZAWDT is not set # CONFIG_RENESAS_RZN1WDT is not set # CONFIG_RENESAS_RZG2LWDT is not set # CONFIG_ASPEED_WATCHDOG is not set # CONFIG_UNIPHIER_WATCHDOG is not set # CONFIG_RTD119X_WATCHDOG is not set # CONFIG_REALTEK_OTTO_WDT is not set # CONFIG_SPRD_WATCHDOG is not set # CONFIG_VISCONTI_WATCHDOG is not set # CONFIG_MSC313E_WATCHDOG is not set # CONFIG_APPLE_WATCHDOG is not set # CONFIG_SUNPLUS_WATCHDOG is not set # CONFIG_SC520_WDT is not set CONFIG_KEMPLD_WDT=y # CONFIG_ATH79_WDT is not set # CONFIG_BCM47XX_WDT is not set # CONFIG_BCM2835_WDT is not set # CONFIG_BCM_KONA_WDT is not set # CONFIG_BCM7038_WDT is not set # CONFIG_IMGPDC_WDT is not set # CONFIG_MPC5200_WDT is not set CONFIG_MEN_A21_WDT=y # CONFIG_UML_WATCHDOG is not set # # USB-based Watchdog Cards # # CONFIG_USBPCWATCHDOG is not set CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set CONFIG_BCMA_POSSIBLE=y # CONFIG_BCMA is not set # # Multifunction device drivers # CONFIG_MFD_CORE=y CONFIG_MFD_ACT8945A=m # CONFIG_MFD_SUN4I_GPADC is not set CONFIG_MFD_AT91_USART=y CONFIG_MFD_ATMEL_FLEXCOM=y # CONFIG_MFD_ATMEL_HLCDC is not set CONFIG_MFD_ATMEL_SMC=y CONFIG_MFD_BCM590XX=m # CONFIG_MFD_BD9571MWV is not set CONFIG_MFD_AXP20X=m CONFIG_MFD_AXP20X_I2C=m CONFIG_MFD_MADERA=m # CONFIG_MFD_MADERA_I2C is not set CONFIG_MFD_MADERA_SPI=m CONFIG_MFD_CS47L15=y # CONFIG_MFD_CS47L35 is not set CONFIG_MFD_CS47L85=y # CONFIG_MFD_CS47L90 is not set # CONFIG_MFD_CS47L92 is not set CONFIG_MFD_CS48L32=y # CONFIG_MFD_ASIC3 is not set # CONFIG_MFD_DA9052_SPI is not set CONFIG_MFD_DA9062=m CONFIG_MFD_DA9063=m CONFIG_MFD_DA9150=m CONFIG_MFD_DLN2=m # CONFIG_MFD_ENE_KB3930 is not set # CONFIG_MFD_EXYNOS_LPASS is not set CONFIG_MFD_GATEWORKS_GSC=m CONFIG_MFD_MC13XXX=m CONFIG_MFD_MC13XXX_SPI=m # CONFIG_MFD_MC13XXX_I2C is not set CONFIG_MFD_MP2629=m # CONFIG_MFD_MXS_LRADC is not set # CONFIG_MFD_MX25_TSADC is not set # CONFIG_MFD_HI6421_PMIC is not set CONFIG_MFD_HI6421_SPMI=m # CONFIG_MFD_HI655X_PMIC is not set CONFIG_HTC_PASIC3=m CONFIG_MFD_IQS62X=m CONFIG_MFD_KEMPLD=y CONFIG_MFD_88PM800=m # CONFIG_MFD_88PM805 is not set CONFIG_MFD_MAX14577=m CONFIG_MFD_MAX77650=m CONFIG_MFD_MAX77686=m CONFIG_MFD_MAX77693=m CONFIG_MFD_MAX77714=m CONFIG_MFD_MAX8907=m CONFIG_MFD_MT6360=m CONFIG_MFD_MT6370=m CONFIG_MFD_MT6397=m # CONFIG_MFD_MENF21BMC is not set CONFIG_MFD_OCELOT=m CONFIG_EZX_PCAP=y # CONFIG_MFD_CPCAP is not set CONFIG_MFD_VIPERBOARD=y CONFIG_MFD_NTXEC=m CONFIG_MFD_RETU=m CONFIG_MFD_PCF50633=m CONFIG_PCF50633_ADC=m CONFIG_PCF50633_GPIO=m # CONFIG_MFD_PM8XXX is not set # CONFIG_MFD_SPMI_PMIC is not set CONFIG_MFD_SY7636A=m # CONFIG_MFD_RT4831 is not set # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RT5120 is not set # CONFIG_MFD_RK808 is not set CONFIG_MFD_RN5T618=m CONFIG_MFD_SI476X_CORE=m CONFIG_MFD_SIMPLE_MFD_I2C=m # CONFIG_MFD_SL28CPLD is not set CONFIG_MFD_SM501=y # CONFIG_MFD_SM501_GPIO is not set # CONFIG_MFD_SKY81452 is not set # CONFIG_MFD_SC27XX_PMIC is not set # CONFIG_ABX500_CORE is not set # CONFIG_MFD_STMPE is not set # CONFIG_MFD_SUN6I_PRCM is not set CONFIG_MFD_SYSCON=y # CONFIG_MFD_TI_AM335X_TSCADC is not set CONFIG_MFD_LP3943=m CONFIG_MFD_TI_LMU=m # CONFIG_TPS6105X is not set CONFIG_TPS65010=m # CONFIG_TPS6507X is not set CONFIG_MFD_TPS65086=m CONFIG_MFD_TPS65217=m # CONFIG_MFD_TI_LP873X is not set CONFIG_MFD_TI_LP87565=m CONFIG_MFD_TPS65218=m CONFIG_MFD_TPS65912=m CONFIG_MFD_TPS65912_I2C=m # CONFIG_MFD_TPS65912_SPI is not set CONFIG_MFD_WL1273_CORE=m CONFIG_MFD_LM3533=m CONFIG_MFD_TMIO=y CONFIG_MFD_T7L66XB=y # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set CONFIG_MFD_TQMX86=y CONFIG_MFD_ARIZONA=m CONFIG_MFD_ARIZONA_I2C=m # CONFIG_MFD_ARIZONA_SPI is not set CONFIG_MFD_CS47L24=y # CONFIG_MFD_WM5102 is not set # CONFIG_MFD_WM5110 is not set CONFIG_MFD_WM8997=y # CONFIG_MFD_WM8998 is not set # CONFIG_MFD_WM831X_SPI is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_STW481X is not set # CONFIG_MFD_STM32_LPTIMER is not set # CONFIG_MFD_STM32_TIMERS is not set CONFIG_MFD_STMFX=m # CONFIG_MFD_ATC260X_I2C is not set # CONFIG_MFD_KHADAS_MCU is not set # CONFIG_MFD_ACER_A500_EC is not set # CONFIG_MFD_QCOM_PM8008 is not set # CONFIG_MFD_VEXPRESS_SYSREG is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set CONFIG_MFD_RSMU_I2C=m CONFIG_MFD_RSMU_SPI=y # end of Multifunction device drivers CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_VIRTUAL_CONSUMER=y # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set CONFIG_REGULATOR_88PG86X=m CONFIG_REGULATOR_88PM800=m # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_ACT8945A is not set # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_ANATOP=m CONFIG_REGULATOR_AXP20X=m CONFIG_REGULATOR_BCM590XX=m # CONFIG_REGULATOR_DA9062 is not set CONFIG_REGULATOR_DA9063=m CONFIG_REGULATOR_DA9121=m CONFIG_REGULATOR_DA9210=m CONFIG_REGULATOR_DA9211=m # CONFIG_REGULATOR_FAN53555 is not set CONFIG_REGULATOR_FAN53880=m CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_HI6421V600=m CONFIG_REGULATOR_ISL9305=m CONFIG_REGULATOR_ISL6271A=m CONFIG_REGULATOR_LM363X=m CONFIG_REGULATOR_LP3971=m CONFIG_REGULATOR_LP3972=m # CONFIG_REGULATOR_LP872X is not set CONFIG_REGULATOR_LP8755=m CONFIG_REGULATOR_LP87565=m # CONFIG_REGULATOR_LTC3589 is not set CONFIG_REGULATOR_LTC3676=m CONFIG_REGULATOR_MAX14577=m CONFIG_REGULATOR_MAX1586=m # CONFIG_REGULATOR_MAX77620 is not set # CONFIG_REGULATOR_MAX77650 is not set # CONFIG_REGULATOR_MAX8649 is not set CONFIG_REGULATOR_MAX8660=m # CONFIG_REGULATOR_MAX8893 is not set CONFIG_REGULATOR_MAX8907=m # CONFIG_REGULATOR_MAX8952 is not set CONFIG_REGULATOR_MAX20086=m CONFIG_REGULATOR_MAX77686=m CONFIG_REGULATOR_MAX77693=m CONFIG_REGULATOR_MAX77802=m # CONFIG_REGULATOR_MAX77826 is not set CONFIG_REGULATOR_MC13XXX_CORE=m CONFIG_REGULATOR_MC13783=m CONFIG_REGULATOR_MC13892=m # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MP5416 is not set # CONFIG_REGULATOR_MP8859 is not set # CONFIG_REGULATOR_MP886X is not set CONFIG_REGULATOR_MPQ7920=m CONFIG_REGULATOR_MT6311=m # CONFIG_REGULATOR_MT6315 is not set # CONFIG_REGULATOR_MT6323 is not set # CONFIG_REGULATOR_MT6331 is not set CONFIG_REGULATOR_MT6332=m CONFIG_REGULATOR_MT6358=m CONFIG_REGULATOR_MT6359=m CONFIG_REGULATOR_MT6360=m # CONFIG_REGULATOR_MT6370 is not set CONFIG_REGULATOR_MT6397=m # CONFIG_REGULATOR_PBIAS is not set # CONFIG_REGULATOR_PCA9450 is not set CONFIG_REGULATOR_PCAP=y # CONFIG_REGULATOR_PCF50633 is not set CONFIG_REGULATOR_PF8X00=m CONFIG_REGULATOR_PFUZE100=m CONFIG_REGULATOR_PV88060=m CONFIG_REGULATOR_PV88080=m CONFIG_REGULATOR_PV88090=m # CONFIG_REGULATOR_PWM is not set # CONFIG_REGULATOR_QCOM_RPMH is not set CONFIG_REGULATOR_QCOM_SPMI=m # CONFIG_REGULATOR_QCOM_USB_VBUS is not set CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m CONFIG_REGULATOR_RN5T618=m CONFIG_REGULATOR_RT4801=m CONFIG_REGULATOR_RT5190A=m # CONFIG_REGULATOR_RT5759 is not set CONFIG_REGULATOR_RT6160=m CONFIG_REGULATOR_RT6245=m CONFIG_REGULATOR_RTQ2134=m CONFIG_REGULATOR_RTMV20=m CONFIG_REGULATOR_RTQ6752=m # CONFIG_REGULATOR_S2MPA01 is not set # CONFIG_REGULATOR_S2MPS11 is not set # CONFIG_REGULATOR_S5M8767 is not set # CONFIG_REGULATOR_SC2731 is not set CONFIG_REGULATOR_SLG51000=m # CONFIG_REGULATOR_STM32_BOOSTER is not set # CONFIG_REGULATOR_STM32_VREFBUF is not set # CONFIG_REGULATOR_STM32_PWR is not set # CONFIG_REGULATOR_TI_ABB is not set # CONFIG_REGULATOR_STW481X_VMMC is not set CONFIG_REGULATOR_SY7636A=m CONFIG_REGULATOR_SY8106A=m # CONFIG_REGULATOR_SY8824X is not set CONFIG_REGULATOR_SY8827N=m CONFIG_REGULATOR_TPS51632=m # CONFIG_REGULATOR_TPS62360 is not set CONFIG_REGULATOR_TPS6286X=m CONFIG_REGULATOR_TPS65023=m CONFIG_REGULATOR_TPS6507X=m CONFIG_REGULATOR_TPS65086=m CONFIG_REGULATOR_TPS65132=m # CONFIG_REGULATOR_TPS65217 is not set CONFIG_REGULATOR_TPS65218=m CONFIG_REGULATOR_TPS6524X=m # CONFIG_REGULATOR_TPS65912 is not set # CONFIG_REGULATOR_TPS68470 is not set # CONFIG_REGULATOR_UNIPHIER is not set CONFIG_REGULATOR_VCTRL=y # CONFIG_REGULATOR_VEXPRESS is not set # CONFIG_REGULATOR_QCOM_LABIBB is not set CONFIG_CEC_CORE=y CONFIG_CEC_NOTIFIER=y CONFIG_CEC_PIN=y # # CEC support # # CONFIG_CEC_PIN_ERROR_INJ is not set CONFIG_MEDIA_CEC_SUPPORT=y CONFIG_CEC_CH7322=m # CONFIG_CEC_MESON_AO is not set # CONFIG_CEC_MESON_G12A_AO is not set CONFIG_CEC_GPIO=y # CONFIG_CEC_SAMSUNG_S5P is not set # CONFIG_CEC_STI is not set # CONFIG_CEC_STM32 is not set # CONFIG_CEC_TEGRA is not set CONFIG_USB_PULSE8_CEC=y CONFIG_USB_RAINSHADOW_CEC=y # end of CEC support # CONFIG_MEDIA_SUPPORT is not set # # Graphics support # # CONFIG_TEGRA_HOST1X is not set # CONFIG_IMX_IPUV3_CORE is not set # CONFIG_DRM is not set # CONFIG_DRM_DEBUG_MODESET_LOCK is not set # # ARM devices # # end of ARM devices # # Frame buffer Devices # CONFIG_FB_CMDLINE=y CONFIG_FB_NOTIFY=y CONFIG_FB=m CONFIG_FIRMWARE_EDID=y CONFIG_FB_CFB_FILLRECT=m CONFIG_FB_CFB_COPYAREA=m CONFIG_FB_CFB_IMAGEBLIT=m CONFIG_FB_SYS_FILLRECT=m CONFIG_FB_SYS_COPYAREA=m CONFIG_FB_SYS_IMAGEBLIT=m # CONFIG_FB_FOREIGN_ENDIAN is not set CONFIG_FB_SYS_FOPS=m CONFIG_FB_DEFERRED_IO=y CONFIG_FB_BACKLIGHT=m CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y # # Frame buffer hardware drivers # CONFIG_FB_ARMCLCD=m # CONFIG_FB_CLPS711X is not set CONFIG_FB_IMX=m # CONFIG_FB_ARC is not set # CONFIG_FB_PVR2 is not set CONFIG_FB_OPENCORES=m CONFIG_FB_S1D13XXX=m # CONFIG_FB_ATMEL is not set # CONFIG_FB_PXA168 is not set # CONFIG_FB_W100 is not set # CONFIG_FB_SH_MOBILE_LCDC is not set CONFIG_FB_TMIO=m CONFIG_FB_TMIO_ACCELL=y # CONFIG_FB_S3C is not set CONFIG_FB_SM501=m CONFIG_FB_SMSCUFX=m # CONFIG_FB_UDL is not set CONFIG_FB_IBM_GXT4500=m # CONFIG_FB_GOLDFISH is not set # CONFIG_FB_DA8XX is not set CONFIG_FB_VIRTUAL=m # CONFIG_FB_METRONOME is not set # CONFIG_FB_BROADSHEET is not set # CONFIG_FB_SIMPLE is not set # CONFIG_FB_SSD1307 is not set # CONFIG_FB_OMAP is not set # CONFIG_FB_OMAP2 is not set # CONFIG_MMP_DISP is not set # end of Frame buffer Devices # # Backlight & LCD device support # CONFIG_LCD_CLASS_DEVICE=y # CONFIG_LCD_L4F00242T03 is not set CONFIG_LCD_LMS283GF05=y CONFIG_LCD_LTV350QV=y # CONFIG_LCD_ILI922X is not set CONFIG_LCD_ILI9320=y CONFIG_LCD_TDO24M=m CONFIG_LCD_VGG2432A4=y CONFIG_LCD_PLATFORM=y CONFIG_LCD_AMS369FG06=m CONFIG_LCD_LMS501KF03=m # CONFIG_LCD_HX8357 is not set # CONFIG_LCD_OTM3225A is not set CONFIG_BACKLIGHT_CLASS_DEVICE=m # CONFIG_BACKLIGHT_KTD253 is not set CONFIG_BACKLIGHT_LM3533=m # CONFIG_BACKLIGHT_OMAP1 is not set CONFIG_BACKLIGHT_PWM=m CONFIG_BACKLIGHT_MT6370=m CONFIG_BACKLIGHT_QCOM_WLED=m CONFIG_BACKLIGHT_ADP8860=m CONFIG_BACKLIGHT_ADP8870=m CONFIG_BACKLIGHT_PCF50633=m CONFIG_BACKLIGHT_LM3630A=m # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m CONFIG_BACKLIGHT_TPS65217=m CONFIG_BACKLIGHT_GPIO=m # CONFIG_BACKLIGHT_LV5207LP is not set CONFIG_BACKLIGHT_BD6107=m # CONFIG_BACKLIGHT_ARCXCNN is not set CONFIG_BACKLIGHT_LED=m # end of Backlight & LCD device support CONFIG_VIDEOMODE_HELPERS=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y # end of Graphics support CONFIG_SOUND=y # CONFIG_SND is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=y # CONFIG_USB_LED_TRIG is not set CONFIG_USB_ULPI_BUS=m CONFIG_USB_CONN_GPIO=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options # # CONFIG_USB_DEFAULT_PERSIST is not set # CONFIG_USB_FEW_INIT_RETRIES is not set # CONFIG_USB_DYNAMIC_MINORS is not set CONFIG_USB_OTG=y CONFIG_USB_OTG_PRODUCTLIST=y CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB=y CONFIG_USB_OTG_FSM=y CONFIG_USB_LEDS_TRIGGER_USBPORT=y CONFIG_USB_AUTOSUSPEND_DELAY=2 CONFIG_USB_MON=m # # USB Host Controller Drivers # CONFIG_USB_C67X00_HCD=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DBGCAP=y # CONFIG_USB_XHCI_PCI_RENESAS is not set CONFIG_USB_XHCI_PLATFORM=m # CONFIG_USB_XHCI_HISTB is not set # CONFIG_USB_XHCI_MTK is not set # CONFIG_USB_XHCI_MVEBU is not set # CONFIG_USB_XHCI_RCAR is not set # CONFIG_USB_BRCMSTB is not set CONFIG_USB_EHCI_HCD=m CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_EHCI_FSL=m # CONFIG_USB_EHCI_HCD_NPCM7XX is not set # CONFIG_USB_EHCI_HCD_ORION is not set # CONFIG_USB_EHCI_HCD_SPEAR is not set # CONFIG_USB_EHCI_HCD_STI is not set CONFIG_USB_EHCI_HCD_AT91=m # CONFIG_USB_EHCI_SH is not set # CONFIG_USB_EHCI_EXYNOS is not set # CONFIG_USB_EHCI_MV is not set # CONFIG_USB_CNS3XXX_EHCI is not set # CONFIG_USB_EHCI_HCD_PLATFORM is not set CONFIG_USB_OXU210HP_HCD=y CONFIG_USB_ISP116X_HCD=m # CONFIG_USB_ISP1362_HCD is not set # CONFIG_USB_FOTG210_HCD is not set CONFIG_USB_MAX3421_HCD=m CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_HCD_SPEAR is not set # CONFIG_USB_OHCI_HCD_STI is not set # CONFIG_USB_OHCI_HCD_S3C2410 is not set CONFIG_USB_OHCI_HCD_LPC32XX=m CONFIG_USB_OHCI_HCD_AT91=m # CONFIG_USB_OHCI_HCD_OMAP3 is not set # CONFIG_USB_OHCI_HCD_DAVINCI is not set # CONFIG_USB_OHCI_SH is not set # CONFIG_USB_OHCI_EXYNOS is not set # CONFIG_USB_CNS3XXX_OHCI is not set CONFIG_USB_OHCI_HCD_PLATFORM=y # CONFIG_USB_U132_HCD is not set # CONFIG_USB_SL811_HCD is not set CONFIG_USB_R8A66597_HCD=m CONFIG_USB_HCD_TEST_MODE=y # # USB Device Class drivers # CONFIG_USB_ACM=y # CONFIG_USB_PRINTER is not set CONFIG_USB_WDM=m CONFIG_USB_TMC=m # # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # # also be needed; see USB_STORAGE Help for more info # # # USB Imaging devices # CONFIG_USB_MDC800=m # CONFIG_USBIP_CORE is not set CONFIG_USB_CDNS_SUPPORT=m # CONFIG_USB_CDNS3 is not set # CONFIG_USB_MTU3 is not set CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_HOST=y # # Platform Glue Layer # # CONFIG_USB_MUSB_TUSB6010 is not set # CONFIG_USB_MUSB_DSPS is not set # CONFIG_USB_MUSB_UX500 is not set # # MUSB DMA mode # CONFIG_MUSB_PIO_ONLY=y CONFIG_USB_DWC3=m # CONFIG_USB_DWC3_ULPI is not set CONFIG_USB_DWC3_HOST=y # # Platform Glue Driver Support # CONFIG_USB_DWC3_OMAP=m CONFIG_USB_DWC3_EXYNOS=m CONFIG_USB_DWC3_KEYSTONE=m CONFIG_USB_DWC3_MESON_G12A=m CONFIG_USB_DWC3_OF_SIMPLE=m CONFIG_USB_DWC3_ST=m CONFIG_USB_DWC3_QCOM=m CONFIG_USB_DWC3_IMX8MP=m CONFIG_USB_DWC3_AM62=m # CONFIG_USB_DWC2 is not set CONFIG_USB_CHIPIDEA=m # CONFIG_USB_CHIPIDEA_HOST is not set CONFIG_USB_CHIPIDEA_MSM=m CONFIG_USB_CHIPIDEA_IMX=m # CONFIG_USB_CHIPIDEA_GENERIC is not set # CONFIG_USB_CHIPIDEA_TEGRA is not set CONFIG_USB_ISP1760=y CONFIG_USB_ISP1760_HCD=y CONFIG_USB_ISP1760_HOST_ROLE=y # # USB port drivers # # CONFIG_USB_USS720 is not set CONFIG_USB_SERIAL=y # CONFIG_USB_SERIAL_CONSOLE is not set # CONFIG_USB_SERIAL_GENERIC is not set CONFIG_USB_SERIAL_SIMPLE=m CONFIG_USB_SERIAL_AIRCABLE=m CONFIG_USB_SERIAL_ARK3116=m CONFIG_USB_SERIAL_BELKIN=m CONFIG_USB_SERIAL_CH341=y CONFIG_USB_SERIAL_WHITEHEAT=y CONFIG_USB_SERIAL_DIGI_ACCELEPORT=y CONFIG_USB_SERIAL_CP210X=y CONFIG_USB_SERIAL_CYPRESS_M8=y # CONFIG_USB_SERIAL_EMPEG is not set CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_SERIAL_VISOR=m # CONFIG_USB_SERIAL_IPAQ is not set CONFIG_USB_SERIAL_IR=y CONFIG_USB_SERIAL_EDGEPORT=m CONFIG_USB_SERIAL_EDGEPORT_TI=m CONFIG_USB_SERIAL_F81232=m CONFIG_USB_SERIAL_F8153X=y CONFIG_USB_SERIAL_GARMIN=y CONFIG_USB_SERIAL_IPW=m CONFIG_USB_SERIAL_IUU=m CONFIG_USB_SERIAL_KEYSPAN_PDA=m # CONFIG_USB_SERIAL_KEYSPAN is not set CONFIG_USB_SERIAL_KLSI=y # CONFIG_USB_SERIAL_KOBIL_SCT is not set # CONFIG_USB_SERIAL_MCT_U232 is not set CONFIG_USB_SERIAL_METRO=m # CONFIG_USB_SERIAL_MOS7720 is not set CONFIG_USB_SERIAL_MOS7840=y CONFIG_USB_SERIAL_MXUPORT=y CONFIG_USB_SERIAL_NAVMAN=m # CONFIG_USB_SERIAL_PL2303 is not set CONFIG_USB_SERIAL_OTI6858=m # CONFIG_USB_SERIAL_QCAUX is not set CONFIG_USB_SERIAL_QUALCOMM=m CONFIG_USB_SERIAL_SPCP8X5=y # CONFIG_USB_SERIAL_SAFE is not set # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set CONFIG_USB_SERIAL_SYMBOL=y CONFIG_USB_SERIAL_TI=y CONFIG_USB_SERIAL_CYBERJACK=m CONFIG_USB_SERIAL_WWAN=m # CONFIG_USB_SERIAL_OPTION is not set CONFIG_USB_SERIAL_OMNINET=m # CONFIG_USB_SERIAL_OPTICON is not set CONFIG_USB_SERIAL_XSENS_MT=m CONFIG_USB_SERIAL_WISHBONE=y # CONFIG_USB_SERIAL_SSU100 is not set # CONFIG_USB_SERIAL_QT2 is not set CONFIG_USB_SERIAL_UPD78F0730=m # CONFIG_USB_SERIAL_XR is not set CONFIG_USB_SERIAL_DEBUG=m # # USB Miscellaneous drivers # CONFIG_USB_EMI62=y # CONFIG_USB_EMI26 is not set CONFIG_USB_ADUTUX=y CONFIG_USB_SEVSEG=y CONFIG_USB_LEGOTOWER=y # CONFIG_USB_LCD is not set CONFIG_USB_CYPRESS_CY7C63=m CONFIG_USB_CYTHERM=m # CONFIG_USB_IDMOUSE is not set CONFIG_USB_FTDI_ELAN=y CONFIG_USB_APPLEDISPLAY=m # CONFIG_USB_QCOM_EUD is not set # CONFIG_APPLE_MFI_FASTCHARGE is not set # CONFIG_USB_SISUSBVGA is not set CONFIG_USB_LD=y CONFIG_USB_TRANCEVIBRATOR=m CONFIG_USB_IOWARRIOR=m # CONFIG_USB_TEST is not set CONFIG_USB_EHSET_TEST_FIXTURE=y # CONFIG_USB_ISIGHTFW is not set CONFIG_USB_YUREX=y CONFIG_USB_EZUSB_FX2=y CONFIG_USB_HUB_USB251XB=m CONFIG_USB_HSIC_USB3503=m # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set CONFIG_USB_CHAOSKEY=y # CONFIG_BRCM_USB_PINMAP is not set CONFIG_USB_ONBOARD_HUB=y # # USB Physical Layer drivers # CONFIG_USB_PHY=y # CONFIG_ISP1301_OMAP is not set # CONFIG_NOP_USB_XCEIV is not set # CONFIG_USB_GPIO_VBUS is not set CONFIG_TAHVO_USB=m CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y CONFIG_USB_ISP1301=m # CONFIG_USB_MXS_PHY is not set # CONFIG_USB_TEGRA_PHY is not set # CONFIG_USB_ULPI is not set # CONFIG_JZ4770_PHY is not set # end of USB Physical Layer drivers # CONFIG_USB_GADGET is not set CONFIG_TYPEC=m CONFIG_TYPEC_TCPM=m CONFIG_TYPEC_TCPCI=m CONFIG_TYPEC_RT1711H=m CONFIG_TYPEC_MT6360=m # CONFIG_TYPEC_TCPCI_MT6370 is not set # CONFIG_TYPEC_TCPCI_MAXIM is not set CONFIG_TYPEC_FUSB302=m CONFIG_TYPEC_UCSI=m # CONFIG_UCSI_CCG is not set CONFIG_UCSI_STM32G0=m CONFIG_TYPEC_TPS6598X=m CONFIG_TYPEC_ANX7411=m CONFIG_TYPEC_RT1719=m CONFIG_TYPEC_HD3SS3220=m CONFIG_TYPEC_STUSB160X=m # CONFIG_TYPEC_QCOM_PMIC is not set CONFIG_TYPEC_WUSB3801=m # # USB Type-C Multiplexer/DeMultiplexer Switch support # # CONFIG_TYPEC_MUX_FSA4480 is not set # CONFIG_TYPEC_MUX_PI3USB30532 is not set # end of USB Type-C Multiplexer/DeMultiplexer Switch support # # USB Type-C Alternate Mode drivers # # end of USB Type-C Alternate Mode drivers CONFIG_USB_ROLE_SWITCH=y CONFIG_MMC=m CONFIG_PWRSEQ_EMMC=m # CONFIG_PWRSEQ_SIMPLE is not set CONFIG_SDIO_UART=m # CONFIG_MMC_TEST is not set # # MMC/SD/SDIO Host Controller Drivers # # CONFIG_MMC_DEBUG is not set CONFIG_MMC_ARMMMCI=m # CONFIG_MMC_STM32_SDMMC is not set # CONFIG_MMC_SDHCI is not set # CONFIG_MMC_MESON_GX is not set # CONFIG_MMC_MESON_MX_SDHC is not set # CONFIG_MMC_MESON_MX_SDIO is not set # CONFIG_MMC_MOXART is not set # CONFIG_MMC_OMAP_HS is not set CONFIG_MMC_ATMELMCI=m CONFIG_MMC_MXC=m # CONFIG_MMC_MVSDIO is not set # CONFIG_MMC_DAVINCI is not set # CONFIG_MMC_SPI is not set # CONFIG_MMC_S3C is not set CONFIG_MMC_TMIO_CORE=m CONFIG_MMC_TMIO=m # CONFIG_MMC_SDHI is not set # CONFIG_MMC_UNIPHIER is not set CONFIG_MMC_DW=m CONFIG_MMC_DW_PLTFM=m CONFIG_MMC_DW_BLUEFIELD=m CONFIG_MMC_DW_EXYNOS=m # CONFIG_MMC_DW_HI3798CV200 is not set CONFIG_MMC_DW_K3=m # CONFIG_MMC_SH_MMCIF is not set # CONFIG_MMC_VUB300 is not set CONFIG_MMC_USHC=m CONFIG_MMC_USDHI6ROL0=m CONFIG_MMC_CQHCI=m CONFIG_MMC_HSQ=m # CONFIG_MMC_BCM2835 is not set CONFIG_MMC_MTK=m # CONFIG_MMC_OWL is not set # CONFIG_MMC_LITEX is not set CONFIG_MEMSTICK=y # CONFIG_MEMSTICK_DEBUG is not set # # MemoryStick drivers # CONFIG_MEMSTICK_UNSAFE_RESUME=y # # MemoryStick Host Controller Drivers # CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=m CONFIG_LEDS_CLASS_FLASH=m CONFIG_LEDS_CLASS_MULTICOLOR=m CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y # # LED drivers # CONFIG_LEDS_AN30259A=m # CONFIG_LEDS_ARIEL is not set CONFIG_LEDS_AW2013=m CONFIG_LEDS_BCM6328=m CONFIG_LEDS_BCM6358=m # CONFIG_LEDS_CR0014114 is not set # CONFIG_LEDS_EL15203000 is not set # CONFIG_LEDS_TURRIS_OMNIA is not set # CONFIG_LEDS_LM3530 is not set # CONFIG_LEDS_LM3532 is not set CONFIG_LEDS_LM3533=m CONFIG_LEDS_LM3642=m # CONFIG_LEDS_LM3692X is not set # CONFIG_LEDS_MT6323 is not set # CONFIG_LEDS_S3C24XX is not set # CONFIG_LEDS_COBALT_QUBE is not set CONFIG_LEDS_GPIO=m CONFIG_LEDS_LP3944=m CONFIG_LEDS_LP3952=m # CONFIG_LEDS_LP50XX is not set CONFIG_LEDS_LP55XX_COMMON=m # CONFIG_LEDS_LP5521 is not set CONFIG_LEDS_LP5523=m CONFIG_LEDS_LP5562=m CONFIG_LEDS_LP8501=m CONFIG_LEDS_LP8860=m CONFIG_LEDS_PCA955X=m # CONFIG_LEDS_PCA955X_GPIO is not set # CONFIG_LEDS_PCA963X is not set CONFIG_LEDS_DAC124S085=m # CONFIG_LEDS_PWM is not set CONFIG_LEDS_REGULATOR=m CONFIG_LEDS_BD2802=m CONFIG_LEDS_LT3593=m CONFIG_LEDS_MC13783=m CONFIG_LEDS_NS2=m CONFIG_LEDS_NETXBIG=m CONFIG_LEDS_TCA6507=m CONFIG_LEDS_TLC591XX=m # CONFIG_LEDS_MAX77650 is not set CONFIG_LEDS_LM355x=m # CONFIG_LEDS_OT200 is not set CONFIG_LEDS_IS31FL319X=m CONFIG_LEDS_IS31FL32XX=m # # LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) # CONFIG_LEDS_BLINKM=m # CONFIG_LEDS_MLXREG is not set CONFIG_LEDS_USER=m # CONFIG_LEDS_SPI_BYTE is not set CONFIG_LEDS_TI_LMU_COMMON=m # CONFIG_LEDS_LM3697 is not set CONFIG_LEDS_LM36274=m # CONFIG_LEDS_IP30 is not set # CONFIG_LEDS_BCM63138 is not set # CONFIG_LEDS_LGM is not set # # Flash and Torch LED drivers # CONFIG_LEDS_AAT1290=m CONFIG_LEDS_AS3645A=m # CONFIG_LEDS_KTD2692 is not set CONFIG_LEDS_LM3601X=m CONFIG_LEDS_MAX77693=m CONFIG_LEDS_MT6360=m CONFIG_LEDS_RT4505=m CONFIG_LEDS_RT8515=m CONFIG_LEDS_SGM3140=m # # RGB LED drivers # # CONFIG_LEDS_PWM_MULTICOLOR is not set CONFIG_LEDS_QCOM_LPG=m # # LED Triggers # CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_ONESHOT=y # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set # CONFIG_LEDS_TRIGGER_CPU is not set CONFIG_LEDS_TRIGGER_ACTIVITY=m # CONFIG_LEDS_TRIGGER_GPIO is not set CONFIG_LEDS_TRIGGER_DEFAULT_ON=m # # iptables trigger is under Netfilter config (LED target) # CONFIG_LEDS_TRIGGER_TRANSIENT=y # CONFIG_LEDS_TRIGGER_CAMERA is not set # CONFIG_LEDS_TRIGGER_PANIC is not set # CONFIG_LEDS_TRIGGER_NETDEV is not set CONFIG_LEDS_TRIGGER_PATTERN=m # CONFIG_LEDS_TRIGGER_AUDIO is not set CONFIG_LEDS_TRIGGER_TTY=y # # Simple LED drivers # CONFIG_ACCESSIBILITY=y # # Speakup console speech # # end of Speakup console speech # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y CONFIG_EDAC=y CONFIG_EDAC_LEGACY_SYSFS=y # CONFIG_EDAC_DEBUG is not set # CONFIG_EDAC_AL_MC is not set CONFIG_EDAC_SYNOPSYS=y # CONFIG_EDAC_XGENE is not set CONFIG_RTC_LIB=y CONFIG_RTC_MC146818_LIB=y CONFIG_RTC_CLASS=y CONFIG_RTC_HCTOSYS=y CONFIG_RTC_HCTOSYS_DEVICE="rtc0" # CONFIG_RTC_SYSTOHC is not set # CONFIG_RTC_DEBUG is not set CONFIG_RTC_LIB_KUNIT_TEST=m # CONFIG_RTC_NVMEM is not set # # RTC interfaces # # CONFIG_RTC_INTF_SYSFS is not set # CONFIG_RTC_INTF_DEV is not set CONFIG_RTC_DRV_TEST=y # # I2C RTC drivers # CONFIG_RTC_DRV_88PM80X=m CONFIG_RTC_DRV_ABB5ZES3=m # CONFIG_RTC_DRV_ABEOZ9 is not set CONFIG_RTC_DRV_ABX80X=m # CONFIG_RTC_DRV_BRCMSTB is not set CONFIG_RTC_DRV_DS1307=m # CONFIG_RTC_DRV_DS1307_CENTURY is not set CONFIG_RTC_DRV_DS1374=m CONFIG_RTC_DRV_DS1374_WDT=y CONFIG_RTC_DRV_DS1672=m # CONFIG_RTC_DRV_HYM8563 is not set CONFIG_RTC_DRV_MAX6900=m # CONFIG_RTC_DRV_MAX8907 is not set # CONFIG_RTC_DRV_MAX77686 is not set # CONFIG_RTC_DRV_NCT3018Y is not set # CONFIG_RTC_DRV_RS5C372 is not set CONFIG_RTC_DRV_ISL1208=m # CONFIG_RTC_DRV_ISL12022 is not set # CONFIG_RTC_DRV_ISL12026 is not set CONFIG_RTC_DRV_X1205=m CONFIG_RTC_DRV_PCF8523=m CONFIG_RTC_DRV_PCF85063=m CONFIG_RTC_DRV_PCF85363=m # CONFIG_RTC_DRV_PCF8563 is not set CONFIG_RTC_DRV_PCF8583=m CONFIG_RTC_DRV_M41T80=m CONFIG_RTC_DRV_M41T80_WDT=y CONFIG_RTC_DRV_BQ32K=m CONFIG_RTC_DRV_RC5T619=m # CONFIG_RTC_DRV_S35390A is not set CONFIG_RTC_DRV_FM3130=m CONFIG_RTC_DRV_RX8010=m CONFIG_RTC_DRV_RX8581=m # CONFIG_RTC_DRV_RX8025 is not set # CONFIG_RTC_DRV_EM3027 is not set # CONFIG_RTC_DRV_RV3028 is not set # CONFIG_RTC_DRV_RV3032 is not set CONFIG_RTC_DRV_RV8803=m # CONFIG_RTC_DRV_S5M is not set CONFIG_RTC_DRV_SD3078=m # # SPI RTC drivers # CONFIG_RTC_DRV_M41T93=y # CONFIG_RTC_DRV_M41T94 is not set CONFIG_RTC_DRV_DS1302=y CONFIG_RTC_DRV_DS1305=y CONFIG_RTC_DRV_DS1343=y # CONFIG_RTC_DRV_DS1347 is not set CONFIG_RTC_DRV_DS1390=m # CONFIG_RTC_DRV_MAX6916 is not set CONFIG_RTC_DRV_R9701=m CONFIG_RTC_DRV_RX4581=m # CONFIG_RTC_DRV_RS5C348 is not set CONFIG_RTC_DRV_MAX6902=m # CONFIG_RTC_DRV_PCF2123 is not set # CONFIG_RTC_DRV_MCP795 is not set CONFIG_RTC_I2C_AND_SPI=m # # SPI and I2C RTC drivers # # CONFIG_RTC_DRV_DS3232 is not set # CONFIG_RTC_DRV_PCF2127 is not set CONFIG_RTC_DRV_RV3029C2=m CONFIG_RTC_DRV_RV3029_HWMON=y CONFIG_RTC_DRV_RX6110=m # # Platform RTC drivers # CONFIG_RTC_DRV_CMOS=m CONFIG_RTC_DRV_DS1286=y CONFIG_RTC_DRV_DS1511=y # CONFIG_RTC_DRV_DS1553 is not set CONFIG_RTC_DRV_DS1685_FAMILY=m # CONFIG_RTC_DRV_DS1685 is not set # CONFIG_RTC_DRV_DS1689 is not set # CONFIG_RTC_DRV_DS17285 is not set CONFIG_RTC_DRV_DS17485=y # CONFIG_RTC_DRV_DS17885 is not set # CONFIG_RTC_DRV_DS1742 is not set CONFIG_RTC_DRV_DS2404=m # CONFIG_RTC_DRV_DA9063 is not set CONFIG_RTC_DRV_STK17TA8=y CONFIG_RTC_DRV_M48T86=y CONFIG_RTC_DRV_M48T35=m CONFIG_RTC_DRV_M48T59=m CONFIG_RTC_DRV_MSM6242=y CONFIG_RTC_DRV_BQ4802=m # CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set # CONFIG_RTC_DRV_GAMECUBE is not set # CONFIG_RTC_DRV_SC27XX is not set CONFIG_RTC_DRV_SPEAR=y CONFIG_RTC_DRV_PCF50633=m # CONFIG_RTC_DRV_ZYNQMP is not set # CONFIG_RTC_DRV_NTXEC is not set # # on-CPU RTC drivers # # CONFIG_RTC_DRV_ASM9260 is not set # CONFIG_RTC_DRV_DAVINCI is not set # CONFIG_RTC_DRV_DIGICOLOR is not set # CONFIG_RTC_DRV_IMXDI is not set # CONFIG_RTC_DRV_FSL_FTM_ALARM is not set # CONFIG_RTC_DRV_MESON is not set # CONFIG_RTC_DRV_MESON_VRTC is not set # CONFIG_RTC_DRV_OMAP is not set # CONFIG_RTC_DRV_S3C is not set # CONFIG_RTC_DRV_EP93XX is not set # CONFIG_RTC_DRV_PL030 is not set CONFIG_RTC_DRV_PL031=m CONFIG_RTC_DRV_AT91RM9200=y # CONFIG_RTC_DRV_AT91SAM9 is not set # CONFIG_RTC_DRV_RZN1 is not set # CONFIG_RTC_DRV_GENERIC is not set # CONFIG_RTC_DRV_VT8500 is not set # CONFIG_RTC_DRV_SUN6I is not set # CONFIG_RTC_DRV_SUNXI is not set # CONFIG_RTC_DRV_MV is not set # CONFIG_RTC_DRV_ARMADA38X is not set # CONFIG_RTC_DRV_CADENCE is not set CONFIG_RTC_DRV_FTRTC010=m # CONFIG_RTC_DRV_STMP is not set CONFIG_RTC_DRV_PCAP=y CONFIG_RTC_DRV_MC13XXX=m # CONFIG_RTC_DRV_JZ4740 is not set # CONFIG_RTC_DRV_LPC24XX is not set # CONFIG_RTC_DRV_LPC32XX is not set # CONFIG_RTC_DRV_PM8XXX is not set # CONFIG_RTC_DRV_TEGRA is not set CONFIG_RTC_DRV_MXC=y CONFIG_RTC_DRV_MXC_V2=y CONFIG_RTC_DRV_SNVS=y # CONFIG_RTC_DRV_MOXART is not set # CONFIG_RTC_DRV_MT2712 is not set # CONFIG_RTC_DRV_MT6397 is not set # CONFIG_RTC_DRV_MT7622 is not set # CONFIG_RTC_DRV_XGENE is not set CONFIG_RTC_DRV_R7301=y # CONFIG_RTC_DRV_STM32 is not set # CONFIG_RTC_DRV_RTD119X is not set # CONFIG_RTC_DRV_ASPEED is not set # CONFIG_RTC_DRV_TI_K3 is not set # # HID Sensor RTC drivers # CONFIG_RTC_DRV_GOLDFISH=m # CONFIG_RTC_DRV_MSC313 is not set # CONFIG_DMADEVICES is not set # # DMABUF options # # CONFIG_SYNC_FILE is not set # CONFIG_DMABUF_HEAPS is not set # end of DMABUF options CONFIG_AUXDISPLAY=y CONFIG_CHARLCD=m CONFIG_LINEDISP=y CONFIG_HD44780_COMMON=m # CONFIG_HD44780 is not set CONFIG_KS0108=m CONFIG_KS0108_PORT=0x378 CONFIG_KS0108_DELAY=2 CONFIG_IMG_ASCII_LCD=y # CONFIG_LCD2S is not set CONFIG_PARPORT_PANEL=m CONFIG_PANEL_PARPORT=0 CONFIG_PANEL_PROFILE=5 CONFIG_PANEL_CHANGE_MESSAGE=y CONFIG_PANEL_BOOT_MESSAGE="" # CONFIG_CHARLCD_BL_OFF is not set CONFIG_CHARLCD_BL_ON=y # CONFIG_CHARLCD_BL_FLASH is not set CONFIG_PANEL=m CONFIG_VFIO=y CONFIG_VFIO_VIRQFD=m CONFIG_VFIO_NOIOMMU=y CONFIG_VFIO_PLATFORM=m # CONFIG_VFIO_AMBA is not set CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET=m CONFIG_VFIO_PLATFORM_AMDXGBE_RESET=m # CONFIG_VFIO_PLATFORM_BCMFLEXRM_RESET is not set CONFIG_VFIO_MDEV=y CONFIG_IRQ_BYPASS_MANAGER=y CONFIG_VIRT_DRIVERS=y CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO=m # CONFIG_VIRTIO_MENU is not set CONFIG_VDPA=y CONFIG_VDPA_SIM=y # CONFIG_VDPA_SIM_NET is not set CONFIG_VDPA_SIM_BLOCK=y CONFIG_VHOST_IOTLB=y CONFIG_VHOST_RING=y CONFIG_VHOST=y CONFIG_VHOST_MENU=y # CONFIG_VHOST_NET is not set CONFIG_VHOST_VDPA=y CONFIG_VHOST_CROSS_ENDIAN_LEGACY=y # # Microsoft Hyper-V guest support # # end of Microsoft Hyper-V guest support CONFIG_GREYBUS=m # CONFIG_GREYBUS_ES2 is not set CONFIG_COMEDI=m # CONFIG_COMEDI_DEBUG is not set CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048 CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480 CONFIG_COMEDI_MISC_DRIVERS=y CONFIG_COMEDI_BOND=m CONFIG_COMEDI_TEST=m # CONFIG_COMEDI_PARPORT is not set # CONFIG_COMEDI_SSV_DNP is not set # CONFIG_COMEDI_ISA_DRIVERS is not set CONFIG_COMEDI_PCMCIA_DRIVERS=m CONFIG_COMEDI_CB_DAS16_CS=m CONFIG_COMEDI_DAS08_CS=m # CONFIG_COMEDI_NI_DAQ_700_CS is not set CONFIG_COMEDI_NI_DAQ_DIO24_CS=m CONFIG_COMEDI_NI_LABPC_CS=m # CONFIG_COMEDI_NI_MIO_CS is not set CONFIG_COMEDI_QUATECH_DAQP_CS=m CONFIG_COMEDI_USB_DRIVERS=m CONFIG_COMEDI_DT9812=m # CONFIG_COMEDI_NI_USB6501 is not set # CONFIG_COMEDI_USBDUX is not set CONFIG_COMEDI_USBDUXFAST=m # CONFIG_COMEDI_USBDUXSIGMA is not set CONFIG_COMEDI_VMK80XX=m CONFIG_COMEDI_8254=m CONFIG_COMEDI_8255=m CONFIG_COMEDI_8255_SA=m CONFIG_COMEDI_KCOMEDILIB=m CONFIG_COMEDI_DAS08=m CONFIG_COMEDI_NI_LABPC=m # CONFIG_COMEDI_TESTS is not set CONFIG_STAGING=y # # IIO staging drivers # # # Accelerometers # # CONFIG_ADIS16203 is not set # CONFIG_ADIS16240 is not set # end of Accelerometers # # Analog to digital converters # # CONFIG_AD7816 is not set # end of Analog to digital converters # # Analog digital bi-direction converters # CONFIG_ADT7316=y CONFIG_ADT7316_SPI=m # CONFIG_ADT7316_I2C is not set # end of Analog digital bi-direction converters # # Direct Digital Synthesis # # CONFIG_AD9832 is not set CONFIG_AD9834=y # end of Direct Digital Synthesis # # Network Analyzer, Impedance Converters # CONFIG_AD5933=m # end of Network Analyzer, Impedance Converters # # Active energy metering IC # CONFIG_ADE7854=m CONFIG_ADE7854_I2C=m # CONFIG_ADE7854_SPI is not set # end of Active energy metering IC # # Resolver to digital converters # CONFIG_AD2S1210=y # end of Resolver to digital converters # end of IIO staging drivers CONFIG_STAGING_MEDIA=y CONFIG_STAGING_BOARD=y # CONFIG_LTE_GDM724X is not set CONFIG_FB_TFT=m CONFIG_FB_TFT_AGM1264K_FL=m CONFIG_FB_TFT_BD663474=m CONFIG_FB_TFT_HX8340BN=m # CONFIG_FB_TFT_HX8347D is not set CONFIG_FB_TFT_HX8353D=m # CONFIG_FB_TFT_HX8357D is not set CONFIG_FB_TFT_ILI9163=m CONFIG_FB_TFT_ILI9320=m # CONFIG_FB_TFT_ILI9325 is not set CONFIG_FB_TFT_ILI9340=m CONFIG_FB_TFT_ILI9341=m # CONFIG_FB_TFT_ILI9481 is not set CONFIG_FB_TFT_ILI9486=m CONFIG_FB_TFT_PCD8544=m CONFIG_FB_TFT_RA8875=m # CONFIG_FB_TFT_S6D02A1 is not set # CONFIG_FB_TFT_S6D1121 is not set # CONFIG_FB_TFT_SEPS525 is not set # CONFIG_FB_TFT_SH1106 is not set CONFIG_FB_TFT_SSD1289=m # CONFIG_FB_TFT_SSD1305 is not set CONFIG_FB_TFT_SSD1306=m CONFIG_FB_TFT_SSD1331=m # CONFIG_FB_TFT_SSD1351 is not set CONFIG_FB_TFT_ST7735R=m CONFIG_FB_TFT_ST7789V=m CONFIG_FB_TFT_TINYLCD=m # CONFIG_FB_TFT_TLS8204 is not set # CONFIG_FB_TFT_UC1611 is not set # CONFIG_FB_TFT_UC1701 is not set # CONFIG_FB_TFT_UPD161704 is not set CONFIG_MOST_COMPONENTS=m # CONFIG_MOST_NET is not set # CONFIG_MOST_DIM2 is not set CONFIG_MOST_I2C=m CONFIG_GREYBUS_BOOTROM=m CONFIG_GREYBUS_FIRMWARE=m # CONFIG_GREYBUS_LIGHT is not set # CONFIG_GREYBUS_LOG is not set # CONFIG_GREYBUS_LOOPBACK is not set CONFIG_GREYBUS_POWER=m # CONFIG_GREYBUS_RAW is not set CONFIG_GREYBUS_VIBRATOR=m CONFIG_GREYBUS_BRIDGED_PHY=m CONFIG_GREYBUS_GPIO=m CONFIG_GREYBUS_I2C=m # CONFIG_GREYBUS_PWM is not set CONFIG_GREYBUS_SDIO=m CONFIG_GREYBUS_SPI=m CONFIG_GREYBUS_UART=m # CONFIG_GREYBUS_USB is not set # CONFIG_GREYBUS_ARCHE is not set CONFIG_BCM_VIDEOCORE=y # CONFIG_BCM2835_VCHIQ is not set # CONFIG_PI433 is not set CONFIG_XIL_AXIS_FIFO=m CONFIG_FIELDBUS_DEV=m # CONFIG_HMS_ANYBUSS_BUS is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set CONFIG_MELLANOX_PLATFORM=y CONFIG_MLXREG_HOTPLUG=m # CONFIG_MLXREG_IO is not set # CONFIG_MLXREG_LC is not set # CONFIG_NVSW_SN2201 is not set # CONFIG_OLPC_XO175 is not set CONFIG_SURFACE_PLATFORMS=y CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y # # Clock driver for ARM Reference designs # # CONFIG_CLK_ICST is not set # CONFIG_CLK_SP810 is not set CONFIG_CLK_VEXPRESS_OSC=y # end of Clock driver for ARM Reference designs # CONFIG_CLK_HSDK is not set CONFIG_LMK04832=m # CONFIG_COMMON_CLK_APPLE_NCO is not set CONFIG_COMMON_CLK_MAX77686=m CONFIG_COMMON_CLK_MAX9485=m # CONFIG_COMMON_CLK_HI655X is not set # CONFIG_COMMON_CLK_SCMI is not set # CONFIG_COMMON_CLK_SCPI is not set CONFIG_COMMON_CLK_SI5341=m # CONFIG_COMMON_CLK_SI5351 is not set CONFIG_COMMON_CLK_SI514=m CONFIG_COMMON_CLK_SI544=m CONFIG_COMMON_CLK_SI570=m # CONFIG_COMMON_CLK_BM1880 is not set CONFIG_COMMON_CLK_CDCE706=m # CONFIG_COMMON_CLK_TPS68470 is not set # CONFIG_COMMON_CLK_CDCE925 is not set CONFIG_COMMON_CLK_CS2000_CP=m # CONFIG_COMMON_CLK_EN7523 is not set # CONFIG_COMMON_CLK_FSL_FLEXSPI is not set # CONFIG_COMMON_CLK_FSL_SAI is not set # CONFIG_COMMON_CLK_GEMINI is not set # CONFIG_COMMON_CLK_LAN966X is not set # CONFIG_COMMON_CLK_ASPEED is not set # CONFIG_COMMON_CLK_S2MPS11 is not set # CONFIG_COMMON_CLK_AXI_CLKGEN is not set # CONFIG_CLK_QORIQ is not set # CONFIG_CLK_LS1028A_PLLDIG is not set # CONFIG_COMMON_CLK_XGENE is not set # CONFIG_COMMON_CLK_PWM is not set # CONFIG_COMMON_CLK_OXNAS is not set CONFIG_COMMON_CLK_RS9_PCIE=m # CONFIG_COMMON_CLK_VC5 is not set # CONFIG_COMMON_CLK_VC7 is not set # CONFIG_COMMON_CLK_MMP2_AUDIO is not set CONFIG_COMMON_CLK_FIXED_MMIO=y # CONFIG_CLK_ACTIONS is not set # CONFIG_CLK_BAIKAL_T1 is not set # CONFIG_CLK_BCM2711_DVP is not set # CONFIG_CLK_BCM2835 is not set # CONFIG_CLK_BCM_63XX is not set # CONFIG_CLK_BCM_63XX_GATE is not set # CONFIG_CLK_BCM_KONA is not set # CONFIG_CLK_BCM_CYGNUS is not set # CONFIG_CLK_BCM_HR2 is not set # CONFIG_CLK_BCM_NSP is not set # CONFIG_CLK_BCM_NS2 is not set # CONFIG_CLK_BCM_SR is not set # CONFIG_CLK_RASPBERRYPI is not set # CONFIG_COMMON_CLK_HI3516CV300 is not set # CONFIG_COMMON_CLK_HI3519 is not set # CONFIG_COMMON_CLK_HI3559A is not set # CONFIG_COMMON_CLK_HI3660 is not set # CONFIG_COMMON_CLK_HI3670 is not set # CONFIG_COMMON_CLK_HI3798CV200 is not set # CONFIG_COMMON_CLK_HI6220 is not set # CONFIG_RESET_HISI is not set # CONFIG_STUB_CLK_HI6220 is not set # CONFIG_STUB_CLK_HI3660 is not set # CONFIG_COMMON_CLK_BOSTON is not set CONFIG_MXC_CLK=y CONFIG_CLK_IMX7D=y CONFIG_CLK_IMX7ULP=y # CONFIG_CLK_IMX8MM is not set CONFIG_CLK_IMX8MN=y CONFIG_CLK_IMX8MP=y CONFIG_CLK_IMX8MQ=y CONFIG_CLK_IMX8ULP=y CONFIG_CLK_IMX93=m CONFIG_CLK_IMXRT1050=y # # Ingenic SoCs drivers # # CONFIG_INGENIC_CGU_JZ4740 is not set # CONFIG_INGENIC_CGU_JZ4725B is not set # CONFIG_INGENIC_CGU_JZ4760 is not set # CONFIG_INGENIC_CGU_JZ4770 is not set # CONFIG_INGENIC_CGU_JZ4780 is not set # CONFIG_INGENIC_CGU_X1000 is not set # CONFIG_INGENIC_CGU_X1830 is not set # CONFIG_INGENIC_TCU_CLK is not set # end of Ingenic SoCs drivers # CONFIG_COMMON_CLK_KEYSTONE is not set # CONFIG_TI_SYSCON_CLK is not set # # Clock driver for MediaTek SoC # # CONFIG_COMMON_CLK_MT2701 is not set # CONFIG_COMMON_CLK_MT2712 is not set # CONFIG_COMMON_CLK_MT6765 is not set # CONFIG_COMMON_CLK_MT6779 is not set # CONFIG_COMMON_CLK_MT6795 is not set # CONFIG_COMMON_CLK_MT6797 is not set # CONFIG_COMMON_CLK_MT7622 is not set # CONFIG_COMMON_CLK_MT7629 is not set # CONFIG_COMMON_CLK_MT7986 is not set # CONFIG_COMMON_CLK_MT8135 is not set # CONFIG_COMMON_CLK_MT8167 is not set # CONFIG_COMMON_CLK_MT8173 is not set # CONFIG_COMMON_CLK_MT8183 is not set # CONFIG_COMMON_CLK_MT8186 is not set # CONFIG_COMMON_CLK_MT8192 is not set # CONFIG_COMMON_CLK_MT8195 is not set # CONFIG_COMMON_CLK_MT8365 is not set # CONFIG_COMMON_CLK_MT8516 is not set # end of Clock driver for MediaTek SoC # # Clock support for Amlogic platforms # CONFIG_COMMON_CLK_MESON_REGMAP=y CONFIG_COMMON_CLK_MESON_MPLL=y CONFIG_COMMON_CLK_MESON_PLL=y CONFIG_COMMON_CLK_MESON8B=y # end of Clock support for Amlogic platforms # CONFIG_MSTAR_MSC313_MPLL is not set # CONFIG_MCHP_CLK_MPFS is not set # CONFIG_COMMON_CLK_PISTACHIO is not set # CONFIG_COMMON_CLK_QCOM is not set # CONFIG_CLK_MT7621 is not set # CONFIG_CLK_RENESAS is not set # CONFIG_COMMON_CLK_SAMSUNG is not set # CONFIG_S3C2410_COMMON_CLK is not set # CONFIG_S3C2412_COMMON_CLK is not set # CONFIG_S3C2443_COMMON_CLK is not set # CONFIG_CLK_SIFIVE is not set # CONFIG_CLK_INTEL_SOCFPGA is not set # CONFIG_SPRD_COMMON_CLK is not set # CONFIG_CLK_STARFIVE_JH7100 is not set CONFIG_CLK_SUNXI=y CONFIG_CLK_SUNXI_CLOCKS=y CONFIG_CLK_SUNXI_PRCM_SUN6I=y CONFIG_CLK_SUNXI_PRCM_SUN8I=y CONFIG_CLK_SUNXI_PRCM_SUN9I=y # CONFIG_SUNXI_CCU is not set # CONFIG_COMMON_CLK_TI_ADPLL is not set # CONFIG_CLK_UNIPHIER is not set # CONFIG_COMMON_CLK_VISCONTI is not set # CONFIG_CLK_LGM_CGU is not set CONFIG_XILINX_VCU=y CONFIG_COMMON_CLK_XLNX_CLKWZRD=y # CONFIG_COMMON_CLK_ZYNQMP is not set CONFIG_CLK_KUNIT_TEST=m CONFIG_CLK_GATE_KUNIT_TEST=m # CONFIG_HWSPINLOCK is not set # # Clock Source drivers # CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y CONFIG_CLKSRC_MMIO=y # CONFIG_BCM2835_TIMER is not set # CONFIG_BCM_KONA_TIMER is not set # CONFIG_DAVINCI_TIMER is not set # CONFIG_DIGICOLOR_TIMER is not set # CONFIG_OMAP_DM_TIMER is not set # CONFIG_DW_APB_TIMER is not set # CONFIG_FTTMR010_TIMER is not set # CONFIG_IXP4XX_TIMER is not set # CONFIG_ROCKCHIP_TIMER is not set # CONFIG_ARMADA_370_XP_TIMER is not set # CONFIG_MESON6_TIMER is not set # CONFIG_ORION_TIMER is not set # CONFIG_OWL_TIMER is not set # CONFIG_RDA_TIMER is not set # CONFIG_SUN4I_TIMER is not set # CONFIG_SUN5I_HSTIMER is not set # CONFIG_TEGRA_TIMER is not set # CONFIG_TEGRA186_TIMER is not set # CONFIG_VT8500_TIMER is not set # CONFIG_NPCM7XX_TIMER is not set # CONFIG_CADENCE_TTC_TIMER is not set # CONFIG_ASM9260_TIMER is not set # CONFIG_CLKSRC_NOMADIK_MTU is not set # CONFIG_CLKSRC_DBX500_PRCMU is not set # CONFIG_CLPS711X_TIMER is not set # CONFIG_MXS_TIMER is not set # CONFIG_NSPIRE_TIMER is not set # CONFIG_KEYSTONE_TIMER is not set # CONFIG_INTEGRATOR_AP_TIMER is not set # CONFIG_CLKSRC_LPC32XX is not set # CONFIG_CLKSRC_PISTACHIO is not set # CONFIG_CLKSRC_TI_32K is not set # CONFIG_CLKSRC_STM32 is not set # CONFIG_CLKSRC_STM32_LP is not set # CONFIG_CLKSRC_MPS2 is not set # CONFIG_ARC_TIMERS is not set # CONFIG_ARM_GLOBAL_TIMER is not set # CONFIG_ARM_TIMER_SP804 is not set CONFIG_ARMV7M_SYSTICK=y # CONFIG_ATMEL_PIT is not set # CONFIG_ATMEL_ST is not set # CONFIG_ATMEL_TCB_CLKSRC is not set # CONFIG_CLKSRC_EXYNOS_MCT is not set # CONFIG_CLKSRC_SAMSUNG_PWM is not set # CONFIG_FSL_FTM_TIMER is not set # CONFIG_OXNAS_RPS_TIMER is not set # CONFIG_MTK_TIMER is not set # CONFIG_SPRD_TIMER is not set # CONFIG_CLKSRC_JCORE_PIT is not set # CONFIG_SH_TIMER_CMT is not set # CONFIG_SH_TIMER_MTU2 is not set # CONFIG_RENESAS_OSTM is not set # CONFIG_SH_TIMER_TMU is not set # CONFIG_EM_TIMER_STI is not set # CONFIG_CLKSRC_QCOM is not set # CONFIG_CLKSRC_VERSATILE is not set # CONFIG_CLKSRC_PXA is not set CONFIG_CLKSRC_IMX_GPT=y CONFIG_CLKSRC_IMX_TPM=y # CONFIG_TIMER_IMX_SYS_CTR is not set # CONFIG_CLKSRC_ST_LPC is not set # CONFIG_GXP_TIMER is not set # CONFIG_MILBEAUT_TIMER is not set # CONFIG_MSC313E_TIMER is not set # CONFIG_INGENIC_TIMER is not set # CONFIG_INGENIC_SYSOST is not set # CONFIG_INGENIC_OST is not set CONFIG_MICROCHIP_PIT64B=y # CONFIG_GOLDFISH_TIMER is not set # end of Clock Source drivers CONFIG_MAILBOX=y # CONFIG_ARM_MHU is not set CONFIG_ARM_MHU_V2=y CONFIG_IMX_MBOX=m CONFIG_PLATFORM_MHU=y CONFIG_PL320_MBOX=y # CONFIG_ARMADA_37XX_RWTM_MBOX is not set # CONFIG_ROCKCHIP_MBOX is not set CONFIG_ALTERA_MBOX=m # CONFIG_HI3660_MBOX is not set # CONFIG_HI6220_MBOX is not set # CONFIG_MAILBOX_TEST is not set # CONFIG_POLARFIRE_SOC_MAILBOX is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_BCM_PDC_MBOX is not set # CONFIG_STM32_IPCC is not set # CONFIG_MTK_ADSP_MBOX is not set # CONFIG_MTK_CMDQ_MBOX is not set # CONFIG_SUN6I_MSGBOX is not set # CONFIG_SPRD_MBOX is not set # CONFIG_QCOM_IPCC is not set CONFIG_IOMMU_IOVA=y CONFIG_IOMMU_API=y # # Remoteproc drivers # # CONFIG_REMOTEPROC is not set # end of Remoteproc drivers # # Rpmsg drivers # CONFIG_RPMSG=m CONFIG_RPMSG_CHAR=m CONFIG_RPMSG_CTRL=m CONFIG_RPMSG_NS=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set CONFIG_RPMSG_VIRTIO=m # end of Rpmsg drivers CONFIG_SOUNDWIRE=m # # SoundWire Devices # # # SOC (System On Chip) specific Drivers # # CONFIG_OWL_PM_DOMAINS is not set # # Amlogic SoC drivers # # CONFIG_MESON_CANVAS is not set # CONFIG_MESON_CLK_MEASURE is not set # CONFIG_MESON_GX_SOCINFO is not set # CONFIG_MESON_GX_PM_DOMAINS is not set # CONFIG_MESON_EE_PM_DOMAINS is not set # CONFIG_MESON_MX_SOCINFO is not set # end of Amlogic SoC drivers # # Apple SoC drivers # # CONFIG_APPLE_PMGR_PWRSTATE is not set # CONFIG_APPLE_RTKIT is not set # CONFIG_APPLE_SART is not set # end of Apple SoC drivers # # ASPEED SoC drivers # # CONFIG_ASPEED_LPC_CTRL is not set # CONFIG_ASPEED_LPC_SNOOP is not set # CONFIG_ASPEED_UART_ROUTING is not set # CONFIG_ASPEED_P2A_CTRL is not set # CONFIG_ASPEED_SOCINFO is not set # end of ASPEED SoC drivers # CONFIG_AT91_SOC_ID is not set CONFIG_AT91_SOC_SFR=y # # Broadcom SoC drivers # # CONFIG_BCM2835_POWER is not set # CONFIG_SOC_BCM63XX is not set # CONFIG_SOC_BRCMSTB is not set # CONFIG_BCM_PMB is not set # end of Broadcom SoC drivers # # NXP/Freescale QorIQ SoC drivers # # CONFIG_QUICC_ENGINE is not set CONFIG_DPAA2_CONSOLE=y # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers # # fujitsu SoC drivers # # end of fujitsu SoC drivers # # i.MX SoC drivers # CONFIG_IMX_GPCV2_PM_DOMAINS=y CONFIG_SOC_IMX8M=y # CONFIG_SOC_IMX9 is not set # end of i.MX SoC drivers # # IXP4xx SoC drivers # # CONFIG_IXP4XX_QMGR is not set # CONFIG_IXP4XX_NPE is not set # end of IXP4xx SoC drivers # # Enable LiteX SoC Builder specific drivers # CONFIG_LITEX=y CONFIG_LITEX_SOC_CONTROLLER=y # end of Enable LiteX SoC Builder specific drivers # # MediaTek SoC drivers # # CONFIG_MTK_CMDQ is not set # CONFIG_MTK_DEVAPC is not set # CONFIG_MTK_INFRACFG is not set # CONFIG_MTK_PMIC_WRAP is not set # CONFIG_MTK_SCPSYS is not set # CONFIG_MTK_SCPSYS_PM_DOMAINS is not set # CONFIG_MTK_MMSYS is not set # end of MediaTek SoC drivers # # Qualcomm SoC drivers # # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_GENI_SE is not set # CONFIG_QCOM_GSBI is not set # CONFIG_QCOM_LLCC is not set # CONFIG_QCOM_RPMH is not set # CONFIG_QCOM_SMD_RPM is not set # CONFIG_QCOM_SPM is not set # CONFIG_QCOM_WCNSS_CTRL is not set # CONFIG_QCOM_APR is not set # CONFIG_QCOM_ICC_BWMON is not set # end of Qualcomm SoC drivers # CONFIG_SOC_RENESAS is not set # CONFIG_ROCKCHIP_GRF is not set # CONFIG_ROCKCHIP_IODOMAIN is not set # CONFIG_ROCKCHIP_PM_DOMAINS is not set # CONFIG_SOC_SAMSUNG is not set # CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER is not set # CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER is not set # CONFIG_SOC_TI is not set # CONFIG_UX500_SOC_ID is not set # # Xilinx SoC drivers # # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers CONFIG_PM_DEVFREQ=y # # DEVFREQ Governors # CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_DEVFREQ_GOV_PERFORMANCE=m CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_USERSPACE=m CONFIG_DEVFREQ_GOV_PASSIVE=y # # DEVFREQ Drivers # # CONFIG_ARM_EXYNOS_BUS_DEVFREQ is not set CONFIG_ARM_IMX_BUS_DEVFREQ=m # CONFIG_ARM_TEGRA_DEVFREQ is not set # CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set # CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ is not set CONFIG_PM_DEVFREQ_EVENT=y # CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP is not set # CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU is not set # CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI is not set CONFIG_EXTCON=y # # Extcon Device Drivers # CONFIG_EXTCON_ADC_JACK=m # CONFIG_EXTCON_GPIO is not set # CONFIG_EXTCON_MAX14577 is not set # CONFIG_EXTCON_MAX3355 is not set CONFIG_EXTCON_PTN5150=m # CONFIG_EXTCON_QCOM_SPMI_MISC is not set CONFIG_EXTCON_RT8973A=m # CONFIG_EXTCON_SM5502 is not set # CONFIG_EXTCON_USB_GPIO is not set CONFIG_EXTCON_USBC_TUSB320=m CONFIG_MEMORY=y CONFIG_DDR=y CONFIG_ARM_PL172_MPMC=m CONFIG_ATMEL_SDRAMC=y CONFIG_ATMEL_EBI=y # CONFIG_BRCMSTB_DPFE is not set # CONFIG_BRCMSTB_MEMC is not set # CONFIG_BT1_L2_CTL is not set # CONFIG_TI_AEMIF is not set # CONFIG_TI_EMIF is not set # CONFIG_OMAP_GPMC is not set # CONFIG_MVEBU_DEVBUS is not set # CONFIG_FSL_CORENET_CF is not set # CONFIG_FSL_IFC is not set # CONFIG_JZ4780_NEMC is not set # CONFIG_MTK_SMI is not set # CONFIG_DA8XX_DDRCTL is not set # CONFIG_PL353_SMC is not set # CONFIG_RENESAS_RPCIF is not set # CONFIG_STM32_FMC2_EBI is not set # CONFIG_SAMSUNG_MC is not set CONFIG_TEGRA_MC=y CONFIG_TEGRA20_EMC=y CONFIG_TEGRA30_EMC=y CONFIG_TEGRA124_EMC=y # CONFIG_TEGRA210_EMC is not set CONFIG_IIO=y CONFIG_IIO_BUFFER=y CONFIG_IIO_BUFFER_CB=y CONFIG_IIO_BUFFER_DMA=y CONFIG_IIO_BUFFER_DMAENGINE=y CONFIG_IIO_BUFFER_HW_CONSUMER=m CONFIG_IIO_KFIFO_BUF=y CONFIG_IIO_TRIGGERED_BUFFER=y CONFIG_IIO_CONFIGFS=y CONFIG_IIO_TRIGGER=y CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_IIO_SW_DEVICE is not set CONFIG_IIO_SW_TRIGGER=y CONFIG_IIO_TRIGGERED_EVENT=y # # Accelerometers # CONFIG_ADIS16201=m CONFIG_ADIS16209=m CONFIG_ADXL313=m CONFIG_ADXL313_I2C=m # CONFIG_ADXL313_SPI is not set CONFIG_ADXL345=m CONFIG_ADXL345_I2C=m CONFIG_ADXL345_SPI=m CONFIG_ADXL355=y # CONFIG_ADXL355_I2C is not set CONFIG_ADXL355_SPI=y CONFIG_ADXL367=m CONFIG_ADXL367_SPI=m CONFIG_ADXL367_I2C=m CONFIG_ADXL372=y CONFIG_ADXL372_SPI=y CONFIG_ADXL372_I2C=m CONFIG_BMA180=m # CONFIG_BMA220 is not set CONFIG_BMA400=y CONFIG_BMA400_I2C=m CONFIG_BMA400_SPI=y CONFIG_BMC150_ACCEL=m CONFIG_BMC150_ACCEL_I2C=m CONFIG_BMC150_ACCEL_SPI=m CONFIG_BMI088_ACCEL=m CONFIG_BMI088_ACCEL_SPI=m # CONFIG_DA280 is not set CONFIG_DA311=m CONFIG_DMARD06=m CONFIG_DMARD09=m CONFIG_DMARD10=m # CONFIG_FXLS8962AF_I2C is not set # CONFIG_FXLS8962AF_SPI is not set CONFIG_IIO_ST_ACCEL_3AXIS=y CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m # CONFIG_IIO_ST_ACCEL_SPI_3AXIS is not set CONFIG_KXSD9=m CONFIG_KXSD9_SPI=m CONFIG_KXSD9_I2C=m CONFIG_KXCJK1013=m CONFIG_MC3230=m CONFIG_MMA7455=m CONFIG_MMA7455_I2C=m CONFIG_MMA7455_SPI=m CONFIG_MMA7660=m CONFIG_MMA8452=m CONFIG_MMA9551_CORE=m CONFIG_MMA9551=m # CONFIG_MMA9553 is not set CONFIG_MSA311=m CONFIG_MXC4005=m # CONFIG_MXC6255 is not set # CONFIG_SCA3000 is not set # CONFIG_SCA3300 is not set # CONFIG_STK8312 is not set CONFIG_STK8BA50=m # end of Accelerometers # # Analog to digital converters # CONFIG_AD_SIGMA_DELTA=y CONFIG_AD7091R5=m CONFIG_AD7124=y # CONFIG_AD7192 is not set CONFIG_AD7266=y CONFIG_AD7280=y CONFIG_AD7291=m # CONFIG_AD7292 is not set # CONFIG_AD7298 is not set # CONFIG_AD7476 is not set CONFIG_AD7606=y CONFIG_AD7606_IFACE_PARALLEL=y CONFIG_AD7606_IFACE_SPI=y CONFIG_AD7766=m CONFIG_AD7768_1=m # CONFIG_AD7780 is not set CONFIG_AD7791=m CONFIG_AD7793=y CONFIG_AD7887=y CONFIG_AD7923=y CONFIG_AD7949=m # CONFIG_AD799X is not set # CONFIG_ADI_AXI_ADC is not set # CONFIG_ASPEED_ADC is not set CONFIG_AT91_SAMA5D2_ADC=y CONFIG_AXP20X_ADC=m CONFIG_AXP288_ADC=m # CONFIG_BCM_IPROC_ADC is not set # CONFIG_BERLIN2_ADC is not set CONFIG_CC10001_ADC=m CONFIG_DA9150_GPADC=m CONFIG_DLN2_ADC=m CONFIG_ENVELOPE_DETECTOR=y # CONFIG_EXYNOS_ADC is not set CONFIG_HI8435=m CONFIG_HX711=y CONFIG_INA2XX_ADC=m # CONFIG_INGENIC_ADC is not set CONFIG_IMX7D_ADC=y # CONFIG_IMX8QXP_ADC is not set # CONFIG_LPC18XX_ADC is not set # CONFIG_LPC32XX_ADC is not set # CONFIG_LTC2471 is not set # CONFIG_LTC2485 is not set # CONFIG_LTC2496 is not set CONFIG_LTC2497=m CONFIG_MAX1027=y # CONFIG_MAX11100 is not set # CONFIG_MAX1118 is not set # CONFIG_MAX11205 is not set # CONFIG_MAX1241 is not set CONFIG_MAX1363=m CONFIG_MAX9611=m CONFIG_MCP320X=m # CONFIG_MCP3422 is not set CONFIG_MCP3911=y # CONFIG_MEDIATEK_MT6360_ADC is not set # CONFIG_MEDIATEK_MT6577_AUXADC is not set CONFIG_MEN_Z188_ADC=m # CONFIG_MESON_SARADC is not set CONFIG_MP2629_ADC=m CONFIG_NAU7802=m # CONFIG_NPCM_ADC is not set CONFIG_QCOM_VADC_COMMON=m CONFIG_QCOM_SPMI_IADC=m CONFIG_QCOM_SPMI_VADC=m CONFIG_QCOM_SPMI_ADC5=m # CONFIG_RCAR_GYRO_ADC is not set CONFIG_RN5T618_ADC=m # CONFIG_ROCKCHIP_SARADC is not set # CONFIG_RICHTEK_RTQ6056 is not set # CONFIG_RZG2L_ADC is not set # CONFIG_SC27XX_ADC is not set # CONFIG_SPEAR_ADC is not set CONFIG_SD_ADC_MODULATOR=m # CONFIG_STM32_ADC_CORE is not set # CONFIG_STM32_DFSDM_CORE is not set # CONFIG_STM32_DFSDM_ADC is not set CONFIG_TI_ADC081C=m CONFIG_TI_ADC0832=y CONFIG_TI_ADC084S021=m # CONFIG_TI_ADC12138 is not set # CONFIG_TI_ADC108S102 is not set # CONFIG_TI_ADC128S052 is not set CONFIG_TI_ADC161S626=m # CONFIG_TI_ADS1015 is not set CONFIG_TI_ADS7950=y # CONFIG_TI_ADS8344 is not set CONFIG_TI_ADS8688=m # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS131E08 is not set CONFIG_TI_TLC4541=m CONFIG_TI_TSC2046=y # CONFIG_VF610_ADC is not set CONFIG_VIPERBOARD_ADC=y CONFIG_XILINX_XADC=m # CONFIG_XILINX_AMS is not set # end of Analog to digital converters # # Analog to digital and digital to analog converters # CONFIG_AD74413R=y # end of Analog to digital and digital to analog converters # # Analog Front Ends # # CONFIG_IIO_RESCALE is not set # end of Analog Front Ends # # Amplifiers # CONFIG_AD8366=m CONFIG_ADA4250=m # CONFIG_HMC425 is not set # end of Amplifiers # # Capacitance to digital converters # CONFIG_AD7150=m CONFIG_AD7746=m # end of Capacitance to digital converters # # Chemical Sensors # CONFIG_ATLAS_PH_SENSOR=m # CONFIG_ATLAS_EZO_SENSOR is not set CONFIG_BME680=m CONFIG_BME680_I2C=m CONFIG_BME680_SPI=m CONFIG_CCS811=m CONFIG_IAQCORE=m CONFIG_PMS7003=y # CONFIG_SCD30_CORE is not set CONFIG_SCD4X=m CONFIG_SENSIRION_SGP30=m CONFIG_SENSIRION_SGP40=m # CONFIG_SPS30_I2C is not set # CONFIG_SPS30_SERIAL is not set CONFIG_SENSEAIR_SUNRISE_CO2=m # CONFIG_VZ89X is not set # end of Chemical Sensors # # Hid Sensor IIO Common # # end of Hid Sensor IIO Common CONFIG_IIO_MS_SENSORS_I2C=m # # IIO SCMI Sensors # # end of IIO SCMI Sensors # # SSP Sensor Common # # CONFIG_IIO_SSP_SENSORS_COMMONS is not set CONFIG_IIO_SSP_SENSORHUB=m # end of SSP Sensor Common CONFIG_IIO_ST_SENSORS_I2C=m CONFIG_IIO_ST_SENSORS_CORE=y # # Digital to analog converters # CONFIG_AD3552R=m # CONFIG_AD5064 is not set CONFIG_AD5360=m CONFIG_AD5380=m CONFIG_AD5421=m # CONFIG_AD5446 is not set CONFIG_AD5449=y # CONFIG_AD5592R is not set # CONFIG_AD5593R is not set CONFIG_AD5504=y CONFIG_AD5624R_SPI=y # CONFIG_LTC2688 is not set CONFIG_AD5686=m CONFIG_AD5686_SPI=m CONFIG_AD5696_I2C=m # CONFIG_AD5755 is not set # CONFIG_AD5758 is not set CONFIG_AD5761=m CONFIG_AD5764=m CONFIG_AD5766=y CONFIG_AD5770R=y CONFIG_AD5791=y CONFIG_AD7293=m # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set CONFIG_DPOT_DAC=y CONFIG_DS4424=m # CONFIG_LPC18XX_DAC is not set CONFIG_LTC1660=m CONFIG_LTC2632=y # CONFIG_M62332 is not set CONFIG_MAX517=m CONFIG_MAX5821=m CONFIG_MCP4725=m CONFIG_MCP4922=m # CONFIG_STM32_DAC is not set CONFIG_TI_DAC082S085=y CONFIG_TI_DAC5571=m CONFIG_TI_DAC7311=m CONFIG_TI_DAC7612=y CONFIG_VF610_DAC=m # end of Digital to analog converters # # IIO dummy driver # # end of IIO dummy driver # # Filters # # end of Filters # # Frequency Synthesizers DDS/PLL # # # Clock Generator/Distribution # # CONFIG_AD9523 is not set # end of Clock Generator/Distribution # # Phase-Locked Loop (PLL) frequency synthesizers # CONFIG_ADF4350=y CONFIG_ADF4371=m CONFIG_ADMV1013=m CONFIG_ADMV4420=m CONFIG_ADRF6780=m # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL # # Digital gyroscope sensors # CONFIG_ADIS16080=m CONFIG_ADIS16130=y CONFIG_ADIS16136=y CONFIG_ADIS16260=m # CONFIG_ADXRS290 is not set # CONFIG_ADXRS450 is not set CONFIG_BMG160=m CONFIG_BMG160_I2C=m CONFIG_BMG160_SPI=m CONFIG_FXAS21002C=y CONFIG_FXAS21002C_I2C=m CONFIG_FXAS21002C_SPI=y # CONFIG_MPU3050_I2C is not set # CONFIG_IIO_ST_GYRO_3AXIS is not set CONFIG_ITG3200=m # end of Digital gyroscope sensors # # Health Sensors # # # Heart Rate Monitors # # CONFIG_AFE4403 is not set CONFIG_AFE4404=m CONFIG_MAX30100=m CONFIG_MAX30102=m # end of Heart Rate Monitors # end of Health Sensors # # Humidity sensors # CONFIG_AM2315=m # CONFIG_DHT11 is not set CONFIG_HDC100X=m CONFIG_HDC2010=m CONFIG_HTS221=m CONFIG_HTS221_I2C=m CONFIG_HTS221_SPI=m CONFIG_HTU21=m # CONFIG_SI7005 is not set CONFIG_SI7020=m # end of Humidity sensors # # Inertial measurement units # CONFIG_ADIS16400=m # CONFIG_ADIS16460 is not set CONFIG_ADIS16475=y CONFIG_ADIS16480=y # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set CONFIG_BOSCH_BNO055=m # CONFIG_BOSCH_BNO055_SERIAL is not set CONFIG_BOSCH_BNO055_I2C=m CONFIG_FXOS8700=y # CONFIG_FXOS8700_I2C is not set CONFIG_FXOS8700_SPI=y CONFIG_KMX61=m CONFIG_INV_ICM42600=m CONFIG_INV_ICM42600_I2C=m CONFIG_INV_ICM42600_SPI=m CONFIG_INV_MPU6050_IIO=y # CONFIG_INV_MPU6050_I2C is not set CONFIG_INV_MPU6050_SPI=y # CONFIG_IIO_ST_LSM6DSX is not set CONFIG_IIO_ST_LSM9DS0=y CONFIG_IIO_ST_LSM9DS0_I2C=m # CONFIG_IIO_ST_LSM9DS0_SPI is not set # end of Inertial measurement units CONFIG_IIO_ADIS_LIB=y CONFIG_IIO_ADIS_LIB_BUFFER=y # # Light sensors # # CONFIG_ADJD_S311 is not set # CONFIG_ADUX1020 is not set CONFIG_AL3010=m # CONFIG_AL3320A is not set # CONFIG_APDS9300 is not set CONFIG_APDS9960=m CONFIG_AS73211=m # CONFIG_BH1750 is not set # CONFIG_BH1780 is not set CONFIG_CM32181=m CONFIG_CM3232=m CONFIG_CM3323=m CONFIG_CM3605=m # CONFIG_CM36651 is not set CONFIG_GP2AP002=m CONFIG_GP2AP020A00F=m # CONFIG_IQS621_ALS is not set # CONFIG_SENSORS_ISL29018 is not set # CONFIG_SENSORS_ISL29028 is not set # CONFIG_ISL29125 is not set CONFIG_JSA1212=m CONFIG_RPR0521=m CONFIG_SENSORS_LM3533=m # CONFIG_LTR501 is not set CONFIG_LTRF216A=m CONFIG_LV0104CS=m CONFIG_MAX44000=m # CONFIG_MAX44009 is not set CONFIG_NOA1305=m CONFIG_OPT3001=m CONFIG_PA12203001=m CONFIG_SI1133=m # CONFIG_SI1145 is not set CONFIG_STK3310=m CONFIG_ST_UVIS25=m CONFIG_ST_UVIS25_I2C=m CONFIG_ST_UVIS25_SPI=m # CONFIG_TCS3414 is not set CONFIG_TCS3472=m CONFIG_SENSORS_TSL2563=m CONFIG_TSL2583=m # CONFIG_TSL2591 is not set CONFIG_TSL2772=m CONFIG_TSL4531=m CONFIG_US5182D=m # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set CONFIG_VEML6030=m CONFIG_VEML6070=m CONFIG_VL6180=m CONFIG_ZOPT2201=m # end of Light sensors # # Magnetometer sensors # CONFIG_AK8974=m # CONFIG_AK8975 is not set # CONFIG_AK09911 is not set CONFIG_BMC150_MAGN=m CONFIG_BMC150_MAGN_I2C=m CONFIG_BMC150_MAGN_SPI=m # CONFIG_MAG3110 is not set # CONFIG_MMC35240 is not set CONFIG_IIO_ST_MAGN_3AXIS=y CONFIG_IIO_ST_MAGN_I2C_3AXIS=m # CONFIG_IIO_ST_MAGN_SPI_3AXIS is not set CONFIG_SENSORS_HMC5843=m CONFIG_SENSORS_HMC5843_I2C=m # CONFIG_SENSORS_HMC5843_SPI is not set CONFIG_SENSORS_RM3100=m CONFIG_SENSORS_RM3100_I2C=m # CONFIG_SENSORS_RM3100_SPI is not set # CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors # # Multiplexers # # CONFIG_IIO_MUX is not set # end of Multiplexers # # Inclinometer sensors # # end of Inclinometer sensors CONFIG_IIO_FORMAT_KUNIT_TEST=m # # Triggers - standalone # # CONFIG_IIO_HRTIMER_TRIGGER is not set CONFIG_IIO_INTERRUPT_TRIGGER=y # CONFIG_IIO_STM32_LPTIMER_TRIGGER is not set # CONFIG_IIO_STM32_TIMER_TRIGGER is not set # CONFIG_IIO_TIGHTLOOP_TRIGGER is not set CONFIG_IIO_SYSFS_TRIGGER=y # end of Triggers - standalone # # Linear and angular position sensors # CONFIG_IQS624_POS=m # end of Linear and angular position sensors # # Digital potentiometers # CONFIG_AD5110=m # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set CONFIG_MAX5432=m # CONFIG_MAX5481 is not set CONFIG_MAX5487=m CONFIG_MCP4018=m # CONFIG_MCP4131 is not set CONFIG_MCP4531=m CONFIG_MCP41010=m CONFIG_TPL0102=m # end of Digital potentiometers # # Digital potentiostats # CONFIG_LMP91000=m # end of Digital potentiostats # # Pressure sensors # CONFIG_ABP060MG=m # CONFIG_BMP280 is not set # CONFIG_DLHL60D is not set CONFIG_DPS310=m # CONFIG_HP03 is not set CONFIG_ICP10100=m CONFIG_MPL115=y CONFIG_MPL115_I2C=m CONFIG_MPL115_SPI=y # CONFIG_MPL3115 is not set # CONFIG_MS5611 is not set # CONFIG_MS5637 is not set CONFIG_IIO_ST_PRESS=m # CONFIG_IIO_ST_PRESS_I2C is not set # CONFIG_IIO_ST_PRESS_SPI is not set CONFIG_T5403=m # CONFIG_HP206C is not set # CONFIG_ZPA2326 is not set # end of Pressure sensors # # Lightning sensors # # CONFIG_AS3935 is not set # end of Lightning sensors # # Proximity and distance sensors # CONFIG_ISL29501=m # CONFIG_LIDAR_LITE_V2 is not set CONFIG_MB1232=m # CONFIG_PING is not set CONFIG_RFD77402=m CONFIG_SRF04=m CONFIG_SX_COMMON=m CONFIG_SX9310=m CONFIG_SX9324=m # CONFIG_SX9360 is not set CONFIG_SX9500=m CONFIG_SRF08=m CONFIG_VCNL3020=m CONFIG_VL53L0X_I2C=m # end of Proximity and distance sensors # # Resolver to digital converters # CONFIG_AD2S90=y CONFIG_AD2S1200=y # end of Resolver to digital converters # # Temperature sensors # # CONFIG_IQS620AT_TEMP is not set # CONFIG_LTC2983 is not set # CONFIG_MAXIM_THERMOCOUPLE is not set CONFIG_MLX90614=m CONFIG_MLX90632=m CONFIG_TMP006=m CONFIG_TMP007=m CONFIG_TMP117=m CONFIG_TSYS01=m CONFIG_TSYS02D=m CONFIG_MAX31856=y # CONFIG_MAX31865 is not set # end of Temperature sensors CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL is not set # CONFIG_PWM_ATMEL_TCB is not set # CONFIG_PWM_BCM_IPROC is not set # CONFIG_PWM_BCM_KONA is not set # CONFIG_PWM_BCM2835 is not set # CONFIG_PWM_BERLIN is not set # CONFIG_PWM_BRCMSTB is not set # CONFIG_PWM_CLK is not set # CONFIG_PWM_CLPS711X is not set # CONFIG_PWM_EP93XX is not set CONFIG_PWM_FSL_FTM=y # CONFIG_PWM_HIBVT is not set # CONFIG_PWM_IMG is not set CONFIG_PWM_IMX1=y # CONFIG_PWM_IMX27 is not set CONFIG_PWM_IMX_TPM=y # CONFIG_PWM_INTEL_LGM is not set # CONFIG_PWM_IQS620A is not set # CONFIG_PWM_JZ4740 is not set # CONFIG_PWM_KEEMBAY is not set # CONFIG_PWM_LP3943 is not set # CONFIG_PWM_LPC18XX_SCT is not set # CONFIG_PWM_LPC32XX is not set # CONFIG_PWM_LPSS_PLATFORM is not set # CONFIG_PWM_MESON is not set # CONFIG_PWM_MTK_DISP is not set # CONFIG_PWM_MEDIATEK is not set # CONFIG_PWM_MXS is not set CONFIG_PWM_NTXEC=m # CONFIG_PWM_OMAP_DMTIMER is not set # CONFIG_PWM_PCA9685 is not set # CONFIG_PWM_PXA is not set # CONFIG_PWM_RASPBERRYPI_POE is not set # CONFIG_PWM_RCAR is not set # CONFIG_PWM_RENESAS_TPU is not set # CONFIG_PWM_ROCKCHIP is not set # CONFIG_PWM_SAMSUNG is not set # CONFIG_PWM_SIFIVE is not set # CONFIG_PWM_SL28CPLD is not set # CONFIG_PWM_SPEAR is not set # CONFIG_PWM_SPRD is not set # CONFIG_PWM_STI is not set # CONFIG_PWM_STM32 is not set # CONFIG_PWM_STM32_LP is not set # CONFIG_PWM_SUN4I is not set # CONFIG_PWM_SUNPLUS is not set # CONFIG_PWM_TEGRA is not set # CONFIG_PWM_TIECAP is not set # CONFIG_PWM_TIEHRPWM is not set # CONFIG_PWM_VISCONTI is not set # CONFIG_PWM_VT8500 is not set # CONFIG_PWM_XILINX is not set # # IRQ chip support # CONFIG_IRQCHIP=y CONFIG_ARM_NVIC=y # CONFIG_AL_FIC is not set CONFIG_MADERA_IRQ=m # CONFIG_JCORE_AIC is not set # CONFIG_RENESAS_INTC_IRQPIN is not set # CONFIG_RENESAS_IRQC is not set # CONFIG_RENESAS_RZA1_IRQC is not set # CONFIG_RENESAS_RZG2L_IRQC is not set # CONFIG_SL28CPLD_INTC is not set # CONFIG_TS4800_IRQ is not set # CONFIG_XILINX_INTC is not set # CONFIG_INGENIC_TCU_IRQ is not set # CONFIG_IRQ_UNIPHIER_AIDET is not set # CONFIG_MESON_IRQ_GPIO is not set CONFIG_IMX_IRQSTEER=y CONFIG_IMX_INTMUX=y # CONFIG_IMX_MU_MSI is not set # CONFIG_EXYNOS_IRQ_COMBINER is not set # CONFIG_MST_IRQ is not set CONFIG_MCHP_EIC=y # CONFIG_SUNPLUS_SP7021_INTC is not set # end of IRQ chip support CONFIG_IPACK_BUS=m # CONFIG_SERIAL_IPOCTAL is not set CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_A10SR is not set # CONFIG_RESET_ATH79 is not set # CONFIG_RESET_AXS10X is not set # CONFIG_RESET_BCM6345 is not set # CONFIG_RESET_BERLIN is not set # CONFIG_RESET_BRCMSTB is not set # CONFIG_RESET_BRCMSTB_RESCAL is not set # CONFIG_RESET_HSDK is not set # CONFIG_RESET_IMX7 is not set # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_K210 is not set # CONFIG_RESET_LANTIQ is not set # CONFIG_RESET_LPC18XX is not set # CONFIG_RESET_MCHP_SPARX5 is not set # CONFIG_RESET_MESON is not set # CONFIG_RESET_MESON_AUDIO_ARB is not set # CONFIG_RESET_NPCM is not set # CONFIG_RESET_PISTACHIO is not set # CONFIG_RESET_QCOM_AOSS is not set # CONFIG_RESET_QCOM_PDC is not set # CONFIG_RESET_RASPBERRYPI is not set # CONFIG_RESET_RZG2L_USBPHY_CTRL is not set # CONFIG_RESET_SCMI is not set # CONFIG_RESET_SIMPLE is not set # CONFIG_RESET_SOCFPGA is not set # CONFIG_RESET_STARFIVE_JH7100 is not set # CONFIG_RESET_SUNPLUS is not set # CONFIG_RESET_SUNXI is not set # CONFIG_RESET_TI_SCI is not set CONFIG_RESET_TI_SYSCON=y CONFIG_RESET_TI_TPS380X=y # CONFIG_RESET_TN48M_CPLD is not set # CONFIG_RESET_UNIPHIER is not set # CONFIG_RESET_UNIPHIER_GLUE is not set # CONFIG_RESET_ZYNQ is not set # CONFIG_COMMON_RESET_HI3660 is not set # CONFIG_COMMON_RESET_HI6220 is not set # # PHY Subsystem # CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PHY_MIPI_DPHY=y # CONFIG_PHY_LPC18XX_USB_OTG is not set # CONFIG_PHY_PISTACHIO_USB is not set # CONFIG_PHY_XGENE is not set # CONFIG_USB_LGM_PHY is not set CONFIG_PHY_CAN_TRANSCEIVER=m # CONFIG_PHY_SUN4I_USB is not set # CONFIG_PHY_SUN6I_MIPI_DPHY is not set # CONFIG_PHY_SUN9I_USB is not set # CONFIG_PHY_SUN50I_USB3 is not set # CONFIG_PHY_MESON8_HDMI_TX is not set # CONFIG_PHY_MESON8B_USB2 is not set # CONFIG_PHY_MESON_GXL_USB2 is not set # CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG is not set # CONFIG_PHY_MESON_G12A_USB2 is not set # CONFIG_PHY_MESON_G12A_USB3_PCIE is not set # CONFIG_PHY_MESON_AXG_PCIE is not set # CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG is not set # CONFIG_PHY_MESON_AXG_MIPI_DPHY is not set # # PHY drivers for Broadcom platforms # # CONFIG_PHY_BCM63XX_USBH is not set # CONFIG_PHY_CYGNUS_PCIE is not set # CONFIG_PHY_BCM_SR_USB is not set CONFIG_BCM_KONA_USB2_PHY=m # CONFIG_PHY_BCM_NS_USB2 is not set # CONFIG_PHY_NS2_USB_DRD is not set # CONFIG_PHY_BRCM_SATA is not set # CONFIG_PHY_BRCM_USB is not set # CONFIG_PHY_BCM_SR_PCIE is not set # end of PHY drivers for Broadcom platforms CONFIG_PHY_CADENCE_TORRENT=m CONFIG_PHY_CADENCE_DPHY=m CONFIG_PHY_CADENCE_DPHY_RX=m CONFIG_PHY_CADENCE_SIERRA=m CONFIG_PHY_CADENCE_SALVO=y # CONFIG_PHY_FSL_IMX8MQ_USB is not set # CONFIG_PHY_MIXEL_LVDS_PHY is not set # CONFIG_PHY_MIXEL_MIPI_DPHY is not set # CONFIG_PHY_FSL_IMX8M_PCIE is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_HI6220_USB is not set # CONFIG_PHY_HI3660_USB is not set # CONFIG_PHY_HI3670_USB is not set # CONFIG_PHY_HI3670_PCIE is not set # CONFIG_PHY_HISTB_COMBPHY is not set # CONFIG_PHY_HISI_INNO_USB2 is not set # CONFIG_PHY_INGENIC_USB is not set # CONFIG_PHY_LANTIQ_VRX200_PCIE is not set # CONFIG_PHY_LANTIQ_RCU_USB2 is not set # CONFIG_ARMADA375_USBCLUSTER_PHY is not set # CONFIG_PHY_BERLIN_SATA is not set # CONFIG_PHY_BERLIN_USB is not set CONFIG_PHY_MVEBU_A3700_UTMI=y # CONFIG_PHY_MVEBU_A38X_COMPHY is not set # CONFIG_PHY_MVEBU_CP110_UTMI is not set CONFIG_PHY_PXA_28NM_HSIC=m CONFIG_PHY_PXA_28NM_USB2=y # CONFIG_PHY_PXA_USB is not set # CONFIG_PHY_MMP3_USB is not set # CONFIG_PHY_MMP3_HSIC is not set # CONFIG_PHY_MTK_PCIE is not set # CONFIG_PHY_MTK_TPHY is not set # CONFIG_PHY_MTK_UFS is not set # CONFIG_PHY_MTK_XSPHY is not set # CONFIG_PHY_MTK_HDMI is not set # CONFIG_PHY_MTK_MIPI_DSI is not set # CONFIG_PHY_MTK_DP is not set # CONFIG_PHY_SPARX5_SERDES is not set CONFIG_PHY_LAN966X_SERDES=y CONFIG_PHY_CPCAP_USB=y CONFIG_PHY_MAPPHONE_MDM6600=y CONFIG_PHY_OCELOT_SERDES=m CONFIG_PHY_ATH79_USB=y # CONFIG_PHY_QCOM_EDP is not set # CONFIG_PHY_QCOM_IPQ4019_USB is not set # CONFIG_PHY_QCOM_PCIE2 is not set # CONFIG_PHY_QCOM_QMP is not set # CONFIG_PHY_QCOM_QUSB2 is not set # CONFIG_PHY_QCOM_USB_HS is not set # CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set CONFIG_PHY_QCOM_USB_HSIC=m # CONFIG_PHY_QCOM_USB_HS_28NM is not set # CONFIG_PHY_QCOM_USB_SS is not set # CONFIG_PHY_QCOM_IPQ806X_USB is not set # CONFIG_PHY_MT7621_PCI is not set # CONFIG_PHY_RALINK_USB is not set # CONFIG_PHY_RCAR_GEN3_USB3 is not set # CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set # CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set # CONFIG_PHY_ROCKCHIP_INNO_USB2 is not set # CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set # CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set # CONFIG_PHY_ROCKCHIP_PCIE is not set # CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 is not set # CONFIG_PHY_ROCKCHIP_TYPEC is not set # CONFIG_PHY_EXYNOS_DP_VIDEO is not set # CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set # CONFIG_PHY_EXYNOS_PCIE is not set # CONFIG_PHY_SAMSUNG_UFS is not set CONFIG_PHY_SAMSUNG_USB2=m # CONFIG_PHY_S5PV210_USB2 is not set CONFIG_PHY_EXYNOS5_USBDRD=m # CONFIG_PHY_UNIPHIER_USB2 is not set # CONFIG_PHY_UNIPHIER_USB3 is not set # CONFIG_PHY_UNIPHIER_PCIE is not set # CONFIG_PHY_UNIPHIER_AHCI is not set # CONFIG_PHY_ST_SPEAR1310_MIPHY is not set # CONFIG_PHY_ST_SPEAR1340_MIPHY is not set # CONFIG_PHY_STIH407_USB is not set # CONFIG_PHY_STM32_USBPHYC is not set # CONFIG_PHY_SUNPLUS_USB is not set # CONFIG_PHY_TEGRA194_P2U is not set # CONFIG_PHY_DA8XX_USB is not set # CONFIG_PHY_DM816X_USB is not set # CONFIG_PHY_AM654_SERDES is not set # CONFIG_PHY_J721E_WIZ is not set # CONFIG_OMAP_CONTROL_PHY is not set # CONFIG_TI_PIPE3 is not set CONFIG_PHY_TUSB1210=m # CONFIG_PHY_INTEL_KEEMBAY_EMMC is not set # CONFIG_PHY_INTEL_KEEMBAY_USB is not set # CONFIG_PHY_INTEL_LGM_COMBO is not set # CONFIG_PHY_INTEL_LGM_EMMC is not set # CONFIG_PHY_INTEL_THUNDERBAY_EMMC is not set # CONFIG_PHY_XILINX_ZYNQMP is not set # end of PHY Subsystem # CONFIG_POWERCAP is not set CONFIG_MCB=y CONFIG_MCB_LPC=m # # Performance monitor support # # CONFIG_ARM_CCN is not set # CONFIG_ARM_CMN is not set # CONFIG_ARM_PMU is not set CONFIG_FSL_IMX8_DDR_PMU=y # CONFIG_ARM_DMC620_PMU is not set # CONFIG_ALIBABA_UNCORE_DRW_PMU is not set # end of Performance monitor support CONFIG_RAS=y # # Android # # end of Android # CONFIG_DAX is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y # CONFIG_NVMEM_APPLE_EFUSES is not set # CONFIG_NVMEM_BCM_OCOTP is not set # CONFIG_NVMEM_BRCM_NVRAM is not set # CONFIG_NVMEM_IMX_IIM is not set # CONFIG_NVMEM_IMX_OCOTP is not set # CONFIG_NVMEM_JZ4780_EFUSE is not set # CONFIG_NVMEM_LAN9662_OTPC is not set # CONFIG_NVMEM_LAYERSCAPE_SFP is not set # CONFIG_NVMEM_LPC18XX_EEPROM is not set # CONFIG_NVMEM_LPC18XX_OTP is not set # CONFIG_NVMEM_MESON_MX_EFUSE is not set CONFIG_NVMEM_MICROCHIP_OTPC=y # CONFIG_NVMEM_MTK_EFUSE is not set # CONFIG_NVMEM_MXS_OCOTP is not set # CONFIG_NVMEM_NINTENDO_OTP is not set # CONFIG_NVMEM_QCOM_QFPROM is not set CONFIG_NVMEM_RMEM=m # CONFIG_NVMEM_ROCKCHIP_EFUSE is not set # CONFIG_NVMEM_ROCKCHIP_OTP is not set # CONFIG_NVMEM_SC27XX_EFUSE is not set CONFIG_NVMEM_SNVS_LPGPR=m CONFIG_NVMEM_SPMI_SDAM=m # CONFIG_NVMEM_SPRD_EFUSE is not set # CONFIG_NVMEM_STM32_ROMEM is not set # CONFIG_NVMEM_SUNPLUS_OCOTP is not set # CONFIG_NVMEM_UNIPHIER_EFUSE is not set # CONFIG_NVMEM_VF610_OCOTP is not set # # HW tracing support # CONFIG_STM=m CONFIG_STM_PROTO_BASIC=m CONFIG_STM_PROTO_SYS_T=m CONFIG_STM_DUMMY=m CONFIG_STM_SOURCE_CONSOLE=m CONFIG_STM_SOURCE_HEARTBEAT=m CONFIG_INTEL_TH=y CONFIG_INTEL_TH_GTH=y # CONFIG_INTEL_TH_STH is not set CONFIG_INTEL_TH_MSU=y CONFIG_INTEL_TH_PTI=m CONFIG_INTEL_TH_DEBUG=y # end of HW tracing support # CONFIG_FPGA is not set CONFIG_FSI=m # CONFIG_FSI_NEW_DEV_NODE is not set CONFIG_FSI_MASTER_GPIO=m CONFIG_FSI_MASTER_HUB=m # CONFIG_FSI_MASTER_ASPEED is not set # CONFIG_FSI_SCOM is not set # CONFIG_FSI_SBEFIFO is not set # CONFIG_TEE is not set CONFIG_MULTIPLEXER=y # # Multiplexer drivers # CONFIG_MUX_ADG792A=m CONFIG_MUX_ADGS1408=y CONFIG_MUX_GPIO=m CONFIG_MUX_MMIO=m # end of Multiplexer drivers CONFIG_PM_OPP=y CONFIG_SIOX=m CONFIG_SIOX_BUS_GPIO=m # CONFIG_SLIMBUS is not set CONFIG_INTERCONNECT=y CONFIG_INTERCONNECT_IMX=m CONFIG_INTERCONNECT_IMX8MM=m CONFIG_INTERCONNECT_IMX8MN=m # CONFIG_INTERCONNECT_IMX8MQ is not set CONFIG_INTERCONNECT_IMX8MP=m # CONFIG_INTERCONNECT_QCOM_OSM_L3 is not set # CONFIG_INTERCONNECT_SAMSUNG is not set CONFIG_COUNTER=m # CONFIG_104_QUAD_8 is not set # CONFIG_INTERRUPT_CNT is not set # CONFIG_STM32_TIMER_CNT is not set # CONFIG_STM32_LPTIMER_CNT is not set # CONFIG_TI_EQEP is not set # CONFIG_FTM_QUADDEC is not set CONFIG_MICROCHIP_TCB_CAPTURE=m # CONFIG_TI_ECAP_CAPTURE is not set CONFIG_MOST=m CONFIG_MOST_USB_HDM=m # CONFIG_MOST_CDEV is not set CONFIG_PECI=y CONFIG_PECI_CPU=y # CONFIG_PECI_ASPEED is not set # CONFIG_HTE is not set # end of Device Drivers # # File systems # CONFIG_VALIDATE_FS_PARSER=y CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set CONFIG_FILE_LOCKING=y CONFIG_FS_ENCRYPTION=y CONFIG_FS_VERITY=y # CONFIG_FS_VERITY_DEBUG is not set # CONFIG_FS_VERITY_BUILTIN_SIGNATURES is not set CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y CONFIG_FANOTIFY=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set # CONFIG_QUOTA_DEBUG is not set CONFIG_QUOTA_TREE=m CONFIG_QFMT_V1=y CONFIG_QFMT_V2=m CONFIG_QUOTACTL=y CONFIG_AUTOFS4_FS=m CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=y CONFIG_CUSE=m # CONFIG_VIRTIO_FS is not set CONFIG_OVERLAY_FS=m CONFIG_OVERLAY_FS_REDIRECT_DIR=y CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # CONFIG_OVERLAY_FS_INDEX is not set # CONFIG_OVERLAY_FS_METACOPY is not set # # Caches # CONFIG_NETFS_SUPPORT=m CONFIG_FSCACHE=m # CONFIG_FSCACHE_DEBUG is not set # end of Caches # # Pseudo filesystems # # CONFIG_PROC_FS is not set CONFIG_KERNFS=y CONFIG_SYSFS=y CONFIG_CONFIGFS_FS=y # end of Pseudo filesystems # CONFIG_MISC_FILESYSTEMS is not set # CONFIG_NETWORK_FILESYSTEMS is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=m # CONFIG_NLS_CODEPAGE_737 is not set CONFIG_NLS_CODEPAGE_775=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_CODEPAGE_852=m # CONFIG_NLS_CODEPAGE_855 is not set CONFIG_NLS_CODEPAGE_857=m # CONFIG_NLS_CODEPAGE_860 is not set CONFIG_NLS_CODEPAGE_861=y CONFIG_NLS_CODEPAGE_862=y CONFIG_NLS_CODEPAGE_863=y CONFIG_NLS_CODEPAGE_864=m # CONFIG_NLS_CODEPAGE_865 is not set CONFIG_NLS_CODEPAGE_866=y CONFIG_NLS_CODEPAGE_869=y CONFIG_NLS_CODEPAGE_936=y CONFIG_NLS_CODEPAGE_950=m CONFIG_NLS_CODEPAGE_932=m CONFIG_NLS_CODEPAGE_949=m CONFIG_NLS_CODEPAGE_874=m # CONFIG_NLS_ISO8859_8 is not set # CONFIG_NLS_CODEPAGE_1250 is not set CONFIG_NLS_CODEPAGE_1251=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=m CONFIG_NLS_ISO8859_2=m # CONFIG_NLS_ISO8859_3 is not set # CONFIG_NLS_ISO8859_4 is not set CONFIG_NLS_ISO8859_5=y CONFIG_NLS_ISO8859_6=m # CONFIG_NLS_ISO8859_7 is not set CONFIG_NLS_ISO8859_9=m # CONFIG_NLS_ISO8859_13 is not set # CONFIG_NLS_ISO8859_14 is not set # CONFIG_NLS_ISO8859_15 is not set CONFIG_NLS_KOI8_R=y # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_MAC_ROMAN is not set # CONFIG_NLS_MAC_CELTIC is not set # CONFIG_NLS_MAC_CENTEURO is not set CONFIG_NLS_MAC_CROATIAN=m CONFIG_NLS_MAC_CYRILLIC=m # CONFIG_NLS_MAC_GAELIC is not set # CONFIG_NLS_MAC_GREEK is not set # CONFIG_NLS_MAC_ICELAND is not set CONFIG_NLS_MAC_INUIT=m # CONFIG_NLS_MAC_ROMANIAN is not set # CONFIG_NLS_MAC_TURKISH is not set # CONFIG_NLS_UTF8 is not set CONFIG_DLM=y CONFIG_DLM_DEPRECATED_API=y # CONFIG_DLM_DEBUG is not set CONFIG_UNICODE=y CONFIG_UNICODE_NORMALIZATION_SELFTEST=m CONFIG_IO_WQ=y # end of File systems # # Security options # CONFIG_KEYS=y # CONFIG_KEYS_REQUEST_CACHE is not set # CONFIG_PERSISTENT_KEYRINGS is not set # CONFIG_TRUSTED_KEYS is not set CONFIG_ENCRYPTED_KEYS=y CONFIG_USER_DECRYPTED_DATA=y CONFIG_KEY_DH_OPERATIONS=y # CONFIG_KEY_NOTIFICATIONS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SECURITYFS is not set CONFIG_FORTIFY_SOURCE=y CONFIG_STATIC_USERMODEHELPER=y CONFIG_STATIC_USERMODEHELPER_PATH="/sbin/usermode-helper" CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf" # # Kernel hardening options # # # Memory initialization # CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y # CONFIG_INIT_STACK_NONE is not set # CONFIG_INIT_STACK_ALL_PATTERN is not set CONFIG_INIT_STACK_ALL_ZERO=y # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set CONFIG_INIT_ON_FREE_DEFAULT_ON=y # end of Memory initialization CONFIG_CC_HAS_RANDSTRUCT=y # CONFIG_RANDSTRUCT_NONE is not set CONFIG_RANDSTRUCT_FULL=y CONFIG_RANDSTRUCT=y # end of Kernel hardening options # end of Security options CONFIG_CRYPTO=y # # Crypto core or helper # CONFIG_CRYPTO_FIPS=y CONFIG_CRYPTO_FIPS_NAME="Linux Kernel Cryptographic API" CONFIG_CRYPTO_FIPS_CUSTOM_VERSION=y CONFIG_CRYPTO_FIPS_VERSION="(none)" CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_AKCIPHER2=y CONFIG_CRYPTO_AKCIPHER=y CONFIG_CRYPTO_KPP2=y CONFIG_CRYPTO_KPP=y CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_USER is not set # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set # CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_AUTHENC=y CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_ENGINE=y # end of Crypto core or helper # # Public-key cryptography # CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_ECC=y CONFIG_CRYPTO_ECDH=m CONFIG_CRYPTO_ECDSA=y CONFIG_CRYPTO_ECRDSA=y # CONFIG_CRYPTO_SM2 is not set CONFIG_CRYPTO_CURVE25519=m # end of Public-key cryptography # # Block ciphers # CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set CONFIG_CRYPTO_ARIA=m CONFIG_CRYPTO_BLOWFISH=y CONFIG_CRYPTO_BLOWFISH_COMMON=y CONFIG_CRYPTO_CAMELLIA=y # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_SM4=m CONFIG_CRYPTO_SM4_GENERIC=m CONFIG_CRYPTO_TWOFISH=y CONFIG_CRYPTO_TWOFISH_COMMON=y # end of Block ciphers # # Length-preserving ciphers and modes # CONFIG_CRYPTO_ADIANTUM=m CONFIG_CRYPTO_CHACHA20=y CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CFB=m CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_CTS=y CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_HCTR2=m CONFIG_CRYPTO_KEYWRAP=m # CONFIG_CRYPTO_LRW is not set # CONFIG_CRYPTO_OFB is not set # CONFIG_CRYPTO_PCBC is not set CONFIG_CRYPTO_XCTR=m CONFIG_CRYPTO_XTS=y CONFIG_CRYPTO_NHPOLY1305=m # end of Length-preserving ciphers and modes # # AEAD (authenticated encryption with associated data) ciphers # # CONFIG_CRYPTO_AEGIS128 is not set CONFIG_CRYPTO_CHACHA20POLY1305=y CONFIG_CRYPTO_CCM=m CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_SEQIV=m CONFIG_CRYPTO_ECHAINIV=y CONFIG_CRYPTO_ESSIV=m # end of AEAD (authenticated encryption with associated data) ciphers # # Hashes, digests, and MACs # # CONFIG_CRYPTO_BLAKE2B is not set CONFIG_CRYPTO_CMAC=m CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_POLYVAL=m CONFIG_CRYPTO_POLY1305=y CONFIG_CRYPTO_RMD160=y CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_SHA3 is not set CONFIG_CRYPTO_SM3=m # CONFIG_CRYPTO_SM3_GENERIC is not set CONFIG_CRYPTO_STREEBOG=y # CONFIG_CRYPTO_VMAC is not set # CONFIG_CRYPTO_WP512 is not set # CONFIG_CRYPTO_XCBC is not set # CONFIG_CRYPTO_XXHASH is not set # end of Hashes, digests, and MACs # # CRCs (cyclic redundancy checks) # CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_CRC32 is not set CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_CRC64_ROCKSOFT=m # end of CRCs (cyclic redundancy checks) # # Compression # CONFIG_CRYPTO_DEFLATE=m # CONFIG_CRYPTO_LZO is not set # CONFIG_CRYPTO_842 is not set # CONFIG_CRYPTO_LZ4 is not set CONFIG_CRYPTO_LZ4HC=m # CONFIG_CRYPTO_ZSTD is not set # end of Compression # # Random number generation # CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_DRBG_MENU=y CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_HASH is not set # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_KDF800108_CTR=y # end of Random number generation # # Userspace interface # CONFIG_CRYPTO_USER_API=y CONFIG_CRYPTO_USER_API_HASH=m # CONFIG_CRYPTO_USER_API_SKCIPHER is not set # CONFIG_CRYPTO_USER_API_RNG is not set CONFIG_CRYPTO_USER_API_AEAD=y # CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set # end of Userspace interface CONFIG_CRYPTO_HASH_INFO=y # # Accelerated Cryptographic Algorithms for CPU (arm) # CONFIG_CRYPTO_POLY1305_ARM=m CONFIG_CRYPTO_BLAKE2S_ARM=y CONFIG_CRYPTO_SHA1_ARM=m CONFIG_CRYPTO_AES_ARM=m # CONFIG_CRYPTO_CHACHA20_NEON is not set # end of Accelerated Cryptographic Algorithms for CPU (arm) CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_ALLWINNER is not set # CONFIG_CRYPTO_DEV_SL3516 is not set CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y CONFIG_CRYPTO_DEV_FSL_CAAM=y CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG=y CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 CONFIG_CRYPTO_DEV_FSL_CAAM_INTC=y CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD=255 CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD=2048 CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y # CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API is not set # CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API is not set CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API=y CONFIG_CRYPTO_DEV_SAHARA=y # CONFIG_CRYPTO_DEV_EXYNOS_RNG is not set # CONFIG_CRYPTO_DEV_S5P is not set CONFIG_CRYPTO_DEV_ATMEL_AUTHENC=y CONFIG_CRYPTO_DEV_ATMEL_AES=y CONFIG_CRYPTO_DEV_ATMEL_TDES=m CONFIG_CRYPTO_DEV_ATMEL_SHA=y CONFIG_CRYPTO_DEV_ATMEL_I2C=m CONFIG_CRYPTO_DEV_ATMEL_ECC=m CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m CONFIG_CRYPTO_DEV_MXS_DCP=m # CONFIG_CRYPTO_DEV_QCE is not set # CONFIG_CRYPTO_DEV_QCOM_RNG is not set # CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set # CONFIG_CRYPTO_DEV_ZYNQMP_AES is not set # CONFIG_CRYPTO_DEV_ZYNQMP_SHA3 is not set CONFIG_CRYPTO_DEV_VIRTIO=m # CONFIG_CRYPTO_DEV_SAFEXCEL is not set # CONFIG_CRYPTO_DEV_ARTPEC6 is not set CONFIG_CRYPTO_DEV_CCREE=m # CONFIG_CRYPTO_DEV_HISI_SEC is not set CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y # CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set # CONFIG_CRYPTO_DEV_SA2UL is not set # CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4 is not set # CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECC is not set # CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU is not set # CONFIG_CRYPTO_DEV_ASPEED is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y CONFIG_PKCS8_PRIVATE_KEY_PARSER=y CONFIG_PKCS7_MESSAGE_PARSER=y CONFIG_PKCS7_TEST_KEY=m # CONFIG_SIGNED_PE_FILE_VERIFICATION is not set # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # # Certificates for signature checking # CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" CONFIG_MODULE_SIG_KEY_TYPE_RSA=y # CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set CONFIG_SYSTEM_TRUSTED_KEYRING=y CONFIG_SYSTEM_TRUSTED_KEYS="" # CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set CONFIG_SECONDARY_TRUSTED_KEYRING=y # CONFIG_SYSTEM_BLACKLIST_KEYRING is not set # end of Certificates for signature checking CONFIG_BINARY_PRINTF=y # # Library routines # CONFIG_LINEAR_RANGES=y # CONFIG_PACKING is not set CONFIG_BITREVERSE=y CONFIG_HAVE_ARCH_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y CONFIG_CORDIC=y CONFIG_PRIME_NUMBERS=m CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_STMP_DEVICE=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y # # Crypto library routines # CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y CONFIG_CRYPTO_LIB_CHACHA=m CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m CONFIG_CRYPTO_LIB_CURVE25519=m CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC_T10DIF=m CONFIG_CRC64_ROCKSOFT=m CONFIG_CRC_ITU_T=y CONFIG_CRC32=y CONFIG_CRC32_SELFTEST=m # CONFIG_CRC32_SLICEBY8 is not set # CONFIG_CRC32_SLICEBY4 is not set CONFIG_CRC32_SARWATE=y # CONFIG_CRC32_BIT is not set CONFIG_CRC64=m CONFIG_CRC4=y # CONFIG_CRC7 is not set CONFIG_LIBCRC32C=y CONFIG_CRC8=y # CONFIG_RANDOM32_SELFTEST is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4HC_COMPRESS=m CONFIG_LZ4_DECOMPRESS=m CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y # CONFIG_XZ_DEC_POWERPC is not set # CONFIG_XZ_DEC_IA64 is not set # CONFIG_XZ_DEC_ARM is not set CONFIG_XZ_DEC_ARMTHUMB=y # CONFIG_XZ_DEC_SPARC is not set CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_BCJ=y CONFIG_XZ_DEC_TEST=m CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_LZMA=y CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_REED_SOLOMON=y CONFIG_REED_SOLOMON_ENC16=y CONFIG_REED_SOLOMON_DEC16=y CONFIG_INTERVAL_TREE=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_DMA=y CONFIG_DMA_OPS=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_GLOBAL_POOL=y # CONFIG_DMA_API_DEBUG is not set # CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_DQL=y CONFIG_GLOB=y # CONFIG_GLOB_SELFTEST is not set CONFIG_NLATTR=y CONFIG_GENERIC_ATOMIC64=y CONFIG_CLZ_TAB=y CONFIG_IRQ_POLL=y CONFIG_MPILIB=y CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_STACKDEPOT=y CONFIG_REF_TRACKER=y # CONFIG_PARMAN is not set # CONFIG_OBJAGG is not set # end of Library routines CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y # # Kernel hacking # # # printk and dmesg options # CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_SYMBOLIC_ERRNAME is not set CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y # # Compile-time checks and compiler options # CONFIG_AS_HAS_NON_CONST_LEB128=y CONFIG_DEBUG_INFO_NONE=y # CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set # CONFIG_DEBUG_INFO_DWARF4 is not set # CONFIG_DEBUG_INFO_DWARF5 is not set CONFIG_FRAME_WARN=1024 CONFIG_STRIP_ASM_SYMS=y # CONFIG_HEADERS_INSTALL is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y CONFIG_VMLINUX_MAP=y # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options # # Generic Kernel Debugging Instruments # CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 CONFIG_MAGIC_SYSRQ_SERIAL=y CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" CONFIG_DEBUG_FS=y # CONFIG_DEBUG_FS_ALLOW_ALL is not set # CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set CONFIG_DEBUG_FS_ALLOW_NONE=y CONFIG_UBSAN=y CONFIG_CC_HAS_UBSAN_BOUNDS=y CONFIG_CC_HAS_UBSAN_ARRAY_BOUNDS=y # CONFIG_UBSAN_BOUNDS is not set CONFIG_UBSAN_SHIFT=y CONFIG_UBSAN_UNREACHABLE=y CONFIG_UBSAN_BOOL=y CONFIG_UBSAN_ENUM=y CONFIG_TEST_UBSAN=m # end of Generic Kernel Debugging Instruments # # Networking Debugging # CONFIG_NET_DEV_REFCNT_TRACKER=y CONFIG_NET_NS_REFCNT_TRACKER=y CONFIG_DEBUG_NET=y # end of Networking Debugging # # Memory Debugging # CONFIG_PAGE_EXTENSION=y # CONFIG_DEBUG_PAGEALLOC is not set CONFIG_PAGE_OWNER=y # CONFIG_PAGE_POISONING is not set CONFIG_DEBUG_OBJECTS=y # CONFIG_DEBUG_OBJECTS_SELFTEST is not set CONFIG_DEBUG_OBJECTS_FREE=y # CONFIG_DEBUG_OBJECTS_TIMERS is not set CONFIG_DEBUG_OBJECTS_WORK=y # CONFIG_DEBUG_OBJECTS_RCU_HEAD is not set CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 CONFIG_SHRINKER_DEBUG=y CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_SCHED_STACK_END_CHECK=y CONFIG_DEBUG_VM_IRQSOFF=y CONFIG_DEBUG_VM=y # CONFIG_DEBUG_VM_MAPLE_TREE is not set # CONFIG_DEBUG_VM_RB is not set # CONFIG_DEBUG_VM_PGFLAGS is not set CONFIG_DEBUG_NOMMU_REGIONS=y # CONFIG_DEBUG_MEMORY_INIT is not set CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # end of Memory Debugging CONFIG_DEBUG_SHIRQ=y # # Debug Oops, Lockups and Hangs # CONFIG_PANIC_ON_OOPS=y CONFIG_PANIC_ON_OOPS_VALUE=1 CONFIG_PANIC_TIMEOUT=0 CONFIG_LOCKUP_DETECTOR=y CONFIG_SOFTLOCKUP_DETECTOR=y CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y # CONFIG_DETECT_HUNG_TASK is not set # CONFIG_WQ_WATCHDOG is not set CONFIG_TEST_LOCKUP=m # end of Debug Oops, Lockups and Hangs # # Scheduler Debugging # # end of Scheduler Debugging CONFIG_DEBUG_TIMEKEEPING=y # # Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_DEBUG_RT_MUTEXES=y # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_MUTEXES is not set CONFIG_DEBUG_RWSEMS=y CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_DEBUG_LOCKING_API_SELFTESTS=y # CONFIG_LOCK_TORTURE_TEST is not set CONFIG_WW_MUTEX_SELFTEST=y # CONFIG_SCF_TORTURE_TEST is not set # end of Lock Debugging (spinlocks, mutexes, etc...) CONFIG_DEBUG_IRQFLAGS=y CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set # # Debug kernel data structures # CONFIG_DEBUG_LIST=y # CONFIG_DEBUG_PLIST is not set CONFIG_DEBUG_SG=y CONFIG_DEBUG_NOTIFIERS=y CONFIG_BUG_ON_DATA_CORRUPTION=y CONFIG_DEBUG_MAPLE_TREE=y # end of Debug kernel data structures CONFIG_DEBUG_CREDENTIALS=y # # RCU Debugging # CONFIG_TORTURE_TEST=y # CONFIG_RCU_SCALE_TEST is not set CONFIG_RCU_TORTURE_TEST=y CONFIG_RCU_REF_SCALE_TEST=y CONFIG_RCU_CPU_STALL_TIMEOUT=21 CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 # CONFIG_RCU_TRACE is not set # CONFIG_RCU_EQS_DEBUG is not set # end of RCU Debugging CONFIG_DEBUG_WQ_FORCE_RR_CPU=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y # CONFIG_SAMPLES is not set # # arm Debugging # CONFIG_UNWINDER_ARM=y CONFIG_ARM_UNWIND=y # CONFIG_BACKTRACE_VERBOSE is not set # CONFIG_DEBUG_USER is not set # CONFIG_DEBUG_LL is not set CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" CONFIG_CORESIGHT=m CONFIG_CORESIGHT_LINKS_AND_SINKS=m CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m CONFIG_CORESIGHT_CATU=m # CONFIG_CORESIGHT_SINK_TPIU is not set CONFIG_CORESIGHT_SINK_ETBV10=m CONFIG_CORESIGHT_SOURCE_ETM3X=m CONFIG_CORESIGHT_STM=m # CONFIG_CORESIGHT_CPU_DEBUG is not set # CONFIG_CORESIGHT_CTI is not set # end of arm Debugging # # Kernel Testing and Coverage # CONFIG_KUNIT=m # CONFIG_KUNIT_DEBUGFS is not set # CONFIG_KUNIT_TEST is not set CONFIG_KUNIT_EXAMPLE_TEST=m # CONFIG_KUNIT_ALL_TESTS is not set # CONFIG_KUNIT_DEFAULT_ENABLED is not set CONFIG_NOTIFIER_ERROR_INJECTION=y CONFIG_PM_NOTIFIER_ERROR_INJECT=y CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=m # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set CONFIG_CPUMASK_KUNIT_TEST=m CONFIG_TEST_LIST_SORT=m CONFIG_TEST_MIN_HEAP=y CONFIG_TEST_SORT=m CONFIG_TEST_DIV64=y # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_TEST_REF_TRACKER is not set CONFIG_RBTREE_TEST=y CONFIG_REED_SOLOMON_TEST=y # CONFIG_INTERVAL_TREE_TEST is not set # CONFIG_PERCPU_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set CONFIG_TEST_HEXDUMP=m # CONFIG_STRING_SELFTEST is not set CONFIG_TEST_STRING_HELPERS=m # CONFIG_TEST_STRSCPY is not set # CONFIG_TEST_KSTRTOX is not set CONFIG_TEST_PRINTF=m CONFIG_TEST_SCANF=m CONFIG_TEST_BITMAP=y # CONFIG_TEST_UUID is not set CONFIG_TEST_XARRAY=m # CONFIG_TEST_RHASHTABLE is not set # CONFIG_TEST_SIPHASH is not set CONFIG_TEST_IDA=m CONFIG_TEST_LKM=m CONFIG_TEST_BITOPS=m CONFIG_TEST_USER_COPY=m CONFIG_TEST_BPF=m CONFIG_TEST_BLACKHOLE_DEV=m CONFIG_FIND_BIT_BENCHMARK=y # CONFIG_TEST_FIRMWARE is not set # CONFIG_BITFIELD_KUNIT is not set CONFIG_HASH_KUNIT_TEST=m # CONFIG_RESOURCE_KUNIT_TEST is not set CONFIG_SYSCTL_KUNIT_TEST=m # CONFIG_LIST_KUNIT_TEST is not set # CONFIG_LINEAR_RANGES_TEST is not set CONFIG_CMDLINE_KUNIT_TEST=m CONFIG_BITS_TEST=m CONFIG_RATIONAL_KUNIT_TEST=m # CONFIG_MEMCPY_KUNIT_TEST is not set CONFIG_IS_SIGNED_TYPE_KUNIT_TEST=m # CONFIG_OVERFLOW_KUNIT_TEST is not set # CONFIG_STACKINIT_KUNIT_TEST is not set # CONFIG_FORTIFY_KUNIT_TEST is not set # CONFIG_TEST_UDELAY is not set # CONFIG_TEST_STATIC_KEYS is not set CONFIG_TEST_MEMCAT_P=y # CONFIG_TEST_MEMINIT is not set CONFIG_TEST_FREE_PAGES=m CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage # # Rust hacking # # end of Rust hacking # CONFIG_WARN_MISSING_DOCUMENTS is not set # CONFIG_WARN_ABI_ERRORS is not set # end of Kernel hacking ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 03/12] mfd: cs48l32: Add support for CS48L31/32/33 codecs @ 2022-11-11 23:07 ` kernel test robot 0 siblings, 0 replies; 98+ messages in thread From: kernel test robot @ 2022-11-11 23:07 UTC (permalink / raw) To: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, llvm, linux-kernel, linux-gpio, Richard Fitzgerald, oe-kbuild-all [-- Attachment #1: Type: text/plain, Size: 2953 bytes --] Hi Richard, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on broonie-sound/for-next] [also build test WARNING on lee-mfd/for-mfd-next linusw-pinctrl/devel linusw-pinctrl/for-next broonie-regulator/for-next linus/master v6.1-rc4 next-20221111] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Richard-Fitzgerald/Add-support-for-the-Cirrus-Logic-CS48L32-audio-codecs/20221110-005630 base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next patch link: https://lore.kernel.org/r/20221109165331.29332-4-rf%40opensource.cirrus.com patch subject: [PATCH 03/12] mfd: cs48l32: Add support for CS48L31/32/33 codecs config: arm-randconfig-c002-20221111 compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 463da45892e2d2a262277b91b96f5f8c05dc25d0) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install arm cross compiling tool for clang build # apt-get install binutils-arm-linux-gnueabi # https://github.com/intel-lab-lkp/linux/commit/e5417b42692fa57b7987ecb90833e01e67186d0e git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Richard-Fitzgerald/Add-support-for-the-Cirrus-Logic-CS48L32-audio-codecs/20221110-005630 git checkout e5417b42692fa57b7987ecb90833e01e67186d0e # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash drivers/mfd/ If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot <lkp@intel.com> All warnings (new ones prefixed by >>): >> drivers/mfd/cs48l32.c:184:21: warning: attribute declaration must precede definition [-Wignored-attributes] static const struct __maybe_unused of_device_id cs48l32_of_match[] = { ^ include/linux/compiler_attributes.h:326:56: note: expanded from macro '__maybe_unused' #define __maybe_unused __attribute__((__unused__)) ^ include/linux/mod_devicetable.h:268:8: note: previous definition is here struct of_device_id { ^ 1 warning generated. vim +184 drivers/mfd/cs48l32.c 183 > 184 static const struct __maybe_unused of_device_id cs48l32_of_match[] = { 185 { .compatible = "cirrus,cs48l31", }, 186 { .compatible = "cirrus,cs48l32", }, 187 { .compatible = "cirrus,cs48l33", }, 188 {}, 189 }; 190 -- 0-DAY CI Kernel Test Service https://01.org/lkp [-- Attachment #2: config --] [-- Type: text/plain, Size: 144279 bytes --] # # Automatically generated file; DO NOT EDIT. # Linux/arm 6.1.0-rc1 Kernel Configuration # CONFIG_CC_VERSION_TEXT="clang version 16.0.0 (git://gitmirror/llvm_project 463da45892e2d2a262277b91b96f5f8c05dc25d0)" CONFIG_GCC_VERSION=0 CONFIG_CC_IS_CLANG=y CONFIG_CLANG_VERSION=160000 CONFIG_AS_IS_LLVM=y CONFIG_AS_VERSION=160000 CONFIG_LD_VERSION=0 CONFIG_LD_IS_LLD=y CONFIG_LLD_VERSION=160000 CONFIG_RUST_IS_AVAILABLE=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_TOOLS_SUPPORT_RELR=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=123 CONFIG_IRQ_WORK=y CONFIG_THREAD_INFO_IN_TASK=y # # General setup # CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_COMPILE_TEST=y # CONFIG_WERROR is not set CONFIG_LOCALVERSION="" CONFIG_BUILD_SALT="" CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_XZ=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_HAVE_KERNEL_LZ4=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_LZMA is not set # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set CONFIG_WATCH_QUEUE=y CONFIG_USELIB=y # CONFIG_AUDIT is not set CONFIG_HAVE_ARCH_AUDITSYSCALL=y # # IRQ subsystem # CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y CONFIG_GENERIC_IRQ_INJECTION=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_CHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_SIM=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y CONFIG_GENERIC_IRQ_DEBUGFS=y # end of IRQ subsystem CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_TIME_KUNIT_TEST=m CONFIG_CONTEXT_TRACKING=y CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem # CONFIG_TICK_ONESHOT=y CONFIG_HZ_PERIODIC=y # CONFIG_NO_HZ_IDLE is not set # CONFIG_NO_HZ is not set CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem CONFIG_BPF=y CONFIG_HAVE_EBPF_JIT=y # # BPF subsystem # CONFIG_BPF_SYSCALL=y # CONFIG_BPF_JIT is not set # CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set # end of BPF subsystem CONFIG_PREEMPT_BUILD=y # CONFIG_PREEMPT_NONE is not set # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y CONFIG_PREEMPT_COUNT=y CONFIG_PREEMPTION=y # # CPU/Task time and stats accounting # CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_PSI=y CONFIG_PSI_DEFAULT_DISABLED=y # end of CPU/Task time and stats accounting CONFIG_CPU_ISOLATION=y # # RCU Subsystem # CONFIG_TREE_RCU=y CONFIG_PREEMPT_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU_GENERIC=y CONFIG_TASKS_RCU=y CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y # end of RCU Subsystem CONFIG_IKCONFIG=y CONFIG_IKHEADERS=m CONFIG_GENERIC_SCHED_CLOCK=y # # Scheduler features # # end of Scheduler features CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough" CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_CGROUPS=y # CONFIG_CGROUP_FAVOR_DYNMODS is not set # CONFIG_MEMCG is not set CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y # CONFIG_CFS_BANDWIDTH is not set # CONFIG_RT_GROUP_SCHED is not set CONFIG_CGROUP_PIDS=y # CONFIG_CGROUP_RDMA is not set # CONFIG_CGROUP_FREEZER is not set CONFIG_CGROUP_DEVICE=y # CONFIG_CGROUP_CPUACCT is not set # CONFIG_CGROUP_PERF is not set CONFIG_CGROUP_BPF=y CONFIG_CGROUP_MISC=y CONFIG_CGROUP_DEBUG=y CONFIG_SOCK_CGROUP_DATA=y CONFIG_SCHED_AUTOGROUP=y # CONFIG_SYSFS_DEPRECATED is not set CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" # CONFIG_RD_GZIP is not set CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y CONFIG_RD_XZ=y CONFIG_RD_LZO=y # CONFIG_RD_LZ4 is not set # CONFIG_RD_ZSTD is not set # CONFIG_BOOT_CONFIG is not set CONFIG_INITRAMFS_PRESERVE_MTIME=y # CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_LD_ORPHAN_WARN=y CONFIG_HAVE_UID16=y CONFIG_EXPERT=y # CONFIG_MULTIUSER is not set CONFIG_SGETMASK_SYSCALL=y CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y # CONFIG_PRINTK is not set CONFIG_BUG=y # CONFIG_ELF_CORE is not set # CONFIG_BASE_FULL is not set CONFIG_FUTEX=y CONFIG_FUTEX_PI=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y # CONFIG_TIMERFD is not set CONFIG_EVENTFD=y # CONFIG_AIO is not set CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y # CONFIG_MEMBARRIER is not set CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y # CONFIG_KCMP is not set # CONFIG_RSEQ is not set CONFIG_EMBEDDED=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_PERF_USE_VMALLOC=y # CONFIG_PC104 is not set # # Kernel Performance Events And Counters # CONFIG_PERF_EVENTS=y # CONFIG_DEBUG_PERF_USE_VMALLOC is not set # end of Kernel Performance Events And Counters CONFIG_SYSTEM_DATA_VERIFICATION=y CONFIG_PROFILING=y # end of General setup CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_NO_IOPORT_MAP=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_PHYS_OFFSET=0x00800000 CONFIG_GENERIC_BUG=y CONFIG_PGTABLE_LEVELS=2 # # System Type # # CONFIG_MMU is not set CONFIG_ARM_SINGLE_ARMV7M=y CONFIG_ARCH_MMAP_RND_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=16 CONFIG_ARCH_AT91=y CONFIG_SOC_SAMV7=y # # Clocksource driver selection # # CONFIG_ATMEL_CLOCKSOURCE_TCB is not set CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y CONFIG_COMMON_CLK_AT91=y CONFIG_ARCH_MXC=y # # Cortex-A/Cortex-M asymmetric multiprocessing platforms # CONFIG_SOC_IMX7D_CM4=y CONFIG_SOC_IMX7D=y CONFIG_SOC_IMX7ULP=y CONFIG_SOC_IMXRT=y # CONFIG_SOC_VF610 is not set # CONFIG_ARCH_STM32 is not set # CONFIG_ARCH_LPC18XX is not set # CONFIG_ARCH_MPS2 is not set # # Processor Type # CONFIG_CPU_V7M=y CONFIG_CPU_THUMBONLY=y CONFIG_CPU_THUMB_CAPABLE=y CONFIG_CPU_32v7M=y CONFIG_CPU_ABRT_NOMMU=y CONFIG_CPU_PABRT_LEGACY=y CONFIG_CPU_CACHE_NOP=y CONFIG_CPU_CACHE_V7M=y CONFIG_CPU_V7M_NUM_IRQ=240 # # Processor Features # CONFIG_ARM_THUMB=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_ICACHE_DISABLE=y CONFIG_CPU_DCACHE_DISABLE=y CONFIG_CPU_BPREDICT_DISABLE=y CONFIG_ARM_L1_CACHE_SHIFT=5 # CONFIG_ARM_DMA_MEM_BUFFERABLE is not set # CONFIG_SET_MEM_PARAM is not set CONFIG_DRAM_BASE=0x00800000 CONFIG_DRAM_SIZE=0x00800000 # CONFIG_REMAP_VECTORS_TO_RAM is not set # CONFIG_ARM_MPU is not set # end of System Type # # Bus support # # end of Bus support # # Kernel Features # CONFIG_IRQSTACKS=y CONFIG_PAGE_OFFSET=0x00800000 CONFIG_ARCH_NR_GPIO=0 CONFIG_HZ_FIXED=0 # CONFIG_HZ_100 is not set # CONFIG_HZ_200 is not set # CONFIG_HZ_250 is not set # CONFIG_HZ_300 is not set CONFIG_HZ_500=y # CONFIG_HZ_1000 is not set CONFIG_HZ=500 CONFIG_SCHED_HRTICK=y CONFIG_THUMB2_KERNEL=y CONFIG_AEABI=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y # CONFIG_ARM_MODULE_PLTS is not set CONFIG_ARCH_FORCE_MAX_ORDER=11 CONFIG_PARAVIRT=y CONFIG_PARAVIRT_TIME_ACCOUNTING=y CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y # end of Kernel Features # # Boot options # CONFIG_USE_OF=y CONFIG_ATAGS=y # CONFIG_UNUSED_BOARD_FILES is not set CONFIG_DEPRECATED_PARAM_STRUCT=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y # CONFIG_ARM_ATAG_DTB_COMPAT is not set CONFIG_CMDLINE="" # CONFIG_XIP_KERNEL is not set # CONFIG_CRASH_DUMP is not set # CONFIG_AUTO_ZRELADDR is not set # end of Boot options # # CPU Power Management # # # CPU Frequency scaling # # CONFIG_CPU_FREQ is not set # end of CPU Frequency scaling # # CPU Idle # CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y # CONFIG_CPU_IDLE_GOV_TEO is not set CONFIG_DT_IDLE_STATES=y # # ARM CPU Idle Drivers # CONFIG_ARM_CPUIDLE=y # CONFIG_ARM_CLPS711X_CPUIDLE is not set # CONFIG_ARM_KIRKWOOD_CPUIDLE is not set # CONFIG_ARM_ZYNQ_CPUIDLE is not set # CONFIG_ARM_AT91_CPUIDLE is not set # CONFIG_ARM_EXYNOS_CPUIDLE is not set # CONFIG_ARM_MVEBU_V7_CPUIDLE is not set # end of ARM CPU Idle Drivers # end of CPU Idle # end of CPU Power Management # # Floating point emulation # # # At least one emulation must be selected # # end of Floating point emulation # # Power management options # CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y CONFIG_SUSPEND_SKIP_SYNC=y CONFIG_PM_SLEEP=y # CONFIG_PM_AUTOSLEEP is not set CONFIG_PM_USERSPACE_AUTOSLEEP=y # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y CONFIG_PM_DEBUG=y CONFIG_PM_ADVANCED_DEBUG=y # CONFIG_PM_TEST_SUSPEND is not set CONFIG_PM_SLEEP_DEBUG=y CONFIG_APM_EMULATION=y CONFIG_PM_CLK=y CONFIG_PM_GENERIC_DOMAINS=y CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y CONFIG_PM_GENERIC_DOMAINS_SLEEP=y CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_CPU_PM=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARM_CPU_SUSPEND=y # end of Power management options CONFIG_AS_VFP_VMRS_FPINST=y # # General architecture-dependent options # CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_HAVE_NMI=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_ARCH_HAS_FORTIFY_SOURCE=y CONFIG_ARCH_HAS_KEEPINITRD=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y CONFIG_ARCH_32BIT_OFF_T=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y # CONFIG_SECCOMP is not set CONFIG_HAVE_STACKPROTECTOR=y # CONFIG_STACKPROTECTOR is not set CONFIG_LTO_NONE=y CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_LOCK_EVENT_COUNTS=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_HAVE_ARCH_PFN_VALID=y # # GCOV-based kernel profiling # # CONFIG_GCOV_KERNEL is not set CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling CONFIG_HAVE_GCC_PLUGINS=y # end of General architecture-dependent options CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=1 CONFIG_MODULE_SIG_FORMAT=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y # CONFIG_MODULE_UNLOAD is not set CONFIG_MODVERSIONS=y # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_MODULE_SIG=y CONFIG_MODULE_SIG_FORCE=y # CONFIG_MODULE_SIG_ALL is not set # # Do not forget to sign required modules with scripts/sign-file # # CONFIG_MODULE_SIG_SHA1 is not set # CONFIG_MODULE_SIG_SHA224 is not set # CONFIG_MODULE_SIG_SHA256 is not set # CONFIG_MODULE_SIG_SHA384 is not set CONFIG_MODULE_SIG_SHA512=y CONFIG_MODULE_SIG_HASH="sha512" CONFIG_MODULE_COMPRESS_NONE=y # CONFIG_MODULE_COMPRESS_GZIP is not set # CONFIG_MODULE_COMPRESS_XZ is not set # CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y # CONFIG_BLOCK is not set CONFIG_ASN1=y CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y CONFIG_FREEZER=y # # Executable file formats # # CONFIG_BINFMT_ELF_FDPIC is not set # CONFIG_BINFMT_SCRIPT is not set CONFIG_ARCH_HAS_BINFMT_FLAT=y CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y # CONFIG_BINFMT_FLAT_OLD is not set CONFIG_BINFMT_ZFLAT=y CONFIG_BINFMT_MISC=m CONFIG_COREDUMP=y # end of Executable file formats # # Memory Management options # # # SLAB allocator options # # CONFIG_SLAB is not set # CONFIG_SLUB is not set CONFIG_SLOB=y # end of SLAB allocator options # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set CONFIG_COMPAT_BRK=y # CONFIG_MMAP_ALLOW_UNINITIALIZED is not set CONFIG_SELECT_MEMORY_MODEL=y # CONFIG_FLATMEM_MANUAL is not set CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_STATIC=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_SPLIT_PTLOCK_CPUS=999999 # CONFIG_PAGE_REPORTING is not set CONFIG_NOMMU_INITIAL_TRIM_EXCESS=1 CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_NEED_PER_CPU_KM=y CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y # CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_PERCPU_STATS is not set CONFIG_GUP_TEST=y # # Data Access Monitoring # CONFIG_DAMON=y # CONFIG_DAMON_SYSFS is not set # end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y CONFIG_NET_INGRESS=y CONFIG_NET_EGRESS=y CONFIG_SKB_EXTENSIONS=y # # Networking options # # CONFIG_PACKET is not set CONFIG_UNIX=y CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y CONFIG_UNIX_DIAG=m # CONFIG_TLS is not set CONFIG_XFRM=y CONFIG_XFRM_OFFLOAD=y CONFIG_XFRM_ALGO=y CONFIG_XFRM_USER=m # CONFIG_XFRM_INTERFACE is not set CONFIG_XFRM_SUB_POLICY=y # CONFIG_XFRM_MIGRATE is not set CONFIG_XFRM_AH=y CONFIG_XFRM_ESP=m CONFIG_XFRM_IPCOMP=m # CONFIG_NET_KEY is not set CONFIG_XFRM_ESPINTCP=y # CONFIG_XDP_SOCKETS is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y # CONFIG_IP_PNP_BOOTP is not set # CONFIG_IP_PNP_RARP is not set CONFIG_NET_IPIP=y # CONFIG_NET_IPGRE_DEMUX is not set CONFIG_NET_IP_TUNNEL=y CONFIG_IP_MROUTE_COMMON=y CONFIG_IP_MROUTE=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_SYN_COOKIES=y # CONFIG_NET_IPVTI is not set CONFIG_NET_UDP_TUNNEL=y CONFIG_NET_FOU=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_INET_AH=y CONFIG_INET_ESP=m CONFIG_INET_ESP_OFFLOAD=m CONFIG_INET_ESPINTCP=y # CONFIG_INET_IPCOMP is not set CONFIG_INET_TUNNEL=y CONFIG_INET_DIAG=m CONFIG_INET_TCP_DIAG=m CONFIG_INET_UDP_DIAG=m CONFIG_INET_RAW_DIAG=m CONFIG_INET_DIAG_DESTROY=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set CONFIG_IPV6=y CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTE_INFO=y CONFIG_IPV6_OPTIMISTIC_DAD=y # CONFIG_INET6_AH is not set # CONFIG_INET6_ESP is not set CONFIG_INET6_IPCOMP=m CONFIG_IPV6_MIP6=m CONFIG_IPV6_ILA=m CONFIG_INET6_XFRM_TUNNEL=m CONFIG_INET6_TUNNEL=y CONFIG_IPV6_VTI=y # CONFIG_IPV6_SIT is not set CONFIG_IPV6_TUNNEL=y CONFIG_IPV6_FOU=y CONFIG_IPV6_FOU_TUNNEL=y CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y # CONFIG_IPV6_MROUTE is not set # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set # CONFIG_IPV6_RPL_LWTUNNEL is not set # CONFIG_IPV6_IOAM6_LWTUNNEL is not set CONFIG_MPTCP=y CONFIG_INET_MPTCP_DIAG=m # CONFIG_MPTCP_IPV6 is not set CONFIG_MPTCP_KUNIT_TEST=m CONFIG_NETWORK_SECMARK=y CONFIG_NET_PTP_CLASSIFY=y CONFIG_NETWORK_PHY_TIMESTAMPING=y CONFIG_NETFILTER=y # CONFIG_NETFILTER_ADVANCED is not set # # Core Netfilter Configuration # CONFIG_NETFILTER_INGRESS=y CONFIG_NETFILTER_EGRESS=y CONFIG_NETFILTER_NETLINK=y CONFIG_NETFILTER_NETLINK_LOG=y # CONFIG_NF_CONNTRACK is not set CONFIG_NF_LOG_SYSLOG=y # CONFIG_NF_TABLES is not set CONFIG_NETFILTER_XTABLES=y # # Xtables combined modules # CONFIG_NETFILTER_XT_MARK=y # # Xtables targets # CONFIG_NETFILTER_XT_TARGET_LOG=y CONFIG_NETFILTER_XT_TARGET_NFLOG=m # CONFIG_NETFILTER_XT_TARGET_SECMARK is not set # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set # # Xtables matches # CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y CONFIG_NETFILTER_XT_MATCH_POLICY=m # end of Core Netfilter Configuration # CONFIG_IP_SET is not set # CONFIG_IP_VS is not set # # IP: Netfilter Configuration # CONFIG_NF_SOCKET_IPV4=m CONFIG_NF_TPROXY_IPV4=m CONFIG_NF_DUP_IPV4=m CONFIG_NF_LOG_ARP=m CONFIG_NF_LOG_IPV4=m CONFIG_NF_REJECT_IPV4=m CONFIG_IP_NF_IPTABLES=y CONFIG_IP_NF_FILTER=y # CONFIG_IP_NF_TARGET_REJECT is not set # CONFIG_IP_NF_MANGLE is not set CONFIG_IP_NF_RAW=y # end of IP: Netfilter Configuration # # IPv6: Netfilter Configuration # CONFIG_NF_SOCKET_IPV6=m # CONFIG_NF_TPROXY_IPV6 is not set CONFIG_NF_DUP_IPV6=y CONFIG_NF_REJECT_IPV6=y CONFIG_NF_LOG_IPV6=y CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m # CONFIG_IP6_NF_FILTER is not set CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m # end of IPv6: Netfilter Configuration # CONFIG_BPFILTER is not set # CONFIG_IP_DCCP is not set CONFIG_IP_SCTP=y CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set CONFIG_SCTP_COOKIE_HMAC_MD5=y # CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set CONFIG_INET_SCTP_DIAG=m CONFIG_RDS=m # CONFIG_RDS_TCP is not set # CONFIG_RDS_DEBUG is not set CONFIG_TIPC=y # CONFIG_TIPC_MEDIA_UDP is not set # CONFIG_TIPC_CRYPTO is not set CONFIG_TIPC_DIAG=m # CONFIG_ATM is not set CONFIG_L2TP=y # CONFIG_L2TP_DEBUGFS is not set # CONFIG_L2TP_V3 is not set # CONFIG_BRIDGE is not set # CONFIG_VLAN_8021Q is not set CONFIG_LLC=y # CONFIG_LLC2 is not set CONFIG_ATALK=y # CONFIG_DEV_APPLETALK is not set CONFIG_X25=m CONFIG_LAPB=m CONFIG_PHONET=m # CONFIG_6LOWPAN is not set CONFIG_IEEE802154=y # CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set # CONFIG_IEEE802154_SOCKET is not set CONFIG_MAC802154=m # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set CONFIG_DNS_RESOLVER=y # CONFIG_BATMAN_ADV is not set CONFIG_OPENVSWITCH=m # CONFIG_VSOCKETS is not set # CONFIG_NETLINK_DIAG is not set CONFIG_MPLS=y CONFIG_NET_MPLS_GSO=m CONFIG_NET_NSH=m CONFIG_HSR=m CONFIG_NET_SWITCHDEV=y CONFIG_NET_L3_MASTER_DEV=y CONFIG_QRTR=y # CONFIG_QRTR_SMD is not set # CONFIG_QRTR_TUN is not set # CONFIG_QRTR_MHI is not set CONFIG_NET_NCSI=y # CONFIG_NCSI_OEM_CMD_GET_MAC is not set CONFIG_NCSI_OEM_CMD_KEEP_PHY=y # CONFIG_CGROUP_NET_PRIO is not set # CONFIG_CGROUP_NET_CLASSID is not set CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y # CONFIG_BPF_STREAM_PARSER is not set # # Network testing # # end of Network testing # end of Networking options # CONFIG_HAMRADIO is not set CONFIG_CAN=m CONFIG_CAN_RAW=m CONFIG_CAN_BCM=m CONFIG_CAN_GW=m CONFIG_CAN_J1939=m CONFIG_CAN_ISOTP=m CONFIG_BT=m CONFIG_BT_BREDR=y # CONFIG_BT_RFCOMM is not set CONFIG_BT_BNEP=y # CONFIG_BT_BNEP_MC_FILTER is not set # CONFIG_BT_BNEP_PROTO_FILTER is not set # CONFIG_BT_HS is not set CONFIG_BT_LE=y # CONFIG_BT_LEDS is not set CONFIG_BT_MSFTEXT=y CONFIG_BT_AOSPEXT=y CONFIG_BT_DEBUGFS=y CONFIG_BT_SELFTEST=y # CONFIG_BT_SELFTEST_ECDH is not set # CONFIG_BT_SELFTEST_SMP is not set CONFIG_BT_FEATURE_DEBUG=y # # Bluetooth device drivers # CONFIG_BT_INTEL=m CONFIG_BT_HCIBTUSB=m CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y # CONFIG_BT_HCIBTUSB_BCM is not set # CONFIG_BT_HCIBTUSB_MTK is not set # CONFIG_BT_HCIBTUSB_RTL is not set CONFIG_BT_HCIBTSDIO=m # CONFIG_BT_HCIUART is not set # CONFIG_BT_HCIBCM203X is not set CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m # CONFIG_BT_HCIDTL1 is not set CONFIG_BT_HCIBT3C=m # CONFIG_BT_HCIBLUECARD is not set # CONFIG_BT_HCIVHCI is not set CONFIG_BT_MRVL=m # CONFIG_BT_MRVL_SDIO is not set CONFIG_BT_ATH3K=m # CONFIG_BT_MTKSDIO is not set # CONFIG_BT_MTKUART is not set # CONFIG_BT_QCOMSMD is not set # CONFIG_BT_VIRTIO is not set # end of Bluetooth device drivers # CONFIG_AF_RXRPC is not set CONFIG_AF_KCM=m CONFIG_STREAM_PARSER=y CONFIG_MCTP=y CONFIG_FIB_RULES=y # CONFIG_WIRELESS is not set # CONFIG_RFKILL is not set CONFIG_NET_9P=y CONFIG_NET_9P_FD=y CONFIG_NET_9P_VIRTIO=m CONFIG_NET_9P_DEBUG=y CONFIG_CAIF=m # CONFIG_CAIF_DEBUG is not set CONFIG_CAIF_NETDEV=m CONFIG_CAIF_USB=m CONFIG_CEPH_LIB=y # CONFIG_CEPH_LIB_PRETTYDEBUG is not set CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y CONFIG_NFC=y CONFIG_NFC_DIGITAL=y # CONFIG_NFC_NCI is not set CONFIG_NFC_HCI=m # CONFIG_NFC_SHDLC is not set # # Near Field Communication (NFC) devices # CONFIG_NFC_TRF7970A=m CONFIG_NFC_SIM=y # CONFIG_NFC_PORT100 is not set CONFIG_NFC_PN533=m CONFIG_NFC_PN533_USB=m CONFIG_NFC_PN533_I2C=m CONFIG_NFC_PN532_UART=m CONFIG_NFC_ST95HF=y # end of Near Field Communication (NFC) devices # CONFIG_PSAMPLE is not set # CONFIG_NET_IFE is not set CONFIG_LWTUNNEL=y CONFIG_LWTUNNEL_BPF=y CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y CONFIG_NET_SOCK_MSG=y CONFIG_PAGE_POOL=y CONFIG_PAGE_POOL_STATS=y # CONFIG_FAILOVER is not set # CONFIG_ETHTOOL_NETLINK is not set CONFIG_NETDEV_ADDR_LIST_TEST=m # # Device Drivers # CONFIG_ARM_AMBA=y CONFIG_PCCARD=m CONFIG_PCMCIA=m CONFIG_PCMCIA_LOAD_CIS=y # # PC-card bridges # # CONFIG_OMAP_CF is not set # # Generic Driver Options # CONFIG_AUXILIARY_BUS=y # CONFIG_UEVENT_HELPER is not set # CONFIG_DEVTMPFS is not set # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set # # Firmware loader # CONFIG_FW_LOADER=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_FW_LOADER_SYSFS=y CONFIG_EXTRA_FIRMWARE="" CONFIG_FW_LOADER_USER_HELPER=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y # CONFIG_FW_LOADER_COMPRESS is not set CONFIG_FW_CACHE=y CONFIG_FW_UPLOAD=y # end of Firmware loader CONFIG_ALLOW_DEV_COREDUMP=y CONFIG_DEBUG_DRIVER=y # CONFIG_DEBUG_DEVRES is not set # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set CONFIG_TEST_ASYNC_DRIVER_PROBE=m CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_SOC_BUS=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=m CONFIG_REGMAP_SPI=y CONFIG_REGMAP_SPMI=m CONFIG_REGMAP_W1=m CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_IRQ=y # end of Generic Driver Options # # Bus devices # # CONFIG_ARM_INTEGRATOR_LM is not set # CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_BT1_APB is not set # CONFIG_BT1_AXI is not set CONFIG_MOXTET=m # CONFIG_HISILICON_LPC is not set CONFIG_IMX_WEIM=y # CONFIG_INTEL_IXP4XX_EB is not set # CONFIG_QCOM_EBI2 is not set CONFIG_VEXPRESS_CONFIG=y # CONFIG_FSL_MC_BUS is not set CONFIG_MHI_BUS=m # CONFIG_MHI_BUS_DEBUG is not set CONFIG_MHI_BUS_EP=y # end of Bus devices # CONFIG_CONNECTOR is not set # # Firmware Drivers # # # ARM System Control and Management Interface Protocol # # CONFIG_ARM_SCMI_PROTOCOL is not set CONFIG_ARM_SCMI_POWER_DOMAIN=y # CONFIG_ARM_SCMI_POWER_CONTROL is not set # end of ARM System Control and Management Interface Protocol # CONFIG_ARM_SCPI_PROTOCOL is not set CONFIG_ARM_SCPI_POWER_DOMAIN=y # CONFIG_FIRMWARE_MEMMAP is not set # CONFIG_TURRIS_MOX_RWTM is not set # CONFIG_BCM47XX_NVRAM is not set CONFIG_GOOGLE_FIRMWARE=y CONFIG_GOOGLE_COREBOOT_TABLE=m CONFIG_GOOGLE_MEMCONSOLE=m CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=m CONFIG_GOOGLE_VPD=m CONFIG_IMX_DSP=m CONFIG_IMX_SCU=y CONFIG_IMX_SCU_PD=y # # Tegra firmware driver # # end of Tegra firmware driver # end of Firmware Drivers CONFIG_GNSS=m CONFIG_GNSS_SERIAL=m CONFIG_GNSS_MTK_SERIAL=m # CONFIG_GNSS_SIRF_SERIAL is not set # CONFIG_GNSS_UBX_SERIAL is not set CONFIG_GNSS_USB=m # CONFIG_MTD is not set CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set # CONFIG_OF_ALL_DTBS is not set CONFIG_OF_FLATTREE=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_KOBJ=y CONFIG_OF_ADDRESS=y CONFIG_OF_IRQ=y CONFIG_OF_RESERVED_MEM=y # CONFIG_OF_OVERLAY is not set CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_PARPORT=y CONFIG_PARPORT_PC=m # CONFIG_PARPORT_PC_FIFO is not set # CONFIG_PARPORT_PC_SUPERIO is not set CONFIG_PARPORT_PC_PCMCIA=m # CONFIG_PARPORT_AX88796 is not set # CONFIG_PARPORT_1284 is not set # # NVME Support # # end of NVME Support # # Misc devices # CONFIG_AD525X_DPOT=m CONFIG_AD525X_DPOT_I2C=m CONFIG_AD525X_DPOT_SPI=m CONFIG_DUMMY_IRQ=y # CONFIG_ICS932S401 is not set # CONFIG_ATMEL_SSC is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_GEHC_ACHC is not set CONFIG_HI6421V600_IRQ=m # CONFIG_QCOM_COINCELL is not set # CONFIG_QCOM_FASTRPC is not set # CONFIG_APDS9802ALS is not set # CONFIG_ISL29003 is not set CONFIG_ISL29020=m CONFIG_SENSORS_TSL2550=m # CONFIG_SENSORS_BH1770 is not set CONFIG_SENSORS_APDS990X=m CONFIG_HMC6352=m # CONFIG_DS1682 is not set CONFIG_LATTICE_ECP3_CONFIG=m CONFIG_SRAM=y CONFIG_SRAM_EXEC=y CONFIG_XILINX_SDFEC=y # CONFIG_HISI_HIKEY_USB is not set # CONFIG_OPEN_DICE is not set CONFIG_VCPU_STALL_DETECTOR=m # CONFIG_C2PORT is not set # # EEPROM support # CONFIG_EEPROM_AT24=m CONFIG_EEPROM_AT25=y CONFIG_EEPROM_LEGACY=m CONFIG_EEPROM_MAX6875=m CONFIG_EEPROM_93CX6=m # CONFIG_EEPROM_93XX46 is not set CONFIG_EEPROM_IDT_89HPESX=m CONFIG_EEPROM_EE1004=m # end of EEPROM support # # Texas Instruments shared transport line discipline # CONFIG_TI_ST=m # end of Texas Instruments shared transport line discipline # # Altera FPGA firmware download module (requires I2C) # CONFIG_ALTERA_STAPL=m # CONFIG_ECHO is not set # CONFIG_MISC_RTSX_USB is not set CONFIG_UACCE=y # CONFIG_PVPANIC is not set # end of Misc devices # # SCSI device support # # end of SCSI device support # # IEEE 1394 (FireWire) support # # CONFIG_FIREWIRE is not set # end of IEEE 1394 (FireWire) support # CONFIG_NETDEVICES is not set # # Input device support # # CONFIG_INPUT is not set # # Hardware I/O ports # CONFIG_SERIO=y CONFIG_SERIO_SERPORT=y CONFIG_SERIO_PARKBD=m CONFIG_SERIO_AMBAKMI=m CONFIG_SERIO_LIBPS2=m CONFIG_SERIO_RAW=m CONFIG_SERIO_ALTERA_PS2=y # CONFIG_SERIO_PS2MULT is not set CONFIG_SERIO_ARC_PS2=y CONFIG_SERIO_APBPS2=y # CONFIG_SERIO_OLPC_APSP is not set # CONFIG_SERIO_SUN4I_PS2 is not set # CONFIG_SERIO_GPIO_PS2 is not set # CONFIG_USERIO is not set # CONFIG_GAMEPORT is not set # end of Hardware I/O ports # end of Input device support # # Character devices # CONFIG_TTY=y # CONFIG_VT is not set CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set # CONFIG_LDISC_AUTOLOAD is not set # # Serial drivers # CONFIG_SERIAL_EARLYCON=y # CONFIG_SERIAL_8250 is not set # # Non-8250 serial port support # # CONFIG_SERIAL_AMBA_PL010 is not set CONFIG_SERIAL_AMBA_PL011=m # CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set # CONFIG_SERIAL_ATMEL is not set # CONFIG_SERIAL_MESON is not set # CONFIG_SERIAL_CLPS711X is not set # CONFIG_SERIAL_SAMSUNG is not set # CONFIG_SERIAL_TEGRA is not set # CONFIG_SERIAL_TEGRA_TCU is not set # CONFIG_SERIAL_MAX3100 is not set # CONFIG_SERIAL_MAX310X is not set CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=m CONFIG_SERIAL_IMX_EARLYCON=y CONFIG_SERIAL_UARTLITE=y # CONFIG_SERIAL_UARTLITE_CONSOLE is not set CONFIG_SERIAL_UARTLITE_NR_UARTS=1 # CONFIG_SERIAL_SH_SCI is not set # CONFIG_SERIAL_HS_LPC32XX is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_MSM is not set # CONFIG_SERIAL_VT8500 is not set # CONFIG_SERIAL_OMAP is not set CONFIG_SERIAL_SIFIVE=y # CONFIG_SERIAL_SIFIVE_CONSOLE is not set # CONFIG_SERIAL_LANTIQ is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set # CONFIG_SERIAL_TIMBERDALE is not set # CONFIG_SERIAL_BCM63XX is not set CONFIG_SERIAL_ALTERA_JTAGUART=m CONFIG_SERIAL_ALTERA_UART=y CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4 CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200 CONFIG_SERIAL_ALTERA_UART_CONSOLE=y # CONFIG_SERIAL_MXS_AUART is not set # CONFIG_SERIAL_XILINX_PS_UART is not set # CONFIG_SERIAL_MPS2_UART is not set CONFIG_SERIAL_ARC=m CONFIG_SERIAL_ARC_NR_PORTS=1 CONFIG_SERIAL_FSL_LPUART=m # CONFIG_SERIAL_FSL_LPUART_CONSOLE is not set # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set # CONFIG_SERIAL_ST_ASC is not set CONFIG_SERIAL_MEN_Z135=y CONFIG_SERIAL_SPRD=y CONFIG_SERIAL_SPRD_CONSOLE=y # CONFIG_SERIAL_STM32 is not set # CONFIG_SERIAL_MVEBU_UART is not set # CONFIG_SERIAL_OWL is not set # CONFIG_SERIAL_RDA is not set # CONFIG_SERIAL_MILBEAUT_USIO is not set CONFIG_SERIAL_LITEUART=y CONFIG_SERIAL_LITEUART_MAX_PORTS=1 # CONFIG_SERIAL_LITEUART_CONSOLE is not set # CONFIG_SERIAL_SUNPLUS is not set # end of Serial drivers CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_NONSTANDARD=y # CONFIG_N_HDLC is not set # CONFIG_N_GSM is not set CONFIG_NULL_TTY=y # CONFIG_HVC_DCC is not set CONFIG_RPMSG_TTY=m CONFIG_SERIAL_DEV_BUS=y # CONFIG_SERIAL_DEV_CTRL_TTYPORT is not set CONFIG_TTY_PRINTK=y CONFIG_TTY_PRINTK_LEVEL=6 # CONFIG_PRINTER is not set CONFIG_PPDEV=m # CONFIG_VIRTIO_CONSOLE is not set CONFIG_IPMI_HANDLER=y CONFIG_IPMI_PLAT_DATA=y # CONFIG_IPMI_PANIC_EVENT is not set CONFIG_IPMI_DEVICE_INTERFACE=y CONFIG_IPMI_SI=m # CONFIG_IPMI_SSIF is not set CONFIG_IPMI_IPMB=m CONFIG_IPMI_WATCHDOG=m CONFIG_IPMI_POWEROFF=y # CONFIG_ASPEED_KCS_IPMI_BMC is not set # CONFIG_NPCM7XX_KCS_IPMI_BMC is not set # CONFIG_ASPEED_BT_IPMI_BMC is not set # CONFIG_IPMB_DEVICE_INTERFACE is not set CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_TIMERIOMEM=m CONFIG_HW_RANDOM_ATMEL=y # CONFIG_HW_RANDOM_BA431 is not set CONFIG_HW_RANDOM_BCM2835=y CONFIG_HW_RANDOM_IPROC_RNG200=y CONFIG_HW_RANDOM_IXP4XX=y CONFIG_HW_RANDOM_OMAP=y CONFIG_HW_RANDOM_OMAP3_ROM=y CONFIG_HW_RANDOM_VIRTIO=m CONFIG_HW_RANDOM_IMX_RNGC=y CONFIG_HW_RANDOM_NOMADIK=y CONFIG_HW_RANDOM_STM32=y CONFIG_HW_RANDOM_MESON=y CONFIG_HW_RANDOM_MTK=y CONFIG_HW_RANDOM_EXYNOS=y CONFIG_HW_RANDOM_NPCM=y CONFIG_HW_RANDOM_KEYSTONE=y # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set # # PCMCIA character devices # CONFIG_SYNCLINK_CS=m CONFIG_CARDMAN_4000=m CONFIG_CARDMAN_4040=m # CONFIG_SCR24X is not set # end of PCMCIA character devices CONFIG_DEVMEM=y CONFIG_TCG_TPM=y # CONFIG_HW_RANDOM_TPM is not set CONFIG_TCG_TIS_CORE=m CONFIG_TCG_TIS=m # CONFIG_TCG_TIS_SPI is not set # CONFIG_TCG_TIS_I2C is not set # CONFIG_TCG_TIS_SYNQUACER is not set CONFIG_TCG_TIS_I2C_CR50=m # CONFIG_TCG_TIS_I2C_ATMEL is not set # CONFIG_TCG_TIS_I2C_INFINEON is not set # CONFIG_TCG_TIS_I2C_NUVOTON is not set CONFIG_TCG_VTPM_PROXY=y CONFIG_TCG_TIS_ST33ZP24=m CONFIG_TCG_TIS_ST33ZP24_I2C=m # CONFIG_TCG_TIS_ST33ZP24_SPI is not set CONFIG_XILLYBUS_CLASS=y CONFIG_XILLYBUS=m CONFIG_XILLYBUS_OF=m CONFIG_XILLYUSB=y CONFIG_RANDOM_TRUST_CPU=y CONFIG_RANDOM_TRUST_BOOTLOADER=y # end of Character devices # # I2C support # CONFIG_I2C=m CONFIG_I2C_BOARDINFO=y # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=m # CONFIG_I2C_MUX is not set CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_SMBUS=m CONFIG_I2C_ALGOBIT=m CONFIG_I2C_ALGOPCA=m # # I2C Hardware Bus support # # CONFIG_I2C_HIX5HD2 is not set # # I2C system bus drivers (mostly embedded / system-on-chip) # # CONFIG_I2C_ALTERA is not set # CONFIG_I2C_ASPEED is not set # CONFIG_I2C_AT91 is not set # CONFIG_I2C_AXXIA is not set # CONFIG_I2C_BCM2835 is not set # CONFIG_I2C_BCM_IPROC is not set # CONFIG_I2C_BCM_KONA is not set CONFIG_I2C_BRCMSTB=m # CONFIG_I2C_CADENCE is not set CONFIG_I2C_CBUS_GPIO=m # CONFIG_I2C_DAVINCI is not set # CONFIG_I2C_DESIGNWARE_PLATFORM is not set # CONFIG_I2C_DIGICOLOR is not set # CONFIG_I2C_EMEV2 is not set # CONFIG_I2C_EXYNOS5 is not set # CONFIG_I2C_GPIO is not set # CONFIG_I2C_HIGHLANDER is not set # CONFIG_I2C_HISI is not set # CONFIG_I2C_IMG is not set CONFIG_I2C_IMX=m # CONFIG_I2C_IMX_LPI2C is not set # CONFIG_I2C_IOP3XX is not set # CONFIG_I2C_JZ4780 is not set CONFIG_I2C_KEMPLD=m # CONFIG_I2C_LPC2K is not set # CONFIG_I2C_MESON is not set # CONFIG_I2C_MICROCHIP_CORE is not set # CONFIG_I2C_MT65XX is not set # CONFIG_I2C_MT7621 is not set # CONFIG_I2C_MV64XXX is not set # CONFIG_I2C_MXS is not set CONFIG_I2C_NOMADIK=m # CONFIG_I2C_NPCM is not set CONFIG_I2C_OCORES=m # CONFIG_I2C_OMAP is not set # CONFIG_I2C_OWL is not set # CONFIG_I2C_APPLE is not set CONFIG_I2C_PCA_PLATFORM=m # CONFIG_I2C_PNX is not set # CONFIG_I2C_PXA is not set # CONFIG_I2C_QCOM_CCI is not set # CONFIG_I2C_QUP is not set # CONFIG_I2C_RIIC is not set CONFIG_I2C_RK3X=m # CONFIG_I2C_RZV2M is not set # CONFIG_I2C_S3C2410 is not set # CONFIG_I2C_SH_MOBILE is not set CONFIG_I2C_SIMTEC=m # CONFIG_I2C_ST is not set # CONFIG_I2C_STM32F4 is not set # CONFIG_I2C_STM32F7 is not set # CONFIG_I2C_SUN6I_P2WI is not set # CONFIG_I2C_SYNQUACER is not set # CONFIG_I2C_TEGRA is not set # CONFIG_I2C_TEGRA_BPMP is not set # CONFIG_I2C_UNIPHIER is not set # CONFIG_I2C_UNIPHIER_F is not set # CONFIG_I2C_VERSATILE is not set # CONFIG_I2C_WMT is not set CONFIG_I2C_XILINX=m # CONFIG_I2C_XLP9XX is not set # CONFIG_I2C_RCAR is not set # # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set CONFIG_I2C_DLN2=m CONFIG_I2C_CP2615=m CONFIG_I2C_PARPORT=m CONFIG_I2C_ROBOTFUZZ_OSIF=m CONFIG_I2C_TAOS_EVM=m CONFIG_I2C_TINY_USB=m CONFIG_I2C_VIPERBOARD=m # # Other I2C/SMBus bus drivers # # CONFIG_I2C_MLXCPLD is not set # CONFIG_I2C_FSI is not set CONFIG_I2C_VIRTIO=m # end of I2C Hardware Bus support CONFIG_I2C_STUB=m CONFIG_I2C_SLAVE=y CONFIG_I2C_SLAVE_EEPROM=m CONFIG_I2C_SLAVE_TESTUNIT=m # CONFIG_I2C_DEBUG_CORE is not set CONFIG_I2C_DEBUG_ALGO=y # CONFIG_I2C_DEBUG_BUS is not set # end of I2C support CONFIG_I3C=m CONFIG_CDNS_I3C_MASTER=m CONFIG_DW_I3C_MASTER=m # CONFIG_SVC_I3C_MASTER is not set # CONFIG_MIPI_I3C_HCI is not set CONFIG_SPI=y # CONFIG_SPI_DEBUG is not set CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y # # SPI Master Controller Drivers # CONFIG_SPI_ALTERA=m CONFIG_SPI_ALTERA_CORE=m # CONFIG_SPI_AR934X is not set # CONFIG_SPI_ATH79 is not set # CONFIG_SPI_ARMADA_3700 is not set # CONFIG_SPI_ASPEED_SMC is not set CONFIG_SPI_ATMEL=y # CONFIG_SPI_AT91_USART is not set # CONFIG_SPI_ATMEL_QUADSPI is not set # CONFIG_SPI_AXI_SPI_ENGINE is not set # CONFIG_SPI_BCM2835 is not set # CONFIG_SPI_BCM2835AUX is not set # CONFIG_SPI_BCM63XX is not set # CONFIG_SPI_BCM63XX_HSSPI is not set # CONFIG_SPI_BCM_QSPI is not set CONFIG_SPI_BITBANG=m CONFIG_SPI_BUTTERFLY=m CONFIG_SPI_CADENCE=y CONFIG_SPI_CADENCE_QUADSPI=m # CONFIG_SPI_CADENCE_XSPI is not set # CONFIG_SPI_CLPS711X is not set CONFIG_SPI_DESIGNWARE=m CONFIG_SPI_DW_DMA=y CONFIG_SPI_DW_MMIO=m # CONFIG_SPI_DW_BT1 is not set CONFIG_SPI_DLN2=m # CONFIG_SPI_EP93XX is not set CONFIG_SPI_FSI=m CONFIG_SPI_FSL_LPSPI=m CONFIG_SPI_FSL_QUADSPI=y # CONFIG_SPI_GXP is not set # CONFIG_SPI_HISI_KUNPENG is not set # CONFIG_SPI_HISI_SFC_V3XX is not set CONFIG_SPI_NXP_FLEXSPI=y CONFIG_SPI_GPIO=m # CONFIG_SPI_IMG_SPFI is not set CONFIG_SPI_IMX=m # CONFIG_SPI_INGENIC is not set # CONFIG_SPI_INTEL_PLATFORM is not set # CONFIG_SPI_JCORE is not set CONFIG_SPI_LM70_LLP=m # CONFIG_SPI_LP8841_RTC is not set # CONFIG_SPI_FSL_SPI is not set # CONFIG_SPI_FSL_DSPI is not set # CONFIG_SPI_MESON_SPICC is not set # CONFIG_SPI_MESON_SPIFC is not set # CONFIG_SPI_MICROCHIP_CORE is not set CONFIG_SPI_MICROCHIP_CORE_QSPI=m # CONFIG_SPI_MT65XX is not set # CONFIG_SPI_MT7621 is not set # CONFIG_SPI_MTK_NOR is not set # CONFIG_SPI_NPCM_FIU is not set # CONFIG_SPI_NPCM_PSPI is not set # CONFIG_SPI_LANTIQ_SSC is not set # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_OMAP_UWIRE is not set # CONFIG_SPI_OMAP24XX is not set # CONFIG_SPI_TI_QSPI is not set # CONFIG_SPI_OMAP_100K is not set # CONFIG_SPI_ORION is not set # CONFIG_SPI_PIC32 is not set # CONFIG_SPI_PIC32_SQI is not set CONFIG_SPI_PL022=m # CONFIG_SPI_PXA2XX is not set CONFIG_SPI_ROCKCHIP=y # CONFIG_SPI_ROCKCHIP_SFC is not set # CONFIG_SPI_RSPI is not set # CONFIG_SPI_QUP is not set # CONFIG_SPI_S3C64XX is not set CONFIG_SPI_SC18IS602=m # CONFIG_SPI_SH_MSIOF is not set # CONFIG_SPI_SH is not set # CONFIG_SPI_SH_HSPI is not set CONFIG_SPI_SIFIVE=m # CONFIG_SPI_SPRD is not set # CONFIG_SPI_SPRD_ADI is not set # CONFIG_SPI_STM32 is not set # CONFIG_SPI_STM32_QSPI is not set # CONFIG_SPI_ST_SSC4 is not set # CONFIG_SPI_SUN4I is not set # CONFIG_SPI_SUN6I is not set # CONFIG_SPI_SUNPLUS_SP7021 is not set # CONFIG_SPI_SYNQUACER is not set # CONFIG_SPI_MXIC is not set # CONFIG_SPI_TEGRA210_QUAD is not set # CONFIG_SPI_TEGRA114 is not set # CONFIG_SPI_TEGRA20_SFLASH is not set # CONFIG_SPI_TEGRA20_SLINK is not set # CONFIG_SPI_UNIPHIER is not set CONFIG_SPI_XCOMM=m CONFIG_SPI_XILINX=m # CONFIG_SPI_XLP is not set # CONFIG_SPI_XTENSA_XTFPGA is not set # CONFIG_SPI_ZYNQ_QSPI is not set CONFIG_SPI_ZYNQMP_GQSPI=y CONFIG_SPI_AMD=m # # SPI Multiplexer support # CONFIG_SPI_MUX=y # # SPI Protocol Masters # CONFIG_SPI_SPIDEV=y CONFIG_SPI_LOOPBACK_TEST=m CONFIG_SPI_TLE62X0=m # CONFIG_SPI_SLAVE is not set CONFIG_SPMI=m CONFIG_SPMI_HISI3670=m # CONFIG_SPMI_MSM_PMIC_ARB is not set # CONFIG_SPMI_MTK_PMIF is not set CONFIG_HSI=m CONFIG_HSI_BOARDINFO=y # # HSI controllers # # CONFIG_OMAP_SSI is not set # # HSI clients # # CONFIG_HSI_CHAR is not set CONFIG_PPS=m # CONFIG_PPS_DEBUG is not set # CONFIG_NTP_PPS is not set # # PPS clients support # CONFIG_PPS_CLIENT_KTIMER=m CONFIG_PPS_CLIENT_LDISC=m # CONFIG_PPS_CLIENT_PARPORT is not set # CONFIG_PPS_CLIENT_GPIO is not set # # PPS generators support # # # PTP clock support # # CONFIG_PTP_1588_CLOCK is not set CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # # end of PTP clock support CONFIG_PINCTRL=y CONFIG_GENERIC_PINCTRL_GROUPS=y CONFIG_PINMUX=y CONFIG_GENERIC_PINMUX_FUNCTIONS=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set # CONFIG_PINCTRL_AMD is not set CONFIG_PINCTRL_AT91=y CONFIG_PINCTRL_AT91PIO4=y CONFIG_PINCTRL_AXP209=m # CONFIG_PINCTRL_BM1880 is not set CONFIG_PINCTRL_CY8C95X0=m # CONFIG_PINCTRL_DA850_PUPD is not set CONFIG_PINCTRL_DA9062=m # CONFIG_PINCTRL_EQUILIBRIUM is not set # CONFIG_PINCTRL_INGENIC is not set # CONFIG_PINCTRL_LPC18XX is not set CONFIG_PINCTRL_MCP23S08_I2C=m CONFIG_PINCTRL_MCP23S08_SPI=m CONFIG_PINCTRL_MCP23S08=m CONFIG_PINCTRL_MICROCHIP_SGPIO=m # CONFIG_PINCTRL_OCELOT is not set # CONFIG_PINCTRL_PISTACHIO is not set # CONFIG_PINCTRL_ROCKCHIP is not set # CONFIG_PINCTRL_SINGLE is not set CONFIG_PINCTRL_STMFX=m # CONFIG_PINCTRL_OWL is not set # CONFIG_PINCTRL_ASPEED_G4 is not set # CONFIG_PINCTRL_ASPEED_G5 is not set # CONFIG_PINCTRL_ASPEED_G6 is not set # CONFIG_PINCTRL_BCM281XX is not set # CONFIG_PINCTRL_BCM2835 is not set # CONFIG_PINCTRL_BCM4908 is not set # CONFIG_PINCTRL_BCM6318 is not set # CONFIG_PINCTRL_BCM6328 is not set # CONFIG_PINCTRL_BCM6358 is not set # CONFIG_PINCTRL_BCM6362 is not set # CONFIG_PINCTRL_BCM6368 is not set # CONFIG_PINCTRL_BCM63268 is not set # CONFIG_PINCTRL_IPROC_GPIO is not set # CONFIG_PINCTRL_CYGNUS_MUX is not set # CONFIG_PINCTRL_NS is not set # CONFIG_PINCTRL_NSP_GPIO is not set # CONFIG_PINCTRL_NS2_MUX is not set # CONFIG_PINCTRL_NSP_MUX is not set # CONFIG_PINCTRL_AS370 is not set # CONFIG_PINCTRL_BERLIN_BG4CT is not set CONFIG_PINCTRL_MADERA=m CONFIG_PINCTRL_CS47L15=y CONFIG_PINCTRL_CS47L85=y CONFIG_PINCTRL_IMX=y CONFIG_PINCTRL_IMX7D=y CONFIG_PINCTRL_IMX7ULP=y # CONFIG_PINCTRL_IMX8MM is not set CONFIG_PINCTRL_IMX8MN=y CONFIG_PINCTRL_IMX8MP=m CONFIG_PINCTRL_IMX8MQ=m CONFIG_PINCTRL_IMX8ULP=m CONFIG_PINCTRL_IMXRT1050=y CONFIG_PINCTRL_IMX93=m # CONFIG_PINCTRL_IMXRT1170 is not set # # Intel pinctrl drivers # # end of Intel pinctrl drivers # # MediaTek pinctrl drivers # CONFIG_EINT_MTK=y CONFIG_PINCTRL_MTK=y # CONFIG_PINCTRL_MT2701 is not set # CONFIG_PINCTRL_MT7623 is not set # CONFIG_PINCTRL_MT7629 is not set # CONFIG_PINCTRL_MT8135 is not set # CONFIG_PINCTRL_MT8127 is not set # CONFIG_PINCTRL_MT2712 is not set # CONFIG_PINCTRL_MT6765 is not set # CONFIG_PINCTRL_MT6779 is not set # CONFIG_PINCTRL_MT6795 is not set # CONFIG_PINCTRL_MT6797 is not set # CONFIG_PINCTRL_MT7622 is not set # CONFIG_PINCTRL_MT7986 is not set # CONFIG_PINCTRL_MT8167 is not set # CONFIG_PINCTRL_MT8173 is not set # CONFIG_PINCTRL_MT8183 is not set # CONFIG_PINCTRL_MT8186 is not set # CONFIG_PINCTRL_MT8188 is not set # CONFIG_PINCTRL_MT8192 is not set # CONFIG_PINCTRL_MT8195 is not set # CONFIG_PINCTRL_MT8365 is not set # CONFIG_PINCTRL_MT8516 is not set CONFIG_PINCTRL_MT6397=y # end of MediaTek pinctrl drivers CONFIG_PINCTRL_MESON=y CONFIG_PINCTRL_MESON8=y CONFIG_PINCTRL_MESON8B=y CONFIG_PINCTRL_MESON8_PMX=y # CONFIG_PINCTRL_WPCM450 is not set # CONFIG_PINCTRL_NPCM7XX is not set # CONFIG_PINCTRL_PXA25X is not set # CONFIG_PINCTRL_PXA27X is not set # CONFIG_PINCTRL_MSM is not set # CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set # CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set # CONFIG_PINCTRL_LPASS_LPI is not set # # Renesas pinctrl drivers # # CONFIG_PINCTRL_RENESAS is not set # CONFIG_PINCTRL_PFC_EMEV2 is not set # CONFIG_PINCTRL_PFC_R8A77995 is not set # CONFIG_PINCTRL_PFC_R8A7794 is not set # CONFIG_PINCTRL_PFC_R8A77990 is not set # CONFIG_PINCTRL_PFC_R8A7779 is not set # CONFIG_PINCTRL_PFC_R8A7790 is not set # CONFIG_PINCTRL_PFC_R8A77950 is not set # CONFIG_PINCTRL_PFC_R8A77951 is not set # CONFIG_PINCTRL_PFC_R8A7778 is not set # CONFIG_PINCTRL_PFC_R8A7793 is not set # CONFIG_PINCTRL_PFC_R8A7791 is not set # CONFIG_PINCTRL_PFC_R8A77965 is not set # CONFIG_PINCTRL_PFC_R8A77960 is not set # CONFIG_PINCTRL_PFC_R8A77961 is not set # CONFIG_PINCTRL_PFC_R8A779F0 is not set # CONFIG_PINCTRL_PFC_R8A7792 is not set # CONFIG_PINCTRL_PFC_R8A77980 is not set # CONFIG_PINCTRL_PFC_R8A77970 is not set # CONFIG_PINCTRL_PFC_R8A779A0 is not set # CONFIG_PINCTRL_PFC_R8A779G0 is not set # CONFIG_PINCTRL_PFC_R8A7740 is not set # CONFIG_PINCTRL_PFC_R8A73A4 is not set # CONFIG_PINCTRL_RZA1 is not set # CONFIG_PINCTRL_RZA2 is not set # CONFIG_PINCTRL_RZG2L is not set # CONFIG_PINCTRL_PFC_R8A77470 is not set # CONFIG_PINCTRL_PFC_R8A7745 is not set # CONFIG_PINCTRL_PFC_R8A7742 is not set # CONFIG_PINCTRL_PFC_R8A7743 is not set # CONFIG_PINCTRL_PFC_R8A7744 is not set # CONFIG_PINCTRL_PFC_R8A774C0 is not set # CONFIG_PINCTRL_PFC_R8A774E1 is not set # CONFIG_PINCTRL_PFC_R8A774A1 is not set # CONFIG_PINCTRL_PFC_R8A774B1 is not set # CONFIG_PINCTRL_RZN1 is not set # CONFIG_PINCTRL_RZV2M is not set # CONFIG_PINCTRL_PFC_SH7203 is not set # CONFIG_PINCTRL_PFC_SH7264 is not set # CONFIG_PINCTRL_PFC_SH7269 is not set # CONFIG_PINCTRL_PFC_SH7720 is not set # CONFIG_PINCTRL_PFC_SH7722 is not set # CONFIG_PINCTRL_PFC_SH7734 is not set # CONFIG_PINCTRL_PFC_SH7757 is not set # CONFIG_PINCTRL_PFC_SH7785 is not set # CONFIG_PINCTRL_PFC_SH7786 is not set # CONFIG_PINCTRL_PFC_SH73A0 is not set # CONFIG_PINCTRL_PFC_SH7723 is not set # CONFIG_PINCTRL_PFC_SH7724 is not set # CONFIG_PINCTRL_PFC_SHX3 is not set # end of Renesas pinctrl drivers # CONFIG_PINCTRL_EXYNOS is not set # CONFIG_PINCTRL_S3C24XX is not set # CONFIG_PINCTRL_S3C64XX is not set # CONFIG_PINCTRL_SPRD_SC9860 is not set # CONFIG_PINCTRL_STARFIVE_JH7100 is not set # CONFIG_PINCTRL_STM32F429 is not set # CONFIG_PINCTRL_STM32F469 is not set # CONFIG_PINCTRL_STM32F746 is not set # CONFIG_PINCTRL_STM32F769 is not set # CONFIG_PINCTRL_STM32H743 is not set # CONFIG_PINCTRL_STM32MP135 is not set # CONFIG_PINCTRL_STM32MP157 is not set # CONFIG_PINCTRL_TI_IODELAY is not set CONFIG_PINCTRL_UNIPHIER=y CONFIG_PINCTRL_UNIPHIER_LD4=y CONFIG_PINCTRL_UNIPHIER_PRO4=y CONFIG_PINCTRL_UNIPHIER_SLD8=y CONFIG_PINCTRL_UNIPHIER_PRO5=y CONFIG_PINCTRL_UNIPHIER_PXS2=y CONFIG_PINCTRL_UNIPHIER_LD6B=y # CONFIG_PINCTRL_UNIPHIER_LD11 is not set # CONFIG_PINCTRL_UNIPHIER_LD20 is not set # CONFIG_PINCTRL_UNIPHIER_PXS3 is not set # CONFIG_PINCTRL_UNIPHIER_NX1 is not set # CONFIG_PINCTRL_TMPV7700 is not set CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIOLIB_IRQCHIP=y CONFIG_DEBUG_GPIO=y # CONFIG_GPIO_SYSFS is not set CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y # # Memory mapped GPIO drivers # CONFIG_GPIO_74XX_MMIO=y # CONFIG_GPIO_ALTERA is not set # CONFIG_GPIO_ASPEED is not set # CONFIG_GPIO_ASPEED_SGPIO is not set # CONFIG_GPIO_ATH79 is not set # CONFIG_GPIO_RASPBERRYPI_EXP is not set # CONFIG_GPIO_BCM_KONA is not set # CONFIG_GPIO_BCM_XGS_IPROC is not set # CONFIG_GPIO_BRCMSTB is not set CONFIG_GPIO_CADENCE=m # CONFIG_GPIO_CLPS711X is not set # CONFIG_GPIO_DWAPB is not set # CONFIG_GPIO_EIC_SPRD is not set # CONFIG_GPIO_EM is not set # CONFIG_GPIO_FTGPIO010 is not set CONFIG_GPIO_GENERIC_PLATFORM=y # CONFIG_GPIO_GRGPIO is not set # CONFIG_GPIO_HISI is not set CONFIG_GPIO_HLWD=y CONFIG_GPIO_IMX_SCU=y # CONFIG_GPIO_IOP is not set CONFIG_GPIO_LOGICVC=m # CONFIG_GPIO_LPC18XX is not set # CONFIG_GPIO_LPC32XX is not set # CONFIG_GPIO_MB86S7X is not set CONFIG_GPIO_MENZ127=y CONFIG_GPIO_MPC8XXX=y # CONFIG_GPIO_MT7621 is not set CONFIG_GPIO_MXC=y # CONFIG_GPIO_MXS is not set # CONFIG_GPIO_OMAP is not set # CONFIG_GPIO_PL061 is not set # CONFIG_GPIO_PMIC_EIC_SPRD is not set # CONFIG_GPIO_PXA is not set # CONFIG_GPIO_RCAR is not set # CONFIG_GPIO_RDA is not set # CONFIG_GPIO_ROCKCHIP is not set # CONFIG_GPIO_SAMA5D2_PIOBU is not set CONFIG_GPIO_SIFIVE=y CONFIG_GPIO_SIOX=m # CONFIG_GPIO_SNPS_CREG is not set # CONFIG_GPIO_SPRD is not set # CONFIG_GPIO_STP_XWAY is not set CONFIG_GPIO_SYSCON=y # CONFIG_GPIO_TEGRA is not set # CONFIG_GPIO_TEGRA186 is not set # CONFIG_GPIO_TS4800 is not set # CONFIG_GPIO_UNIPHIER is not set CONFIG_GPIO_VF610=y # CONFIG_GPIO_VISCONTI is not set # CONFIG_GPIO_XGENE_SB is not set CONFIG_GPIO_XILINX=y # CONFIG_GPIO_XLP is not set CONFIG_GPIO_ZEVIO=y CONFIG_GPIO_AMD_FCH=y # CONFIG_GPIO_IDT3243X is not set # end of Memory mapped GPIO drivers # # I2C GPIO expanders # CONFIG_GPIO_ADNP=m CONFIG_GPIO_GW_PLD=m # CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set CONFIG_GPIO_PCA953X=m CONFIG_GPIO_PCA953X_IRQ=y # CONFIG_GPIO_PCA9570 is not set CONFIG_GPIO_PCF857X=m CONFIG_GPIO_TPIC2810=m # CONFIG_GPIO_TS4900 is not set # end of I2C GPIO expanders # # MFD GPIO expanders # CONFIG_GPIO_ARIZONA=m CONFIG_GPIO_DLN2=m CONFIG_HTC_EGPIO=y CONFIG_GPIO_KEMPLD=m CONFIG_GPIO_LP3943=m # CONFIG_GPIO_LP87565 is not set CONFIG_GPIO_MADERA=m CONFIG_GPIO_MAX77650=m # CONFIG_GPIO_SL28CPLD is not set # CONFIG_GPIO_TPS65086 is not set CONFIG_GPIO_TPS65218=m CONFIG_GPIO_TPS65912=m # end of MFD GPIO expanders # # SPI GPIO expanders # CONFIG_GPIO_74X164=y CONFIG_GPIO_MAX3191X=y # CONFIG_GPIO_MAX7301 is not set CONFIG_GPIO_MC33880=y # CONFIG_GPIO_PISOSR is not set CONFIG_GPIO_XRA1403=m CONFIG_GPIO_MOXTET=m # end of SPI GPIO expanders # # USB GPIO expanders # CONFIG_GPIO_VIPERBOARD=m # end of USB GPIO expanders # # Virtual GPIO drivers # CONFIG_GPIO_AGGREGATOR=y CONFIG_GPIO_MOCKUP=m CONFIG_GPIO_VIRTIO=m CONFIG_GPIO_SIM=y # end of Virtual GPIO drivers CONFIG_W1=m # # 1-wire Bus Masters # CONFIG_W1_MASTER_DS2490=m # CONFIG_W1_MASTER_DS2482 is not set # CONFIG_W1_MASTER_MXC is not set CONFIG_W1_MASTER_DS1WM=m CONFIG_W1_MASTER_GPIO=m CONFIG_W1_MASTER_SGI=m # end of 1-wire Bus Masters # # 1-wire Slaves # CONFIG_W1_SLAVE_THERM=m CONFIG_W1_SLAVE_SMEM=m # CONFIG_W1_SLAVE_DS2405 is not set # CONFIG_W1_SLAVE_DS2408 is not set CONFIG_W1_SLAVE_DS2413=m CONFIG_W1_SLAVE_DS2406=m CONFIG_W1_SLAVE_DS2423=m CONFIG_W1_SLAVE_DS2805=m # CONFIG_W1_SLAVE_DS2430 is not set # CONFIG_W1_SLAVE_DS2431 is not set CONFIG_W1_SLAVE_DS2433=m CONFIG_W1_SLAVE_DS2433_CRC=y # CONFIG_W1_SLAVE_DS2438 is not set CONFIG_W1_SLAVE_DS250X=m # CONFIG_W1_SLAVE_DS2780 is not set CONFIG_W1_SLAVE_DS2781=m # CONFIG_W1_SLAVE_DS28E04 is not set # CONFIG_W1_SLAVE_DS28E17 is not set # end of 1-wire Slaves # CONFIG_POWER_RESET is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_PDA_POWER=m CONFIG_APM_POWER=m CONFIG_GENERIC_ADC_BATTERY=m CONFIG_IP5XXX_POWER=m CONFIG_TEST_POWER=m CONFIG_CHARGER_ADP5061=m # CONFIG_BATTERY_ACT8945A is not set CONFIG_BATTERY_CW2015=m CONFIG_BATTERY_DS2760=m # CONFIG_BATTERY_DS2780 is not set CONFIG_BATTERY_DS2781=m CONFIG_BATTERY_DS2782=m # CONFIG_BATTERY_LEGO_EV3 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set CONFIG_BATTERY_SBS=m # CONFIG_CHARGER_SBS is not set CONFIG_BATTERY_BQ27XXX=y CONFIG_BATTERY_BQ27XXX_I2C=m CONFIG_BATTERY_BQ27XXX_HDQ=m # CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set CONFIG_CHARGER_DA9150=m # CONFIG_BATTERY_DA9150 is not set CONFIG_CHARGER_AXP20X=m # CONFIG_BATTERY_AXP20X is not set CONFIG_AXP20X_POWER=m CONFIG_BATTERY_MAX17040=m CONFIG_BATTERY_MAX17042=m CONFIG_BATTERY_MAX1721X=m CONFIG_CHARGER_PCF50633=m # CONFIG_CHARGER_ISP1704 is not set CONFIG_CHARGER_MAX8903=y CONFIG_CHARGER_LP8727=m CONFIG_CHARGER_GPIO=m # CONFIG_CHARGER_MANAGER is not set CONFIG_CHARGER_LT3651=y CONFIG_CHARGER_LTC4162L=m CONFIG_CHARGER_MAX14577=m # CONFIG_CHARGER_DETECTOR_MAX14656 is not set CONFIG_CHARGER_MAX77650=m CONFIG_CHARGER_MAX77693=m CONFIG_CHARGER_MAX77976=m CONFIG_CHARGER_MP2629=m CONFIG_CHARGER_MT6360=m CONFIG_CHARGER_MT6370=m # CONFIG_CHARGER_QCOM_SMBB is not set # CONFIG_CHARGER_BQ2415X is not set CONFIG_CHARGER_BQ24190=m CONFIG_CHARGER_BQ24257=m CONFIG_CHARGER_BQ24735=m CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ25890=m CONFIG_CHARGER_BQ25980=m # CONFIG_CHARGER_BQ256XX is not set CONFIG_CHARGER_SMB347=m # CONFIG_CHARGER_TPS65217 is not set CONFIG_BATTERY_GAUGE_LTC2941=m CONFIG_BATTERY_GOLDFISH=m CONFIG_BATTERY_RT5033=m # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_SC2731 is not set # CONFIG_FUEL_GAUGE_SC27XX is not set CONFIG_CHARGER_UCS1002=m # CONFIG_CHARGER_BD99954 is not set CONFIG_RN5T618_POWER=m # CONFIG_BATTERY_UG3105 is not set CONFIG_HWMON=y CONFIG_HWMON_VID=y CONFIG_HWMON_DEBUG_CHIP=y # # Native drivers # # CONFIG_SENSORS_AD7314 is not set CONFIG_SENSORS_AD7414=m CONFIG_SENSORS_AD7418=m CONFIG_SENSORS_ADM1021=m CONFIG_SENSORS_ADM1025=m CONFIG_SENSORS_ADM1026=m # CONFIG_SENSORS_ADM1029 is not set CONFIG_SENSORS_ADM1031=m CONFIG_SENSORS_ADM1177=m CONFIG_SENSORS_ADM9240=m CONFIG_SENSORS_ADT7X10=y CONFIG_SENSORS_ADT7310=y CONFIG_SENSORS_ADT7410=m # CONFIG_SENSORS_ADT7411 is not set CONFIG_SENSORS_ADT7462=m CONFIG_SENSORS_ADT7470=m # CONFIG_SENSORS_ADT7475 is not set CONFIG_SENSORS_AHT10=m # CONFIG_SENSORS_AS370 is not set CONFIG_SENSORS_ASC7621=m CONFIG_SENSORS_AXI_FAN_CONTROL=y # CONFIG_SENSORS_ASB100 is not set # CONFIG_SENSORS_ASPEED is not set CONFIG_SENSORS_ATXP1=m # CONFIG_SENSORS_BT1_PVT is not set CONFIG_SENSORS_DS620=m CONFIG_SENSORS_DS1621=m # CONFIG_SENSORS_SPARX5 is not set CONFIG_SENSORS_F71805F=y # CONFIG_SENSORS_F71882FG is not set CONFIG_SENSORS_F75375S=m CONFIG_SENSORS_GSC=m # CONFIG_SENSORS_MC13783_ADC is not set # CONFIG_SENSORS_FSCHMD is not set # CONFIG_SENSORS_FTSTEUTATES is not set # CONFIG_SENSORS_GL518SM is not set CONFIG_SENSORS_GL520SM=m CONFIG_SENSORS_G760A=m CONFIG_SENSORS_G762=m CONFIG_SENSORS_GPIO_FAN=m CONFIG_SENSORS_HIH6130=m # CONFIG_SENSORS_IBMAEM is not set # CONFIG_SENSORS_IBMPEX is not set CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_JC42 is not set # CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LAN966X is not set CONFIG_SENSORS_LINEAGE=m # CONFIG_SENSORS_LTC2945 is not set CONFIG_SENSORS_LTC2947=m CONFIG_SENSORS_LTC2947_I2C=m # CONFIG_SENSORS_LTC2947_SPI is not set CONFIG_SENSORS_LTC2990=m # CONFIG_SENSORS_LTC2992 is not set CONFIG_SENSORS_LTC4151=m CONFIG_SENSORS_LTC4215=m # CONFIG_SENSORS_LTC4222 is not set CONFIG_SENSORS_LTC4245=m # CONFIG_SENSORS_LTC4260 is not set CONFIG_SENSORS_LTC4261=m # CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set CONFIG_SENSORS_MAX1619=m CONFIG_SENSORS_MAX1668=m CONFIG_SENSORS_MAX197=m CONFIG_SENSORS_MAX31722=m CONFIG_SENSORS_MAX31730=m # CONFIG_SENSORS_MAX31760 is not set CONFIG_SENSORS_MAX6620=m # CONFIG_SENSORS_MAX6621 is not set CONFIG_SENSORS_MAX6639=m CONFIG_SENSORS_MAX6642=m # CONFIG_SENSORS_MAX6650 is not set CONFIG_SENSORS_MAX6697=m CONFIG_SENSORS_MAX31790=m CONFIG_SENSORS_MCP3021=m # CONFIG_SENSORS_MLXREG_FAN is not set CONFIG_SENSORS_TC654=m # CONFIG_SENSORS_TPS23861 is not set CONFIG_SENSORS_MR75203=y CONFIG_SENSORS_ADCXX=y CONFIG_SENSORS_LM63=m CONFIG_SENSORS_LM70=y CONFIG_SENSORS_LM73=m # CONFIG_SENSORS_LM75 is not set # CONFIG_SENSORS_LM77 is not set CONFIG_SENSORS_LM78=m CONFIG_SENSORS_LM80=m # CONFIG_SENSORS_LM83 is not set CONFIG_SENSORS_LM85=m CONFIG_SENSORS_LM87=m # CONFIG_SENSORS_LM90 is not set CONFIG_SENSORS_LM92=m CONFIG_SENSORS_LM93=m # CONFIG_SENSORS_LM95234 is not set # CONFIG_SENSORS_LM95241 is not set CONFIG_SENSORS_LM95245=m CONFIG_SENSORS_PC87360=y CONFIG_SENSORS_PC87427=y CONFIG_SENSORS_NTC_THERMISTOR=m # CONFIG_SENSORS_NCT6683 is not set CONFIG_SENSORS_NCT6775_CORE=m # CONFIG_SENSORS_NCT6775 is not set CONFIG_SENSORS_NCT6775_I2C=m CONFIG_SENSORS_NCT7802=m CONFIG_SENSORS_NCT7904=m CONFIG_SENSORS_NPCM7XX=m # CONFIG_SENSORS_NSA320 is not set CONFIG_SENSORS_OCC_P8_I2C=m CONFIG_SENSORS_OCC=m CONFIG_SENSORS_PCF8591=m # CONFIG_SENSORS_PECI_CPUTEMP is not set # CONFIG_SENSORS_PECI_DIMMTEMP is not set # CONFIG_PMBUS is not set # CONFIG_SENSORS_PWM_FAN is not set # CONFIG_SENSORS_RASPBERRYPI_HWMON is not set # CONFIG_SENSORS_SL28CPLD is not set # CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SBRMI is not set # CONFIG_SENSORS_SHT15 is not set CONFIG_SENSORS_SHT21=m CONFIG_SENSORS_SHT3x=m # CONFIG_SENSORS_SHT4x is not set # CONFIG_SENSORS_SHTC1 is not set CONFIG_SENSORS_SY7636A=m CONFIG_SENSORS_DME1737=m # CONFIG_SENSORS_EMC1403 is not set CONFIG_SENSORS_EMC2103=m CONFIG_SENSORS_EMC2305=m CONFIG_SENSORS_EMC6W201=m # CONFIG_SENSORS_SMSC47M1 is not set CONFIG_SENSORS_SMSC47M192=m # CONFIG_SENSORS_SMSC47B397 is not set CONFIG_SENSORS_SCH56XX_COMMON=y CONFIG_SENSORS_SCH5627=y CONFIG_SENSORS_SCH5636=y CONFIG_SENSORS_STTS751=m CONFIG_SENSORS_SMM665=m # CONFIG_SENSORS_ADC128D818 is not set CONFIG_SENSORS_ADS7828=m CONFIG_SENSORS_ADS7871=y CONFIG_SENSORS_AMC6821=m CONFIG_SENSORS_INA209=m CONFIG_SENSORS_INA2XX=m # CONFIG_SENSORS_INA238 is not set CONFIG_SENSORS_INA3221=m CONFIG_SENSORS_TC74=m CONFIG_SENSORS_THMC50=m CONFIG_SENSORS_TMP102=m CONFIG_SENSORS_TMP103=m # CONFIG_SENSORS_TMP108 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set CONFIG_SENSORS_TMP464=m CONFIG_SENSORS_TMP513=m CONFIG_SENSORS_VEXPRESS=m CONFIG_SENSORS_VT1211=y # CONFIG_SENSORS_W83773G is not set # CONFIG_SENSORS_W83781D is not set CONFIG_SENSORS_W83791D=m CONFIG_SENSORS_W83792D=m CONFIG_SENSORS_W83793=m CONFIG_SENSORS_W83795=m CONFIG_SENSORS_W83795_FANCTRL=y # CONFIG_SENSORS_W83L785TS is not set CONFIG_SENSORS_W83L786NG=m # CONFIG_SENSORS_W83627HF is not set CONFIG_SENSORS_W83627EHF=y # CONFIG_THERMAL is not set CONFIG_WATCHDOG=y CONFIG_WATCHDOG_CORE=y CONFIG_WATCHDOG_NOWAYOUT=y CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set # CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set # # Watchdog Pretimeout Governors # # CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set # # Watchdog Device Drivers # CONFIG_SOFT_WATCHDOG=m # CONFIG_DA9052_WATCHDOG is not set # CONFIG_DA9055_WATCHDOG is not set CONFIG_DA9063_WATCHDOG=m CONFIG_DA9062_WATCHDOG=m CONFIG_GPIO_WATCHDOG=y CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y # CONFIG_MENF21BMC_WATCHDOG is not set CONFIG_MENZ069_WATCHDOG=m # CONFIG_XILINX_WATCHDOG is not set CONFIG_ZIIRAVE_WATCHDOG=m # CONFIG_MLX_WDT is not set # CONFIG_SL28CPLD_WATCHDOG is not set CONFIG_ARM_SP805_WATCHDOG=y # CONFIG_ARMADA_37XX_WATCHDOG is not set # CONFIG_ASM9260_WATCHDOG is not set # CONFIG_AT91RM9200_WATCHDOG is not set CONFIG_AT91SAM9X_WATCHDOG=m CONFIG_SAMA5D4_WATCHDOG=m # CONFIG_CADENCE_WATCHDOG is not set # CONFIG_977_WATCHDOG is not set CONFIG_FTWDT010_WATCHDOG=m # CONFIG_S3C2410_WATCHDOG is not set CONFIG_DW_WATCHDOG=y # CONFIG_EP93XX_WATCHDOG is not set # CONFIG_OMAP_WATCHDOG is not set # CONFIG_PNX4008_WATCHDOG is not set # CONFIG_DAVINCI_WATCHDOG is not set # CONFIG_K3_RTI_WATCHDOG is not set # CONFIG_ORION_WATCHDOG is not set # CONFIG_RN5T618_WATCHDOG is not set # CONFIG_SUNXI_WATCHDOG is not set # CONFIG_NPCM7XX_WATCHDOG is not set # CONFIG_STMP3XXX_RTC_WATCHDOG is not set # CONFIG_TS4800_WATCHDOG is not set # CONFIG_TS72XX_WATCHDOG is not set # CONFIG_MAX63XX_WATCHDOG is not set # CONFIG_MAX77620_WATCHDOG is not set # CONFIG_IMX2_WDT is not set # CONFIG_IMX7ULP_WDT is not set # CONFIG_RETU_WATCHDOG is not set # CONFIG_MOXART_WDT is not set # CONFIG_ST_LPC_WATCHDOG is not set # CONFIG_TEGRA_WATCHDOG is not set # CONFIG_QCOM_WDT is not set # CONFIG_MESON_GXBB_WATCHDOG is not set # CONFIG_MESON_WATCHDOG is not set # CONFIG_MEDIATEK_WATCHDOG is not set # CONFIG_DIGICOLOR_WATCHDOG is not set # CONFIG_LPC18XX_WATCHDOG is not set # CONFIG_RENESAS_WDT is not set # CONFIG_RENESAS_RZAWDT is not set # CONFIG_RENESAS_RZN1WDT is not set # CONFIG_RENESAS_RZG2LWDT is not set # CONFIG_ASPEED_WATCHDOG is not set # CONFIG_UNIPHIER_WATCHDOG is not set # CONFIG_RTD119X_WATCHDOG is not set # CONFIG_REALTEK_OTTO_WDT is not set # CONFIG_SPRD_WATCHDOG is not set # CONFIG_VISCONTI_WATCHDOG is not set # CONFIG_MSC313E_WATCHDOG is not set # CONFIG_APPLE_WATCHDOG is not set # CONFIG_SUNPLUS_WATCHDOG is not set # CONFIG_SC520_WDT is not set CONFIG_KEMPLD_WDT=y # CONFIG_ATH79_WDT is not set # CONFIG_BCM47XX_WDT is not set # CONFIG_BCM2835_WDT is not set # CONFIG_BCM_KONA_WDT is not set # CONFIG_BCM7038_WDT is not set # CONFIG_IMGPDC_WDT is not set # CONFIG_MPC5200_WDT is not set CONFIG_MEN_A21_WDT=y # CONFIG_UML_WATCHDOG is not set # # USB-based Watchdog Cards # # CONFIG_USBPCWATCHDOG is not set CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set CONFIG_BCMA_POSSIBLE=y # CONFIG_BCMA is not set # # Multifunction device drivers # CONFIG_MFD_CORE=y CONFIG_MFD_ACT8945A=m # CONFIG_MFD_SUN4I_GPADC is not set CONFIG_MFD_AT91_USART=y CONFIG_MFD_ATMEL_FLEXCOM=y # CONFIG_MFD_ATMEL_HLCDC is not set CONFIG_MFD_ATMEL_SMC=y CONFIG_MFD_BCM590XX=m # CONFIG_MFD_BD9571MWV is not set CONFIG_MFD_AXP20X=m CONFIG_MFD_AXP20X_I2C=m CONFIG_MFD_MADERA=m # CONFIG_MFD_MADERA_I2C is not set CONFIG_MFD_MADERA_SPI=m CONFIG_MFD_CS47L15=y # CONFIG_MFD_CS47L35 is not set CONFIG_MFD_CS47L85=y # CONFIG_MFD_CS47L90 is not set # CONFIG_MFD_CS47L92 is not set CONFIG_MFD_CS48L32=y # CONFIG_MFD_ASIC3 is not set # CONFIG_MFD_DA9052_SPI is not set CONFIG_MFD_DA9062=m CONFIG_MFD_DA9063=m CONFIG_MFD_DA9150=m CONFIG_MFD_DLN2=m # CONFIG_MFD_ENE_KB3930 is not set # CONFIG_MFD_EXYNOS_LPASS is not set CONFIG_MFD_GATEWORKS_GSC=m CONFIG_MFD_MC13XXX=m CONFIG_MFD_MC13XXX_SPI=m # CONFIG_MFD_MC13XXX_I2C is not set CONFIG_MFD_MP2629=m # CONFIG_MFD_MXS_LRADC is not set # CONFIG_MFD_MX25_TSADC is not set # CONFIG_MFD_HI6421_PMIC is not set CONFIG_MFD_HI6421_SPMI=m # CONFIG_MFD_HI655X_PMIC is not set CONFIG_HTC_PASIC3=m CONFIG_MFD_IQS62X=m CONFIG_MFD_KEMPLD=y CONFIG_MFD_88PM800=m # CONFIG_MFD_88PM805 is not set CONFIG_MFD_MAX14577=m CONFIG_MFD_MAX77650=m CONFIG_MFD_MAX77686=m CONFIG_MFD_MAX77693=m CONFIG_MFD_MAX77714=m CONFIG_MFD_MAX8907=m CONFIG_MFD_MT6360=m CONFIG_MFD_MT6370=m CONFIG_MFD_MT6397=m # CONFIG_MFD_MENF21BMC is not set CONFIG_MFD_OCELOT=m CONFIG_EZX_PCAP=y # CONFIG_MFD_CPCAP is not set CONFIG_MFD_VIPERBOARD=y CONFIG_MFD_NTXEC=m CONFIG_MFD_RETU=m CONFIG_MFD_PCF50633=m CONFIG_PCF50633_ADC=m CONFIG_PCF50633_GPIO=m # CONFIG_MFD_PM8XXX is not set # CONFIG_MFD_SPMI_PMIC is not set CONFIG_MFD_SY7636A=m # CONFIG_MFD_RT4831 is not set # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RT5120 is not set # CONFIG_MFD_RK808 is not set CONFIG_MFD_RN5T618=m CONFIG_MFD_SI476X_CORE=m CONFIG_MFD_SIMPLE_MFD_I2C=m # CONFIG_MFD_SL28CPLD is not set CONFIG_MFD_SM501=y # CONFIG_MFD_SM501_GPIO is not set # CONFIG_MFD_SKY81452 is not set # CONFIG_MFD_SC27XX_PMIC is not set # CONFIG_ABX500_CORE is not set # CONFIG_MFD_STMPE is not set # CONFIG_MFD_SUN6I_PRCM is not set CONFIG_MFD_SYSCON=y # CONFIG_MFD_TI_AM335X_TSCADC is not set CONFIG_MFD_LP3943=m CONFIG_MFD_TI_LMU=m # CONFIG_TPS6105X is not set CONFIG_TPS65010=m # CONFIG_TPS6507X is not set CONFIG_MFD_TPS65086=m CONFIG_MFD_TPS65217=m # CONFIG_MFD_TI_LP873X is not set CONFIG_MFD_TI_LP87565=m CONFIG_MFD_TPS65218=m CONFIG_MFD_TPS65912=m CONFIG_MFD_TPS65912_I2C=m # CONFIG_MFD_TPS65912_SPI is not set CONFIG_MFD_WL1273_CORE=m CONFIG_MFD_LM3533=m CONFIG_MFD_TMIO=y CONFIG_MFD_T7L66XB=y # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set CONFIG_MFD_TQMX86=y CONFIG_MFD_ARIZONA=m CONFIG_MFD_ARIZONA_I2C=m # CONFIG_MFD_ARIZONA_SPI is not set CONFIG_MFD_CS47L24=y # CONFIG_MFD_WM5102 is not set # CONFIG_MFD_WM5110 is not set CONFIG_MFD_WM8997=y # CONFIG_MFD_WM8998 is not set # CONFIG_MFD_WM831X_SPI is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_STW481X is not set # CONFIG_MFD_STM32_LPTIMER is not set # CONFIG_MFD_STM32_TIMERS is not set CONFIG_MFD_STMFX=m # CONFIG_MFD_ATC260X_I2C is not set # CONFIG_MFD_KHADAS_MCU is not set # CONFIG_MFD_ACER_A500_EC is not set # CONFIG_MFD_QCOM_PM8008 is not set # CONFIG_MFD_VEXPRESS_SYSREG is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set CONFIG_MFD_RSMU_I2C=m CONFIG_MFD_RSMU_SPI=y # end of Multifunction device drivers CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_VIRTUAL_CONSUMER=y # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set CONFIG_REGULATOR_88PG86X=m CONFIG_REGULATOR_88PM800=m # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_ACT8945A is not set # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_ANATOP=m CONFIG_REGULATOR_AXP20X=m CONFIG_REGULATOR_BCM590XX=m # CONFIG_REGULATOR_DA9062 is not set CONFIG_REGULATOR_DA9063=m CONFIG_REGULATOR_DA9121=m CONFIG_REGULATOR_DA9210=m CONFIG_REGULATOR_DA9211=m # CONFIG_REGULATOR_FAN53555 is not set CONFIG_REGULATOR_FAN53880=m CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_HI6421V600=m CONFIG_REGULATOR_ISL9305=m CONFIG_REGULATOR_ISL6271A=m CONFIG_REGULATOR_LM363X=m CONFIG_REGULATOR_LP3971=m CONFIG_REGULATOR_LP3972=m # CONFIG_REGULATOR_LP872X is not set CONFIG_REGULATOR_LP8755=m CONFIG_REGULATOR_LP87565=m # CONFIG_REGULATOR_LTC3589 is not set CONFIG_REGULATOR_LTC3676=m CONFIG_REGULATOR_MAX14577=m CONFIG_REGULATOR_MAX1586=m # CONFIG_REGULATOR_MAX77620 is not set # CONFIG_REGULATOR_MAX77650 is not set # CONFIG_REGULATOR_MAX8649 is not set CONFIG_REGULATOR_MAX8660=m # CONFIG_REGULATOR_MAX8893 is not set CONFIG_REGULATOR_MAX8907=m # CONFIG_REGULATOR_MAX8952 is not set CONFIG_REGULATOR_MAX20086=m CONFIG_REGULATOR_MAX77686=m CONFIG_REGULATOR_MAX77693=m CONFIG_REGULATOR_MAX77802=m # CONFIG_REGULATOR_MAX77826 is not set CONFIG_REGULATOR_MC13XXX_CORE=m CONFIG_REGULATOR_MC13783=m CONFIG_REGULATOR_MC13892=m # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MP5416 is not set # CONFIG_REGULATOR_MP8859 is not set # CONFIG_REGULATOR_MP886X is not set CONFIG_REGULATOR_MPQ7920=m CONFIG_REGULATOR_MT6311=m # CONFIG_REGULATOR_MT6315 is not set # CONFIG_REGULATOR_MT6323 is not set # CONFIG_REGULATOR_MT6331 is not set CONFIG_REGULATOR_MT6332=m CONFIG_REGULATOR_MT6358=m CONFIG_REGULATOR_MT6359=m CONFIG_REGULATOR_MT6360=m # CONFIG_REGULATOR_MT6370 is not set CONFIG_REGULATOR_MT6397=m # CONFIG_REGULATOR_PBIAS is not set # CONFIG_REGULATOR_PCA9450 is not set CONFIG_REGULATOR_PCAP=y # CONFIG_REGULATOR_PCF50633 is not set CONFIG_REGULATOR_PF8X00=m CONFIG_REGULATOR_PFUZE100=m CONFIG_REGULATOR_PV88060=m CONFIG_REGULATOR_PV88080=m CONFIG_REGULATOR_PV88090=m # CONFIG_REGULATOR_PWM is not set # CONFIG_REGULATOR_QCOM_RPMH is not set CONFIG_REGULATOR_QCOM_SPMI=m # CONFIG_REGULATOR_QCOM_USB_VBUS is not set CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m CONFIG_REGULATOR_RN5T618=m CONFIG_REGULATOR_RT4801=m CONFIG_REGULATOR_RT5190A=m # CONFIG_REGULATOR_RT5759 is not set CONFIG_REGULATOR_RT6160=m CONFIG_REGULATOR_RT6245=m CONFIG_REGULATOR_RTQ2134=m CONFIG_REGULATOR_RTMV20=m CONFIG_REGULATOR_RTQ6752=m # CONFIG_REGULATOR_S2MPA01 is not set # CONFIG_REGULATOR_S2MPS11 is not set # CONFIG_REGULATOR_S5M8767 is not set # CONFIG_REGULATOR_SC2731 is not set CONFIG_REGULATOR_SLG51000=m # CONFIG_REGULATOR_STM32_BOOSTER is not set # CONFIG_REGULATOR_STM32_VREFBUF is not set # CONFIG_REGULATOR_STM32_PWR is not set # CONFIG_REGULATOR_TI_ABB is not set # CONFIG_REGULATOR_STW481X_VMMC is not set CONFIG_REGULATOR_SY7636A=m CONFIG_REGULATOR_SY8106A=m # CONFIG_REGULATOR_SY8824X is not set CONFIG_REGULATOR_SY8827N=m CONFIG_REGULATOR_TPS51632=m # CONFIG_REGULATOR_TPS62360 is not set CONFIG_REGULATOR_TPS6286X=m CONFIG_REGULATOR_TPS65023=m CONFIG_REGULATOR_TPS6507X=m CONFIG_REGULATOR_TPS65086=m CONFIG_REGULATOR_TPS65132=m # CONFIG_REGULATOR_TPS65217 is not set CONFIG_REGULATOR_TPS65218=m CONFIG_REGULATOR_TPS6524X=m # CONFIG_REGULATOR_TPS65912 is not set # CONFIG_REGULATOR_TPS68470 is not set # CONFIG_REGULATOR_UNIPHIER is not set CONFIG_REGULATOR_VCTRL=y # CONFIG_REGULATOR_VEXPRESS is not set # CONFIG_REGULATOR_QCOM_LABIBB is not set CONFIG_CEC_CORE=y CONFIG_CEC_NOTIFIER=y CONFIG_CEC_PIN=y # # CEC support # # CONFIG_CEC_PIN_ERROR_INJ is not set CONFIG_MEDIA_CEC_SUPPORT=y CONFIG_CEC_CH7322=m # CONFIG_CEC_MESON_AO is not set # CONFIG_CEC_MESON_G12A_AO is not set CONFIG_CEC_GPIO=y # CONFIG_CEC_SAMSUNG_S5P is not set # CONFIG_CEC_STI is not set # CONFIG_CEC_STM32 is not set # CONFIG_CEC_TEGRA is not set CONFIG_USB_PULSE8_CEC=y CONFIG_USB_RAINSHADOW_CEC=y # end of CEC support # CONFIG_MEDIA_SUPPORT is not set # # Graphics support # # CONFIG_TEGRA_HOST1X is not set # CONFIG_IMX_IPUV3_CORE is not set # CONFIG_DRM is not set # CONFIG_DRM_DEBUG_MODESET_LOCK is not set # # ARM devices # # end of ARM devices # # Frame buffer Devices # CONFIG_FB_CMDLINE=y CONFIG_FB_NOTIFY=y CONFIG_FB=m CONFIG_FIRMWARE_EDID=y CONFIG_FB_CFB_FILLRECT=m CONFIG_FB_CFB_COPYAREA=m CONFIG_FB_CFB_IMAGEBLIT=m CONFIG_FB_SYS_FILLRECT=m CONFIG_FB_SYS_COPYAREA=m CONFIG_FB_SYS_IMAGEBLIT=m # CONFIG_FB_FOREIGN_ENDIAN is not set CONFIG_FB_SYS_FOPS=m CONFIG_FB_DEFERRED_IO=y CONFIG_FB_BACKLIGHT=m CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y # # Frame buffer hardware drivers # CONFIG_FB_ARMCLCD=m # CONFIG_FB_CLPS711X is not set CONFIG_FB_IMX=m # CONFIG_FB_ARC is not set # CONFIG_FB_PVR2 is not set CONFIG_FB_OPENCORES=m CONFIG_FB_S1D13XXX=m # CONFIG_FB_ATMEL is not set # CONFIG_FB_PXA168 is not set # CONFIG_FB_W100 is not set # CONFIG_FB_SH_MOBILE_LCDC is not set CONFIG_FB_TMIO=m CONFIG_FB_TMIO_ACCELL=y # CONFIG_FB_S3C is not set CONFIG_FB_SM501=m CONFIG_FB_SMSCUFX=m # CONFIG_FB_UDL is not set CONFIG_FB_IBM_GXT4500=m # CONFIG_FB_GOLDFISH is not set # CONFIG_FB_DA8XX is not set CONFIG_FB_VIRTUAL=m # CONFIG_FB_METRONOME is not set # CONFIG_FB_BROADSHEET is not set # CONFIG_FB_SIMPLE is not set # CONFIG_FB_SSD1307 is not set # CONFIG_FB_OMAP is not set # CONFIG_FB_OMAP2 is not set # CONFIG_MMP_DISP is not set # end of Frame buffer Devices # # Backlight & LCD device support # CONFIG_LCD_CLASS_DEVICE=y # CONFIG_LCD_L4F00242T03 is not set CONFIG_LCD_LMS283GF05=y CONFIG_LCD_LTV350QV=y # CONFIG_LCD_ILI922X is not set CONFIG_LCD_ILI9320=y CONFIG_LCD_TDO24M=m CONFIG_LCD_VGG2432A4=y CONFIG_LCD_PLATFORM=y CONFIG_LCD_AMS369FG06=m CONFIG_LCD_LMS501KF03=m # CONFIG_LCD_HX8357 is not set # CONFIG_LCD_OTM3225A is not set CONFIG_BACKLIGHT_CLASS_DEVICE=m # CONFIG_BACKLIGHT_KTD253 is not set CONFIG_BACKLIGHT_LM3533=m # CONFIG_BACKLIGHT_OMAP1 is not set CONFIG_BACKLIGHT_PWM=m CONFIG_BACKLIGHT_MT6370=m CONFIG_BACKLIGHT_QCOM_WLED=m CONFIG_BACKLIGHT_ADP8860=m CONFIG_BACKLIGHT_ADP8870=m CONFIG_BACKLIGHT_PCF50633=m CONFIG_BACKLIGHT_LM3630A=m # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m CONFIG_BACKLIGHT_TPS65217=m CONFIG_BACKLIGHT_GPIO=m # CONFIG_BACKLIGHT_LV5207LP is not set CONFIG_BACKLIGHT_BD6107=m # CONFIG_BACKLIGHT_ARCXCNN is not set CONFIG_BACKLIGHT_LED=m # end of Backlight & LCD device support CONFIG_VIDEOMODE_HELPERS=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y # end of Graphics support CONFIG_SOUND=y # CONFIG_SND is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=y # CONFIG_USB_LED_TRIG is not set CONFIG_USB_ULPI_BUS=m CONFIG_USB_CONN_GPIO=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options # # CONFIG_USB_DEFAULT_PERSIST is not set # CONFIG_USB_FEW_INIT_RETRIES is not set # CONFIG_USB_DYNAMIC_MINORS is not set CONFIG_USB_OTG=y CONFIG_USB_OTG_PRODUCTLIST=y CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB=y CONFIG_USB_OTG_FSM=y CONFIG_USB_LEDS_TRIGGER_USBPORT=y CONFIG_USB_AUTOSUSPEND_DELAY=2 CONFIG_USB_MON=m # # USB Host Controller Drivers # CONFIG_USB_C67X00_HCD=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DBGCAP=y # CONFIG_USB_XHCI_PCI_RENESAS is not set CONFIG_USB_XHCI_PLATFORM=m # CONFIG_USB_XHCI_HISTB is not set # CONFIG_USB_XHCI_MTK is not set # CONFIG_USB_XHCI_MVEBU is not set # CONFIG_USB_XHCI_RCAR is not set # CONFIG_USB_BRCMSTB is not set CONFIG_USB_EHCI_HCD=m CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_EHCI_FSL=m # CONFIG_USB_EHCI_HCD_NPCM7XX is not set # CONFIG_USB_EHCI_HCD_ORION is not set # CONFIG_USB_EHCI_HCD_SPEAR is not set # CONFIG_USB_EHCI_HCD_STI is not set CONFIG_USB_EHCI_HCD_AT91=m # CONFIG_USB_EHCI_SH is not set # CONFIG_USB_EHCI_EXYNOS is not set # CONFIG_USB_EHCI_MV is not set # CONFIG_USB_CNS3XXX_EHCI is not set # CONFIG_USB_EHCI_HCD_PLATFORM is not set CONFIG_USB_OXU210HP_HCD=y CONFIG_USB_ISP116X_HCD=m # CONFIG_USB_ISP1362_HCD is not set # CONFIG_USB_FOTG210_HCD is not set CONFIG_USB_MAX3421_HCD=m CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_HCD_SPEAR is not set # CONFIG_USB_OHCI_HCD_STI is not set # CONFIG_USB_OHCI_HCD_S3C2410 is not set CONFIG_USB_OHCI_HCD_LPC32XX=m CONFIG_USB_OHCI_HCD_AT91=m # CONFIG_USB_OHCI_HCD_OMAP3 is not set # CONFIG_USB_OHCI_HCD_DAVINCI is not set # CONFIG_USB_OHCI_SH is not set # CONFIG_USB_OHCI_EXYNOS is not set # CONFIG_USB_CNS3XXX_OHCI is not set CONFIG_USB_OHCI_HCD_PLATFORM=y # CONFIG_USB_U132_HCD is not set # CONFIG_USB_SL811_HCD is not set CONFIG_USB_R8A66597_HCD=m CONFIG_USB_HCD_TEST_MODE=y # # USB Device Class drivers # CONFIG_USB_ACM=y # CONFIG_USB_PRINTER is not set CONFIG_USB_WDM=m CONFIG_USB_TMC=m # # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # # also be needed; see USB_STORAGE Help for more info # # # USB Imaging devices # CONFIG_USB_MDC800=m # CONFIG_USBIP_CORE is not set CONFIG_USB_CDNS_SUPPORT=m # CONFIG_USB_CDNS3 is not set # CONFIG_USB_MTU3 is not set CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_HOST=y # # Platform Glue Layer # # CONFIG_USB_MUSB_TUSB6010 is not set # CONFIG_USB_MUSB_DSPS is not set # CONFIG_USB_MUSB_UX500 is not set # # MUSB DMA mode # CONFIG_MUSB_PIO_ONLY=y CONFIG_USB_DWC3=m # CONFIG_USB_DWC3_ULPI is not set CONFIG_USB_DWC3_HOST=y # # Platform Glue Driver Support # CONFIG_USB_DWC3_OMAP=m CONFIG_USB_DWC3_EXYNOS=m CONFIG_USB_DWC3_KEYSTONE=m CONFIG_USB_DWC3_MESON_G12A=m CONFIG_USB_DWC3_OF_SIMPLE=m CONFIG_USB_DWC3_ST=m CONFIG_USB_DWC3_QCOM=m CONFIG_USB_DWC3_IMX8MP=m CONFIG_USB_DWC3_AM62=m # CONFIG_USB_DWC2 is not set CONFIG_USB_CHIPIDEA=m # CONFIG_USB_CHIPIDEA_HOST is not set CONFIG_USB_CHIPIDEA_MSM=m CONFIG_USB_CHIPIDEA_IMX=m # CONFIG_USB_CHIPIDEA_GENERIC is not set # CONFIG_USB_CHIPIDEA_TEGRA is not set CONFIG_USB_ISP1760=y CONFIG_USB_ISP1760_HCD=y CONFIG_USB_ISP1760_HOST_ROLE=y # # USB port drivers # # CONFIG_USB_USS720 is not set CONFIG_USB_SERIAL=y # CONFIG_USB_SERIAL_CONSOLE is not set # CONFIG_USB_SERIAL_GENERIC is not set CONFIG_USB_SERIAL_SIMPLE=m CONFIG_USB_SERIAL_AIRCABLE=m CONFIG_USB_SERIAL_ARK3116=m CONFIG_USB_SERIAL_BELKIN=m CONFIG_USB_SERIAL_CH341=y CONFIG_USB_SERIAL_WHITEHEAT=y CONFIG_USB_SERIAL_DIGI_ACCELEPORT=y CONFIG_USB_SERIAL_CP210X=y CONFIG_USB_SERIAL_CYPRESS_M8=y # CONFIG_USB_SERIAL_EMPEG is not set CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_SERIAL_VISOR=m # CONFIG_USB_SERIAL_IPAQ is not set CONFIG_USB_SERIAL_IR=y CONFIG_USB_SERIAL_EDGEPORT=m CONFIG_USB_SERIAL_EDGEPORT_TI=m CONFIG_USB_SERIAL_F81232=m CONFIG_USB_SERIAL_F8153X=y CONFIG_USB_SERIAL_GARMIN=y CONFIG_USB_SERIAL_IPW=m CONFIG_USB_SERIAL_IUU=m CONFIG_USB_SERIAL_KEYSPAN_PDA=m # CONFIG_USB_SERIAL_KEYSPAN is not set CONFIG_USB_SERIAL_KLSI=y # CONFIG_USB_SERIAL_KOBIL_SCT is not set # CONFIG_USB_SERIAL_MCT_U232 is not set CONFIG_USB_SERIAL_METRO=m # CONFIG_USB_SERIAL_MOS7720 is not set CONFIG_USB_SERIAL_MOS7840=y CONFIG_USB_SERIAL_MXUPORT=y CONFIG_USB_SERIAL_NAVMAN=m # CONFIG_USB_SERIAL_PL2303 is not set CONFIG_USB_SERIAL_OTI6858=m # CONFIG_USB_SERIAL_QCAUX is not set CONFIG_USB_SERIAL_QUALCOMM=m CONFIG_USB_SERIAL_SPCP8X5=y # CONFIG_USB_SERIAL_SAFE is not set # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set CONFIG_USB_SERIAL_SYMBOL=y CONFIG_USB_SERIAL_TI=y CONFIG_USB_SERIAL_CYBERJACK=m CONFIG_USB_SERIAL_WWAN=m # CONFIG_USB_SERIAL_OPTION is not set CONFIG_USB_SERIAL_OMNINET=m # CONFIG_USB_SERIAL_OPTICON is not set CONFIG_USB_SERIAL_XSENS_MT=m CONFIG_USB_SERIAL_WISHBONE=y # CONFIG_USB_SERIAL_SSU100 is not set # CONFIG_USB_SERIAL_QT2 is not set CONFIG_USB_SERIAL_UPD78F0730=m # CONFIG_USB_SERIAL_XR is not set CONFIG_USB_SERIAL_DEBUG=m # # USB Miscellaneous drivers # CONFIG_USB_EMI62=y # CONFIG_USB_EMI26 is not set CONFIG_USB_ADUTUX=y CONFIG_USB_SEVSEG=y CONFIG_USB_LEGOTOWER=y # CONFIG_USB_LCD is not set CONFIG_USB_CYPRESS_CY7C63=m CONFIG_USB_CYTHERM=m # CONFIG_USB_IDMOUSE is not set CONFIG_USB_FTDI_ELAN=y CONFIG_USB_APPLEDISPLAY=m # CONFIG_USB_QCOM_EUD is not set # CONFIG_APPLE_MFI_FASTCHARGE is not set # CONFIG_USB_SISUSBVGA is not set CONFIG_USB_LD=y CONFIG_USB_TRANCEVIBRATOR=m CONFIG_USB_IOWARRIOR=m # CONFIG_USB_TEST is not set CONFIG_USB_EHSET_TEST_FIXTURE=y # CONFIG_USB_ISIGHTFW is not set CONFIG_USB_YUREX=y CONFIG_USB_EZUSB_FX2=y CONFIG_USB_HUB_USB251XB=m CONFIG_USB_HSIC_USB3503=m # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set CONFIG_USB_CHAOSKEY=y # CONFIG_BRCM_USB_PINMAP is not set CONFIG_USB_ONBOARD_HUB=y # # USB Physical Layer drivers # CONFIG_USB_PHY=y # CONFIG_ISP1301_OMAP is not set # CONFIG_NOP_USB_XCEIV is not set # CONFIG_USB_GPIO_VBUS is not set CONFIG_TAHVO_USB=m CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y CONFIG_USB_ISP1301=m # CONFIG_USB_MXS_PHY is not set # CONFIG_USB_TEGRA_PHY is not set # CONFIG_USB_ULPI is not set # CONFIG_JZ4770_PHY is not set # end of USB Physical Layer drivers # CONFIG_USB_GADGET is not set CONFIG_TYPEC=m CONFIG_TYPEC_TCPM=m CONFIG_TYPEC_TCPCI=m CONFIG_TYPEC_RT1711H=m CONFIG_TYPEC_MT6360=m # CONFIG_TYPEC_TCPCI_MT6370 is not set # CONFIG_TYPEC_TCPCI_MAXIM is not set CONFIG_TYPEC_FUSB302=m CONFIG_TYPEC_UCSI=m # CONFIG_UCSI_CCG is not set CONFIG_UCSI_STM32G0=m CONFIG_TYPEC_TPS6598X=m CONFIG_TYPEC_ANX7411=m CONFIG_TYPEC_RT1719=m CONFIG_TYPEC_HD3SS3220=m CONFIG_TYPEC_STUSB160X=m # CONFIG_TYPEC_QCOM_PMIC is not set CONFIG_TYPEC_WUSB3801=m # # USB Type-C Multiplexer/DeMultiplexer Switch support # # CONFIG_TYPEC_MUX_FSA4480 is not set # CONFIG_TYPEC_MUX_PI3USB30532 is not set # end of USB Type-C Multiplexer/DeMultiplexer Switch support # # USB Type-C Alternate Mode drivers # # end of USB Type-C Alternate Mode drivers CONFIG_USB_ROLE_SWITCH=y CONFIG_MMC=m CONFIG_PWRSEQ_EMMC=m # CONFIG_PWRSEQ_SIMPLE is not set CONFIG_SDIO_UART=m # CONFIG_MMC_TEST is not set # # MMC/SD/SDIO Host Controller Drivers # # CONFIG_MMC_DEBUG is not set CONFIG_MMC_ARMMMCI=m # CONFIG_MMC_STM32_SDMMC is not set # CONFIG_MMC_SDHCI is not set # CONFIG_MMC_MESON_GX is not set # CONFIG_MMC_MESON_MX_SDHC is not set # CONFIG_MMC_MESON_MX_SDIO is not set # CONFIG_MMC_MOXART is not set # CONFIG_MMC_OMAP_HS is not set CONFIG_MMC_ATMELMCI=m CONFIG_MMC_MXC=m # CONFIG_MMC_MVSDIO is not set # CONFIG_MMC_DAVINCI is not set # CONFIG_MMC_SPI is not set # CONFIG_MMC_S3C is not set CONFIG_MMC_TMIO_CORE=m CONFIG_MMC_TMIO=m # CONFIG_MMC_SDHI is not set # CONFIG_MMC_UNIPHIER is not set CONFIG_MMC_DW=m CONFIG_MMC_DW_PLTFM=m CONFIG_MMC_DW_BLUEFIELD=m CONFIG_MMC_DW_EXYNOS=m # CONFIG_MMC_DW_HI3798CV200 is not set CONFIG_MMC_DW_K3=m # CONFIG_MMC_SH_MMCIF is not set # CONFIG_MMC_VUB300 is not set CONFIG_MMC_USHC=m CONFIG_MMC_USDHI6ROL0=m CONFIG_MMC_CQHCI=m CONFIG_MMC_HSQ=m # CONFIG_MMC_BCM2835 is not set CONFIG_MMC_MTK=m # CONFIG_MMC_OWL is not set # CONFIG_MMC_LITEX is not set CONFIG_MEMSTICK=y # CONFIG_MEMSTICK_DEBUG is not set # # MemoryStick drivers # CONFIG_MEMSTICK_UNSAFE_RESUME=y # # MemoryStick Host Controller Drivers # CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=m CONFIG_LEDS_CLASS_FLASH=m CONFIG_LEDS_CLASS_MULTICOLOR=m CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y # # LED drivers # CONFIG_LEDS_AN30259A=m # CONFIG_LEDS_ARIEL is not set CONFIG_LEDS_AW2013=m CONFIG_LEDS_BCM6328=m CONFIG_LEDS_BCM6358=m # CONFIG_LEDS_CR0014114 is not set # CONFIG_LEDS_EL15203000 is not set # CONFIG_LEDS_TURRIS_OMNIA is not set # CONFIG_LEDS_LM3530 is not set # CONFIG_LEDS_LM3532 is not set CONFIG_LEDS_LM3533=m CONFIG_LEDS_LM3642=m # CONFIG_LEDS_LM3692X is not set # CONFIG_LEDS_MT6323 is not set # CONFIG_LEDS_S3C24XX is not set # CONFIG_LEDS_COBALT_QUBE is not set CONFIG_LEDS_GPIO=m CONFIG_LEDS_LP3944=m CONFIG_LEDS_LP3952=m # CONFIG_LEDS_LP50XX is not set CONFIG_LEDS_LP55XX_COMMON=m # CONFIG_LEDS_LP5521 is not set CONFIG_LEDS_LP5523=m CONFIG_LEDS_LP5562=m CONFIG_LEDS_LP8501=m CONFIG_LEDS_LP8860=m CONFIG_LEDS_PCA955X=m # CONFIG_LEDS_PCA955X_GPIO is not set # CONFIG_LEDS_PCA963X is not set CONFIG_LEDS_DAC124S085=m # CONFIG_LEDS_PWM is not set CONFIG_LEDS_REGULATOR=m CONFIG_LEDS_BD2802=m CONFIG_LEDS_LT3593=m CONFIG_LEDS_MC13783=m CONFIG_LEDS_NS2=m CONFIG_LEDS_NETXBIG=m CONFIG_LEDS_TCA6507=m CONFIG_LEDS_TLC591XX=m # CONFIG_LEDS_MAX77650 is not set CONFIG_LEDS_LM355x=m # CONFIG_LEDS_OT200 is not set CONFIG_LEDS_IS31FL319X=m CONFIG_LEDS_IS31FL32XX=m # # LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) # CONFIG_LEDS_BLINKM=m # CONFIG_LEDS_MLXREG is not set CONFIG_LEDS_USER=m # CONFIG_LEDS_SPI_BYTE is not set CONFIG_LEDS_TI_LMU_COMMON=m # CONFIG_LEDS_LM3697 is not set CONFIG_LEDS_LM36274=m # CONFIG_LEDS_IP30 is not set # CONFIG_LEDS_BCM63138 is not set # CONFIG_LEDS_LGM is not set # # Flash and Torch LED drivers # CONFIG_LEDS_AAT1290=m CONFIG_LEDS_AS3645A=m # CONFIG_LEDS_KTD2692 is not set CONFIG_LEDS_LM3601X=m CONFIG_LEDS_MAX77693=m CONFIG_LEDS_MT6360=m CONFIG_LEDS_RT4505=m CONFIG_LEDS_RT8515=m CONFIG_LEDS_SGM3140=m # # RGB LED drivers # # CONFIG_LEDS_PWM_MULTICOLOR is not set CONFIG_LEDS_QCOM_LPG=m # # LED Triggers # CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_ONESHOT=y # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set # CONFIG_LEDS_TRIGGER_CPU is not set CONFIG_LEDS_TRIGGER_ACTIVITY=m # CONFIG_LEDS_TRIGGER_GPIO is not set CONFIG_LEDS_TRIGGER_DEFAULT_ON=m # # iptables trigger is under Netfilter config (LED target) # CONFIG_LEDS_TRIGGER_TRANSIENT=y # CONFIG_LEDS_TRIGGER_CAMERA is not set # CONFIG_LEDS_TRIGGER_PANIC is not set # CONFIG_LEDS_TRIGGER_NETDEV is not set CONFIG_LEDS_TRIGGER_PATTERN=m # CONFIG_LEDS_TRIGGER_AUDIO is not set CONFIG_LEDS_TRIGGER_TTY=y # # Simple LED drivers # CONFIG_ACCESSIBILITY=y # # Speakup console speech # # end of Speakup console speech # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y CONFIG_EDAC=y CONFIG_EDAC_LEGACY_SYSFS=y # CONFIG_EDAC_DEBUG is not set # CONFIG_EDAC_AL_MC is not set CONFIG_EDAC_SYNOPSYS=y # CONFIG_EDAC_XGENE is not set CONFIG_RTC_LIB=y CONFIG_RTC_MC146818_LIB=y CONFIG_RTC_CLASS=y CONFIG_RTC_HCTOSYS=y CONFIG_RTC_HCTOSYS_DEVICE="rtc0" # CONFIG_RTC_SYSTOHC is not set # CONFIG_RTC_DEBUG is not set CONFIG_RTC_LIB_KUNIT_TEST=m # CONFIG_RTC_NVMEM is not set # # RTC interfaces # # CONFIG_RTC_INTF_SYSFS is not set # CONFIG_RTC_INTF_DEV is not set CONFIG_RTC_DRV_TEST=y # # I2C RTC drivers # CONFIG_RTC_DRV_88PM80X=m CONFIG_RTC_DRV_ABB5ZES3=m # CONFIG_RTC_DRV_ABEOZ9 is not set CONFIG_RTC_DRV_ABX80X=m # CONFIG_RTC_DRV_BRCMSTB is not set CONFIG_RTC_DRV_DS1307=m # CONFIG_RTC_DRV_DS1307_CENTURY is not set CONFIG_RTC_DRV_DS1374=m CONFIG_RTC_DRV_DS1374_WDT=y CONFIG_RTC_DRV_DS1672=m # CONFIG_RTC_DRV_HYM8563 is not set CONFIG_RTC_DRV_MAX6900=m # CONFIG_RTC_DRV_MAX8907 is not set # CONFIG_RTC_DRV_MAX77686 is not set # CONFIG_RTC_DRV_NCT3018Y is not set # CONFIG_RTC_DRV_RS5C372 is not set CONFIG_RTC_DRV_ISL1208=m # CONFIG_RTC_DRV_ISL12022 is not set # CONFIG_RTC_DRV_ISL12026 is not set CONFIG_RTC_DRV_X1205=m CONFIG_RTC_DRV_PCF8523=m CONFIG_RTC_DRV_PCF85063=m CONFIG_RTC_DRV_PCF85363=m # CONFIG_RTC_DRV_PCF8563 is not set CONFIG_RTC_DRV_PCF8583=m CONFIG_RTC_DRV_M41T80=m CONFIG_RTC_DRV_M41T80_WDT=y CONFIG_RTC_DRV_BQ32K=m CONFIG_RTC_DRV_RC5T619=m # CONFIG_RTC_DRV_S35390A is not set CONFIG_RTC_DRV_FM3130=m CONFIG_RTC_DRV_RX8010=m CONFIG_RTC_DRV_RX8581=m # CONFIG_RTC_DRV_RX8025 is not set # CONFIG_RTC_DRV_EM3027 is not set # CONFIG_RTC_DRV_RV3028 is not set # CONFIG_RTC_DRV_RV3032 is not set CONFIG_RTC_DRV_RV8803=m # CONFIG_RTC_DRV_S5M is not set CONFIG_RTC_DRV_SD3078=m # # SPI RTC drivers # CONFIG_RTC_DRV_M41T93=y # CONFIG_RTC_DRV_M41T94 is not set CONFIG_RTC_DRV_DS1302=y CONFIG_RTC_DRV_DS1305=y CONFIG_RTC_DRV_DS1343=y # CONFIG_RTC_DRV_DS1347 is not set CONFIG_RTC_DRV_DS1390=m # CONFIG_RTC_DRV_MAX6916 is not set CONFIG_RTC_DRV_R9701=m CONFIG_RTC_DRV_RX4581=m # CONFIG_RTC_DRV_RS5C348 is not set CONFIG_RTC_DRV_MAX6902=m # CONFIG_RTC_DRV_PCF2123 is not set # CONFIG_RTC_DRV_MCP795 is not set CONFIG_RTC_I2C_AND_SPI=m # # SPI and I2C RTC drivers # # CONFIG_RTC_DRV_DS3232 is not set # CONFIG_RTC_DRV_PCF2127 is not set CONFIG_RTC_DRV_RV3029C2=m CONFIG_RTC_DRV_RV3029_HWMON=y CONFIG_RTC_DRV_RX6110=m # # Platform RTC drivers # CONFIG_RTC_DRV_CMOS=m CONFIG_RTC_DRV_DS1286=y CONFIG_RTC_DRV_DS1511=y # CONFIG_RTC_DRV_DS1553 is not set CONFIG_RTC_DRV_DS1685_FAMILY=m # CONFIG_RTC_DRV_DS1685 is not set # CONFIG_RTC_DRV_DS1689 is not set # CONFIG_RTC_DRV_DS17285 is not set CONFIG_RTC_DRV_DS17485=y # CONFIG_RTC_DRV_DS17885 is not set # CONFIG_RTC_DRV_DS1742 is not set CONFIG_RTC_DRV_DS2404=m # CONFIG_RTC_DRV_DA9063 is not set CONFIG_RTC_DRV_STK17TA8=y CONFIG_RTC_DRV_M48T86=y CONFIG_RTC_DRV_M48T35=m CONFIG_RTC_DRV_M48T59=m CONFIG_RTC_DRV_MSM6242=y CONFIG_RTC_DRV_BQ4802=m # CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set # CONFIG_RTC_DRV_GAMECUBE is not set # CONFIG_RTC_DRV_SC27XX is not set CONFIG_RTC_DRV_SPEAR=y CONFIG_RTC_DRV_PCF50633=m # CONFIG_RTC_DRV_ZYNQMP is not set # CONFIG_RTC_DRV_NTXEC is not set # # on-CPU RTC drivers # # CONFIG_RTC_DRV_ASM9260 is not set # CONFIG_RTC_DRV_DAVINCI is not set # CONFIG_RTC_DRV_DIGICOLOR is not set # CONFIG_RTC_DRV_IMXDI is not set # CONFIG_RTC_DRV_FSL_FTM_ALARM is not set # CONFIG_RTC_DRV_MESON is not set # CONFIG_RTC_DRV_MESON_VRTC is not set # CONFIG_RTC_DRV_OMAP is not set # CONFIG_RTC_DRV_S3C is not set # CONFIG_RTC_DRV_EP93XX is not set # CONFIG_RTC_DRV_PL030 is not set CONFIG_RTC_DRV_PL031=m CONFIG_RTC_DRV_AT91RM9200=y # CONFIG_RTC_DRV_AT91SAM9 is not set # CONFIG_RTC_DRV_RZN1 is not set # CONFIG_RTC_DRV_GENERIC is not set # CONFIG_RTC_DRV_VT8500 is not set # CONFIG_RTC_DRV_SUN6I is not set # CONFIG_RTC_DRV_SUNXI is not set # CONFIG_RTC_DRV_MV is not set # CONFIG_RTC_DRV_ARMADA38X is not set # CONFIG_RTC_DRV_CADENCE is not set CONFIG_RTC_DRV_FTRTC010=m # CONFIG_RTC_DRV_STMP is not set CONFIG_RTC_DRV_PCAP=y CONFIG_RTC_DRV_MC13XXX=m # CONFIG_RTC_DRV_JZ4740 is not set # CONFIG_RTC_DRV_LPC24XX is not set # CONFIG_RTC_DRV_LPC32XX is not set # CONFIG_RTC_DRV_PM8XXX is not set # CONFIG_RTC_DRV_TEGRA is not set CONFIG_RTC_DRV_MXC=y CONFIG_RTC_DRV_MXC_V2=y CONFIG_RTC_DRV_SNVS=y # CONFIG_RTC_DRV_MOXART is not set # CONFIG_RTC_DRV_MT2712 is not set # CONFIG_RTC_DRV_MT6397 is not set # CONFIG_RTC_DRV_MT7622 is not set # CONFIG_RTC_DRV_XGENE is not set CONFIG_RTC_DRV_R7301=y # CONFIG_RTC_DRV_STM32 is not set # CONFIG_RTC_DRV_RTD119X is not set # CONFIG_RTC_DRV_ASPEED is not set # CONFIG_RTC_DRV_TI_K3 is not set # # HID Sensor RTC drivers # CONFIG_RTC_DRV_GOLDFISH=m # CONFIG_RTC_DRV_MSC313 is not set # CONFIG_DMADEVICES is not set # # DMABUF options # # CONFIG_SYNC_FILE is not set # CONFIG_DMABUF_HEAPS is not set # end of DMABUF options CONFIG_AUXDISPLAY=y CONFIG_CHARLCD=m CONFIG_LINEDISP=y CONFIG_HD44780_COMMON=m # CONFIG_HD44780 is not set CONFIG_KS0108=m CONFIG_KS0108_PORT=0x378 CONFIG_KS0108_DELAY=2 CONFIG_IMG_ASCII_LCD=y # CONFIG_LCD2S is not set CONFIG_PARPORT_PANEL=m CONFIG_PANEL_PARPORT=0 CONFIG_PANEL_PROFILE=5 CONFIG_PANEL_CHANGE_MESSAGE=y CONFIG_PANEL_BOOT_MESSAGE="" # CONFIG_CHARLCD_BL_OFF is not set CONFIG_CHARLCD_BL_ON=y # CONFIG_CHARLCD_BL_FLASH is not set CONFIG_PANEL=m CONFIG_VFIO=y CONFIG_VFIO_VIRQFD=m CONFIG_VFIO_NOIOMMU=y CONFIG_VFIO_PLATFORM=m # CONFIG_VFIO_AMBA is not set CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET=m CONFIG_VFIO_PLATFORM_AMDXGBE_RESET=m # CONFIG_VFIO_PLATFORM_BCMFLEXRM_RESET is not set CONFIG_VFIO_MDEV=y CONFIG_IRQ_BYPASS_MANAGER=y CONFIG_VIRT_DRIVERS=y CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO=m # CONFIG_VIRTIO_MENU is not set CONFIG_VDPA=y CONFIG_VDPA_SIM=y # CONFIG_VDPA_SIM_NET is not set CONFIG_VDPA_SIM_BLOCK=y CONFIG_VHOST_IOTLB=y CONFIG_VHOST_RING=y CONFIG_VHOST=y CONFIG_VHOST_MENU=y # CONFIG_VHOST_NET is not set CONFIG_VHOST_VDPA=y CONFIG_VHOST_CROSS_ENDIAN_LEGACY=y # # Microsoft Hyper-V guest support # # end of Microsoft Hyper-V guest support CONFIG_GREYBUS=m # CONFIG_GREYBUS_ES2 is not set CONFIG_COMEDI=m # CONFIG_COMEDI_DEBUG is not set CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048 CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480 CONFIG_COMEDI_MISC_DRIVERS=y CONFIG_COMEDI_BOND=m CONFIG_COMEDI_TEST=m # CONFIG_COMEDI_PARPORT is not set # CONFIG_COMEDI_SSV_DNP is not set # CONFIG_COMEDI_ISA_DRIVERS is not set CONFIG_COMEDI_PCMCIA_DRIVERS=m CONFIG_COMEDI_CB_DAS16_CS=m CONFIG_COMEDI_DAS08_CS=m # CONFIG_COMEDI_NI_DAQ_700_CS is not set CONFIG_COMEDI_NI_DAQ_DIO24_CS=m CONFIG_COMEDI_NI_LABPC_CS=m # CONFIG_COMEDI_NI_MIO_CS is not set CONFIG_COMEDI_QUATECH_DAQP_CS=m CONFIG_COMEDI_USB_DRIVERS=m CONFIG_COMEDI_DT9812=m # CONFIG_COMEDI_NI_USB6501 is not set # CONFIG_COMEDI_USBDUX is not set CONFIG_COMEDI_USBDUXFAST=m # CONFIG_COMEDI_USBDUXSIGMA is not set CONFIG_COMEDI_VMK80XX=m CONFIG_COMEDI_8254=m CONFIG_COMEDI_8255=m CONFIG_COMEDI_8255_SA=m CONFIG_COMEDI_KCOMEDILIB=m CONFIG_COMEDI_DAS08=m CONFIG_COMEDI_NI_LABPC=m # CONFIG_COMEDI_TESTS is not set CONFIG_STAGING=y # # IIO staging drivers # # # Accelerometers # # CONFIG_ADIS16203 is not set # CONFIG_ADIS16240 is not set # end of Accelerometers # # Analog to digital converters # # CONFIG_AD7816 is not set # end of Analog to digital converters # # Analog digital bi-direction converters # CONFIG_ADT7316=y CONFIG_ADT7316_SPI=m # CONFIG_ADT7316_I2C is not set # end of Analog digital bi-direction converters # # Direct Digital Synthesis # # CONFIG_AD9832 is not set CONFIG_AD9834=y # end of Direct Digital Synthesis # # Network Analyzer, Impedance Converters # CONFIG_AD5933=m # end of Network Analyzer, Impedance Converters # # Active energy metering IC # CONFIG_ADE7854=m CONFIG_ADE7854_I2C=m # CONFIG_ADE7854_SPI is not set # end of Active energy metering IC # # Resolver to digital converters # CONFIG_AD2S1210=y # end of Resolver to digital converters # end of IIO staging drivers CONFIG_STAGING_MEDIA=y CONFIG_STAGING_BOARD=y # CONFIG_LTE_GDM724X is not set CONFIG_FB_TFT=m CONFIG_FB_TFT_AGM1264K_FL=m CONFIG_FB_TFT_BD663474=m CONFIG_FB_TFT_HX8340BN=m # CONFIG_FB_TFT_HX8347D is not set CONFIG_FB_TFT_HX8353D=m # CONFIG_FB_TFT_HX8357D is not set CONFIG_FB_TFT_ILI9163=m CONFIG_FB_TFT_ILI9320=m # CONFIG_FB_TFT_ILI9325 is not set CONFIG_FB_TFT_ILI9340=m CONFIG_FB_TFT_ILI9341=m # CONFIG_FB_TFT_ILI9481 is not set CONFIG_FB_TFT_ILI9486=m CONFIG_FB_TFT_PCD8544=m CONFIG_FB_TFT_RA8875=m # CONFIG_FB_TFT_S6D02A1 is not set # CONFIG_FB_TFT_S6D1121 is not set # CONFIG_FB_TFT_SEPS525 is not set # CONFIG_FB_TFT_SH1106 is not set CONFIG_FB_TFT_SSD1289=m # CONFIG_FB_TFT_SSD1305 is not set CONFIG_FB_TFT_SSD1306=m CONFIG_FB_TFT_SSD1331=m # CONFIG_FB_TFT_SSD1351 is not set CONFIG_FB_TFT_ST7735R=m CONFIG_FB_TFT_ST7789V=m CONFIG_FB_TFT_TINYLCD=m # CONFIG_FB_TFT_TLS8204 is not set # CONFIG_FB_TFT_UC1611 is not set # CONFIG_FB_TFT_UC1701 is not set # CONFIG_FB_TFT_UPD161704 is not set CONFIG_MOST_COMPONENTS=m # CONFIG_MOST_NET is not set # CONFIG_MOST_DIM2 is not set CONFIG_MOST_I2C=m CONFIG_GREYBUS_BOOTROM=m CONFIG_GREYBUS_FIRMWARE=m # CONFIG_GREYBUS_LIGHT is not set # CONFIG_GREYBUS_LOG is not set # CONFIG_GREYBUS_LOOPBACK is not set CONFIG_GREYBUS_POWER=m # CONFIG_GREYBUS_RAW is not set CONFIG_GREYBUS_VIBRATOR=m CONFIG_GREYBUS_BRIDGED_PHY=m CONFIG_GREYBUS_GPIO=m CONFIG_GREYBUS_I2C=m # CONFIG_GREYBUS_PWM is not set CONFIG_GREYBUS_SDIO=m CONFIG_GREYBUS_SPI=m CONFIG_GREYBUS_UART=m # CONFIG_GREYBUS_USB is not set # CONFIG_GREYBUS_ARCHE is not set CONFIG_BCM_VIDEOCORE=y # CONFIG_BCM2835_VCHIQ is not set # CONFIG_PI433 is not set CONFIG_XIL_AXIS_FIFO=m CONFIG_FIELDBUS_DEV=m # CONFIG_HMS_ANYBUSS_BUS is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set CONFIG_MELLANOX_PLATFORM=y CONFIG_MLXREG_HOTPLUG=m # CONFIG_MLXREG_IO is not set # CONFIG_MLXREG_LC is not set # CONFIG_NVSW_SN2201 is not set # CONFIG_OLPC_XO175 is not set CONFIG_SURFACE_PLATFORMS=y CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y # # Clock driver for ARM Reference designs # # CONFIG_CLK_ICST is not set # CONFIG_CLK_SP810 is not set CONFIG_CLK_VEXPRESS_OSC=y # end of Clock driver for ARM Reference designs # CONFIG_CLK_HSDK is not set CONFIG_LMK04832=m # CONFIG_COMMON_CLK_APPLE_NCO is not set CONFIG_COMMON_CLK_MAX77686=m CONFIG_COMMON_CLK_MAX9485=m # CONFIG_COMMON_CLK_HI655X is not set # CONFIG_COMMON_CLK_SCMI is not set # CONFIG_COMMON_CLK_SCPI is not set CONFIG_COMMON_CLK_SI5341=m # CONFIG_COMMON_CLK_SI5351 is not set CONFIG_COMMON_CLK_SI514=m CONFIG_COMMON_CLK_SI544=m CONFIG_COMMON_CLK_SI570=m # CONFIG_COMMON_CLK_BM1880 is not set CONFIG_COMMON_CLK_CDCE706=m # CONFIG_COMMON_CLK_TPS68470 is not set # CONFIG_COMMON_CLK_CDCE925 is not set CONFIG_COMMON_CLK_CS2000_CP=m # CONFIG_COMMON_CLK_EN7523 is not set # CONFIG_COMMON_CLK_FSL_FLEXSPI is not set # CONFIG_COMMON_CLK_FSL_SAI is not set # CONFIG_COMMON_CLK_GEMINI is not set # CONFIG_COMMON_CLK_LAN966X is not set # CONFIG_COMMON_CLK_ASPEED is not set # CONFIG_COMMON_CLK_S2MPS11 is not set # CONFIG_COMMON_CLK_AXI_CLKGEN is not set # CONFIG_CLK_QORIQ is not set # CONFIG_CLK_LS1028A_PLLDIG is not set # CONFIG_COMMON_CLK_XGENE is not set # CONFIG_COMMON_CLK_PWM is not set # CONFIG_COMMON_CLK_OXNAS is not set CONFIG_COMMON_CLK_RS9_PCIE=m # CONFIG_COMMON_CLK_VC5 is not set # CONFIG_COMMON_CLK_VC7 is not set # CONFIG_COMMON_CLK_MMP2_AUDIO is not set CONFIG_COMMON_CLK_FIXED_MMIO=y # CONFIG_CLK_ACTIONS is not set # CONFIG_CLK_BAIKAL_T1 is not set # CONFIG_CLK_BCM2711_DVP is not set # CONFIG_CLK_BCM2835 is not set # CONFIG_CLK_BCM_63XX is not set # CONFIG_CLK_BCM_63XX_GATE is not set # CONFIG_CLK_BCM_KONA is not set # CONFIG_CLK_BCM_CYGNUS is not set # CONFIG_CLK_BCM_HR2 is not set # CONFIG_CLK_BCM_NSP is not set # CONFIG_CLK_BCM_NS2 is not set # CONFIG_CLK_BCM_SR is not set # CONFIG_CLK_RASPBERRYPI is not set # CONFIG_COMMON_CLK_HI3516CV300 is not set # CONFIG_COMMON_CLK_HI3519 is not set # CONFIG_COMMON_CLK_HI3559A is not set # CONFIG_COMMON_CLK_HI3660 is not set # CONFIG_COMMON_CLK_HI3670 is not set # CONFIG_COMMON_CLK_HI3798CV200 is not set # CONFIG_COMMON_CLK_HI6220 is not set # CONFIG_RESET_HISI is not set # CONFIG_STUB_CLK_HI6220 is not set # CONFIG_STUB_CLK_HI3660 is not set # CONFIG_COMMON_CLK_BOSTON is not set CONFIG_MXC_CLK=y CONFIG_CLK_IMX7D=y CONFIG_CLK_IMX7ULP=y # CONFIG_CLK_IMX8MM is not set CONFIG_CLK_IMX8MN=y CONFIG_CLK_IMX8MP=y CONFIG_CLK_IMX8MQ=y CONFIG_CLK_IMX8ULP=y CONFIG_CLK_IMX93=m CONFIG_CLK_IMXRT1050=y # # Ingenic SoCs drivers # # CONFIG_INGENIC_CGU_JZ4740 is not set # CONFIG_INGENIC_CGU_JZ4725B is not set # CONFIG_INGENIC_CGU_JZ4760 is not set # CONFIG_INGENIC_CGU_JZ4770 is not set # CONFIG_INGENIC_CGU_JZ4780 is not set # CONFIG_INGENIC_CGU_X1000 is not set # CONFIG_INGENIC_CGU_X1830 is not set # CONFIG_INGENIC_TCU_CLK is not set # end of Ingenic SoCs drivers # CONFIG_COMMON_CLK_KEYSTONE is not set # CONFIG_TI_SYSCON_CLK is not set # # Clock driver for MediaTek SoC # # CONFIG_COMMON_CLK_MT2701 is not set # CONFIG_COMMON_CLK_MT2712 is not set # CONFIG_COMMON_CLK_MT6765 is not set # CONFIG_COMMON_CLK_MT6779 is not set # CONFIG_COMMON_CLK_MT6795 is not set # CONFIG_COMMON_CLK_MT6797 is not set # CONFIG_COMMON_CLK_MT7622 is not set # CONFIG_COMMON_CLK_MT7629 is not set # CONFIG_COMMON_CLK_MT7986 is not set # CONFIG_COMMON_CLK_MT8135 is not set # CONFIG_COMMON_CLK_MT8167 is not set # CONFIG_COMMON_CLK_MT8173 is not set # CONFIG_COMMON_CLK_MT8183 is not set # CONFIG_COMMON_CLK_MT8186 is not set # CONFIG_COMMON_CLK_MT8192 is not set # CONFIG_COMMON_CLK_MT8195 is not set # CONFIG_COMMON_CLK_MT8365 is not set # CONFIG_COMMON_CLK_MT8516 is not set # end of Clock driver for MediaTek SoC # # Clock support for Amlogic platforms # CONFIG_COMMON_CLK_MESON_REGMAP=y CONFIG_COMMON_CLK_MESON_MPLL=y CONFIG_COMMON_CLK_MESON_PLL=y CONFIG_COMMON_CLK_MESON8B=y # end of Clock support for Amlogic platforms # CONFIG_MSTAR_MSC313_MPLL is not set # CONFIG_MCHP_CLK_MPFS is not set # CONFIG_COMMON_CLK_PISTACHIO is not set # CONFIG_COMMON_CLK_QCOM is not set # CONFIG_CLK_MT7621 is not set # CONFIG_CLK_RENESAS is not set # CONFIG_COMMON_CLK_SAMSUNG is not set # CONFIG_S3C2410_COMMON_CLK is not set # CONFIG_S3C2412_COMMON_CLK is not set # CONFIG_S3C2443_COMMON_CLK is not set # CONFIG_CLK_SIFIVE is not set # CONFIG_CLK_INTEL_SOCFPGA is not set # CONFIG_SPRD_COMMON_CLK is not set # CONFIG_CLK_STARFIVE_JH7100 is not set CONFIG_CLK_SUNXI=y CONFIG_CLK_SUNXI_CLOCKS=y CONFIG_CLK_SUNXI_PRCM_SUN6I=y CONFIG_CLK_SUNXI_PRCM_SUN8I=y CONFIG_CLK_SUNXI_PRCM_SUN9I=y # CONFIG_SUNXI_CCU is not set # CONFIG_COMMON_CLK_TI_ADPLL is not set # CONFIG_CLK_UNIPHIER is not set # CONFIG_COMMON_CLK_VISCONTI is not set # CONFIG_CLK_LGM_CGU is not set CONFIG_XILINX_VCU=y CONFIG_COMMON_CLK_XLNX_CLKWZRD=y # CONFIG_COMMON_CLK_ZYNQMP is not set CONFIG_CLK_KUNIT_TEST=m CONFIG_CLK_GATE_KUNIT_TEST=m # CONFIG_HWSPINLOCK is not set # # Clock Source drivers # CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y CONFIG_CLKSRC_MMIO=y # CONFIG_BCM2835_TIMER is not set # CONFIG_BCM_KONA_TIMER is not set # CONFIG_DAVINCI_TIMER is not set # CONFIG_DIGICOLOR_TIMER is not set # CONFIG_OMAP_DM_TIMER is not set # CONFIG_DW_APB_TIMER is not set # CONFIG_FTTMR010_TIMER is not set # CONFIG_IXP4XX_TIMER is not set # CONFIG_ROCKCHIP_TIMER is not set # CONFIG_ARMADA_370_XP_TIMER is not set # CONFIG_MESON6_TIMER is not set # CONFIG_ORION_TIMER is not set # CONFIG_OWL_TIMER is not set # CONFIG_RDA_TIMER is not set # CONFIG_SUN4I_TIMER is not set # CONFIG_SUN5I_HSTIMER is not set # CONFIG_TEGRA_TIMER is not set # CONFIG_TEGRA186_TIMER is not set # CONFIG_VT8500_TIMER is not set # CONFIG_NPCM7XX_TIMER is not set # CONFIG_CADENCE_TTC_TIMER is not set # CONFIG_ASM9260_TIMER is not set # CONFIG_CLKSRC_NOMADIK_MTU is not set # CONFIG_CLKSRC_DBX500_PRCMU is not set # CONFIG_CLPS711X_TIMER is not set # CONFIG_MXS_TIMER is not set # CONFIG_NSPIRE_TIMER is not set # CONFIG_KEYSTONE_TIMER is not set # CONFIG_INTEGRATOR_AP_TIMER is not set # CONFIG_CLKSRC_LPC32XX is not set # CONFIG_CLKSRC_PISTACHIO is not set # CONFIG_CLKSRC_TI_32K is not set # CONFIG_CLKSRC_STM32 is not set # CONFIG_CLKSRC_STM32_LP is not set # CONFIG_CLKSRC_MPS2 is not set # CONFIG_ARC_TIMERS is not set # CONFIG_ARM_GLOBAL_TIMER is not set # CONFIG_ARM_TIMER_SP804 is not set CONFIG_ARMV7M_SYSTICK=y # CONFIG_ATMEL_PIT is not set # CONFIG_ATMEL_ST is not set # CONFIG_ATMEL_TCB_CLKSRC is not set # CONFIG_CLKSRC_EXYNOS_MCT is not set # CONFIG_CLKSRC_SAMSUNG_PWM is not set # CONFIG_FSL_FTM_TIMER is not set # CONFIG_OXNAS_RPS_TIMER is not set # CONFIG_MTK_TIMER is not set # CONFIG_SPRD_TIMER is not set # CONFIG_CLKSRC_JCORE_PIT is not set # CONFIG_SH_TIMER_CMT is not set # CONFIG_SH_TIMER_MTU2 is not set # CONFIG_RENESAS_OSTM is not set # CONFIG_SH_TIMER_TMU is not set # CONFIG_EM_TIMER_STI is not set # CONFIG_CLKSRC_QCOM is not set # CONFIG_CLKSRC_VERSATILE is not set # CONFIG_CLKSRC_PXA is not set CONFIG_CLKSRC_IMX_GPT=y CONFIG_CLKSRC_IMX_TPM=y # CONFIG_TIMER_IMX_SYS_CTR is not set # CONFIG_CLKSRC_ST_LPC is not set # CONFIG_GXP_TIMER is not set # CONFIG_MILBEAUT_TIMER is not set # CONFIG_MSC313E_TIMER is not set # CONFIG_INGENIC_TIMER is not set # CONFIG_INGENIC_SYSOST is not set # CONFIG_INGENIC_OST is not set CONFIG_MICROCHIP_PIT64B=y # CONFIG_GOLDFISH_TIMER is not set # end of Clock Source drivers CONFIG_MAILBOX=y # CONFIG_ARM_MHU is not set CONFIG_ARM_MHU_V2=y CONFIG_IMX_MBOX=m CONFIG_PLATFORM_MHU=y CONFIG_PL320_MBOX=y # CONFIG_ARMADA_37XX_RWTM_MBOX is not set # CONFIG_ROCKCHIP_MBOX is not set CONFIG_ALTERA_MBOX=m # CONFIG_HI3660_MBOX is not set # CONFIG_HI6220_MBOX is not set # CONFIG_MAILBOX_TEST is not set # CONFIG_POLARFIRE_SOC_MAILBOX is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_BCM_PDC_MBOX is not set # CONFIG_STM32_IPCC is not set # CONFIG_MTK_ADSP_MBOX is not set # CONFIG_MTK_CMDQ_MBOX is not set # CONFIG_SUN6I_MSGBOX is not set # CONFIG_SPRD_MBOX is not set # CONFIG_QCOM_IPCC is not set CONFIG_IOMMU_IOVA=y CONFIG_IOMMU_API=y # # Remoteproc drivers # # CONFIG_REMOTEPROC is not set # end of Remoteproc drivers # # Rpmsg drivers # CONFIG_RPMSG=m CONFIG_RPMSG_CHAR=m CONFIG_RPMSG_CTRL=m CONFIG_RPMSG_NS=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set CONFIG_RPMSG_VIRTIO=m # end of Rpmsg drivers CONFIG_SOUNDWIRE=m # # SoundWire Devices # # # SOC (System On Chip) specific Drivers # # CONFIG_OWL_PM_DOMAINS is not set # # Amlogic SoC drivers # # CONFIG_MESON_CANVAS is not set # CONFIG_MESON_CLK_MEASURE is not set # CONFIG_MESON_GX_SOCINFO is not set # CONFIG_MESON_GX_PM_DOMAINS is not set # CONFIG_MESON_EE_PM_DOMAINS is not set # CONFIG_MESON_MX_SOCINFO is not set # end of Amlogic SoC drivers # # Apple SoC drivers # # CONFIG_APPLE_PMGR_PWRSTATE is not set # CONFIG_APPLE_RTKIT is not set # CONFIG_APPLE_SART is not set # end of Apple SoC drivers # # ASPEED SoC drivers # # CONFIG_ASPEED_LPC_CTRL is not set # CONFIG_ASPEED_LPC_SNOOP is not set # CONFIG_ASPEED_UART_ROUTING is not set # CONFIG_ASPEED_P2A_CTRL is not set # CONFIG_ASPEED_SOCINFO is not set # end of ASPEED SoC drivers # CONFIG_AT91_SOC_ID is not set CONFIG_AT91_SOC_SFR=y # # Broadcom SoC drivers # # CONFIG_BCM2835_POWER is not set # CONFIG_SOC_BCM63XX is not set # CONFIG_SOC_BRCMSTB is not set # CONFIG_BCM_PMB is not set # end of Broadcom SoC drivers # # NXP/Freescale QorIQ SoC drivers # # CONFIG_QUICC_ENGINE is not set CONFIG_DPAA2_CONSOLE=y # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers # # fujitsu SoC drivers # # end of fujitsu SoC drivers # # i.MX SoC drivers # CONFIG_IMX_GPCV2_PM_DOMAINS=y CONFIG_SOC_IMX8M=y # CONFIG_SOC_IMX9 is not set # end of i.MX SoC drivers # # IXP4xx SoC drivers # # CONFIG_IXP4XX_QMGR is not set # CONFIG_IXP4XX_NPE is not set # end of IXP4xx SoC drivers # # Enable LiteX SoC Builder specific drivers # CONFIG_LITEX=y CONFIG_LITEX_SOC_CONTROLLER=y # end of Enable LiteX SoC Builder specific drivers # # MediaTek SoC drivers # # CONFIG_MTK_CMDQ is not set # CONFIG_MTK_DEVAPC is not set # CONFIG_MTK_INFRACFG is not set # CONFIG_MTK_PMIC_WRAP is not set # CONFIG_MTK_SCPSYS is not set # CONFIG_MTK_SCPSYS_PM_DOMAINS is not set # CONFIG_MTK_MMSYS is not set # end of MediaTek SoC drivers # # Qualcomm SoC drivers # # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_GENI_SE is not set # CONFIG_QCOM_GSBI is not set # CONFIG_QCOM_LLCC is not set # CONFIG_QCOM_RPMH is not set # CONFIG_QCOM_SMD_RPM is not set # CONFIG_QCOM_SPM is not set # CONFIG_QCOM_WCNSS_CTRL is not set # CONFIG_QCOM_APR is not set # CONFIG_QCOM_ICC_BWMON is not set # end of Qualcomm SoC drivers # CONFIG_SOC_RENESAS is not set # CONFIG_ROCKCHIP_GRF is not set # CONFIG_ROCKCHIP_IODOMAIN is not set # CONFIG_ROCKCHIP_PM_DOMAINS is not set # CONFIG_SOC_SAMSUNG is not set # CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER is not set # CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER is not set # CONFIG_SOC_TI is not set # CONFIG_UX500_SOC_ID is not set # # Xilinx SoC drivers # # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers CONFIG_PM_DEVFREQ=y # # DEVFREQ Governors # CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_DEVFREQ_GOV_PERFORMANCE=m CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_USERSPACE=m CONFIG_DEVFREQ_GOV_PASSIVE=y # # DEVFREQ Drivers # # CONFIG_ARM_EXYNOS_BUS_DEVFREQ is not set CONFIG_ARM_IMX_BUS_DEVFREQ=m # CONFIG_ARM_TEGRA_DEVFREQ is not set # CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set # CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ is not set CONFIG_PM_DEVFREQ_EVENT=y # CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP is not set # CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU is not set # CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI is not set CONFIG_EXTCON=y # # Extcon Device Drivers # CONFIG_EXTCON_ADC_JACK=m # CONFIG_EXTCON_GPIO is not set # CONFIG_EXTCON_MAX14577 is not set # CONFIG_EXTCON_MAX3355 is not set CONFIG_EXTCON_PTN5150=m # CONFIG_EXTCON_QCOM_SPMI_MISC is not set CONFIG_EXTCON_RT8973A=m # CONFIG_EXTCON_SM5502 is not set # CONFIG_EXTCON_USB_GPIO is not set CONFIG_EXTCON_USBC_TUSB320=m CONFIG_MEMORY=y CONFIG_DDR=y CONFIG_ARM_PL172_MPMC=m CONFIG_ATMEL_SDRAMC=y CONFIG_ATMEL_EBI=y # CONFIG_BRCMSTB_DPFE is not set # CONFIG_BRCMSTB_MEMC is not set # CONFIG_BT1_L2_CTL is not set # CONFIG_TI_AEMIF is not set # CONFIG_TI_EMIF is not set # CONFIG_OMAP_GPMC is not set # CONFIG_MVEBU_DEVBUS is not set # CONFIG_FSL_CORENET_CF is not set # CONFIG_FSL_IFC is not set # CONFIG_JZ4780_NEMC is not set # CONFIG_MTK_SMI is not set # CONFIG_DA8XX_DDRCTL is not set # CONFIG_PL353_SMC is not set # CONFIG_RENESAS_RPCIF is not set # CONFIG_STM32_FMC2_EBI is not set # CONFIG_SAMSUNG_MC is not set CONFIG_TEGRA_MC=y CONFIG_TEGRA20_EMC=y CONFIG_TEGRA30_EMC=y CONFIG_TEGRA124_EMC=y # CONFIG_TEGRA210_EMC is not set CONFIG_IIO=y CONFIG_IIO_BUFFER=y CONFIG_IIO_BUFFER_CB=y CONFIG_IIO_BUFFER_DMA=y CONFIG_IIO_BUFFER_DMAENGINE=y CONFIG_IIO_BUFFER_HW_CONSUMER=m CONFIG_IIO_KFIFO_BUF=y CONFIG_IIO_TRIGGERED_BUFFER=y CONFIG_IIO_CONFIGFS=y CONFIG_IIO_TRIGGER=y CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_IIO_SW_DEVICE is not set CONFIG_IIO_SW_TRIGGER=y CONFIG_IIO_TRIGGERED_EVENT=y # # Accelerometers # CONFIG_ADIS16201=m CONFIG_ADIS16209=m CONFIG_ADXL313=m CONFIG_ADXL313_I2C=m # CONFIG_ADXL313_SPI is not set CONFIG_ADXL345=m CONFIG_ADXL345_I2C=m CONFIG_ADXL345_SPI=m CONFIG_ADXL355=y # CONFIG_ADXL355_I2C is not set CONFIG_ADXL355_SPI=y CONFIG_ADXL367=m CONFIG_ADXL367_SPI=m CONFIG_ADXL367_I2C=m CONFIG_ADXL372=y CONFIG_ADXL372_SPI=y CONFIG_ADXL372_I2C=m CONFIG_BMA180=m # CONFIG_BMA220 is not set CONFIG_BMA400=y CONFIG_BMA400_I2C=m CONFIG_BMA400_SPI=y CONFIG_BMC150_ACCEL=m CONFIG_BMC150_ACCEL_I2C=m CONFIG_BMC150_ACCEL_SPI=m CONFIG_BMI088_ACCEL=m CONFIG_BMI088_ACCEL_SPI=m # CONFIG_DA280 is not set CONFIG_DA311=m CONFIG_DMARD06=m CONFIG_DMARD09=m CONFIG_DMARD10=m # CONFIG_FXLS8962AF_I2C is not set # CONFIG_FXLS8962AF_SPI is not set CONFIG_IIO_ST_ACCEL_3AXIS=y CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m # CONFIG_IIO_ST_ACCEL_SPI_3AXIS is not set CONFIG_KXSD9=m CONFIG_KXSD9_SPI=m CONFIG_KXSD9_I2C=m CONFIG_KXCJK1013=m CONFIG_MC3230=m CONFIG_MMA7455=m CONFIG_MMA7455_I2C=m CONFIG_MMA7455_SPI=m CONFIG_MMA7660=m CONFIG_MMA8452=m CONFIG_MMA9551_CORE=m CONFIG_MMA9551=m # CONFIG_MMA9553 is not set CONFIG_MSA311=m CONFIG_MXC4005=m # CONFIG_MXC6255 is not set # CONFIG_SCA3000 is not set # CONFIG_SCA3300 is not set # CONFIG_STK8312 is not set CONFIG_STK8BA50=m # end of Accelerometers # # Analog to digital converters # CONFIG_AD_SIGMA_DELTA=y CONFIG_AD7091R5=m CONFIG_AD7124=y # CONFIG_AD7192 is not set CONFIG_AD7266=y CONFIG_AD7280=y CONFIG_AD7291=m # CONFIG_AD7292 is not set # CONFIG_AD7298 is not set # CONFIG_AD7476 is not set CONFIG_AD7606=y CONFIG_AD7606_IFACE_PARALLEL=y CONFIG_AD7606_IFACE_SPI=y CONFIG_AD7766=m CONFIG_AD7768_1=m # CONFIG_AD7780 is not set CONFIG_AD7791=m CONFIG_AD7793=y CONFIG_AD7887=y CONFIG_AD7923=y CONFIG_AD7949=m # CONFIG_AD799X is not set # CONFIG_ADI_AXI_ADC is not set # CONFIG_ASPEED_ADC is not set CONFIG_AT91_SAMA5D2_ADC=y CONFIG_AXP20X_ADC=m CONFIG_AXP288_ADC=m # CONFIG_BCM_IPROC_ADC is not set # CONFIG_BERLIN2_ADC is not set CONFIG_CC10001_ADC=m CONFIG_DA9150_GPADC=m CONFIG_DLN2_ADC=m CONFIG_ENVELOPE_DETECTOR=y # CONFIG_EXYNOS_ADC is not set CONFIG_HI8435=m CONFIG_HX711=y CONFIG_INA2XX_ADC=m # CONFIG_INGENIC_ADC is not set CONFIG_IMX7D_ADC=y # CONFIG_IMX8QXP_ADC is not set # CONFIG_LPC18XX_ADC is not set # CONFIG_LPC32XX_ADC is not set # CONFIG_LTC2471 is not set # CONFIG_LTC2485 is not set # CONFIG_LTC2496 is not set CONFIG_LTC2497=m CONFIG_MAX1027=y # CONFIG_MAX11100 is not set # CONFIG_MAX1118 is not set # CONFIG_MAX11205 is not set # CONFIG_MAX1241 is not set CONFIG_MAX1363=m CONFIG_MAX9611=m CONFIG_MCP320X=m # CONFIG_MCP3422 is not set CONFIG_MCP3911=y # CONFIG_MEDIATEK_MT6360_ADC is not set # CONFIG_MEDIATEK_MT6577_AUXADC is not set CONFIG_MEN_Z188_ADC=m # CONFIG_MESON_SARADC is not set CONFIG_MP2629_ADC=m CONFIG_NAU7802=m # CONFIG_NPCM_ADC is not set CONFIG_QCOM_VADC_COMMON=m CONFIG_QCOM_SPMI_IADC=m CONFIG_QCOM_SPMI_VADC=m CONFIG_QCOM_SPMI_ADC5=m # CONFIG_RCAR_GYRO_ADC is not set CONFIG_RN5T618_ADC=m # CONFIG_ROCKCHIP_SARADC is not set # CONFIG_RICHTEK_RTQ6056 is not set # CONFIG_RZG2L_ADC is not set # CONFIG_SC27XX_ADC is not set # CONFIG_SPEAR_ADC is not set CONFIG_SD_ADC_MODULATOR=m # CONFIG_STM32_ADC_CORE is not set # CONFIG_STM32_DFSDM_CORE is not set # CONFIG_STM32_DFSDM_ADC is not set CONFIG_TI_ADC081C=m CONFIG_TI_ADC0832=y CONFIG_TI_ADC084S021=m # CONFIG_TI_ADC12138 is not set # CONFIG_TI_ADC108S102 is not set # CONFIG_TI_ADC128S052 is not set CONFIG_TI_ADC161S626=m # CONFIG_TI_ADS1015 is not set CONFIG_TI_ADS7950=y # CONFIG_TI_ADS8344 is not set CONFIG_TI_ADS8688=m # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS131E08 is not set CONFIG_TI_TLC4541=m CONFIG_TI_TSC2046=y # CONFIG_VF610_ADC is not set CONFIG_VIPERBOARD_ADC=y CONFIG_XILINX_XADC=m # CONFIG_XILINX_AMS is not set # end of Analog to digital converters # # Analog to digital and digital to analog converters # CONFIG_AD74413R=y # end of Analog to digital and digital to analog converters # # Analog Front Ends # # CONFIG_IIO_RESCALE is not set # end of Analog Front Ends # # Amplifiers # CONFIG_AD8366=m CONFIG_ADA4250=m # CONFIG_HMC425 is not set # end of Amplifiers # # Capacitance to digital converters # CONFIG_AD7150=m CONFIG_AD7746=m # end of Capacitance to digital converters # # Chemical Sensors # CONFIG_ATLAS_PH_SENSOR=m # CONFIG_ATLAS_EZO_SENSOR is not set CONFIG_BME680=m CONFIG_BME680_I2C=m CONFIG_BME680_SPI=m CONFIG_CCS811=m CONFIG_IAQCORE=m CONFIG_PMS7003=y # CONFIG_SCD30_CORE is not set CONFIG_SCD4X=m CONFIG_SENSIRION_SGP30=m CONFIG_SENSIRION_SGP40=m # CONFIG_SPS30_I2C is not set # CONFIG_SPS30_SERIAL is not set CONFIG_SENSEAIR_SUNRISE_CO2=m # CONFIG_VZ89X is not set # end of Chemical Sensors # # Hid Sensor IIO Common # # end of Hid Sensor IIO Common CONFIG_IIO_MS_SENSORS_I2C=m # # IIO SCMI Sensors # # end of IIO SCMI Sensors # # SSP Sensor Common # # CONFIG_IIO_SSP_SENSORS_COMMONS is not set CONFIG_IIO_SSP_SENSORHUB=m # end of SSP Sensor Common CONFIG_IIO_ST_SENSORS_I2C=m CONFIG_IIO_ST_SENSORS_CORE=y # # Digital to analog converters # CONFIG_AD3552R=m # CONFIG_AD5064 is not set CONFIG_AD5360=m CONFIG_AD5380=m CONFIG_AD5421=m # CONFIG_AD5446 is not set CONFIG_AD5449=y # CONFIG_AD5592R is not set # CONFIG_AD5593R is not set CONFIG_AD5504=y CONFIG_AD5624R_SPI=y # CONFIG_LTC2688 is not set CONFIG_AD5686=m CONFIG_AD5686_SPI=m CONFIG_AD5696_I2C=m # CONFIG_AD5755 is not set # CONFIG_AD5758 is not set CONFIG_AD5761=m CONFIG_AD5764=m CONFIG_AD5766=y CONFIG_AD5770R=y CONFIG_AD5791=y CONFIG_AD7293=m # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set CONFIG_DPOT_DAC=y CONFIG_DS4424=m # CONFIG_LPC18XX_DAC is not set CONFIG_LTC1660=m CONFIG_LTC2632=y # CONFIG_M62332 is not set CONFIG_MAX517=m CONFIG_MAX5821=m CONFIG_MCP4725=m CONFIG_MCP4922=m # CONFIG_STM32_DAC is not set CONFIG_TI_DAC082S085=y CONFIG_TI_DAC5571=m CONFIG_TI_DAC7311=m CONFIG_TI_DAC7612=y CONFIG_VF610_DAC=m # end of Digital to analog converters # # IIO dummy driver # # end of IIO dummy driver # # Filters # # end of Filters # # Frequency Synthesizers DDS/PLL # # # Clock Generator/Distribution # # CONFIG_AD9523 is not set # end of Clock Generator/Distribution # # Phase-Locked Loop (PLL) frequency synthesizers # CONFIG_ADF4350=y CONFIG_ADF4371=m CONFIG_ADMV1013=m CONFIG_ADMV4420=m CONFIG_ADRF6780=m # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL # # Digital gyroscope sensors # CONFIG_ADIS16080=m CONFIG_ADIS16130=y CONFIG_ADIS16136=y CONFIG_ADIS16260=m # CONFIG_ADXRS290 is not set # CONFIG_ADXRS450 is not set CONFIG_BMG160=m CONFIG_BMG160_I2C=m CONFIG_BMG160_SPI=m CONFIG_FXAS21002C=y CONFIG_FXAS21002C_I2C=m CONFIG_FXAS21002C_SPI=y # CONFIG_MPU3050_I2C is not set # CONFIG_IIO_ST_GYRO_3AXIS is not set CONFIG_ITG3200=m # end of Digital gyroscope sensors # # Health Sensors # # # Heart Rate Monitors # # CONFIG_AFE4403 is not set CONFIG_AFE4404=m CONFIG_MAX30100=m CONFIG_MAX30102=m # end of Heart Rate Monitors # end of Health Sensors # # Humidity sensors # CONFIG_AM2315=m # CONFIG_DHT11 is not set CONFIG_HDC100X=m CONFIG_HDC2010=m CONFIG_HTS221=m CONFIG_HTS221_I2C=m CONFIG_HTS221_SPI=m CONFIG_HTU21=m # CONFIG_SI7005 is not set CONFIG_SI7020=m # end of Humidity sensors # # Inertial measurement units # CONFIG_ADIS16400=m # CONFIG_ADIS16460 is not set CONFIG_ADIS16475=y CONFIG_ADIS16480=y # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set CONFIG_BOSCH_BNO055=m # CONFIG_BOSCH_BNO055_SERIAL is not set CONFIG_BOSCH_BNO055_I2C=m CONFIG_FXOS8700=y # CONFIG_FXOS8700_I2C is not set CONFIG_FXOS8700_SPI=y CONFIG_KMX61=m CONFIG_INV_ICM42600=m CONFIG_INV_ICM42600_I2C=m CONFIG_INV_ICM42600_SPI=m CONFIG_INV_MPU6050_IIO=y # CONFIG_INV_MPU6050_I2C is not set CONFIG_INV_MPU6050_SPI=y # CONFIG_IIO_ST_LSM6DSX is not set CONFIG_IIO_ST_LSM9DS0=y CONFIG_IIO_ST_LSM9DS0_I2C=m # CONFIG_IIO_ST_LSM9DS0_SPI is not set # end of Inertial measurement units CONFIG_IIO_ADIS_LIB=y CONFIG_IIO_ADIS_LIB_BUFFER=y # # Light sensors # # CONFIG_ADJD_S311 is not set # CONFIG_ADUX1020 is not set CONFIG_AL3010=m # CONFIG_AL3320A is not set # CONFIG_APDS9300 is not set CONFIG_APDS9960=m CONFIG_AS73211=m # CONFIG_BH1750 is not set # CONFIG_BH1780 is not set CONFIG_CM32181=m CONFIG_CM3232=m CONFIG_CM3323=m CONFIG_CM3605=m # CONFIG_CM36651 is not set CONFIG_GP2AP002=m CONFIG_GP2AP020A00F=m # CONFIG_IQS621_ALS is not set # CONFIG_SENSORS_ISL29018 is not set # CONFIG_SENSORS_ISL29028 is not set # CONFIG_ISL29125 is not set CONFIG_JSA1212=m CONFIG_RPR0521=m CONFIG_SENSORS_LM3533=m # CONFIG_LTR501 is not set CONFIG_LTRF216A=m CONFIG_LV0104CS=m CONFIG_MAX44000=m # CONFIG_MAX44009 is not set CONFIG_NOA1305=m CONFIG_OPT3001=m CONFIG_PA12203001=m CONFIG_SI1133=m # CONFIG_SI1145 is not set CONFIG_STK3310=m CONFIG_ST_UVIS25=m CONFIG_ST_UVIS25_I2C=m CONFIG_ST_UVIS25_SPI=m # CONFIG_TCS3414 is not set CONFIG_TCS3472=m CONFIG_SENSORS_TSL2563=m CONFIG_TSL2583=m # CONFIG_TSL2591 is not set CONFIG_TSL2772=m CONFIG_TSL4531=m CONFIG_US5182D=m # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set CONFIG_VEML6030=m CONFIG_VEML6070=m CONFIG_VL6180=m CONFIG_ZOPT2201=m # end of Light sensors # # Magnetometer sensors # CONFIG_AK8974=m # CONFIG_AK8975 is not set # CONFIG_AK09911 is not set CONFIG_BMC150_MAGN=m CONFIG_BMC150_MAGN_I2C=m CONFIG_BMC150_MAGN_SPI=m # CONFIG_MAG3110 is not set # CONFIG_MMC35240 is not set CONFIG_IIO_ST_MAGN_3AXIS=y CONFIG_IIO_ST_MAGN_I2C_3AXIS=m # CONFIG_IIO_ST_MAGN_SPI_3AXIS is not set CONFIG_SENSORS_HMC5843=m CONFIG_SENSORS_HMC5843_I2C=m # CONFIG_SENSORS_HMC5843_SPI is not set CONFIG_SENSORS_RM3100=m CONFIG_SENSORS_RM3100_I2C=m # CONFIG_SENSORS_RM3100_SPI is not set # CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors # # Multiplexers # # CONFIG_IIO_MUX is not set # end of Multiplexers # # Inclinometer sensors # # end of Inclinometer sensors CONFIG_IIO_FORMAT_KUNIT_TEST=m # # Triggers - standalone # # CONFIG_IIO_HRTIMER_TRIGGER is not set CONFIG_IIO_INTERRUPT_TRIGGER=y # CONFIG_IIO_STM32_LPTIMER_TRIGGER is not set # CONFIG_IIO_STM32_TIMER_TRIGGER is not set # CONFIG_IIO_TIGHTLOOP_TRIGGER is not set CONFIG_IIO_SYSFS_TRIGGER=y # end of Triggers - standalone # # Linear and angular position sensors # CONFIG_IQS624_POS=m # end of Linear and angular position sensors # # Digital potentiometers # CONFIG_AD5110=m # CONFIG_AD5272 is not set # CONFIG_DS1803 is not set CONFIG_MAX5432=m # CONFIG_MAX5481 is not set CONFIG_MAX5487=m CONFIG_MCP4018=m # CONFIG_MCP4131 is not set CONFIG_MCP4531=m CONFIG_MCP41010=m CONFIG_TPL0102=m # end of Digital potentiometers # # Digital potentiostats # CONFIG_LMP91000=m # end of Digital potentiostats # # Pressure sensors # CONFIG_ABP060MG=m # CONFIG_BMP280 is not set # CONFIG_DLHL60D is not set CONFIG_DPS310=m # CONFIG_HP03 is not set CONFIG_ICP10100=m CONFIG_MPL115=y CONFIG_MPL115_I2C=m CONFIG_MPL115_SPI=y # CONFIG_MPL3115 is not set # CONFIG_MS5611 is not set # CONFIG_MS5637 is not set CONFIG_IIO_ST_PRESS=m # CONFIG_IIO_ST_PRESS_I2C is not set # CONFIG_IIO_ST_PRESS_SPI is not set CONFIG_T5403=m # CONFIG_HP206C is not set # CONFIG_ZPA2326 is not set # end of Pressure sensors # # Lightning sensors # # CONFIG_AS3935 is not set # end of Lightning sensors # # Proximity and distance sensors # CONFIG_ISL29501=m # CONFIG_LIDAR_LITE_V2 is not set CONFIG_MB1232=m # CONFIG_PING is not set CONFIG_RFD77402=m CONFIG_SRF04=m CONFIG_SX_COMMON=m CONFIG_SX9310=m CONFIG_SX9324=m # CONFIG_SX9360 is not set CONFIG_SX9500=m CONFIG_SRF08=m CONFIG_VCNL3020=m CONFIG_VL53L0X_I2C=m # end of Proximity and distance sensors # # Resolver to digital converters # CONFIG_AD2S90=y CONFIG_AD2S1200=y # end of Resolver to digital converters # # Temperature sensors # # CONFIG_IQS620AT_TEMP is not set # CONFIG_LTC2983 is not set # CONFIG_MAXIM_THERMOCOUPLE is not set CONFIG_MLX90614=m CONFIG_MLX90632=m CONFIG_TMP006=m CONFIG_TMP007=m CONFIG_TMP117=m CONFIG_TSYS01=m CONFIG_TSYS02D=m CONFIG_MAX31856=y # CONFIG_MAX31865 is not set # end of Temperature sensors CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL is not set # CONFIG_PWM_ATMEL_TCB is not set # CONFIG_PWM_BCM_IPROC is not set # CONFIG_PWM_BCM_KONA is not set # CONFIG_PWM_BCM2835 is not set # CONFIG_PWM_BERLIN is not set # CONFIG_PWM_BRCMSTB is not set # CONFIG_PWM_CLK is not set # CONFIG_PWM_CLPS711X is not set # CONFIG_PWM_EP93XX is not set CONFIG_PWM_FSL_FTM=y # CONFIG_PWM_HIBVT is not set # CONFIG_PWM_IMG is not set CONFIG_PWM_IMX1=y # CONFIG_PWM_IMX27 is not set CONFIG_PWM_IMX_TPM=y # CONFIG_PWM_INTEL_LGM is not set # CONFIG_PWM_IQS620A is not set # CONFIG_PWM_JZ4740 is not set # CONFIG_PWM_KEEMBAY is not set # CONFIG_PWM_LP3943 is not set # CONFIG_PWM_LPC18XX_SCT is not set # CONFIG_PWM_LPC32XX is not set # CONFIG_PWM_LPSS_PLATFORM is not set # CONFIG_PWM_MESON is not set # CONFIG_PWM_MTK_DISP is not set # CONFIG_PWM_MEDIATEK is not set # CONFIG_PWM_MXS is not set CONFIG_PWM_NTXEC=m # CONFIG_PWM_OMAP_DMTIMER is not set # CONFIG_PWM_PCA9685 is not set # CONFIG_PWM_PXA is not set # CONFIG_PWM_RASPBERRYPI_POE is not set # CONFIG_PWM_RCAR is not set # CONFIG_PWM_RENESAS_TPU is not set # CONFIG_PWM_ROCKCHIP is not set # CONFIG_PWM_SAMSUNG is not set # CONFIG_PWM_SIFIVE is not set # CONFIG_PWM_SL28CPLD is not set # CONFIG_PWM_SPEAR is not set # CONFIG_PWM_SPRD is not set # CONFIG_PWM_STI is not set # CONFIG_PWM_STM32 is not set # CONFIG_PWM_STM32_LP is not set # CONFIG_PWM_SUN4I is not set # CONFIG_PWM_SUNPLUS is not set # CONFIG_PWM_TEGRA is not set # CONFIG_PWM_TIECAP is not set # CONFIG_PWM_TIEHRPWM is not set # CONFIG_PWM_VISCONTI is not set # CONFIG_PWM_VT8500 is not set # CONFIG_PWM_XILINX is not set # # IRQ chip support # CONFIG_IRQCHIP=y CONFIG_ARM_NVIC=y # CONFIG_AL_FIC is not set CONFIG_MADERA_IRQ=m # CONFIG_JCORE_AIC is not set # CONFIG_RENESAS_INTC_IRQPIN is not set # CONFIG_RENESAS_IRQC is not set # CONFIG_RENESAS_RZA1_IRQC is not set # CONFIG_RENESAS_RZG2L_IRQC is not set # CONFIG_SL28CPLD_INTC is not set # CONFIG_TS4800_IRQ is not set # CONFIG_XILINX_INTC is not set # CONFIG_INGENIC_TCU_IRQ is not set # CONFIG_IRQ_UNIPHIER_AIDET is not set # CONFIG_MESON_IRQ_GPIO is not set CONFIG_IMX_IRQSTEER=y CONFIG_IMX_INTMUX=y # CONFIG_IMX_MU_MSI is not set # CONFIG_EXYNOS_IRQ_COMBINER is not set # CONFIG_MST_IRQ is not set CONFIG_MCHP_EIC=y # CONFIG_SUNPLUS_SP7021_INTC is not set # end of IRQ chip support CONFIG_IPACK_BUS=m # CONFIG_SERIAL_IPOCTAL is not set CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_A10SR is not set # CONFIG_RESET_ATH79 is not set # CONFIG_RESET_AXS10X is not set # CONFIG_RESET_BCM6345 is not set # CONFIG_RESET_BERLIN is not set # CONFIG_RESET_BRCMSTB is not set # CONFIG_RESET_BRCMSTB_RESCAL is not set # CONFIG_RESET_HSDK is not set # CONFIG_RESET_IMX7 is not set # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_K210 is not set # CONFIG_RESET_LANTIQ is not set # CONFIG_RESET_LPC18XX is not set # CONFIG_RESET_MCHP_SPARX5 is not set # CONFIG_RESET_MESON is not set # CONFIG_RESET_MESON_AUDIO_ARB is not set # CONFIG_RESET_NPCM is not set # CONFIG_RESET_PISTACHIO is not set # CONFIG_RESET_QCOM_AOSS is not set # CONFIG_RESET_QCOM_PDC is not set # CONFIG_RESET_RASPBERRYPI is not set # CONFIG_RESET_RZG2L_USBPHY_CTRL is not set # CONFIG_RESET_SCMI is not set # CONFIG_RESET_SIMPLE is not set # CONFIG_RESET_SOCFPGA is not set # CONFIG_RESET_STARFIVE_JH7100 is not set # CONFIG_RESET_SUNPLUS is not set # CONFIG_RESET_SUNXI is not set # CONFIG_RESET_TI_SCI is not set CONFIG_RESET_TI_SYSCON=y CONFIG_RESET_TI_TPS380X=y # CONFIG_RESET_TN48M_CPLD is not set # CONFIG_RESET_UNIPHIER is not set # CONFIG_RESET_UNIPHIER_GLUE is not set # CONFIG_RESET_ZYNQ is not set # CONFIG_COMMON_RESET_HI3660 is not set # CONFIG_COMMON_RESET_HI6220 is not set # # PHY Subsystem # CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PHY_MIPI_DPHY=y # CONFIG_PHY_LPC18XX_USB_OTG is not set # CONFIG_PHY_PISTACHIO_USB is not set # CONFIG_PHY_XGENE is not set # CONFIG_USB_LGM_PHY is not set CONFIG_PHY_CAN_TRANSCEIVER=m # CONFIG_PHY_SUN4I_USB is not set # CONFIG_PHY_SUN6I_MIPI_DPHY is not set # CONFIG_PHY_SUN9I_USB is not set # CONFIG_PHY_SUN50I_USB3 is not set # CONFIG_PHY_MESON8_HDMI_TX is not set # CONFIG_PHY_MESON8B_USB2 is not set # CONFIG_PHY_MESON_GXL_USB2 is not set # CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG is not set # CONFIG_PHY_MESON_G12A_USB2 is not set # CONFIG_PHY_MESON_G12A_USB3_PCIE is not set # CONFIG_PHY_MESON_AXG_PCIE is not set # CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG is not set # CONFIG_PHY_MESON_AXG_MIPI_DPHY is not set # # PHY drivers for Broadcom platforms # # CONFIG_PHY_BCM63XX_USBH is not set # CONFIG_PHY_CYGNUS_PCIE is not set # CONFIG_PHY_BCM_SR_USB is not set CONFIG_BCM_KONA_USB2_PHY=m # CONFIG_PHY_BCM_NS_USB2 is not set # CONFIG_PHY_NS2_USB_DRD is not set # CONFIG_PHY_BRCM_SATA is not set # CONFIG_PHY_BRCM_USB is not set # CONFIG_PHY_BCM_SR_PCIE is not set # end of PHY drivers for Broadcom platforms CONFIG_PHY_CADENCE_TORRENT=m CONFIG_PHY_CADENCE_DPHY=m CONFIG_PHY_CADENCE_DPHY_RX=m CONFIG_PHY_CADENCE_SIERRA=m CONFIG_PHY_CADENCE_SALVO=y # CONFIG_PHY_FSL_IMX8MQ_USB is not set # CONFIG_PHY_MIXEL_LVDS_PHY is not set # CONFIG_PHY_MIXEL_MIPI_DPHY is not set # CONFIG_PHY_FSL_IMX8M_PCIE is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_HI6220_USB is not set # CONFIG_PHY_HI3660_USB is not set # CONFIG_PHY_HI3670_USB is not set # CONFIG_PHY_HI3670_PCIE is not set # CONFIG_PHY_HISTB_COMBPHY is not set # CONFIG_PHY_HISI_INNO_USB2 is not set # CONFIG_PHY_INGENIC_USB is not set # CONFIG_PHY_LANTIQ_VRX200_PCIE is not set # CONFIG_PHY_LANTIQ_RCU_USB2 is not set # CONFIG_ARMADA375_USBCLUSTER_PHY is not set # CONFIG_PHY_BERLIN_SATA is not set # CONFIG_PHY_BERLIN_USB is not set CONFIG_PHY_MVEBU_A3700_UTMI=y # CONFIG_PHY_MVEBU_A38X_COMPHY is not set # CONFIG_PHY_MVEBU_CP110_UTMI is not set CONFIG_PHY_PXA_28NM_HSIC=m CONFIG_PHY_PXA_28NM_USB2=y # CONFIG_PHY_PXA_USB is not set # CONFIG_PHY_MMP3_USB is not set # CONFIG_PHY_MMP3_HSIC is not set # CONFIG_PHY_MTK_PCIE is not set # CONFIG_PHY_MTK_TPHY is not set # CONFIG_PHY_MTK_UFS is not set # CONFIG_PHY_MTK_XSPHY is not set # CONFIG_PHY_MTK_HDMI is not set # CONFIG_PHY_MTK_MIPI_DSI is not set # CONFIG_PHY_MTK_DP is not set # CONFIG_PHY_SPARX5_SERDES is not set CONFIG_PHY_LAN966X_SERDES=y CONFIG_PHY_CPCAP_USB=y CONFIG_PHY_MAPPHONE_MDM6600=y CONFIG_PHY_OCELOT_SERDES=m CONFIG_PHY_ATH79_USB=y # CONFIG_PHY_QCOM_EDP is not set # CONFIG_PHY_QCOM_IPQ4019_USB is not set # CONFIG_PHY_QCOM_PCIE2 is not set # CONFIG_PHY_QCOM_QMP is not set # CONFIG_PHY_QCOM_QUSB2 is not set # CONFIG_PHY_QCOM_USB_HS is not set # CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set CONFIG_PHY_QCOM_USB_HSIC=m # CONFIG_PHY_QCOM_USB_HS_28NM is not set # CONFIG_PHY_QCOM_USB_SS is not set # CONFIG_PHY_QCOM_IPQ806X_USB is not set # CONFIG_PHY_MT7621_PCI is not set # CONFIG_PHY_RALINK_USB is not set # CONFIG_PHY_RCAR_GEN3_USB3 is not set # CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set # CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set # CONFIG_PHY_ROCKCHIP_INNO_USB2 is not set # CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set # CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set # CONFIG_PHY_ROCKCHIP_PCIE is not set # CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 is not set # CONFIG_PHY_ROCKCHIP_TYPEC is not set # CONFIG_PHY_EXYNOS_DP_VIDEO is not set # CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set # CONFIG_PHY_EXYNOS_PCIE is not set # CONFIG_PHY_SAMSUNG_UFS is not set CONFIG_PHY_SAMSUNG_USB2=m # CONFIG_PHY_S5PV210_USB2 is not set CONFIG_PHY_EXYNOS5_USBDRD=m # CONFIG_PHY_UNIPHIER_USB2 is not set # CONFIG_PHY_UNIPHIER_USB3 is not set # CONFIG_PHY_UNIPHIER_PCIE is not set # CONFIG_PHY_UNIPHIER_AHCI is not set # CONFIG_PHY_ST_SPEAR1310_MIPHY is not set # CONFIG_PHY_ST_SPEAR1340_MIPHY is not set # CONFIG_PHY_STIH407_USB is not set # CONFIG_PHY_STM32_USBPHYC is not set # CONFIG_PHY_SUNPLUS_USB is not set # CONFIG_PHY_TEGRA194_P2U is not set # CONFIG_PHY_DA8XX_USB is not set # CONFIG_PHY_DM816X_USB is not set # CONFIG_PHY_AM654_SERDES is not set # CONFIG_PHY_J721E_WIZ is not set # CONFIG_OMAP_CONTROL_PHY is not set # CONFIG_TI_PIPE3 is not set CONFIG_PHY_TUSB1210=m # CONFIG_PHY_INTEL_KEEMBAY_EMMC is not set # CONFIG_PHY_INTEL_KEEMBAY_USB is not set # CONFIG_PHY_INTEL_LGM_COMBO is not set # CONFIG_PHY_INTEL_LGM_EMMC is not set # CONFIG_PHY_INTEL_THUNDERBAY_EMMC is not set # CONFIG_PHY_XILINX_ZYNQMP is not set # end of PHY Subsystem # CONFIG_POWERCAP is not set CONFIG_MCB=y CONFIG_MCB_LPC=m # # Performance monitor support # # CONFIG_ARM_CCN is not set # CONFIG_ARM_CMN is not set # CONFIG_ARM_PMU is not set CONFIG_FSL_IMX8_DDR_PMU=y # CONFIG_ARM_DMC620_PMU is not set # CONFIG_ALIBABA_UNCORE_DRW_PMU is not set # end of Performance monitor support CONFIG_RAS=y # # Android # # end of Android # CONFIG_DAX is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y # CONFIG_NVMEM_APPLE_EFUSES is not set # CONFIG_NVMEM_BCM_OCOTP is not set # CONFIG_NVMEM_BRCM_NVRAM is not set # CONFIG_NVMEM_IMX_IIM is not set # CONFIG_NVMEM_IMX_OCOTP is not set # CONFIG_NVMEM_JZ4780_EFUSE is not set # CONFIG_NVMEM_LAN9662_OTPC is not set # CONFIG_NVMEM_LAYERSCAPE_SFP is not set # CONFIG_NVMEM_LPC18XX_EEPROM is not set # CONFIG_NVMEM_LPC18XX_OTP is not set # CONFIG_NVMEM_MESON_MX_EFUSE is not set CONFIG_NVMEM_MICROCHIP_OTPC=y # CONFIG_NVMEM_MTK_EFUSE is not set # CONFIG_NVMEM_MXS_OCOTP is not set # CONFIG_NVMEM_NINTENDO_OTP is not set # CONFIG_NVMEM_QCOM_QFPROM is not set CONFIG_NVMEM_RMEM=m # CONFIG_NVMEM_ROCKCHIP_EFUSE is not set # CONFIG_NVMEM_ROCKCHIP_OTP is not set # CONFIG_NVMEM_SC27XX_EFUSE is not set CONFIG_NVMEM_SNVS_LPGPR=m CONFIG_NVMEM_SPMI_SDAM=m # CONFIG_NVMEM_SPRD_EFUSE is not set # CONFIG_NVMEM_STM32_ROMEM is not set # CONFIG_NVMEM_SUNPLUS_OCOTP is not set # CONFIG_NVMEM_UNIPHIER_EFUSE is not set # CONFIG_NVMEM_VF610_OCOTP is not set # # HW tracing support # CONFIG_STM=m CONFIG_STM_PROTO_BASIC=m CONFIG_STM_PROTO_SYS_T=m CONFIG_STM_DUMMY=m CONFIG_STM_SOURCE_CONSOLE=m CONFIG_STM_SOURCE_HEARTBEAT=m CONFIG_INTEL_TH=y CONFIG_INTEL_TH_GTH=y # CONFIG_INTEL_TH_STH is not set CONFIG_INTEL_TH_MSU=y CONFIG_INTEL_TH_PTI=m CONFIG_INTEL_TH_DEBUG=y # end of HW tracing support # CONFIG_FPGA is not set CONFIG_FSI=m # CONFIG_FSI_NEW_DEV_NODE is not set CONFIG_FSI_MASTER_GPIO=m CONFIG_FSI_MASTER_HUB=m # CONFIG_FSI_MASTER_ASPEED is not set # CONFIG_FSI_SCOM is not set # CONFIG_FSI_SBEFIFO is not set # CONFIG_TEE is not set CONFIG_MULTIPLEXER=y # # Multiplexer drivers # CONFIG_MUX_ADG792A=m CONFIG_MUX_ADGS1408=y CONFIG_MUX_GPIO=m CONFIG_MUX_MMIO=m # end of Multiplexer drivers CONFIG_PM_OPP=y CONFIG_SIOX=m CONFIG_SIOX_BUS_GPIO=m # CONFIG_SLIMBUS is not set CONFIG_INTERCONNECT=y CONFIG_INTERCONNECT_IMX=m CONFIG_INTERCONNECT_IMX8MM=m CONFIG_INTERCONNECT_IMX8MN=m # CONFIG_INTERCONNECT_IMX8MQ is not set CONFIG_INTERCONNECT_IMX8MP=m # CONFIG_INTERCONNECT_QCOM_OSM_L3 is not set # CONFIG_INTERCONNECT_SAMSUNG is not set CONFIG_COUNTER=m # CONFIG_104_QUAD_8 is not set # CONFIG_INTERRUPT_CNT is not set # CONFIG_STM32_TIMER_CNT is not set # CONFIG_STM32_LPTIMER_CNT is not set # CONFIG_TI_EQEP is not set # CONFIG_FTM_QUADDEC is not set CONFIG_MICROCHIP_TCB_CAPTURE=m # CONFIG_TI_ECAP_CAPTURE is not set CONFIG_MOST=m CONFIG_MOST_USB_HDM=m # CONFIG_MOST_CDEV is not set CONFIG_PECI=y CONFIG_PECI_CPU=y # CONFIG_PECI_ASPEED is not set # CONFIG_HTE is not set # end of Device Drivers # # File systems # CONFIG_VALIDATE_FS_PARSER=y CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set CONFIG_FILE_LOCKING=y CONFIG_FS_ENCRYPTION=y CONFIG_FS_VERITY=y # CONFIG_FS_VERITY_DEBUG is not set # CONFIG_FS_VERITY_BUILTIN_SIGNATURES is not set CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y CONFIG_FANOTIFY=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set # CONFIG_QUOTA_DEBUG is not set CONFIG_QUOTA_TREE=m CONFIG_QFMT_V1=y CONFIG_QFMT_V2=m CONFIG_QUOTACTL=y CONFIG_AUTOFS4_FS=m CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=y CONFIG_CUSE=m # CONFIG_VIRTIO_FS is not set CONFIG_OVERLAY_FS=m CONFIG_OVERLAY_FS_REDIRECT_DIR=y CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # CONFIG_OVERLAY_FS_INDEX is not set # CONFIG_OVERLAY_FS_METACOPY is not set # # Caches # CONFIG_NETFS_SUPPORT=m CONFIG_FSCACHE=m # CONFIG_FSCACHE_DEBUG is not set # end of Caches # # Pseudo filesystems # # CONFIG_PROC_FS is not set CONFIG_KERNFS=y CONFIG_SYSFS=y CONFIG_CONFIGFS_FS=y # end of Pseudo filesystems # CONFIG_MISC_FILESYSTEMS is not set # CONFIG_NETWORK_FILESYSTEMS is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=m # CONFIG_NLS_CODEPAGE_737 is not set CONFIG_NLS_CODEPAGE_775=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_CODEPAGE_852=m # CONFIG_NLS_CODEPAGE_855 is not set CONFIG_NLS_CODEPAGE_857=m # CONFIG_NLS_CODEPAGE_860 is not set CONFIG_NLS_CODEPAGE_861=y CONFIG_NLS_CODEPAGE_862=y CONFIG_NLS_CODEPAGE_863=y CONFIG_NLS_CODEPAGE_864=m # CONFIG_NLS_CODEPAGE_865 is not set CONFIG_NLS_CODEPAGE_866=y CONFIG_NLS_CODEPAGE_869=y CONFIG_NLS_CODEPAGE_936=y CONFIG_NLS_CODEPAGE_950=m CONFIG_NLS_CODEPAGE_932=m CONFIG_NLS_CODEPAGE_949=m CONFIG_NLS_CODEPAGE_874=m # CONFIG_NLS_ISO8859_8 is not set # CONFIG_NLS_CODEPAGE_1250 is not set CONFIG_NLS_CODEPAGE_1251=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=m CONFIG_NLS_ISO8859_2=m # CONFIG_NLS_ISO8859_3 is not set # CONFIG_NLS_ISO8859_4 is not set CONFIG_NLS_ISO8859_5=y CONFIG_NLS_ISO8859_6=m # CONFIG_NLS_ISO8859_7 is not set CONFIG_NLS_ISO8859_9=m # CONFIG_NLS_ISO8859_13 is not set # CONFIG_NLS_ISO8859_14 is not set # CONFIG_NLS_ISO8859_15 is not set CONFIG_NLS_KOI8_R=y # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_MAC_ROMAN is not set # CONFIG_NLS_MAC_CELTIC is not set # CONFIG_NLS_MAC_CENTEURO is not set CONFIG_NLS_MAC_CROATIAN=m CONFIG_NLS_MAC_CYRILLIC=m # CONFIG_NLS_MAC_GAELIC is not set # CONFIG_NLS_MAC_GREEK is not set # CONFIG_NLS_MAC_ICELAND is not set CONFIG_NLS_MAC_INUIT=m # CONFIG_NLS_MAC_ROMANIAN is not set # CONFIG_NLS_MAC_TURKISH is not set # CONFIG_NLS_UTF8 is not set CONFIG_DLM=y CONFIG_DLM_DEPRECATED_API=y # CONFIG_DLM_DEBUG is not set CONFIG_UNICODE=y CONFIG_UNICODE_NORMALIZATION_SELFTEST=m CONFIG_IO_WQ=y # end of File systems # # Security options # CONFIG_KEYS=y # CONFIG_KEYS_REQUEST_CACHE is not set # CONFIG_PERSISTENT_KEYRINGS is not set # CONFIG_TRUSTED_KEYS is not set CONFIG_ENCRYPTED_KEYS=y CONFIG_USER_DECRYPTED_DATA=y CONFIG_KEY_DH_OPERATIONS=y # CONFIG_KEY_NOTIFICATIONS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SECURITYFS is not set CONFIG_FORTIFY_SOURCE=y CONFIG_STATIC_USERMODEHELPER=y CONFIG_STATIC_USERMODEHELPER_PATH="/sbin/usermode-helper" CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf" # # Kernel hardening options # # # Memory initialization # CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y # CONFIG_INIT_STACK_NONE is not set # CONFIG_INIT_STACK_ALL_PATTERN is not set CONFIG_INIT_STACK_ALL_ZERO=y # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set CONFIG_INIT_ON_FREE_DEFAULT_ON=y # end of Memory initialization CONFIG_CC_HAS_RANDSTRUCT=y # CONFIG_RANDSTRUCT_NONE is not set CONFIG_RANDSTRUCT_FULL=y CONFIG_RANDSTRUCT=y # end of Kernel hardening options # end of Security options CONFIG_CRYPTO=y # # Crypto core or helper # CONFIG_CRYPTO_FIPS=y CONFIG_CRYPTO_FIPS_NAME="Linux Kernel Cryptographic API" CONFIG_CRYPTO_FIPS_CUSTOM_VERSION=y CONFIG_CRYPTO_FIPS_VERSION="(none)" CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_AKCIPHER2=y CONFIG_CRYPTO_AKCIPHER=y CONFIG_CRYPTO_KPP2=y CONFIG_CRYPTO_KPP=y CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_USER is not set # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set # CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_AUTHENC=y CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_ENGINE=y # end of Crypto core or helper # # Public-key cryptography # CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_ECC=y CONFIG_CRYPTO_ECDH=m CONFIG_CRYPTO_ECDSA=y CONFIG_CRYPTO_ECRDSA=y # CONFIG_CRYPTO_SM2 is not set CONFIG_CRYPTO_CURVE25519=m # end of Public-key cryptography # # Block ciphers # CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set CONFIG_CRYPTO_ARIA=m CONFIG_CRYPTO_BLOWFISH=y CONFIG_CRYPTO_BLOWFISH_COMMON=y CONFIG_CRYPTO_CAMELLIA=y # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_SM4=m CONFIG_CRYPTO_SM4_GENERIC=m CONFIG_CRYPTO_TWOFISH=y CONFIG_CRYPTO_TWOFISH_COMMON=y # end of Block ciphers # # Length-preserving ciphers and modes # CONFIG_CRYPTO_ADIANTUM=m CONFIG_CRYPTO_CHACHA20=y CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CFB=m CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_CTS=y CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_HCTR2=m CONFIG_CRYPTO_KEYWRAP=m # CONFIG_CRYPTO_LRW is not set # CONFIG_CRYPTO_OFB is not set # CONFIG_CRYPTO_PCBC is not set CONFIG_CRYPTO_XCTR=m CONFIG_CRYPTO_XTS=y CONFIG_CRYPTO_NHPOLY1305=m # end of Length-preserving ciphers and modes # # AEAD (authenticated encryption with associated data) ciphers # # CONFIG_CRYPTO_AEGIS128 is not set CONFIG_CRYPTO_CHACHA20POLY1305=y CONFIG_CRYPTO_CCM=m CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_SEQIV=m CONFIG_CRYPTO_ECHAINIV=y CONFIG_CRYPTO_ESSIV=m # end of AEAD (authenticated encryption with associated data) ciphers # # Hashes, digests, and MACs # # CONFIG_CRYPTO_BLAKE2B is not set CONFIG_CRYPTO_CMAC=m CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_POLYVAL=m CONFIG_CRYPTO_POLY1305=y CONFIG_CRYPTO_RMD160=y CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_SHA3 is not set CONFIG_CRYPTO_SM3=m # CONFIG_CRYPTO_SM3_GENERIC is not set CONFIG_CRYPTO_STREEBOG=y # CONFIG_CRYPTO_VMAC is not set # CONFIG_CRYPTO_WP512 is not set # CONFIG_CRYPTO_XCBC is not set # CONFIG_CRYPTO_XXHASH is not set # end of Hashes, digests, and MACs # # CRCs (cyclic redundancy checks) # CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_CRC32 is not set CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_CRC64_ROCKSOFT=m # end of CRCs (cyclic redundancy checks) # # Compression # CONFIG_CRYPTO_DEFLATE=m # CONFIG_CRYPTO_LZO is not set # CONFIG_CRYPTO_842 is not set # CONFIG_CRYPTO_LZ4 is not set CONFIG_CRYPTO_LZ4HC=m # CONFIG_CRYPTO_ZSTD is not set # end of Compression # # Random number generation # CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_DRBG_MENU=y CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_HASH is not set # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_KDF800108_CTR=y # end of Random number generation # # Userspace interface # CONFIG_CRYPTO_USER_API=y CONFIG_CRYPTO_USER_API_HASH=m # CONFIG_CRYPTO_USER_API_SKCIPHER is not set # CONFIG_CRYPTO_USER_API_RNG is not set CONFIG_CRYPTO_USER_API_AEAD=y # CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set # end of Userspace interface CONFIG_CRYPTO_HASH_INFO=y # # Accelerated Cryptographic Algorithms for CPU (arm) # CONFIG_CRYPTO_POLY1305_ARM=m CONFIG_CRYPTO_BLAKE2S_ARM=y CONFIG_CRYPTO_SHA1_ARM=m CONFIG_CRYPTO_AES_ARM=m # CONFIG_CRYPTO_CHACHA20_NEON is not set # end of Accelerated Cryptographic Algorithms for CPU (arm) CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_ALLWINNER is not set # CONFIG_CRYPTO_DEV_SL3516 is not set CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y CONFIG_CRYPTO_DEV_FSL_CAAM=y CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG=y CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 CONFIG_CRYPTO_DEV_FSL_CAAM_INTC=y CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD=255 CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD=2048 CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y # CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API is not set # CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API is not set CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API=y CONFIG_CRYPTO_DEV_SAHARA=y # CONFIG_CRYPTO_DEV_EXYNOS_RNG is not set # CONFIG_CRYPTO_DEV_S5P is not set CONFIG_CRYPTO_DEV_ATMEL_AUTHENC=y CONFIG_CRYPTO_DEV_ATMEL_AES=y CONFIG_CRYPTO_DEV_ATMEL_TDES=m CONFIG_CRYPTO_DEV_ATMEL_SHA=y CONFIG_CRYPTO_DEV_ATMEL_I2C=m CONFIG_CRYPTO_DEV_ATMEL_ECC=m CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m CONFIG_CRYPTO_DEV_MXS_DCP=m # CONFIG_CRYPTO_DEV_QCE is not set # CONFIG_CRYPTO_DEV_QCOM_RNG is not set # CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set # CONFIG_CRYPTO_DEV_ZYNQMP_AES is not set # CONFIG_CRYPTO_DEV_ZYNQMP_SHA3 is not set CONFIG_CRYPTO_DEV_VIRTIO=m # CONFIG_CRYPTO_DEV_SAFEXCEL is not set # CONFIG_CRYPTO_DEV_ARTPEC6 is not set CONFIG_CRYPTO_DEV_CCREE=m # CONFIG_CRYPTO_DEV_HISI_SEC is not set CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y # CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set # CONFIG_CRYPTO_DEV_SA2UL is not set # CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4 is not set # CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECC is not set # CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU is not set # CONFIG_CRYPTO_DEV_ASPEED is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y CONFIG_PKCS8_PRIVATE_KEY_PARSER=y CONFIG_PKCS7_MESSAGE_PARSER=y CONFIG_PKCS7_TEST_KEY=m # CONFIG_SIGNED_PE_FILE_VERIFICATION is not set # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # # Certificates for signature checking # CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" CONFIG_MODULE_SIG_KEY_TYPE_RSA=y # CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set CONFIG_SYSTEM_TRUSTED_KEYRING=y CONFIG_SYSTEM_TRUSTED_KEYS="" # CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set CONFIG_SECONDARY_TRUSTED_KEYRING=y # CONFIG_SYSTEM_BLACKLIST_KEYRING is not set # end of Certificates for signature checking CONFIG_BINARY_PRINTF=y # # Library routines # CONFIG_LINEAR_RANGES=y # CONFIG_PACKING is not set CONFIG_BITREVERSE=y CONFIG_HAVE_ARCH_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y CONFIG_CORDIC=y CONFIG_PRIME_NUMBERS=m CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_STMP_DEVICE=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y # # Crypto library routines # CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y CONFIG_CRYPTO_LIB_CHACHA=m CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m CONFIG_CRYPTO_LIB_CURVE25519=m CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC_T10DIF=m CONFIG_CRC64_ROCKSOFT=m CONFIG_CRC_ITU_T=y CONFIG_CRC32=y CONFIG_CRC32_SELFTEST=m # CONFIG_CRC32_SLICEBY8 is not set # CONFIG_CRC32_SLICEBY4 is not set CONFIG_CRC32_SARWATE=y # CONFIG_CRC32_BIT is not set CONFIG_CRC64=m CONFIG_CRC4=y # CONFIG_CRC7 is not set CONFIG_LIBCRC32C=y CONFIG_CRC8=y # CONFIG_RANDOM32_SELFTEST is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4HC_COMPRESS=m CONFIG_LZ4_DECOMPRESS=m CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y # CONFIG_XZ_DEC_POWERPC is not set # CONFIG_XZ_DEC_IA64 is not set # CONFIG_XZ_DEC_ARM is not set CONFIG_XZ_DEC_ARMTHUMB=y # CONFIG_XZ_DEC_SPARC is not set CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_BCJ=y CONFIG_XZ_DEC_TEST=m CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_LZMA=y CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_REED_SOLOMON=y CONFIG_REED_SOLOMON_ENC16=y CONFIG_REED_SOLOMON_DEC16=y CONFIG_INTERVAL_TREE=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_DMA=y CONFIG_DMA_OPS=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_GLOBAL_POOL=y # CONFIG_DMA_API_DEBUG is not set # CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_DQL=y CONFIG_GLOB=y # CONFIG_GLOB_SELFTEST is not set CONFIG_NLATTR=y CONFIG_GENERIC_ATOMIC64=y CONFIG_CLZ_TAB=y CONFIG_IRQ_POLL=y CONFIG_MPILIB=y CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_STACKDEPOT=y CONFIG_REF_TRACKER=y # CONFIG_PARMAN is not set # CONFIG_OBJAGG is not set # end of Library routines CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y # # Kernel hacking # # # printk and dmesg options # CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_SYMBOLIC_ERRNAME is not set CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y # # Compile-time checks and compiler options # CONFIG_AS_HAS_NON_CONST_LEB128=y CONFIG_DEBUG_INFO_NONE=y # CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set # CONFIG_DEBUG_INFO_DWARF4 is not set # CONFIG_DEBUG_INFO_DWARF5 is not set CONFIG_FRAME_WARN=1024 CONFIG_STRIP_ASM_SYMS=y # CONFIG_HEADERS_INSTALL is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y CONFIG_VMLINUX_MAP=y # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options # # Generic Kernel Debugging Instruments # CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 CONFIG_MAGIC_SYSRQ_SERIAL=y CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" CONFIG_DEBUG_FS=y # CONFIG_DEBUG_FS_ALLOW_ALL is not set # CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set CONFIG_DEBUG_FS_ALLOW_NONE=y CONFIG_UBSAN=y CONFIG_CC_HAS_UBSAN_BOUNDS=y CONFIG_CC_HAS_UBSAN_ARRAY_BOUNDS=y # CONFIG_UBSAN_BOUNDS is not set CONFIG_UBSAN_SHIFT=y CONFIG_UBSAN_UNREACHABLE=y CONFIG_UBSAN_BOOL=y CONFIG_UBSAN_ENUM=y CONFIG_TEST_UBSAN=m # end of Generic Kernel Debugging Instruments # # Networking Debugging # CONFIG_NET_DEV_REFCNT_TRACKER=y CONFIG_NET_NS_REFCNT_TRACKER=y CONFIG_DEBUG_NET=y # end of Networking Debugging # # Memory Debugging # CONFIG_PAGE_EXTENSION=y # CONFIG_DEBUG_PAGEALLOC is not set CONFIG_PAGE_OWNER=y # CONFIG_PAGE_POISONING is not set CONFIG_DEBUG_OBJECTS=y # CONFIG_DEBUG_OBJECTS_SELFTEST is not set CONFIG_DEBUG_OBJECTS_FREE=y # CONFIG_DEBUG_OBJECTS_TIMERS is not set CONFIG_DEBUG_OBJECTS_WORK=y # CONFIG_DEBUG_OBJECTS_RCU_HEAD is not set CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 CONFIG_SHRINKER_DEBUG=y CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_SCHED_STACK_END_CHECK=y CONFIG_DEBUG_VM_IRQSOFF=y CONFIG_DEBUG_VM=y # CONFIG_DEBUG_VM_MAPLE_TREE is not set # CONFIG_DEBUG_VM_RB is not set # CONFIG_DEBUG_VM_PGFLAGS is not set CONFIG_DEBUG_NOMMU_REGIONS=y # CONFIG_DEBUG_MEMORY_INIT is not set CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # end of Memory Debugging CONFIG_DEBUG_SHIRQ=y # # Debug Oops, Lockups and Hangs # CONFIG_PANIC_ON_OOPS=y CONFIG_PANIC_ON_OOPS_VALUE=1 CONFIG_PANIC_TIMEOUT=0 CONFIG_LOCKUP_DETECTOR=y CONFIG_SOFTLOCKUP_DETECTOR=y CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y # CONFIG_DETECT_HUNG_TASK is not set # CONFIG_WQ_WATCHDOG is not set CONFIG_TEST_LOCKUP=m # end of Debug Oops, Lockups and Hangs # # Scheduler Debugging # # end of Scheduler Debugging CONFIG_DEBUG_TIMEKEEPING=y # # Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_DEBUG_RT_MUTEXES=y # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_MUTEXES is not set CONFIG_DEBUG_RWSEMS=y CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_DEBUG_LOCKING_API_SELFTESTS=y # CONFIG_LOCK_TORTURE_TEST is not set CONFIG_WW_MUTEX_SELFTEST=y # CONFIG_SCF_TORTURE_TEST is not set # end of Lock Debugging (spinlocks, mutexes, etc...) CONFIG_DEBUG_IRQFLAGS=y CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set # # Debug kernel data structures # CONFIG_DEBUG_LIST=y # CONFIG_DEBUG_PLIST is not set CONFIG_DEBUG_SG=y CONFIG_DEBUG_NOTIFIERS=y CONFIG_BUG_ON_DATA_CORRUPTION=y CONFIG_DEBUG_MAPLE_TREE=y # end of Debug kernel data structures CONFIG_DEBUG_CREDENTIALS=y # # RCU Debugging # CONFIG_TORTURE_TEST=y # CONFIG_RCU_SCALE_TEST is not set CONFIG_RCU_TORTURE_TEST=y CONFIG_RCU_REF_SCALE_TEST=y CONFIG_RCU_CPU_STALL_TIMEOUT=21 CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 # CONFIG_RCU_TRACE is not set # CONFIG_RCU_EQS_DEBUG is not set # end of RCU Debugging CONFIG_DEBUG_WQ_FORCE_RR_CPU=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y # CONFIG_SAMPLES is not set # # arm Debugging # CONFIG_UNWINDER_ARM=y CONFIG_ARM_UNWIND=y # CONFIG_BACKTRACE_VERBOSE is not set # CONFIG_DEBUG_USER is not set # CONFIG_DEBUG_LL is not set CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" CONFIG_CORESIGHT=m CONFIG_CORESIGHT_LINKS_AND_SINKS=m CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m CONFIG_CORESIGHT_CATU=m # CONFIG_CORESIGHT_SINK_TPIU is not set CONFIG_CORESIGHT_SINK_ETBV10=m CONFIG_CORESIGHT_SOURCE_ETM3X=m CONFIG_CORESIGHT_STM=m # CONFIG_CORESIGHT_CPU_DEBUG is not set # CONFIG_CORESIGHT_CTI is not set # end of arm Debugging # # Kernel Testing and Coverage # CONFIG_KUNIT=m # CONFIG_KUNIT_DEBUGFS is not set # CONFIG_KUNIT_TEST is not set CONFIG_KUNIT_EXAMPLE_TEST=m # CONFIG_KUNIT_ALL_TESTS is not set # CONFIG_KUNIT_DEFAULT_ENABLED is not set CONFIG_NOTIFIER_ERROR_INJECTION=y CONFIG_PM_NOTIFIER_ERROR_INJECT=y CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=m # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set CONFIG_CPUMASK_KUNIT_TEST=m CONFIG_TEST_LIST_SORT=m CONFIG_TEST_MIN_HEAP=y CONFIG_TEST_SORT=m CONFIG_TEST_DIV64=y # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_TEST_REF_TRACKER is not set CONFIG_RBTREE_TEST=y CONFIG_REED_SOLOMON_TEST=y # CONFIG_INTERVAL_TREE_TEST is not set # CONFIG_PERCPU_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set CONFIG_TEST_HEXDUMP=m # CONFIG_STRING_SELFTEST is not set CONFIG_TEST_STRING_HELPERS=m # CONFIG_TEST_STRSCPY is not set # CONFIG_TEST_KSTRTOX is not set CONFIG_TEST_PRINTF=m CONFIG_TEST_SCANF=m CONFIG_TEST_BITMAP=y # CONFIG_TEST_UUID is not set CONFIG_TEST_XARRAY=m # CONFIG_TEST_RHASHTABLE is not set # CONFIG_TEST_SIPHASH is not set CONFIG_TEST_IDA=m CONFIG_TEST_LKM=m CONFIG_TEST_BITOPS=m CONFIG_TEST_USER_COPY=m CONFIG_TEST_BPF=m CONFIG_TEST_BLACKHOLE_DEV=m CONFIG_FIND_BIT_BENCHMARK=y # CONFIG_TEST_FIRMWARE is not set # CONFIG_BITFIELD_KUNIT is not set CONFIG_HASH_KUNIT_TEST=m # CONFIG_RESOURCE_KUNIT_TEST is not set CONFIG_SYSCTL_KUNIT_TEST=m # CONFIG_LIST_KUNIT_TEST is not set # CONFIG_LINEAR_RANGES_TEST is not set CONFIG_CMDLINE_KUNIT_TEST=m CONFIG_BITS_TEST=m CONFIG_RATIONAL_KUNIT_TEST=m # CONFIG_MEMCPY_KUNIT_TEST is not set CONFIG_IS_SIGNED_TYPE_KUNIT_TEST=m # CONFIG_OVERFLOW_KUNIT_TEST is not set # CONFIG_STACKINIT_KUNIT_TEST is not set # CONFIG_FORTIFY_KUNIT_TEST is not set # CONFIG_TEST_UDELAY is not set # CONFIG_TEST_STATIC_KEYS is not set CONFIG_TEST_MEMCAT_P=y # CONFIG_TEST_MEMINIT is not set CONFIG_TEST_FREE_PAGES=m CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage # # Rust hacking # # end of Rust hacking # CONFIG_WARN_MISSING_DOCUMENTS is not set # CONFIG_WARN_ABI_ERRORS is not set # end of Kernel hacking ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 03/12] mfd: cs48l32: Add support for CS48L31/32/33 codecs 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-16 15:43 ` Lee Jones -1 siblings, 0 replies; 98+ messages in thread From: Lee Jones @ 2022-11-16 15:43 UTC (permalink / raw) To: Richard Fitzgerald Cc: robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On Wed, 09 Nov 2022, Richard Fitzgerald wrote: > From: Piotr Stankiewicz <piotrs@opensource.cirrus.com> > > The CS48L31/32/33 audio codecs are multi-function devices > containing gpios, irq controller and regulators in addition > to the core audio functionality. > > Signed-off-by: Piotr Stankiewicz <piotrs@opensource.cirrus.com> > Signed-off-by: Qi Zhou <qi.zhou@cirrus.com> > Signed-off-by: Stuart Henderson <stuarth@opensource.cirrus.com> > Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> > --- > MAINTAINERS | 5 +- > drivers/mfd/Kconfig | 13 + > drivers/mfd/Makefile | 2 + > drivers/mfd/cs48l32-tables.c | 541 +++++++++++++++++++++++++++++++ > drivers/mfd/cs48l32.c | 434 +++++++++++++++++++++++++ > drivers/mfd/cs48l32.h | 28 ++ > include/linux/mfd/cs48l32/core.h | 49 +++ > 7 files changed, 1071 insertions(+), 1 deletion(-) > create mode 100644 drivers/mfd/cs48l32-tables.c > create mode 100644 drivers/mfd/cs48l32.c > create mode 100644 drivers/mfd/cs48l32.h > create mode 100644 include/linux/mfd/cs48l32/core.h Nice first attempt. Few nits below. > diff --git a/MAINTAINERS b/MAINTAINERS > index 3f94ed38089b..f1d696f29f11 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -5001,7 +5001,7 @@ F: include/dt-bindings/pinctrl/lochnagar.h > F: include/linux/mfd/lochnagar* > F: sound/soc/codecs/lochnagar-sc.c > > -CIRRUS LOGIC MADERA CODEC DRIVERS > +CIRRUS LOGIC MADERA/CS48L32 CODEC DRIVERS > M: Charles Keepax <ckeepax@opensource.cirrus.com> > M: Richard Fitzgerald <rf@opensource.cirrus.com> > L: alsa-devel@alsa-project.org (moderated for non-subscribers) > @@ -5009,16 +5009,19 @@ L: patches@opensource.cirrus.com > S: Supported > W: https://github.com/CirrusLogic/linux-drivers/wiki > T: git https://github.com/CirrusLogic/linux-drivers.git > +F: Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml > F: Documentation/devicetree/bindings/mfd/cirrus,madera.yaml > F: Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml > F: Documentation/devicetree/bindings/sound/cirrus,madera.yaml > F: drivers/gpio/gpio-madera* > F: drivers/irqchip/irq-madera* > F: drivers/mfd/cs47l* > +F: drivers/mfd/cs48l* > F: drivers/mfd/madera* > F: drivers/pinctrl/cirrus/* > F: include/dt-bindings/sound/madera* > F: include/linux/irqchip/irq-madera* > +F: include/linux/mfd/cs48l32/* > F: include/linux/mfd/madera/* > F: include/sound/madera* > F: sound/soc/codecs/cs47l* > diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig > index 6653d03e0fe3..2be52ba23c7a 100644 > --- a/drivers/mfd/Kconfig > +++ b/drivers/mfd/Kconfig > @@ -300,6 +300,19 @@ config MFD_CS47L92 > help > Support for Cirrus Logic CS42L92, CS47L92 and CS47L93 Smart Codecs > > +config MFD_CS48L32 > + bool "Cirrus Logic CS48L31/32/33" > + depends on SPI_MASTER > + select MFD_CORE > + select REGMAP > + select REGMAP_SPI > + select REGMAP_IRQ > + select CIRRUS_CS48L32_IRQ > + select PINCTRL > + select PINCTRL_CS48L32 > + help > + Support for Cirrus Logic CS48L31, CS48L32 and CS48L33 Smart Codecs. > + > config MFD_ASIC3 > bool "Compaq ASIC3" > depends on GPIOLIB > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile > index 4dd479212b3a..4edbeb9b7a31 100644 > --- a/drivers/mfd/Makefile > +++ b/drivers/mfd/Makefile > @@ -91,6 +91,8 @@ obj-$(CONFIG_MFD_MADERA) += madera.o > obj-$(CONFIG_MFD_MADERA_I2C) += madera-i2c.o > obj-$(CONFIG_MFD_MADERA_SPI) += madera-spi.o > > +obj-$(CONFIG_MFD_CS48L32) += cs48l32.o cs48l32-tables.o > + > obj-$(CONFIG_TPS6105X) += tps6105x.o > obj-$(CONFIG_TPS65010) += tps65010.o > obj-$(CONFIG_TPS6507X) += tps6507x.o > diff --git a/drivers/mfd/cs48l32-tables.c b/drivers/mfd/cs48l32-tables.c > new file mode 100644 > index 000000000000..5dab9753deb0 > --- /dev/null > +++ b/drivers/mfd/cs48l32-tables.c > @@ -0,0 +1,541 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Regmap tables for Cirrus Logic CS48L32 audio codec. > + * > + * Copyright (C) 2018, 2020, 2022 Cirrus Logic, Inc. and > + * Cirrus Logic International Semiconductor Ltd. > + */ > + > +#include <linux/device.h> > +#include <linux/module.h> > +#include <linux/mfd/cs48l32/core.h> > +#include <linux/mfd/cs48l32/registers.h> > + > +#include "cs48l32.h" > + > +static const struct reg_sequence cs48l32_reva_patch[] = { > + { 0x00001044, 0x0005000f }, > + { 0x00001c34, 0x000037e8 }, > + { 0x000046d8, 0x00000fe0 }, > +}; > + > +int cs48l32_patch(struct cs48l32_mfd *cs48l32) > +{ > + int ret; > + > + ret = regmap_register_patch(cs48l32->regmap, cs48l32_reva_patch, > + ARRAY_SIZE(cs48l32_reva_patch)); > + if (ret < 0) > + dev_err(cs48l32->dev, "Error applying patch: %d\n", ret); > + > + return ret; > +} > + > +static const struct reg_default cs48l32_reg_default[] = { > + { 0x00000c08, 0xe1000001 }, /* GPIO1_CTRL1 */ > + { 0x00000c0c, 0xe1000001 }, /* GPIO2_CTRL1 */ > + { 0x00000c10, 0xe1000001 }, /* GPIO3_CTRL1 */ > + { 0x00000c14, 0xe1000001 }, /* GPIO4_CTRL1 */ > + { 0x00000c18, 0xe1000001 }, /* GPIO5_CTRL1 */ > + { 0x00000c1c, 0xe1000001 }, /* GPIO6_CTRL1 */ > + { 0x00000c20, 0xe1000001 }, /* GPIO7_CTRL1 */ > + { 0x00000c24, 0xe1000001 }, /* GPIO8_CTRL1 */ > + { 0x00000c28, 0xe1000001 }, /* GPIO9_CTRL1 */ > + { 0x00000c2c, 0xe1000001 }, /* GPIO10_CTRL1 */ > + { 0x00000c30, 0xe1000001 }, /* GPIO11_CTRL1 */ > + { 0x00000c34, 0xe1000001 }, /* GPIO12_CTRL1 */ > + { 0x00000c38, 0xe1000001 }, /* GPIO13_CTRL1 */ > + { 0x00000c3c, 0xe1000001 }, /* GPIO14_CTRL1 */ > + { 0x00000c40, 0xe1000001 }, /* GPIO15_CTRL1 */ > + { 0x00000c44, 0xe1000001 }, /* GPIO16_CTRL1 */ > + { 0x00001020, 0x00000000 }, /* OUTPUT_SYS_CLK */ > + { 0x00001044, 0x0005000f }, /* AUXPDM_CTRL */ > + { 0x0000105c, 0x00000000 }, /* AUXPDM_CTRL2 */ > + { 0x00001400, 0x00000002 }, /* CLOCK32K */ > + { 0x00001404, 0x00000404 }, /* SYSTEM_CLOCK1 */ > + { 0x00001420, 0x00000003 }, /* SAMPLE_RATE1 */ > + { 0x00001424, 0x00000003 }, /* SAMPLE_RATE2 */ > + { 0x00001428, 0x00000003 }, /* SAMPLE_RATE3 */ > + { 0x0000142c, 0x00000003 }, /* SAMPLE_RATE4 */ > + { 0x00001c00, 0x00000002 }, /* FLL1_CONTROL1 */ > + { 0x00001c04, 0x88203004 }, /* FLL1_CONTROL2 */ > + { 0x00001c08, 0x00000000 }, /* FLL1_CONTROL3 */ > + { 0x00001c0c, 0x21f05001 }, /* FLL1_CONTROL4 */ > + { 0x00001ca0, 0x00000c04 }, /* FLL1_GPIO_CLOCK */ > + { 0x00002000, 0x00000006 }, /* CHARGE_PUMP1 */ > + { 0x00002408, 0x000003e4 }, /* LDO2_CTRL1 */ > + { 0x00002410, 0x000000e6 }, /* MICBIAS_CTRL1 */ > + { 0x00002418, 0x00000222 }, /* MICBIAS_CTRL5 */ > + { 0x00002710, 0x00004600 }, /* IRQ1_CTRL_AOD */ > + { 0x00004000, 0x00000000 }, /* INPUT_CONTROL */ > + { 0x00004008, 0x00000400 }, /* INPUT_RATE_CONTROL */ > + { 0x0000400c, 0x00000000 }, /* INPUT_CONTROL2 */ > + { 0x00004020, 0x00050020 }, /* INPUT1_CONTROL1 */ > + { 0x00004024, 0x00000000 }, /* IN1L_CONTROL1 */ > + { 0x00004028, 0x10800080 }, /* IN1L_CONTROL2 */ > + { 0x00004044, 0x00000000 }, /* IN1R_CONTROL1 */ > + { 0x00004048, 0x10800080 }, /* IN1R_CONTROL2 */ > + { 0x00004060, 0x00050020 }, /* INPUT2_CONTROL1 */ > + { 0x00004064, 0x00000000 }, /* IN2L_CONTROL1 */ > + { 0x00004068, 0x10800000 }, /* IN2L_CONTROL2 */ > + { 0x00004084, 0x00000000 }, /* IN2R_CONTROL1 */ > + { 0x00004088, 0x10800000 }, /* IN2R_CONTROL2 */ > + { 0x00004244, 0x00000002 }, /* INPUT_HPF_CONTROL */ > + { 0x00004248, 0x00000022 }, /* INPUT_VOL_CONTROL */ > + { 0x00004300, 0x00000000 }, /* AUXPDM_CONTROL1 */ > + { 0x00004304, 0x00000000 }, /* AUXPDM_CONTROL2 */ > + { 0x00004308, 0x00010008 }, /* AUXPDM1_CONTROL1 */ > + { 0x00004310, 0x00010008 }, /* AUXPDM2_CONTROL1 */ > + { 0x00004688, 0x00000000 }, /* ADC1L_ANA_CONTROL1 */ > + { 0x0000468c, 0x00000000 }, /* ADC1R_ANA_CONTROL1 */ > + { 0x00006000, 0x00000000 }, /* ASP1_ENABLES1 */ > + { 0x00006004, 0x00000028 }, /* ASP1_CONTROL1 */ > + { 0x00006008, 0x18180200 }, /* ASP1_CONTROL2 */ > + { 0x0000600c, 0x00000002 }, /* ASP1_CONTROL3 */ > + { 0x00006010, 0x03020100 }, /* ASP1_FRAME_CONTROL1 */ > + { 0x00006014, 0x07060504 }, /* ASP1_FRAME_CONTROL2 */ > + { 0x00006020, 0x03020100 }, /* ASP1_FRAME_CONTROL5 */ > + { 0x00006024, 0x07060504 }, /* ASP1_FRAME_CONTROL6 */ > + { 0x00006030, 0x00000020 }, /* ASP1_DATA_CONTROL1 */ > + { 0x00006040, 0x00000020 }, /* ASP1_DATA_CONTROL5 */ > + { 0x00006080, 0x00000000 }, /* ASP2_ENABLES1 */ > + { 0x00006084, 0x00000028 }, /* ASP2_CONTROL1 */ > + { 0x00006088, 0x18180200 }, /* ASP2_CONTROL2 */ > + { 0x0000608c, 0x00000002 }, /* ASP2_CONTROL3 */ > + { 0x00006090, 0x03020100 }, /* ASP2_FRAME_CONTROL1 */ > + { 0x000060a0, 0x03020100 }, /* ASP2_FRAME_CONTROL5 */ > + { 0x000060b0, 0x00000020 }, /* ASP2_DATA_CONTROL1 */ > + { 0x000060c0, 0x00000020 }, /* ASP2_DATA_CONTROL5 */ > + { 0x00008200, 0x00800000 }, /* ASP1TX1_INPUT1 */ > + { 0x00008204, 0x00800000 }, /* ASP1TX1_INPUT2 */ > + { 0x00008208, 0x00800000 }, /* ASP1TX1_INPUT3 */ > + { 0x0000820c, 0x00800000 }, /* ASP1TX1_INPUT4 */ > + { 0x00008210, 0x00800000 }, /* ASP1TX2_INPUT1 */ > + { 0x00008214, 0x00800000 }, /* ASP1TX2_INPUT2 */ > + { 0x00008218, 0x00800000 }, /* ASP1TX2_INPUT3 */ > + { 0x0000821c, 0x00800000 }, /* ASP1TX2_INPUT4 */ > + { 0x00008220, 0x00800000 }, /* ASP1TX3_INPUT1 */ > + { 0x00008224, 0x00800000 }, /* ASP1TX3_INPUT2 */ > + { 0x00008228, 0x00800000 }, /* ASP1TX3_INPUT3 */ > + { 0x0000822c, 0x00800000 }, /* ASP1TX3_INPUT4 */ > + { 0x00008230, 0x00800000 }, /* ASP1TX4_INPUT1 */ > + { 0x00008234, 0x00800000 }, /* ASP1TX4_INPUT2 */ > + { 0x00008238, 0x00800000 }, /* ASP1TX4_INPUT3 */ > + { 0x0000823c, 0x00800000 }, /* ASP1TX4_INPUT4 */ > + { 0x00008240, 0x00800000 }, /* ASP1TX5_INPUT1 */ > + { 0x00008244, 0x00800000 }, /* ASP1TX5_INPUT2 */ > + { 0x00008248, 0x00800000 }, /* ASP1TX5_INPUT3 */ > + { 0x0000824c, 0x00800000 }, /* ASP1TX5_INPUT4 */ > + { 0x00008250, 0x00800000 }, /* ASP1TX6_INPUT1 */ > + { 0x00008254, 0x00800000 }, /* ASP1TX6_INPUT2 */ > + { 0x00008258, 0x00800000 }, /* ASP1TX6_INPUT3 */ > + { 0x0000825c, 0x00800000 }, /* ASP1TX6_INPUT4 */ > + { 0x00008260, 0x00800000 }, /* ASP1TX7_INPUT1 */ > + { 0x00008264, 0x00800000 }, /* ASP1TX7_INPUT2 */ > + { 0x00008268, 0x00800000 }, /* ASP1TX7_INPUT3 */ > + { 0x0000826c, 0x00800000 }, /* ASP1TX7_INPUT4 */ > + { 0x00008270, 0x00800000 }, /* ASP1TX8_INPUT1 */ > + { 0x00008274, 0x00800000 }, /* ASP1TX8_INPUT2 */ > + { 0x00008278, 0x00800000 }, /* ASP1TX8_INPUT3 */ > + { 0x0000827c, 0x00800000 }, /* ASP1TX8_INPUT4 */ > + { 0x00008300, 0x00800000 }, /* ASP2TX1_INPUT1 */ > + { 0x00008304, 0x00800000 }, /* ASP2TX1_INPUT2 */ > + { 0x00008308, 0x00800000 }, /* ASP2TX1_INPUT3 */ > + { 0x0000830c, 0x00800000 }, /* ASP2TX1_INPUT4 */ > + { 0x00008310, 0x00800000 }, /* ASP2TX2_INPUT1 */ > + { 0x00008314, 0x00800000 }, /* ASP2TX2_INPUT2 */ > + { 0x00008318, 0x00800000 }, /* ASP2TX2_INPUT3 */ > + { 0x0000831c, 0x00800000 }, /* ASP2TX2_INPUT4 */ > + { 0x00008320, 0x00800000 }, /* ASP2TX3_INPUT1 */ > + { 0x00008324, 0x00800000 }, /* ASP2TX3_INPUT2 */ > + { 0x00008328, 0x00800000 }, /* ASP2TX3_INPUT3 */ > + { 0x0000832c, 0x00800000 }, /* ASP2TX3_INPUT4 */ > + { 0x00008330, 0x00800000 }, /* ASP2TX4_INPUT1 */ > + { 0x00008334, 0x00800000 }, /* ASP2TX4_INPUT2 */ > + { 0x00008338, 0x00800000 }, /* ASP2TX4_INPUT3 */ > + { 0x0000833c, 0x00800000 }, /* ASP2TX4_INPUT4 */ > + { 0x00008980, 0x00000000 }, /* ISRC1INT1_INPUT1 */ > + { 0x00008990, 0x00000000 }, /* ISRC1INT2_INPUT1 */ > + { 0x000089a0, 0x00000000 }, /* ISRC1INT3_INPUT1 */ > + { 0x000089b0, 0x00000000 }, /* ISRC1INT4_INPUT1 */ > + { 0x000089c0, 0x00000000 }, /* ISRC1DEC1_INPUT1 */ > + { 0x000089d0, 0x00000000 }, /* ISRC1DEC2_INPUT1 */ > + { 0x000089e0, 0x00000000 }, /* ISRC1DEC3_INPUT1 */ > + { 0x000089f0, 0x00000000 }, /* ISRC1DEC4_INPUT1 */ > + { 0x00008a00, 0x00000000 }, /* ISRC2INT1_INPUT1 */ > + { 0x00008a10, 0x00000000 }, /* ISRC2INT2_INPUT1 */ > + { 0x00008a40, 0x00000000 }, /* ISRC2DEC1_INPUT1 */ > + { 0x00008a50, 0x00000000 }, /* ISRC2DEC2_INPUT1 */ > + { 0x00008a80, 0x00000000 }, /* ISRC3INT1_INPUT1 */ > + { 0x00008a90, 0x00000000 }, /* ISRC3INT2_INPUT1 */ > + { 0x00008ac0, 0x00000000 }, /* ISRC3DEC1_INPUT1 */ > + { 0x00008ad0, 0x00000000 }, /* ISRC3DEC2_INPUT1 */ > + { 0x00008b80, 0x00800000 }, /* EQ1_INPUT1 */ > + { 0x00008b84, 0x00800000 }, /* EQ1_INPUT2 */ > + { 0x00008b88, 0x00800000 }, /* EQ1_INPUT3 */ > + { 0x00008b8c, 0x00800000 }, /* EQ1_INPUT4 */ > + { 0x00008b90, 0x00800000 }, /* EQ2_INPUT1 */ > + { 0x00008b94, 0x00800000 }, /* EQ2_INPUT2 */ > + { 0x00008b98, 0x00800000 }, /* EQ2_INPUT3 */ > + { 0x00008b9c, 0x00800000 }, /* EQ2_INPUT4 */ > + { 0x00008ba0, 0x00800000 }, /* EQ3_INPUT1 */ > + { 0x00008ba4, 0x00800000 }, /* EQ3_INPUT2 */ > + { 0x00008ba8, 0x00800000 }, /* EQ3_INPUT3 */ > + { 0x00008bac, 0x00800000 }, /* EQ3_INPUT4 */ > + { 0x00008bb0, 0x00800000 }, /* EQ4_INPUT1 */ > + { 0x00008bb4, 0x00800000 }, /* EQ4_INPUT2 */ > + { 0x00008bb8, 0x00800000 }, /* EQ4_INPUT3 */ > + { 0x00008bbc, 0x00800000 }, /* EQ4_INPUT4 */ > + { 0x00008c00, 0x00800000 }, /* DRC1L_INPUT1 */ > + { 0x00008c04, 0x00800000 }, /* DRC1L_INPUT2 */ > + { 0x00008c08, 0x00800000 }, /* DRC1L_INPUT3 */ > + { 0x00008c0c, 0x00800000 }, /* DRC1L_INPUT4 */ > + { 0x00008c10, 0x00800000 }, /* DRC1R_INPUT1 */ > + { 0x00008c14, 0x00800000 }, /* DRC1R_INPUT2 */ > + { 0x00008c18, 0x00800000 }, /* DRC1R_INPUT3 */ > + { 0x00008c1c, 0x00800000 }, /* DRC1R_INPUT4 */ > + { 0x00008c20, 0x00800000 }, /* DRC2L_INPUT1 */ > + { 0x00008c24, 0x00800000 }, /* DRC2L_INPUT2 */ > + { 0x00008c28, 0x00800000 }, /* DRC2L_INPUT3 */ > + { 0x00008c2c, 0x00800000 }, /* DRC2L_INPUT4 */ > + { 0x00008c30, 0x00800000 }, /* DRC2R_INPUT1 */ > + { 0x00008c34, 0x00800000 }, /* DRC2R_INPUT2 */ > + { 0x00008c38, 0x00800000 }, /* DRC2R_INPUT3 */ > + { 0x00008c3c, 0x00800000 }, /* DRC2R_INPUT4 */ > + { 0x00008c80, 0x00800000 }, /* LHPF1_INPUT1 */ > + { 0x00008c84, 0x00800000 }, /* LHPF1_INPUT2 */ > + { 0x00008c88, 0x00800000 }, /* LHPF1_INPUT3 */ > + { 0x00008c8c, 0x00800000 }, /* LHPF1_INPUT4 */ > + { 0x00008c90, 0x00800000 }, /* LHPF2_INPUT1 */ > + { 0x00008c94, 0x00800000 }, /* LHPF2_INPUT2 */ > + { 0x00008c98, 0x00800000 }, /* LHPF2_INPUT3 */ > + { 0x00008c9c, 0x00800000 }, /* LHPF2_INPUT4 */ > + { 0x00008ca0, 0x00800000 }, /* LHPF3_INPUT1 */ > + { 0x00008ca4, 0x00800000 }, /* LHPF3_INPUT2 */ > + { 0x00008ca8, 0x00800000 }, /* LHPF3_INPUT3 */ > + { 0x00008cac, 0x00800000 }, /* LHPF3_INPUT4 */ > + { 0x00008cb0, 0x00800000 }, /* LHPF4_INPUT1 */ > + { 0x00008cb4, 0x00800000 }, /* LHPF4_INPUT2 */ > + { 0x00008cb8, 0x00800000 }, /* LHPF4_INPUT3 */ > + { 0x00008cbc, 0x00800000 }, /* LHPF4_INPUT4 */ > + { 0x00009000, 0x00800000 }, /* DSP1RX1_INPUT1 */ > + { 0x00009004, 0x00800000 }, /* DSP1RX1_INPUT2 */ > + { 0x00009008, 0x00800000 }, /* DSP1RX1_INPUT3 */ > + { 0x0000900c, 0x00800000 }, /* DSP1RX1_INPUT4 */ > + { 0x00009010, 0x00800000 }, /* DSP1RX2_INPUT1 */ > + { 0x00009014, 0x00800000 }, /* DSP1RX2_INPUT2 */ > + { 0x00009018, 0x00800000 }, /* DSP1RX2_INPUT3 */ > + { 0x0000901c, 0x00800000 }, /* DSP1RX2_INPUT4 */ > + { 0x00009020, 0x00800000 }, /* DSP1RX3_INPUT1 */ > + { 0x00009024, 0x00800000 }, /* DSP1RX3_INPUT2 */ > + { 0x00009028, 0x00800000 }, /* DSP1RX3_INPUT3 */ > + { 0x0000902c, 0x00800000 }, /* DSP1RX3_INPUT4 */ > + { 0x00009030, 0x00800000 }, /* DSP1RX4_INPUT1 */ > + { 0x00009034, 0x00800000 }, /* DSP1RX4_INPUT2 */ > + { 0x00009038, 0x00800000 }, /* DSP1RX4_INPUT3 */ > + { 0x0000903c, 0x00800000 }, /* DSP1RX4_INPUT4 */ > + { 0x00009040, 0x00800000 }, /* DSP1RX5_INPUT1 */ > + { 0x00009044, 0x00800000 }, /* DSP1RX5_INPUT2 */ > + { 0x00009048, 0x00800000 }, /* DSP1RX5_INPUT3 */ > + { 0x0000904c, 0x00800000 }, /* DSP1RX5_INPUT4 */ > + { 0x00009050, 0x00800000 }, /* DSP1RX6_INPUT1 */ > + { 0x00009054, 0x00800000 }, /* DSP1RX6_INPUT2 */ > + { 0x00009058, 0x00800000 }, /* DSP1RX6_INPUT3 */ > + { 0x0000905c, 0x00800000 }, /* DSP1RX6_INPUT4 */ > + { 0x00009060, 0x00800000 }, /* DSP1RX7_INPUT1 */ > + { 0x00009064, 0x00800000 }, /* DSP1RX7_INPUT2 */ > + { 0x00009068, 0x00800000 }, /* DSP1RX7_INPUT3 */ > + { 0x0000906c, 0x00800000 }, /* DSP1RX7_INPUT4 */ > + { 0x00009070, 0x00800000 }, /* DSP1RX8_INPUT1 */ > + { 0x00009074, 0x00800000 }, /* DSP1RX8_INPUT2 */ > + { 0x00009078, 0x00800000 }, /* DSP1RX8_INPUT3 */ > + { 0x0000907c, 0x00800000 }, /* DSP1RX8_INPUT4 */ > + { 0x0000a400, 0x00000000 }, /* ISRC1_CONTROL1 */ > + { 0x0000a404, 0x00000000 }, /* ISRC1_CONTROL2 */ > + { 0x0000a510, 0x00000000 }, /* ISRC2_CONTROL1 */ > + { 0x0000a514, 0x00000000 }, /* ISRC2_CONTROL2 */ > + { 0x0000a620, 0x00000000 }, /* ISRC3_CONTROL1 */ > + { 0x0000a624, 0x00000000 }, /* ISRC3_CONTROL2 */ > + { 0x0000a800, 0x00000000 }, /* FX_SAMPLE_RATE */ > + { 0x0000a808, 0x00000000 }, /* EQ_CONTROL1 */ > + { 0x0000a80c, 0x00000000 }, /* EQ_CONTROL2 */ > + { 0x0000a810, 0x0c0c0c0c }, /* EQ1_GAIN1 */ > + { 0x0000a814, 0x0000000c }, /* EQ1_GAIN2 */ > + { 0x0000a818, 0x03fe0fc8 }, /* EQ1_BAND1_COEFF1 */ > + { 0x0000a81c, 0x00000b75 }, /* EQ1_BAND1_COEFF2 */ > + { 0x0000a820, 0x000000e0 }, /* EQ1_BAND1_PG */ > + { 0x0000a824, 0xf1361ec4 }, /* EQ1_BAND2_COEFF1 */ > + { 0x0000a828, 0x00000409 }, /* EQ1_BAND2_COEFF2 */ > + { 0x0000a82c, 0x000004cc }, /* EQ1_BAND2_PG */ > + { 0x0000a830, 0xf3371c9b }, /* EQ1_BAND3_COEFF1 */ > + { 0x0000a834, 0x0000040b }, /* EQ1_BAND3_COEFF2 */ > + { 0x0000a838, 0x00000cbb }, /* EQ1_BAND3_PG */ > + { 0x0000a83c, 0xf7d916f8 }, /* EQ1_BAND4_COEFF1 */ > + { 0x0000a840, 0x0000040a }, /* EQ1_BAND4_COEFF2 */ > + { 0x0000a844, 0x00001f14 }, /* EQ1_BAND4_PG */ > + { 0x0000a848, 0x0563058c }, /* EQ1_BAND5_COEFF1 */ > + { 0x0000a84c, 0x00000000 }, /* EQ1_BAND5_COEFF1 + 4 */ > + { 0x0000a850, 0x00004000 }, /* EQ1_BAND5_PG */ > + { 0x0000a854, 0x0c0c0c0c }, /* EQ2_GAIN1 */ > + { 0x0000a858, 0x0000000c }, /* EQ2_GAIN2 */ > + { 0x0000a85c, 0x03fe0fc8 }, /* EQ2_BAND1_COEFF1 */ > + { 0x0000a860, 0x00000b75 }, /* EQ2_BAND1_COEFF2 */ > + { 0x0000a864, 0x000000e0 }, /* EQ2_BAND1_PG */ > + { 0x0000a868, 0xf1361ec4 }, /* EQ2_BAND2_COEFF1 */ > + { 0x0000a86c, 0x00000409 }, /* EQ2_BAND2_COEFF2 */ > + { 0x0000a870, 0x000004cc }, /* EQ2_BAND2_PG */ > + { 0x0000a874, 0xf3371c9b }, /* EQ2_BAND3_COEFF1 */ > + { 0x0000a878, 0x0000040b }, /* EQ2_BAND3_COEFF2 */ > + { 0x0000a87c, 0x00000cbb }, /* EQ2_BAND3_PG */ > + { 0x0000a880, 0xf7d916f8 }, /* EQ2_BAND4_COEFF1 */ > + { 0x0000a884, 0x0000040a }, /* EQ2_BAND4_COEFF2 */ > + { 0x0000a888, 0x00001f14 }, /* EQ2_BAND4_PG */ > + { 0x0000a88c, 0x0563058c }, /* EQ2_BAND5_COEFF1 */ > + { 0x0000a890, 0x00000000 }, /* EQ2_BAND5_COEFF1 + 4 */ > + { 0x0000a894, 0x00004000 }, /* EQ2_BAND5_PG */ > + { 0x0000a898, 0x0c0c0c0c }, /* EQ3_GAIN1 */ > + { 0x0000a89c, 0x0000000c }, /* EQ3_GAIN2 */ > + { 0x0000a8a0, 0x03fe0fc8 }, /* EQ3_BAND1_COEFF1 */ > + { 0x0000a8a4, 0x00000b75 }, /* EQ3_BAND1_COEFF2 */ > + { 0x0000a8a8, 0x000000e0 }, /* EQ3_BAND1_PG */ > + { 0x0000a8ac, 0xf1361ec4 }, /* EQ3_BAND2_COEFF1 */ > + { 0x0000a8b0, 0x00000409 }, /* EQ3_BAND2_COEFF2 */ > + { 0x0000a8b4, 0x000004cc }, /* EQ3_BAND2_PG */ > + { 0x0000a8b8, 0xf3371c9b }, /* EQ3_BAND3_COEFF1 */ > + { 0x0000a8bc, 0x0000040b }, /* EQ3_BAND3_COEFF2 */ > + { 0x0000a8c0, 0x00000cbb }, /* EQ3_BAND3_PG */ > + { 0x0000a8c4, 0xf7d916f8 }, /* EQ3_BAND4_COEFF1 */ > + { 0x0000a8c8, 0x0000040a }, /* EQ3_BAND4_COEFF2 */ > + { 0x0000a8cc, 0x00001f14 }, /* EQ3_BAND4_PG */ > + { 0x0000a8d0, 0x0563058c }, /* EQ3_BAND5_COEFF1 */ > + { 0x0000a8d4, 0x00000000 }, /* EQ3_BAND5_COEFF1 + 4 */ > + { 0x0000a8d8, 0x00004000 }, /* EQ3_BAND5_PG */ > + { 0x0000a8dc, 0x0c0c0c0c }, /* EQ4_GAIN1 */ > + { 0x0000a8e0, 0x0000000c }, /* EQ4_GAIN2 */ > + { 0x0000a8e4, 0x03fe0fc8 }, /* EQ4_BAND1_COEFF1 */ > + { 0x0000a8e8, 0x00000b75 }, /* EQ4_BAND1_COEFF2 */ > + { 0x0000a8ec, 0x000000e0 }, /* EQ4_BAND1_PG */ > + { 0x0000a8f0, 0xf1361ec4 }, /* EQ4_BAND2_COEFF1 */ > + { 0x0000a8f4, 0x00000409 }, /* EQ4_BAND2_COEFF2 */ > + { 0x0000a8f8, 0x000004cc }, /* EQ4_BAND2_PG */ > + { 0x0000a8fc, 0xf3371c9b }, /* EQ4_BAND3_COEFF1 */ > + { 0x0000a900, 0x0000040b }, /* EQ4_BAND3_COEFF2 */ > + { 0x0000a904, 0x00000cbb }, /* EQ4_BAND3_PG */ > + { 0x0000a908, 0xf7d916f8 }, /* EQ4_BAND4_COEFF1 */ > + { 0x0000a90c, 0x0000040a }, /* EQ4_BAND4_COEFF2 */ > + { 0x0000a910, 0x00001f14 }, /* EQ4_BAND4_PG */ > + { 0x0000a914, 0x0563058c }, /* EQ4_BAND5_COEFF1 */ > + { 0x0000a918, 0x00000000 }, /* EQ4_BAND5_COEFF1 + 4 */ > + { 0x0000a91c, 0x00004000 }, /* EQ4_BAND5_PG */ > + { 0x0000aa30, 0x00000000 }, /* LHPF_CONTROL1 */ > + { 0x0000aa34, 0x00000000 }, /* LHPF_CONTROL2 */ > + { 0x0000aa38, 0x00000000 }, /* LHPF1_COEFF */ > + { 0x0000aa3c, 0x00000000 }, /* LHPF2_COEFF */ > + { 0x0000aa40, 0x00000000 }, /* LHPF3_COEFF */ > + { 0x0000aa44, 0x00000000 }, /* LHPF4_COEFF */ > + { 0x0000ab00, 0x00000000 }, /* DRC1_CONTROL1 */ > + { 0x0000ab04, 0x49130018 }, /* DRC1_CONTROL2 */ > + { 0x0000ab08, 0x00000018 }, /* DRC1_CONTROL3 */ > + { 0x0000ab0c, 0x00000000 }, /* DRC1_CONTROL4 */ > + { 0x0000ab14, 0x00000000 }, /* DRC2_CONTROL1 */ > + { 0x0000ab18, 0x49130018 }, /* DRC2_CONTROL2 */ > + { 0x0000ab1c, 0x00000018 }, /* DRC2_CONTROL3 */ > + { 0x0000ab20, 0x00000000 }, /* DRC2_CONTROL4 */ > + { 0x0000b000, 0x00000000 }, /* TONE_GENERATOR1 */ > + { 0x0000b004, 0x00100000 }, /* TONE_GENERATOR2 */ > + { 0x0000b400, 0x00000000 }, /* COMFORT_NOISE_GENERATOR */ > + { 0x0000b800, 0x00000000 }, /* US_CONTROL */ > + { 0x0000b804, 0x00002020 }, /* US1_CONTROL */ > + { 0x0000b808, 0x00000000 }, /* US1_DET_CONTROL */ > + { 0x0000b814, 0x00002020 }, /* US2_CONTROL */ > + { 0x0000b818, 0x00000000 }, /* US2_DET_CONTROL */ > + { 0x00018110, 0xffffffff }, /* IRQ1_MASK_1 */ > + { 0x00018114, 0xfffffff7 }, /* IRQ1_MASK_2 */ > + { 0x00018118, 0xffffffff }, /* IRQ1_MASK_3 */ > + { 0x0001811c, 0xffffffff }, /* IRQ1_MASK_4 */ > + { 0x00018120, 0xffffffff }, /* IRQ1_MASK_5 */ > + { 0x00018124, 0xffffffff }, /* IRQ1_MASK_6 */ > + { 0x00018128, 0xffffffff }, /* IRQ1_MASK_7 */ > + { 0x0001812c, 0xffffffff }, /* IRQ1_MASK_8 */ > + { 0x00018130, 0xffffffff }, /* IRQ1_MASK_9 */ > + { 0x00018134, 0xffffffff }, /* IRQ1_MASK_10 */ > + { 0x00018138, 0xffffffff }, /* IRQ1_MASK_11 */ > +}; > + > +static bool cs48l32_readable_register(struct device *dev, unsigned int reg) > +{ > + switch (reg) { > + case CS48L32_DEVID: > + case CS48L32_REVID: > + case CS48L32_OTPID: > + case CS48L32_SFT_RESET: > + case CS48L32_CTRL_IF_DEBUG3: > + case CS48L32_MCU_CTRL1: > + case CS48L32_GPIO1_CTRL1 ... CS48L32_GPIO16_CTRL1: > + case CS48L32_OUTPUT_SYS_CLK: > + case CS48L32_AUXPDM_CTRL: > + case CS48L32_AUXPDM_CTRL2: > + case CS48L32_CLOCK32K: > + case CS48L32_SYSTEM_CLOCK1 ... CS48L32_SYSTEM_CLOCK2: > + case CS48L32_SAMPLE_RATE1 ... CS48L32_SAMPLE_RATE4: > + case CS48L32_FLL1_CONTROL1 ... CS48L32_FLL1_GPIO_CLOCK: > + case CS48L32_CHARGE_PUMP1: > + case CS48L32_LDO2_CTRL1: > + case CS48L32_MICBIAS_CTRL1: > + case CS48L32_MICBIAS_CTRL5: > + case CS48L32_IRQ1_CTRL_AOD: > + case CS48L32_INPUT_CONTROL: > + case CS48L32_INPUT_STATUS: > + case CS48L32_INPUT_RATE_CONTROL: > + case CS48L32_INPUT_CONTROL2: > + case CS48L32_INPUT_CONTROL3: > + case CS48L32_INPUT1_CONTROL1: > + case CS48L32_IN1L_CONTROL1 ... CS48L32_IN1L_CONTROL2: > + case CS48L32_IN1R_CONTROL1 ... CS48L32_IN1R_CONTROL2: > + case CS48L32_INPUT2_CONTROL1: > + case CS48L32_IN2L_CONTROL1 ... CS48L32_IN2L_CONTROL2: > + case CS48L32_IN2R_CONTROL1 ... CS48L32_IN2R_CONTROL2: > + case CS48L32_INPUT_HPF_CONTROL: > + case CS48L32_INPUT_VOL_CONTROL: > + case CS48L32_AUXPDM_CONTROL1: > + case CS48L32_AUXPDM_CONTROL2: > + case CS48L32_AUXPDM1_CONTROL1: > + case CS48L32_AUXPDM2_CONTROL1: > + case CS48L32_ADC1L_ANA_CONTROL1: > + case CS48L32_ADC1R_ANA_CONTROL1: > + case CS48L32_ASP1_ENABLES1 ... CS48L32_ASP1_DATA_CONTROL5: > + case CS48L32_ASP2_ENABLES1 ... CS48L32_ASP2_DATA_CONTROL5: > + case CS48L32_ASP1TX1_INPUT1 ... CS48L32_ASP1TX8_INPUT4: > + case CS48L32_ASP2TX1_INPUT1 ... CS48L32_ASP2TX4_INPUT4: > + case CS48L32_ISRC1INT1_INPUT1 ... CS48L32_ISRC1DEC4_INPUT1: > + case CS48L32_ISRC2INT1_INPUT1 ... CS48L32_ISRC2DEC2_INPUT1: > + case CS48L32_ISRC3INT1_INPUT1 ... CS48L32_ISRC3DEC2_INPUT1: > + case CS48L32_EQ1_INPUT1 ... CS48L32_EQ4_INPUT4: > + case CS48L32_DRC1L_INPUT1 ... CS48L32_DRC1R_INPUT4: > + case CS48L32_DRC2L_INPUT1 ... CS48L32_DRC2R_INPUT4: > + case CS48L32_LHPF1_INPUT1 ... CS48L32_LHPF1_INPUT4: > + case CS48L32_LHPF2_INPUT1 ... CS48L32_LHPF2_INPUT4: > + case CS48L32_LHPF3_INPUT1 ... CS48L32_LHPF3_INPUT4: > + case CS48L32_LHPF4_INPUT1 ... CS48L32_LHPF4_INPUT4: > + case CS48L32_DSP1RX1_INPUT1 ... CS48L32_DSP1RX8_INPUT4: > + case CS48L32_ISRC1_CONTROL1 ... CS48L32_ISRC1_CONTROL2: > + case CS48L32_ISRC2_CONTROL1 ... CS48L32_ISRC2_CONTROL2: > + case CS48L32_ISRC3_CONTROL1 ... CS48L32_ISRC3_CONTROL2: > + case CS48L32_FX_SAMPLE_RATE: > + case CS48L32_EQ_CONTROL1 ... CS48L32_EQ_CONTROL2: > + case CS48L32_EQ1_GAIN1 ... CS48L32_EQ1_BAND5_PG: > + case CS48L32_EQ2_GAIN1 ... CS48L32_EQ2_BAND5_PG: > + case CS48L32_EQ3_GAIN1 ... CS48L32_EQ3_BAND5_PG: > + case CS48L32_EQ4_GAIN1 ... CS48L32_EQ4_BAND5_PG: > + case CS48L32_LHPF_CONTROL1 ... CS48L32_LHPF_CONTROL2: > + case CS48L32_LHPF1_COEFF ... CS48L32_LHPF4_COEFF: > + case CS48L32_DRC1_CONTROL1 ... CS48L32_DRC1_CONTROL4: > + case CS48L32_DRC2_CONTROL1 ... CS48L32_DRC2_CONTROL4: > + case CS48L32_TONE_GENERATOR1 ... CS48L32_TONE_GENERATOR2: > + case CS48L32_COMFORT_NOISE_GENERATOR: > + case CS48L32_US_CONTROL: > + case CS48L32_US1_CONTROL: > + case CS48L32_US1_DET_CONTROL: > + case CS48L32_US2_CONTROL: > + case CS48L32_US2_DET_CONTROL: > + case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24: > + case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8: > + case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7: > + case CS48L32_IRQ1_STATUS: > + case CS48L32_IRQ1_EINT_1 ... CS48L32_IRQ1_EINT_11: > + case CS48L32_IRQ1_STS_1 ... CS48L32_IRQ1_STS_11: > + case CS48L32_IRQ1_MASK_1 ... CS48L32_IRQ1_MASK_11: > + case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_147455: > + case CS48L32_DSP1_SYS_INFO_ID ... CS48L32_DSP1_AHBM_WINDOW_DEBUG_1: > + case CS48L32_DSP1_XMEM_UNPACKED24_0 ... CS48L32_DSP1_XMEM_UNPACKED24_196607: > + case CS48L32_DSP1_CLOCK_FREQ ... CS48L32_DSP1_SAMPLE_RATE_TX8: > + case CS48L32_DSP1_SCRATCH1 ... CS48L32_DSP1_SCRATCH4: > + case CS48L32_DSP1_CCM_CORE_CONTROL ... CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1: > + case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_49151: > + case CS48L32_DSP1_YMEM_UNPACKED24_0 ... CS48L32_DSP1_YMEM_UNPACKED24_65535: > + case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_71679: > + return true; > + default: > + return false; > + } > +} > + > +static bool cs48l32_volatile_register(struct device *dev, unsigned int reg) > +{ > + switch (reg) { > + case CS48L32_DEVID: > + case CS48L32_REVID: > + case CS48L32_OTPID: > + case CS48L32_SFT_RESET: > + case CS48L32_CTRL_IF_DEBUG3: > + case CS48L32_MCU_CTRL1: > + case CS48L32_SYSTEM_CLOCK2: > + case CS48L32_FLL1_CONTROL5: > + case CS48L32_FLL1_CONTROL6: > + case CS48L32_INPUT_STATUS: > + case CS48L32_INPUT_CONTROL3: > + case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24: > + case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8: > + case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7: > + case CS48L32_IRQ1_STATUS: > + case CS48L32_IRQ1_EINT_1 ... CS48L32_IRQ1_EINT_11: > + case CS48L32_IRQ1_STS_1 ... CS48L32_IRQ1_STS_11: > + case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_147455: > + case CS48L32_DSP1_SYS_INFO_ID ... CS48L32_DSP1_AHBM_WINDOW_DEBUG_1: > + case CS48L32_DSP1_XMEM_UNPACKED24_0 ... CS48L32_DSP1_XMEM_UNPACKED24_196607: > + case CS48L32_DSP1_CLOCK_FREQ ... CS48L32_DSP1_SAMPLE_RATE_TX8: > + case CS48L32_DSP1_SCRATCH1 ... CS48L32_DSP1_SCRATCH4: > + case CS48L32_DSP1_CCM_CORE_CONTROL ... CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1: > + case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_49151: > + case CS48L32_DSP1_YMEM_UNPACKED24_0 ... CS48L32_DSP1_YMEM_UNPACKED24_65535: > + case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_71679: > + return true; > + default: > + return false; > + } > +} > + > +/* > + * The bus bridge requires DSP packed memory registers to be accessed in > + * aligned block multiples. > + * Mark precious to prevent regmap debugfs causing an illegal bus transaction. > + */ > +static bool cs48l32_precious_register(struct device *dev, unsigned int reg) > +{ > + switch (reg) { > + case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_147455: > + case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_49151: > + case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_71679: > + return true; > + default: > + return false; > + } > +} > + > +static const struct regmap_config cs48l32_spi_regmap = { > + .name = "cs48l32", > + .reg_bits = 32, > + .reg_stride = 4, > + .pad_bits = 32, > + .val_bits = 32, > + .reg_format_endian = REGMAP_ENDIAN_BIG, > + .val_format_endian = REGMAP_ENDIAN_BIG, > + > + .max_register = CS48L32_DSP1_PMEM_71679, > + .readable_reg = &cs48l32_readable_register, > + .volatile_reg = &cs48l32_volatile_register, > + .precious_reg = &cs48l32_precious_register, > + > + .cache_type = REGCACHE_RBTREE, > + .reg_defaults = cs48l32_reg_default, > + .num_reg_defaults = ARRAY_SIZE(cs48l32_reg_default), > +}; > + > +int cs48l32_init_regmap(struct spi_device *spi, struct cs48l32_mfd *cs48l32) > +{ > + cs48l32->regmap = devm_regmap_init_spi(spi, &cs48l32_spi_regmap); > + if (IS_ERR(cs48l32->regmap)) > + return PTR_ERR(cs48l32->regmap); > + > + return 0; > +} > diff --git a/drivers/mfd/cs48l32.c b/drivers/mfd/cs48l32.c > new file mode 100644 > index 000000000000..9506a1e0560b > --- /dev/null > +++ b/drivers/mfd/cs48l32.c > @@ -0,0 +1,434 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * MFD for Cirrus Logic CS48L32 audio codec. The name MFD should be omitted. If you must, you can say 'core driver' or something. > + * Copyright (C) 2016-2018, 2020, 2022 Cirrus Logic, Inc. and > + * Cirrus Logic International Semiconductor Ltd. > + */ > + > +#include <linux/delay.h> > +#include <linux/err.h> > +#include <linux/gpio/consumer.h> > +#include <linux/mfd/core.h> > +#include <linux/mfd/cs48l32/core.h> > +#include <linux/mfd/cs48l32/registers.h> > +#include <linux/module.h> > +#include <linux/notifier.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/pinctrl/consumer.h> > +#include <linux/platform_device.h> > +#include <linux/pm_runtime.h> > +#include <linux/property.h> > +#include <linux/regmap.h> > +#include <linux/regulator/consumer.h> > +#include <linux/regulator/driver.h> > +#include <linux/regulator/machine.h> > +#include <linux/regulator/of_regulator.h> > +#include <linux/spi/spi.h> Could you review these include files please. Are they all utilised? > +#include "cs48l32.h" > + > +static const char * const cs48l32_core_supplies[] = { > + "VDD_A", > + "VDD_IO", > +}; > + > +static const char * const cs48l32_supplies[] = { > + "VOUT_MIC", > + "VDD_CP", > +}; > + > +static const struct mfd_cell cs48l32_devs[] = { > + { .name = "cs48l32-pinctrl", }, > + { .name = "cs48l32-irq", }, > + { .name = "cs48l32-micsupp", }, > + { > + .name = "cs48l32-codec", > + .parent_supplies = cs48l32_supplies, > + .num_parent_supplies = ARRAY_SIZE(cs48l32_supplies), > + }, > +}; > + > +static int cs48l32_wait_for_boot(struct cs48l32_mfd *cs48l32) > +{ > + unsigned int val; > + int i, ret; > + > + /* regmap_read_poll_timeout would fail on read errors so roll our own */ It would, why? Is it fixable? Has it been reported? > + for (i = 0; i < CS48L32_BOOT_TIMEOUT_MS; ++i) { > + val = 0; What happens if you don't initialise this? Why is that better than checking the return value? > + regmap_read(cs48l32->regmap, CS48L32_IRQ1_EINT_2, &val); > + if (val & CS48L32_BOOT_DONE_EINT1_MASK) > + break; > + > + usleep_range(1000, 2000); > + } > + if (i == CS48L32_BOOT_TIMEOUT_MS) { > + dev_err(cs48l32->dev, "BOOT_DONE timed out\n"); > + return -ETIMEDOUT; > + } > + > + ret = regmap_read(cs48l32->regmap, CS48L32_MCU_CTRL1, &val); > + if (ret) { > + dev_err(cs48l32->dev, "Failed to read MCU_CTRL1: %d\n", ret); > + return ret; > + } > + > + if (val & BIT(CS48L32_MCU_STS_SHIFT)) { > + dev_err(cs48l32->dev, "MCU boot failed\n"); > + return -EIO; > + } > + > + ret = regmap_set_bits(cs48l32->regmap, CS48L32_CTRL_IF_DEBUG3, CS48L32_SEEN_BOOT_DONE); > + if (ret) { > + dev_err(cs48l32->dev, "Failed to write CTRL_IF_DEBUG3: %d\n", ret); > + return ret; > + } > + > + pm_runtime_mark_last_busy(cs48l32->dev); > + > + return 0; > +} > + > +static int cs48l32_soft_reset(struct cs48l32_mfd *cs48l32) > +{ > + int ret; > + > + ret = regmap_write(cs48l32->regmap, CS48L32_SFT_RESET, CS48L32_SFT_RESET_MAGIC); > + if (ret != 0) { > + dev_err(cs48l32->dev, "Failed to write soft reset: %d\n", ret); > + return ret; > + } > + > + usleep_range(2000, 3000); > + > + return 0; > +} > + > +static void cs48l32_enable_hard_reset(struct cs48l32_mfd *cs48l32) > +{ > + if (cs48l32->reset_gpio) > + gpiod_set_value_cansleep(cs48l32->reset_gpio, 0); > +} > + > +static void cs48l32_disable_hard_reset(struct cs48l32_mfd *cs48l32) > +{ > + if (cs48l32->reset_gpio) { > + gpiod_set_value_cansleep(cs48l32->reset_gpio, 1); > + usleep_range(2000, 3000); > + } > +} > + > +static int __maybe_unused cs48l32_runtime_resume(struct device *dev) > +{ > + struct cs48l32_mfd *cs48l32 = dev_get_drvdata(dev); > + unsigned int val; > + int ret; > + > + dev_dbg(cs48l32->dev, "Leaving sleep mode\n"); > + > + ret = regulator_enable(cs48l32->vdd_d); > + if (ret) { > + dev_err(cs48l32->dev, "Failed to enable VDD_D: %d\n", ret); > + return ret; > + } > + > + usleep_range(2000, 3000); > + > + regcache_cache_only(cs48l32->regmap, false); > + > + /* Did it power down during suspend? */ > + ret = regmap_read(cs48l32->regmap, CS48L32_CTRL_IF_DEBUG3, &val); > + if ((ret == 0) && (val & CS48L32_SEEN_BOOT_DONE)) { > + dev_dbg(cs48l32->dev, "VDD_D didn't power off during suspend\n"); > + } else { > + ret = cs48l32_wait_for_boot(cs48l32); > + if (ret) > + goto err; > + > + /* Flag that the registers have reset to defaults */ > + regcache_mark_dirty(cs48l32->regmap); > + } > + > + ret = regcache_sync(cs48l32->regmap); > + if (ret) { > + dev_err(cs48l32->dev, "Failed to restore register cache\n"); > + goto err; > + } > + > + return 0; > + > +err: > + regcache_cache_only(cs48l32->regmap, true); > + regulator_disable(cs48l32->vdd_d); > + return ret; > +} > + > +static int __maybe_unused cs48l32_runtime_suspend(struct device *dev) > +{ > + struct cs48l32_mfd *cs48l32 = dev_get_drvdata(dev); > + > + dev_dbg(cs48l32->dev, "Entering sleep mode\n"); > + > + regcache_cache_only(cs48l32->regmap, true); > + regulator_disable(cs48l32->vdd_d); > + > + return 0; > +} > + > +static const struct dev_pm_ops cs48l32_pm_ops = { > + SET_RUNTIME_PM_OPS(cs48l32_runtime_suspend, cs48l32_runtime_resume, NULL) > +}; > + > +static const struct __maybe_unused of_device_id cs48l32_of_match[] = { > + { .compatible = "cirrus,cs48l31", }, > + { .compatible = "cirrus,cs48l32", }, > + { .compatible = "cirrus,cs48l33", }, > + {}, > +}; > + > +static int cs48l32_configure_clk32k(struct cs48l32_mfd *cs48l32) > +{ > + int ret = 0; > + > + ret = clk_prepare_enable(cs48l32->mclk1); > + if (ret) { > + dev_err(cs48l32->dev, "Failed to enable 32k clock: %d\n", ret); > + return ret; > + } > + > + ret = regmap_update_bits(cs48l32->regmap, CS48L32_CLOCK32K, > + CS48L32_CLK_32K_EN_MASK | CS48L32_CLK_32K_SRC_MASK, > + CS48L32_CLK_32K_EN_MASK | CS48L32_32K_MCLK1); > + if (ret) { > + dev_err(cs48l32->dev, "Failed to init 32k clock: %d\n", ret); > + clk_disable_unprepare(cs48l32->mclk1); > + return ret; > + } > + > + return 0; > +} > + > +static int cs48l32_get_clocks(struct cs48l32_mfd *cs48l32) > +{ > + cs48l32->mclk1 = devm_clk_get_optional(cs48l32->dev, "mclk1"); > + if (IS_ERR(cs48l32->mclk1)) > + return dev_err_probe(cs48l32->dev, PTR_ERR(cs48l32->mclk1), > + "Failed to get mclk1\n"); > + > + return 0; > +} > + > +static int cs48l32_get_reset_gpio(struct cs48l32_mfd *cs48l32) > +{ > + struct gpio_desc *reset; > + > + reset = devm_gpiod_get_optional(cs48l32->dev, "reset", GPIOD_OUT_LOW); > + if (IS_ERR(reset)) > + return dev_err_probe(cs48l32->dev, PTR_ERR(reset), "Failed to request /RESET\n"); > + > + /* > + * A hard reset is needed for full reset of the chip. We allow running > + * without hard reset only because it can be useful for early > + * prototyping and some debugging, but we need to warn it's not ideal. > + */ > + if (!reset) > + dev_warn(cs48l32->dev, "Running without reset GPIO is not recommended\n"); > + > + cs48l32->reset_gpio = reset; > + > + return 0; > +} > + > +static int cs48l32_spi_probe(struct spi_device *spi) > +{ > + struct device *dev = &spi->dev; > + struct cs48l32_mfd *cs48l32; Prefer if you didn't put 'mfd' in the name. This is more traditional: struct cs48l32 *ddata; > + unsigned int hwid, rev, otp_rev; > + int i, ret; > + > + cs48l32 = devm_kzalloc(&spi->dev, sizeof(*cs48l32), GFP_KERNEL); > + if (!cs48l32) > + return -ENOMEM; > + > + ret = cs48l32_init_regmap(spi, cs48l32); > + if (ret) > + return dev_err_probe(&spi->dev, ret, "Failed to allocate regmap\n"); > + > + cs48l32->dev = dev; > + cs48l32->irq = spi->irq; > + > + dev_set_drvdata(cs48l32->dev, cs48l32); > + > + BLOCKING_INIT_NOTIFIER_HEAD(&cs48l32->notifier); > + > + regcache_cache_only(cs48l32->regmap, true); > + > + ret = cs48l32_get_reset_gpio(cs48l32); > + if (ret) > + return ret; > + > + ret = cs48l32_get_clocks(cs48l32); > + if (ret) > + return ret; > + > + for (i = 0; i < ARRAY_SIZE(cs48l32_core_supplies); i++) > + cs48l32->core_supplies[i].supply = cs48l32_core_supplies[i]; > + > + cs48l32->num_core_supplies = ARRAY_SIZE(cs48l32_core_supplies); Set this before the for(), then use the variable instead of ARRAY_SIZE() again. > + ret = devm_regulator_bulk_get(dev, cs48l32->num_core_supplies, cs48l32->core_supplies); > + if (ret) > + return dev_err_probe(dev, ret, "Failed to request core supplies\n"); > + > + cs48l32->vdd_d = devm_regulator_get(cs48l32->dev, "VDD_D"); > + if (IS_ERR(cs48l32->vdd_d)) > + return dev_err_probe(dev, PTR_ERR(cs48l32->vdd_d), "Failed to request VDD_D\n"); > + > + ret = regulator_set_voltage(cs48l32->vdd_d, 1200000, 1200000); > + if (ret) > + return dev_err_probe(dev, ret, "Failed to request VDD_D=1.2v\n"); > + > + ret = regulator_bulk_enable(cs48l32->num_core_supplies, cs48l32->core_supplies); > + if (ret) > + return dev_err_probe(dev, ret, "Failed to enable core supplies\n"); > + > + ret = regulator_enable(cs48l32->vdd_d); > + if (ret) { > + dev_err(dev, "Failed to enable VDD_D: %d\n", ret); > + goto err_enable; > + } > + > + cs48l32_disable_hard_reset(cs48l32); > + > + regcache_cache_only(cs48l32->regmap, false); > + > + /* If we don't have a reset GPIO use a soft reset */ > + if (!cs48l32->reset_gpio) { > + ret = cs48l32_soft_reset(cs48l32); > + if (ret) > + goto err_reset; > + } > + > + ret = cs48l32_wait_for_boot(cs48l32); > + if (ret) { > + dev_err(cs48l32->dev, "Device failed initial boot: %d\n", ret); > + goto err_reset; > + } > + > + ret = regmap_read(cs48l32->regmap, CS48L32_DEVID, &hwid); > + if (ret) { > + dev_err(dev, "Failed to read ID register: %d\n", ret); > + goto err_reset; > + } > + hwid &= CS48L32_DEVID_MASK; > + > + switch (hwid) { > + case CS48L31_SILICON_ID: > + case CS48L32_SILICON_ID: > + case CS48L33_SILICON_ID: > + break; > + default: > + dev_err(cs48l32->dev, "Unknown device ID: %x\n", hwid); > + ret = -EINVAL; > + goto err_reset; > + } > + > + ret = regmap_read(cs48l32->regmap, CS48L32_REVID, &rev); > + if (ret) { > + dev_err(dev, "Failed to read revision register: %d\n", ret); > + goto err_reset; > + } > + rev &= CS48L32_AREVID_MASK | CS48L32_MTLREVID_MASK; > + > + ret = regmap_read(cs48l32->regmap, CS48L32_OTPID, &otp_rev); > + if (ret) { > + dev_err(dev, "Failed to read OTP revision register: %d\n", ret); > + goto err_reset; > + } > + otp_rev &= CS48L32_OTPID_MASK; > + > + cs48l32->part = hwid & 0xff; > + > + dev_info(dev, "CS48L%x revision %X%u.%u\n", cs48l32->part, > + rev >> CS48L32_AREVID_SHIFT, rev & CS48L32_MTLREVID_MASK, otp_rev); > + > + /* Apply hardware patch */ > + ret = cs48l32_patch(cs48l32); > + if (ret) { > + dev_err(cs48l32->dev, "Failed to apply patch %d\n", ret); > + goto err_reset; > + } > + > + ret = cs48l32_configure_clk32k(cs48l32); > + if (ret) > + goto err_reset; > + > + pm_runtime_set_active(cs48l32->dev); > + pm_runtime_enable(cs48l32->dev); > + pm_runtime_set_autosuspend_delay(cs48l32->dev, 100); > + pm_runtime_use_autosuspend(cs48l32->dev); > + > + ret = mfd_add_devices(cs48l32->dev, PLATFORM_DEVID_NONE, > + cs48l32_devs, ARRAY_SIZE(cs48l32_devs), NULL, 0, NULL); > + if (ret) { > + dev_err(cs48l32->dev, "Failed to add subdevices: %d\n", ret); > + goto err_clk32k; > + } > + > + return 0; > + > +err_clk32k: > + clk_disable_unprepare(cs48l32->mclk1); > +err_reset: > + cs48l32_enable_hard_reset(cs48l32); > + regulator_disable(cs48l32->vdd_d); > +err_enable: > + regulator_bulk_disable(cs48l32->num_core_supplies, cs48l32->core_supplies); > + > + return ret; > +} > + > +static void cs48l32_spi_remove(struct spi_device *spi) > +{ > + struct cs48l32_mfd *cs48l32 = spi_get_drvdata(spi); > + > + /* Prevent any IRQs being serviced while we clean up */ > + disable_irq(cs48l32->irq); > + > + mfd_remove_devices(cs48l32->dev); devm_*? > + pm_runtime_disable(cs48l32->dev); > + regulator_disable(cs48l32->vdd_d); > + clk_disable_unprepare(cs48l32->mclk1); > + cs48l32_enable_hard_reset(cs48l32); > + regulator_bulk_disable(cs48l32->num_core_supplies, cs48l32->core_supplies); > +} > + > +static const struct spi_device_id cs48l32_spi_ids[] = { > + { "cs48l31", }, > + { "cs48l32", }, > + { "cs48l33", }, > + { }, > +}; > +MODULE_DEVICE_TABLE(spi, cs48l32_spi_ids); > + > +static struct spi_driver cs48l32_spi_driver = { > + .driver = { > + .name = "cs48l32", > + .owner = THIS_MODULE, > + .pm = &cs48l32_pm_ops, > + .of_match_table = of_match_ptr(cs48l32_of_match), > + }, > + .probe = &cs48l32_spi_probe, > + .remove = &cs48l32_spi_remove, > + .id_table = cs48l32_spi_ids, > +}; > + Remove this line please. > +module_spi_driver(cs48l32_spi_driver); > + > +MODULE_SOFTDEP("pre: pinctrl-cs48l32 irq-cirrus-cs48l32"); > +MODULE_DESCRIPTION("CS48L32 MFD driver"); !MFD > +MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); > +MODULE_LICENSE("GPL"); > diff --git a/drivers/mfd/cs48l32.h b/drivers/mfd/cs48l32.h > new file mode 100644 > index 000000000000..36020c0cd686 > --- /dev/null > +++ b/drivers/mfd/cs48l32.h > @@ -0,0 +1,28 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * MFD for Cirrus Logic CS48L32 audio codec. !MFD > + * Copyright (C) 2016-2018, 2020, 2022 Cirrus Logic, Inc. and > + * Cirrus Logic International Semiconductor Ltd. > + */ > + > +#ifndef CS48L32_MFD_H > +#define CS48L32_MFD_H MFD_ at the front please. > +#include <linux/bits.h> > + > +#define CS48L31_SILICON_ID 0x48a31 > +#define CS48L32_SILICON_ID 0x48a32 > +#define CS48L33_SILICON_ID 0x48a33 > + > +#define CS48L32_32K_MCLK1 0 > + > +#define CS48L32_SFT_RESET_MAGIC 0x5a000000 > +#define CS48L32_SEEN_BOOT_DONE BIT(0) > + > +#define CS48L32_BOOT_TIMEOUT_MS 25 > + > +int cs48l32_init_regmap(struct spi_device *spi, struct cs48l32_mfd *cs48l32); > +int cs48l32_patch(struct cs48l32_mfd *cs48l32); > + > +#endif > diff --git a/include/linux/mfd/cs48l32/core.h b/include/linux/mfd/cs48l32/core.h > new file mode 100644 > index 000000000000..1c4269d70c8c > --- /dev/null > +++ b/include/linux/mfd/cs48l32/core.h > @@ -0,0 +1,49 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * MFD for Cirrus Logic CS48L32 audio codec. !MFD > + * Copyright (C) 2016-2020, 2022 Cirrus Logic, Inc. and > + * Cirrus Logic International Semiconductor Ltd. > + */ > + > +#ifndef CS48L32_CORE_H > +#define CS48L32_CORE_H > + > +#include <linux/clk.h> > +#include <linux/gpio/consumer.h> > +#include <linux/interrupt.h> > +#include <linux/notifier.h> > +#include <linux/regmap.h> > +#include <linux/regulator/consumer.h> > + > +#define CS48L32_MAX_CORE_SUPPLIES 2 > + > +struct snd_soc_dapm_context; > + > +struct cs48l32_mfd { !mfd > + struct regmap *regmap; > + struct device *dev; > + struct gpio_desc *reset_gpio; > + struct clk *mclk1; > + struct snd_soc_dapm_context *dapm; > + > + int num_core_supplies; > + struct regulator_bulk_data core_supplies[CS48L32_MAX_CORE_SUPPLIES]; > + struct regulator *vdd_d; > + > + struct device *irq_dev; > + struct regmap_irq_chip_data *irq_data; > + int irq; > + > + u8 part; > + > + struct blocking_notifier_head notifier; > +}; > + > +static inline int cs48l32_call_notifiers(struct cs48l32_mfd *mfd, > + unsigned long event, > + void *data) > +{ > + return blocking_notifier_call_chain(&mfd->notifier, event, data); > +} > +#endif -- Lee Jones [李琼斯] ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 03/12] mfd: cs48l32: Add support for CS48L31/32/33 codecs @ 2022-11-16 15:43 ` Lee Jones 0 siblings, 0 replies; 98+ messages in thread From: Lee Jones @ 2022-11-16 15:43 UTC (permalink / raw) To: Richard Fitzgerald Cc: devicetree, alsa-devel, maz, linus.walleij, linux-kernel, linux-gpio, robh+dt, broonie, krzysztof.kozlowski+dt, patches, tglx On Wed, 09 Nov 2022, Richard Fitzgerald wrote: > From: Piotr Stankiewicz <piotrs@opensource.cirrus.com> > > The CS48L31/32/33 audio codecs are multi-function devices > containing gpios, irq controller and regulators in addition > to the core audio functionality. > > Signed-off-by: Piotr Stankiewicz <piotrs@opensource.cirrus.com> > Signed-off-by: Qi Zhou <qi.zhou@cirrus.com> > Signed-off-by: Stuart Henderson <stuarth@opensource.cirrus.com> > Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> > --- > MAINTAINERS | 5 +- > drivers/mfd/Kconfig | 13 + > drivers/mfd/Makefile | 2 + > drivers/mfd/cs48l32-tables.c | 541 +++++++++++++++++++++++++++++++ > drivers/mfd/cs48l32.c | 434 +++++++++++++++++++++++++ > drivers/mfd/cs48l32.h | 28 ++ > include/linux/mfd/cs48l32/core.h | 49 +++ > 7 files changed, 1071 insertions(+), 1 deletion(-) > create mode 100644 drivers/mfd/cs48l32-tables.c > create mode 100644 drivers/mfd/cs48l32.c > create mode 100644 drivers/mfd/cs48l32.h > create mode 100644 include/linux/mfd/cs48l32/core.h Nice first attempt. Few nits below. > diff --git a/MAINTAINERS b/MAINTAINERS > index 3f94ed38089b..f1d696f29f11 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -5001,7 +5001,7 @@ F: include/dt-bindings/pinctrl/lochnagar.h > F: include/linux/mfd/lochnagar* > F: sound/soc/codecs/lochnagar-sc.c > > -CIRRUS LOGIC MADERA CODEC DRIVERS > +CIRRUS LOGIC MADERA/CS48L32 CODEC DRIVERS > M: Charles Keepax <ckeepax@opensource.cirrus.com> > M: Richard Fitzgerald <rf@opensource.cirrus.com> > L: alsa-devel@alsa-project.org (moderated for non-subscribers) > @@ -5009,16 +5009,19 @@ L: patches@opensource.cirrus.com > S: Supported > W: https://github.com/CirrusLogic/linux-drivers/wiki > T: git https://github.com/CirrusLogic/linux-drivers.git > +F: Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml > F: Documentation/devicetree/bindings/mfd/cirrus,madera.yaml > F: Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml > F: Documentation/devicetree/bindings/sound/cirrus,madera.yaml > F: drivers/gpio/gpio-madera* > F: drivers/irqchip/irq-madera* > F: drivers/mfd/cs47l* > +F: drivers/mfd/cs48l* > F: drivers/mfd/madera* > F: drivers/pinctrl/cirrus/* > F: include/dt-bindings/sound/madera* > F: include/linux/irqchip/irq-madera* > +F: include/linux/mfd/cs48l32/* > F: include/linux/mfd/madera/* > F: include/sound/madera* > F: sound/soc/codecs/cs47l* > diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig > index 6653d03e0fe3..2be52ba23c7a 100644 > --- a/drivers/mfd/Kconfig > +++ b/drivers/mfd/Kconfig > @@ -300,6 +300,19 @@ config MFD_CS47L92 > help > Support for Cirrus Logic CS42L92, CS47L92 and CS47L93 Smart Codecs > > +config MFD_CS48L32 > + bool "Cirrus Logic CS48L31/32/33" > + depends on SPI_MASTER > + select MFD_CORE > + select REGMAP > + select REGMAP_SPI > + select REGMAP_IRQ > + select CIRRUS_CS48L32_IRQ > + select PINCTRL > + select PINCTRL_CS48L32 > + help > + Support for Cirrus Logic CS48L31, CS48L32 and CS48L33 Smart Codecs. > + > config MFD_ASIC3 > bool "Compaq ASIC3" > depends on GPIOLIB > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile > index 4dd479212b3a..4edbeb9b7a31 100644 > --- a/drivers/mfd/Makefile > +++ b/drivers/mfd/Makefile > @@ -91,6 +91,8 @@ obj-$(CONFIG_MFD_MADERA) += madera.o > obj-$(CONFIG_MFD_MADERA_I2C) += madera-i2c.o > obj-$(CONFIG_MFD_MADERA_SPI) += madera-spi.o > > +obj-$(CONFIG_MFD_CS48L32) += cs48l32.o cs48l32-tables.o > + > obj-$(CONFIG_TPS6105X) += tps6105x.o > obj-$(CONFIG_TPS65010) += tps65010.o > obj-$(CONFIG_TPS6507X) += tps6507x.o > diff --git a/drivers/mfd/cs48l32-tables.c b/drivers/mfd/cs48l32-tables.c > new file mode 100644 > index 000000000000..5dab9753deb0 > --- /dev/null > +++ b/drivers/mfd/cs48l32-tables.c > @@ -0,0 +1,541 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Regmap tables for Cirrus Logic CS48L32 audio codec. > + * > + * Copyright (C) 2018, 2020, 2022 Cirrus Logic, Inc. and > + * Cirrus Logic International Semiconductor Ltd. > + */ > + > +#include <linux/device.h> > +#include <linux/module.h> > +#include <linux/mfd/cs48l32/core.h> > +#include <linux/mfd/cs48l32/registers.h> > + > +#include "cs48l32.h" > + > +static const struct reg_sequence cs48l32_reva_patch[] = { > + { 0x00001044, 0x0005000f }, > + { 0x00001c34, 0x000037e8 }, > + { 0x000046d8, 0x00000fe0 }, > +}; > + > +int cs48l32_patch(struct cs48l32_mfd *cs48l32) > +{ > + int ret; > + > + ret = regmap_register_patch(cs48l32->regmap, cs48l32_reva_patch, > + ARRAY_SIZE(cs48l32_reva_patch)); > + if (ret < 0) > + dev_err(cs48l32->dev, "Error applying patch: %d\n", ret); > + > + return ret; > +} > + > +static const struct reg_default cs48l32_reg_default[] = { > + { 0x00000c08, 0xe1000001 }, /* GPIO1_CTRL1 */ > + { 0x00000c0c, 0xe1000001 }, /* GPIO2_CTRL1 */ > + { 0x00000c10, 0xe1000001 }, /* GPIO3_CTRL1 */ > + { 0x00000c14, 0xe1000001 }, /* GPIO4_CTRL1 */ > + { 0x00000c18, 0xe1000001 }, /* GPIO5_CTRL1 */ > + { 0x00000c1c, 0xe1000001 }, /* GPIO6_CTRL1 */ > + { 0x00000c20, 0xe1000001 }, /* GPIO7_CTRL1 */ > + { 0x00000c24, 0xe1000001 }, /* GPIO8_CTRL1 */ > + { 0x00000c28, 0xe1000001 }, /* GPIO9_CTRL1 */ > + { 0x00000c2c, 0xe1000001 }, /* GPIO10_CTRL1 */ > + { 0x00000c30, 0xe1000001 }, /* GPIO11_CTRL1 */ > + { 0x00000c34, 0xe1000001 }, /* GPIO12_CTRL1 */ > + { 0x00000c38, 0xe1000001 }, /* GPIO13_CTRL1 */ > + { 0x00000c3c, 0xe1000001 }, /* GPIO14_CTRL1 */ > + { 0x00000c40, 0xe1000001 }, /* GPIO15_CTRL1 */ > + { 0x00000c44, 0xe1000001 }, /* GPIO16_CTRL1 */ > + { 0x00001020, 0x00000000 }, /* OUTPUT_SYS_CLK */ > + { 0x00001044, 0x0005000f }, /* AUXPDM_CTRL */ > + { 0x0000105c, 0x00000000 }, /* AUXPDM_CTRL2 */ > + { 0x00001400, 0x00000002 }, /* CLOCK32K */ > + { 0x00001404, 0x00000404 }, /* SYSTEM_CLOCK1 */ > + { 0x00001420, 0x00000003 }, /* SAMPLE_RATE1 */ > + { 0x00001424, 0x00000003 }, /* SAMPLE_RATE2 */ > + { 0x00001428, 0x00000003 }, /* SAMPLE_RATE3 */ > + { 0x0000142c, 0x00000003 }, /* SAMPLE_RATE4 */ > + { 0x00001c00, 0x00000002 }, /* FLL1_CONTROL1 */ > + { 0x00001c04, 0x88203004 }, /* FLL1_CONTROL2 */ > + { 0x00001c08, 0x00000000 }, /* FLL1_CONTROL3 */ > + { 0x00001c0c, 0x21f05001 }, /* FLL1_CONTROL4 */ > + { 0x00001ca0, 0x00000c04 }, /* FLL1_GPIO_CLOCK */ > + { 0x00002000, 0x00000006 }, /* CHARGE_PUMP1 */ > + { 0x00002408, 0x000003e4 }, /* LDO2_CTRL1 */ > + { 0x00002410, 0x000000e6 }, /* MICBIAS_CTRL1 */ > + { 0x00002418, 0x00000222 }, /* MICBIAS_CTRL5 */ > + { 0x00002710, 0x00004600 }, /* IRQ1_CTRL_AOD */ > + { 0x00004000, 0x00000000 }, /* INPUT_CONTROL */ > + { 0x00004008, 0x00000400 }, /* INPUT_RATE_CONTROL */ > + { 0x0000400c, 0x00000000 }, /* INPUT_CONTROL2 */ > + { 0x00004020, 0x00050020 }, /* INPUT1_CONTROL1 */ > + { 0x00004024, 0x00000000 }, /* IN1L_CONTROL1 */ > + { 0x00004028, 0x10800080 }, /* IN1L_CONTROL2 */ > + { 0x00004044, 0x00000000 }, /* IN1R_CONTROL1 */ > + { 0x00004048, 0x10800080 }, /* IN1R_CONTROL2 */ > + { 0x00004060, 0x00050020 }, /* INPUT2_CONTROL1 */ > + { 0x00004064, 0x00000000 }, /* IN2L_CONTROL1 */ > + { 0x00004068, 0x10800000 }, /* IN2L_CONTROL2 */ > + { 0x00004084, 0x00000000 }, /* IN2R_CONTROL1 */ > + { 0x00004088, 0x10800000 }, /* IN2R_CONTROL2 */ > + { 0x00004244, 0x00000002 }, /* INPUT_HPF_CONTROL */ > + { 0x00004248, 0x00000022 }, /* INPUT_VOL_CONTROL */ > + { 0x00004300, 0x00000000 }, /* AUXPDM_CONTROL1 */ > + { 0x00004304, 0x00000000 }, /* AUXPDM_CONTROL2 */ > + { 0x00004308, 0x00010008 }, /* AUXPDM1_CONTROL1 */ > + { 0x00004310, 0x00010008 }, /* AUXPDM2_CONTROL1 */ > + { 0x00004688, 0x00000000 }, /* ADC1L_ANA_CONTROL1 */ > + { 0x0000468c, 0x00000000 }, /* ADC1R_ANA_CONTROL1 */ > + { 0x00006000, 0x00000000 }, /* ASP1_ENABLES1 */ > + { 0x00006004, 0x00000028 }, /* ASP1_CONTROL1 */ > + { 0x00006008, 0x18180200 }, /* ASP1_CONTROL2 */ > + { 0x0000600c, 0x00000002 }, /* ASP1_CONTROL3 */ > + { 0x00006010, 0x03020100 }, /* ASP1_FRAME_CONTROL1 */ > + { 0x00006014, 0x07060504 }, /* ASP1_FRAME_CONTROL2 */ > + { 0x00006020, 0x03020100 }, /* ASP1_FRAME_CONTROL5 */ > + { 0x00006024, 0x07060504 }, /* ASP1_FRAME_CONTROL6 */ > + { 0x00006030, 0x00000020 }, /* ASP1_DATA_CONTROL1 */ > + { 0x00006040, 0x00000020 }, /* ASP1_DATA_CONTROL5 */ > + { 0x00006080, 0x00000000 }, /* ASP2_ENABLES1 */ > + { 0x00006084, 0x00000028 }, /* ASP2_CONTROL1 */ > + { 0x00006088, 0x18180200 }, /* ASP2_CONTROL2 */ > + { 0x0000608c, 0x00000002 }, /* ASP2_CONTROL3 */ > + { 0x00006090, 0x03020100 }, /* ASP2_FRAME_CONTROL1 */ > + { 0x000060a0, 0x03020100 }, /* ASP2_FRAME_CONTROL5 */ > + { 0x000060b0, 0x00000020 }, /* ASP2_DATA_CONTROL1 */ > + { 0x000060c0, 0x00000020 }, /* ASP2_DATA_CONTROL5 */ > + { 0x00008200, 0x00800000 }, /* ASP1TX1_INPUT1 */ > + { 0x00008204, 0x00800000 }, /* ASP1TX1_INPUT2 */ > + { 0x00008208, 0x00800000 }, /* ASP1TX1_INPUT3 */ > + { 0x0000820c, 0x00800000 }, /* ASP1TX1_INPUT4 */ > + { 0x00008210, 0x00800000 }, /* ASP1TX2_INPUT1 */ > + { 0x00008214, 0x00800000 }, /* ASP1TX2_INPUT2 */ > + { 0x00008218, 0x00800000 }, /* ASP1TX2_INPUT3 */ > + { 0x0000821c, 0x00800000 }, /* ASP1TX2_INPUT4 */ > + { 0x00008220, 0x00800000 }, /* ASP1TX3_INPUT1 */ > + { 0x00008224, 0x00800000 }, /* ASP1TX3_INPUT2 */ > + { 0x00008228, 0x00800000 }, /* ASP1TX3_INPUT3 */ > + { 0x0000822c, 0x00800000 }, /* ASP1TX3_INPUT4 */ > + { 0x00008230, 0x00800000 }, /* ASP1TX4_INPUT1 */ > + { 0x00008234, 0x00800000 }, /* ASP1TX4_INPUT2 */ > + { 0x00008238, 0x00800000 }, /* ASP1TX4_INPUT3 */ > + { 0x0000823c, 0x00800000 }, /* ASP1TX4_INPUT4 */ > + { 0x00008240, 0x00800000 }, /* ASP1TX5_INPUT1 */ > + { 0x00008244, 0x00800000 }, /* ASP1TX5_INPUT2 */ > + { 0x00008248, 0x00800000 }, /* ASP1TX5_INPUT3 */ > + { 0x0000824c, 0x00800000 }, /* ASP1TX5_INPUT4 */ > + { 0x00008250, 0x00800000 }, /* ASP1TX6_INPUT1 */ > + { 0x00008254, 0x00800000 }, /* ASP1TX6_INPUT2 */ > + { 0x00008258, 0x00800000 }, /* ASP1TX6_INPUT3 */ > + { 0x0000825c, 0x00800000 }, /* ASP1TX6_INPUT4 */ > + { 0x00008260, 0x00800000 }, /* ASP1TX7_INPUT1 */ > + { 0x00008264, 0x00800000 }, /* ASP1TX7_INPUT2 */ > + { 0x00008268, 0x00800000 }, /* ASP1TX7_INPUT3 */ > + { 0x0000826c, 0x00800000 }, /* ASP1TX7_INPUT4 */ > + { 0x00008270, 0x00800000 }, /* ASP1TX8_INPUT1 */ > + { 0x00008274, 0x00800000 }, /* ASP1TX8_INPUT2 */ > + { 0x00008278, 0x00800000 }, /* ASP1TX8_INPUT3 */ > + { 0x0000827c, 0x00800000 }, /* ASP1TX8_INPUT4 */ > + { 0x00008300, 0x00800000 }, /* ASP2TX1_INPUT1 */ > + { 0x00008304, 0x00800000 }, /* ASP2TX1_INPUT2 */ > + { 0x00008308, 0x00800000 }, /* ASP2TX1_INPUT3 */ > + { 0x0000830c, 0x00800000 }, /* ASP2TX1_INPUT4 */ > + { 0x00008310, 0x00800000 }, /* ASP2TX2_INPUT1 */ > + { 0x00008314, 0x00800000 }, /* ASP2TX2_INPUT2 */ > + { 0x00008318, 0x00800000 }, /* ASP2TX2_INPUT3 */ > + { 0x0000831c, 0x00800000 }, /* ASP2TX2_INPUT4 */ > + { 0x00008320, 0x00800000 }, /* ASP2TX3_INPUT1 */ > + { 0x00008324, 0x00800000 }, /* ASP2TX3_INPUT2 */ > + { 0x00008328, 0x00800000 }, /* ASP2TX3_INPUT3 */ > + { 0x0000832c, 0x00800000 }, /* ASP2TX3_INPUT4 */ > + { 0x00008330, 0x00800000 }, /* ASP2TX4_INPUT1 */ > + { 0x00008334, 0x00800000 }, /* ASP2TX4_INPUT2 */ > + { 0x00008338, 0x00800000 }, /* ASP2TX4_INPUT3 */ > + { 0x0000833c, 0x00800000 }, /* ASP2TX4_INPUT4 */ > + { 0x00008980, 0x00000000 }, /* ISRC1INT1_INPUT1 */ > + { 0x00008990, 0x00000000 }, /* ISRC1INT2_INPUT1 */ > + { 0x000089a0, 0x00000000 }, /* ISRC1INT3_INPUT1 */ > + { 0x000089b0, 0x00000000 }, /* ISRC1INT4_INPUT1 */ > + { 0x000089c0, 0x00000000 }, /* ISRC1DEC1_INPUT1 */ > + { 0x000089d0, 0x00000000 }, /* ISRC1DEC2_INPUT1 */ > + { 0x000089e0, 0x00000000 }, /* ISRC1DEC3_INPUT1 */ > + { 0x000089f0, 0x00000000 }, /* ISRC1DEC4_INPUT1 */ > + { 0x00008a00, 0x00000000 }, /* ISRC2INT1_INPUT1 */ > + { 0x00008a10, 0x00000000 }, /* ISRC2INT2_INPUT1 */ > + { 0x00008a40, 0x00000000 }, /* ISRC2DEC1_INPUT1 */ > + { 0x00008a50, 0x00000000 }, /* ISRC2DEC2_INPUT1 */ > + { 0x00008a80, 0x00000000 }, /* ISRC3INT1_INPUT1 */ > + { 0x00008a90, 0x00000000 }, /* ISRC3INT2_INPUT1 */ > + { 0x00008ac0, 0x00000000 }, /* ISRC3DEC1_INPUT1 */ > + { 0x00008ad0, 0x00000000 }, /* ISRC3DEC2_INPUT1 */ > + { 0x00008b80, 0x00800000 }, /* EQ1_INPUT1 */ > + { 0x00008b84, 0x00800000 }, /* EQ1_INPUT2 */ > + { 0x00008b88, 0x00800000 }, /* EQ1_INPUT3 */ > + { 0x00008b8c, 0x00800000 }, /* EQ1_INPUT4 */ > + { 0x00008b90, 0x00800000 }, /* EQ2_INPUT1 */ > + { 0x00008b94, 0x00800000 }, /* EQ2_INPUT2 */ > + { 0x00008b98, 0x00800000 }, /* EQ2_INPUT3 */ > + { 0x00008b9c, 0x00800000 }, /* EQ2_INPUT4 */ > + { 0x00008ba0, 0x00800000 }, /* EQ3_INPUT1 */ > + { 0x00008ba4, 0x00800000 }, /* EQ3_INPUT2 */ > + { 0x00008ba8, 0x00800000 }, /* EQ3_INPUT3 */ > + { 0x00008bac, 0x00800000 }, /* EQ3_INPUT4 */ > + { 0x00008bb0, 0x00800000 }, /* EQ4_INPUT1 */ > + { 0x00008bb4, 0x00800000 }, /* EQ4_INPUT2 */ > + { 0x00008bb8, 0x00800000 }, /* EQ4_INPUT3 */ > + { 0x00008bbc, 0x00800000 }, /* EQ4_INPUT4 */ > + { 0x00008c00, 0x00800000 }, /* DRC1L_INPUT1 */ > + { 0x00008c04, 0x00800000 }, /* DRC1L_INPUT2 */ > + { 0x00008c08, 0x00800000 }, /* DRC1L_INPUT3 */ > + { 0x00008c0c, 0x00800000 }, /* DRC1L_INPUT4 */ > + { 0x00008c10, 0x00800000 }, /* DRC1R_INPUT1 */ > + { 0x00008c14, 0x00800000 }, /* DRC1R_INPUT2 */ > + { 0x00008c18, 0x00800000 }, /* DRC1R_INPUT3 */ > + { 0x00008c1c, 0x00800000 }, /* DRC1R_INPUT4 */ > + { 0x00008c20, 0x00800000 }, /* DRC2L_INPUT1 */ > + { 0x00008c24, 0x00800000 }, /* DRC2L_INPUT2 */ > + { 0x00008c28, 0x00800000 }, /* DRC2L_INPUT3 */ > + { 0x00008c2c, 0x00800000 }, /* DRC2L_INPUT4 */ > + { 0x00008c30, 0x00800000 }, /* DRC2R_INPUT1 */ > + { 0x00008c34, 0x00800000 }, /* DRC2R_INPUT2 */ > + { 0x00008c38, 0x00800000 }, /* DRC2R_INPUT3 */ > + { 0x00008c3c, 0x00800000 }, /* DRC2R_INPUT4 */ > + { 0x00008c80, 0x00800000 }, /* LHPF1_INPUT1 */ > + { 0x00008c84, 0x00800000 }, /* LHPF1_INPUT2 */ > + { 0x00008c88, 0x00800000 }, /* LHPF1_INPUT3 */ > + { 0x00008c8c, 0x00800000 }, /* LHPF1_INPUT4 */ > + { 0x00008c90, 0x00800000 }, /* LHPF2_INPUT1 */ > + { 0x00008c94, 0x00800000 }, /* LHPF2_INPUT2 */ > + { 0x00008c98, 0x00800000 }, /* LHPF2_INPUT3 */ > + { 0x00008c9c, 0x00800000 }, /* LHPF2_INPUT4 */ > + { 0x00008ca0, 0x00800000 }, /* LHPF3_INPUT1 */ > + { 0x00008ca4, 0x00800000 }, /* LHPF3_INPUT2 */ > + { 0x00008ca8, 0x00800000 }, /* LHPF3_INPUT3 */ > + { 0x00008cac, 0x00800000 }, /* LHPF3_INPUT4 */ > + { 0x00008cb0, 0x00800000 }, /* LHPF4_INPUT1 */ > + { 0x00008cb4, 0x00800000 }, /* LHPF4_INPUT2 */ > + { 0x00008cb8, 0x00800000 }, /* LHPF4_INPUT3 */ > + { 0x00008cbc, 0x00800000 }, /* LHPF4_INPUT4 */ > + { 0x00009000, 0x00800000 }, /* DSP1RX1_INPUT1 */ > + { 0x00009004, 0x00800000 }, /* DSP1RX1_INPUT2 */ > + { 0x00009008, 0x00800000 }, /* DSP1RX1_INPUT3 */ > + { 0x0000900c, 0x00800000 }, /* DSP1RX1_INPUT4 */ > + { 0x00009010, 0x00800000 }, /* DSP1RX2_INPUT1 */ > + { 0x00009014, 0x00800000 }, /* DSP1RX2_INPUT2 */ > + { 0x00009018, 0x00800000 }, /* DSP1RX2_INPUT3 */ > + { 0x0000901c, 0x00800000 }, /* DSP1RX2_INPUT4 */ > + { 0x00009020, 0x00800000 }, /* DSP1RX3_INPUT1 */ > + { 0x00009024, 0x00800000 }, /* DSP1RX3_INPUT2 */ > + { 0x00009028, 0x00800000 }, /* DSP1RX3_INPUT3 */ > + { 0x0000902c, 0x00800000 }, /* DSP1RX3_INPUT4 */ > + { 0x00009030, 0x00800000 }, /* DSP1RX4_INPUT1 */ > + { 0x00009034, 0x00800000 }, /* DSP1RX4_INPUT2 */ > + { 0x00009038, 0x00800000 }, /* DSP1RX4_INPUT3 */ > + { 0x0000903c, 0x00800000 }, /* DSP1RX4_INPUT4 */ > + { 0x00009040, 0x00800000 }, /* DSP1RX5_INPUT1 */ > + { 0x00009044, 0x00800000 }, /* DSP1RX5_INPUT2 */ > + { 0x00009048, 0x00800000 }, /* DSP1RX5_INPUT3 */ > + { 0x0000904c, 0x00800000 }, /* DSP1RX5_INPUT4 */ > + { 0x00009050, 0x00800000 }, /* DSP1RX6_INPUT1 */ > + { 0x00009054, 0x00800000 }, /* DSP1RX6_INPUT2 */ > + { 0x00009058, 0x00800000 }, /* DSP1RX6_INPUT3 */ > + { 0x0000905c, 0x00800000 }, /* DSP1RX6_INPUT4 */ > + { 0x00009060, 0x00800000 }, /* DSP1RX7_INPUT1 */ > + { 0x00009064, 0x00800000 }, /* DSP1RX7_INPUT2 */ > + { 0x00009068, 0x00800000 }, /* DSP1RX7_INPUT3 */ > + { 0x0000906c, 0x00800000 }, /* DSP1RX7_INPUT4 */ > + { 0x00009070, 0x00800000 }, /* DSP1RX8_INPUT1 */ > + { 0x00009074, 0x00800000 }, /* DSP1RX8_INPUT2 */ > + { 0x00009078, 0x00800000 }, /* DSP1RX8_INPUT3 */ > + { 0x0000907c, 0x00800000 }, /* DSP1RX8_INPUT4 */ > + { 0x0000a400, 0x00000000 }, /* ISRC1_CONTROL1 */ > + { 0x0000a404, 0x00000000 }, /* ISRC1_CONTROL2 */ > + { 0x0000a510, 0x00000000 }, /* ISRC2_CONTROL1 */ > + { 0x0000a514, 0x00000000 }, /* ISRC2_CONTROL2 */ > + { 0x0000a620, 0x00000000 }, /* ISRC3_CONTROL1 */ > + { 0x0000a624, 0x00000000 }, /* ISRC3_CONTROL2 */ > + { 0x0000a800, 0x00000000 }, /* FX_SAMPLE_RATE */ > + { 0x0000a808, 0x00000000 }, /* EQ_CONTROL1 */ > + { 0x0000a80c, 0x00000000 }, /* EQ_CONTROL2 */ > + { 0x0000a810, 0x0c0c0c0c }, /* EQ1_GAIN1 */ > + { 0x0000a814, 0x0000000c }, /* EQ1_GAIN2 */ > + { 0x0000a818, 0x03fe0fc8 }, /* EQ1_BAND1_COEFF1 */ > + { 0x0000a81c, 0x00000b75 }, /* EQ1_BAND1_COEFF2 */ > + { 0x0000a820, 0x000000e0 }, /* EQ1_BAND1_PG */ > + { 0x0000a824, 0xf1361ec4 }, /* EQ1_BAND2_COEFF1 */ > + { 0x0000a828, 0x00000409 }, /* EQ1_BAND2_COEFF2 */ > + { 0x0000a82c, 0x000004cc }, /* EQ1_BAND2_PG */ > + { 0x0000a830, 0xf3371c9b }, /* EQ1_BAND3_COEFF1 */ > + { 0x0000a834, 0x0000040b }, /* EQ1_BAND3_COEFF2 */ > + { 0x0000a838, 0x00000cbb }, /* EQ1_BAND3_PG */ > + { 0x0000a83c, 0xf7d916f8 }, /* EQ1_BAND4_COEFF1 */ > + { 0x0000a840, 0x0000040a }, /* EQ1_BAND4_COEFF2 */ > + { 0x0000a844, 0x00001f14 }, /* EQ1_BAND4_PG */ > + { 0x0000a848, 0x0563058c }, /* EQ1_BAND5_COEFF1 */ > + { 0x0000a84c, 0x00000000 }, /* EQ1_BAND5_COEFF1 + 4 */ > + { 0x0000a850, 0x00004000 }, /* EQ1_BAND5_PG */ > + { 0x0000a854, 0x0c0c0c0c }, /* EQ2_GAIN1 */ > + { 0x0000a858, 0x0000000c }, /* EQ2_GAIN2 */ > + { 0x0000a85c, 0x03fe0fc8 }, /* EQ2_BAND1_COEFF1 */ > + { 0x0000a860, 0x00000b75 }, /* EQ2_BAND1_COEFF2 */ > + { 0x0000a864, 0x000000e0 }, /* EQ2_BAND1_PG */ > + { 0x0000a868, 0xf1361ec4 }, /* EQ2_BAND2_COEFF1 */ > + { 0x0000a86c, 0x00000409 }, /* EQ2_BAND2_COEFF2 */ > + { 0x0000a870, 0x000004cc }, /* EQ2_BAND2_PG */ > + { 0x0000a874, 0xf3371c9b }, /* EQ2_BAND3_COEFF1 */ > + { 0x0000a878, 0x0000040b }, /* EQ2_BAND3_COEFF2 */ > + { 0x0000a87c, 0x00000cbb }, /* EQ2_BAND3_PG */ > + { 0x0000a880, 0xf7d916f8 }, /* EQ2_BAND4_COEFF1 */ > + { 0x0000a884, 0x0000040a }, /* EQ2_BAND4_COEFF2 */ > + { 0x0000a888, 0x00001f14 }, /* EQ2_BAND4_PG */ > + { 0x0000a88c, 0x0563058c }, /* EQ2_BAND5_COEFF1 */ > + { 0x0000a890, 0x00000000 }, /* EQ2_BAND5_COEFF1 + 4 */ > + { 0x0000a894, 0x00004000 }, /* EQ2_BAND5_PG */ > + { 0x0000a898, 0x0c0c0c0c }, /* EQ3_GAIN1 */ > + { 0x0000a89c, 0x0000000c }, /* EQ3_GAIN2 */ > + { 0x0000a8a0, 0x03fe0fc8 }, /* EQ3_BAND1_COEFF1 */ > + { 0x0000a8a4, 0x00000b75 }, /* EQ3_BAND1_COEFF2 */ > + { 0x0000a8a8, 0x000000e0 }, /* EQ3_BAND1_PG */ > + { 0x0000a8ac, 0xf1361ec4 }, /* EQ3_BAND2_COEFF1 */ > + { 0x0000a8b0, 0x00000409 }, /* EQ3_BAND2_COEFF2 */ > + { 0x0000a8b4, 0x000004cc }, /* EQ3_BAND2_PG */ > + { 0x0000a8b8, 0xf3371c9b }, /* EQ3_BAND3_COEFF1 */ > + { 0x0000a8bc, 0x0000040b }, /* EQ3_BAND3_COEFF2 */ > + { 0x0000a8c0, 0x00000cbb }, /* EQ3_BAND3_PG */ > + { 0x0000a8c4, 0xf7d916f8 }, /* EQ3_BAND4_COEFF1 */ > + { 0x0000a8c8, 0x0000040a }, /* EQ3_BAND4_COEFF2 */ > + { 0x0000a8cc, 0x00001f14 }, /* EQ3_BAND4_PG */ > + { 0x0000a8d0, 0x0563058c }, /* EQ3_BAND5_COEFF1 */ > + { 0x0000a8d4, 0x00000000 }, /* EQ3_BAND5_COEFF1 + 4 */ > + { 0x0000a8d8, 0x00004000 }, /* EQ3_BAND5_PG */ > + { 0x0000a8dc, 0x0c0c0c0c }, /* EQ4_GAIN1 */ > + { 0x0000a8e0, 0x0000000c }, /* EQ4_GAIN2 */ > + { 0x0000a8e4, 0x03fe0fc8 }, /* EQ4_BAND1_COEFF1 */ > + { 0x0000a8e8, 0x00000b75 }, /* EQ4_BAND1_COEFF2 */ > + { 0x0000a8ec, 0x000000e0 }, /* EQ4_BAND1_PG */ > + { 0x0000a8f0, 0xf1361ec4 }, /* EQ4_BAND2_COEFF1 */ > + { 0x0000a8f4, 0x00000409 }, /* EQ4_BAND2_COEFF2 */ > + { 0x0000a8f8, 0x000004cc }, /* EQ4_BAND2_PG */ > + { 0x0000a8fc, 0xf3371c9b }, /* EQ4_BAND3_COEFF1 */ > + { 0x0000a900, 0x0000040b }, /* EQ4_BAND3_COEFF2 */ > + { 0x0000a904, 0x00000cbb }, /* EQ4_BAND3_PG */ > + { 0x0000a908, 0xf7d916f8 }, /* EQ4_BAND4_COEFF1 */ > + { 0x0000a90c, 0x0000040a }, /* EQ4_BAND4_COEFF2 */ > + { 0x0000a910, 0x00001f14 }, /* EQ4_BAND4_PG */ > + { 0x0000a914, 0x0563058c }, /* EQ4_BAND5_COEFF1 */ > + { 0x0000a918, 0x00000000 }, /* EQ4_BAND5_COEFF1 + 4 */ > + { 0x0000a91c, 0x00004000 }, /* EQ4_BAND5_PG */ > + { 0x0000aa30, 0x00000000 }, /* LHPF_CONTROL1 */ > + { 0x0000aa34, 0x00000000 }, /* LHPF_CONTROL2 */ > + { 0x0000aa38, 0x00000000 }, /* LHPF1_COEFF */ > + { 0x0000aa3c, 0x00000000 }, /* LHPF2_COEFF */ > + { 0x0000aa40, 0x00000000 }, /* LHPF3_COEFF */ > + { 0x0000aa44, 0x00000000 }, /* LHPF4_COEFF */ > + { 0x0000ab00, 0x00000000 }, /* DRC1_CONTROL1 */ > + { 0x0000ab04, 0x49130018 }, /* DRC1_CONTROL2 */ > + { 0x0000ab08, 0x00000018 }, /* DRC1_CONTROL3 */ > + { 0x0000ab0c, 0x00000000 }, /* DRC1_CONTROL4 */ > + { 0x0000ab14, 0x00000000 }, /* DRC2_CONTROL1 */ > + { 0x0000ab18, 0x49130018 }, /* DRC2_CONTROL2 */ > + { 0x0000ab1c, 0x00000018 }, /* DRC2_CONTROL3 */ > + { 0x0000ab20, 0x00000000 }, /* DRC2_CONTROL4 */ > + { 0x0000b000, 0x00000000 }, /* TONE_GENERATOR1 */ > + { 0x0000b004, 0x00100000 }, /* TONE_GENERATOR2 */ > + { 0x0000b400, 0x00000000 }, /* COMFORT_NOISE_GENERATOR */ > + { 0x0000b800, 0x00000000 }, /* US_CONTROL */ > + { 0x0000b804, 0x00002020 }, /* US1_CONTROL */ > + { 0x0000b808, 0x00000000 }, /* US1_DET_CONTROL */ > + { 0x0000b814, 0x00002020 }, /* US2_CONTROL */ > + { 0x0000b818, 0x00000000 }, /* US2_DET_CONTROL */ > + { 0x00018110, 0xffffffff }, /* IRQ1_MASK_1 */ > + { 0x00018114, 0xfffffff7 }, /* IRQ1_MASK_2 */ > + { 0x00018118, 0xffffffff }, /* IRQ1_MASK_3 */ > + { 0x0001811c, 0xffffffff }, /* IRQ1_MASK_4 */ > + { 0x00018120, 0xffffffff }, /* IRQ1_MASK_5 */ > + { 0x00018124, 0xffffffff }, /* IRQ1_MASK_6 */ > + { 0x00018128, 0xffffffff }, /* IRQ1_MASK_7 */ > + { 0x0001812c, 0xffffffff }, /* IRQ1_MASK_8 */ > + { 0x00018130, 0xffffffff }, /* IRQ1_MASK_9 */ > + { 0x00018134, 0xffffffff }, /* IRQ1_MASK_10 */ > + { 0x00018138, 0xffffffff }, /* IRQ1_MASK_11 */ > +}; > + > +static bool cs48l32_readable_register(struct device *dev, unsigned int reg) > +{ > + switch (reg) { > + case CS48L32_DEVID: > + case CS48L32_REVID: > + case CS48L32_OTPID: > + case CS48L32_SFT_RESET: > + case CS48L32_CTRL_IF_DEBUG3: > + case CS48L32_MCU_CTRL1: > + case CS48L32_GPIO1_CTRL1 ... CS48L32_GPIO16_CTRL1: > + case CS48L32_OUTPUT_SYS_CLK: > + case CS48L32_AUXPDM_CTRL: > + case CS48L32_AUXPDM_CTRL2: > + case CS48L32_CLOCK32K: > + case CS48L32_SYSTEM_CLOCK1 ... CS48L32_SYSTEM_CLOCK2: > + case CS48L32_SAMPLE_RATE1 ... CS48L32_SAMPLE_RATE4: > + case CS48L32_FLL1_CONTROL1 ... CS48L32_FLL1_GPIO_CLOCK: > + case CS48L32_CHARGE_PUMP1: > + case CS48L32_LDO2_CTRL1: > + case CS48L32_MICBIAS_CTRL1: > + case CS48L32_MICBIAS_CTRL5: > + case CS48L32_IRQ1_CTRL_AOD: > + case CS48L32_INPUT_CONTROL: > + case CS48L32_INPUT_STATUS: > + case CS48L32_INPUT_RATE_CONTROL: > + case CS48L32_INPUT_CONTROL2: > + case CS48L32_INPUT_CONTROL3: > + case CS48L32_INPUT1_CONTROL1: > + case CS48L32_IN1L_CONTROL1 ... CS48L32_IN1L_CONTROL2: > + case CS48L32_IN1R_CONTROL1 ... CS48L32_IN1R_CONTROL2: > + case CS48L32_INPUT2_CONTROL1: > + case CS48L32_IN2L_CONTROL1 ... CS48L32_IN2L_CONTROL2: > + case CS48L32_IN2R_CONTROL1 ... CS48L32_IN2R_CONTROL2: > + case CS48L32_INPUT_HPF_CONTROL: > + case CS48L32_INPUT_VOL_CONTROL: > + case CS48L32_AUXPDM_CONTROL1: > + case CS48L32_AUXPDM_CONTROL2: > + case CS48L32_AUXPDM1_CONTROL1: > + case CS48L32_AUXPDM2_CONTROL1: > + case CS48L32_ADC1L_ANA_CONTROL1: > + case CS48L32_ADC1R_ANA_CONTROL1: > + case CS48L32_ASP1_ENABLES1 ... CS48L32_ASP1_DATA_CONTROL5: > + case CS48L32_ASP2_ENABLES1 ... CS48L32_ASP2_DATA_CONTROL5: > + case CS48L32_ASP1TX1_INPUT1 ... CS48L32_ASP1TX8_INPUT4: > + case CS48L32_ASP2TX1_INPUT1 ... CS48L32_ASP2TX4_INPUT4: > + case CS48L32_ISRC1INT1_INPUT1 ... CS48L32_ISRC1DEC4_INPUT1: > + case CS48L32_ISRC2INT1_INPUT1 ... CS48L32_ISRC2DEC2_INPUT1: > + case CS48L32_ISRC3INT1_INPUT1 ... CS48L32_ISRC3DEC2_INPUT1: > + case CS48L32_EQ1_INPUT1 ... CS48L32_EQ4_INPUT4: > + case CS48L32_DRC1L_INPUT1 ... CS48L32_DRC1R_INPUT4: > + case CS48L32_DRC2L_INPUT1 ... CS48L32_DRC2R_INPUT4: > + case CS48L32_LHPF1_INPUT1 ... CS48L32_LHPF1_INPUT4: > + case CS48L32_LHPF2_INPUT1 ... CS48L32_LHPF2_INPUT4: > + case CS48L32_LHPF3_INPUT1 ... CS48L32_LHPF3_INPUT4: > + case CS48L32_LHPF4_INPUT1 ... CS48L32_LHPF4_INPUT4: > + case CS48L32_DSP1RX1_INPUT1 ... CS48L32_DSP1RX8_INPUT4: > + case CS48L32_ISRC1_CONTROL1 ... CS48L32_ISRC1_CONTROL2: > + case CS48L32_ISRC2_CONTROL1 ... CS48L32_ISRC2_CONTROL2: > + case CS48L32_ISRC3_CONTROL1 ... CS48L32_ISRC3_CONTROL2: > + case CS48L32_FX_SAMPLE_RATE: > + case CS48L32_EQ_CONTROL1 ... CS48L32_EQ_CONTROL2: > + case CS48L32_EQ1_GAIN1 ... CS48L32_EQ1_BAND5_PG: > + case CS48L32_EQ2_GAIN1 ... CS48L32_EQ2_BAND5_PG: > + case CS48L32_EQ3_GAIN1 ... CS48L32_EQ3_BAND5_PG: > + case CS48L32_EQ4_GAIN1 ... CS48L32_EQ4_BAND5_PG: > + case CS48L32_LHPF_CONTROL1 ... CS48L32_LHPF_CONTROL2: > + case CS48L32_LHPF1_COEFF ... CS48L32_LHPF4_COEFF: > + case CS48L32_DRC1_CONTROL1 ... CS48L32_DRC1_CONTROL4: > + case CS48L32_DRC2_CONTROL1 ... CS48L32_DRC2_CONTROL4: > + case CS48L32_TONE_GENERATOR1 ... CS48L32_TONE_GENERATOR2: > + case CS48L32_COMFORT_NOISE_GENERATOR: > + case CS48L32_US_CONTROL: > + case CS48L32_US1_CONTROL: > + case CS48L32_US1_DET_CONTROL: > + case CS48L32_US2_CONTROL: > + case CS48L32_US2_DET_CONTROL: > + case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24: > + case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8: > + case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7: > + case CS48L32_IRQ1_STATUS: > + case CS48L32_IRQ1_EINT_1 ... CS48L32_IRQ1_EINT_11: > + case CS48L32_IRQ1_STS_1 ... CS48L32_IRQ1_STS_11: > + case CS48L32_IRQ1_MASK_1 ... CS48L32_IRQ1_MASK_11: > + case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_147455: > + case CS48L32_DSP1_SYS_INFO_ID ... CS48L32_DSP1_AHBM_WINDOW_DEBUG_1: > + case CS48L32_DSP1_XMEM_UNPACKED24_0 ... CS48L32_DSP1_XMEM_UNPACKED24_196607: > + case CS48L32_DSP1_CLOCK_FREQ ... CS48L32_DSP1_SAMPLE_RATE_TX8: > + case CS48L32_DSP1_SCRATCH1 ... CS48L32_DSP1_SCRATCH4: > + case CS48L32_DSP1_CCM_CORE_CONTROL ... CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1: > + case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_49151: > + case CS48L32_DSP1_YMEM_UNPACKED24_0 ... CS48L32_DSP1_YMEM_UNPACKED24_65535: > + case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_71679: > + return true; > + default: > + return false; > + } > +} > + > +static bool cs48l32_volatile_register(struct device *dev, unsigned int reg) > +{ > + switch (reg) { > + case CS48L32_DEVID: > + case CS48L32_REVID: > + case CS48L32_OTPID: > + case CS48L32_SFT_RESET: > + case CS48L32_CTRL_IF_DEBUG3: > + case CS48L32_MCU_CTRL1: > + case CS48L32_SYSTEM_CLOCK2: > + case CS48L32_FLL1_CONTROL5: > + case CS48L32_FLL1_CONTROL6: > + case CS48L32_INPUT_STATUS: > + case CS48L32_INPUT_CONTROL3: > + case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24: > + case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8: > + case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7: > + case CS48L32_IRQ1_STATUS: > + case CS48L32_IRQ1_EINT_1 ... CS48L32_IRQ1_EINT_11: > + case CS48L32_IRQ1_STS_1 ... CS48L32_IRQ1_STS_11: > + case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_147455: > + case CS48L32_DSP1_SYS_INFO_ID ... CS48L32_DSP1_AHBM_WINDOW_DEBUG_1: > + case CS48L32_DSP1_XMEM_UNPACKED24_0 ... CS48L32_DSP1_XMEM_UNPACKED24_196607: > + case CS48L32_DSP1_CLOCK_FREQ ... CS48L32_DSP1_SAMPLE_RATE_TX8: > + case CS48L32_DSP1_SCRATCH1 ... CS48L32_DSP1_SCRATCH4: > + case CS48L32_DSP1_CCM_CORE_CONTROL ... CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1: > + case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_49151: > + case CS48L32_DSP1_YMEM_UNPACKED24_0 ... CS48L32_DSP1_YMEM_UNPACKED24_65535: > + case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_71679: > + return true; > + default: > + return false; > + } > +} > + > +/* > + * The bus bridge requires DSP packed memory registers to be accessed in > + * aligned block multiples. > + * Mark precious to prevent regmap debugfs causing an illegal bus transaction. > + */ > +static bool cs48l32_precious_register(struct device *dev, unsigned int reg) > +{ > + switch (reg) { > + case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_147455: > + case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_49151: > + case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_71679: > + return true; > + default: > + return false; > + } > +} > + > +static const struct regmap_config cs48l32_spi_regmap = { > + .name = "cs48l32", > + .reg_bits = 32, > + .reg_stride = 4, > + .pad_bits = 32, > + .val_bits = 32, > + .reg_format_endian = REGMAP_ENDIAN_BIG, > + .val_format_endian = REGMAP_ENDIAN_BIG, > + > + .max_register = CS48L32_DSP1_PMEM_71679, > + .readable_reg = &cs48l32_readable_register, > + .volatile_reg = &cs48l32_volatile_register, > + .precious_reg = &cs48l32_precious_register, > + > + .cache_type = REGCACHE_RBTREE, > + .reg_defaults = cs48l32_reg_default, > + .num_reg_defaults = ARRAY_SIZE(cs48l32_reg_default), > +}; > + > +int cs48l32_init_regmap(struct spi_device *spi, struct cs48l32_mfd *cs48l32) > +{ > + cs48l32->regmap = devm_regmap_init_spi(spi, &cs48l32_spi_regmap); > + if (IS_ERR(cs48l32->regmap)) > + return PTR_ERR(cs48l32->regmap); > + > + return 0; > +} > diff --git a/drivers/mfd/cs48l32.c b/drivers/mfd/cs48l32.c > new file mode 100644 > index 000000000000..9506a1e0560b > --- /dev/null > +++ b/drivers/mfd/cs48l32.c > @@ -0,0 +1,434 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * MFD for Cirrus Logic CS48L32 audio codec. The name MFD should be omitted. If you must, you can say 'core driver' or something. > + * Copyright (C) 2016-2018, 2020, 2022 Cirrus Logic, Inc. and > + * Cirrus Logic International Semiconductor Ltd. > + */ > + > +#include <linux/delay.h> > +#include <linux/err.h> > +#include <linux/gpio/consumer.h> > +#include <linux/mfd/core.h> > +#include <linux/mfd/cs48l32/core.h> > +#include <linux/mfd/cs48l32/registers.h> > +#include <linux/module.h> > +#include <linux/notifier.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/pinctrl/consumer.h> > +#include <linux/platform_device.h> > +#include <linux/pm_runtime.h> > +#include <linux/property.h> > +#include <linux/regmap.h> > +#include <linux/regulator/consumer.h> > +#include <linux/regulator/driver.h> > +#include <linux/regulator/machine.h> > +#include <linux/regulator/of_regulator.h> > +#include <linux/spi/spi.h> Could you review these include files please. Are they all utilised? > +#include "cs48l32.h" > + > +static const char * const cs48l32_core_supplies[] = { > + "VDD_A", > + "VDD_IO", > +}; > + > +static const char * const cs48l32_supplies[] = { > + "VOUT_MIC", > + "VDD_CP", > +}; > + > +static const struct mfd_cell cs48l32_devs[] = { > + { .name = "cs48l32-pinctrl", }, > + { .name = "cs48l32-irq", }, > + { .name = "cs48l32-micsupp", }, > + { > + .name = "cs48l32-codec", > + .parent_supplies = cs48l32_supplies, > + .num_parent_supplies = ARRAY_SIZE(cs48l32_supplies), > + }, > +}; > + > +static int cs48l32_wait_for_boot(struct cs48l32_mfd *cs48l32) > +{ > + unsigned int val; > + int i, ret; > + > + /* regmap_read_poll_timeout would fail on read errors so roll our own */ It would, why? Is it fixable? Has it been reported? > + for (i = 0; i < CS48L32_BOOT_TIMEOUT_MS; ++i) { > + val = 0; What happens if you don't initialise this? Why is that better than checking the return value? > + regmap_read(cs48l32->regmap, CS48L32_IRQ1_EINT_2, &val); > + if (val & CS48L32_BOOT_DONE_EINT1_MASK) > + break; > + > + usleep_range(1000, 2000); > + } > + if (i == CS48L32_BOOT_TIMEOUT_MS) { > + dev_err(cs48l32->dev, "BOOT_DONE timed out\n"); > + return -ETIMEDOUT; > + } > + > + ret = regmap_read(cs48l32->regmap, CS48L32_MCU_CTRL1, &val); > + if (ret) { > + dev_err(cs48l32->dev, "Failed to read MCU_CTRL1: %d\n", ret); > + return ret; > + } > + > + if (val & BIT(CS48L32_MCU_STS_SHIFT)) { > + dev_err(cs48l32->dev, "MCU boot failed\n"); > + return -EIO; > + } > + > + ret = regmap_set_bits(cs48l32->regmap, CS48L32_CTRL_IF_DEBUG3, CS48L32_SEEN_BOOT_DONE); > + if (ret) { > + dev_err(cs48l32->dev, "Failed to write CTRL_IF_DEBUG3: %d\n", ret); > + return ret; > + } > + > + pm_runtime_mark_last_busy(cs48l32->dev); > + > + return 0; > +} > + > +static int cs48l32_soft_reset(struct cs48l32_mfd *cs48l32) > +{ > + int ret; > + > + ret = regmap_write(cs48l32->regmap, CS48L32_SFT_RESET, CS48L32_SFT_RESET_MAGIC); > + if (ret != 0) { > + dev_err(cs48l32->dev, "Failed to write soft reset: %d\n", ret); > + return ret; > + } > + > + usleep_range(2000, 3000); > + > + return 0; > +} > + > +static void cs48l32_enable_hard_reset(struct cs48l32_mfd *cs48l32) > +{ > + if (cs48l32->reset_gpio) > + gpiod_set_value_cansleep(cs48l32->reset_gpio, 0); > +} > + > +static void cs48l32_disable_hard_reset(struct cs48l32_mfd *cs48l32) > +{ > + if (cs48l32->reset_gpio) { > + gpiod_set_value_cansleep(cs48l32->reset_gpio, 1); > + usleep_range(2000, 3000); > + } > +} > + > +static int __maybe_unused cs48l32_runtime_resume(struct device *dev) > +{ > + struct cs48l32_mfd *cs48l32 = dev_get_drvdata(dev); > + unsigned int val; > + int ret; > + > + dev_dbg(cs48l32->dev, "Leaving sleep mode\n"); > + > + ret = regulator_enable(cs48l32->vdd_d); > + if (ret) { > + dev_err(cs48l32->dev, "Failed to enable VDD_D: %d\n", ret); > + return ret; > + } > + > + usleep_range(2000, 3000); > + > + regcache_cache_only(cs48l32->regmap, false); > + > + /* Did it power down during suspend? */ > + ret = regmap_read(cs48l32->regmap, CS48L32_CTRL_IF_DEBUG3, &val); > + if ((ret == 0) && (val & CS48L32_SEEN_BOOT_DONE)) { > + dev_dbg(cs48l32->dev, "VDD_D didn't power off during suspend\n"); > + } else { > + ret = cs48l32_wait_for_boot(cs48l32); > + if (ret) > + goto err; > + > + /* Flag that the registers have reset to defaults */ > + regcache_mark_dirty(cs48l32->regmap); > + } > + > + ret = regcache_sync(cs48l32->regmap); > + if (ret) { > + dev_err(cs48l32->dev, "Failed to restore register cache\n"); > + goto err; > + } > + > + return 0; > + > +err: > + regcache_cache_only(cs48l32->regmap, true); > + regulator_disable(cs48l32->vdd_d); > + return ret; > +} > + > +static int __maybe_unused cs48l32_runtime_suspend(struct device *dev) > +{ > + struct cs48l32_mfd *cs48l32 = dev_get_drvdata(dev); > + > + dev_dbg(cs48l32->dev, "Entering sleep mode\n"); > + > + regcache_cache_only(cs48l32->regmap, true); > + regulator_disable(cs48l32->vdd_d); > + > + return 0; > +} > + > +static const struct dev_pm_ops cs48l32_pm_ops = { > + SET_RUNTIME_PM_OPS(cs48l32_runtime_suspend, cs48l32_runtime_resume, NULL) > +}; > + > +static const struct __maybe_unused of_device_id cs48l32_of_match[] = { > + { .compatible = "cirrus,cs48l31", }, > + { .compatible = "cirrus,cs48l32", }, > + { .compatible = "cirrus,cs48l33", }, > + {}, > +}; > + > +static int cs48l32_configure_clk32k(struct cs48l32_mfd *cs48l32) > +{ > + int ret = 0; > + > + ret = clk_prepare_enable(cs48l32->mclk1); > + if (ret) { > + dev_err(cs48l32->dev, "Failed to enable 32k clock: %d\n", ret); > + return ret; > + } > + > + ret = regmap_update_bits(cs48l32->regmap, CS48L32_CLOCK32K, > + CS48L32_CLK_32K_EN_MASK | CS48L32_CLK_32K_SRC_MASK, > + CS48L32_CLK_32K_EN_MASK | CS48L32_32K_MCLK1); > + if (ret) { > + dev_err(cs48l32->dev, "Failed to init 32k clock: %d\n", ret); > + clk_disable_unprepare(cs48l32->mclk1); > + return ret; > + } > + > + return 0; > +} > + > +static int cs48l32_get_clocks(struct cs48l32_mfd *cs48l32) > +{ > + cs48l32->mclk1 = devm_clk_get_optional(cs48l32->dev, "mclk1"); > + if (IS_ERR(cs48l32->mclk1)) > + return dev_err_probe(cs48l32->dev, PTR_ERR(cs48l32->mclk1), > + "Failed to get mclk1\n"); > + > + return 0; > +} > + > +static int cs48l32_get_reset_gpio(struct cs48l32_mfd *cs48l32) > +{ > + struct gpio_desc *reset; > + > + reset = devm_gpiod_get_optional(cs48l32->dev, "reset", GPIOD_OUT_LOW); > + if (IS_ERR(reset)) > + return dev_err_probe(cs48l32->dev, PTR_ERR(reset), "Failed to request /RESET\n"); > + > + /* > + * A hard reset is needed for full reset of the chip. We allow running > + * without hard reset only because it can be useful for early > + * prototyping and some debugging, but we need to warn it's not ideal. > + */ > + if (!reset) > + dev_warn(cs48l32->dev, "Running without reset GPIO is not recommended\n"); > + > + cs48l32->reset_gpio = reset; > + > + return 0; > +} > + > +static int cs48l32_spi_probe(struct spi_device *spi) > +{ > + struct device *dev = &spi->dev; > + struct cs48l32_mfd *cs48l32; Prefer if you didn't put 'mfd' in the name. This is more traditional: struct cs48l32 *ddata; > + unsigned int hwid, rev, otp_rev; > + int i, ret; > + > + cs48l32 = devm_kzalloc(&spi->dev, sizeof(*cs48l32), GFP_KERNEL); > + if (!cs48l32) > + return -ENOMEM; > + > + ret = cs48l32_init_regmap(spi, cs48l32); > + if (ret) > + return dev_err_probe(&spi->dev, ret, "Failed to allocate regmap\n"); > + > + cs48l32->dev = dev; > + cs48l32->irq = spi->irq; > + > + dev_set_drvdata(cs48l32->dev, cs48l32); > + > + BLOCKING_INIT_NOTIFIER_HEAD(&cs48l32->notifier); > + > + regcache_cache_only(cs48l32->regmap, true); > + > + ret = cs48l32_get_reset_gpio(cs48l32); > + if (ret) > + return ret; > + > + ret = cs48l32_get_clocks(cs48l32); > + if (ret) > + return ret; > + > + for (i = 0; i < ARRAY_SIZE(cs48l32_core_supplies); i++) > + cs48l32->core_supplies[i].supply = cs48l32_core_supplies[i]; > + > + cs48l32->num_core_supplies = ARRAY_SIZE(cs48l32_core_supplies); Set this before the for(), then use the variable instead of ARRAY_SIZE() again. > + ret = devm_regulator_bulk_get(dev, cs48l32->num_core_supplies, cs48l32->core_supplies); > + if (ret) > + return dev_err_probe(dev, ret, "Failed to request core supplies\n"); > + > + cs48l32->vdd_d = devm_regulator_get(cs48l32->dev, "VDD_D"); > + if (IS_ERR(cs48l32->vdd_d)) > + return dev_err_probe(dev, PTR_ERR(cs48l32->vdd_d), "Failed to request VDD_D\n"); > + > + ret = regulator_set_voltage(cs48l32->vdd_d, 1200000, 1200000); > + if (ret) > + return dev_err_probe(dev, ret, "Failed to request VDD_D=1.2v\n"); > + > + ret = regulator_bulk_enable(cs48l32->num_core_supplies, cs48l32->core_supplies); > + if (ret) > + return dev_err_probe(dev, ret, "Failed to enable core supplies\n"); > + > + ret = regulator_enable(cs48l32->vdd_d); > + if (ret) { > + dev_err(dev, "Failed to enable VDD_D: %d\n", ret); > + goto err_enable; > + } > + > + cs48l32_disable_hard_reset(cs48l32); > + > + regcache_cache_only(cs48l32->regmap, false); > + > + /* If we don't have a reset GPIO use a soft reset */ > + if (!cs48l32->reset_gpio) { > + ret = cs48l32_soft_reset(cs48l32); > + if (ret) > + goto err_reset; > + } > + > + ret = cs48l32_wait_for_boot(cs48l32); > + if (ret) { > + dev_err(cs48l32->dev, "Device failed initial boot: %d\n", ret); > + goto err_reset; > + } > + > + ret = regmap_read(cs48l32->regmap, CS48L32_DEVID, &hwid); > + if (ret) { > + dev_err(dev, "Failed to read ID register: %d\n", ret); > + goto err_reset; > + } > + hwid &= CS48L32_DEVID_MASK; > + > + switch (hwid) { > + case CS48L31_SILICON_ID: > + case CS48L32_SILICON_ID: > + case CS48L33_SILICON_ID: > + break; > + default: > + dev_err(cs48l32->dev, "Unknown device ID: %x\n", hwid); > + ret = -EINVAL; > + goto err_reset; > + } > + > + ret = regmap_read(cs48l32->regmap, CS48L32_REVID, &rev); > + if (ret) { > + dev_err(dev, "Failed to read revision register: %d\n", ret); > + goto err_reset; > + } > + rev &= CS48L32_AREVID_MASK | CS48L32_MTLREVID_MASK; > + > + ret = regmap_read(cs48l32->regmap, CS48L32_OTPID, &otp_rev); > + if (ret) { > + dev_err(dev, "Failed to read OTP revision register: %d\n", ret); > + goto err_reset; > + } > + otp_rev &= CS48L32_OTPID_MASK; > + > + cs48l32->part = hwid & 0xff; > + > + dev_info(dev, "CS48L%x revision %X%u.%u\n", cs48l32->part, > + rev >> CS48L32_AREVID_SHIFT, rev & CS48L32_MTLREVID_MASK, otp_rev); > + > + /* Apply hardware patch */ > + ret = cs48l32_patch(cs48l32); > + if (ret) { > + dev_err(cs48l32->dev, "Failed to apply patch %d\n", ret); > + goto err_reset; > + } > + > + ret = cs48l32_configure_clk32k(cs48l32); > + if (ret) > + goto err_reset; > + > + pm_runtime_set_active(cs48l32->dev); > + pm_runtime_enable(cs48l32->dev); > + pm_runtime_set_autosuspend_delay(cs48l32->dev, 100); > + pm_runtime_use_autosuspend(cs48l32->dev); > + > + ret = mfd_add_devices(cs48l32->dev, PLATFORM_DEVID_NONE, > + cs48l32_devs, ARRAY_SIZE(cs48l32_devs), NULL, 0, NULL); > + if (ret) { > + dev_err(cs48l32->dev, "Failed to add subdevices: %d\n", ret); > + goto err_clk32k; > + } > + > + return 0; > + > +err_clk32k: > + clk_disable_unprepare(cs48l32->mclk1); > +err_reset: > + cs48l32_enable_hard_reset(cs48l32); > + regulator_disable(cs48l32->vdd_d); > +err_enable: > + regulator_bulk_disable(cs48l32->num_core_supplies, cs48l32->core_supplies); > + > + return ret; > +} > + > +static void cs48l32_spi_remove(struct spi_device *spi) > +{ > + struct cs48l32_mfd *cs48l32 = spi_get_drvdata(spi); > + > + /* Prevent any IRQs being serviced while we clean up */ > + disable_irq(cs48l32->irq); > + > + mfd_remove_devices(cs48l32->dev); devm_*? > + pm_runtime_disable(cs48l32->dev); > + regulator_disable(cs48l32->vdd_d); > + clk_disable_unprepare(cs48l32->mclk1); > + cs48l32_enable_hard_reset(cs48l32); > + regulator_bulk_disable(cs48l32->num_core_supplies, cs48l32->core_supplies); > +} > + > +static const struct spi_device_id cs48l32_spi_ids[] = { > + { "cs48l31", }, > + { "cs48l32", }, > + { "cs48l33", }, > + { }, > +}; > +MODULE_DEVICE_TABLE(spi, cs48l32_spi_ids); > + > +static struct spi_driver cs48l32_spi_driver = { > + .driver = { > + .name = "cs48l32", > + .owner = THIS_MODULE, > + .pm = &cs48l32_pm_ops, > + .of_match_table = of_match_ptr(cs48l32_of_match), > + }, > + .probe = &cs48l32_spi_probe, > + .remove = &cs48l32_spi_remove, > + .id_table = cs48l32_spi_ids, > +}; > + Remove this line please. > +module_spi_driver(cs48l32_spi_driver); > + > +MODULE_SOFTDEP("pre: pinctrl-cs48l32 irq-cirrus-cs48l32"); > +MODULE_DESCRIPTION("CS48L32 MFD driver"); !MFD > +MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); > +MODULE_LICENSE("GPL"); > diff --git a/drivers/mfd/cs48l32.h b/drivers/mfd/cs48l32.h > new file mode 100644 > index 000000000000..36020c0cd686 > --- /dev/null > +++ b/drivers/mfd/cs48l32.h > @@ -0,0 +1,28 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * MFD for Cirrus Logic CS48L32 audio codec. !MFD > + * Copyright (C) 2016-2018, 2020, 2022 Cirrus Logic, Inc. and > + * Cirrus Logic International Semiconductor Ltd. > + */ > + > +#ifndef CS48L32_MFD_H > +#define CS48L32_MFD_H MFD_ at the front please. > +#include <linux/bits.h> > + > +#define CS48L31_SILICON_ID 0x48a31 > +#define CS48L32_SILICON_ID 0x48a32 > +#define CS48L33_SILICON_ID 0x48a33 > + > +#define CS48L32_32K_MCLK1 0 > + > +#define CS48L32_SFT_RESET_MAGIC 0x5a000000 > +#define CS48L32_SEEN_BOOT_DONE BIT(0) > + > +#define CS48L32_BOOT_TIMEOUT_MS 25 > + > +int cs48l32_init_regmap(struct spi_device *spi, struct cs48l32_mfd *cs48l32); > +int cs48l32_patch(struct cs48l32_mfd *cs48l32); > + > +#endif > diff --git a/include/linux/mfd/cs48l32/core.h b/include/linux/mfd/cs48l32/core.h > new file mode 100644 > index 000000000000..1c4269d70c8c > --- /dev/null > +++ b/include/linux/mfd/cs48l32/core.h > @@ -0,0 +1,49 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * MFD for Cirrus Logic CS48L32 audio codec. !MFD > + * Copyright (C) 2016-2020, 2022 Cirrus Logic, Inc. and > + * Cirrus Logic International Semiconductor Ltd. > + */ > + > +#ifndef CS48L32_CORE_H > +#define CS48L32_CORE_H > + > +#include <linux/clk.h> > +#include <linux/gpio/consumer.h> > +#include <linux/interrupt.h> > +#include <linux/notifier.h> > +#include <linux/regmap.h> > +#include <linux/regulator/consumer.h> > + > +#define CS48L32_MAX_CORE_SUPPLIES 2 > + > +struct snd_soc_dapm_context; > + > +struct cs48l32_mfd { !mfd > + struct regmap *regmap; > + struct device *dev; > + struct gpio_desc *reset_gpio; > + struct clk *mclk1; > + struct snd_soc_dapm_context *dapm; > + > + int num_core_supplies; > + struct regulator_bulk_data core_supplies[CS48L32_MAX_CORE_SUPPLIES]; > + struct regulator *vdd_d; > + > + struct device *irq_dev; > + struct regmap_irq_chip_data *irq_data; > + int irq; > + > + u8 part; > + > + struct blocking_notifier_head notifier; > +}; > + > +static inline int cs48l32_call_notifiers(struct cs48l32_mfd *mfd, > + unsigned long event, > + void *data) > +{ > + return blocking_notifier_call_chain(&mfd->notifier, event, data); > +} > +#endif -- Lee Jones [李琼斯] ^ permalink raw reply [flat|nested] 98+ messages in thread
* [PATCH 04/12] dt-bindings: pinctrl: Add Cirrus Logic CS48L31/32/33 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-09 16:53 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches, Richard Fitzgerald Codecs in this family have multiple digital I/O functions for audio, DSP subsystem, GPIO and various special functions. All muxable pins are selectable as either a GPIO or one of the available alternate functions. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- .../bindings/pinctrl/cirrus,cs48l32.yaml | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml new file mode 100644 index 000000000000..b24fbae6a8f8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/cirrus,cs48l32.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CS48L32 audio codec pinctrl driver + +maintainers: + - patches@opensource.cirrus.com + +description: | +The Cirrus Logic CS48L32 codec has a number of GPIO functions for +interfacing to external hardware. Certain groups of GPIO pins also +have an alternate function. + +The properties for this driver exist within the parent MFD driver node. +See the core bindings for the parent MFD driver for an example: + + Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml + +And the generic pinctrl bindings: + + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +properties: + pin-settings: + description: + One subnode is required to contain the default settings. It + contains an arbitrary number of configuration subnodes, one for + each group or pin configuration you want to apply as a default. + type: object + patternProperties: + '-pins$': + type: object + allOf: + - $ref: "pincfg-node.yaml#" + - $ref: "pinmux-node.yaml#" + properties: + groups: + description: + Name of one pin group to configure. + enum: [ asp1, asp2, in1-pdm, in2-pdm, + gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, + gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, + gpio14, gpio15, gpio16 ] + + function: + description: + Name of function to assign to this group. + enum: [ asp1, asp2, in1-pdm, in2-pdm, spi2, io, dsp-gpio, + irq1, fll1-clk, fll1-lock, opclk, opclk-dsp, uart, + input-path-signal-detect, + ultrasonic-in1-activity-detect, ultrasonic-in2-activity-detect, + dma-ch0-programmable-transfer-complete, + dma-ch1-programmable-transfer-complete, + dma-ch2-programmable-transfer-complete, + dma-ch3-programmable-transfer-complete, + dma-ch4-programmable-transfer-complete, + dma-ch5-programmable-transfer-complete, + dma-ch6-programmable-transfer-complete, + dma-ch7-programmable-transfer-complete, + sample-rate-change-trigger-a, sample-rate-change-trigger-b, + sample-rate-change-trigger-c, sample-rate-change-trigger-d, + timer1-irq-ch1, timer1-irq-ch2, timer1-irq-ch3, timer1-irq-ch4, + timer2-irq-ch1, timer2-irq-ch2, timer2-irq-ch3, timer2-irq-ch4, + timer3-irq-ch1, timer3-irq-ch2, timer3-irq-ch3, timer3-irq-ch4, + timer4-irq-ch1, timer4-irq-ch2, timer4-irq-ch3, timer4-irq-ch4, + timer5-irq-ch1, timer5-irq-ch2, timer5-irq-ch3, timer5-irq-ch4, + timer-1, timer-2, timer-3, timer-4, timer-5 ] + + bias-disable: true + + bias-bus-hold: true + + bias-pull-up: true + + bias-pull-down: true + + drive-push-pull: true + + drive-open-drain: true + + drive-strength: + description: + Drive strength in mA. + enum: [ 4, 8 ] + + output-low: true + + output-high: true + + additionalProperties: false + + required: + - groups + + additionalProperties: false -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 04/12] dt-bindings: pinctrl: Add Cirrus Logic CS48L31/32/33 @ 2022-11-09 16:53 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio, Richard Fitzgerald Codecs in this family have multiple digital I/O functions for audio, DSP subsystem, GPIO and various special functions. All muxable pins are selectable as either a GPIO or one of the available alternate functions. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- .../bindings/pinctrl/cirrus,cs48l32.yaml | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml new file mode 100644 index 000000000000..b24fbae6a8f8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/cirrus,cs48l32.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CS48L32 audio codec pinctrl driver + +maintainers: + - patches@opensource.cirrus.com + +description: | +The Cirrus Logic CS48L32 codec has a number of GPIO functions for +interfacing to external hardware. Certain groups of GPIO pins also +have an alternate function. + +The properties for this driver exist within the parent MFD driver node. +See the core bindings for the parent MFD driver for an example: + + Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml + +And the generic pinctrl bindings: + + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +properties: + pin-settings: + description: + One subnode is required to contain the default settings. It + contains an arbitrary number of configuration subnodes, one for + each group or pin configuration you want to apply as a default. + type: object + patternProperties: + '-pins$': + type: object + allOf: + - $ref: "pincfg-node.yaml#" + - $ref: "pinmux-node.yaml#" + properties: + groups: + description: + Name of one pin group to configure. + enum: [ asp1, asp2, in1-pdm, in2-pdm, + gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, + gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, + gpio14, gpio15, gpio16 ] + + function: + description: + Name of function to assign to this group. + enum: [ asp1, asp2, in1-pdm, in2-pdm, spi2, io, dsp-gpio, + irq1, fll1-clk, fll1-lock, opclk, opclk-dsp, uart, + input-path-signal-detect, + ultrasonic-in1-activity-detect, ultrasonic-in2-activity-detect, + dma-ch0-programmable-transfer-complete, + dma-ch1-programmable-transfer-complete, + dma-ch2-programmable-transfer-complete, + dma-ch3-programmable-transfer-complete, + dma-ch4-programmable-transfer-complete, + dma-ch5-programmable-transfer-complete, + dma-ch6-programmable-transfer-complete, + dma-ch7-programmable-transfer-complete, + sample-rate-change-trigger-a, sample-rate-change-trigger-b, + sample-rate-change-trigger-c, sample-rate-change-trigger-d, + timer1-irq-ch1, timer1-irq-ch2, timer1-irq-ch3, timer1-irq-ch4, + timer2-irq-ch1, timer2-irq-ch2, timer2-irq-ch3, timer2-irq-ch4, + timer3-irq-ch1, timer3-irq-ch2, timer3-irq-ch3, timer3-irq-ch4, + timer4-irq-ch1, timer4-irq-ch2, timer4-irq-ch3, timer4-irq-ch4, + timer5-irq-ch1, timer5-irq-ch2, timer5-irq-ch3, timer5-irq-ch4, + timer-1, timer-2, timer-3, timer-4, timer-5 ] + + bias-disable: true + + bias-bus-hold: true + + bias-pull-up: true + + bias-pull-down: true + + drive-push-pull: true + + drive-open-drain: true + + drive-strength: + description: + Drive strength in mA. + enum: [ 4, 8 ] + + output-low: true + + output-high: true + + additionalProperties: false + + required: + - groups + + additionalProperties: false -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* Re: [PATCH 04/12] dt-bindings: pinctrl: Add Cirrus Logic CS48L31/32/33 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-09 21:09 ` Rob Herring -1 siblings, 0 replies; 98+ messages in thread From: Rob Herring @ 2022-11-09 21:09 UTC (permalink / raw) To: Richard Fitzgerald Cc: alsa-devel, linus.walleij, patches, linux-gpio, devicetree, tglx, krzysztof.kozlowski+dt, linux-kernel, robh+dt, maz, broonie, lee On Wed, 09 Nov 2022 16:53:23 +0000, Richard Fitzgerald wrote: > Codecs in this family have multiple digital I/O functions for audio, > DSP subsystem, GPIO and various special functions. All muxable pins > are selectable as either a GPIO or one of the available alternate > functions. > > Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> > --- > .../bindings/pinctrl/cirrus,cs48l32.yaml | 98 +++++++++++++++++++ > 1 file changed, 98 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml:14:1: [error] syntax error: could not find expected ':' (syntax) dtschema/dtc warnings/errors: make[1]: *** Deleting file 'Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.example.dts' Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml:14:1: could not find expected ':' make[1]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.example.dts] Error 1 make[1]: *** Waiting for unfinished jobs.... ./Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml:14:1: could not find expected ':' /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml: ignoring, error parsing file make: *** [Makefile:1492: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml: Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 04/12] dt-bindings: pinctrl: Add Cirrus Logic CS48L31/32/33 @ 2022-11-09 21:09 ` Rob Herring 0 siblings, 0 replies; 98+ messages in thread From: Rob Herring @ 2022-11-09 21:09 UTC (permalink / raw) To: Richard Fitzgerald Cc: devicetree, alsa-devel, patches, linus.walleij, lee, linux-kernel, linux-gpio, robh+dt, broonie, krzysztof.kozlowski+dt, maz, tglx On Wed, 09 Nov 2022 16:53:23 +0000, Richard Fitzgerald wrote: > Codecs in this family have multiple digital I/O functions for audio, > DSP subsystem, GPIO and various special functions. All muxable pins > are selectable as either a GPIO or one of the available alternate > functions. > > Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> > --- > .../bindings/pinctrl/cirrus,cs48l32.yaml | 98 +++++++++++++++++++ > 1 file changed, 98 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml:14:1: [error] syntax error: could not find expected ':' (syntax) dtschema/dtc warnings/errors: make[1]: *** Deleting file 'Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.example.dts' Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml:14:1: could not find expected ':' make[1]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.example.dts] Error 1 make[1]: *** Waiting for unfinished jobs.... ./Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml:14:1: could not find expected ':' /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml: ignoring, error parsing file make: *** [Makefile:1492: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml: Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 04/12] dt-bindings: pinctrl: Add Cirrus Logic CS48L31/32/33 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-14 8:39 ` Krzysztof Kozlowski -1 siblings, 0 replies; 98+ messages in thread From: Krzysztof Kozlowski @ 2022-11-14 8:39 UTC (permalink / raw) To: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches On 09/11/2022 17:53, Richard Fitzgerald wrote: > Codecs in this family have multiple digital I/O functions for audio, > DSP subsystem, GPIO and various special functions. All muxable pins > are selectable as either a GPIO or one of the available alternate > functions. > > Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> > --- > .../bindings/pinctrl/cirrus,cs48l32.yaml | 98 +++++++++++++++++++ > 1 file changed, 98 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml > new file mode 100644 > index 000000000000..b24fbae6a8f8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml > @@ -0,0 +1,98 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/cirrus,cs48l32.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Cirrus Logic CS48L32 audio codec pinctrl driver Drop driver. s/pinctrl/Pin Controller/ > + > +maintainers: > + - patches@opensource.cirrus.com > + > +description: | > +The Cirrus Logic CS48L32 codec has a number of GPIO functions for > +interfacing to external hardware. Certain groups of GPIO pins also > +have an alternate function. > + > +The properties for this driver exist within the parent MFD driver node. Drop driver... so probably entire sentence. > +See the core bindings for the parent MFD driver for an example: Drop driver. Describe hardware instead. > + > + Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml > + > +And the generic pinctrl bindings: > + > + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt Drop entire sentence. > + > +properties: Your schema does not match on its own. Where is the compatible? This is not how schemas for devices (also MFD) is done. > + pin-settings: > + description: > + One subnode is required to contain the default settings. It > + contains an arbitrary number of configuration subnodes, one for > + each group or pin configuration you want to apply as a default. > + type: object > + patternProperties: > + '-pins$': > + type: object > + allOf: > + - $ref: "pincfg-node.yaml#" > + - $ref: "pinmux-node.yaml#" Drop quotes. Except this, test your patches before sending. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 04/12] dt-bindings: pinctrl: Add Cirrus Logic CS48L31/32/33 @ 2022-11-14 8:39 ` Krzysztof Kozlowski 0 siblings, 0 replies; 98+ messages in thread From: Krzysztof Kozlowski @ 2022-11-14 8:39 UTC (permalink / raw) To: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio On 09/11/2022 17:53, Richard Fitzgerald wrote: > Codecs in this family have multiple digital I/O functions for audio, > DSP subsystem, GPIO and various special functions. All muxable pins > are selectable as either a GPIO or one of the available alternate > functions. > > Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> > --- > .../bindings/pinctrl/cirrus,cs48l32.yaml | 98 +++++++++++++++++++ > 1 file changed, 98 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml > new file mode 100644 > index 000000000000..b24fbae6a8f8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml > @@ -0,0 +1,98 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/cirrus,cs48l32.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Cirrus Logic CS48L32 audio codec pinctrl driver Drop driver. s/pinctrl/Pin Controller/ > + > +maintainers: > + - patches@opensource.cirrus.com > + > +description: | > +The Cirrus Logic CS48L32 codec has a number of GPIO functions for > +interfacing to external hardware. Certain groups of GPIO pins also > +have an alternate function. > + > +The properties for this driver exist within the parent MFD driver node. Drop driver... so probably entire sentence. > +See the core bindings for the parent MFD driver for an example: Drop driver. Describe hardware instead. > + > + Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml > + > +And the generic pinctrl bindings: > + > + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt Drop entire sentence. > + > +properties: Your schema does not match on its own. Where is the compatible? This is not how schemas for devices (also MFD) is done. > + pin-settings: > + description: > + One subnode is required to contain the default settings. It > + contains an arbitrary number of configuration subnodes, one for > + each group or pin configuration you want to apply as a default. > + type: object > + patternProperties: > + '-pins$': > + type: object > + allOf: > + - $ref: "pincfg-node.yaml#" > + - $ref: "pinmux-node.yaml#" Drop quotes. Except this, test your patches before sending. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 98+ messages in thread
* [PATCH 05/12] pinctrl: cirrus: Add support for CS48L31/32/33 codecs 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-09 16:53 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches, Richard Fitzgerald From: Piotr Stankiewicz <piotrs@opensource.cirrus.com> Codecs in this family have multiple digital I/O functions for audio, DSP subsystem, GPIO and various special functions. All muxable pins are selectable as either a GPIO or an alternate function. Signed-off-by: Piotr Stankiewicz <piotrs@opensource.cirrus.com> Signed-off-by: Qi Zhou <qi.zhou@cirrus.com> Signed-off-by: Stuart Henderson <stuarth@opensource.cirrus.com> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- MAINTAINERS | 1 + drivers/pinctrl/cirrus/Kconfig | 5 + drivers/pinctrl/cirrus/Makefile | 2 + drivers/pinctrl/cirrus/pinctrl-cs48l32.c | 932 +++++++++++++++++++++++ drivers/pinctrl/cirrus/pinctrl-cs48l32.h | 62 ++ 5 files changed, 1002 insertions(+) create mode 100644 drivers/pinctrl/cirrus/pinctrl-cs48l32.c create mode 100644 drivers/pinctrl/cirrus/pinctrl-cs48l32.h diff --git a/MAINTAINERS b/MAINTAINERS index f1d696f29f11..cd1773d39dd8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5011,6 +5011,7 @@ W: https://github.com/CirrusLogic/linux-drivers/wiki T: git https://github.com/CirrusLogic/linux-drivers.git F: Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml F: Documentation/devicetree/bindings/mfd/cirrus,madera.yaml +F: Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml F: Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml F: Documentation/devicetree/bindings/sound/cirrus,madera.yaml F: drivers/gpio/gpio-madera* diff --git a/drivers/pinctrl/cirrus/Kconfig b/drivers/pinctrl/cirrus/Kconfig index 530426a74f75..c51192bde87a 100644 --- a/drivers/pinctrl/cirrus/Kconfig +++ b/drivers/pinctrl/cirrus/Kconfig @@ -30,3 +30,8 @@ config PINCTRL_CS47L90 config PINCTRL_CS47L92 bool + +config PINCTRL_CS48L32 + tristate + select PINMUX + select GENERIC_PINCONF diff --git a/drivers/pinctrl/cirrus/Makefile b/drivers/pinctrl/cirrus/Makefile index a484518c840e..18290f6be00c 100644 --- a/drivers/pinctrl/cirrus/Makefile +++ b/drivers/pinctrl/cirrus/Makefile @@ -19,4 +19,6 @@ ifeq ($(CONFIG_PINCTRL_CS47L92),y) pinctrl-madera-objs += pinctrl-cs47l92.o endif +obj-$(CONFIG_PINCTRL_CS48L32) += pinctrl-cs48l32.o + obj-$(CONFIG_PINCTRL_MADERA) += pinctrl-madera.o diff --git a/drivers/pinctrl/cirrus/pinctrl-cs48l32.c b/drivers/pinctrl/cirrus/pinctrl-cs48l32.c new file mode 100644 index 000000000000..cb5031d6d0ce --- /dev/null +++ b/drivers/pinctrl/cirrus/pinctrl-cs48l32.c @@ -0,0 +1,932 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Pinctrl for Cirrus Logic CS48L32 + * + * Copyright (C) 2017-2018, 2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ +#include <linux/err.h> +#include <linux/mfd/cs48l32/core.h> +#include <linux/mfd/cs48l32/registers.h> +#include <linux/module.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/slab.h> + +#include "../pinctrl-utils.h" +#include "pinctrl-cs48l32.h" + +/* + * Pins are named after their GPIO number + * NOTE: IDs are zero-indexed for coding convenience + */ +static const struct pinctrl_pin_desc cs48l32_pins[] = { + PINCTRL_PIN(0, "gpio1"), + PINCTRL_PIN(1, "gpio2"), + PINCTRL_PIN(2, "gpio3"), + PINCTRL_PIN(3, "gpio4"), + PINCTRL_PIN(4, "gpio5"), + PINCTRL_PIN(5, "gpio6"), + PINCTRL_PIN(6, "gpio7"), + PINCTRL_PIN(7, "gpio8"), + PINCTRL_PIN(8, "gpio9"), + PINCTRL_PIN(9, "gpio10"), + PINCTRL_PIN(10, "gpio11"), + PINCTRL_PIN(11, "gpio12"), + PINCTRL_PIN(12, "gpio13"), + PINCTRL_PIN(13, "gpio14"), + PINCTRL_PIN(14, "gpio15"), + PINCTRL_PIN(15, "gpio16"), +}; + +/* + * All single-pin functions can be mapped to any GPIO, however pinmux applies + * functions to pin groups and only those groups declared as supporting that + * function. To make this work we must put each pin in its own dummy group so + * that the functions can be described as applying to all pins. + * Since these do not correspond to anything in the actual hardware - they are + * merely an adaptation to pinctrl's view of the world - we use the same name + * as the pin to avoid confusion when comparing with datasheet instructions + */ +static const char * const cs48l32_pin_single_group_names[] = { + "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", +}; + +/* set of pin numbers for single-pin groups */ +static const unsigned int cs48l32_pin_single_group_pins[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, +}; + +static const char * const cs48l32_asp1_group_names[] = { "asp1" }; +static const char * const cs48l32_asp2_group_names[] = { "asp2" }; +static const char * const cs48l32_in1pdm_group_names[] = { "in1-pdm" }; +static const char * const cs48l32_in2pdm_group_names[] = { "in2-pdm" }; +static const char * const cs48l32_spi2_group_names[] = { "spi2" }; + +/* + * alt-functions always apply to only one group, other functions always + * apply to all pins + */ +static const struct { + const char *name; + const char * const *group_names; + u32 func; +} cs48l32_mux_funcs[] = { + { + .name = "asp1", + .group_names = cs48l32_asp1_group_names, + .func = 0x000 + }, + { + .name = "asp2", + .group_names = cs48l32_asp2_group_names, + .func = 0x000 + }, + { + .name = "in1-pdm", + .group_names = cs48l32_in1pdm_group_names, + .func = 0x000 + }, + { + .name = "in2-pdm", + .group_names = cs48l32_in2pdm_group_names, + .func = 0x000, + }, + { + .name = "spi2", + .group_names = cs48l32_spi2_group_names, + .func = 0x000 + }, + { + .name = "io", + .group_names = cs48l32_pin_single_group_names, + .func = 0x001 + }, + { + .name = "dsp-gpio", + .group_names = cs48l32_pin_single_group_names, + .func = 0x002 + }, + { + .name = "irq1", + .group_names = cs48l32_pin_single_group_names, + .func = 0x003 + }, + { + .name = "fll1-clk", + .group_names = cs48l32_pin_single_group_names, + .func = 0x010 + }, + { + .name = "fll1-lock", + .group_names = cs48l32_pin_single_group_names, + .func = 0x018 + }, + { + .name = "opclk", + .group_names = cs48l32_pin_single_group_names, + .func = 0x048 + }, + { + .name = "opclk-dsp", + .group_names = cs48l32_pin_single_group_names, + .func = 0x04a + }, + { + .name = "uart", + .group_names = cs48l32_pin_single_group_names, + .func = 0x04c + }, + { + .name = "input-path-signal-detect", + .group_names = cs48l32_pin_single_group_names, + .func = 0x08c + }, + { + .name = "ultrasonic-in1-activity-detect", + .group_names = cs48l32_pin_single_group_names, + .func = 0x090 + }, + { + .name = "ultrasonic-in2-activity-detect", + .group_names = cs48l32_pin_single_group_names, + .func = 0x092 + }, + { + .name = "dma-ch0-programmable-transfer-complete", + .group_names = cs48l32_pin_single_group_names, + .func = 0x190 + }, + { + .name = "dma-ch1-programmable-transfer-complete", + .group_names = cs48l32_pin_single_group_names, + .func = 0x191 + }, + { + .name = "dma-ch2-programmable-transfer-complete", + .group_names = cs48l32_pin_single_group_names, + .func = 0x192 + }, + { + .name = "dma-ch3-programmable-transfer-complete", + .group_names = cs48l32_pin_single_group_names, + .func = 0x193 + }, + { + .name = "dma-ch4-programmable-transfer-complete", + .group_names = cs48l32_pin_single_group_names, + .func = 0x194 + }, + { + .name = "dma-ch5-programmable-transfer-complete", + .group_names = cs48l32_pin_single_group_names, + .func = 0x195 + }, + { + .name = "dma-ch6-programmable-transfer-complete", + .group_names = cs48l32_pin_single_group_names, + .func = 0x196 + }, + { + .name = "dma-ch7-programmable-transfer-complete", + .group_names = cs48l32_pin_single_group_names, + .func = 0x197 + }, + { + .name = "sample-rate-change-trigger-a", + .group_names = cs48l32_pin_single_group_names, + .func = 0x214 + }, + { + .name = "sample-rate-change-trigger-b", + .group_names = cs48l32_pin_single_group_names, + .func = 0x215 + }, + { + .name = "sample-rate-change-trigger-c", + .group_names = cs48l32_pin_single_group_names, + .func = 0x216 + }, + { + .name = "sample-rate-change-trigger-d", + .group_names = cs48l32_pin_single_group_names, + .func = 0x217 + }, + { + .name = "timer1-irq-ch1", + .group_names = cs48l32_pin_single_group_names, + .func = 0x230 + }, + { + .name = "timer1-irq-ch2", + .group_names = cs48l32_pin_single_group_names, + .func = 0x231 + }, + { + .name = "timer1-irq-ch3", + .group_names = cs48l32_pin_single_group_names, + .func = 0x232 + }, + { + .name = "timer1-irq-ch4", + .group_names = cs48l32_pin_single_group_names, + .func = 0x233 + }, + { + .name = "timer2-irq-ch1", + .group_names = cs48l32_pin_single_group_names, + .func = 0x234 + }, + { + .name = "timer2-irq-ch2", + .group_names = cs48l32_pin_single_group_names, + .func = 0x235 + }, + { + .name = "timer2-irq-ch3", + .group_names = cs48l32_pin_single_group_names, + .func = 0x236 + }, + { + .name = "timer2-irq-ch4", + .group_names = cs48l32_pin_single_group_names, + .func = 0x237 + }, + { + .name = "timer3-irq-ch1", + .group_names = cs48l32_pin_single_group_names, + .func = 0x238 + }, + { + .name = "timer3-irq-ch2", + .group_names = cs48l32_pin_single_group_names, + .func = 0x239 + }, + { + .name = "timer3-irq-ch3", + .group_names = cs48l32_pin_single_group_names, + .func = 0x23a + }, + { + .name = "timer3-irq-ch4", + .group_names = cs48l32_pin_single_group_names, + .func = 0x23b + }, + { + .name = "timer4-irq-ch1", + .group_names = cs48l32_pin_single_group_names, + .func = 0x23c + }, + { + .name = "timer4-irq-ch2", + .group_names = cs48l32_pin_single_group_names, + .func = 0x23d + }, + { + .name = "timer4-irq-ch3", + .group_names = cs48l32_pin_single_group_names, + .func = 0x23e + }, + { + .name = "timer4-irq-ch4", + .group_names = cs48l32_pin_single_group_names, + .func = 0x23f + }, + { + .name = "timer5-irq-ch1", + .group_names = cs48l32_pin_single_group_names, + .func = 0x240 + }, + { + .name = "timer5-irq-ch2", + .group_names = cs48l32_pin_single_group_names, + .func = 0x241 + }, + { + .name = "timer5-irq-ch3", + .group_names = cs48l32_pin_single_group_names, + .func = 0x242 + }, + { + .name = "timer5-irq-ch4", + .group_names = cs48l32_pin_single_group_names, + .func = 0x243 + }, + { + .name = "timer-1", + .group_names = cs48l32_pin_single_group_names, + .func = 0x250 + }, + { + .name = "timer-2", + .group_names = cs48l32_pin_single_group_names, + .func = 0x251 + }, + { + .name = "timer-3", + .group_names = cs48l32_pin_single_group_names, + .func = 0x252 + }, + { + .name = "timer-4", + .group_names = cs48l32_pin_single_group_names, + .func = 0x253 + }, + { + .name = "timer-5", + .group_names = cs48l32_pin_single_group_names, + .func = 0x254 + }, +}; + +/* Note - all 1 less than in datasheet because these are zero-indexed */ +static const unsigned int cs48l32_asp1_pins[] = { 2, 3, 4, 5 }; +static const unsigned int cs48l32_asp2_pins[] = { 6, 7, 8, 9 }; +static const unsigned int cs48l32_spi2_pins[] = { 10, 11, 12, 13, 14, 15 }; + +static const struct cs48l32_pin_groups cs48l32_pin_groups[] = { + { "asp1", cs48l32_asp1_pins, ARRAY_SIZE(cs48l32_asp1_pins) }, + { "asp2", cs48l32_asp2_pins, ARRAY_SIZE(cs48l32_asp2_pins) }, + { "spi2", cs48l32_spi2_pins, ARRAY_SIZE(cs48l32_spi2_pins) }, +}; + +static const struct cs48l32_pin_chip cs48l32_pin_chip = { + .n_pins = CS48L32_NUM_GPIOS, + .pin_groups = cs48l32_pin_groups, + .n_pin_groups = ARRAY_SIZE(cs48l32_pin_groups), +}; + +static unsigned int cs48l32_pin_make_drv_str(struct cs48l32_pin_private *priv, + unsigned int milliamps) +{ + switch (milliamps) { + case 4: + return 0; + case 8: + return 1 << CS48L32_GP_DRV_STR_SHIFT; + default: + break; + } + + dev_warn(priv->dev, "%u mA is not a valid drive strength\n", milliamps); + + return 0; +} + +static unsigned int cs48l32_pin_unmake_drv_str(struct cs48l32_pin_private *priv, + unsigned int regval) +{ + regval = (regval & CS48L32_GP_DRV_STR_MASK) >> CS48L32_GP_DRV_STR_SHIFT; + + switch (regval) { + case 0: + return 4; + case 1: + return 8; + default: + break; + } + + return 0; +} + +static int cs48l32_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + + /* Number of alt function groups plus number of single-pin groups */ + return priv->chip->n_pin_groups + priv->chip->n_pins; +} + +static const char *cs48l32_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + + if (selector < priv->chip->n_pin_groups) + return priv->chip->pin_groups[selector].name; + + selector -= priv->chip->n_pin_groups; + + return cs48l32_pin_single_group_names[selector]; +} + +static int cs48l32_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + + if (selector < priv->chip->n_pin_groups) { + *pins = priv->chip->pin_groups[selector].pins; + *num_pins = priv->chip->pin_groups[selector].n_pins; + } else { + /* return the dummy group for a single pin */ + selector -= priv->chip->n_pin_groups; + *pins = &cs48l32_pin_single_group_pins[selector]; + *num_pins = 1; + } + + return 0; +} + +static void cs48l32_pin_dbg_show_fn(struct cs48l32_pin_private *priv, + struct seq_file *s, + unsigned int pin, unsigned int fn) +{ + const struct cs48l32_pin_chip *chip = priv->chip; + int i, g_pin; + + if (fn != 0) { + for (i = 0; i < ARRAY_SIZE(cs48l32_mux_funcs); ++i) { + if (cs48l32_mux_funcs[i].func == fn) { + seq_printf(s, " FN=%s", cs48l32_mux_funcs[i].name); + return; + } + } + return; /* ignore unknown function values */ + } + + /* alt function */ + for (i = 0; i < chip->n_pin_groups; ++i) { + for (g_pin = 0; g_pin < chip->pin_groups[i].n_pins; ++g_pin) { + if (chip->pin_groups[i].pins[g_pin] == pin) { + seq_printf(s, " FN=%s", chip->pin_groups[i].name); + return; + } + } + } +} + +static void cs48l32_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + unsigned int reg = CS48L32_GPIO1_CTRL1 + (4 * pin); + unsigned int conf, fn; + int ret; + + ret = regmap_read(priv->mfd->regmap, reg, &conf); + if (ret) + return; + + seq_printf(s, "%08x", conf); + + fn = (conf & CS48L32_GP_FN_MASK) >> CS48L32_GP_FN_SHIFT; + cs48l32_pin_dbg_show_fn(priv, s, pin, fn); + + /* State of direction bit is only relevant if function==1 */ + if (fn == 1) { + if (conf & CS48L32_GP_DIR_MASK) + seq_puts(s, " IN"); + else + seq_puts(s, " OUT"); + } + + if (conf & CS48L32_GP_PU_MASK) + seq_puts(s, " PU"); + + if (conf & CS48L32_GP_PD_MASK) + seq_puts(s, " PD"); + + if (conf & CS48L32_GP_DB_MASK) + seq_puts(s, " DB"); + + if (conf & CS48L32_GP_OP_CFG_MASK) + seq_puts(s, " OD"); + else + seq_puts(s, " CMOS"); + + seq_printf(s, " DRV=%umA", cs48l32_pin_unmake_drv_str(priv, conf)); +} + + +static const struct pinctrl_ops cs48l32_pin_group_ops = { + .get_groups_count = &cs48l32_get_groups_count, + .get_group_name = &cs48l32_get_group_name, + .get_group_pins = &cs48l32_get_group_pins, + .pin_dbg_show = &cs48l32_pin_dbg_show, + .dt_node_to_map = &pinconf_generic_dt_node_to_map_all, + .dt_free_map = &pinctrl_utils_free_map, +}; + +static int cs48l32_mux_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(cs48l32_mux_funcs); +} + +static const char *cs48l32_mux_get_func_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return cs48l32_mux_funcs[selector].name; +} + +static int cs48l32_mux_get_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + + *groups = cs48l32_mux_funcs[selector].group_names; + + if (cs48l32_mux_funcs[selector].func == 0) { + /* alt func always maps to a single group */ + *num_groups = 1; + } else { + /* other funcs map to all available gpio pins */ + *num_groups = priv->chip->n_pins; + } + + return 0; +} + +static int cs48l32_mux_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, + unsigned int group) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + struct cs48l32_mfd *mfd = priv->mfd; + const struct cs48l32_pin_groups *pin_group = priv->chip->pin_groups; + unsigned int n_chip_groups = priv->chip->n_pin_groups; + const char *func_name = cs48l32_mux_funcs[selector].name; + unsigned int reg; + int i, ret; + + dev_dbg(priv->dev, "%s selecting %u (%s) for group %u (%s)\n", + __func__, selector, func_name, group, + cs48l32_get_group_name(pctldev, group)); + + if (cs48l32_mux_funcs[selector].func == 0) { + /* alt func pin assignments are codec-specific */ + for (i = 0; i < n_chip_groups; ++i) { + if (strcmp(func_name, pin_group->name) == 0) + break; + + ++pin_group; + } + + if (i == n_chip_groups) + return -EINVAL; + + for (i = 0; i < pin_group->n_pins; ++i) { + reg = CS48L32_GPIO1_CTRL1 + (4 * pin_group->pins[i]); + + dev_dbg(priv->dev, "%s setting 0x%x func bits to 0\n", __func__, reg); + + ret = regmap_update_bits(mfd->regmap, reg, CS48L32_GP_FN_MASK, 0); + if (ret) + break; + + } + } else { + /* + * for other funcs the group will be the gpio number and will + * be offset by the number of chip-specific functions at the + * start of the group list + */ + group -= n_chip_groups; + reg = CS48L32_GPIO1_CTRL1 + (4 * group); + + dev_dbg(priv->dev, "%s setting 0x%x func bits to 0x%x\n", + __func__, reg, cs48l32_mux_funcs[selector].func); + + ret = regmap_update_bits(mfd->regmap, + reg, + CS48L32_GP_FN_MASK, + cs48l32_mux_funcs[selector].func); + } + + if (ret) + dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret); + + return ret; +} + +static int cs48l32_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin, + bool input) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + struct cs48l32_mfd *mfd = priv->mfd; + unsigned int reg = CS48L32_GPIO1_CTRL1 + (4 * pin); + unsigned int val; + int ret; + + if (input) + val = CS48L32_GP_DIR_MASK; + else + val = 0; + + ret = regmap_update_bits(mfd->regmap, reg, CS48L32_GP_DIR_MASK, val); + if (ret) + dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret); + + return ret; +} + +static int cs48l32_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + struct cs48l32_mfd *mfd = priv->mfd; + unsigned int reg = CS48L32_GPIO1_CTRL1 + (4 * pin); + int ret; + + /* put the pin into GPIO mode */ + ret = regmap_update_bits(mfd->regmap, reg, CS48L32_GP_FN_MASK, 1); + if (ret) + dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret); + + return ret; +} + +static void cs48l32_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + struct cs48l32_mfd *mfd = priv->mfd; + unsigned int reg = CS48L32_GPIO1_CTRL1 + (4 * pin); + int ret; + + /* disable GPIO by setting to GPIO IN */ + cs48l32_gpio_set_direction(pctldev, range, pin, true); + + ret = regmap_update_bits(mfd->regmap, reg, CS48L32_GP_FN_MASK, 1); + if (ret) + dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret); +} +static const struct pinmux_ops cs48l32_pin_mux_ops = { + .get_functions_count = &cs48l32_mux_get_funcs_count, + .get_function_name = &cs48l32_mux_get_func_name, + .get_function_groups = &cs48l32_mux_get_groups, + .set_mux = &cs48l32_mux_set_mux, + .gpio_request_enable = &cs48l32_gpio_request_enable, + .gpio_disable_free = &cs48l32_gpio_disable_free, + .gpio_set_direction = &cs48l32_gpio_set_direction, + .strict = true, /* GPIO and other functions are exclusive */ +}; + +static int cs48l32_pin_conf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + unsigned int param = pinconf_to_config_param(*config); + unsigned int result = 0; + unsigned int conf; + int ret; + + ret = regmap_read(priv->mfd->regmap, CS48L32_GPIO1_CTRL1 + (4 * pin), &conf); + if (ret) { + dev_err(priv->dev, "Failed to read GP%d conf (%d)\n", pin + 1, ret); + return ret; + } + + switch (param) { + case PIN_CONFIG_BIAS_BUS_HOLD: + conf &= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + if (conf == (CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK)) + result = 1; + break; + case PIN_CONFIG_BIAS_DISABLE: + conf &= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + if (!conf) + result = 1; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + conf &= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + if (conf == CS48L32_GP_PD_MASK) + result = 1; + break; + case PIN_CONFIG_BIAS_PULL_UP: + conf &= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + if (conf == CS48L32_GP_PU_MASK) + result = 1; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (conf & CS48L32_GP_OP_CFG_MASK) + result = 1; + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (!(conf & CS48L32_GP_OP_CFG_MASK)) + result = 1; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + result = cs48l32_pin_unmake_drv_str(priv, conf); + break; + case PIN_CONFIG_INPUT_DEBOUNCE: + dev_dbg(priv->dev, "Input debounce time not supported."); + break; + case PIN_CONFIG_INPUT_ENABLE: + if (conf & CS48L32_GP_DIR_MASK) + result = 1; + break; + case PIN_CONFIG_OUTPUT: + if ((conf & CS48L32_GP_DIR_MASK) && (conf & CS48L32_GP_LVL_MASK)) + result = 1; + break; + default: + return -EINVAL; + } + + *config = pinconf_to_config_packed(param, result); + + return 0; +} + +static int cs48l32_pin_conf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + unsigned int conf = 0; + unsigned int mask = 0; + unsigned int reg = CS48L32_GPIO1_CTRL1 + (4 * pin); + unsigned int val; + int ret; + + while (num_configs) { + dev_dbg(priv->dev, "%s config 0x%lx\n", __func__, *configs); + + switch (pinconf_to_config_param(*configs)) { + case PIN_CONFIG_BIAS_BUS_HOLD: + mask |= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + conf |= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + break; + case PIN_CONFIG_BIAS_DISABLE: + mask |= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + conf &= ~(CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + mask |= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + conf |= CS48L32_GP_PD_MASK; + conf &= ~CS48L32_GP_PU_MASK; + break; + case PIN_CONFIG_BIAS_PULL_UP: + mask |= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + conf |= CS48L32_GP_PU_MASK; + conf &= ~CS48L32_GP_PD_MASK; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + mask |= CS48L32_GP_OP_CFG_MASK; + conf |= CS48L32_GP_OP_CFG_MASK; + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + mask |= CS48L32_GP_OP_CFG_MASK; + conf &= ~CS48L32_GP_OP_CFG_MASK; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + val = pinconf_to_config_argument(*configs); + mask |= CS48L32_GP_DRV_STR_MASK; + conf &= ~CS48L32_GP_DRV_STR_MASK; + conf |= cs48l32_pin_make_drv_str(priv, val); + break; + case PIN_CONFIG_INPUT_DEBOUNCE: + dev_dbg(priv->dev, "Input debounce time not supported."); + break; + case PIN_CONFIG_INPUT_ENABLE: + val = pinconf_to_config_argument(*configs); + mask |= CS48L32_GP_DIR_MASK; + if (val) + conf |= CS48L32_GP_DIR_MASK; + else + conf &= ~CS48L32_GP_DIR_MASK; + break; + case PIN_CONFIG_OUTPUT: + val = pinconf_to_config_argument(*configs); + mask |= CS48L32_GP_LVL_MASK; + if (val) + conf |= CS48L32_GP_LVL_MASK; + else + conf &= ~CS48L32_GP_LVL_MASK; + + mask |= CS48L32_GP_DIR_MASK; + conf &= ~CS48L32_GP_DIR_MASK; + break; + default: + return -EINVAL; + } + + ++configs; + --num_configs; + } + + dev_dbg(priv->dev, "%s gpio%d 0x%x:0x%x\n", __func__, pin + 1, reg, conf); + + ret = regmap_update_bits(priv->mfd->regmap, reg, mask, conf); + if (ret) + dev_err(priv->dev, "Failed to write GPIO%d conf (%d) reg 0x%x\n", + pin + 1, ret, reg); + + return ret; +} + +static int cs48l32_pin_conf_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + const struct cs48l32_pin_groups *pin_group; + unsigned int n_groups = priv->chip->n_pin_groups; + int i, ret; + + dev_dbg(priv->dev, "%s setting group %s\n", __func__, + cs48l32_get_group_name(pctldev, selector)); + + if (selector >= n_groups) { + /* group is a single pin, convert to pin number and set */ + return cs48l32_pin_conf_set(pctldev, + selector - n_groups, + configs, + num_configs); + } else { + pin_group = &priv->chip->pin_groups[selector]; + + for (i = 0; i < pin_group->n_pins; ++i) { + ret = cs48l32_pin_conf_set(pctldev, + pin_group->pins[i], + configs, + num_configs); + if (ret) + return ret; + } + } + + return 0; +} + +static const struct pinconf_ops cs48l32_pin_conf_ops = { + .is_generic = true, + .pin_config_get = &cs48l32_pin_conf_get, + .pin_config_set = &cs48l32_pin_conf_set, + .pin_config_group_set = &cs48l32_pin_conf_group_set, + +}; + +static struct pinctrl_desc cs48l32_pin_desc = { + .name = "cs48l32-pinctrl", + .pins = cs48l32_pins, + .pctlops = &cs48l32_pin_group_ops, + .pmxops = &cs48l32_pin_mux_ops, + .confops = &cs48l32_pin_conf_ops, + .owner = THIS_MODULE, +}; + +static int cs48l32_pin_probe(struct platform_device *pdev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(pdev->dev.parent); + struct cs48l32_pin_private *priv; + int ret; + + BUILD_BUG_ON(ARRAY_SIZE(cs48l32_pin_single_group_names) != + ARRAY_SIZE(cs48l32_pin_single_group_pins)); + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + priv->mfd = mfd; + /* Composite MFD device so shares the parent OF node. */ + pdev->dev.of_node = mfd->dev->of_node; + + priv->chip = &cs48l32_pin_chip; + cs48l32_pin_desc.npins = priv->chip->n_pins; + + ret = devm_pinctrl_register_and_init(&pdev->dev, &cs48l32_pin_desc, priv, &priv->pctl); + if (ret) + return dev_err_probe(priv->dev, ret, "Failed pinctrl register\n"); + + ret = pinctrl_enable(priv->pctl); + if (ret) + return dev_err_probe(priv->dev, ret, "Failed to enable pinctrl\n"); + + platform_set_drvdata(pdev, priv); + + dev_dbg(priv->dev, "pinctrl registered\n"); + + return 0; +} + +static struct platform_driver cs48l32_pin_driver = { + .probe = &cs48l32_pin_probe, + .driver = { + .name = "cs48l32-pinctrl", + }, +}; + +module_platform_driver(cs48l32_pin_driver); + +MODULE_DESCRIPTION("CS48L32 pinctrl driver"); +MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); +MODULE_AUTHOR("Piotr Stankiewicz <piotrs@opensource.cirrus.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/cirrus/pinctrl-cs48l32.h b/drivers/pinctrl/cirrus/pinctrl-cs48l32.h new file mode 100644 index 000000000000..2193c7558dd3 --- /dev/null +++ b/drivers/pinctrl/cirrus/pinctrl-cs48l32.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Pinctrl for Cirrus Logic CS48L32 + * + * Copyright (C) 2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef PINCTRL_CS48L32_H +#define PINCTRL_CS48L32_H + +#include <linux/device.h> +#include <linux/mfd/cs48l32/core.h> + +struct pinctrl_dev; + +#define CS48L32_GP_DIR_MASK 0x80000000 +#define CS48L32_GP_DIR_SHIFT 31 +#define CS48L32_GP_PU_MASK 0x40000000 +#define CS48L32_GP_PU_SHIFT 30 +#define CS48L32_GP_PD_MASK 0x20000000 +#define CS48L32_GP_PD_SHIFT 29 +#define CS48L32_GP_DRV_STR_MASK 0x03000000 +#define CS48L32_GP_DRV_STR_SHIFT 24 +#define CS48L32_GP_DBTIME_MASK 0x000f0000 +#define CS48L32_GP_DBTIME_SHIFT 16 +#define CS48L32_GP_LVL_MASK 0x00008000 +#define CS48L32_GP_LVL_SHIFT 15 +#define CS48L32_GP_OP_CFG_MASK 0x00004000 +#define CS48L32_GP_OP_CFG_SHIFT 14 +#define CS48L32_GP_DB_MASK 0x00002000 +#define CS48L32_GP_DB_SHIFT 13 +#define CS48L32_GP_POL_MASK 0x00001000 +#define CS48L32_GP_POL_SHIFT 12 +#define CS48L32_GP_FN_MASK 0x000007ff +#define CS48L32_GP_FN_SHIFT 0 + +#define CS48L32_NUM_GPIOS 16 + +struct cs48l32_pin_groups { + const char *name; + const unsigned int *pins; + unsigned int n_pins; +}; + +struct cs48l32_pin_chip { + unsigned int n_pins; + + const struct cs48l32_pin_groups *pin_groups; + unsigned int n_pin_groups; +}; + +struct cs48l32_pin_private { + struct cs48l32_mfd *mfd; + + const struct cs48l32_pin_chip *chip; /* chip-specific groups */ + + struct device *dev; + struct pinctrl_dev *pctl; +}; + +#endif -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 05/12] pinctrl: cirrus: Add support for CS48L31/32/33 codecs @ 2022-11-09 16:53 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio, Richard Fitzgerald From: Piotr Stankiewicz <piotrs@opensource.cirrus.com> Codecs in this family have multiple digital I/O functions for audio, DSP subsystem, GPIO and various special functions. All muxable pins are selectable as either a GPIO or an alternate function. Signed-off-by: Piotr Stankiewicz <piotrs@opensource.cirrus.com> Signed-off-by: Qi Zhou <qi.zhou@cirrus.com> Signed-off-by: Stuart Henderson <stuarth@opensource.cirrus.com> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- MAINTAINERS | 1 + drivers/pinctrl/cirrus/Kconfig | 5 + drivers/pinctrl/cirrus/Makefile | 2 + drivers/pinctrl/cirrus/pinctrl-cs48l32.c | 932 +++++++++++++++++++++++ drivers/pinctrl/cirrus/pinctrl-cs48l32.h | 62 ++ 5 files changed, 1002 insertions(+) create mode 100644 drivers/pinctrl/cirrus/pinctrl-cs48l32.c create mode 100644 drivers/pinctrl/cirrus/pinctrl-cs48l32.h diff --git a/MAINTAINERS b/MAINTAINERS index f1d696f29f11..cd1773d39dd8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5011,6 +5011,7 @@ W: https://github.com/CirrusLogic/linux-drivers/wiki T: git https://github.com/CirrusLogic/linux-drivers.git F: Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml F: Documentation/devicetree/bindings/mfd/cirrus,madera.yaml +F: Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml F: Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml F: Documentation/devicetree/bindings/sound/cirrus,madera.yaml F: drivers/gpio/gpio-madera* diff --git a/drivers/pinctrl/cirrus/Kconfig b/drivers/pinctrl/cirrus/Kconfig index 530426a74f75..c51192bde87a 100644 --- a/drivers/pinctrl/cirrus/Kconfig +++ b/drivers/pinctrl/cirrus/Kconfig @@ -30,3 +30,8 @@ config PINCTRL_CS47L90 config PINCTRL_CS47L92 bool + +config PINCTRL_CS48L32 + tristate + select PINMUX + select GENERIC_PINCONF diff --git a/drivers/pinctrl/cirrus/Makefile b/drivers/pinctrl/cirrus/Makefile index a484518c840e..18290f6be00c 100644 --- a/drivers/pinctrl/cirrus/Makefile +++ b/drivers/pinctrl/cirrus/Makefile @@ -19,4 +19,6 @@ ifeq ($(CONFIG_PINCTRL_CS47L92),y) pinctrl-madera-objs += pinctrl-cs47l92.o endif +obj-$(CONFIG_PINCTRL_CS48L32) += pinctrl-cs48l32.o + obj-$(CONFIG_PINCTRL_MADERA) += pinctrl-madera.o diff --git a/drivers/pinctrl/cirrus/pinctrl-cs48l32.c b/drivers/pinctrl/cirrus/pinctrl-cs48l32.c new file mode 100644 index 000000000000..cb5031d6d0ce --- /dev/null +++ b/drivers/pinctrl/cirrus/pinctrl-cs48l32.c @@ -0,0 +1,932 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Pinctrl for Cirrus Logic CS48L32 + * + * Copyright (C) 2017-2018, 2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ +#include <linux/err.h> +#include <linux/mfd/cs48l32/core.h> +#include <linux/mfd/cs48l32/registers.h> +#include <linux/module.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/slab.h> + +#include "../pinctrl-utils.h" +#include "pinctrl-cs48l32.h" + +/* + * Pins are named after their GPIO number + * NOTE: IDs are zero-indexed for coding convenience + */ +static const struct pinctrl_pin_desc cs48l32_pins[] = { + PINCTRL_PIN(0, "gpio1"), + PINCTRL_PIN(1, "gpio2"), + PINCTRL_PIN(2, "gpio3"), + PINCTRL_PIN(3, "gpio4"), + PINCTRL_PIN(4, "gpio5"), + PINCTRL_PIN(5, "gpio6"), + PINCTRL_PIN(6, "gpio7"), + PINCTRL_PIN(7, "gpio8"), + PINCTRL_PIN(8, "gpio9"), + PINCTRL_PIN(9, "gpio10"), + PINCTRL_PIN(10, "gpio11"), + PINCTRL_PIN(11, "gpio12"), + PINCTRL_PIN(12, "gpio13"), + PINCTRL_PIN(13, "gpio14"), + PINCTRL_PIN(14, "gpio15"), + PINCTRL_PIN(15, "gpio16"), +}; + +/* + * All single-pin functions can be mapped to any GPIO, however pinmux applies + * functions to pin groups and only those groups declared as supporting that + * function. To make this work we must put each pin in its own dummy group so + * that the functions can be described as applying to all pins. + * Since these do not correspond to anything in the actual hardware - they are + * merely an adaptation to pinctrl's view of the world - we use the same name + * as the pin to avoid confusion when comparing with datasheet instructions + */ +static const char * const cs48l32_pin_single_group_names[] = { + "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", +}; + +/* set of pin numbers for single-pin groups */ +static const unsigned int cs48l32_pin_single_group_pins[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, +}; + +static const char * const cs48l32_asp1_group_names[] = { "asp1" }; +static const char * const cs48l32_asp2_group_names[] = { "asp2" }; +static const char * const cs48l32_in1pdm_group_names[] = { "in1-pdm" }; +static const char * const cs48l32_in2pdm_group_names[] = { "in2-pdm" }; +static const char * const cs48l32_spi2_group_names[] = { "spi2" }; + +/* + * alt-functions always apply to only one group, other functions always + * apply to all pins + */ +static const struct { + const char *name; + const char * const *group_names; + u32 func; +} cs48l32_mux_funcs[] = { + { + .name = "asp1", + .group_names = cs48l32_asp1_group_names, + .func = 0x000 + }, + { + .name = "asp2", + .group_names = cs48l32_asp2_group_names, + .func = 0x000 + }, + { + .name = "in1-pdm", + .group_names = cs48l32_in1pdm_group_names, + .func = 0x000 + }, + { + .name = "in2-pdm", + .group_names = cs48l32_in2pdm_group_names, + .func = 0x000, + }, + { + .name = "spi2", + .group_names = cs48l32_spi2_group_names, + .func = 0x000 + }, + { + .name = "io", + .group_names = cs48l32_pin_single_group_names, + .func = 0x001 + }, + { + .name = "dsp-gpio", + .group_names = cs48l32_pin_single_group_names, + .func = 0x002 + }, + { + .name = "irq1", + .group_names = cs48l32_pin_single_group_names, + .func = 0x003 + }, + { + .name = "fll1-clk", + .group_names = cs48l32_pin_single_group_names, + .func = 0x010 + }, + { + .name = "fll1-lock", + .group_names = cs48l32_pin_single_group_names, + .func = 0x018 + }, + { + .name = "opclk", + .group_names = cs48l32_pin_single_group_names, + .func = 0x048 + }, + { + .name = "opclk-dsp", + .group_names = cs48l32_pin_single_group_names, + .func = 0x04a + }, + { + .name = "uart", + .group_names = cs48l32_pin_single_group_names, + .func = 0x04c + }, + { + .name = "input-path-signal-detect", + .group_names = cs48l32_pin_single_group_names, + .func = 0x08c + }, + { + .name = "ultrasonic-in1-activity-detect", + .group_names = cs48l32_pin_single_group_names, + .func = 0x090 + }, + { + .name = "ultrasonic-in2-activity-detect", + .group_names = cs48l32_pin_single_group_names, + .func = 0x092 + }, + { + .name = "dma-ch0-programmable-transfer-complete", + .group_names = cs48l32_pin_single_group_names, + .func = 0x190 + }, + { + .name = "dma-ch1-programmable-transfer-complete", + .group_names = cs48l32_pin_single_group_names, + .func = 0x191 + }, + { + .name = "dma-ch2-programmable-transfer-complete", + .group_names = cs48l32_pin_single_group_names, + .func = 0x192 + }, + { + .name = "dma-ch3-programmable-transfer-complete", + .group_names = cs48l32_pin_single_group_names, + .func = 0x193 + }, + { + .name = "dma-ch4-programmable-transfer-complete", + .group_names = cs48l32_pin_single_group_names, + .func = 0x194 + }, + { + .name = "dma-ch5-programmable-transfer-complete", + .group_names = cs48l32_pin_single_group_names, + .func = 0x195 + }, + { + .name = "dma-ch6-programmable-transfer-complete", + .group_names = cs48l32_pin_single_group_names, + .func = 0x196 + }, + { + .name = "dma-ch7-programmable-transfer-complete", + .group_names = cs48l32_pin_single_group_names, + .func = 0x197 + }, + { + .name = "sample-rate-change-trigger-a", + .group_names = cs48l32_pin_single_group_names, + .func = 0x214 + }, + { + .name = "sample-rate-change-trigger-b", + .group_names = cs48l32_pin_single_group_names, + .func = 0x215 + }, + { + .name = "sample-rate-change-trigger-c", + .group_names = cs48l32_pin_single_group_names, + .func = 0x216 + }, + { + .name = "sample-rate-change-trigger-d", + .group_names = cs48l32_pin_single_group_names, + .func = 0x217 + }, + { + .name = "timer1-irq-ch1", + .group_names = cs48l32_pin_single_group_names, + .func = 0x230 + }, + { + .name = "timer1-irq-ch2", + .group_names = cs48l32_pin_single_group_names, + .func = 0x231 + }, + { + .name = "timer1-irq-ch3", + .group_names = cs48l32_pin_single_group_names, + .func = 0x232 + }, + { + .name = "timer1-irq-ch4", + .group_names = cs48l32_pin_single_group_names, + .func = 0x233 + }, + { + .name = "timer2-irq-ch1", + .group_names = cs48l32_pin_single_group_names, + .func = 0x234 + }, + { + .name = "timer2-irq-ch2", + .group_names = cs48l32_pin_single_group_names, + .func = 0x235 + }, + { + .name = "timer2-irq-ch3", + .group_names = cs48l32_pin_single_group_names, + .func = 0x236 + }, + { + .name = "timer2-irq-ch4", + .group_names = cs48l32_pin_single_group_names, + .func = 0x237 + }, + { + .name = "timer3-irq-ch1", + .group_names = cs48l32_pin_single_group_names, + .func = 0x238 + }, + { + .name = "timer3-irq-ch2", + .group_names = cs48l32_pin_single_group_names, + .func = 0x239 + }, + { + .name = "timer3-irq-ch3", + .group_names = cs48l32_pin_single_group_names, + .func = 0x23a + }, + { + .name = "timer3-irq-ch4", + .group_names = cs48l32_pin_single_group_names, + .func = 0x23b + }, + { + .name = "timer4-irq-ch1", + .group_names = cs48l32_pin_single_group_names, + .func = 0x23c + }, + { + .name = "timer4-irq-ch2", + .group_names = cs48l32_pin_single_group_names, + .func = 0x23d + }, + { + .name = "timer4-irq-ch3", + .group_names = cs48l32_pin_single_group_names, + .func = 0x23e + }, + { + .name = "timer4-irq-ch4", + .group_names = cs48l32_pin_single_group_names, + .func = 0x23f + }, + { + .name = "timer5-irq-ch1", + .group_names = cs48l32_pin_single_group_names, + .func = 0x240 + }, + { + .name = "timer5-irq-ch2", + .group_names = cs48l32_pin_single_group_names, + .func = 0x241 + }, + { + .name = "timer5-irq-ch3", + .group_names = cs48l32_pin_single_group_names, + .func = 0x242 + }, + { + .name = "timer5-irq-ch4", + .group_names = cs48l32_pin_single_group_names, + .func = 0x243 + }, + { + .name = "timer-1", + .group_names = cs48l32_pin_single_group_names, + .func = 0x250 + }, + { + .name = "timer-2", + .group_names = cs48l32_pin_single_group_names, + .func = 0x251 + }, + { + .name = "timer-3", + .group_names = cs48l32_pin_single_group_names, + .func = 0x252 + }, + { + .name = "timer-4", + .group_names = cs48l32_pin_single_group_names, + .func = 0x253 + }, + { + .name = "timer-5", + .group_names = cs48l32_pin_single_group_names, + .func = 0x254 + }, +}; + +/* Note - all 1 less than in datasheet because these are zero-indexed */ +static const unsigned int cs48l32_asp1_pins[] = { 2, 3, 4, 5 }; +static const unsigned int cs48l32_asp2_pins[] = { 6, 7, 8, 9 }; +static const unsigned int cs48l32_spi2_pins[] = { 10, 11, 12, 13, 14, 15 }; + +static const struct cs48l32_pin_groups cs48l32_pin_groups[] = { + { "asp1", cs48l32_asp1_pins, ARRAY_SIZE(cs48l32_asp1_pins) }, + { "asp2", cs48l32_asp2_pins, ARRAY_SIZE(cs48l32_asp2_pins) }, + { "spi2", cs48l32_spi2_pins, ARRAY_SIZE(cs48l32_spi2_pins) }, +}; + +static const struct cs48l32_pin_chip cs48l32_pin_chip = { + .n_pins = CS48L32_NUM_GPIOS, + .pin_groups = cs48l32_pin_groups, + .n_pin_groups = ARRAY_SIZE(cs48l32_pin_groups), +}; + +static unsigned int cs48l32_pin_make_drv_str(struct cs48l32_pin_private *priv, + unsigned int milliamps) +{ + switch (milliamps) { + case 4: + return 0; + case 8: + return 1 << CS48L32_GP_DRV_STR_SHIFT; + default: + break; + } + + dev_warn(priv->dev, "%u mA is not a valid drive strength\n", milliamps); + + return 0; +} + +static unsigned int cs48l32_pin_unmake_drv_str(struct cs48l32_pin_private *priv, + unsigned int regval) +{ + regval = (regval & CS48L32_GP_DRV_STR_MASK) >> CS48L32_GP_DRV_STR_SHIFT; + + switch (regval) { + case 0: + return 4; + case 1: + return 8; + default: + break; + } + + return 0; +} + +static int cs48l32_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + + /* Number of alt function groups plus number of single-pin groups */ + return priv->chip->n_pin_groups + priv->chip->n_pins; +} + +static const char *cs48l32_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + + if (selector < priv->chip->n_pin_groups) + return priv->chip->pin_groups[selector].name; + + selector -= priv->chip->n_pin_groups; + + return cs48l32_pin_single_group_names[selector]; +} + +static int cs48l32_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + + if (selector < priv->chip->n_pin_groups) { + *pins = priv->chip->pin_groups[selector].pins; + *num_pins = priv->chip->pin_groups[selector].n_pins; + } else { + /* return the dummy group for a single pin */ + selector -= priv->chip->n_pin_groups; + *pins = &cs48l32_pin_single_group_pins[selector]; + *num_pins = 1; + } + + return 0; +} + +static void cs48l32_pin_dbg_show_fn(struct cs48l32_pin_private *priv, + struct seq_file *s, + unsigned int pin, unsigned int fn) +{ + const struct cs48l32_pin_chip *chip = priv->chip; + int i, g_pin; + + if (fn != 0) { + for (i = 0; i < ARRAY_SIZE(cs48l32_mux_funcs); ++i) { + if (cs48l32_mux_funcs[i].func == fn) { + seq_printf(s, " FN=%s", cs48l32_mux_funcs[i].name); + return; + } + } + return; /* ignore unknown function values */ + } + + /* alt function */ + for (i = 0; i < chip->n_pin_groups; ++i) { + for (g_pin = 0; g_pin < chip->pin_groups[i].n_pins; ++g_pin) { + if (chip->pin_groups[i].pins[g_pin] == pin) { + seq_printf(s, " FN=%s", chip->pin_groups[i].name); + return; + } + } + } +} + +static void cs48l32_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + unsigned int reg = CS48L32_GPIO1_CTRL1 + (4 * pin); + unsigned int conf, fn; + int ret; + + ret = regmap_read(priv->mfd->regmap, reg, &conf); + if (ret) + return; + + seq_printf(s, "%08x", conf); + + fn = (conf & CS48L32_GP_FN_MASK) >> CS48L32_GP_FN_SHIFT; + cs48l32_pin_dbg_show_fn(priv, s, pin, fn); + + /* State of direction bit is only relevant if function==1 */ + if (fn == 1) { + if (conf & CS48L32_GP_DIR_MASK) + seq_puts(s, " IN"); + else + seq_puts(s, " OUT"); + } + + if (conf & CS48L32_GP_PU_MASK) + seq_puts(s, " PU"); + + if (conf & CS48L32_GP_PD_MASK) + seq_puts(s, " PD"); + + if (conf & CS48L32_GP_DB_MASK) + seq_puts(s, " DB"); + + if (conf & CS48L32_GP_OP_CFG_MASK) + seq_puts(s, " OD"); + else + seq_puts(s, " CMOS"); + + seq_printf(s, " DRV=%umA", cs48l32_pin_unmake_drv_str(priv, conf)); +} + + +static const struct pinctrl_ops cs48l32_pin_group_ops = { + .get_groups_count = &cs48l32_get_groups_count, + .get_group_name = &cs48l32_get_group_name, + .get_group_pins = &cs48l32_get_group_pins, + .pin_dbg_show = &cs48l32_pin_dbg_show, + .dt_node_to_map = &pinconf_generic_dt_node_to_map_all, + .dt_free_map = &pinctrl_utils_free_map, +}; + +static int cs48l32_mux_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(cs48l32_mux_funcs); +} + +static const char *cs48l32_mux_get_func_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return cs48l32_mux_funcs[selector].name; +} + +static int cs48l32_mux_get_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + + *groups = cs48l32_mux_funcs[selector].group_names; + + if (cs48l32_mux_funcs[selector].func == 0) { + /* alt func always maps to a single group */ + *num_groups = 1; + } else { + /* other funcs map to all available gpio pins */ + *num_groups = priv->chip->n_pins; + } + + return 0; +} + +static int cs48l32_mux_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, + unsigned int group) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + struct cs48l32_mfd *mfd = priv->mfd; + const struct cs48l32_pin_groups *pin_group = priv->chip->pin_groups; + unsigned int n_chip_groups = priv->chip->n_pin_groups; + const char *func_name = cs48l32_mux_funcs[selector].name; + unsigned int reg; + int i, ret; + + dev_dbg(priv->dev, "%s selecting %u (%s) for group %u (%s)\n", + __func__, selector, func_name, group, + cs48l32_get_group_name(pctldev, group)); + + if (cs48l32_mux_funcs[selector].func == 0) { + /* alt func pin assignments are codec-specific */ + for (i = 0; i < n_chip_groups; ++i) { + if (strcmp(func_name, pin_group->name) == 0) + break; + + ++pin_group; + } + + if (i == n_chip_groups) + return -EINVAL; + + for (i = 0; i < pin_group->n_pins; ++i) { + reg = CS48L32_GPIO1_CTRL1 + (4 * pin_group->pins[i]); + + dev_dbg(priv->dev, "%s setting 0x%x func bits to 0\n", __func__, reg); + + ret = regmap_update_bits(mfd->regmap, reg, CS48L32_GP_FN_MASK, 0); + if (ret) + break; + + } + } else { + /* + * for other funcs the group will be the gpio number and will + * be offset by the number of chip-specific functions at the + * start of the group list + */ + group -= n_chip_groups; + reg = CS48L32_GPIO1_CTRL1 + (4 * group); + + dev_dbg(priv->dev, "%s setting 0x%x func bits to 0x%x\n", + __func__, reg, cs48l32_mux_funcs[selector].func); + + ret = regmap_update_bits(mfd->regmap, + reg, + CS48L32_GP_FN_MASK, + cs48l32_mux_funcs[selector].func); + } + + if (ret) + dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret); + + return ret; +} + +static int cs48l32_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin, + bool input) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + struct cs48l32_mfd *mfd = priv->mfd; + unsigned int reg = CS48L32_GPIO1_CTRL1 + (4 * pin); + unsigned int val; + int ret; + + if (input) + val = CS48L32_GP_DIR_MASK; + else + val = 0; + + ret = regmap_update_bits(mfd->regmap, reg, CS48L32_GP_DIR_MASK, val); + if (ret) + dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret); + + return ret; +} + +static int cs48l32_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + struct cs48l32_mfd *mfd = priv->mfd; + unsigned int reg = CS48L32_GPIO1_CTRL1 + (4 * pin); + int ret; + + /* put the pin into GPIO mode */ + ret = regmap_update_bits(mfd->regmap, reg, CS48L32_GP_FN_MASK, 1); + if (ret) + dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret); + + return ret; +} + +static void cs48l32_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + struct cs48l32_mfd *mfd = priv->mfd; + unsigned int reg = CS48L32_GPIO1_CTRL1 + (4 * pin); + int ret; + + /* disable GPIO by setting to GPIO IN */ + cs48l32_gpio_set_direction(pctldev, range, pin, true); + + ret = regmap_update_bits(mfd->regmap, reg, CS48L32_GP_FN_MASK, 1); + if (ret) + dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret); +} +static const struct pinmux_ops cs48l32_pin_mux_ops = { + .get_functions_count = &cs48l32_mux_get_funcs_count, + .get_function_name = &cs48l32_mux_get_func_name, + .get_function_groups = &cs48l32_mux_get_groups, + .set_mux = &cs48l32_mux_set_mux, + .gpio_request_enable = &cs48l32_gpio_request_enable, + .gpio_disable_free = &cs48l32_gpio_disable_free, + .gpio_set_direction = &cs48l32_gpio_set_direction, + .strict = true, /* GPIO and other functions are exclusive */ +}; + +static int cs48l32_pin_conf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + unsigned int param = pinconf_to_config_param(*config); + unsigned int result = 0; + unsigned int conf; + int ret; + + ret = regmap_read(priv->mfd->regmap, CS48L32_GPIO1_CTRL1 + (4 * pin), &conf); + if (ret) { + dev_err(priv->dev, "Failed to read GP%d conf (%d)\n", pin + 1, ret); + return ret; + } + + switch (param) { + case PIN_CONFIG_BIAS_BUS_HOLD: + conf &= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + if (conf == (CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK)) + result = 1; + break; + case PIN_CONFIG_BIAS_DISABLE: + conf &= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + if (!conf) + result = 1; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + conf &= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + if (conf == CS48L32_GP_PD_MASK) + result = 1; + break; + case PIN_CONFIG_BIAS_PULL_UP: + conf &= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + if (conf == CS48L32_GP_PU_MASK) + result = 1; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (conf & CS48L32_GP_OP_CFG_MASK) + result = 1; + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (!(conf & CS48L32_GP_OP_CFG_MASK)) + result = 1; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + result = cs48l32_pin_unmake_drv_str(priv, conf); + break; + case PIN_CONFIG_INPUT_DEBOUNCE: + dev_dbg(priv->dev, "Input debounce time not supported."); + break; + case PIN_CONFIG_INPUT_ENABLE: + if (conf & CS48L32_GP_DIR_MASK) + result = 1; + break; + case PIN_CONFIG_OUTPUT: + if ((conf & CS48L32_GP_DIR_MASK) && (conf & CS48L32_GP_LVL_MASK)) + result = 1; + break; + default: + return -EINVAL; + } + + *config = pinconf_to_config_packed(param, result); + + return 0; +} + +static int cs48l32_pin_conf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + unsigned int conf = 0; + unsigned int mask = 0; + unsigned int reg = CS48L32_GPIO1_CTRL1 + (4 * pin); + unsigned int val; + int ret; + + while (num_configs) { + dev_dbg(priv->dev, "%s config 0x%lx\n", __func__, *configs); + + switch (pinconf_to_config_param(*configs)) { + case PIN_CONFIG_BIAS_BUS_HOLD: + mask |= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + conf |= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + break; + case PIN_CONFIG_BIAS_DISABLE: + mask |= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + conf &= ~(CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + mask |= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + conf |= CS48L32_GP_PD_MASK; + conf &= ~CS48L32_GP_PU_MASK; + break; + case PIN_CONFIG_BIAS_PULL_UP: + mask |= CS48L32_GP_PU_MASK | CS48L32_GP_PD_MASK; + conf |= CS48L32_GP_PU_MASK; + conf &= ~CS48L32_GP_PD_MASK; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + mask |= CS48L32_GP_OP_CFG_MASK; + conf |= CS48L32_GP_OP_CFG_MASK; + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + mask |= CS48L32_GP_OP_CFG_MASK; + conf &= ~CS48L32_GP_OP_CFG_MASK; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + val = pinconf_to_config_argument(*configs); + mask |= CS48L32_GP_DRV_STR_MASK; + conf &= ~CS48L32_GP_DRV_STR_MASK; + conf |= cs48l32_pin_make_drv_str(priv, val); + break; + case PIN_CONFIG_INPUT_DEBOUNCE: + dev_dbg(priv->dev, "Input debounce time not supported."); + break; + case PIN_CONFIG_INPUT_ENABLE: + val = pinconf_to_config_argument(*configs); + mask |= CS48L32_GP_DIR_MASK; + if (val) + conf |= CS48L32_GP_DIR_MASK; + else + conf &= ~CS48L32_GP_DIR_MASK; + break; + case PIN_CONFIG_OUTPUT: + val = pinconf_to_config_argument(*configs); + mask |= CS48L32_GP_LVL_MASK; + if (val) + conf |= CS48L32_GP_LVL_MASK; + else + conf &= ~CS48L32_GP_LVL_MASK; + + mask |= CS48L32_GP_DIR_MASK; + conf &= ~CS48L32_GP_DIR_MASK; + break; + default: + return -EINVAL; + } + + ++configs; + --num_configs; + } + + dev_dbg(priv->dev, "%s gpio%d 0x%x:0x%x\n", __func__, pin + 1, reg, conf); + + ret = regmap_update_bits(priv->mfd->regmap, reg, mask, conf); + if (ret) + dev_err(priv->dev, "Failed to write GPIO%d conf (%d) reg 0x%x\n", + pin + 1, ret, reg); + + return ret; +} + +static int cs48l32_pin_conf_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + struct cs48l32_pin_private *priv = pinctrl_dev_get_drvdata(pctldev); + const struct cs48l32_pin_groups *pin_group; + unsigned int n_groups = priv->chip->n_pin_groups; + int i, ret; + + dev_dbg(priv->dev, "%s setting group %s\n", __func__, + cs48l32_get_group_name(pctldev, selector)); + + if (selector >= n_groups) { + /* group is a single pin, convert to pin number and set */ + return cs48l32_pin_conf_set(pctldev, + selector - n_groups, + configs, + num_configs); + } else { + pin_group = &priv->chip->pin_groups[selector]; + + for (i = 0; i < pin_group->n_pins; ++i) { + ret = cs48l32_pin_conf_set(pctldev, + pin_group->pins[i], + configs, + num_configs); + if (ret) + return ret; + } + } + + return 0; +} + +static const struct pinconf_ops cs48l32_pin_conf_ops = { + .is_generic = true, + .pin_config_get = &cs48l32_pin_conf_get, + .pin_config_set = &cs48l32_pin_conf_set, + .pin_config_group_set = &cs48l32_pin_conf_group_set, + +}; + +static struct pinctrl_desc cs48l32_pin_desc = { + .name = "cs48l32-pinctrl", + .pins = cs48l32_pins, + .pctlops = &cs48l32_pin_group_ops, + .pmxops = &cs48l32_pin_mux_ops, + .confops = &cs48l32_pin_conf_ops, + .owner = THIS_MODULE, +}; + +static int cs48l32_pin_probe(struct platform_device *pdev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(pdev->dev.parent); + struct cs48l32_pin_private *priv; + int ret; + + BUILD_BUG_ON(ARRAY_SIZE(cs48l32_pin_single_group_names) != + ARRAY_SIZE(cs48l32_pin_single_group_pins)); + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + priv->mfd = mfd; + /* Composite MFD device so shares the parent OF node. */ + pdev->dev.of_node = mfd->dev->of_node; + + priv->chip = &cs48l32_pin_chip; + cs48l32_pin_desc.npins = priv->chip->n_pins; + + ret = devm_pinctrl_register_and_init(&pdev->dev, &cs48l32_pin_desc, priv, &priv->pctl); + if (ret) + return dev_err_probe(priv->dev, ret, "Failed pinctrl register\n"); + + ret = pinctrl_enable(priv->pctl); + if (ret) + return dev_err_probe(priv->dev, ret, "Failed to enable pinctrl\n"); + + platform_set_drvdata(pdev, priv); + + dev_dbg(priv->dev, "pinctrl registered\n"); + + return 0; +} + +static struct platform_driver cs48l32_pin_driver = { + .probe = &cs48l32_pin_probe, + .driver = { + .name = "cs48l32-pinctrl", + }, +}; + +module_platform_driver(cs48l32_pin_driver); + +MODULE_DESCRIPTION("CS48L32 pinctrl driver"); +MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); +MODULE_AUTHOR("Piotr Stankiewicz <piotrs@opensource.cirrus.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/cirrus/pinctrl-cs48l32.h b/drivers/pinctrl/cirrus/pinctrl-cs48l32.h new file mode 100644 index 000000000000..2193c7558dd3 --- /dev/null +++ b/drivers/pinctrl/cirrus/pinctrl-cs48l32.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Pinctrl for Cirrus Logic CS48L32 + * + * Copyright (C) 2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef PINCTRL_CS48L32_H +#define PINCTRL_CS48L32_H + +#include <linux/device.h> +#include <linux/mfd/cs48l32/core.h> + +struct pinctrl_dev; + +#define CS48L32_GP_DIR_MASK 0x80000000 +#define CS48L32_GP_DIR_SHIFT 31 +#define CS48L32_GP_PU_MASK 0x40000000 +#define CS48L32_GP_PU_SHIFT 30 +#define CS48L32_GP_PD_MASK 0x20000000 +#define CS48L32_GP_PD_SHIFT 29 +#define CS48L32_GP_DRV_STR_MASK 0x03000000 +#define CS48L32_GP_DRV_STR_SHIFT 24 +#define CS48L32_GP_DBTIME_MASK 0x000f0000 +#define CS48L32_GP_DBTIME_SHIFT 16 +#define CS48L32_GP_LVL_MASK 0x00008000 +#define CS48L32_GP_LVL_SHIFT 15 +#define CS48L32_GP_OP_CFG_MASK 0x00004000 +#define CS48L32_GP_OP_CFG_SHIFT 14 +#define CS48L32_GP_DB_MASK 0x00002000 +#define CS48L32_GP_DB_SHIFT 13 +#define CS48L32_GP_POL_MASK 0x00001000 +#define CS48L32_GP_POL_SHIFT 12 +#define CS48L32_GP_FN_MASK 0x000007ff +#define CS48L32_GP_FN_SHIFT 0 + +#define CS48L32_NUM_GPIOS 16 + +struct cs48l32_pin_groups { + const char *name; + const unsigned int *pins; + unsigned int n_pins; +}; + +struct cs48l32_pin_chip { + unsigned int n_pins; + + const struct cs48l32_pin_groups *pin_groups; + unsigned int n_pin_groups; +}; + +struct cs48l32_pin_private { + struct cs48l32_mfd *mfd; + + const struct cs48l32_pin_chip *chip; /* chip-specific groups */ + + struct device *dev; + struct pinctrl_dev *pctl; +}; + +#endif -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* Re: [PATCH 05/12] pinctrl: cirrus: Add support for CS48L31/32/33 codecs 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-10 10:02 ` Linus Walleij -1 siblings, 0 replies; 98+ messages in thread From: Linus Walleij @ 2022-11-10 10:02 UTC (permalink / raw) To: Richard Fitzgerald Cc: lee, robh+dt, krzysztof.kozlowski+dt, broonie, tglx, maz, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On Wed, Nov 9, 2022 at 5:53 PM Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > From: Piotr Stankiewicz <piotrs@opensource.cirrus.com> > > Codecs in this family have multiple digital I/O functions for audio, > DSP subsystem, GPIO and various special functions. All muxable pins > are selectable as either a GPIO or an alternate function. > > Signed-off-by: Piotr Stankiewicz <piotrs@opensource.cirrus.com> > Signed-off-by: Qi Zhou <qi.zhou@cirrus.com> > Signed-off-by: Stuart Henderson <stuarth@opensource.cirrus.com> > Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> This looks OK. Acked-by: Linus Walleij <linus.walleij@linaro.org> Does this patch have compile-time dependencies on the other patches or is it something I can just merge separately? Yours, Linus Walleij ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 05/12] pinctrl: cirrus: Add support for CS48L31/32/33 codecs @ 2022-11-10 10:02 ` Linus Walleij 0 siblings, 0 replies; 98+ messages in thread From: Linus Walleij @ 2022-11-10 10:02 UTC (permalink / raw) To: Richard Fitzgerald Cc: devicetree, alsa-devel, maz, lee, linux-kernel, robh+dt, linux-gpio, broonie, krzysztof.kozlowski+dt, patches, tglx On Wed, Nov 9, 2022 at 5:53 PM Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > From: Piotr Stankiewicz <piotrs@opensource.cirrus.com> > > Codecs in this family have multiple digital I/O functions for audio, > DSP subsystem, GPIO and various special functions. All muxable pins > are selectable as either a GPIO or an alternate function. > > Signed-off-by: Piotr Stankiewicz <piotrs@opensource.cirrus.com> > Signed-off-by: Qi Zhou <qi.zhou@cirrus.com> > Signed-off-by: Stuart Henderson <stuarth@opensource.cirrus.com> > Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> This looks OK. Acked-by: Linus Walleij <linus.walleij@linaro.org> Does this patch have compile-time dependencies on the other patches or is it something I can just merge separately? Yours, Linus Walleij ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 05/12] pinctrl: cirrus: Add support for CS48L31/32/33 codecs 2022-11-10 10:02 ` Linus Walleij @ 2022-11-10 10:55 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-10 10:55 UTC (permalink / raw) To: Linus Walleij Cc: lee, robh+dt, krzysztof.kozlowski+dt, broonie, tglx, maz, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On 10/11/2022 10:02, Linus Walleij wrote: > On Wed, Nov 9, 2022 at 5:53 PM Richard Fitzgerald > <rf@opensource.cirrus.com> wrote: > >> From: Piotr Stankiewicz <piotrs@opensource.cirrus.com> >> >> Codecs in this family have multiple digital I/O functions for audio, >> DSP subsystem, GPIO and various special functions. All muxable pins >> are selectable as either a GPIO or an alternate function. >> >> Signed-off-by: Piotr Stankiewicz <piotrs@opensource.cirrus.com> >> Signed-off-by: Qi Zhou <qi.zhou@cirrus.com> >> Signed-off-by: Stuart Henderson <stuarth@opensource.cirrus.com> >> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> > > This looks OK. > Acked-by: Linus Walleij <linus.walleij@linaro.org> > > Does this patch have compile-time dependencies on the other > patches or is it something I can just merge separately? > It has compile-time dependencies on the MFD at least. I should have said that in the cover letter. > Yours, > Linus Walleij ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 05/12] pinctrl: cirrus: Add support for CS48L31/32/33 codecs @ 2022-11-10 10:55 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-10 10:55 UTC (permalink / raw) To: Linus Walleij Cc: devicetree, alsa-devel, maz, lee, linux-kernel, robh+dt, linux-gpio, broonie, krzysztof.kozlowski+dt, patches, tglx On 10/11/2022 10:02, Linus Walleij wrote: > On Wed, Nov 9, 2022 at 5:53 PM Richard Fitzgerald > <rf@opensource.cirrus.com> wrote: > >> From: Piotr Stankiewicz <piotrs@opensource.cirrus.com> >> >> Codecs in this family have multiple digital I/O functions for audio, >> DSP subsystem, GPIO and various special functions. All muxable pins >> are selectable as either a GPIO or an alternate function. >> >> Signed-off-by: Piotr Stankiewicz <piotrs@opensource.cirrus.com> >> Signed-off-by: Qi Zhou <qi.zhou@cirrus.com> >> Signed-off-by: Stuart Henderson <stuarth@opensource.cirrus.com> >> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> > > This looks OK. > Acked-by: Linus Walleij <linus.walleij@linaro.org> > > Does this patch have compile-time dependencies on the other > patches or is it something I can just merge separately? > It has compile-time dependencies on the MFD at least. I should have said that in the cover letter. > Yours, > Linus Walleij ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 05/12] pinctrl: cirrus: Add support for CS48L31/32/33 codecs 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-12 21:01 ` kernel test robot -1 siblings, 0 replies; 98+ messages in thread From: kernel test robot @ 2022-11-12 21:01 UTC (permalink / raw) To: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: oe-kbuild-all, alsa-devel, devicetree, linux-gpio, linux-kernel, patches, Richard Fitzgerald [-- Attachment #1: Type: text/plain, Size: 2103 bytes --] Hi Richard, Thank you for the patch! Yet something to improve: [auto build test ERROR on broonie-sound/for-next] [also build test ERROR on lee-mfd/for-mfd-next linusw-pinctrl/devel linusw-pinctrl/for-next broonie-regulator/for-next linus/master v6.1-rc4 next-20221111] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Richard-Fitzgerald/Add-support-for-the-Cirrus-Logic-CS48L32-audio-codecs/20221110-005630 base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next patch link: https://lore.kernel.org/r/20221109165331.29332-6-rf%40opensource.cirrus.com patch subject: [PATCH 05/12] pinctrl: cirrus: Add support for CS48L31/32/33 codecs config: s390-randconfig-c44-20221113 compiler: s390-linux-gcc (GCC) 12.1.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/intel-lab-lkp/linux/commit/23ae23e54f7ece974162bb1a195bd01addda9400 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Richard-Fitzgerald/Add-support-for-the-Cirrus-Logic-CS48L32-audio-codecs/20221110-005630 git checkout 23ae23e54f7ece974162bb1a195bd01addda9400 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=s390 SHELL=/bin/bash If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): s390-linux-ld: drivers/pinctrl/cirrus/pinctrl-cs48l32.o: in function `pinconf_generic_dt_node_to_map_all': >> pinctrl-cs48l32.c:(.text+0xa8c): undefined reference to `pinconf_generic_dt_node_to_map' -- 0-DAY CI Kernel Test Service https://01.org/lkp [-- Attachment #2: config --] [-- Type: text/plain, Size: 115479 bytes --] # # Automatically generated file; DO NOT EDIT. # Linux/s390 6.1.0-rc1 Kernel Configuration # CONFIG_CC_VERSION_TEXT="s390-linux-gcc (GCC) 12.1.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=120100 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y CONFIG_AS_VERSION=23800 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23800 CONFIG_LLD_VERSION=0 CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=123 CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y # # General setup # CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_COMPILE_TEST=y # CONFIG_WERROR is not set CONFIG_LOCALVERSION="" CONFIG_BUILD_SALT="" CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_BZIP2=y CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_XZ=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_HAVE_KERNEL_LZ4=y CONFIG_HAVE_KERNEL_ZSTD=y CONFIG_HAVE_KERNEL_UNCOMPRESSED=y # CONFIG_KERNEL_GZIP is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_LZMA=y # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set # CONFIG_KERNEL_ZSTD is not set # CONFIG_KERNEL_UNCOMPRESSED is not set CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SYSVIPC=y # CONFIG_WATCH_QUEUE is not set CONFIG_CROSS_MEMORY_ATTACH=y # CONFIG_USELIB is not set CONFIG_HAVE_ARCH_AUDITSYSCALL=y # # IRQ subsystem # CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_SIM=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_SPARSE_IRQ=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set # end of IRQ subsystem CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_TIME_KUNIT_TEST=m CONFIG_CONTEXT_TRACKING=y CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem # CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ_COMMON=y # CONFIG_HZ_PERIODIC is not set CONFIG_NO_HZ_IDLE=y # CONFIG_NO_HZ is not set CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem CONFIG_HAVE_EBPF_JIT=y CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y # # BPF subsystem # # CONFIG_BPF_SYSCALL is not set # end of BPF subsystem CONFIG_PREEMPT_VOLUNTARY_BUILD=y # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set CONFIG_PREEMPT_COUNT=y # # CPU/Task time and stats accounting # CONFIG_VIRT_CPU_ACCOUNTING=y CONFIG_VIRT_CPU_ACCOUNTING_NATIVE=y # CONFIG_PSI is not set # end of CPU/Task time and stats accounting CONFIG_CPU_ISOLATION=y # # RCU Subsystem # CONFIG_TREE_RCU=y CONFIG_RCU_EXPERT=y CONFIG_SRCU=y CONFIG_TREE_SRCU=y # CONFIG_FORCE_TASKS_RCU is not set # CONFIG_FORCE_TASKS_RUDE_RCU is not set # CONFIG_FORCE_TASKS_TRACE_RCU is not set CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y CONFIG_RCU_FANOUT=64 CONFIG_RCU_FANOUT_LEAF=16 # CONFIG_RCU_NOCB_CPU is not set # end of RCU Subsystem CONFIG_IKCONFIG=m # CONFIG_IKHEADERS is not set # # Scheduler features # # end of Scheduler features CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y CONFIG_CC_HAS_INT128=y CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y CONFIG_CGROUP_FAVOR_DYNMODS=y CONFIG_MEMCG=y CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_PIDS=y CONFIG_CGROUP_RDMA=y # CONFIG_CGROUP_FREEZER is not set # CONFIG_CGROUP_HUGETLB is not set # CONFIG_CPUSETS is not set CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y # CONFIG_CGROUP_PERF is not set CONFIG_CGROUP_MISC=y CONFIG_CGROUP_DEBUG=y CONFIG_SCHED_AUTOGROUP=y # CONFIG_SYSFS_DEPRECATED is not set CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" # CONFIG_RD_GZIP is not set CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y CONFIG_RD_XZ=y CONFIG_RD_LZO=y # CONFIG_RD_LZ4 is not set # CONFIG_RD_ZSTD is not set CONFIG_BOOT_CONFIG=y # CONFIG_BOOT_CONFIG_EMBED is not set CONFIG_INITRAMFS_PRESERVE_MTIME=y CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_EXPERT=y # CONFIG_MULTIUSER is not set # CONFIG_SGETMASK_SYSCALL is not set CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y # CONFIG_PRINTK is not set # CONFIG_BUG is not set CONFIG_BASE_FULL=y # CONFIG_FUTEX is not set CONFIG_EPOLL=y CONFIG_SIGNALFD=y # CONFIG_TIMERFD is not set CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y # CONFIG_KCMP is not set CONFIG_RSEQ=y # CONFIG_DEBUG_RSEQ is not set # CONFIG_EMBEDDED is not set CONFIG_HAVE_PERF_EVENTS=y CONFIG_PC104=y # # Kernel Performance Events And Counters # CONFIG_PERF_EVENTS=y # CONFIG_DEBUG_PERF_USE_VMALLOC is not set # end of Kernel Performance Events And Counters CONFIG_SYSTEM_DATA_VERIFICATION=y CONFIG_PROFILING=y CONFIG_TRACEPOINTS=y # end of General setup CONFIG_MMU=y CONFIG_CPU_BIG_ENDIAN=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_AUDIT_ARCH=y CONFIG_NO_IOPORT_MAP=y # CONFIG_PCI_QUIRKS is not set CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_S390=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_PGTABLE_LEVELS=5 CONFIG_HAVE_LIVEPATCH=y # # Processor type and features # CONFIG_HAVE_MARCH_Z10_FEATURES=y CONFIG_HAVE_MARCH_Z196_FEATURES=y CONFIG_HAVE_MARCH_ZEC12_FEATURES=y CONFIG_HAVE_MARCH_Z13_FEATURES=y CONFIG_HAVE_MARCH_Z14_FEATURES=y CONFIG_HAVE_MARCH_Z15_FEATURES=y # CONFIG_MARCH_Z10 is not set # CONFIG_MARCH_Z196 is not set # CONFIG_MARCH_ZEC12 is not set # CONFIG_MARCH_Z13 is not set # CONFIG_MARCH_Z14 is not set CONFIG_MARCH_Z15=y CONFIG_MARCH_ZEC12_TUNE=y # CONFIG_TUNE_DEFAULT is not set # CONFIG_TUNE_Z10 is not set # CONFIG_TUNE_Z196 is not set CONFIG_TUNE_ZEC12=y # CONFIG_TUNE_Z13 is not set # CONFIG_TUNE_Z14 is not set # CONFIG_TUNE_Z15 is not set # CONFIG_TUNE_Z16 is not set CONFIG_64BIT=y CONFIG_COMMAND_LINE_SIZE=4096 CONFIG_SMP=y CONFIG_NR_CPUS=64 CONFIG_HOTPLUG_CPU=y # CONFIG_SCHED_TOPOLOGY is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_250 is not set # CONFIG_HZ_300 is not set CONFIG_HZ_1000=y CONFIG_HZ=1000 CONFIG_SCHED_HRTICK=y CONFIG_KEXEC=y # CONFIG_KERNEL_NOBP is not set CONFIG_EXPOLINE=y CONFIG_EXPOLINE_EXTERN=y # CONFIG_EXPOLINE_OFF is not set # CONFIG_EXPOLINE_AUTO is not set CONFIG_EXPOLINE_FULL=y CONFIG_RELOCATABLE=y # CONFIG_RANDOMIZE_BASE is not set # end of Processor type and features # # Memory setup # CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_DEFAULT=y CONFIG_MAX_PHYSMEM_BITS=46 CONFIG_CHECK_STACK=y CONFIG_STACK_GUARD=256 # end of Memory setup # # I/O subsystem # # CONFIG_QDIO is not set CONFIG_PCI_NR_FUNCTIONS=512 CONFIG_HAS_IOMEM=y # CONFIG_CHSC_SCH is not set # CONFIG_SCM_BUS is not set # end of I/O subsystem # # Dump support # # CONFIG_CRASH_DUMP is not set # end of Dump support CONFIG_CCW=y # # Virtualization # # CONFIG_PROTECTED_VIRTUALIZATION_GUEST is not set CONFIG_PFAULT=y CONFIG_CMM=m # CONFIG_S390_HYPFS_FS is not set CONFIG_HAVE_KVM=y # CONFIG_VIRTUALIZATION is not set # CONFIG_S390_GUEST is not set # end of Virtualization CONFIG_S390_MODULES_SANITY_TEST_HELPERS=y # # Selftests # CONFIG_S390_UNWIND_SELFTEST=y CONFIG_S390_MODULES_SANITY_TEST=m # end of Selftests # # General architecture-dependent options # CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y CONFIG_GENERIC_ENTRY=y # CONFIG_KPROBES is not set CONFIG_JUMP_LABEL=y CONFIG_STATIC_KEYS_SELFTEST=y CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_KPROBES_ON_FTRACE=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y CONFIG_HAVE_NMI=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_ARCH_HAS_FORTIFY_SOURCE=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_ARCH_32BIT_USTAT_F_TINODE=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y CONFIG_MMU_GATHER_TABLE_FREE=y CONFIG_MMU_GATHER_RCU_TABLE_FREE=y CONFIG_MMU_GATHER_MERGE_VMAS=y CONFIG_MMU_GATHER_NO_GATHER=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_HAVE_CMPXCHG_LOCAL=y CONFIG_HAVE_CMPXCHG_DOUBLE=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y # CONFIG_SECCOMP is not set CONFIG_LTO_NONE=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_IDLE=y CONFIG_ARCH_HAS_SCALED_CPUTIME=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_SOFT_DIRTY=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ALTERNATE_USER_ADDRESS_SPACE=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_HAVE_RELIABLE_STACKTRACE=y CONFIG_CLONE_BACKWARDS2=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y # CONFIG_COMPAT_32BIT_TIME is not set CONFIG_HAVE_ARCH_VMAP_STACK=y # CONFIG_VMAP_STACK is not set CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_HAS_MEM_ENCRYPT=y CONFIG_ARCH_HAS_VDSO_DATA=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y # # GCOV-based kernel profiling # # CONFIG_GCOV_KERNEL is not set CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling CONFIG_HAVE_GCC_PLUGINS=y # CONFIG_GCC_PLUGINS is not set # end of General architecture-dependent options CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULE_SIG_FORMAT=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODULE_UNLOAD_TAINT_TRACKING=y CONFIG_MODVERSIONS=y CONFIG_ASM_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_MODULE_SIG=y CONFIG_MODULE_SIG_FORCE=y CONFIG_MODULE_SIG_ALL=y # CONFIG_MODULE_SIG_SHA1 is not set # CONFIG_MODULE_SIG_SHA224 is not set CONFIG_MODULE_SIG_SHA256=y # CONFIG_MODULE_SIG_SHA384 is not set # CONFIG_MODULE_SIG_SHA512 is not set CONFIG_MODULE_SIG_HASH="sha256" # CONFIG_MODULE_COMPRESS_NONE is not set # CONFIG_MODULE_COMPRESS_GZIP is not set # CONFIG_MODULE_COMPRESS_XZ is not set CONFIG_MODULE_COMPRESS_ZSTD=y # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y # CONFIG_BLOCK_LEGACY_AUTOLOAD is not set CONFIG_BLK_RQ_ALLOC_TIME=y CONFIG_BLK_CGROUP_RWSTAT=y CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_ICQ=y CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_DEV_INTEGRITY is not set CONFIG_BLK_DEV_ZONED=y # CONFIG_BLK_DEV_THROTTLING is not set CONFIG_BLK_WBT=y # CONFIG_BLK_WBT_MQ is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_FC_APPID is not set CONFIG_BLK_CGROUP_IOCOST=y CONFIG_BLK_CGROUP_IOPRIO=y # CONFIG_BLK_DEBUG_FS is not set CONFIG_BLK_SED_OPAL=y # CONFIG_BLK_INLINE_ENCRYPTION is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y CONFIG_EFI_PARTITION=y # end of Partition Types CONFIG_BLK_MQ_PCI=y CONFIG_BLK_MQ_VIRTIO=y # # IO Schedulers # CONFIG_MQ_IOSCHED_DEADLINE=y # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_IOSCHED_BFQ=y CONFIG_BFQ_GROUP_IOSCHED=y # CONFIG_BFQ_CGROUP_DEBUG is not set # end of IO Schedulers CONFIG_PADATA=y CONFIG_ASN1=y CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y CONFIG_ARCH_INLINE_SPIN_LOCK=y CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y CONFIG_ARCH_INLINE_SPIN_UNLOCK=y CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y CONFIG_ARCH_INLINE_READ_TRYLOCK=y CONFIG_ARCH_INLINE_READ_LOCK=y CONFIG_ARCH_INLINE_READ_LOCK_BH=y CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y CONFIG_ARCH_INLINE_READ_UNLOCK=y CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y CONFIG_ARCH_INLINE_WRITE_TRYLOCK=y CONFIG_ARCH_INLINE_WRITE_LOCK=y CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y CONFIG_ARCH_INLINE_WRITE_UNLOCK=y CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_RWSEM_SPIN_ON_OWNER=y CONFIG_LOCK_SPIN_ON_OWNER=y CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y # # Executable file formats # CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_ELF_KUNIT_TEST is not set CONFIG_ARCH_BINFMT_ELF_STATE=y CONFIG_ELFCORE=y # CONFIG_BINFMT_SCRIPT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_COREDUMP is not set # end of Executable file formats # # Memory Management options # # CONFIG_SWAP is not set # # SLAB allocator options # # CONFIG_SLAB is not set # CONFIG_SLUB is not set CONFIG_SLOB=y # end of SLAB allocator options CONFIG_SHUFFLE_PAGE_ALLOCATOR=y # CONFIG_COMPAT_BRK is not set CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y CONFIG_HAVE_MEMBLOCK_PHYS_MAP=y CONFIG_HAVE_FAST_GUP=y CONFIG_MEMORY_ISOLATION=y CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y CONFIG_MEMORY_HOTREMOVE=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y # CONFIG_COMPACTION is not set CONFIG_PAGE_REPORTING=y CONFIG_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 # CONFIG_TRANSPARENT_HUGEPAGE is not set CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 CONFIG_DEFERRED_STRUCT_PAGE_INIT=y # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y CONFIG_ZONE_DMA=y CONFIG_GET_FREE_REGION=y # CONFIG_VM_EVENT_COUNTERS is not set CONFIG_PERCPU_STATS=y CONFIG_GUP_TEST=y CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_USERFAULTFD=y CONFIG_LRU_GEN=y # CONFIG_LRU_GEN_ENABLED is not set CONFIG_LRU_GEN_STATS=y # # Data Access Monitoring # # CONFIG_DAMON is not set # end of Data Access Monitoring # end of Memory Management options # CONFIG_NET is not set # # Device Drivers # CONFIG_HAVE_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y # CONFIG_PCIEPORTBUS is not set # CONFIG_PCIEASPM is not set CONFIG_PCIE_PTM=y CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCI_MSI_ARCH_FALLBACKS=y CONFIG_PCI_DEBUG=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=m # CONFIG_PCI_PF_STUB is not set CONFIG_PCI_ATS=y CONFIG_PCI_DOE=y CONFIG_PCI_IOV=y CONFIG_PCI_PRI=y CONFIG_PCI_PASID=y CONFIG_PCIE_BUS_TUNE_OFF=y # CONFIG_PCIE_BUS_DEFAULT is not set # CONFIG_PCIE_BUS_SAFE is not set # CONFIG_PCIE_BUS_PERFORMANCE is not set # CONFIG_PCIE_BUS_PEER2PEER is not set CONFIG_HOTPLUG_PCI=y CONFIG_HOTPLUG_PCI_CPCI=y CONFIG_HOTPLUG_PCI_SHPC=y # CONFIG_HOTPLUG_PCI_S390 is not set # # PCI controller drivers # # CONFIG_PCIE_XILINX_NWL is not set # CONFIG_PCI_TEGRA is not set # CONFIG_PCIE_RCAR_HOST is not set # CONFIG_PCIE_RCAR_EP is not set CONFIG_PCIE_XILINX=y # CONFIG_PCIE_XILINX_CPM is not set # CONFIG_PCI_VERSATILE is not set # CONFIG_PCIE_ALTERA is not set # CONFIG_PCIE_MEDIATEK_GEN3 is not set # CONFIG_PCIE_MT7621 is not set # # DesignWare PCI Core Support # CONFIG_PCIE_DW=y CONFIG_PCIE_DW_HOST=y CONFIG_PCIE_DW_EP=y CONFIG_PCIE_DW_PLAT=y CONFIG_PCIE_DW_PLAT_HOST=y CONFIG_PCIE_DW_PLAT_EP=y # CONFIG_PCI_EXYNOS is not set # CONFIG_PCI_IMX6 is not set # CONFIG_PCIE_SPEAR13XX is not set # CONFIG_PCI_KEYSTONE_HOST is not set # CONFIG_PCI_KEYSTONE_EP is not set # CONFIG_PCIE_ARMADA_8K is not set # CONFIG_PCIE_ARTPEC6_HOST is not set # CONFIG_PCIE_ARTPEC6_EP is not set # CONFIG_PCIE_KEEMBAY_HOST is not set # CONFIG_PCIE_KEEMBAY_EP is not set # CONFIG_PCIE_HISI_STB is not set CONFIG_PCI_MESON=y # CONFIG_PCIE_TEGRA194_HOST is not set # CONFIG_PCIE_TEGRA194_EP is not set # CONFIG_PCIE_VISCONTI_HOST is not set # CONFIG_PCIE_FU740 is not set # end of DesignWare PCI Core Support # # Mobiveil PCIe Core Support # # CONFIG_PCIE_LAYERSCAPE_GEN4 is not set # end of Mobiveil PCIe Core Support # # Cadence PCIe controllers support # # end of Cadence PCIe controllers support # end of PCI controller drivers # # PCI Endpoint # CONFIG_PCI_ENDPOINT=y CONFIG_PCI_ENDPOINT_CONFIGFS=y CONFIG_PCI_EPF_TEST=y CONFIG_PCI_EPF_NTB=y # end of PCI Endpoint # # PCI switch controller drivers # CONFIG_PCI_SW_SWITCHTEC=m # end of PCI switch controller drivers CONFIG_CXL_BUS=y CONFIG_CXL_PCI=y # CONFIG_CXL_MEM_RAW_COMMANDS is not set # CONFIG_CXL_PMEM is not set CONFIG_CXL_MEM=y CONFIG_CXL_PORT=y CONFIG_CXL_REGION=y CONFIG_PCCARD=y CONFIG_PCMCIA=y CONFIG_PCMCIA_LOAD_CIS=y # CONFIG_CARDBUS is not set # # PC-card bridges # CONFIG_YENTA=m # CONFIG_YENTA_O2 is not set CONFIG_YENTA_RICOH=y # CONFIG_YENTA_TI is not set # CONFIG_YENTA_TOSHIBA is not set # CONFIG_PD6729 is not set CONFIG_I82092=y CONFIG_PCCARD_NONSTATIC=y CONFIG_RAPIDIO=y CONFIG_RAPIDIO_DISC_TIMEOUT=30 # CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set CONFIG_RAPIDIO_DEBUG=y CONFIG_RAPIDIO_ENUM_BASIC=m # CONFIG_RAPIDIO_CHMAN is not set CONFIG_RAPIDIO_MPORT_CDEV=m # # RapidIO Switch drivers # CONFIG_RAPIDIO_CPS_XX=m CONFIG_RAPIDIO_CPS_GEN2=m CONFIG_RAPIDIO_RXS_GEN3=m # end of RapidIO Switch drivers # # Generic Driver Options # CONFIG_AUXILIARY_BUS=y # CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y # CONFIG_STANDALONE is not set CONFIG_PREVENT_FIRMWARE_BUILD=y # # Firmware loader # CONFIG_FW_LOADER=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_FW_LOADER_SYSFS=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_FW_LOADER_USER_HELPER is not set # CONFIG_FW_LOADER_COMPRESS is not set CONFIG_FW_UPLOAD=y # end of Firmware loader # CONFIG_ALLOW_DEV_COREDUMP is not set # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set # CONFIG_PM_QOS_KUNIT_TEST is not set # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set # CONFIG_DRIVER_PE_KUNIT_TEST is not set CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y CONFIG_REGMAP_SPI=y CONFIG_REGMAP_SPMI=m CONFIG_REGMAP_W1=y CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_IRQ=y CONFIG_DMA_SHARED_BUFFER=y CONFIG_DMA_FENCE_TRACE=y # end of Generic Driver Options # # Bus devices # # CONFIG_ARM_INTEGRATOR_LM is not set # CONFIG_BT1_APB is not set # CONFIG_BT1_AXI is not set # CONFIG_HISILICON_LPC is not set # CONFIG_INTEL_IXP4XX_EB is not set # CONFIG_QCOM_EBI2 is not set CONFIG_MHI_BUS=y # CONFIG_MHI_BUS_DEBUG is not set # CONFIG_MHI_BUS_PCI_GENERIC is not set CONFIG_MHI_BUS_EP=m # end of Bus devices # # Firmware Drivers # # # ARM System Control and Management Interface Protocol # # CONFIG_ARM_SCMI_PROTOCOL is not set # end of ARM System Control and Management Interface Protocol CONFIG_FIRMWARE_MEMMAP=y # CONFIG_BCM47XX_NVRAM is not set CONFIG_GOOGLE_FIRMWARE=y # # Tegra firmware driver # # end of Tegra firmware driver # end of Firmware Drivers CONFIG_GNSS=m CONFIG_MTD=m # CONFIG_MTD_TESTS is not set # # Partition parsers # # CONFIG_MTD_AR7_PARTS is not set # CONFIG_MTD_BCM63XX_PARTS is not set # CONFIG_MTD_BRCM_U_BOOT is not set CONFIG_MTD_CMDLINE_PARTS=m # CONFIG_MTD_PARSER_IMAGETAG is not set # CONFIG_MTD_PARSER_TRX is not set # CONFIG_MTD_SHARPSL_PARTS is not set CONFIG_MTD_REDBOOT_PARTS=m CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y CONFIG_MTD_REDBOOT_PARTS_READONLY=y # end of Partition parsers # # User Modules And Translation Layers # CONFIG_MTD_BLKDEVS=m CONFIG_MTD_BLOCK=m CONFIG_MTD_BLOCK_RO=m # # Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. # CONFIG_FTL=m CONFIG_NFTL=m CONFIG_NFTL_RW=y # CONFIG_INFTL is not set CONFIG_RFD_FTL=m # CONFIG_SSFDC is not set CONFIG_SM_FTL=m CONFIG_MTD_OOPS=m # CONFIG_MTD_PARTITIONED_MASTER is not set # # RAM/ROM/Flash chip drivers # CONFIG_MTD_CFI=m # CONFIG_MTD_JEDECPROBE is not set CONFIG_MTD_GEN_PROBE=m # CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_INTELEXT=m CONFIG_MTD_CFI_AMDSTD=m CONFIG_MTD_CFI_STAA=m CONFIG_MTD_CFI_UTIL=m CONFIG_MTD_RAM=m # CONFIG_MTD_ROM is not set CONFIG_MTD_ABSENT=m # end of RAM/ROM/Flash chip drivers # # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set CONFIG_MTD_PHYSMAP=m # CONFIG_MTD_PHYSMAP_COMPAT is not set # CONFIG_MTD_SC520CDP is not set # CONFIG_MTD_NETSC520 is not set # CONFIG_MTD_TS5500 is not set CONFIG_MTD_INTEL_VR_NOR=m CONFIG_MTD_PLATRAM=m # end of Mapping drivers for chip access # # Self-contained MTD device drivers # CONFIG_MTD_PMC551=m CONFIG_MTD_PMC551_BUGFIX=y CONFIG_MTD_PMC551_DEBUG=y CONFIG_MTD_DATAFLASH=m # CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set # CONFIG_MTD_DATAFLASH_OTP is not set CONFIG_MTD_MCHP23K256=m # CONFIG_MTD_MCHP48L640 is not set CONFIG_MTD_SPEAR_SMI=m CONFIG_MTD_SST25L=m CONFIG_MTD_SLRAM=m CONFIG_MTD_PHRAM=m CONFIG_MTD_MTDRAM=m CONFIG_MTDRAM_TOTAL_SIZE=4096 CONFIG_MTDRAM_ERASE_SIZE=128 CONFIG_MTD_BLOCK2MTD=m # # Disk-On-Chip Device Drivers # CONFIG_MTD_DOCG3=m CONFIG_BCH_CONST_M=14 CONFIG_BCH_CONST_T=4 # end of Self-contained MTD device drivers # # NAND # CONFIG_MTD_NAND_CORE=m CONFIG_MTD_ONENAND=m CONFIG_MTD_ONENAND_VERIFY_WRITE=y # CONFIG_MTD_ONENAND_GENERIC is not set # CONFIG_MTD_ONENAND_SAMSUNG is not set # CONFIG_MTD_ONENAND_OTP is not set # CONFIG_MTD_ONENAND_2X_PROGRAM is not set # CONFIG_MTD_RAW_NAND is not set CONFIG_MTD_SPI_NAND=m # # ECC engine support # CONFIG_MTD_NAND_ECC=y CONFIG_MTD_NAND_ECC_SW_HAMMING=y # CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set CONFIG_MTD_NAND_ECC_SW_BCH=y CONFIG_MTD_NAND_ECC_MXIC=y # CONFIG_MTD_NAND_ECC_MEDIATEK is not set # end of ECC engine support # end of NAND # # LPDDR & LPDDR2 PCM memory drivers # CONFIG_MTD_LPDDR=m CONFIG_MTD_QINFO_PROBE=m # end of LPDDR & LPDDR2 PCM memory drivers CONFIG_MTD_SPI_NOR=m CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y CONFIG_MTD_SPI_NOR_SWP_DISABLE=y # CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE is not set # CONFIG_MTD_SPI_NOR_SWP_KEEP is not set # CONFIG_SPI_HISI_SFC is not set CONFIG_MTD_UBI=m CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_FASTMAP=y # CONFIG_MTD_UBI_GLUEBI is not set # CONFIG_MTD_UBI_BLOCK is not set # CONFIG_MTD_HYPERBUS is not set # CONFIG_OF is not set CONFIG_PARPORT=y CONFIG_PARPORT_AX88796=m # CONFIG_PARPORT_1284 is not set CONFIG_PARPORT_NOT_PC=y CONFIG_BLK_DEV=y CONFIG_BLK_DEV_NULL_BLK=y CONFIG_BLK_DEV_NULL_BLK_FAULT_INJECTION=y CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m # CONFIG_ZRAM is not set CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # # DRBD disabled because PROC_FS or INET not selected # CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_CDROM_PKTCDVD is not set # # S/390 block device drivers # CONFIG_DCSSBLK=y CONFIG_DASD=m # CONFIG_DASD_PROFILE is not set CONFIG_DASD_ECKD=m CONFIG_DASD_FBA=m # CONFIG_DASD_DIAG is not set # CONFIG_DASD_EER is not set CONFIG_VIRTIO_BLK=y # CONFIG_BLK_DEV_UBLK is not set # # NVME Support # CONFIG_NVME_COMMON=y CONFIG_NVME_CORE=y CONFIG_BLK_DEV_NVME=m # CONFIG_NVME_MULTIPATH is not set CONFIG_NVME_VERBOSE_ERRORS=y # CONFIG_NVME_HWMON is not set CONFIG_NVME_FABRICS=y CONFIG_NVME_FC=y # CONFIG_NVME_AUTH is not set CONFIG_NVME_TARGET=y # CONFIG_NVME_TARGET_PASSTHRU is not set CONFIG_NVME_TARGET_LOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_AUTH=y # end of NVME Support # # Misc devices # CONFIG_SENSORS_LIS3LV02D=y CONFIG_AD525X_DPOT=y CONFIG_AD525X_DPOT_I2C=y # CONFIG_AD525X_DPOT_SPI is not set # CONFIG_DUMMY_IRQ is not set CONFIG_PHANTOM=y CONFIG_TIFM_CORE=y # CONFIG_TIFM_7XX1 is not set CONFIG_ICS932S401=m # CONFIG_ATMEL_SSC is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_GEHC_ACHC is not set # CONFIG_HP_ILO is not set # CONFIG_QCOM_COINCELL is not set # CONFIG_QCOM_FASTRPC is not set CONFIG_APDS9802ALS=m # CONFIG_ISL29003 is not set CONFIG_ISL29020=y CONFIG_SENSORS_TSL2550=y CONFIG_SENSORS_BH1770=y CONFIG_SENSORS_APDS990X=m CONFIG_HMC6352=y CONFIG_DS1682=y # CONFIG_PCH_PHUB is not set # CONFIG_LATTICE_ECP3_CONFIG is not set CONFIG_SRAM=y CONFIG_DW_XDATA_PCIE=m CONFIG_PCI_ENDPOINT_TEST=y CONFIG_XILINX_SDFEC=m CONFIG_MISC_RTSX=y CONFIG_C2PORT=m # # EEPROM support # CONFIG_EEPROM_AT24=m # CONFIG_EEPROM_AT25 is not set CONFIG_EEPROM_LEGACY=m # CONFIG_EEPROM_MAX6875 is not set CONFIG_EEPROM_93CX6=y CONFIG_EEPROM_93XX46=y CONFIG_EEPROM_IDT_89HPESX=m # CONFIG_EEPROM_EE1004 is not set # end of EEPROM support CONFIG_CB710_CORE=y # CONFIG_CB710_DEBUG is not set CONFIG_CB710_DEBUG_ASSUMPTIONS=y # # Texas Instruments shared transport line discipline # # end of Texas Instruments shared transport line discipline CONFIG_SENSORS_LIS3_SPI=y # CONFIG_SENSORS_LIS3_I2C is not set CONFIG_ALTERA_STAPL=m # CONFIG_GENWQE is not set # CONFIG_ECHO is not set # CONFIG_BCM_VK is not set CONFIG_MISC_ALCOR_PCI=y CONFIG_MISC_RTSX_PCI=y CONFIG_HABANA_AI=y # CONFIG_UACCE is not set # CONFIG_PVPANIC is not set CONFIG_GP_PCI1XXXX=y # end of Misc devices # # SCSI device support # CONFIG_SCSI_MOD=m CONFIG_RAID_ATTRS=m CONFIG_SCSI_COMMON=m CONFIG_SCSI=m CONFIG_SCSI_DMA=y # # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=m # CONFIG_CHR_DEV_ST is not set # CONFIG_BLK_DEV_SR is not set CONFIG_CHR_DEV_SG=m CONFIG_BLK_DEV_BSG=y CONFIG_CHR_DEV_SCH=m # CONFIG_SCSI_CONSTANTS is not set CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y # # SCSI Transports # CONFIG_SCSI_SPI_ATTRS=m CONFIG_SCSI_SAS_ATTRS=m CONFIG_SCSI_SAS_LIBSAS=m CONFIG_SCSI_SAS_HOST_SMP=y CONFIG_SCSI_SRP_ATTRS=m # end of SCSI Transports CONFIG_SCSI_LOWLEVEL=y CONFIG_ISCSI_BOOT_SYSFS=m CONFIG_BLK_DEV_3W_XXXX_RAID=m CONFIG_SCSI_HPSA=m CONFIG_SCSI_3W_9XXX=m CONFIG_SCSI_3W_SAS=m # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set # CONFIG_SCSI_AIC79XX is not set CONFIG_SCSI_AIC94XX=m # CONFIG_AIC94XX_DEBUG is not set CONFIG_SCSI_MVSAS=m CONFIG_SCSI_MVSAS_DEBUG=y # CONFIG_SCSI_MVSAS_TASKLET is not set # CONFIG_SCSI_MVUMI is not set CONFIG_SCSI_ADVANSYS=m CONFIG_SCSI_ARCMSR=m CONFIG_SCSI_ESAS2R=m CONFIG_MEGARAID_NEWGEN=y CONFIG_MEGARAID_MM=m CONFIG_MEGARAID_MAILBOX=m CONFIG_MEGARAID_LEGACY=m # CONFIG_MEGARAID_SAS is not set CONFIG_SCSI_MPT3SAS=m CONFIG_SCSI_MPT2SAS_MAX_SGE=128 CONFIG_SCSI_MPT3SAS_MAX_SGE=128 # CONFIG_SCSI_MPT2SAS is not set CONFIG_SCSI_MPI3MR=m # CONFIG_SCSI_HPTIOP is not set CONFIG_SCSI_BUSLOGIC=m CONFIG_SCSI_FLASHPOINT=y # CONFIG_SCSI_MYRB is not set # CONFIG_SCSI_MYRS is not set CONFIG_SCSI_SNIC=m CONFIG_SCSI_SNIC_DEBUG_FS=y CONFIG_SCSI_DMX3191D=m CONFIG_SCSI_FDOMAIN=m CONFIG_SCSI_FDOMAIN_PCI=m CONFIG_SCSI_IPS=m # CONFIG_SCSI_INITIO is not set CONFIG_SCSI_INIA100=m # CONFIG_SCSI_STEX is not set # CONFIG_SCSI_SYM53C8XX_2 is not set CONFIG_SCSI_QLOGIC_1280=m CONFIG_SCSI_DC395x=m CONFIG_SCSI_AM53C974=m CONFIG_SCSI_WD719X=m CONFIG_SCSI_DEBUG=m # CONFIG_SCSI_PM8001 is not set CONFIG_SCSI_VIRTIO=m CONFIG_SCSI_LOWLEVEL_PCMCIA=y # CONFIG_PCMCIA_AHA152X is not set # CONFIG_PCMCIA_FDOMAIN is not set # CONFIG_PCMCIA_NINJA_SCSI is not set # CONFIG_PCMCIA_QLOGIC is not set CONFIG_PCMCIA_SYM53C500=m CONFIG_SCSI_DH=y CONFIG_SCSI_DH_RDAC=m # CONFIG_SCSI_DH_HP_SW is not set # CONFIG_SCSI_DH_EMC is not set CONFIG_SCSI_DH_ALUA=m # end of SCSI device support # CONFIG_ATA is not set # CONFIG_MD is not set # CONFIG_TARGET_CORE is not set # CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # CONFIG_FIREWIRE=y CONFIG_FIREWIRE_OHCI=m CONFIG_FIREWIRE_SBP2=m # CONFIG_FIREWIRE_NOSY is not set # end of IEEE 1394 (FireWire) support # # Input device support # CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y CONFIG_INPUT_SPARSEKMAP=y CONFIG_INPUT_MATRIXKMAP=m # # Userland interfaces # CONFIG_INPUT_MOUSEDEV=m CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 CONFIG_INPUT_JOYDEV=y CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set # # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set CONFIG_INPUT_MOUSE=y # CONFIG_MOUSE_PS2 is not set CONFIG_MOUSE_SERIAL=y # CONFIG_MOUSE_CYAPA is not set CONFIG_MOUSE_ELAN_I2C=m CONFIG_MOUSE_ELAN_I2C_I2C=y CONFIG_MOUSE_ELAN_I2C_SMBUS=y # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_MOUSE_GPIO is not set # CONFIG_MOUSE_SYNAPTICS_I2C is not set CONFIG_INPUT_JOYSTICK=y CONFIG_JOYSTICK_ANALOG=y CONFIG_JOYSTICK_A3D=y # CONFIG_JOYSTICK_ADC is not set CONFIG_JOYSTICK_ADI=y CONFIG_JOYSTICK_COBRA=m # CONFIG_JOYSTICK_GF2K is not set CONFIG_JOYSTICK_GRIP=m CONFIG_JOYSTICK_GRIP_MP=y CONFIG_JOYSTICK_GUILLEMOT=m CONFIG_JOYSTICK_INTERACT=y # CONFIG_JOYSTICK_SIDEWINDER is not set CONFIG_JOYSTICK_TMDC=y CONFIG_JOYSTICK_IFORCE=m CONFIG_JOYSTICK_IFORCE_232=m CONFIG_JOYSTICK_WARRIOR=m CONFIG_JOYSTICK_MAGELLAN=m CONFIG_JOYSTICK_SPACEORB=y CONFIG_JOYSTICK_SPACEBALL=y CONFIG_JOYSTICK_STINGER=y CONFIG_JOYSTICK_TWIDJOY=y CONFIG_JOYSTICK_ZHENHUA=m # CONFIG_JOYSTICK_DB9 is not set CONFIG_JOYSTICK_GAMECON=y # CONFIG_JOYSTICK_TURBOGRAFX is not set CONFIG_JOYSTICK_AS5011=y # CONFIG_JOYSTICK_JOYDUMP is not set CONFIG_JOYSTICK_WALKERA0701=m CONFIG_JOYSTICK_PSXPAD_SPI=m CONFIG_JOYSTICK_PSXPAD_SPI_FF=y CONFIG_JOYSTICK_QWIIC=y # CONFIG_JOYSTICK_FSIA6B is not set CONFIG_JOYSTICK_SENSEHAT=y CONFIG_INPUT_TABLET=y CONFIG_TABLET_SERIAL_WACOM4=m CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_88PM860X is not set CONFIG_TOUCHSCREEN_ADS7846=m # CONFIG_TOUCHSCREEN_AD7877 is not set CONFIG_TOUCHSCREEN_AD7879=y # CONFIG_TOUCHSCREEN_AD7879_I2C is not set # CONFIG_TOUCHSCREEN_AD7879_SPI is not set # CONFIG_TOUCHSCREEN_ADC is not set # CONFIG_TOUCHSCREEN_ATMEL_MXT is not set CONFIG_TOUCHSCREEN_AUO_PIXCIR=m CONFIG_TOUCHSCREEN_BU21013=m CONFIG_TOUCHSCREEN_BU21029=y CONFIG_TOUCHSCREEN_CY8CTMA140=m CONFIG_TOUCHSCREEN_CY8CTMG110=m CONFIG_TOUCHSCREEN_CYTTSP_CORE=y # CONFIG_TOUCHSCREEN_CYTTSP_I2C is not set CONFIG_TOUCHSCREEN_CYTTSP_SPI=y # CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set CONFIG_TOUCHSCREEN_DA9034=m # CONFIG_TOUCHSCREEN_DA9052 is not set CONFIG_TOUCHSCREEN_DYNAPRO=y CONFIG_TOUCHSCREEN_HAMPSHIRE=m CONFIG_TOUCHSCREEN_EETI=m CONFIG_TOUCHSCREEN_EGALAX_SERIAL=y # CONFIG_TOUCHSCREEN_EXC3000 is not set CONFIG_TOUCHSCREEN_FUJITSU=m CONFIG_TOUCHSCREEN_GOODIX=y CONFIG_TOUCHSCREEN_HIDEEP=y CONFIG_TOUCHSCREEN_HYCON_HY46XX=y CONFIG_TOUCHSCREEN_ILI210X=m CONFIG_TOUCHSCREEN_ILITEK=y # CONFIG_TOUCHSCREEN_IPROC is not set # CONFIG_TOUCHSCREEN_S6SY761 is not set CONFIG_TOUCHSCREEN_GUNZE=y # CONFIG_TOUCHSCREEN_EKTF2127 is not set # CONFIG_TOUCHSCREEN_ELAN is not set # CONFIG_TOUCHSCREEN_ELO is not set CONFIG_TOUCHSCREEN_WACOM_W8001=y CONFIG_TOUCHSCREEN_WACOM_I2C=m # CONFIG_TOUCHSCREEN_MAX11801 is not set CONFIG_TOUCHSCREEN_MCS5000=y CONFIG_TOUCHSCREEN_MMS114=m # CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set CONFIG_TOUCHSCREEN_MSG2638=y # CONFIG_TOUCHSCREEN_MTOUCH is not set CONFIG_TOUCHSCREEN_IMAGIS=m # CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set CONFIG_TOUCHSCREEN_INEXIO=m CONFIG_TOUCHSCREEN_MK712=m CONFIG_TOUCHSCREEN_PENMOUNT=m # CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set # CONFIG_TOUCHSCREEN_RASPBERRYPI_FW is not set # CONFIG_TOUCHSCREEN_MIGOR is not set CONFIG_TOUCHSCREEN_TOUCHRIGHT=m # CONFIG_TOUCHSCREEN_TOUCHWIN is not set CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m CONFIG_TOUCHSCREEN_PIXCIR=y CONFIG_TOUCHSCREEN_WDT87XX_I2C=y # CONFIG_TOUCHSCREEN_WM831X is not set CONFIG_TOUCHSCREEN_MC13783=m CONFIG_TOUCHSCREEN_TOUCHIT213=y CONFIG_TOUCHSCREEN_TSC_SERIO=y CONFIG_TOUCHSCREEN_TSC200X_CORE=m CONFIG_TOUCHSCREEN_TSC2004=m # CONFIG_TOUCHSCREEN_TSC2005 is not set CONFIG_TOUCHSCREEN_TSC2007=y CONFIG_TOUCHSCREEN_TSC2007_IIO=y CONFIG_TOUCHSCREEN_PCAP=m CONFIG_TOUCHSCREEN_RM_TS=m # CONFIG_TOUCHSCREEN_SILEAD is not set CONFIG_TOUCHSCREEN_SIS_I2C=m # CONFIG_TOUCHSCREEN_ST1232 is not set CONFIG_TOUCHSCREEN_STMFTS=y # CONFIG_TOUCHSCREEN_SUN4I is not set CONFIG_TOUCHSCREEN_SURFACE3_SPI=m CONFIG_TOUCHSCREEN_SX8654=y CONFIG_TOUCHSCREEN_TPS6507X=y CONFIG_TOUCHSCREEN_ZET6223=m CONFIG_TOUCHSCREEN_ZFORCE=m # CONFIG_TOUCHSCREEN_COLIBRI_VF50 is not set CONFIG_TOUCHSCREEN_ROHM_BU21023=m # CONFIG_TOUCHSCREEN_IQS5XX is not set CONFIG_TOUCHSCREEN_ZINITIX=y # CONFIG_INPUT_MISC is not set # CONFIG_RMI4_CORE is not set # # Hardware I/O ports # CONFIG_SERIO=y CONFIG_SERIO_SERPORT=m # CONFIG_SERIO_PARKBD is not set CONFIG_SERIO_PCIPS2=m CONFIG_SERIO_LIBPS2=y CONFIG_SERIO_RAW=m # CONFIG_SERIO_ALTERA_PS2 is not set CONFIG_SERIO_PS2MULT=m CONFIG_SERIO_ARC_PS2=y # CONFIG_SERIO_OLPC_APSP is not set # CONFIG_SERIO_SUN4I_PS2 is not set CONFIG_SERIO_GPIO_PS2=m # CONFIG_USERIO is not set CONFIG_GAMEPORT=y CONFIG_GAMEPORT_NS558=y CONFIG_GAMEPORT_L4=y # CONFIG_GAMEPORT_EMU10K1 is not set # CONFIG_GAMEPORT_FM801 is not set # end of Hardware I/O ports # end of Input device support # # Character devices # CONFIG_TTY=y CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y # CONFIG_VT_CONSOLE is not set CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set CONFIG_LDISC_AUTOLOAD=y # # Serial drivers # # # Non-8250 serial port support # # CONFIG_SERIAL_AMBA_PL010 is not set # CONFIG_SERIAL_MESON is not set # CONFIG_SERIAL_CLPS711X is not set # CONFIG_SERIAL_SAMSUNG is not set # CONFIG_SERIAL_TEGRA is not set # CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_MAX310X=m # CONFIG_SERIAL_IMX is not set CONFIG_SERIAL_UARTLITE=m CONFIG_SERIAL_UARTLITE_NR_UARTS=1 # CONFIG_SERIAL_SH_SCI is not set CONFIG_SERIAL_CORE=y # CONFIG_SERIAL_ICOM is not set CONFIG_SERIAL_JSM=y # CONFIG_SERIAL_MSM is not set # CONFIG_SERIAL_VT8500 is not set # CONFIG_SERIAL_OMAP is not set # CONFIG_SERIAL_LANTIQ is not set # CONFIG_SERIAL_SCCNXP is not set CONFIG_SERIAL_SC16IS7XX=y # CONFIG_SERIAL_SC16IS7XX_I2C is not set # CONFIG_SERIAL_SC16IS7XX_SPI is not set # CONFIG_SERIAL_TIMBERDALE is not set # CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set # CONFIG_SERIAL_PCH_UART is not set # CONFIG_SERIAL_MXS_AUART is not set # CONFIG_SERIAL_MPS2_UART is not set # CONFIG_SERIAL_ARC is not set CONFIG_SERIAL_RP2=m CONFIG_SERIAL_RP2_NR_UARTS=32 CONFIG_SERIAL_FSL_LPUART=m # CONFIG_SERIAL_FSL_LPUART_CONSOLE is not set # CONFIG_SERIAL_ST_ASC is not set # CONFIG_SERIAL_MEN_Z135 is not set # CONFIG_SERIAL_STM32 is not set # CONFIG_SERIAL_OWL is not set # CONFIG_SERIAL_RDA is not set # CONFIG_SERIAL_LITEUART is not set # CONFIG_SERIAL_SUNPLUS is not set # end of Serial drivers CONFIG_SERIAL_NONSTANDARD=y CONFIG_MOXA_INTELLIO=m CONFIG_MOXA_SMARTIO=m CONFIG_SYNCLINK_GT=y # CONFIG_N_HDLC is not set CONFIG_NOZOMI=y # CONFIG_NULL_TTY is not set CONFIG_HVC_DRIVER=y CONFIG_RPMSG_TTY=m # CONFIG_SERIAL_DEV_BUS is not set # CONFIG_TTY_PRINTK is not set # CONFIG_PRINTER is not set CONFIG_PPDEV=m CONFIG_VIRTIO_CONSOLE=y CONFIG_IPMI_HANDLER=y CONFIG_IPMI_PLAT_DATA=y # CONFIG_IPMI_PANIC_EVENT is not set CONFIG_IPMI_DEVICE_INTERFACE=m CONFIG_IPMI_SI=y CONFIG_IPMI_SSIF=y CONFIG_IPMI_IPMB=m # CONFIG_IPMI_WATCHDOG is not set # CONFIG_IPMI_POWEROFF is not set # CONFIG_ASPEED_KCS_IPMI_BMC is not set # CONFIG_NPCM7XX_KCS_IPMI_BMC is not set # CONFIG_ASPEED_BT_IPMI_BMC is not set CONFIG_IPMB_DEVICE_INTERFACE=y # CONFIG_HW_RANDOM is not set CONFIG_APPLICOM=m # # PCMCIA character devices # CONFIG_SYNCLINK_CS=y CONFIG_CARDMAN_4000=m CONFIG_CARDMAN_4040=y CONFIG_SCR24X=y # end of PCMCIA character devices CONFIG_DEVMEM=y CONFIG_DEVPORT=y CONFIG_HANGCHECK_TIMER=m CONFIG_TCG_TPM=m # CONFIG_TCG_TIS_SPI is not set # CONFIG_TCG_TIS_I2C is not set # CONFIG_TCG_TIS_SYNQUACER is not set CONFIG_TCG_TIS_I2C_CR50=m CONFIG_TCG_TIS_I2C_ATMEL=m # CONFIG_TCG_TIS_I2C_INFINEON is not set # CONFIG_TCG_TIS_I2C_NUVOTON is not set CONFIG_TCG_VTPM_PROXY=m CONFIG_TCG_TIS_ST33ZP24=m CONFIG_TCG_TIS_ST33ZP24_I2C=m # CONFIG_TCG_TIS_ST33ZP24_SPI is not set # # S/390 character device drivers # # CONFIG_TN3270 is not set CONFIG_TN3215=y CONFIG_TN3215_CONSOLE=y CONFIG_CCW_CONSOLE=y CONFIG_SCLP_TTY=y # CONFIG_SCLP_CONSOLE is not set CONFIG_SCLP_VT220_TTY=y CONFIG_SCLP_VT220_CONSOLE=y CONFIG_HMC_DRV=m CONFIG_SCLP_OFB=y # CONFIG_S390_UV_UAPI is not set # CONFIG_S390_TAPE is not set CONFIG_VMCP=y CONFIG_VMCP_CMA_SIZE=4 CONFIG_MONWRITER=y CONFIG_S390_VMUR=m CONFIG_XILLYBUS_CLASS=y CONFIG_XILLYBUS=y CONFIG_XILLYBUS_PCIE=y CONFIG_RANDOM_TRUST_CPU=y CONFIG_RANDOM_TRUST_BOOTLOADER=y # end of Character devices # # I2C support # CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y # # Multiplexer I2C Chip support # CONFIG_I2C_MUX_GPIO=m CONFIG_I2C_MUX_LTC4306=y CONFIG_I2C_MUX_PCA9541=m # CONFIG_I2C_MUX_PCA954x is not set # CONFIG_I2C_MUX_REG is not set CONFIG_I2C_MUX_MLXCPLD=m # end of Multiplexer I2C Chip support # CONFIG_I2C_HELPER_AUTO is not set CONFIG_I2C_SMBUS=y # # I2C Algorithms # CONFIG_I2C_ALGOBIT=y CONFIG_I2C_ALGOPCF=m # CONFIG_I2C_ALGOPCA is not set # end of I2C Algorithms # # I2C Hardware Bus support # # # PC SMBus host controller drivers # CONFIG_I2C_CCGX_UCSI=y CONFIG_I2C_ALI1535=m # CONFIG_I2C_ALI1563 is not set CONFIG_I2C_ALI15X3=y CONFIG_I2C_AMD756=y CONFIG_I2C_AMD8111=m # CONFIG_I2C_HIX5HD2 is not set # CONFIG_I2C_I801 is not set # CONFIG_I2C_ISCH is not set CONFIG_I2C_PIIX4=y CONFIG_I2C_NFORCE2=y CONFIG_I2C_NVIDIA_GPU=y # CONFIG_I2C_SIS5595 is not set # CONFIG_I2C_SIS630 is not set CONFIG_I2C_SIS96X=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set # # I2C system bus drivers (mostly embedded / system-on-chip) # # CONFIG_I2C_ASPEED is not set # CONFIG_I2C_AT91 is not set # CONFIG_I2C_AXXIA is not set # CONFIG_I2C_BCM_IPROC is not set # CONFIG_I2C_BCM_KONA is not set CONFIG_I2C_BRCMSTB=y # CONFIG_I2C_CADENCE is not set CONFIG_I2C_CBUS_GPIO=m # CONFIG_I2C_DAVINCI is not set CONFIG_I2C_DESIGNWARE_CORE=y CONFIG_I2C_DESIGNWARE_SLAVE=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_DESIGNWARE_PCI=m # CONFIG_I2C_DIGICOLOR is not set # CONFIG_I2C_EG20T is not set CONFIG_I2C_GPIO=m CONFIG_I2C_GPIO_FAULT_INJECTOR=y # CONFIG_I2C_HIGHLANDER is not set # CONFIG_I2C_HISI is not set # CONFIG_I2C_IMG is not set # CONFIG_I2C_IMX is not set # CONFIG_I2C_IMX_LPI2C is not set # CONFIG_I2C_IOP3XX is not set # CONFIG_I2C_JZ4780 is not set # CONFIG_I2C_MT65XX is not set # CONFIG_I2C_MT7621 is not set # CONFIG_I2C_MV64XXX is not set # CONFIG_I2C_MXS is not set # CONFIG_I2C_NPCM is not set CONFIG_I2C_OCORES=y # CONFIG_I2C_OMAP is not set # CONFIG_I2C_OWL is not set # CONFIG_I2C_APPLE is not set # CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_PNX is not set # CONFIG_I2C_PXA is not set # CONFIG_I2C_QCOM_CCI is not set # CONFIG_I2C_QUP is not set # CONFIG_I2C_RIIC is not set # CONFIG_I2C_RZV2M is not set # CONFIG_I2C_S3C2410 is not set # CONFIG_I2C_SH_MOBILE is not set CONFIG_I2C_SIMTEC=m # CONFIG_I2C_ST is not set # CONFIG_I2C_STM32F4 is not set # CONFIG_I2C_STM32F7 is not set # CONFIG_I2C_SYNQUACER is not set # CONFIG_I2C_TEGRA_BPMP is not set # CONFIG_I2C_UNIPHIER is not set # CONFIG_I2C_UNIPHIER_F is not set # CONFIG_I2C_VERSATILE is not set # CONFIG_I2C_WMT is not set # CONFIG_I2C_THUNDERX is not set CONFIG_I2C_XILINX=m # CONFIG_I2C_XLP9XX is not set # CONFIG_I2C_RCAR is not set # # External I2C/SMBus adapter drivers # # CONFIG_I2C_PARPORT is not set CONFIG_I2C_PCI1XXXX=m # CONFIG_I2C_TAOS_EVM is not set # # Other I2C/SMBus bus drivers # # CONFIG_I2C_MLXCPLD is not set CONFIG_I2C_VIRTIO=y # end of I2C Hardware Bus support CONFIG_I2C_STUB=m CONFIG_I2C_SLAVE=y # CONFIG_I2C_SLAVE_EEPROM is not set CONFIG_I2C_SLAVE_TESTUNIT=m # CONFIG_I2C_DEBUG_CORE is not set CONFIG_I2C_DEBUG_ALGO=y # CONFIG_I2C_DEBUG_BUS is not set # end of I2C support CONFIG_I3C=y # CONFIG_CDNS_I3C_MASTER is not set # CONFIG_DW_I3C_MASTER is not set CONFIG_SVC_I3C_MASTER=y CONFIG_MIPI_I3C_HCI=m CONFIG_SPI=y CONFIG_SPI_DEBUG=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y # # SPI Master Controller Drivers # CONFIG_SPI_ALTERA=m CONFIG_SPI_ALTERA_CORE=m # CONFIG_SPI_ALTERA_DFL is not set # CONFIG_SPI_AR934X is not set # CONFIG_SPI_ATH79 is not set # CONFIG_SPI_ARMADA_3700 is not set CONFIG_SPI_AXI_SPI_ENGINE=y # CONFIG_SPI_BCM2835 is not set # CONFIG_SPI_BCM2835AUX is not set # CONFIG_SPI_BCM63XX is not set # CONFIG_SPI_BCM63XX_HSSPI is not set # CONFIG_SPI_BCM_QSPI is not set CONFIG_SPI_BITBANG=y CONFIG_SPI_BUTTERFLY=m # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_XSPI is not set # CONFIG_SPI_CLPS711X is not set CONFIG_SPI_DESIGNWARE=y CONFIG_SPI_DW_DMA=y CONFIG_SPI_DW_PCI=m CONFIG_SPI_DW_MMIO=y # CONFIG_SPI_DW_BT1 is not set # CONFIG_SPI_EP93XX is not set # CONFIG_SPI_FSL_LPSPI is not set # CONFIG_SPI_FSL_QUADSPI is not set # CONFIG_SPI_GXP is not set # CONFIG_SPI_HISI_KUNPENG is not set # CONFIG_SPI_HISI_SFC_V3XX is not set CONFIG_SPI_NXP_FLEXSPI=y CONFIG_SPI_GPIO=y # CONFIG_SPI_IMG_SPFI is not set # CONFIG_SPI_IMX is not set # CONFIG_SPI_INGENIC is not set # CONFIG_SPI_INTEL_PCI is not set # CONFIG_SPI_INTEL_PLATFORM is not set CONFIG_SPI_LM70_LLP=m # CONFIG_SPI_LP8841_RTC is not set # CONFIG_SPI_FSL_DSPI is not set # CONFIG_SPI_MESON_SPIFC is not set CONFIG_SPI_MICROCHIP_CORE=y CONFIG_SPI_MICROCHIP_CORE_QSPI=y # CONFIG_SPI_MT65XX is not set # CONFIG_SPI_MT7621 is not set # CONFIG_SPI_MTK_NOR is not set # CONFIG_SPI_NPCM_PSPI is not set # CONFIG_SPI_LANTIQ_SSC is not set # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_OMAP24XX is not set # CONFIG_SPI_TI_QSPI is not set # CONFIG_SPI_OMAP_100K is not set # CONFIG_SPI_ORION is not set # CONFIG_SPI_PIC32 is not set # CONFIG_SPI_PIC32_SQI is not set CONFIG_SPI_PXA2XX=m CONFIG_SPI_ROCKCHIP=y # CONFIG_SPI_ROCKCHIP_SFC is not set # CONFIG_SPI_RSPI is not set # CONFIG_SPI_QUP is not set # CONFIG_SPI_S3C64XX is not set CONFIG_SPI_SC18IS602=y # CONFIG_SPI_SH is not set # CONFIG_SPI_SH_HSPI is not set CONFIG_SPI_SIFIVE=y # CONFIG_SPI_SLAVE_MT27XX is not set # CONFIG_SPI_SPRD is not set # CONFIG_SPI_SPRD_ADI is not set # CONFIG_SPI_STM32 is not set # CONFIG_SPI_ST_SSC4 is not set # CONFIG_SPI_SUN4I is not set # CONFIG_SPI_SUNPLUS_SP7021 is not set # CONFIG_SPI_SYNQUACER is not set CONFIG_SPI_MXIC=m # CONFIG_SPI_THUNDERX is not set # CONFIG_SPI_TOPCLIFF_PCH is not set CONFIG_SPI_XCOMM=y # CONFIG_SPI_XILINX is not set # CONFIG_SPI_XLP is not set # CONFIG_SPI_XTENSA_XTFPGA is not set # CONFIG_SPI_ZYNQ_QSPI is not set CONFIG_SPI_ZYNQMP_GQSPI=m CONFIG_SPI_AMD=m # # SPI Multiplexer support # CONFIG_SPI_MUX=y # # SPI Protocol Masters # CONFIG_SPI_SPIDEV=y CONFIG_SPI_LOOPBACK_TEST=m # CONFIG_SPI_TLE62X0 is not set CONFIG_SPI_SLAVE=y # CONFIG_SPI_SLAVE_TIME is not set CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y CONFIG_SPI_DYNAMIC=y CONFIG_SPMI=m # CONFIG_SPMI_HISI3670 is not set # CONFIG_SPMI_MSM_PMIC_ARB is not set # CONFIG_SPMI_MTK_PMIF is not set # CONFIG_HSI is not set CONFIG_PPS=y CONFIG_PPS_DEBUG=y # # PPS clients support # CONFIG_PPS_CLIENT_KTIMER=y # CONFIG_PPS_CLIENT_LDISC is not set # CONFIG_PPS_CLIENT_PARPORT is not set # CONFIG_PPS_CLIENT_GPIO is not set # # PPS generators support # # # PTP clock support # CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # # end of PTP clock support CONFIG_PINCTRL=y CONFIG_PINMUX=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set # CONFIG_PINCTRL_AMD is not set # CONFIG_PINCTRL_CY8C95X0 is not set CONFIG_PINCTRL_MCP23S08_I2C=y CONFIG_PINCTRL_MCP23S08_SPI=y CONFIG_PINCTRL_MCP23S08=y CONFIG_PINCTRL_SX150X=y CONFIG_PINCTRL_MADERA=m CONFIG_PINCTRL_CS47L15=y CONFIG_PINCTRL_CS47L35=y CONFIG_PINCTRL_CS47L92=y CONFIG_PINCTRL_CS48L32=y # # Intel pinctrl drivers # # end of Intel pinctrl drivers # # MediaTek pinctrl drivers # # CONFIG_EINT_MTK is not set # end of MediaTek pinctrl drivers # CONFIG_PINCTRL_PXA25X is not set # CONFIG_PINCTRL_PXA27X is not set # CONFIG_PINCTRL_MSM is not set # CONFIG_PINCTRL_LPASS_LPI is not set # # Renesas pinctrl drivers # # CONFIG_PINCTRL_RENESAS is not set # CONFIG_PINCTRL_PFC_EMEV2 is not set # CONFIG_PINCTRL_PFC_R8A77995 is not set # CONFIG_PINCTRL_PFC_R8A7794 is not set # CONFIG_PINCTRL_PFC_R8A77990 is not set # CONFIG_PINCTRL_PFC_R8A7779 is not set # CONFIG_PINCTRL_PFC_R8A7790 is not set # CONFIG_PINCTRL_PFC_R8A77950 is not set # CONFIG_PINCTRL_PFC_R8A77951 is not set # CONFIG_PINCTRL_PFC_R8A7778 is not set # CONFIG_PINCTRL_PFC_R8A7793 is not set # CONFIG_PINCTRL_PFC_R8A7791 is not set # CONFIG_PINCTRL_PFC_R8A77965 is not set # CONFIG_PINCTRL_PFC_R8A77960 is not set # CONFIG_PINCTRL_PFC_R8A77961 is not set # CONFIG_PINCTRL_PFC_R8A779F0 is not set # CONFIG_PINCTRL_PFC_R8A7792 is not set # CONFIG_PINCTRL_PFC_R8A77980 is not set # CONFIG_PINCTRL_PFC_R8A77970 is not set # CONFIG_PINCTRL_PFC_R8A779A0 is not set # CONFIG_PINCTRL_PFC_R8A779G0 is not set # CONFIG_PINCTRL_PFC_R8A7740 is not set # CONFIG_PINCTRL_PFC_R8A73A4 is not set # CONFIG_PINCTRL_PFC_R8A77470 is not set # CONFIG_PINCTRL_PFC_R8A7745 is not set # CONFIG_PINCTRL_PFC_R8A7742 is not set # CONFIG_PINCTRL_PFC_R8A7743 is not set # CONFIG_PINCTRL_PFC_R8A7744 is not set # CONFIG_PINCTRL_PFC_R8A774C0 is not set # CONFIG_PINCTRL_PFC_R8A774E1 is not set # CONFIG_PINCTRL_PFC_R8A774A1 is not set # CONFIG_PINCTRL_PFC_R8A774B1 is not set # CONFIG_PINCTRL_PFC_SH7203 is not set # CONFIG_PINCTRL_PFC_SH7264 is not set # CONFIG_PINCTRL_PFC_SH7269 is not set # CONFIG_PINCTRL_PFC_SH7720 is not set # CONFIG_PINCTRL_PFC_SH7722 is not set # CONFIG_PINCTRL_PFC_SH7734 is not set # CONFIG_PINCTRL_PFC_SH7757 is not set # CONFIG_PINCTRL_PFC_SH7785 is not set # CONFIG_PINCTRL_PFC_SH7786 is not set # CONFIG_PINCTRL_PFC_SH73A0 is not set # CONFIG_PINCTRL_PFC_SH7723 is not set # CONFIG_PINCTRL_PFC_SH7724 is not set # CONFIG_PINCTRL_PFC_SHX3 is not set # end of Renesas pinctrl drivers CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_GPIOLIB_IRQCHIP=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y # # Memory mapped GPIO drivers # # CONFIG_GPIO_ATH79 is not set # CONFIG_GPIO_CLPS711X is not set CONFIG_GPIO_DWAPB=y # CONFIG_GPIO_GENERIC_PLATFORM is not set # CONFIG_GPIO_HISI is not set # CONFIG_GPIO_IOP is not set CONFIG_GPIO_MB86S7X=y # CONFIG_GPIO_MENZ127 is not set # CONFIG_GPIO_MPC8XXX is not set # CONFIG_GPIO_MXC is not set # CONFIG_GPIO_MXS is not set # CONFIG_GPIO_PXA is not set # CONFIG_GPIO_RCAR is not set # CONFIG_GPIO_ROCKCHIP is not set # CONFIG_GPIO_THUNDERX is not set # CONFIG_GPIO_VX855 is not set # CONFIG_GPIO_XGENE_SB is not set # CONFIG_GPIO_XLP is not set CONFIG_GPIO_AMD_FCH=m # CONFIG_GPIO_IDT3243X is not set # end of Memory mapped GPIO drivers # # I2C GPIO expanders # # CONFIG_GPIO_MAX7300 is not set CONFIG_GPIO_MAX732X=m # CONFIG_GPIO_PCA953X is not set CONFIG_GPIO_PCA9570=y # CONFIG_GPIO_PCF857X is not set CONFIG_GPIO_TPIC2810=m # CONFIG_GPIO_TS4900 is not set # end of I2C GPIO expanders # # MFD GPIO expanders # CONFIG_GPIO_ARIZONA=y # CONFIG_GPIO_BD9571MWV is not set # CONFIG_GPIO_DA9052 is not set # CONFIG_GPIO_LP3943 is not set CONFIG_GPIO_LP873X=m # CONFIG_GPIO_MADERA is not set CONFIG_GPIO_PALMAS=y # CONFIG_GPIO_SL28CPLD is not set CONFIG_GPIO_TPS65086=m CONFIG_GPIO_TPS65910=y CONFIG_GPIO_TPS65912=m CONFIG_GPIO_TWL4030=m CONFIG_GPIO_TWL6040=y CONFIG_GPIO_WM831X=y # CONFIG_GPIO_WM8350 is not set CONFIG_GPIO_WM8994=m # end of MFD GPIO expanders # # PCI GPIO expanders # # CONFIG_GPIO_BT8XX is not set # CONFIG_GPIO_MLXBF is not set # CONFIG_GPIO_MLXBF2 is not set # CONFIG_GPIO_ML_IOH is not set # CONFIG_GPIO_PCH is not set CONFIG_GPIO_PCI_IDIO_16=y CONFIG_GPIO_PCIE_IDIO_24=m CONFIG_GPIO_RDC321X=m # end of PCI GPIO expanders # # SPI GPIO expanders # CONFIG_GPIO_MAX3191X=m # CONFIG_GPIO_MAX7301 is not set # CONFIG_GPIO_MC33880 is not set CONFIG_GPIO_PISOSR=y CONFIG_GPIO_XRA1403=y # end of SPI GPIO expanders # # Virtual GPIO drivers # CONFIG_GPIO_AGGREGATOR=y # CONFIG_GPIO_MOCKUP is not set CONFIG_GPIO_VIRTIO=y CONFIG_GPIO_SIM=y # end of Virtual GPIO drivers CONFIG_W1=y # # 1-wire Bus Masters # CONFIG_W1_MASTER_MATROX=y CONFIG_W1_MASTER_DS2482=m # CONFIG_W1_MASTER_MXC is not set CONFIG_W1_MASTER_DS1WM=y # CONFIG_W1_MASTER_GPIO is not set CONFIG_W1_MASTER_SGI=y # end of 1-wire Bus Masters # # 1-wire Slaves # CONFIG_W1_SLAVE_THERM=m CONFIG_W1_SLAVE_SMEM=m CONFIG_W1_SLAVE_DS2405=y CONFIG_W1_SLAVE_DS2408=m CONFIG_W1_SLAVE_DS2408_READBACK=y CONFIG_W1_SLAVE_DS2413=m CONFIG_W1_SLAVE_DS2406=y # CONFIG_W1_SLAVE_DS2423 is not set CONFIG_W1_SLAVE_DS2805=m # CONFIG_W1_SLAVE_DS2430 is not set # CONFIG_W1_SLAVE_DS2431 is not set # CONFIG_W1_SLAVE_DS2433 is not set # CONFIG_W1_SLAVE_DS2438 is not set CONFIG_W1_SLAVE_DS250X=m CONFIG_W1_SLAVE_DS2780=y CONFIG_W1_SLAVE_DS2781=y # CONFIG_W1_SLAVE_DS28E04 is not set # CONFIG_W1_SLAVE_DS28E17 is not set # end of 1-wire Slaves # CONFIG_POWER_RESET is not set CONFIG_POWER_SUPPLY=y CONFIG_POWER_SUPPLY_DEBUG=y CONFIG_POWER_SUPPLY_HWMON=y CONFIG_GENERIC_ADC_BATTERY=m CONFIG_IP5XXX_POWER=y CONFIG_MAX8925_POWER=y CONFIG_WM831X_BACKUP=m CONFIG_WM831X_POWER=m CONFIG_WM8350_POWER=m CONFIG_TEST_POWER=m CONFIG_BATTERY_88PM860X=y CONFIG_CHARGER_ADP5061=y # CONFIG_BATTERY_ACT8945A is not set # CONFIG_BATTERY_CW2015 is not set CONFIG_BATTERY_DS2760=y # CONFIG_BATTERY_DS2780 is not set CONFIG_BATTERY_DS2781=y CONFIG_BATTERY_DS2782=m # CONFIG_BATTERY_SAMSUNG_SDI is not set CONFIG_BATTERY_SBS=y CONFIG_CHARGER_SBS=y CONFIG_MANAGER_SBS=y CONFIG_BATTERY_BQ27XXX=m # CONFIG_BATTERY_BQ27XXX_I2C is not set CONFIG_BATTERY_BQ27XXX_HDQ=m CONFIG_BATTERY_DA9030=y CONFIG_BATTERY_DA9052=m CONFIG_CHARGER_DA9150=m # CONFIG_BATTERY_DA9150 is not set CONFIG_BATTERY_MAX17040=y # CONFIG_BATTERY_MAX17042 is not set CONFIG_BATTERY_MAX1721X=y CONFIG_BATTERY_TWL4030_MADC=m CONFIG_CHARGER_88PM860X=m CONFIG_CHARGER_PCF50633=m CONFIG_BATTERY_RX51=m # CONFIG_CHARGER_MAX8903 is not set CONFIG_CHARGER_TWL4030=m CONFIG_CHARGER_LP8727=y CONFIG_CHARGER_GPIO=m CONFIG_CHARGER_LT3651=m CONFIG_CHARGER_LTC4162L=y # CONFIG_CHARGER_MAX14577 is not set # CONFIG_CHARGER_MAX77693 is not set CONFIG_CHARGER_MAX77976=m CONFIG_CHARGER_BQ2415X=y CONFIG_CHARGER_BQ24257=m CONFIG_CHARGER_BQ24735=m CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ25890=y CONFIG_CHARGER_BQ25980=m CONFIG_CHARGER_BQ256XX=m # CONFIG_CHARGER_TPS65090 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set CONFIG_BATTERY_GOLDFISH=m CONFIG_BATTERY_RT5033=m # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_SC2731 is not set # CONFIG_FUEL_GAUGE_SC27XX is not set CONFIG_CHARGER_BD99954=m # CONFIG_BATTERY_UG3105 is not set CONFIG_HWMON=y CONFIG_HWMON_VID=y CONFIG_HWMON_DEBUG_CHIP=y # # Native drivers # CONFIG_SENSORS_AD7314=y # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set CONFIG_SENSORS_ADM1025=y # CONFIG_SENSORS_ADM1026 is not set CONFIG_SENSORS_ADM1029=y CONFIG_SENSORS_ADM1031=m # CONFIG_SENSORS_ADM1177 is not set CONFIG_SENSORS_ADM9240=m CONFIG_SENSORS_ADT7X10=y CONFIG_SENSORS_ADT7310=y CONFIG_SENSORS_ADT7410=m CONFIG_SENSORS_ADT7411=y # CONFIG_SENSORS_ADT7462 is not set CONFIG_SENSORS_ADT7470=y CONFIG_SENSORS_ADT7475=m # CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ASB100 is not set # CONFIG_SENSORS_ASPEED is not set CONFIG_SENSORS_ATXP1=y # CONFIG_SENSORS_BT1_PVT is not set CONFIG_SENSORS_DS620=m CONFIG_SENSORS_DS1621=m # CONFIG_SENSORS_DA9052_ADC is not set # CONFIG_SENSORS_I5K_AMB is not set # CONFIG_SENSORS_SPARX5 is not set CONFIG_SENSORS_F71805F=y # CONFIG_SENSORS_F71882FG is not set CONFIG_SENSORS_F75375S=y CONFIG_SENSORS_MC13783_ADC=m # CONFIG_SENSORS_FSCHMD is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set CONFIG_SENSORS_G760A=m CONFIG_SENSORS_G762=y CONFIG_SENSORS_HIH6130=y CONFIG_SENSORS_IBMAEM=m CONFIG_SENSORS_IBMPEX=y CONFIG_SENSORS_IIO_HWMON=m CONFIG_SENSORS_IT87=m CONFIG_SENSORS_JC42=m CONFIG_SENSORS_POWR1220=m # CONFIG_SENSORS_LAN966X is not set # CONFIG_SENSORS_LINEAGE is not set CONFIG_SENSORS_LTC2945=y CONFIG_SENSORS_LTC2947=y CONFIG_SENSORS_LTC2947_I2C=m CONFIG_SENSORS_LTC2947_SPI=y # CONFIG_SENSORS_LTC2990 is not set CONFIG_SENSORS_LTC2992=m CONFIG_SENSORS_LTC4151=y CONFIG_SENSORS_LTC4215=m # CONFIG_SENSORS_LTC4222 is not set CONFIG_SENSORS_LTC4245=m # CONFIG_SENSORS_LTC4260 is not set CONFIG_SENSORS_LTC4261=y CONFIG_SENSORS_MAX1111=m CONFIG_SENSORS_MAX127=y CONFIG_SENSORS_MAX16065=y CONFIG_SENSORS_MAX1619=y # CONFIG_SENSORS_MAX1668 is not set CONFIG_SENSORS_MAX197=m CONFIG_SENSORS_MAX31722=m CONFIG_SENSORS_MAX31730=y # CONFIG_SENSORS_MAX31760 is not set CONFIG_SENSORS_MAX6620=m CONFIG_SENSORS_MAX6621=m # CONFIG_SENSORS_MAX6639 is not set CONFIG_SENSORS_MAX6650=y # CONFIG_SENSORS_MAX6697 is not set CONFIG_SENSORS_MAX31790=m # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set CONFIG_SENSORS_TPS23861=m CONFIG_SENSORS_MR75203=y # CONFIG_SENSORS_ADCXX is not set CONFIG_SENSORS_LM63=m CONFIG_SENSORS_LM70=m CONFIG_SENSORS_LM73=m CONFIG_SENSORS_LM75=m # CONFIG_SENSORS_LM77 is not set CONFIG_SENSORS_LM78=m CONFIG_SENSORS_LM80=y CONFIG_SENSORS_LM83=m CONFIG_SENSORS_LM85=y CONFIG_SENSORS_LM87=m CONFIG_SENSORS_LM90=m CONFIG_SENSORS_LM92=y CONFIG_SENSORS_LM93=y # CONFIG_SENSORS_LM95234 is not set # CONFIG_SENSORS_LM95241 is not set CONFIG_SENSORS_LM95245=m CONFIG_SENSORS_PC87360=m CONFIG_SENSORS_PC87427=y # CONFIG_SENSORS_NTC_THERMISTOR is not set CONFIG_SENSORS_NCT6683=y CONFIG_SENSORS_NCT6775_CORE=m CONFIG_SENSORS_NCT6775=m CONFIG_SENSORS_NCT6775_I2C=m CONFIG_SENSORS_NCT7802=m CONFIG_SENSORS_NPCM7XX=y # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set CONFIG_PMBUS=y # CONFIG_SENSORS_PMBUS is not set # CONFIG_SENSORS_ADM1266 is not set CONFIG_SENSORS_ADM1275=m # CONFIG_SENSORS_BEL_PFE is not set CONFIG_SENSORS_BPA_RS600=y CONFIG_SENSORS_DELTA_AHE50DC_FAN=y CONFIG_SENSORS_FSP_3Y=m # CONFIG_SENSORS_IBM_CFFPS is not set CONFIG_SENSORS_DPS920AB=y CONFIG_SENSORS_INSPUR_IPSPS=y # CONFIG_SENSORS_IR35221 is not set # CONFIG_SENSORS_IR36021 is not set CONFIG_SENSORS_IR38064=m # CONFIG_SENSORS_IRPS5401 is not set # CONFIG_SENSORS_ISL68137 is not set CONFIG_SENSORS_LM25066=y CONFIG_SENSORS_LT7182S=m CONFIG_SENSORS_LTC2978=y CONFIG_SENSORS_LTC3815=m # CONFIG_SENSORS_MAX15301 is not set CONFIG_SENSORS_MAX16064=m CONFIG_SENSORS_MAX16601=y # CONFIG_SENSORS_MAX20730 is not set CONFIG_SENSORS_MAX20751=m CONFIG_SENSORS_MAX31785=y CONFIG_SENSORS_MAX34440=m CONFIG_SENSORS_MAX8688=m # CONFIG_SENSORS_MP2888 is not set CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP5023=y CONFIG_SENSORS_PIM4328=m CONFIG_SENSORS_PLI1209BC=m # CONFIG_SENSORS_PM6764TR is not set # CONFIG_SENSORS_PXE1610 is not set CONFIG_SENSORS_Q54SJ108A2=y CONFIG_SENSORS_STPDDC60=y CONFIG_SENSORS_TPS40422=y # CONFIG_SENSORS_TPS53679 is not set # CONFIG_SENSORS_TPS546D24 is not set # CONFIG_SENSORS_UCD9000 is not set CONFIG_SENSORS_UCD9200=y # CONFIG_SENSORS_XDPE152 is not set CONFIG_SENSORS_XDPE122=y CONFIG_SENSORS_ZL6100=y # CONFIG_SENSORS_PWM_FAN is not set # CONFIG_SENSORS_RASPBERRYPI_HWMON is not set # CONFIG_SENSORS_SL28CPLD is not set CONFIG_SENSORS_SBTSI=m # CONFIG_SENSORS_SBRMI is not set CONFIG_SENSORS_SHT15=y CONFIG_SENSORS_SHT21=y # CONFIG_SENSORS_SHT3x is not set CONFIG_SENSORS_SHT4x=y # CONFIG_SENSORS_SHTC1 is not set CONFIG_SENSORS_SIS5595=y CONFIG_SENSORS_SY7636A=y CONFIG_SENSORS_DME1737=y # CONFIG_SENSORS_EMC1403 is not set CONFIG_SENSORS_EMC2103=y # CONFIG_SENSORS_EMC2305 is not set CONFIG_SENSORS_EMC6W201=m # CONFIG_SENSORS_SMSC47M1 is not set CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47B397=y # CONFIG_SENSORS_STTS751 is not set CONFIG_SENSORS_SMM665=m CONFIG_SENSORS_ADC128D818=y CONFIG_SENSORS_ADS7828=y CONFIG_SENSORS_ADS7871=y CONFIG_SENSORS_AMC6821=y # CONFIG_SENSORS_INA209 is not set CONFIG_SENSORS_INA2XX=y CONFIG_SENSORS_INA238=m CONFIG_SENSORS_INA3221=y CONFIG_SENSORS_TC74=y # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP102 is not set CONFIG_SENSORS_TMP103=y # CONFIG_SENSORS_TMP108 is not set CONFIG_SENSORS_TMP401=m CONFIG_SENSORS_TMP421=y CONFIG_SENSORS_TMP464=m CONFIG_SENSORS_TMP513=m CONFIG_SENSORS_VIA686A=y CONFIG_SENSORS_VT1211=m CONFIG_SENSORS_VT8231=m CONFIG_SENSORS_W83773G=m # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set # CONFIG_SENSORS_W83792D is not set CONFIG_SENSORS_W83793=m CONFIG_SENSORS_W83795=m # CONFIG_SENSORS_W83795_FANCTRL is not set CONFIG_SENSORS_W83L785TS=m # CONFIG_SENSORS_W83L786NG is not set CONFIG_SENSORS_W83627HF=y # CONFIG_SENSORS_W83627EHF is not set CONFIG_SENSORS_WM831X=y CONFIG_SENSORS_WM8350=y # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y CONFIG_SSB=y CONFIG_SSB_SPROM=y CONFIG_SSB_PCIHOST_POSSIBLE=y # CONFIG_SSB_PCIHOST is not set CONFIG_SSB_PCMCIAHOST_POSSIBLE=y CONFIG_SSB_PCMCIAHOST=y CONFIG_SSB_SDIOHOST_POSSIBLE=y CONFIG_SSB_SDIOHOST=y CONFIG_SSB_DRIVER_GPIO=y CONFIG_BCMA_POSSIBLE=y # CONFIG_BCMA is not set # # Multifunction device drivers # CONFIG_MFD_CORE=y # CONFIG_MFD_SUN4I_GPADC is not set # CONFIG_MFD_AS3711 is not set # CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_AT91_USART is not set CONFIG_MFD_BCM590XX=y CONFIG_MFD_BD9571MWV=y # CONFIG_MFD_AXP20X_I2C is not set CONFIG_MFD_MADERA=m CONFIG_MFD_MADERA_I2C=m CONFIG_MFD_MADERA_SPI=m CONFIG_MFD_CS47L15=y CONFIG_MFD_CS47L35=y # CONFIG_MFD_CS47L85 is not set # CONFIG_MFD_CS47L90 is not set CONFIG_MFD_CS47L92=y CONFIG_MFD_CS48L32=y # CONFIG_MFD_ASIC3 is not set CONFIG_PMIC_DA903X=y CONFIG_PMIC_DA9052=y CONFIG_MFD_DA9052_SPI=y # CONFIG_MFD_DA9052_I2C is not set # CONFIG_MFD_DA9055 is not set # CONFIG_MFD_DA9062 is not set CONFIG_MFD_DA9063=y CONFIG_MFD_DA9150=m # CONFIG_MFD_ENE_KB3930 is not set # CONFIG_MFD_EXYNOS_LPASS is not set CONFIG_MFD_MC13XXX=y CONFIG_MFD_MC13XXX_SPI=y CONFIG_MFD_MC13XXX_I2C=m # CONFIG_MFD_MP2629 is not set # CONFIG_MFD_MXS_LRADC is not set # CONFIG_MFD_MX25_TSADC is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_HTC_I2CPLD is not set CONFIG_LPC_ICH=m CONFIG_LPC_SCH=m # CONFIG_MFD_IQS62X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set CONFIG_MFD_88PM800=m # CONFIG_MFD_88PM805 is not set CONFIG_MFD_88PM860X=y CONFIG_MFD_MAX14577=y # CONFIG_MFD_MAX77620 is not set # CONFIG_MFD_MAX77650 is not set # CONFIG_MFD_MAX77686 is not set CONFIG_MFD_MAX77693=y # CONFIG_MFD_MAX77714 is not set # CONFIG_MFD_MAX77843 is not set CONFIG_MFD_MAX8907=y CONFIG_MFD_MAX8925=y # CONFIG_MFD_MAX8997 is not set CONFIG_MFD_MAX8998=y CONFIG_MFD_MT6360=m CONFIG_MFD_MT6370=m CONFIG_MFD_MT6397=y # CONFIG_MFD_MENF21BMC is not set CONFIG_MFD_OCELOT=y CONFIG_EZX_PCAP=y # CONFIG_MFD_CPCAP is not set # CONFIG_MFD_NTXEC is not set # CONFIG_MFD_RETU is not set CONFIG_MFD_PCF50633=y # CONFIG_PCF50633_ADC is not set CONFIG_PCF50633_GPIO=y # CONFIG_MFD_PM8XXX is not set CONFIG_MFD_SY7636A=y CONFIG_MFD_RDC321X=y # CONFIG_MFD_RT4831 is not set CONFIG_MFD_RT5033=y # CONFIG_MFD_RT5120 is not set # CONFIG_MFD_RC5T583 is not set # CONFIG_MFD_SEC_CORE is not set CONFIG_MFD_SI476X_CORE=y CONFIG_MFD_SIMPLE_MFD_I2C=y # CONFIG_MFD_SL28CPLD is not set # CONFIG_MFD_SM501 is not set CONFIG_MFD_SKY81452=y # CONFIG_MFD_SC27XX_PMIC is not set # CONFIG_ABX500_CORE is not set # CONFIG_MFD_SUN6I_PRCM is not set CONFIG_MFD_SYSCON=y CONFIG_MFD_TI_AM335X_TSCADC=m CONFIG_MFD_LP3943=y # CONFIG_MFD_LP8788 is not set CONFIG_MFD_TI_LMU=y CONFIG_MFD_PALMAS=y # CONFIG_TPS6105X is not set # CONFIG_TPS65010 is not set # CONFIG_TPS6507X is not set CONFIG_MFD_TPS65086=m CONFIG_MFD_TPS65090=y CONFIG_MFD_TI_LP873X=m # CONFIG_MFD_TPS6586X is not set CONFIG_MFD_TPS65910=y CONFIG_MFD_TPS65912=m # CONFIG_MFD_TPS65912_I2C is not set CONFIG_MFD_TPS65912_SPI=m CONFIG_TWL4030_CORE=y # CONFIG_MFD_TWL4030_AUDIO is not set CONFIG_TWL6040_CORE=y CONFIG_MFD_WL1273_CORE=m CONFIG_MFD_LM3533=m # CONFIG_MFD_TIMBERDALE is not set CONFIG_MFD_TQMX86=y CONFIG_MFD_VX855=y CONFIG_MFD_ARIZONA=y CONFIG_MFD_ARIZONA_I2C=m CONFIG_MFD_ARIZONA_SPI=y CONFIG_MFD_CS47L24=y CONFIG_MFD_WM5102=y # CONFIG_MFD_WM5110 is not set # CONFIG_MFD_WM8997 is not set # CONFIG_MFD_WM8998 is not set # CONFIG_MFD_WM8400 is not set CONFIG_MFD_WM831X=y CONFIG_MFD_WM831X_I2C=y CONFIG_MFD_WM831X_SPI=y CONFIG_MFD_WM8350=y CONFIG_MFD_WM8350_I2C=y CONFIG_MFD_WM8994=m # CONFIG_MFD_STW481X is not set # CONFIG_MFD_STM32_LPTIMER is not set # CONFIG_MFD_STM32_TIMERS is not set # CONFIG_MFD_STMFX is not set # CONFIG_MFD_WCD934X is not set CONFIG_MFD_ATC260X=m CONFIG_MFD_ATC260X_I2C=m # CONFIG_MFD_KHADAS_MCU is not set # CONFIG_MFD_ACER_A500_EC is not set # CONFIG_MFD_INTEL_M10_BMC is not set # end of Multifunction device drivers # CONFIG_REGULATOR is not set CONFIG_RC_CORE=m # CONFIG_LIRC is not set # CONFIG_RC_MAP is not set CONFIG_RC_DECODERS=y CONFIG_IR_IMON_DECODER=m # CONFIG_IR_JVC_DECODER is not set CONFIG_IR_MCE_KBD_DECODER=m CONFIG_IR_NEC_DECODER=m # CONFIG_IR_RC5_DECODER is not set # CONFIG_IR_RC6_DECODER is not set # CONFIG_IR_RCMM_DECODER is not set CONFIG_IR_SANYO_DECODER=m # CONFIG_IR_SHARP_DECODER is not set CONFIG_IR_SONY_DECODER=m CONFIG_IR_XMP_DECODER=m # CONFIG_RC_DEVICES is not set # # CEC support # # CONFIG_MEDIA_CEC_SUPPORT is not set # end of CEC support # CONFIG_MEDIA_SUPPORT is not set # # Graphics support # CONFIG_APERTURE_HELPERS=y # CONFIG_IMX_IPUV3_CORE is not set # CONFIG_DRM is not set CONFIG_DRM_DEBUG_MODESET_LOCK=y # # ARM devices # # end of ARM devices # # Frame buffer Devices # CONFIG_FB_CMDLINE=y CONFIG_FB_NOTIFY=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_DDC=y CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y CONFIG_FB_SYS_FILLRECT=y CONFIG_FB_SYS_COPYAREA=y CONFIG_FB_SYS_IMAGEBLIT=y CONFIG_FB_FOREIGN_ENDIAN=y # CONFIG_FB_BOTH_ENDIAN is not set CONFIG_FB_BIG_ENDIAN=y # CONFIG_FB_LITTLE_ENDIAN is not set CONFIG_FB_SYS_FOPS=y CONFIG_FB_DEFERRED_IO=y CONFIG_FB_SVGALIB=m CONFIG_FB_BACKLIGHT=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y # # Frame buffer hardware drivers # CONFIG_FB_CIRRUS=y # CONFIG_FB_PM2 is not set # CONFIG_FB_CLPS711X is not set # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_ARC is not set # CONFIG_FB_CONTROL is not set CONFIG_FB_ASILIANT=y CONFIG_FB_IMSTT=y # CONFIG_FB_GBE is not set # CONFIG_FB_PVR2 is not set CONFIG_FB_OPENCORES=y CONFIG_FB_S1D13XXX=y # CONFIG_FB_NVIDIA is not set CONFIG_FB_RIVA=m CONFIG_FB_RIVA_I2C=y # CONFIG_FB_RIVA_DEBUG is not set # CONFIG_FB_RIVA_BACKLIGHT is not set # CONFIG_FB_I740 is not set # CONFIG_FB_MATROX is not set # CONFIG_FB_RADEON is not set CONFIG_FB_ATY128=m # CONFIG_FB_ATY128_BACKLIGHT is not set CONFIG_FB_ATY=y CONFIG_FB_ATY_CT=y # CONFIG_FB_ATY_GENERIC_LCD is not set CONFIG_FB_ATY_GX=y CONFIG_FB_ATY_BACKLIGHT=y CONFIG_FB_S3=m CONFIG_FB_S3_DDC=y CONFIG_FB_SAVAGE=m CONFIG_FB_SAVAGE_I2C=y CONFIG_FB_SAVAGE_ACCEL=y # CONFIG_FB_SIS is not set # CONFIG_FB_VIA is not set CONFIG_FB_NEOMAGIC=y # CONFIG_FB_KYRO is not set CONFIG_FB_3DFX=y CONFIG_FB_3DFX_ACCEL=y # CONFIG_FB_3DFX_I2C is not set CONFIG_FB_VOODOO1=m # CONFIG_FB_VT8623 is not set CONFIG_FB_TRIDENT=y CONFIG_FB_ARK=m CONFIG_FB_PM3=y CONFIG_FB_CARMINE=m CONFIG_FB_CARMINE_DRAM_EVAL=y # CONFIG_CARMINE_DRAM_CUSTOM is not set # CONFIG_FB_WM8505 is not set # CONFIG_FB_W100 is not set # CONFIG_FB_TMIO is not set CONFIG_FB_IBM_GXT4500=m # CONFIG_FB_GOLDFISH is not set CONFIG_FB_VIRTUAL=y # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set # CONFIG_FB_BROADSHEET is not set CONFIG_FB_SIMPLE=y CONFIG_FB_SSD1307=y CONFIG_FB_SM712=y # CONFIG_MMP_DISP is not set # end of Frame buffer Devices # # Backlight & LCD device support # CONFIG_LCD_CLASS_DEVICE=y # CONFIG_LCD_L4F00242T03 is not set CONFIG_LCD_LMS283GF05=m CONFIG_LCD_LTV350QV=y # CONFIG_LCD_ILI922X is not set CONFIG_LCD_ILI9320=y # CONFIG_LCD_TDO24M is not set CONFIG_LCD_VGG2432A4=y CONFIG_LCD_PLATFORM=m CONFIG_LCD_AMS369FG06=m CONFIG_LCD_LMS501KF03=y CONFIG_LCD_HX8357=y CONFIG_LCD_OTM3225A=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_KTD253=y CONFIG_BACKLIGHT_LM3533=m # CONFIG_BACKLIGHT_OMAP1 is not set CONFIG_BACKLIGHT_PWM=m # CONFIG_BACKLIGHT_DA903X is not set # CONFIG_BACKLIGHT_DA9052 is not set # CONFIG_BACKLIGHT_MAX8925 is not set CONFIG_BACKLIGHT_MT6370=m CONFIG_BACKLIGHT_QCOM_WLED=y # CONFIG_BACKLIGHT_WM831X is not set # CONFIG_BACKLIGHT_ADP8860 is not set CONFIG_BACKLIGHT_ADP8870=m # CONFIG_BACKLIGHT_88PM860X is not set CONFIG_BACKLIGHT_PCF50633=y CONFIG_BACKLIGHT_LM3630A=m CONFIG_BACKLIGHT_LM3639=y CONFIG_BACKLIGHT_LP855X=y CONFIG_BACKLIGHT_PANDORA=m CONFIG_BACKLIGHT_SKY81452=y CONFIG_BACKLIGHT_GPIO=m CONFIG_BACKLIGHT_LV5207LP=y # CONFIG_BACKLIGHT_BD6107 is not set CONFIG_BACKLIGHT_ARCXCNN=y # end of Backlight & LCD device support CONFIG_VGASTATE=y # # Console display driver support # CONFIG_DUMMY_CONSOLE=y CONFIG_DUMMY_CONSOLE_COLUMNS=80 CONFIG_DUMMY_CONSOLE_ROWS=25 # CONFIG_FRAMEBUFFER_CONSOLE is not set # end of Console display driver support # CONFIG_LOGO is not set # end of Graphics support # CONFIG_SOUND is not set # # HID support # # CONFIG_HID is not set # # I2C HID support # # end of I2C HID support # # Intel ISH HID support # # end of Intel ISH HID support # end of HID support CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y # CONFIG_MMC_BLOCK is not set # CONFIG_SDIO_UART is not set # CONFIG_MMC_TEST is not set # # MMC/SD/SDIO Host Controller Drivers # CONFIG_MMC_DEBUG=y # CONFIG_MMC_SDHCI is not set # CONFIG_MMC_MOXART is not set # CONFIG_MMC_OMAP_HS is not set CONFIG_MMC_ALCOR=y CONFIG_MMC_TIFM_SD=y # CONFIG_MMC_DAVINCI is not set # CONFIG_MMC_SPI is not set # CONFIG_MMC_S3C is not set CONFIG_MMC_SDRICOH_CS=m # CONFIG_MMC_TMIO is not set # CONFIG_MMC_SDHI is not set # CONFIG_MMC_CB710 is not set # CONFIG_MMC_VIA_SDMMC is not set # CONFIG_MMC_DW is not set # CONFIG_MMC_SH_MMCIF is not set CONFIG_MMC_USDHI6ROL0=m # CONFIG_MMC_REALTEK_PCI is not set CONFIG_MMC_CQHCI=y CONFIG_MMC_HSQ=m CONFIG_MMC_TOSHIBA_PCI=m # CONFIG_MMC_BCM2835 is not set # CONFIG_MMC_OWL is not set # CONFIG_MMC_LITEX is not set CONFIG_SCSI_UFSHCD=m # CONFIG_SCSI_UFS_BSG is not set # CONFIG_SCSI_UFS_HPB is not set # CONFIG_SCSI_UFS_FAULT_INJECTION is not set # CONFIG_SCSI_UFS_HWMON is not set CONFIG_SCSI_UFSHCD_PCI=m CONFIG_SCSI_UFS_DWC_TC_PCI=m CONFIG_SCSI_UFSHCD_PLATFORM=m # CONFIG_SCSI_UFS_CDNS_PLATFORM is not set # CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set # CONFIG_SCSI_UFS_HISI is not set # CONFIG_SCSI_UFS_RENESAS is not set # CONFIG_SCSI_UFS_EXYNOS is not set CONFIG_MEMSTICK=y # CONFIG_MEMSTICK_DEBUG is not set # # MemoryStick drivers # # CONFIG_MEMSTICK_UNSAFE_RESUME is not set CONFIG_MSPRO_BLOCK=m # CONFIG_MS_BLOCK is not set # # MemoryStick Host Controller Drivers # CONFIG_MEMSTICK_TIFM_MS=m # CONFIG_MEMSTICK_JMICRON_38X is not set # CONFIG_MEMSTICK_R592 is not set CONFIG_MEMSTICK_REALTEK_PCI=m CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y # CONFIG_LEDS_CLASS_FLASH is not set CONFIG_LEDS_CLASS_MULTICOLOR=m # CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set # # LED drivers # CONFIG_LEDS_88PM860X=y # CONFIG_LEDS_ARIEL is not set CONFIG_LEDS_LM3530=m CONFIG_LEDS_LM3532=m CONFIG_LEDS_LM3533=m # CONFIG_LEDS_LM3642 is not set # CONFIG_LEDS_MT6323 is not set # CONFIG_LEDS_S3C24XX is not set # CONFIG_LEDS_COBALT_QUBE is not set # CONFIG_LEDS_COBALT_RAQ is not set CONFIG_LEDS_PCA9532=m CONFIG_LEDS_PCA9532_GPIO=y # CONFIG_LEDS_GPIO is not set # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_LP3952 is not set CONFIG_LEDS_LP50XX=m # CONFIG_LEDS_PCA955X is not set CONFIG_LEDS_PCA963X=m CONFIG_LEDS_WM831X_STATUS=y # CONFIG_LEDS_WM8350 is not set CONFIG_LEDS_DA903X=y CONFIG_LEDS_DA9052=y # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_PWM is not set CONFIG_LEDS_BD2802=y # CONFIG_LEDS_LT3593 is not set CONFIG_LEDS_MC13783=m CONFIG_LEDS_NS2=y # CONFIG_LEDS_TCA6507 is not set CONFIG_LEDS_TLC591XX=y CONFIG_LEDS_LM355x=y # CONFIG_LEDS_OT200 is not set CONFIG_LEDS_IS31FL319X=m # # LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) # CONFIG_LEDS_BLINKM=m CONFIG_LEDS_MLXREG=m CONFIG_LEDS_USER=y CONFIG_LEDS_TI_LMU_COMMON=y CONFIG_LEDS_LM36274=y # CONFIG_LEDS_IP30 is not set # # Flash and Torch LED drivers # # # RGB LED drivers # CONFIG_LEDS_PWM_MULTICOLOR=m # # LED Triggers # # CONFIG_LEDS_TRIGGERS is not set # # Simple LED drivers # # CONFIG_ACCESSIBILITY is not set # CONFIG_DMADEVICES is not set # # DMABUF options # CONFIG_SYNC_FILE=y CONFIG_SW_SYNC=y # CONFIG_UDMABUF is not set CONFIG_DMABUF_MOVE_NOTIFY=y CONFIG_DMABUF_DEBUG=y # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_SYSFS_STATS=y # CONFIG_DMABUF_HEAPS_SYSTEM is not set # end of DMABUF options CONFIG_AUXDISPLAY=y CONFIG_CHARLCD=m CONFIG_LINEDISP=m CONFIG_HD44780_COMMON=m # CONFIG_HD44780 is not set CONFIG_IMG_ASCII_LCD=m # CONFIG_HT16K33 is not set # CONFIG_LCD2S is not set CONFIG_PARPORT_PANEL=m CONFIG_PANEL_PARPORT=0 CONFIG_PANEL_PROFILE=5 CONFIG_PANEL_CHANGE_MESSAGE=y CONFIG_PANEL_BOOT_MESSAGE="" # CONFIG_CHARLCD_BL_OFF is not set CONFIG_CHARLCD_BL_ON=y # CONFIG_CHARLCD_BL_FLASH is not set # CONFIG_PANEL is not set CONFIG_UIO=y # CONFIG_UIO_CIF is not set CONFIG_UIO_PDRV_GENIRQ=y CONFIG_UIO_DMEM_GENIRQ=m # CONFIG_UIO_AEC is not set CONFIG_UIO_SERCOS3=m # CONFIG_UIO_PCI_GENERIC is not set CONFIG_UIO_NETX=m CONFIG_UIO_PRUSS=m CONFIG_UIO_MF624=m # CONFIG_UIO_DFL is not set CONFIG_VFIO=y CONFIG_VFIO_IOMMU_TYPE1=y CONFIG_VFIO_VIRQFD=y CONFIG_VFIO_NOIOMMU=y CONFIG_VFIO_PCI_CORE=y CONFIG_VFIO_PCI=y # CONFIG_VFIO_PLATFORM is not set # CONFIG_VFIO_MDEV is not set CONFIG_IRQ_BYPASS_MANAGER=y # CONFIG_VIRT_DRIVERS is not set CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO=y CONFIG_VIRTIO_PCI_LIB=m CONFIG_VIRTIO_MENU=y CONFIG_VIRTIO_PCI=m # CONFIG_VIRTIO_PCI_LEGACY is not set CONFIG_VIRTIO_PMEM=m # CONFIG_VIRTIO_BALLOON is not set CONFIG_VIRTIO_INPUT=y # CONFIG_VIRTIO_MMIO is not set CONFIG_VHOST_MENU=y CONFIG_VHOST_CROSS_ENDIAN_LEGACY=y # # Microsoft Hyper-V guest support # # end of Microsoft Hyper-V guest support CONFIG_GREYBUS=m # CONFIG_COMEDI is not set # CONFIG_STAGING is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set # CONFIG_OLPC_XO175 is not set CONFIG_SURFACE_PLATFORMS=y # CONFIG_COMMON_CLK is not set # CONFIG_HWSPINLOCK is not set # # Clock Source drivers # # CONFIG_BCM2835_TIMER is not set # CONFIG_BCM_KONA_TIMER is not set # CONFIG_DAVINCI_TIMER is not set # CONFIG_DIGICOLOR_TIMER is not set # CONFIG_OMAP_DM_TIMER is not set # CONFIG_DW_APB_TIMER is not set # CONFIG_FTTMR010_TIMER is not set # CONFIG_IXP4XX_TIMER is not set # CONFIG_MESON6_TIMER is not set # CONFIG_OWL_TIMER is not set # CONFIG_RDA_TIMER is not set # CONFIG_SUN4I_TIMER is not set # CONFIG_TEGRA_TIMER is not set # CONFIG_VT8500_TIMER is not set # CONFIG_NPCM7XX_TIMER is not set # CONFIG_ASM9260_TIMER is not set # CONFIG_CLKSRC_DBX500_PRCMU is not set # CONFIG_CLPS711X_TIMER is not set # CONFIG_MXS_TIMER is not set # CONFIG_NSPIRE_TIMER is not set # CONFIG_INTEGRATOR_AP_TIMER is not set # CONFIG_CLKSRC_PISTACHIO is not set # CONFIG_CLKSRC_STM32_LP is not set # CONFIG_ARMV7M_SYSTICK is not set # CONFIG_ATMEL_PIT is not set # CONFIG_ATMEL_ST is not set # CONFIG_CLKSRC_SAMSUNG_PWM is not set # CONFIG_FSL_FTM_TIMER is not set # CONFIG_OXNAS_RPS_TIMER is not set # CONFIG_MTK_TIMER is not set # CONFIG_SPRD_TIMER is not set # CONFIG_SH_TIMER_CMT is not set # CONFIG_SH_TIMER_MTU2 is not set # CONFIG_RENESAS_OSTM is not set # CONFIG_SH_TIMER_TMU is not set # CONFIG_EM_TIMER_STI is not set # CONFIG_CLKSRC_PXA is not set # CONFIG_TIMER_IMX_SYS_CTR is not set # CONFIG_CLKSRC_ST_LPC is not set # CONFIG_GXP_TIMER is not set # CONFIG_MSC313E_TIMER is not set # CONFIG_MICROCHIP_PIT64B is not set # end of Clock Source drivers # CONFIG_MAILBOX is not set CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y # # Generic IOMMU Pagetable Support # # CONFIG_IOMMU_IO_PGTABLE_LPAE is not set # CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set # CONFIG_IOMMU_IO_PGTABLE_DART is not set # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set CONFIG_IOMMU_DEFAULT_DMA_STRICT=y # CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set # CONFIG_OMAP_IOMMU is not set # CONFIG_ROCKCHIP_IOMMU is not set # CONFIG_SUN50I_IOMMU is not set # CONFIG_IPMMU_VMSA is not set # CONFIG_APPLE_DART is not set # CONFIG_ARM_SMMU is not set CONFIG_S390_IOMMU=y # CONFIG_S390_CCW_IOMMU is not set # CONFIG_S390_AP_IOMMU is not set # CONFIG_MTK_IOMMU is not set # CONFIG_QCOM_IOMMU is not set # CONFIG_SPRD_IOMMU is not set # # Remoteproc drivers # # CONFIG_REMOTEPROC is not set # end of Remoteproc drivers # # Rpmsg drivers # CONFIG_RPMSG=m CONFIG_RPMSG_CTRL=m CONFIG_RPMSG_NS=m CONFIG_RPMSG_VIRTIO=m # end of Rpmsg drivers # # SOC (System On Chip) specific Drivers # # # Amlogic SoC drivers # # CONFIG_MESON_CANVAS is not set # CONFIG_MESON_CLK_MEASURE is not set # CONFIG_MESON_GX_SOCINFO is not set # CONFIG_MESON_MX_SOCINFO is not set # end of Amlogic SoC drivers # # Apple SoC drivers # # CONFIG_APPLE_SART is not set # end of Apple SoC drivers # # ASPEED SoC drivers # # CONFIG_ASPEED_LPC_CTRL is not set # CONFIG_ASPEED_LPC_SNOOP is not set # CONFIG_ASPEED_UART_ROUTING is not set # CONFIG_ASPEED_P2A_CTRL is not set # CONFIG_ASPEED_SOCINFO is not set # end of ASPEED SoC drivers # CONFIG_AT91_SOC_ID is not set # CONFIG_AT91_SOC_SFR is not set # # Broadcom SoC drivers # # CONFIG_SOC_BCM63XX is not set # CONFIG_SOC_BRCMSTB is not set # end of Broadcom SoC drivers # # NXP/Freescale QorIQ SoC drivers # # end of NXP/Freescale QorIQ SoC drivers # # fujitsu SoC drivers # # end of fujitsu SoC drivers # # i.MX SoC drivers # # CONFIG_SOC_IMX8M is not set # CONFIG_SOC_IMX9 is not set # end of i.MX SoC drivers # # IXP4xx SoC drivers # # CONFIG_IXP4XX_QMGR is not set # CONFIG_IXP4XX_NPE is not set # end of IXP4xx SoC drivers # # Enable LiteX SoC Builder specific drivers # # CONFIG_LITEX_SOC_CONTROLLER is not set # end of Enable LiteX SoC Builder specific drivers # # MediaTek SoC drivers # # CONFIG_MTK_CMDQ is not set # CONFIG_MTK_DEVAPC is not set # CONFIG_MTK_INFRACFG is not set # CONFIG_MTK_MMSYS is not set # end of MediaTek SoC drivers # # Qualcomm SoC drivers # # CONFIG_QCOM_GENI_SE is not set # CONFIG_QCOM_GSBI is not set # CONFIG_QCOM_LLCC is not set # CONFIG_QCOM_RPMH is not set # CONFIG_QCOM_SMD_RPM is not set # CONFIG_QCOM_SPM is not set # CONFIG_QCOM_WCNSS_CTRL is not set # CONFIG_QCOM_ICC_BWMON is not set # end of Qualcomm SoC drivers # CONFIG_SOC_RENESAS is not set # CONFIG_ROCKCHIP_GRF is not set # CONFIG_SOC_SAMSUNG is not set # CONFIG_SOC_TI is not set # CONFIG_UX500_SOC_ID is not set # # Xilinx SoC drivers # # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers CONFIG_PM_DEVFREQ=y # # DEVFREQ Governors # CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=m CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_DEVFREQ_GOV_PASSIVE=y # # DEVFREQ Drivers # # CONFIG_ARM_EXYNOS_BUS_DEVFREQ is not set # CONFIG_ARM_IMX_BUS_DEVFREQ is not set # CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set CONFIG_PM_DEVFREQ_EVENT=y # CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP is not set # CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU is not set # CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI is not set # CONFIG_EXTCON is not set CONFIG_MEMORY=y # CONFIG_BRCMSTB_DPFE is not set # CONFIG_BRCMSTB_MEMC is not set # CONFIG_BT1_L2_CTL is not set # CONFIG_TI_EMIF is not set CONFIG_FPGA_DFL_EMIF=m # CONFIG_FSL_CORENET_CF is not set # CONFIG_FSL_IFC is not set # CONFIG_MTK_SMI is not set # CONFIG_DA8XX_DDRCTL is not set # CONFIG_RENESAS_RPCIF is not set # CONFIG_STM32_FMC2_EBI is not set # CONFIG_SAMSUNG_MC is not set CONFIG_IIO=y CONFIG_IIO_BUFFER=y CONFIG_IIO_BUFFER_CB=y CONFIG_IIO_BUFFER_DMA=m CONFIG_IIO_BUFFER_DMAENGINE=m CONFIG_IIO_BUFFER_HW_CONSUMER=y CONFIG_IIO_KFIFO_BUF=y CONFIG_IIO_TRIGGERED_BUFFER=y CONFIG_IIO_CONFIGFS=m CONFIG_IIO_TRIGGER=y CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 CONFIG_IIO_SW_DEVICE=m # CONFIG_IIO_SW_TRIGGER is not set # CONFIG_IIO_TRIGGERED_EVENT is not set # # Accelerometers # # CONFIG_ADIS16201 is not set CONFIG_ADIS16209=m CONFIG_ADXL313=m CONFIG_ADXL313_I2C=m # CONFIG_ADXL313_SPI is not set # CONFIG_ADXL345_I2C is not set # CONFIG_ADXL345_SPI is not set CONFIG_ADXL355=y CONFIG_ADXL355_I2C=m CONFIG_ADXL355_SPI=y # CONFIG_ADXL367_SPI is not set # CONFIG_ADXL367_I2C is not set CONFIG_ADXL372=y CONFIG_ADXL372_SPI=m CONFIG_ADXL372_I2C=y CONFIG_BMA180=m # CONFIG_BMA220 is not set # CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set CONFIG_BMI088_ACCEL=y CONFIG_BMI088_ACCEL_SPI=y # CONFIG_DA280 is not set CONFIG_DA311=m CONFIG_DMARD06=m CONFIG_DMARD09=y # CONFIG_DMARD10 is not set CONFIG_FXLS8962AF=y CONFIG_FXLS8962AF_I2C=m CONFIG_FXLS8962AF_SPI=y CONFIG_KXSD9=y CONFIG_KXSD9_SPI=m # CONFIG_KXSD9_I2C is not set # CONFIG_KXCJK1013 is not set CONFIG_MC3230=y # CONFIG_MMA7455_I2C is not set # CONFIG_MMA7455_SPI is not set CONFIG_MMA7660=m CONFIG_MMA8452=y CONFIG_MMA9551_CORE=m CONFIG_MMA9551=m # CONFIG_MMA9553 is not set CONFIG_MSA311=m CONFIG_MXC4005=m # CONFIG_MXC6255 is not set # CONFIG_SCA3000 is not set # CONFIG_SCA3300 is not set CONFIG_STK8312=y CONFIG_STK8BA50=m # end of Accelerometers # # Analog to digital converters # CONFIG_AD_SIGMA_DELTA=y CONFIG_AD7091R5=m CONFIG_AD7124=m CONFIG_AD7192=y CONFIG_AD7266=y CONFIG_AD7280=m CONFIG_AD7291=y # CONFIG_AD7292 is not set CONFIG_AD7298=y # CONFIG_AD7476 is not set CONFIG_AD7606=m CONFIG_AD7606_IFACE_PARALLEL=m # CONFIG_AD7606_IFACE_SPI is not set CONFIG_AD7766=m CONFIG_AD7768_1=m CONFIG_AD7780=m CONFIG_AD7791=y CONFIG_AD7793=y # CONFIG_AD7887 is not set # CONFIG_AD7923 is not set CONFIG_AD7949=y CONFIG_AD799X=y # CONFIG_AT91_SAMA5D2_ADC is not set # CONFIG_BCM_IPROC_ADC is not set # CONFIG_BERLIN2_ADC is not set CONFIG_DA9150_GPADC=m # CONFIG_ENVELOPE_DETECTOR is not set # CONFIG_HI8435 is not set # CONFIG_HX711 is not set # CONFIG_INGENIC_ADC is not set # CONFIG_IMX7D_ADC is not set # CONFIG_IMX8QXP_ADC is not set # CONFIG_LPC18XX_ADC is not set # CONFIG_LPC32XX_ADC is not set CONFIG_LTC2471=y CONFIG_LTC2485=y CONFIG_LTC2496=m CONFIG_LTC2497=m CONFIG_MAX1027=m CONFIG_MAX11100=m # CONFIG_MAX1118 is not set # CONFIG_MAX11205 is not set CONFIG_MAX1241=y # CONFIG_MAX1363 is not set CONFIG_MAX9611=m CONFIG_MCP320X=m CONFIG_MCP3422=m # CONFIG_MCP3911 is not set # CONFIG_MEDIATEK_MT6360_ADC is not set # CONFIG_MEDIATEK_MT6577_AUXADC is not set CONFIG_MEN_Z188_ADC=y CONFIG_NAU7802=m # CONFIG_NPCM_ADC is not set CONFIG_PALMAS_GPADC=y CONFIG_QCOM_VADC_COMMON=m # CONFIG_QCOM_SPMI_IADC is not set CONFIG_QCOM_SPMI_VADC=m # CONFIG_QCOM_SPMI_ADC5 is not set # CONFIG_RCAR_GYRO_ADC is not set CONFIG_RICHTEK_RTQ6056=m # CONFIG_RZG2L_ADC is not set # CONFIG_SC27XX_ADC is not set # CONFIG_SPEAR_ADC is not set CONFIG_SD_ADC_MODULATOR=m # CONFIG_STM32_DFSDM_CORE is not set # CONFIG_STM32_DFSDM_ADC is not set # CONFIG_TI_ADC081C is not set # CONFIG_TI_ADC0832 is not set CONFIG_TI_ADC084S021=y CONFIG_TI_ADC12138=y CONFIG_TI_ADC108S102=m # CONFIG_TI_ADC128S052 is not set CONFIG_TI_ADC161S626=m # CONFIG_TI_ADS1015 is not set CONFIG_TI_ADS7950=m CONFIG_TI_ADS8344=m # CONFIG_TI_ADS8688 is not set CONFIG_TI_ADS124S08=y CONFIG_TI_ADS131E08=m # CONFIG_TI_AM335X_ADC is not set CONFIG_TI_TLC4541=y CONFIG_TI_TSC2046=y CONFIG_TWL4030_MADC=m # CONFIG_TWL6030_GPADC is not set # CONFIG_VF610_ADC is not set CONFIG_XILINX_XADC=y # CONFIG_XILINX_AMS is not set # end of Analog to digital converters # # Analog to digital and digital to analog converters # CONFIG_AD74413R=y # end of Analog to digital and digital to analog converters # # Analog Front Ends # CONFIG_IIO_RESCALE=m # end of Analog Front Ends # # Amplifiers # CONFIG_AD8366=m CONFIG_ADA4250=m CONFIG_HMC425=y # end of Amplifiers # # Capacitance to digital converters # CONFIG_AD7150=m # CONFIG_AD7746 is not set # end of Capacitance to digital converters # # Chemical Sensors # CONFIG_ATLAS_PH_SENSOR=m # CONFIG_ATLAS_EZO_SENSOR is not set # CONFIG_BME680 is not set CONFIG_CCS811=y CONFIG_IAQCORE=y # CONFIG_SCD30_CORE is not set CONFIG_SCD4X=m CONFIG_SENSIRION_SGP30=m CONFIG_SENSIRION_SGP40=y CONFIG_SPS30=m CONFIG_SPS30_I2C=m CONFIG_SENSEAIR_SUNRISE_CO2=m CONFIG_VZ89X=m # end of Chemical Sensors # # Hid Sensor IIO Common # # end of Hid Sensor IIO Common CONFIG_IIO_MS_SENSORS_I2C=y # # IIO SCMI Sensors # # end of IIO SCMI Sensors # # SSP Sensor Common # CONFIG_IIO_SSP_SENSORS_COMMONS=m CONFIG_IIO_SSP_SENSORHUB=m # end of SSP Sensor Common CONFIG_IIO_ST_SENSORS_I2C=m CONFIG_IIO_ST_SENSORS_SPI=y CONFIG_IIO_ST_SENSORS_CORE=y # # Digital to analog converters # CONFIG_AD3552R=m # CONFIG_AD5064 is not set # CONFIG_AD5360 is not set CONFIG_AD5380=m CONFIG_AD5421=m # CONFIG_AD5446 is not set CONFIG_AD5449=y CONFIG_AD5592R_BASE=m # CONFIG_AD5592R is not set CONFIG_AD5593R=m CONFIG_AD5504=m CONFIG_AD5624R_SPI=m CONFIG_LTC2688=m CONFIG_AD5686=y # CONFIG_AD5686_SPI is not set CONFIG_AD5696_I2C=y # CONFIG_AD5755 is not set # CONFIG_AD5758 is not set CONFIG_AD5761=m CONFIG_AD5764=m CONFIG_AD5766=y CONFIG_AD5770R=m # CONFIG_AD5791 is not set CONFIG_AD7293=y CONFIG_AD7303=m CONFIG_AD8801=y # CONFIG_DPOT_DAC is not set CONFIG_DS4424=y # CONFIG_LPC18XX_DAC is not set # CONFIG_LTC1660 is not set CONFIG_LTC2632=m # CONFIG_M62332 is not set CONFIG_MAX517=m # CONFIG_MAX5821 is not set CONFIG_MCP4725=m # CONFIG_MCP4922 is not set CONFIG_TI_DAC082S085=y CONFIG_TI_DAC5571=y CONFIG_TI_DAC7311=y CONFIG_TI_DAC7612=y CONFIG_VF610_DAC=y # end of Digital to analog converters # # IIO dummy driver # CONFIG_IIO_SIMPLE_DUMMY=m # CONFIG_IIO_SIMPLE_DUMMY_EVENTS is not set CONFIG_IIO_SIMPLE_DUMMY_BUFFER=y # end of IIO dummy driver # # Filters # # end of Filters # # Frequency Synthesizers DDS/PLL # # # Clock Generator/Distribution # # CONFIG_AD9523 is not set # end of Clock Generator/Distribution # # Phase-Locked Loop (PLL) frequency synthesizers # CONFIG_ADF4350=y # CONFIG_ADF4371 is not set # CONFIG_ADMV4420 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL # # Digital gyroscope sensors # # CONFIG_ADIS16080 is not set CONFIG_ADIS16130=m CONFIG_ADIS16136=y # CONFIG_ADIS16260 is not set CONFIG_ADXRS290=m # CONFIG_ADXRS450 is not set # CONFIG_BMG160 is not set CONFIG_FXAS21002C=y CONFIG_FXAS21002C_I2C=y CONFIG_FXAS21002C_SPI=y CONFIG_MPU3050=y CONFIG_MPU3050_I2C=y CONFIG_IIO_ST_GYRO_3AXIS=y # CONFIG_IIO_ST_GYRO_I2C_3AXIS is not set # CONFIG_IIO_ST_GYRO_SPI_3AXIS is not set CONFIG_ITG3200=m # end of Digital gyroscope sensors # # Health Sensors # # # Heart Rate Monitors # CONFIG_AFE4403=y CONFIG_AFE4404=y CONFIG_MAX30100=m CONFIG_MAX30102=y # end of Heart Rate Monitors # end of Health Sensors # # Humidity sensors # CONFIG_AM2315=m # CONFIG_DHT11 is not set # CONFIG_HDC100X is not set CONFIG_HDC2010=y # CONFIG_HTS221 is not set CONFIG_HTU21=y CONFIG_SI7005=m CONFIG_SI7020=y # end of Humidity sensors # # Inertial measurement units # # CONFIG_ADIS16400 is not set # CONFIG_ADIS16460 is not set CONFIG_ADIS16475=y CONFIG_ADIS16480=y CONFIG_BMI160=y CONFIG_BMI160_I2C=m CONFIG_BMI160_SPI=y CONFIG_BOSCH_BNO055=m CONFIG_BOSCH_BNO055_I2C=m CONFIG_FXOS8700=m # CONFIG_FXOS8700_I2C is not set CONFIG_FXOS8700_SPI=m # CONFIG_KMX61 is not set CONFIG_INV_ICM42600=y CONFIG_INV_ICM42600_I2C=y # CONFIG_INV_ICM42600_SPI is not set CONFIG_INV_MPU6050_IIO=m CONFIG_INV_MPU6050_I2C=m CONFIG_INV_MPU6050_SPI=m # CONFIG_IIO_ST_LSM6DSX is not set # end of Inertial measurement units CONFIG_IIO_ADIS_LIB=y CONFIG_IIO_ADIS_LIB_BUFFER=y # # Light sensors # # CONFIG_ADJD_S311 is not set CONFIG_ADUX1020=m CONFIG_AL3010=y CONFIG_AL3320A=m CONFIG_APDS9300=y CONFIG_APDS9960=y CONFIG_AS73211=m CONFIG_BH1750=m CONFIG_BH1780=y CONFIG_CM32181=y CONFIG_CM3232=y CONFIG_CM3323=y CONFIG_CM3605=y # CONFIG_CM36651 is not set CONFIG_GP2AP002=y # CONFIG_GP2AP020A00F is not set # CONFIG_IQS621_ALS is not set # CONFIG_SENSORS_ISL29018 is not set # CONFIG_SENSORS_ISL29028 is not set # CONFIG_ISL29125 is not set CONFIG_JSA1212=m CONFIG_RPR0521=y # CONFIG_SENSORS_LM3533 is not set CONFIG_LTR501=m CONFIG_LTRF216A=m # CONFIG_LV0104CS is not set CONFIG_MAX44000=m # CONFIG_MAX44009 is not set CONFIG_NOA1305=m CONFIG_OPT3001=m # CONFIG_PA12203001 is not set # CONFIG_SI1133 is not set # CONFIG_SI1145 is not set CONFIG_STK3310=y CONFIG_ST_UVIS25=y CONFIG_ST_UVIS25_I2C=y CONFIG_ST_UVIS25_SPI=y CONFIG_TCS3414=y # CONFIG_TCS3472 is not set # CONFIG_SENSORS_TSL2563 is not set CONFIG_TSL2583=m CONFIG_TSL2591=y # CONFIG_TSL2772 is not set CONFIG_TSL4531=y CONFIG_US5182D=m CONFIG_VCNL4000=m CONFIG_VCNL4035=m CONFIG_VEML6030=m CONFIG_VEML6070=m # CONFIG_VL6180 is not set CONFIG_ZOPT2201=y # end of Light sensors # # Magnetometer sensors # CONFIG_AK8974=m CONFIG_AK8975=y CONFIG_AK09911=m CONFIG_BMC150_MAGN=m CONFIG_BMC150_MAGN_I2C=m # CONFIG_BMC150_MAGN_SPI is not set CONFIG_MAG3110=m CONFIG_MMC35240=m CONFIG_IIO_ST_MAGN_3AXIS=m CONFIG_IIO_ST_MAGN_I2C_3AXIS=m CONFIG_IIO_ST_MAGN_SPI_3AXIS=m # CONFIG_SENSORS_HMC5843_I2C is not set # CONFIG_SENSORS_HMC5843_SPI is not set CONFIG_SENSORS_RM3100=m CONFIG_SENSORS_RM3100_I2C=m # CONFIG_SENSORS_RM3100_SPI is not set # CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors # # Multiplexers # # CONFIG_IIO_MUX is not set # end of Multiplexers # # Inclinometer sensors # # end of Inclinometer sensors CONFIG_IIO_RESCALE_KUNIT_TEST=m CONFIG_IIO_FORMAT_KUNIT_TEST=m # # Triggers - standalone # CONFIG_IIO_INTERRUPT_TRIGGER=y # CONFIG_IIO_STM32_LPTIMER_TRIGGER is not set # CONFIG_IIO_STM32_TIMER_TRIGGER is not set # CONFIG_IIO_SYSFS_TRIGGER is not set # end of Triggers - standalone # # Linear and angular position sensors # # CONFIG_IQS624_POS is not set # end of Linear and angular position sensors # # Digital potentiometers # CONFIG_AD5110=y CONFIG_AD5272=y CONFIG_DS1803=m CONFIG_MAX5432=y # CONFIG_MAX5481 is not set CONFIG_MAX5487=y CONFIG_MCP4018=y CONFIG_MCP4131=y CONFIG_MCP4531=m CONFIG_MCP41010=y CONFIG_TPL0102=y # end of Digital potentiometers # # Digital potentiostats # CONFIG_LMP91000=y # end of Digital potentiostats # # Pressure sensors # # CONFIG_ABP060MG is not set CONFIG_BMP280=y CONFIG_BMP280_I2C=y CONFIG_BMP280_SPI=y CONFIG_DLHL60D=m CONFIG_DPS310=m # CONFIG_HP03 is not set # CONFIG_ICP10100 is not set CONFIG_MPL115=y CONFIG_MPL115_I2C=y CONFIG_MPL115_SPI=m CONFIG_MPL3115=m CONFIG_MS5611=y CONFIG_MS5611_I2C=m CONFIG_MS5611_SPI=y CONFIG_MS5637=m CONFIG_IIO_ST_PRESS=y CONFIG_IIO_ST_PRESS_I2C=m CONFIG_IIO_ST_PRESS_SPI=y # CONFIG_T5403 is not set CONFIG_HP206C=m CONFIG_ZPA2326=y CONFIG_ZPA2326_I2C=y CONFIG_ZPA2326_SPI=y # end of Pressure sensors # # Lightning sensors # CONFIG_AS3935=y # end of Lightning sensors # # Proximity and distance sensors # CONFIG_ISL29501=y # CONFIG_LIDAR_LITE_V2 is not set CONFIG_MB1232=m # CONFIG_PING is not set CONFIG_RFD77402=y CONFIG_SRF04=y CONFIG_SX_COMMON=m CONFIG_SX9310=m CONFIG_SX9324=m CONFIG_SX9360=m CONFIG_SX9500=y CONFIG_SRF08=y CONFIG_VCNL3020=m CONFIG_VL53L0X_I2C=m # end of Proximity and distance sensors # # Resolver to digital converters # CONFIG_AD2S90=y # CONFIG_AD2S1200 is not set # end of Resolver to digital converters # # Temperature sensors # # CONFIG_IQS620AT_TEMP is not set CONFIG_LTC2983=m # CONFIG_MAXIM_THERMOCOUPLE is not set CONFIG_MLX90614=m CONFIG_MLX90632=y CONFIG_TMP006=m # CONFIG_TMP007 is not set CONFIG_TMP117=m # CONFIG_TSYS01 is not set CONFIG_TSYS02D=m CONFIG_MAX31856=m CONFIG_MAX31865=m # end of Temperature sensors # CONFIG_NTB is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_BCM2835 is not set # CONFIG_PWM_BERLIN is not set # CONFIG_PWM_BRCMSTB is not set # CONFIG_PWM_CLK is not set # CONFIG_PWM_CLPS711X is not set CONFIG_PWM_DWC=m # CONFIG_PWM_EP93XX is not set # CONFIG_PWM_HIBVT is not set # CONFIG_PWM_IMX1 is not set # CONFIG_PWM_IMX27 is not set # CONFIG_PWM_INTEL_LGM is not set # CONFIG_PWM_IQS620A is not set CONFIG_PWM_LP3943=m # CONFIG_PWM_LPC18XX_SCT is not set # CONFIG_PWM_LPC32XX is not set # CONFIG_PWM_LPSS_PCI is not set # CONFIG_PWM_LPSS_PLATFORM is not set # CONFIG_PWM_MTK_DISP is not set # CONFIG_PWM_MEDIATEK is not set CONFIG_PWM_PCA9685=y # CONFIG_PWM_PXA is not set # CONFIG_PWM_RASPBERRYPI_POE is not set # CONFIG_PWM_RCAR is not set # CONFIG_PWM_RENESAS_TPU is not set # CONFIG_PWM_ROCKCHIP is not set # CONFIG_PWM_SAMSUNG is not set # CONFIG_PWM_SL28CPLD is not set # CONFIG_PWM_SPRD is not set # CONFIG_PWM_STM32 is not set # CONFIG_PWM_STM32_LP is not set # CONFIG_PWM_TEGRA is not set # CONFIG_PWM_TIECAP is not set # CONFIG_PWM_TIEHRPWM is not set CONFIG_PWM_TWL=m CONFIG_PWM_TWL_LED=y # CONFIG_PWM_VISCONTI is not set # CONFIG_PWM_VT8500 is not set # # IRQ chip support # # CONFIG_AL_FIC is not set CONFIG_MADERA_IRQ=m # CONFIG_RENESAS_INTC_IRQPIN is not set # CONFIG_RENESAS_IRQC is not set # CONFIG_RENESAS_RZA1_IRQC is not set # CONFIG_RENESAS_RZG2L_IRQC is not set # CONFIG_SL28CPLD_INTC is not set # CONFIG_TS4800_IRQ is not set # CONFIG_INGENIC_TCU_IRQ is not set # CONFIG_IRQ_UNIPHIER_AIDET is not set # CONFIG_MESON_IRQ_GPIO is not set # CONFIG_IMX_IRQSTEER is not set # CONFIG_IMX_INTMUX is not set # CONFIG_EXYNOS_IRQ_COMBINER is not set # CONFIG_MST_IRQ is not set # CONFIG_MCHP_EIC is not set # CONFIG_SUNPLUS_SP7021_INTC is not set # end of IRQ chip support # CONFIG_IPACK_BUS is not set # CONFIG_RESET_CONTROLLER is not set # # PHY Subsystem # CONFIG_GENERIC_PHY=y # CONFIG_PHY_PISTACHIO_USB is not set CONFIG_PHY_CAN_TRANSCEIVER=y # # PHY drivers for Broadcom platforms # # CONFIG_PHY_BCM63XX_USBH is not set # CONFIG_BCM_KONA_USB2_PHY is not set # end of PHY drivers for Broadcom platforms # CONFIG_PHY_HI6220_USB is not set # CONFIG_PHY_HI3660_USB is not set # CONFIG_PHY_HI3670_USB is not set # CONFIG_PHY_HI3670_PCIE is not set # CONFIG_PHY_HISTB_COMBPHY is not set # CONFIG_PHY_HISI_INNO_USB2 is not set CONFIG_PHY_PXA_28NM_HSIC=y # CONFIG_PHY_PXA_28NM_USB2 is not set # CONFIG_PHY_PXA_USB is not set # CONFIG_PHY_MMP3_USB is not set # CONFIG_PHY_MMP3_HSIC is not set # CONFIG_PHY_MT7621_PCI is not set # CONFIG_PHY_RALINK_USB is not set # CONFIG_PHY_RCAR_GEN3_USB3 is not set # CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set # CONFIG_PHY_ROCKCHIP_PCIE is not set # CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 is not set # CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set # CONFIG_PHY_SAMSUNG_USB2 is not set # CONFIG_PHY_ST_SPEAR1310_MIPHY is not set # CONFIG_PHY_ST_SPEAR1340_MIPHY is not set # CONFIG_PHY_TEGRA194_P2U is not set # CONFIG_PHY_DA8XX_USB is not set # CONFIG_OMAP_CONTROL_PHY is not set # CONFIG_TI_PIPE3 is not set # CONFIG_PHY_INTEL_KEEMBAY_EMMC is not set # CONFIG_PHY_INTEL_KEEMBAY_USB is not set # CONFIG_PHY_INTEL_LGM_EMMC is not set # CONFIG_PHY_XILINX_ZYNQMP is not set # end of PHY Subsystem CONFIG_POWERCAP=y CONFIG_MCB=y # CONFIG_MCB_PCI is not set CONFIG_MCB_LPC=y # # Performance monitor support # # CONFIG_ARM_CCN is not set # CONFIG_ARM_CMN is not set # CONFIG_ARM_SMMU_V3_PMU is not set # CONFIG_FSL_IMX8_DDR_PMU is not set # CONFIG_XGENE_PMU is not set # CONFIG_ARM_DMC620_PMU is not set # CONFIG_MARVELL_CN10K_TAD_PMU is not set # CONFIG_ALIBABA_UNCORE_DRW_PMU is not set # CONFIG_HNS3_PMU is not set # CONFIG_MARVELL_CN10K_DDR_PMU is not set # end of Performance monitor support # CONFIG_RAS is not set # CONFIG_USB4 is not set # # Android # # CONFIG_ANDROID_BINDER_IPC is not set # end of Android CONFIG_LIBNVDIMM=m # CONFIG_BLK_DEV_PMEM is not set # CONFIG_BTT is not set CONFIG_DAX=y CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y # CONFIG_NVMEM_APPLE_EFUSES is not set # CONFIG_NVMEM_BCM_OCOTP is not set # CONFIG_NVMEM_BRCM_NVRAM is not set # CONFIG_NVMEM_IMX_IIM is not set # CONFIG_NVMEM_IMX_OCOTP is not set # CONFIG_NVMEM_LAN9662_OTPC is not set # CONFIG_NVMEM_LAYERSCAPE_SFP is not set # CONFIG_NVMEM_LPC18XX_EEPROM is not set # CONFIG_NVMEM_LPC18XX_OTP is not set # CONFIG_NVMEM_MESON_MX_EFUSE is not set # CONFIG_NVMEM_MICROCHIP_OTPC is not set # CONFIG_NVMEM_MTK_EFUSE is not set # CONFIG_NVMEM_MXS_OCOTP is not set # CONFIG_NVMEM_NINTENDO_OTP is not set # CONFIG_NVMEM_QCOM_QFPROM is not set CONFIG_NVMEM_RMEM=y # CONFIG_NVMEM_ROCKCHIP_EFUSE is not set # CONFIG_NVMEM_ROCKCHIP_OTP is not set # CONFIG_NVMEM_SC27XX_EFUSE is not set # CONFIG_NVMEM_SNVS_LPGPR is not set # CONFIG_NVMEM_SPMI_SDAM is not set # CONFIG_NVMEM_SPRD_EFUSE is not set # CONFIG_NVMEM_STM32_ROMEM is not set # CONFIG_NVMEM_SUNPLUS_OCOTP is not set # CONFIG_NVMEM_UNIPHIER_EFUSE is not set # CONFIG_NVMEM_VF610_OCOTP is not set # # HW tracing support # # CONFIG_STM is not set CONFIG_INTEL_TH=y CONFIG_INTEL_TH_PCI=m CONFIG_INTEL_TH_GTH=y # CONFIG_INTEL_TH_MSU is not set CONFIG_INTEL_TH_PTI=y # CONFIG_INTEL_TH_DEBUG is not set # CONFIG_HISI_PTT is not set # end of HW tracing support CONFIG_FPGA=y # CONFIG_FPGA_MGR_SOCFPGA is not set # CONFIG_FPGA_MGR_SOCFPGA_A10 is not set CONFIG_ALTERA_PR_IP_CORE=m CONFIG_FPGA_MGR_ALTERA_PS_SPI=m CONFIG_FPGA_MGR_ALTERA_CVP=y # CONFIG_FPGA_MGR_ZYNQ_FPGA is not set CONFIG_FPGA_MGR_XILINX_SPI=y CONFIG_FPGA_MGR_MACHXO2_SPI=y CONFIG_FPGA_BRIDGE=y CONFIG_ALTERA_FREEZE_BRIDGE=y CONFIG_XILINX_PR_DECOUPLER=m CONFIG_FPGA_REGION=m CONFIG_FPGA_DFL=m # CONFIG_FPGA_DFL_FME is not set # CONFIG_FPGA_DFL_AFU is not set CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m # CONFIG_FPGA_DFL_PCI is not set # CONFIG_FPGA_MGR_ZYNQMP_FPGA is not set # CONFIG_FPGA_MGR_VERSAL_FPGA is not set # CONFIG_FPGA_MGR_MICROCHIP_SPI is not set # CONFIG_TEE is not set CONFIG_MULTIPLEXER=y # # Multiplexer drivers # CONFIG_MUX_ADG792A=y # CONFIG_MUX_ADGS1408 is not set CONFIG_MUX_GPIO=y # CONFIG_MUX_MMIO is not set # end of Multiplexer drivers CONFIG_PM_OPP=y # CONFIG_SIOX is not set CONFIG_SLIMBUS=y CONFIG_SLIM_QCOM_CTRL=y # CONFIG_INTERCONNECT is not set # CONFIG_COUNTER is not set # CONFIG_MOST is not set # CONFIG_PECI is not set CONFIG_HTE=y # end of Device Drivers # # File systems # CONFIG_VALIDATE_FS_PARSER=y CONFIG_FS_IOMAP=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y # CONFIG_EXT2_FS_POSIX_ACL is not set # CONFIG_EXT2_FS_SECURITY is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_POSIX_ACL is not set CONFIG_EXT3_FS_SECURITY=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y # CONFIG_EXT4_DEBUG is not set CONFIG_EXT4_KUNIT_TESTS=y CONFIG_JBD2=y CONFIG_JBD2_DEBUG=y CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=m CONFIG_REISERFS_CHECK=y # CONFIG_REISERFS_FS_XATTR is not set CONFIG_JFS_FS=y # CONFIG_JFS_POSIX_ACL is not set CONFIG_JFS_SECURITY=y # CONFIG_JFS_DEBUG is not set CONFIG_JFS_STATISTICS=y CONFIG_XFS_FS=m CONFIG_XFS_SUPPORT_V4=y # CONFIG_XFS_QUOTA is not set CONFIG_XFS_POSIX_ACL=y # CONFIG_XFS_RT is not set CONFIG_XFS_ONLINE_SCRUB=y # CONFIG_XFS_ONLINE_REPAIR is not set CONFIG_XFS_DEBUG=y CONFIG_XFS_ASSERT_FATAL=y # CONFIG_GFS2_FS is not set CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y # CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set # CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set # CONFIG_BTRFS_DEBUG is not set CONFIG_BTRFS_ASSERT=y CONFIG_BTRFS_FS_REF_VERIFY=y CONFIG_NILFS2_FS=y CONFIG_F2FS_FS=m # CONFIG_F2FS_STAT_FS is not set CONFIG_F2FS_FS_XATTR=y # CONFIG_F2FS_FS_POSIX_ACL is not set # CONFIG_F2FS_FS_SECURITY is not set CONFIG_F2FS_CHECK_FS=y CONFIG_F2FS_FAULT_INJECTION=y CONFIG_F2FS_FS_COMPRESSION=y CONFIG_F2FS_FS_LZO=y CONFIG_F2FS_FS_LZORLE=y CONFIG_F2FS_FS_LZ4=y CONFIG_F2FS_FS_LZ4HC=y CONFIG_F2FS_FS_ZSTD=y CONFIG_F2FS_IOSTAT=y CONFIG_F2FS_UNFAIR_RWSEM=y # CONFIG_ZONEFS_FS is not set CONFIG_FS_DAX=y CONFIG_FS_DAX_LIMITED=y CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y CONFIG_EXPORTFS_BLOCK_OPS=y # CONFIG_FILE_LOCKING is not set # CONFIG_FS_ENCRYPTION is not set CONFIG_FS_VERITY=y CONFIG_FS_VERITY_DEBUG=y # CONFIG_FS_VERITY_BUILTIN_SIGNATURES is not set # CONFIG_DNOTIFY is not set # CONFIG_INOTIFY_USER is not set # CONFIG_FANOTIFY is not set # CONFIG_QUOTA is not set CONFIG_AUTOFS4_FS=y CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=y CONFIG_CUSE=y # CONFIG_VIRTIO_FS is not set # CONFIG_OVERLAY_FS is not set # # Caches # CONFIG_NETFS_SUPPORT=m CONFIG_FSCACHE=m # CONFIG_FSCACHE_DEBUG is not set CONFIG_CACHEFILES=m CONFIG_CACHEFILES_DEBUG=y # CONFIG_CACHEFILES_ONDEMAND is not set # end of Caches # # CD-ROM/DVD Filesystems # CONFIG_ISO9660_FS=y # CONFIG_JOLIET is not set CONFIG_ZISOFS=y CONFIG_UDF_FS=m # end of CD-ROM/DVD Filesystems # # DOS/FAT/EXFAT/NT Filesystems # CONFIG_FAT_FS=m CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_FAT_DEFAULT_UTF8=y # CONFIG_FAT_KUNIT_TEST is not set # CONFIG_EXFAT_FS is not set # CONFIG_NTFS_FS is not set CONFIG_NTFS3_FS=m # CONFIG_NTFS3_64BIT_CLUSTER is not set # CONFIG_NTFS3_LZX_XPRESS is not set # CONFIG_NTFS3_FS_POSIX_ACL is not set # end of DOS/FAT/EXFAT/NT Filesystems # # Pseudo filesystems # # CONFIG_PROC_FS is not set CONFIG_KERNFS=y CONFIG_SYSFS=y # CONFIG_TMPFS is not set CONFIG_ARCH_SUPPORTS_HUGETLBFS=y CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y CONFIG_MEMFD_CREATE=y CONFIG_ARCH_HAS_GIGANTIC_PAGE=y CONFIG_CONFIGFS_FS=y # end of Pseudo filesystems # CONFIG_MISC_FILESYSTEMS is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_CODEPAGE_737=y CONFIG_NLS_CODEPAGE_775=m # CONFIG_NLS_CODEPAGE_850 is not set CONFIG_NLS_CODEPAGE_852=m CONFIG_NLS_CODEPAGE_855=m # CONFIG_NLS_CODEPAGE_857 is not set CONFIG_NLS_CODEPAGE_860=m CONFIG_NLS_CODEPAGE_861=y CONFIG_NLS_CODEPAGE_862=y CONFIG_NLS_CODEPAGE_863=m CONFIG_NLS_CODEPAGE_864=y # CONFIG_NLS_CODEPAGE_865 is not set # CONFIG_NLS_CODEPAGE_866 is not set CONFIG_NLS_CODEPAGE_869=y CONFIG_NLS_CODEPAGE_936=y # CONFIG_NLS_CODEPAGE_950 is not set # CONFIG_NLS_CODEPAGE_932 is not set CONFIG_NLS_CODEPAGE_949=m CONFIG_NLS_CODEPAGE_874=y CONFIG_NLS_ISO8859_8=y # CONFIG_NLS_CODEPAGE_1250 is not set CONFIG_NLS_CODEPAGE_1251=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_2=y # CONFIG_NLS_ISO8859_3 is not set CONFIG_NLS_ISO8859_4=m CONFIG_NLS_ISO8859_5=m # CONFIG_NLS_ISO8859_6 is not set CONFIG_NLS_ISO8859_7=m CONFIG_NLS_ISO8859_9=m CONFIG_NLS_ISO8859_13=y CONFIG_NLS_ISO8859_14=m # CONFIG_NLS_ISO8859_15 is not set CONFIG_NLS_KOI8_R=y CONFIG_NLS_KOI8_U=m CONFIG_NLS_MAC_ROMAN=m # CONFIG_NLS_MAC_CELTIC is not set # CONFIG_NLS_MAC_CENTEURO is not set # CONFIG_NLS_MAC_CROATIAN is not set CONFIG_NLS_MAC_CYRILLIC=m CONFIG_NLS_MAC_GAELIC=y # CONFIG_NLS_MAC_GREEK is not set CONFIG_NLS_MAC_ICELAND=y CONFIG_NLS_MAC_INUIT=y CONFIG_NLS_MAC_ROMANIAN=y # CONFIG_NLS_MAC_TURKISH is not set CONFIG_NLS_UTF8=y # CONFIG_UNICODE is not set CONFIG_IO_WQ=y # end of File systems # # Security options # CONFIG_KEYS=y CONFIG_KEYS_REQUEST_CACHE=y # CONFIG_PERSISTENT_KEYRINGS is not set CONFIG_TRUSTED_KEYS=y # # No trust source selected! # # CONFIG_ENCRYPTED_KEYS is not set CONFIG_KEY_DH_OPERATIONS=y CONFIG_SECURITY_DMESG_RESTRICT=y # CONFIG_SECURITYFS is not set # CONFIG_FORTIFY_SOURCE is not set CONFIG_STATIC_USERMODEHELPER=y CONFIG_STATIC_USERMODEHELPER_PATH="/sbin/usermode-helper" # CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf" # # Kernel hardening options # # # Memory initialization # CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y # CONFIG_INIT_STACK_NONE is not set # CONFIG_INIT_STACK_ALL_PATTERN is not set CONFIG_INIT_STACK_ALL_ZERO=y # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y CONFIG_ZERO_CALL_USED_REGS=y # end of Memory initialization CONFIG_RANDSTRUCT_NONE=y # end of Kernel hardening options # end of Security options CONFIG_XOR_BLOCKS=m CONFIG_CRYPTO=y # # Crypto core or helper # # CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_AKCIPHER2=y CONFIG_CRYPTO_AKCIPHER=y CONFIG_CRYPTO_KPP2=y CONFIG_CRYPTO_KPP=y CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_PCRYPT=y CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_AUTHENC=m CONFIG_CRYPTO_TEST=y # end of Crypto core or helper # # Public-key cryptography # CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_ECC=y CONFIG_CRYPTO_ECDH=m CONFIG_CRYPTO_ECDSA=y # CONFIG_CRYPTO_ECRDSA is not set # CONFIG_CRYPTO_SM2 is not set CONFIG_CRYPTO_CURVE25519=m # end of Public-key cryptography # # Block ciphers # CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_AES_TI=y CONFIG_CRYPTO_ARIA=m CONFIG_CRYPTO_BLOWFISH=y CONFIG_CRYPTO_BLOWFISH_COMMON=y CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST_COMMON=m # CONFIG_CRYPTO_CAST5 is not set CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_SM4=y CONFIG_CRYPTO_SM4_GENERIC=y # CONFIG_CRYPTO_TWOFISH is not set # end of Block ciphers # # Length-preserving ciphers and modes # CONFIG_CRYPTO_ADIANTUM=y CONFIG_CRYPTO_CHACHA20=y CONFIG_CRYPTO_CBC=m # CONFIG_CRYPTO_CFB is not set CONFIG_CRYPTO_CTR=y # CONFIG_CRYPTO_CTS is not set CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_HCTR2=m CONFIG_CRYPTO_KEYWRAP=m CONFIG_CRYPTO_LRW=y CONFIG_CRYPTO_OFB=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XCTR=m CONFIG_CRYPTO_XTS=y CONFIG_CRYPTO_NHPOLY1305=y # end of Length-preserving ciphers and modes # # AEAD (authenticated encryption with associated data) ciphers # CONFIG_CRYPTO_AEGIS128=y CONFIG_CRYPTO_CHACHA20POLY1305=m CONFIG_CRYPTO_CCM=y # CONFIG_CRYPTO_GCM is not set # CONFIG_CRYPTO_SEQIV is not set CONFIG_CRYPTO_ECHAINIV=y CONFIG_CRYPTO_ESSIV=m # end of AEAD (authenticated encryption with associated data) ciphers # # Hashes, digests, and MACs # CONFIG_CRYPTO_BLAKE2B=m # CONFIG_CRYPTO_CMAC is not set CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_MD4=m # CONFIG_CRYPTO_MD5 is not set CONFIG_CRYPTO_MICHAEL_MIC=y CONFIG_CRYPTO_POLYVAL=m CONFIG_CRYPTO_POLY1305=y CONFIG_CRYPTO_RMD160=y CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA3=m CONFIG_CRYPTO_SM3=m CONFIG_CRYPTO_SM3_GENERIC=m # CONFIG_CRYPTO_STREEBOG is not set CONFIG_CRYPTO_VMAC=y CONFIG_CRYPTO_WP512=m CONFIG_CRYPTO_XCBC=m CONFIG_CRYPTO_XXHASH=m # end of Hashes, digests, and MACs # # CRCs (cyclic redundancy checks) # CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRCT10DIF=m CONFIG_CRYPTO_CRC64_ROCKSOFT=m # end of CRCs (cyclic redundancy checks) # # Compression # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_842=m CONFIG_CRYPTO_LZ4=m # CONFIG_CRYPTO_LZ4HC is not set CONFIG_CRYPTO_ZSTD=y # end of Compression # # Random number generation # CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_DRBG_MENU=y CONFIG_CRYPTO_DRBG_HMAC=y CONFIG_CRYPTO_DRBG_HASH=y CONFIG_CRYPTO_DRBG_CTR=y CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_KDF800108_CTR=y # end of Random number generation # # Userspace interface # # end of Userspace interface CONFIG_CRYPTO_HASH_INFO=y # # Accelerated Cryptographic Algorithms for CPU (s390) # # CONFIG_CRYPTO_CRC32_S390 is not set # CONFIG_CRYPTO_SHA512_S390 is not set # CONFIG_CRYPTO_SHA1_S390 is not set # CONFIG_CRYPTO_SHA256_S390 is not set CONFIG_CRYPTO_SHA3_256_S390=y CONFIG_CRYPTO_SHA3_512_S390=m CONFIG_CRYPTO_GHASH_S390=m CONFIG_CRYPTO_AES_S390=m CONFIG_CRYPTO_DES_S390=y CONFIG_CRYPTO_CHACHA_S390=m # end of Accelerated Cryptographic Algorithms for CPU (s390) # CONFIG_CRYPTO_HW is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y CONFIG_PKCS8_PRIVATE_KEY_PARSER=m CONFIG_PKCS7_MESSAGE_PARSER=y # CONFIG_PKCS7_TEST_KEY is not set CONFIG_SIGNED_PE_FILE_VERIFICATION=y CONFIG_FIPS_SIGNATURE_SELFTEST=y # # Certificates for signature checking # CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" # CONFIG_MODULE_SIG_KEY_TYPE_RSA is not set CONFIG_MODULE_SIG_KEY_TYPE_ECDSA=y CONFIG_SYSTEM_TRUSTED_KEYRING=y CONFIG_SYSTEM_TRUSTED_KEYS="" CONFIG_SYSTEM_EXTRA_CERTIFICATE=y CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096 # CONFIG_SECONDARY_TRUSTED_KEYRING is not set CONFIG_SYSTEM_BLACKLIST_KEYRING=y CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" # CONFIG_SYSTEM_REVOCATION_LIST is not set CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y # end of Certificates for signature checking CONFIG_BINARY_PRINTF=y # # Library routines # CONFIG_RAID6_PQ=m # CONFIG_RAID6_PQ_BENCHMARK is not set CONFIG_LINEAR_RANGES=m CONFIG_PACKING=y CONFIG_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_CORDIC=m CONFIG_PRIME_NUMBERS=m CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y # # Crypto library routines # CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y # CONFIG_CRYPTO_LIB_CHACHA is not set CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m # CONFIG_CRYPTO_LIB_CURVE25519 is not set CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y # CONFIG_CRYPTO_LIB_POLY1305 is not set # CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set CONFIG_CRYPTO_LIB_SHA1=m CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC_T10DIF=m # CONFIG_CRC64_ROCKSOFT is not set CONFIG_CRC_ITU_T=y CONFIG_CRC32=y CONFIG_CRC32_SELFTEST=y # CONFIG_CRC32_SLICEBY8 is not set CONFIG_CRC32_SLICEBY4=y # CONFIG_CRC32_SARWATE is not set # CONFIG_CRC32_BIT is not set CONFIG_CRC64=m CONFIG_CRC4=m CONFIG_CRC7=y CONFIG_LIBCRC32C=m CONFIG_CRC8=y CONFIG_XXHASH=y CONFIG_RANDOM32_SELFTEST=y CONFIG_842_COMPRESS=m CONFIG_842_DECOMPRESS=m CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m # CONFIG_ZLIB_DFLTCC is not set CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4_COMPRESS=m CONFIG_LZ4HC_COMPRESS=m CONFIG_LZ4_DECOMPRESS=m CONFIG_ZSTD_COMMON=y CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y CONFIG_XZ_DEC_POWERPC=y # CONFIG_XZ_DEC_IA64 is not set # CONFIG_XZ_DEC_ARM is not set CONFIG_XZ_DEC_ARMTHUMB=y # CONFIG_XZ_DEC_SPARC is not set # CONFIG_XZ_DEC_MICROLZMA is not set CONFIG_XZ_DEC_BCJ=y CONFIG_XZ_DEC_TEST=m CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_LZMA=y CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_BCH=m CONFIG_INTERVAL_TREE=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_DMA=y CONFIG_DMA_OPS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED=y CONFIG_SWIOTLB=y # CONFIG_DMA_CMA is not set # CONFIG_DMA_API_DEBUG is not set CONFIG_DMA_MAP_BENCHMARK=y CONFIG_SGL_ALLOC=y CONFIG_IOMMU_HELPER=y CONFIG_CHECK_SIGNATURE=y # CONFIG_CPUMASK_OFFSTACK is not set # CONFIG_FORCE_NR_CPUS is not set CONFIG_GLOB=y # CONFIG_GLOB_SELFTEST is not set CONFIG_CLZ_TAB=y CONFIG_IRQ_POLL=y CONFIG_MPILIB=y CONFIG_OID_REGISTRY=y CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_VDSO_TIME_NS=y CONFIG_SG_POOL=y CONFIG_MEMREGION=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y CONFIG_SBITMAP=y # CONFIG_PARMAN is not set # CONFIG_OBJAGG is not set # end of Library routines # # Kernel hacking # # # printk and dmesg options # CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_SYMBOLIC_ERRNAME is not set # end of printk and dmesg options CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_MISC is not set # # Compile-time checks and compiler options # CONFIG_AS_HAS_NON_CONST_LEB128=y CONFIG_DEBUG_INFO_NONE=y # CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set # CONFIG_DEBUG_INFO_DWARF4 is not set # CONFIG_DEBUG_INFO_DWARF5 is not set CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set # CONFIG_HEADERS_INSTALL is not set CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_SECTION_MISMATCH_WARN_ONLY=y # CONFIG_VMLINUX_MAP is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options # # Generic Kernel Debugging Instruments # # CONFIG_MAGIC_SYSRQ is not set CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y CONFIG_UBSAN=y CONFIG_CC_HAS_UBSAN_BOUNDS=y # CONFIG_UBSAN_BOUNDS is not set CONFIG_UBSAN_SHIFT=y # CONFIG_UBSAN_DIV_ZERO is not set CONFIG_UBSAN_UNREACHABLE=y # CONFIG_UBSAN_BOOL is not set CONFIG_UBSAN_ENUM=y CONFIG_UBSAN_SANITIZE_ALL=y CONFIG_TEST_UBSAN=m CONFIG_HAVE_ARCH_KCSAN=y CONFIG_HAVE_KCSAN_COMPILER=y # CONFIG_KCSAN is not set # end of Generic Kernel Debugging Instruments # # Networking Debugging # # end of Networking Debugging # # Memory Debugging # CONFIG_PAGE_EXTENSION=y CONFIG_DEBUG_PAGEALLOC=y CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y # CONFIG_PAGE_OWNER is not set CONFIG_PAGE_POISONING=y CONFIG_DEBUG_PAGE_REF=y CONFIG_DEBUG_RODATA_TEST=y CONFIG_ARCH_HAS_DEBUG_WX=y # CONFIG_DEBUG_WX is not set CONFIG_GENERIC_PTDUMP=y CONFIG_PTDUMP_CORE=y CONFIG_PTDUMP_DEBUGFS=y CONFIG_DEBUG_OBJECTS=y # CONFIG_DEBUG_OBJECTS_SELFTEST is not set # CONFIG_DEBUG_OBJECTS_FREE is not set # CONFIG_DEBUG_OBJECTS_TIMERS is not set # CONFIG_DEBUG_OBJECTS_WORK is not set # CONFIG_DEBUG_OBJECTS_RCU_HEAD is not set # CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER is not set CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 CONFIG_SHRINKER_DEBUG=y CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set CONFIG_DEBUG_STACK_USAGE=y # CONFIG_SCHED_STACK_END_CHECK is not set CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y # CONFIG_DEBUG_VM is not set CONFIG_DEBUG_VM_PGTABLE=y # CONFIG_DEBUG_MEMORY_INIT is not set CONFIG_DEBUG_PER_CPU_MAPS=y CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y CONFIG_HAVE_ARCH_KFENCE=y # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set # # Debug Oops, Lockups and Hangs # # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 CONFIG_DETECT_HUNG_TASK=y CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y # CONFIG_WQ_WATCHDOG is not set CONFIG_TEST_LOCKUP=m # end of Debug Oops, Lockups and Hangs # # Scheduler Debugging # # end of Scheduler Debugging CONFIG_DEBUG_TIMEKEEPING=y # # Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_PROVE_LOCKING=y CONFIG_PROVE_RAW_LOCK_NESTING=y CONFIG_LOCK_STAT=y CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y CONFIG_DEBUG_RWSEMS=y CONFIG_DEBUG_LOCK_ALLOC=y CONFIG_LOCKDEP=y CONFIG_LOCKDEP_BITS=15 CONFIG_LOCKDEP_CHAINS_BITS=16 CONFIG_LOCKDEP_STACK_TRACE_BITS=19 CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 # CONFIG_DEBUG_LOCKDEP is not set CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_DEBUG_LOCKING_API_SELFTESTS=y CONFIG_LOCK_TORTURE_TEST=y CONFIG_WW_MUTEX_SELFTEST=m CONFIG_SCF_TORTURE_TEST=y # CONFIG_CSD_LOCK_WAIT_DEBUG is not set # end of Lock Debugging (spinlocks, mutexes, etc...) CONFIG_TRACE_IRQFLAGS=y # CONFIG_DEBUG_IRQFLAGS is not set CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set CONFIG_DEBUG_KOBJECT=y # # Debug kernel data structures # CONFIG_DEBUG_LIST=y # CONFIG_DEBUG_PLIST is not set CONFIG_DEBUG_SG=y # CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_BUG_ON_DATA_CORRUPTION is not set # CONFIG_DEBUG_MAPLE_TREE is not set # end of Debug kernel data structures # CONFIG_DEBUG_CREDENTIALS is not set # # RCU Debugging # CONFIG_PROVE_RCU=y CONFIG_PROVE_RCU_LIST=y CONFIG_TORTURE_TEST=y # CONFIG_RCU_SCALE_TEST is not set # CONFIG_RCU_TORTURE_TEST is not set CONFIG_RCU_REF_SCALE_TEST=y CONFIG_RCU_CPU_STALL_TIMEOUT=21 CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 CONFIG_RCU_TRACE=y CONFIG_RCU_EQS_DEBUG=y # end of RCU Debugging CONFIG_DEBUG_WQ_FORCE_RR_CPU=y # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set CONFIG_NOP_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_FENTRY=y CONFIG_HAVE_NOP_MCOUNT=y CONFIG_TRACER_MAX_TRACE=y CONFIG_TRACE_CLOCK=y CONFIG_RING_BUFFER=y CONFIG_EVENT_TRACING=y CONFIG_CONTEXT_SWITCH_TRACER=y CONFIG_RING_BUFFER_ALLOW_SWAP=y CONFIG_PREEMPTIRQ_TRACEPOINTS=y CONFIG_TRACING=y CONFIG_GENERIC_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y CONFIG_BOOTTIME_TRACING=y # CONFIG_FUNCTION_TRACER is not set # CONFIG_STACK_TRACER is not set CONFIG_IRQSOFF_TRACER=y # CONFIG_SCHED_TRACER is not set # CONFIG_HWLAT_TRACER is not set CONFIG_OSNOISE_TRACER=y # CONFIG_TIMERLAT_TRACER is not set CONFIG_FTRACE_SYSCALLS=y CONFIG_TRACER_SNAPSHOT=y CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y CONFIG_TRACE_BRANCH_PROFILING=y # CONFIG_BRANCH_PROFILE_NONE is not set CONFIG_PROFILE_ANNOTATED_BRANCHES=y # CONFIG_PROFILE_ALL_BRANCHES is not set CONFIG_TRACING_BRANCHES=y CONFIG_BRANCH_TRACER=y CONFIG_BLK_DEV_IO_TRACE=y # CONFIG_UPROBE_EVENTS is not set CONFIG_DYNAMIC_EVENTS=y CONFIG_SYNTH_EVENTS=y # CONFIG_USER_EVENTS is not set # CONFIG_HIST_TRIGGERS is not set CONFIG_TRACE_EVENT_INJECT=y # CONFIG_TRACEPOINT_BENCHMARK is not set CONFIG_RING_BUFFER_BENCHMARK=y # CONFIG_TRACE_EVAL_MAP_FILE is not set CONFIG_FTRACE_SELFTEST=y CONFIG_FTRACE_STARTUP_TEST=y CONFIG_EVENT_TRACE_STARTUP_TEST=y # CONFIG_EVENT_TRACE_TEST_SYSCALLS is not set CONFIG_RING_BUFFER_STARTUP_TEST=y # CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set CONFIG_PREEMPTIRQ_DELAY_TEST=m CONFIG_SYNTH_EVENT_GEN_TEST=y CONFIG_DA_MON_EVENTS=y CONFIG_DA_MON_EVENTS_ID=y CONFIG_RV=y CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PRINTK=y CONFIG_RV_REACT_PANIC=y # CONFIG_SAMPLES is not set CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y CONFIG_STRICT_DEVMEM=y CONFIG_IO_STRICT_DEVMEM=y # # s390 Debugging # CONFIG_EARLY_PRINTK=y CONFIG_DEBUG_ENTRY=y # CONFIG_CIO_INJECT is not set # end of s390 Debugging # # Kernel Testing and Coverage # CONFIG_KUNIT=y CONFIG_KUNIT_DEBUGFS=y # CONFIG_KUNIT_TEST is not set CONFIG_KUNIT_EXAMPLE_TEST=y # CONFIG_KUNIT_ALL_TESTS is not set CONFIG_KUNIT_DEFAULT_ENABLED=y # CONFIG_NOTIFIER_ERROR_INJECTION is not set CONFIG_FAULT_INJECTION=y CONFIG_FAIL_PAGE_ALLOC=y # CONFIG_FAULT_INJECTION_USERCOPY is not set CONFIG_FAIL_MAKE_REQUEST=y # CONFIG_FAIL_IO_TIMEOUT is not set # CONFIG_FAULT_INJECTION_DEBUG_FS is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set # end of Kernel Testing and Coverage # # Rust hacking # # end of Rust hacking # CONFIG_WARN_MISSING_DOCUMENTS is not set # CONFIG_WARN_ABI_ERRORS is not set # end of Kernel hacking ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 05/12] pinctrl: cirrus: Add support for CS48L31/32/33 codecs @ 2022-11-12 21:01 ` kernel test robot 0 siblings, 0 replies; 98+ messages in thread From: kernel test robot @ 2022-11-12 21:01 UTC (permalink / raw) To: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio, Richard Fitzgerald, oe-kbuild-all [-- Attachment #1: Type: text/plain, Size: 2103 bytes --] Hi Richard, Thank you for the patch! Yet something to improve: [auto build test ERROR on broonie-sound/for-next] [also build test ERROR on lee-mfd/for-mfd-next linusw-pinctrl/devel linusw-pinctrl/for-next broonie-regulator/for-next linus/master v6.1-rc4 next-20221111] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Richard-Fitzgerald/Add-support-for-the-Cirrus-Logic-CS48L32-audio-codecs/20221110-005630 base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next patch link: https://lore.kernel.org/r/20221109165331.29332-6-rf%40opensource.cirrus.com patch subject: [PATCH 05/12] pinctrl: cirrus: Add support for CS48L31/32/33 codecs config: s390-randconfig-c44-20221113 compiler: s390-linux-gcc (GCC) 12.1.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/intel-lab-lkp/linux/commit/23ae23e54f7ece974162bb1a195bd01addda9400 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Richard-Fitzgerald/Add-support-for-the-Cirrus-Logic-CS48L32-audio-codecs/20221110-005630 git checkout 23ae23e54f7ece974162bb1a195bd01addda9400 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=s390 SHELL=/bin/bash If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): s390-linux-ld: drivers/pinctrl/cirrus/pinctrl-cs48l32.o: in function `pinconf_generic_dt_node_to_map_all': >> pinctrl-cs48l32.c:(.text+0xa8c): undefined reference to `pinconf_generic_dt_node_to_map' -- 0-DAY CI Kernel Test Service https://01.org/lkp [-- Attachment #2: config --] [-- Type: text/plain, Size: 115479 bytes --] # # Automatically generated file; DO NOT EDIT. # Linux/s390 6.1.0-rc1 Kernel Configuration # CONFIG_CC_VERSION_TEXT="s390-linux-gcc (GCC) 12.1.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=120100 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y CONFIG_AS_VERSION=23800 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23800 CONFIG_LLD_VERSION=0 CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=123 CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y # # General setup # CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_COMPILE_TEST=y # CONFIG_WERROR is not set CONFIG_LOCALVERSION="" CONFIG_BUILD_SALT="" CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_BZIP2=y CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_XZ=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_HAVE_KERNEL_LZ4=y CONFIG_HAVE_KERNEL_ZSTD=y CONFIG_HAVE_KERNEL_UNCOMPRESSED=y # CONFIG_KERNEL_GZIP is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_LZMA=y # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set # CONFIG_KERNEL_ZSTD is not set # CONFIG_KERNEL_UNCOMPRESSED is not set CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SYSVIPC=y # CONFIG_WATCH_QUEUE is not set CONFIG_CROSS_MEMORY_ATTACH=y # CONFIG_USELIB is not set CONFIG_HAVE_ARCH_AUDITSYSCALL=y # # IRQ subsystem # CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_SIM=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_SPARSE_IRQ=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set # end of IRQ subsystem CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_TIME_KUNIT_TEST=m CONFIG_CONTEXT_TRACKING=y CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem # CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ_COMMON=y # CONFIG_HZ_PERIODIC is not set CONFIG_NO_HZ_IDLE=y # CONFIG_NO_HZ is not set CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem CONFIG_HAVE_EBPF_JIT=y CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y # # BPF subsystem # # CONFIG_BPF_SYSCALL is not set # end of BPF subsystem CONFIG_PREEMPT_VOLUNTARY_BUILD=y # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set CONFIG_PREEMPT_COUNT=y # # CPU/Task time and stats accounting # CONFIG_VIRT_CPU_ACCOUNTING=y CONFIG_VIRT_CPU_ACCOUNTING_NATIVE=y # CONFIG_PSI is not set # end of CPU/Task time and stats accounting CONFIG_CPU_ISOLATION=y # # RCU Subsystem # CONFIG_TREE_RCU=y CONFIG_RCU_EXPERT=y CONFIG_SRCU=y CONFIG_TREE_SRCU=y # CONFIG_FORCE_TASKS_RCU is not set # CONFIG_FORCE_TASKS_RUDE_RCU is not set # CONFIG_FORCE_TASKS_TRACE_RCU is not set CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y CONFIG_RCU_FANOUT=64 CONFIG_RCU_FANOUT_LEAF=16 # CONFIG_RCU_NOCB_CPU is not set # end of RCU Subsystem CONFIG_IKCONFIG=m # CONFIG_IKHEADERS is not set # # Scheduler features # # end of Scheduler features CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y CONFIG_CC_HAS_INT128=y CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y CONFIG_CGROUP_FAVOR_DYNMODS=y CONFIG_MEMCG=y CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_PIDS=y CONFIG_CGROUP_RDMA=y # CONFIG_CGROUP_FREEZER is not set # CONFIG_CGROUP_HUGETLB is not set # CONFIG_CPUSETS is not set CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y # CONFIG_CGROUP_PERF is not set CONFIG_CGROUP_MISC=y CONFIG_CGROUP_DEBUG=y CONFIG_SCHED_AUTOGROUP=y # CONFIG_SYSFS_DEPRECATED is not set CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" # CONFIG_RD_GZIP is not set CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y CONFIG_RD_XZ=y CONFIG_RD_LZO=y # CONFIG_RD_LZ4 is not set # CONFIG_RD_ZSTD is not set CONFIG_BOOT_CONFIG=y # CONFIG_BOOT_CONFIG_EMBED is not set CONFIG_INITRAMFS_PRESERVE_MTIME=y CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_EXPERT=y # CONFIG_MULTIUSER is not set # CONFIG_SGETMASK_SYSCALL is not set CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y # CONFIG_PRINTK is not set # CONFIG_BUG is not set CONFIG_BASE_FULL=y # CONFIG_FUTEX is not set CONFIG_EPOLL=y CONFIG_SIGNALFD=y # CONFIG_TIMERFD is not set CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y # CONFIG_KCMP is not set CONFIG_RSEQ=y # CONFIG_DEBUG_RSEQ is not set # CONFIG_EMBEDDED is not set CONFIG_HAVE_PERF_EVENTS=y CONFIG_PC104=y # # Kernel Performance Events And Counters # CONFIG_PERF_EVENTS=y # CONFIG_DEBUG_PERF_USE_VMALLOC is not set # end of Kernel Performance Events And Counters CONFIG_SYSTEM_DATA_VERIFICATION=y CONFIG_PROFILING=y CONFIG_TRACEPOINTS=y # end of General setup CONFIG_MMU=y CONFIG_CPU_BIG_ENDIAN=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_AUDIT_ARCH=y CONFIG_NO_IOPORT_MAP=y # CONFIG_PCI_QUIRKS is not set CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_S390=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_PGTABLE_LEVELS=5 CONFIG_HAVE_LIVEPATCH=y # # Processor type and features # CONFIG_HAVE_MARCH_Z10_FEATURES=y CONFIG_HAVE_MARCH_Z196_FEATURES=y CONFIG_HAVE_MARCH_ZEC12_FEATURES=y CONFIG_HAVE_MARCH_Z13_FEATURES=y CONFIG_HAVE_MARCH_Z14_FEATURES=y CONFIG_HAVE_MARCH_Z15_FEATURES=y # CONFIG_MARCH_Z10 is not set # CONFIG_MARCH_Z196 is not set # CONFIG_MARCH_ZEC12 is not set # CONFIG_MARCH_Z13 is not set # CONFIG_MARCH_Z14 is not set CONFIG_MARCH_Z15=y CONFIG_MARCH_ZEC12_TUNE=y # CONFIG_TUNE_DEFAULT is not set # CONFIG_TUNE_Z10 is not set # CONFIG_TUNE_Z196 is not set CONFIG_TUNE_ZEC12=y # CONFIG_TUNE_Z13 is not set # CONFIG_TUNE_Z14 is not set # CONFIG_TUNE_Z15 is not set # CONFIG_TUNE_Z16 is not set CONFIG_64BIT=y CONFIG_COMMAND_LINE_SIZE=4096 CONFIG_SMP=y CONFIG_NR_CPUS=64 CONFIG_HOTPLUG_CPU=y # CONFIG_SCHED_TOPOLOGY is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_250 is not set # CONFIG_HZ_300 is not set CONFIG_HZ_1000=y CONFIG_HZ=1000 CONFIG_SCHED_HRTICK=y CONFIG_KEXEC=y # CONFIG_KERNEL_NOBP is not set CONFIG_EXPOLINE=y CONFIG_EXPOLINE_EXTERN=y # CONFIG_EXPOLINE_OFF is not set # CONFIG_EXPOLINE_AUTO is not set CONFIG_EXPOLINE_FULL=y CONFIG_RELOCATABLE=y # CONFIG_RANDOMIZE_BASE is not set # end of Processor type and features # # Memory setup # CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_DEFAULT=y CONFIG_MAX_PHYSMEM_BITS=46 CONFIG_CHECK_STACK=y CONFIG_STACK_GUARD=256 # end of Memory setup # # I/O subsystem # # CONFIG_QDIO is not set CONFIG_PCI_NR_FUNCTIONS=512 CONFIG_HAS_IOMEM=y # CONFIG_CHSC_SCH is not set # CONFIG_SCM_BUS is not set # end of I/O subsystem # # Dump support # # CONFIG_CRASH_DUMP is not set # end of Dump support CONFIG_CCW=y # # Virtualization # # CONFIG_PROTECTED_VIRTUALIZATION_GUEST is not set CONFIG_PFAULT=y CONFIG_CMM=m # CONFIG_S390_HYPFS_FS is not set CONFIG_HAVE_KVM=y # CONFIG_VIRTUALIZATION is not set # CONFIG_S390_GUEST is not set # end of Virtualization CONFIG_S390_MODULES_SANITY_TEST_HELPERS=y # # Selftests # CONFIG_S390_UNWIND_SELFTEST=y CONFIG_S390_MODULES_SANITY_TEST=m # end of Selftests # # General architecture-dependent options # CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y CONFIG_GENERIC_ENTRY=y # CONFIG_KPROBES is not set CONFIG_JUMP_LABEL=y CONFIG_STATIC_KEYS_SELFTEST=y CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_KPROBES_ON_FTRACE=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y CONFIG_HAVE_NMI=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_ARCH_HAS_FORTIFY_SOURCE=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_ARCH_32BIT_USTAT_F_TINODE=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y CONFIG_MMU_GATHER_TABLE_FREE=y CONFIG_MMU_GATHER_RCU_TABLE_FREE=y CONFIG_MMU_GATHER_MERGE_VMAS=y CONFIG_MMU_GATHER_NO_GATHER=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_HAVE_CMPXCHG_LOCAL=y CONFIG_HAVE_CMPXCHG_DOUBLE=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y # CONFIG_SECCOMP is not set CONFIG_LTO_NONE=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_IDLE=y CONFIG_ARCH_HAS_SCALED_CPUTIME=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_SOFT_DIRTY=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ALTERNATE_USER_ADDRESS_SPACE=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_HAVE_RELIABLE_STACKTRACE=y CONFIG_CLONE_BACKWARDS2=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y # CONFIG_COMPAT_32BIT_TIME is not set CONFIG_HAVE_ARCH_VMAP_STACK=y # CONFIG_VMAP_STACK is not set CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_HAS_MEM_ENCRYPT=y CONFIG_ARCH_HAS_VDSO_DATA=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y # # GCOV-based kernel profiling # # CONFIG_GCOV_KERNEL is not set CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling CONFIG_HAVE_GCC_PLUGINS=y # CONFIG_GCC_PLUGINS is not set # end of General architecture-dependent options CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULE_SIG_FORMAT=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODULE_UNLOAD_TAINT_TRACKING=y CONFIG_MODVERSIONS=y CONFIG_ASM_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_MODULE_SIG=y CONFIG_MODULE_SIG_FORCE=y CONFIG_MODULE_SIG_ALL=y # CONFIG_MODULE_SIG_SHA1 is not set # CONFIG_MODULE_SIG_SHA224 is not set CONFIG_MODULE_SIG_SHA256=y # CONFIG_MODULE_SIG_SHA384 is not set # CONFIG_MODULE_SIG_SHA512 is not set CONFIG_MODULE_SIG_HASH="sha256" # CONFIG_MODULE_COMPRESS_NONE is not set # CONFIG_MODULE_COMPRESS_GZIP is not set # CONFIG_MODULE_COMPRESS_XZ is not set CONFIG_MODULE_COMPRESS_ZSTD=y # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y # CONFIG_BLOCK_LEGACY_AUTOLOAD is not set CONFIG_BLK_RQ_ALLOC_TIME=y CONFIG_BLK_CGROUP_RWSTAT=y CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_ICQ=y CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_DEV_INTEGRITY is not set CONFIG_BLK_DEV_ZONED=y # CONFIG_BLK_DEV_THROTTLING is not set CONFIG_BLK_WBT=y # CONFIG_BLK_WBT_MQ is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_FC_APPID is not set CONFIG_BLK_CGROUP_IOCOST=y CONFIG_BLK_CGROUP_IOPRIO=y # CONFIG_BLK_DEBUG_FS is not set CONFIG_BLK_SED_OPAL=y # CONFIG_BLK_INLINE_ENCRYPTION is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y CONFIG_EFI_PARTITION=y # end of Partition Types CONFIG_BLK_MQ_PCI=y CONFIG_BLK_MQ_VIRTIO=y # # IO Schedulers # CONFIG_MQ_IOSCHED_DEADLINE=y # CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_IOSCHED_BFQ=y CONFIG_BFQ_GROUP_IOSCHED=y # CONFIG_BFQ_CGROUP_DEBUG is not set # end of IO Schedulers CONFIG_PADATA=y CONFIG_ASN1=y CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y CONFIG_ARCH_INLINE_SPIN_LOCK=y CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y CONFIG_ARCH_INLINE_SPIN_UNLOCK=y CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y CONFIG_ARCH_INLINE_READ_TRYLOCK=y CONFIG_ARCH_INLINE_READ_LOCK=y CONFIG_ARCH_INLINE_READ_LOCK_BH=y CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y CONFIG_ARCH_INLINE_READ_UNLOCK=y CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y CONFIG_ARCH_INLINE_WRITE_TRYLOCK=y CONFIG_ARCH_INLINE_WRITE_LOCK=y CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y CONFIG_ARCH_INLINE_WRITE_UNLOCK=y CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_RWSEM_SPIN_ON_OWNER=y CONFIG_LOCK_SPIN_ON_OWNER=y CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y # # Executable file formats # CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_ELF_KUNIT_TEST is not set CONFIG_ARCH_BINFMT_ELF_STATE=y CONFIG_ELFCORE=y # CONFIG_BINFMT_SCRIPT is not set # CONFIG_BINFMT_MISC is not set # CONFIG_COREDUMP is not set # end of Executable file formats # # Memory Management options # # CONFIG_SWAP is not set # # SLAB allocator options # # CONFIG_SLAB is not set # CONFIG_SLUB is not set CONFIG_SLOB=y # end of SLAB allocator options CONFIG_SHUFFLE_PAGE_ALLOCATOR=y # CONFIG_COMPAT_BRK is not set CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y CONFIG_HAVE_MEMBLOCK_PHYS_MAP=y CONFIG_HAVE_FAST_GUP=y CONFIG_MEMORY_ISOLATION=y CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y CONFIG_MEMORY_HOTREMOVE=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y # CONFIG_COMPACTION is not set CONFIG_PAGE_REPORTING=y CONFIG_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 # CONFIG_TRANSPARENT_HUGEPAGE is not set CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 CONFIG_DEFERRED_STRUCT_PAGE_INIT=y # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y CONFIG_ZONE_DMA=y CONFIG_GET_FREE_REGION=y # CONFIG_VM_EVENT_COUNTERS is not set CONFIG_PERCPU_STATS=y CONFIG_GUP_TEST=y CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_USERFAULTFD=y CONFIG_LRU_GEN=y # CONFIG_LRU_GEN_ENABLED is not set CONFIG_LRU_GEN_STATS=y # # Data Access Monitoring # # CONFIG_DAMON is not set # end of Data Access Monitoring # end of Memory Management options # CONFIG_NET is not set # # Device Drivers # CONFIG_HAVE_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y # CONFIG_PCIEPORTBUS is not set # CONFIG_PCIEASPM is not set CONFIG_PCIE_PTM=y CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCI_MSI_ARCH_FALLBACKS=y CONFIG_PCI_DEBUG=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=m # CONFIG_PCI_PF_STUB is not set CONFIG_PCI_ATS=y CONFIG_PCI_DOE=y CONFIG_PCI_IOV=y CONFIG_PCI_PRI=y CONFIG_PCI_PASID=y CONFIG_PCIE_BUS_TUNE_OFF=y # CONFIG_PCIE_BUS_DEFAULT is not set # CONFIG_PCIE_BUS_SAFE is not set # CONFIG_PCIE_BUS_PERFORMANCE is not set # CONFIG_PCIE_BUS_PEER2PEER is not set CONFIG_HOTPLUG_PCI=y CONFIG_HOTPLUG_PCI_CPCI=y CONFIG_HOTPLUG_PCI_SHPC=y # CONFIG_HOTPLUG_PCI_S390 is not set # # PCI controller drivers # # CONFIG_PCIE_XILINX_NWL is not set # CONFIG_PCI_TEGRA is not set # CONFIG_PCIE_RCAR_HOST is not set # CONFIG_PCIE_RCAR_EP is not set CONFIG_PCIE_XILINX=y # CONFIG_PCIE_XILINX_CPM is not set # CONFIG_PCI_VERSATILE is not set # CONFIG_PCIE_ALTERA is not set # CONFIG_PCIE_MEDIATEK_GEN3 is not set # CONFIG_PCIE_MT7621 is not set # # DesignWare PCI Core Support # CONFIG_PCIE_DW=y CONFIG_PCIE_DW_HOST=y CONFIG_PCIE_DW_EP=y CONFIG_PCIE_DW_PLAT=y CONFIG_PCIE_DW_PLAT_HOST=y CONFIG_PCIE_DW_PLAT_EP=y # CONFIG_PCI_EXYNOS is not set # CONFIG_PCI_IMX6 is not set # CONFIG_PCIE_SPEAR13XX is not set # CONFIG_PCI_KEYSTONE_HOST is not set # CONFIG_PCI_KEYSTONE_EP is not set # CONFIG_PCIE_ARMADA_8K is not set # CONFIG_PCIE_ARTPEC6_HOST is not set # CONFIG_PCIE_ARTPEC6_EP is not set # CONFIG_PCIE_KEEMBAY_HOST is not set # CONFIG_PCIE_KEEMBAY_EP is not set # CONFIG_PCIE_HISI_STB is not set CONFIG_PCI_MESON=y # CONFIG_PCIE_TEGRA194_HOST is not set # CONFIG_PCIE_TEGRA194_EP is not set # CONFIG_PCIE_VISCONTI_HOST is not set # CONFIG_PCIE_FU740 is not set # end of DesignWare PCI Core Support # # Mobiveil PCIe Core Support # # CONFIG_PCIE_LAYERSCAPE_GEN4 is not set # end of Mobiveil PCIe Core Support # # Cadence PCIe controllers support # # end of Cadence PCIe controllers support # end of PCI controller drivers # # PCI Endpoint # CONFIG_PCI_ENDPOINT=y CONFIG_PCI_ENDPOINT_CONFIGFS=y CONFIG_PCI_EPF_TEST=y CONFIG_PCI_EPF_NTB=y # end of PCI Endpoint # # PCI switch controller drivers # CONFIG_PCI_SW_SWITCHTEC=m # end of PCI switch controller drivers CONFIG_CXL_BUS=y CONFIG_CXL_PCI=y # CONFIG_CXL_MEM_RAW_COMMANDS is not set # CONFIG_CXL_PMEM is not set CONFIG_CXL_MEM=y CONFIG_CXL_PORT=y CONFIG_CXL_REGION=y CONFIG_PCCARD=y CONFIG_PCMCIA=y CONFIG_PCMCIA_LOAD_CIS=y # CONFIG_CARDBUS is not set # # PC-card bridges # CONFIG_YENTA=m # CONFIG_YENTA_O2 is not set CONFIG_YENTA_RICOH=y # CONFIG_YENTA_TI is not set # CONFIG_YENTA_TOSHIBA is not set # CONFIG_PD6729 is not set CONFIG_I82092=y CONFIG_PCCARD_NONSTATIC=y CONFIG_RAPIDIO=y CONFIG_RAPIDIO_DISC_TIMEOUT=30 # CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set CONFIG_RAPIDIO_DEBUG=y CONFIG_RAPIDIO_ENUM_BASIC=m # CONFIG_RAPIDIO_CHMAN is not set CONFIG_RAPIDIO_MPORT_CDEV=m # # RapidIO Switch drivers # CONFIG_RAPIDIO_CPS_XX=m CONFIG_RAPIDIO_CPS_GEN2=m CONFIG_RAPIDIO_RXS_GEN3=m # end of RapidIO Switch drivers # # Generic Driver Options # CONFIG_AUXILIARY_BUS=y # CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y # CONFIG_STANDALONE is not set CONFIG_PREVENT_FIRMWARE_BUILD=y # # Firmware loader # CONFIG_FW_LOADER=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_FW_LOADER_SYSFS=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_FW_LOADER_USER_HELPER is not set # CONFIG_FW_LOADER_COMPRESS is not set CONFIG_FW_UPLOAD=y # end of Firmware loader # CONFIG_ALLOW_DEV_COREDUMP is not set # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set # CONFIG_PM_QOS_KUNIT_TEST is not set # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set # CONFIG_DRIVER_PE_KUNIT_TEST is not set CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y CONFIG_REGMAP_SPI=y CONFIG_REGMAP_SPMI=m CONFIG_REGMAP_W1=y CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_IRQ=y CONFIG_DMA_SHARED_BUFFER=y CONFIG_DMA_FENCE_TRACE=y # end of Generic Driver Options # # Bus devices # # CONFIG_ARM_INTEGRATOR_LM is not set # CONFIG_BT1_APB is not set # CONFIG_BT1_AXI is not set # CONFIG_HISILICON_LPC is not set # CONFIG_INTEL_IXP4XX_EB is not set # CONFIG_QCOM_EBI2 is not set CONFIG_MHI_BUS=y # CONFIG_MHI_BUS_DEBUG is not set # CONFIG_MHI_BUS_PCI_GENERIC is not set CONFIG_MHI_BUS_EP=m # end of Bus devices # # Firmware Drivers # # # ARM System Control and Management Interface Protocol # # CONFIG_ARM_SCMI_PROTOCOL is not set # end of ARM System Control and Management Interface Protocol CONFIG_FIRMWARE_MEMMAP=y # CONFIG_BCM47XX_NVRAM is not set CONFIG_GOOGLE_FIRMWARE=y # # Tegra firmware driver # # end of Tegra firmware driver # end of Firmware Drivers CONFIG_GNSS=m CONFIG_MTD=m # CONFIG_MTD_TESTS is not set # # Partition parsers # # CONFIG_MTD_AR7_PARTS is not set # CONFIG_MTD_BCM63XX_PARTS is not set # CONFIG_MTD_BRCM_U_BOOT is not set CONFIG_MTD_CMDLINE_PARTS=m # CONFIG_MTD_PARSER_IMAGETAG is not set # CONFIG_MTD_PARSER_TRX is not set # CONFIG_MTD_SHARPSL_PARTS is not set CONFIG_MTD_REDBOOT_PARTS=m CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y CONFIG_MTD_REDBOOT_PARTS_READONLY=y # end of Partition parsers # # User Modules And Translation Layers # CONFIG_MTD_BLKDEVS=m CONFIG_MTD_BLOCK=m CONFIG_MTD_BLOCK_RO=m # # Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. # CONFIG_FTL=m CONFIG_NFTL=m CONFIG_NFTL_RW=y # CONFIG_INFTL is not set CONFIG_RFD_FTL=m # CONFIG_SSFDC is not set CONFIG_SM_FTL=m CONFIG_MTD_OOPS=m # CONFIG_MTD_PARTITIONED_MASTER is not set # # RAM/ROM/Flash chip drivers # CONFIG_MTD_CFI=m # CONFIG_MTD_JEDECPROBE is not set CONFIG_MTD_GEN_PROBE=m # CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_INTELEXT=m CONFIG_MTD_CFI_AMDSTD=m CONFIG_MTD_CFI_STAA=m CONFIG_MTD_CFI_UTIL=m CONFIG_MTD_RAM=m # CONFIG_MTD_ROM is not set CONFIG_MTD_ABSENT=m # end of RAM/ROM/Flash chip drivers # # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set CONFIG_MTD_PHYSMAP=m # CONFIG_MTD_PHYSMAP_COMPAT is not set # CONFIG_MTD_SC520CDP is not set # CONFIG_MTD_NETSC520 is not set # CONFIG_MTD_TS5500 is not set CONFIG_MTD_INTEL_VR_NOR=m CONFIG_MTD_PLATRAM=m # end of Mapping drivers for chip access # # Self-contained MTD device drivers # CONFIG_MTD_PMC551=m CONFIG_MTD_PMC551_BUGFIX=y CONFIG_MTD_PMC551_DEBUG=y CONFIG_MTD_DATAFLASH=m # CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set # CONFIG_MTD_DATAFLASH_OTP is not set CONFIG_MTD_MCHP23K256=m # CONFIG_MTD_MCHP48L640 is not set CONFIG_MTD_SPEAR_SMI=m CONFIG_MTD_SST25L=m CONFIG_MTD_SLRAM=m CONFIG_MTD_PHRAM=m CONFIG_MTD_MTDRAM=m CONFIG_MTDRAM_TOTAL_SIZE=4096 CONFIG_MTDRAM_ERASE_SIZE=128 CONFIG_MTD_BLOCK2MTD=m # # Disk-On-Chip Device Drivers # CONFIG_MTD_DOCG3=m CONFIG_BCH_CONST_M=14 CONFIG_BCH_CONST_T=4 # end of Self-contained MTD device drivers # # NAND # CONFIG_MTD_NAND_CORE=m CONFIG_MTD_ONENAND=m CONFIG_MTD_ONENAND_VERIFY_WRITE=y # CONFIG_MTD_ONENAND_GENERIC is not set # CONFIG_MTD_ONENAND_SAMSUNG is not set # CONFIG_MTD_ONENAND_OTP is not set # CONFIG_MTD_ONENAND_2X_PROGRAM is not set # CONFIG_MTD_RAW_NAND is not set CONFIG_MTD_SPI_NAND=m # # ECC engine support # CONFIG_MTD_NAND_ECC=y CONFIG_MTD_NAND_ECC_SW_HAMMING=y # CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set CONFIG_MTD_NAND_ECC_SW_BCH=y CONFIG_MTD_NAND_ECC_MXIC=y # CONFIG_MTD_NAND_ECC_MEDIATEK is not set # end of ECC engine support # end of NAND # # LPDDR & LPDDR2 PCM memory drivers # CONFIG_MTD_LPDDR=m CONFIG_MTD_QINFO_PROBE=m # end of LPDDR & LPDDR2 PCM memory drivers CONFIG_MTD_SPI_NOR=m CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y CONFIG_MTD_SPI_NOR_SWP_DISABLE=y # CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE is not set # CONFIG_MTD_SPI_NOR_SWP_KEEP is not set # CONFIG_SPI_HISI_SFC is not set CONFIG_MTD_UBI=m CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_FASTMAP=y # CONFIG_MTD_UBI_GLUEBI is not set # CONFIG_MTD_UBI_BLOCK is not set # CONFIG_MTD_HYPERBUS is not set # CONFIG_OF is not set CONFIG_PARPORT=y CONFIG_PARPORT_AX88796=m # CONFIG_PARPORT_1284 is not set CONFIG_PARPORT_NOT_PC=y CONFIG_BLK_DEV=y CONFIG_BLK_DEV_NULL_BLK=y CONFIG_BLK_DEV_NULL_BLK_FAULT_INJECTION=y CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m # CONFIG_ZRAM is not set CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # # DRBD disabled because PROC_FS or INET not selected # CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_CDROM_PKTCDVD is not set # # S/390 block device drivers # CONFIG_DCSSBLK=y CONFIG_DASD=m # CONFIG_DASD_PROFILE is not set CONFIG_DASD_ECKD=m CONFIG_DASD_FBA=m # CONFIG_DASD_DIAG is not set # CONFIG_DASD_EER is not set CONFIG_VIRTIO_BLK=y # CONFIG_BLK_DEV_UBLK is not set # # NVME Support # CONFIG_NVME_COMMON=y CONFIG_NVME_CORE=y CONFIG_BLK_DEV_NVME=m # CONFIG_NVME_MULTIPATH is not set CONFIG_NVME_VERBOSE_ERRORS=y # CONFIG_NVME_HWMON is not set CONFIG_NVME_FABRICS=y CONFIG_NVME_FC=y # CONFIG_NVME_AUTH is not set CONFIG_NVME_TARGET=y # CONFIG_NVME_TARGET_PASSTHRU is not set CONFIG_NVME_TARGET_LOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_AUTH=y # end of NVME Support # # Misc devices # CONFIG_SENSORS_LIS3LV02D=y CONFIG_AD525X_DPOT=y CONFIG_AD525X_DPOT_I2C=y # CONFIG_AD525X_DPOT_SPI is not set # CONFIG_DUMMY_IRQ is not set CONFIG_PHANTOM=y CONFIG_TIFM_CORE=y # CONFIG_TIFM_7XX1 is not set CONFIG_ICS932S401=m # CONFIG_ATMEL_SSC is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_GEHC_ACHC is not set # CONFIG_HP_ILO is not set # CONFIG_QCOM_COINCELL is not set # CONFIG_QCOM_FASTRPC is not set CONFIG_APDS9802ALS=m # CONFIG_ISL29003 is not set CONFIG_ISL29020=y CONFIG_SENSORS_TSL2550=y CONFIG_SENSORS_BH1770=y CONFIG_SENSORS_APDS990X=m CONFIG_HMC6352=y CONFIG_DS1682=y # CONFIG_PCH_PHUB is not set # CONFIG_LATTICE_ECP3_CONFIG is not set CONFIG_SRAM=y CONFIG_DW_XDATA_PCIE=m CONFIG_PCI_ENDPOINT_TEST=y CONFIG_XILINX_SDFEC=m CONFIG_MISC_RTSX=y CONFIG_C2PORT=m # # EEPROM support # CONFIG_EEPROM_AT24=m # CONFIG_EEPROM_AT25 is not set CONFIG_EEPROM_LEGACY=m # CONFIG_EEPROM_MAX6875 is not set CONFIG_EEPROM_93CX6=y CONFIG_EEPROM_93XX46=y CONFIG_EEPROM_IDT_89HPESX=m # CONFIG_EEPROM_EE1004 is not set # end of EEPROM support CONFIG_CB710_CORE=y # CONFIG_CB710_DEBUG is not set CONFIG_CB710_DEBUG_ASSUMPTIONS=y # # Texas Instruments shared transport line discipline # # end of Texas Instruments shared transport line discipline CONFIG_SENSORS_LIS3_SPI=y # CONFIG_SENSORS_LIS3_I2C is not set CONFIG_ALTERA_STAPL=m # CONFIG_GENWQE is not set # CONFIG_ECHO is not set # CONFIG_BCM_VK is not set CONFIG_MISC_ALCOR_PCI=y CONFIG_MISC_RTSX_PCI=y CONFIG_HABANA_AI=y # CONFIG_UACCE is not set # CONFIG_PVPANIC is not set CONFIG_GP_PCI1XXXX=y # end of Misc devices # # SCSI device support # CONFIG_SCSI_MOD=m CONFIG_RAID_ATTRS=m CONFIG_SCSI_COMMON=m CONFIG_SCSI=m CONFIG_SCSI_DMA=y # # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=m # CONFIG_CHR_DEV_ST is not set # CONFIG_BLK_DEV_SR is not set CONFIG_CHR_DEV_SG=m CONFIG_BLK_DEV_BSG=y CONFIG_CHR_DEV_SCH=m # CONFIG_SCSI_CONSTANTS is not set CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y # # SCSI Transports # CONFIG_SCSI_SPI_ATTRS=m CONFIG_SCSI_SAS_ATTRS=m CONFIG_SCSI_SAS_LIBSAS=m CONFIG_SCSI_SAS_HOST_SMP=y CONFIG_SCSI_SRP_ATTRS=m # end of SCSI Transports CONFIG_SCSI_LOWLEVEL=y CONFIG_ISCSI_BOOT_SYSFS=m CONFIG_BLK_DEV_3W_XXXX_RAID=m CONFIG_SCSI_HPSA=m CONFIG_SCSI_3W_9XXX=m CONFIG_SCSI_3W_SAS=m # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set # CONFIG_SCSI_AIC79XX is not set CONFIG_SCSI_AIC94XX=m # CONFIG_AIC94XX_DEBUG is not set CONFIG_SCSI_MVSAS=m CONFIG_SCSI_MVSAS_DEBUG=y # CONFIG_SCSI_MVSAS_TASKLET is not set # CONFIG_SCSI_MVUMI is not set CONFIG_SCSI_ADVANSYS=m CONFIG_SCSI_ARCMSR=m CONFIG_SCSI_ESAS2R=m CONFIG_MEGARAID_NEWGEN=y CONFIG_MEGARAID_MM=m CONFIG_MEGARAID_MAILBOX=m CONFIG_MEGARAID_LEGACY=m # CONFIG_MEGARAID_SAS is not set CONFIG_SCSI_MPT3SAS=m CONFIG_SCSI_MPT2SAS_MAX_SGE=128 CONFIG_SCSI_MPT3SAS_MAX_SGE=128 # CONFIG_SCSI_MPT2SAS is not set CONFIG_SCSI_MPI3MR=m # CONFIG_SCSI_HPTIOP is not set CONFIG_SCSI_BUSLOGIC=m CONFIG_SCSI_FLASHPOINT=y # CONFIG_SCSI_MYRB is not set # CONFIG_SCSI_MYRS is not set CONFIG_SCSI_SNIC=m CONFIG_SCSI_SNIC_DEBUG_FS=y CONFIG_SCSI_DMX3191D=m CONFIG_SCSI_FDOMAIN=m CONFIG_SCSI_FDOMAIN_PCI=m CONFIG_SCSI_IPS=m # CONFIG_SCSI_INITIO is not set CONFIG_SCSI_INIA100=m # CONFIG_SCSI_STEX is not set # CONFIG_SCSI_SYM53C8XX_2 is not set CONFIG_SCSI_QLOGIC_1280=m CONFIG_SCSI_DC395x=m CONFIG_SCSI_AM53C974=m CONFIG_SCSI_WD719X=m CONFIG_SCSI_DEBUG=m # CONFIG_SCSI_PM8001 is not set CONFIG_SCSI_VIRTIO=m CONFIG_SCSI_LOWLEVEL_PCMCIA=y # CONFIG_PCMCIA_AHA152X is not set # CONFIG_PCMCIA_FDOMAIN is not set # CONFIG_PCMCIA_NINJA_SCSI is not set # CONFIG_PCMCIA_QLOGIC is not set CONFIG_PCMCIA_SYM53C500=m CONFIG_SCSI_DH=y CONFIG_SCSI_DH_RDAC=m # CONFIG_SCSI_DH_HP_SW is not set # CONFIG_SCSI_DH_EMC is not set CONFIG_SCSI_DH_ALUA=m # end of SCSI device support # CONFIG_ATA is not set # CONFIG_MD is not set # CONFIG_TARGET_CORE is not set # CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # CONFIG_FIREWIRE=y CONFIG_FIREWIRE_OHCI=m CONFIG_FIREWIRE_SBP2=m # CONFIG_FIREWIRE_NOSY is not set # end of IEEE 1394 (FireWire) support # # Input device support # CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y CONFIG_INPUT_SPARSEKMAP=y CONFIG_INPUT_MATRIXKMAP=m # # Userland interfaces # CONFIG_INPUT_MOUSEDEV=m CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 CONFIG_INPUT_JOYDEV=y CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set # # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set CONFIG_INPUT_MOUSE=y # CONFIG_MOUSE_PS2 is not set CONFIG_MOUSE_SERIAL=y # CONFIG_MOUSE_CYAPA is not set CONFIG_MOUSE_ELAN_I2C=m CONFIG_MOUSE_ELAN_I2C_I2C=y CONFIG_MOUSE_ELAN_I2C_SMBUS=y # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_MOUSE_GPIO is not set # CONFIG_MOUSE_SYNAPTICS_I2C is not set CONFIG_INPUT_JOYSTICK=y CONFIG_JOYSTICK_ANALOG=y CONFIG_JOYSTICK_A3D=y # CONFIG_JOYSTICK_ADC is not set CONFIG_JOYSTICK_ADI=y CONFIG_JOYSTICK_COBRA=m # CONFIG_JOYSTICK_GF2K is not set CONFIG_JOYSTICK_GRIP=m CONFIG_JOYSTICK_GRIP_MP=y CONFIG_JOYSTICK_GUILLEMOT=m CONFIG_JOYSTICK_INTERACT=y # CONFIG_JOYSTICK_SIDEWINDER is not set CONFIG_JOYSTICK_TMDC=y CONFIG_JOYSTICK_IFORCE=m CONFIG_JOYSTICK_IFORCE_232=m CONFIG_JOYSTICK_WARRIOR=m CONFIG_JOYSTICK_MAGELLAN=m CONFIG_JOYSTICK_SPACEORB=y CONFIG_JOYSTICK_SPACEBALL=y CONFIG_JOYSTICK_STINGER=y CONFIG_JOYSTICK_TWIDJOY=y CONFIG_JOYSTICK_ZHENHUA=m # CONFIG_JOYSTICK_DB9 is not set CONFIG_JOYSTICK_GAMECON=y # CONFIG_JOYSTICK_TURBOGRAFX is not set CONFIG_JOYSTICK_AS5011=y # CONFIG_JOYSTICK_JOYDUMP is not set CONFIG_JOYSTICK_WALKERA0701=m CONFIG_JOYSTICK_PSXPAD_SPI=m CONFIG_JOYSTICK_PSXPAD_SPI_FF=y CONFIG_JOYSTICK_QWIIC=y # CONFIG_JOYSTICK_FSIA6B is not set CONFIG_JOYSTICK_SENSEHAT=y CONFIG_INPUT_TABLET=y CONFIG_TABLET_SERIAL_WACOM4=m CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_88PM860X is not set CONFIG_TOUCHSCREEN_ADS7846=m # CONFIG_TOUCHSCREEN_AD7877 is not set CONFIG_TOUCHSCREEN_AD7879=y # CONFIG_TOUCHSCREEN_AD7879_I2C is not set # CONFIG_TOUCHSCREEN_AD7879_SPI is not set # CONFIG_TOUCHSCREEN_ADC is not set # CONFIG_TOUCHSCREEN_ATMEL_MXT is not set CONFIG_TOUCHSCREEN_AUO_PIXCIR=m CONFIG_TOUCHSCREEN_BU21013=m CONFIG_TOUCHSCREEN_BU21029=y CONFIG_TOUCHSCREEN_CY8CTMA140=m CONFIG_TOUCHSCREEN_CY8CTMG110=m CONFIG_TOUCHSCREEN_CYTTSP_CORE=y # CONFIG_TOUCHSCREEN_CYTTSP_I2C is not set CONFIG_TOUCHSCREEN_CYTTSP_SPI=y # CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set CONFIG_TOUCHSCREEN_DA9034=m # CONFIG_TOUCHSCREEN_DA9052 is not set CONFIG_TOUCHSCREEN_DYNAPRO=y CONFIG_TOUCHSCREEN_HAMPSHIRE=m CONFIG_TOUCHSCREEN_EETI=m CONFIG_TOUCHSCREEN_EGALAX_SERIAL=y # CONFIG_TOUCHSCREEN_EXC3000 is not set CONFIG_TOUCHSCREEN_FUJITSU=m CONFIG_TOUCHSCREEN_GOODIX=y CONFIG_TOUCHSCREEN_HIDEEP=y CONFIG_TOUCHSCREEN_HYCON_HY46XX=y CONFIG_TOUCHSCREEN_ILI210X=m CONFIG_TOUCHSCREEN_ILITEK=y # CONFIG_TOUCHSCREEN_IPROC is not set # CONFIG_TOUCHSCREEN_S6SY761 is not set CONFIG_TOUCHSCREEN_GUNZE=y # CONFIG_TOUCHSCREEN_EKTF2127 is not set # CONFIG_TOUCHSCREEN_ELAN is not set # CONFIG_TOUCHSCREEN_ELO is not set CONFIG_TOUCHSCREEN_WACOM_W8001=y CONFIG_TOUCHSCREEN_WACOM_I2C=m # CONFIG_TOUCHSCREEN_MAX11801 is not set CONFIG_TOUCHSCREEN_MCS5000=y CONFIG_TOUCHSCREEN_MMS114=m # CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set CONFIG_TOUCHSCREEN_MSG2638=y # CONFIG_TOUCHSCREEN_MTOUCH is not set CONFIG_TOUCHSCREEN_IMAGIS=m # CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set CONFIG_TOUCHSCREEN_INEXIO=m CONFIG_TOUCHSCREEN_MK712=m CONFIG_TOUCHSCREEN_PENMOUNT=m # CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set # CONFIG_TOUCHSCREEN_RASPBERRYPI_FW is not set # CONFIG_TOUCHSCREEN_MIGOR is not set CONFIG_TOUCHSCREEN_TOUCHRIGHT=m # CONFIG_TOUCHSCREEN_TOUCHWIN is not set CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m CONFIG_TOUCHSCREEN_PIXCIR=y CONFIG_TOUCHSCREEN_WDT87XX_I2C=y # CONFIG_TOUCHSCREEN_WM831X is not set CONFIG_TOUCHSCREEN_MC13783=m CONFIG_TOUCHSCREEN_TOUCHIT213=y CONFIG_TOUCHSCREEN_TSC_SERIO=y CONFIG_TOUCHSCREEN_TSC200X_CORE=m CONFIG_TOUCHSCREEN_TSC2004=m # CONFIG_TOUCHSCREEN_TSC2005 is not set CONFIG_TOUCHSCREEN_TSC2007=y CONFIG_TOUCHSCREEN_TSC2007_IIO=y CONFIG_TOUCHSCREEN_PCAP=m CONFIG_TOUCHSCREEN_RM_TS=m # CONFIG_TOUCHSCREEN_SILEAD is not set CONFIG_TOUCHSCREEN_SIS_I2C=m # CONFIG_TOUCHSCREEN_ST1232 is not set CONFIG_TOUCHSCREEN_STMFTS=y # CONFIG_TOUCHSCREEN_SUN4I is not set CONFIG_TOUCHSCREEN_SURFACE3_SPI=m CONFIG_TOUCHSCREEN_SX8654=y CONFIG_TOUCHSCREEN_TPS6507X=y CONFIG_TOUCHSCREEN_ZET6223=m CONFIG_TOUCHSCREEN_ZFORCE=m # CONFIG_TOUCHSCREEN_COLIBRI_VF50 is not set CONFIG_TOUCHSCREEN_ROHM_BU21023=m # CONFIG_TOUCHSCREEN_IQS5XX is not set CONFIG_TOUCHSCREEN_ZINITIX=y # CONFIG_INPUT_MISC is not set # CONFIG_RMI4_CORE is not set # # Hardware I/O ports # CONFIG_SERIO=y CONFIG_SERIO_SERPORT=m # CONFIG_SERIO_PARKBD is not set CONFIG_SERIO_PCIPS2=m CONFIG_SERIO_LIBPS2=y CONFIG_SERIO_RAW=m # CONFIG_SERIO_ALTERA_PS2 is not set CONFIG_SERIO_PS2MULT=m CONFIG_SERIO_ARC_PS2=y # CONFIG_SERIO_OLPC_APSP is not set # CONFIG_SERIO_SUN4I_PS2 is not set CONFIG_SERIO_GPIO_PS2=m # CONFIG_USERIO is not set CONFIG_GAMEPORT=y CONFIG_GAMEPORT_NS558=y CONFIG_GAMEPORT_L4=y # CONFIG_GAMEPORT_EMU10K1 is not set # CONFIG_GAMEPORT_FM801 is not set # end of Hardware I/O ports # end of Input device support # # Character devices # CONFIG_TTY=y CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y # CONFIG_VT_CONSOLE is not set CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set CONFIG_LDISC_AUTOLOAD=y # # Serial drivers # # # Non-8250 serial port support # # CONFIG_SERIAL_AMBA_PL010 is not set # CONFIG_SERIAL_MESON is not set # CONFIG_SERIAL_CLPS711X is not set # CONFIG_SERIAL_SAMSUNG is not set # CONFIG_SERIAL_TEGRA is not set # CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_MAX310X=m # CONFIG_SERIAL_IMX is not set CONFIG_SERIAL_UARTLITE=m CONFIG_SERIAL_UARTLITE_NR_UARTS=1 # CONFIG_SERIAL_SH_SCI is not set CONFIG_SERIAL_CORE=y # CONFIG_SERIAL_ICOM is not set CONFIG_SERIAL_JSM=y # CONFIG_SERIAL_MSM is not set # CONFIG_SERIAL_VT8500 is not set # CONFIG_SERIAL_OMAP is not set # CONFIG_SERIAL_LANTIQ is not set # CONFIG_SERIAL_SCCNXP is not set CONFIG_SERIAL_SC16IS7XX=y # CONFIG_SERIAL_SC16IS7XX_I2C is not set # CONFIG_SERIAL_SC16IS7XX_SPI is not set # CONFIG_SERIAL_TIMBERDALE is not set # CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set # CONFIG_SERIAL_PCH_UART is not set # CONFIG_SERIAL_MXS_AUART is not set # CONFIG_SERIAL_MPS2_UART is not set # CONFIG_SERIAL_ARC is not set CONFIG_SERIAL_RP2=m CONFIG_SERIAL_RP2_NR_UARTS=32 CONFIG_SERIAL_FSL_LPUART=m # CONFIG_SERIAL_FSL_LPUART_CONSOLE is not set # CONFIG_SERIAL_ST_ASC is not set # CONFIG_SERIAL_MEN_Z135 is not set # CONFIG_SERIAL_STM32 is not set # CONFIG_SERIAL_OWL is not set # CONFIG_SERIAL_RDA is not set # CONFIG_SERIAL_LITEUART is not set # CONFIG_SERIAL_SUNPLUS is not set # end of Serial drivers CONFIG_SERIAL_NONSTANDARD=y CONFIG_MOXA_INTELLIO=m CONFIG_MOXA_SMARTIO=m CONFIG_SYNCLINK_GT=y # CONFIG_N_HDLC is not set CONFIG_NOZOMI=y # CONFIG_NULL_TTY is not set CONFIG_HVC_DRIVER=y CONFIG_RPMSG_TTY=m # CONFIG_SERIAL_DEV_BUS is not set # CONFIG_TTY_PRINTK is not set # CONFIG_PRINTER is not set CONFIG_PPDEV=m CONFIG_VIRTIO_CONSOLE=y CONFIG_IPMI_HANDLER=y CONFIG_IPMI_PLAT_DATA=y # CONFIG_IPMI_PANIC_EVENT is not set CONFIG_IPMI_DEVICE_INTERFACE=m CONFIG_IPMI_SI=y CONFIG_IPMI_SSIF=y CONFIG_IPMI_IPMB=m # CONFIG_IPMI_WATCHDOG is not set # CONFIG_IPMI_POWEROFF is not set # CONFIG_ASPEED_KCS_IPMI_BMC is not set # CONFIG_NPCM7XX_KCS_IPMI_BMC is not set # CONFIG_ASPEED_BT_IPMI_BMC is not set CONFIG_IPMB_DEVICE_INTERFACE=y # CONFIG_HW_RANDOM is not set CONFIG_APPLICOM=m # # PCMCIA character devices # CONFIG_SYNCLINK_CS=y CONFIG_CARDMAN_4000=m CONFIG_CARDMAN_4040=y CONFIG_SCR24X=y # end of PCMCIA character devices CONFIG_DEVMEM=y CONFIG_DEVPORT=y CONFIG_HANGCHECK_TIMER=m CONFIG_TCG_TPM=m # CONFIG_TCG_TIS_SPI is not set # CONFIG_TCG_TIS_I2C is not set # CONFIG_TCG_TIS_SYNQUACER is not set CONFIG_TCG_TIS_I2C_CR50=m CONFIG_TCG_TIS_I2C_ATMEL=m # CONFIG_TCG_TIS_I2C_INFINEON is not set # CONFIG_TCG_TIS_I2C_NUVOTON is not set CONFIG_TCG_VTPM_PROXY=m CONFIG_TCG_TIS_ST33ZP24=m CONFIG_TCG_TIS_ST33ZP24_I2C=m # CONFIG_TCG_TIS_ST33ZP24_SPI is not set # # S/390 character device drivers # # CONFIG_TN3270 is not set CONFIG_TN3215=y CONFIG_TN3215_CONSOLE=y CONFIG_CCW_CONSOLE=y CONFIG_SCLP_TTY=y # CONFIG_SCLP_CONSOLE is not set CONFIG_SCLP_VT220_TTY=y CONFIG_SCLP_VT220_CONSOLE=y CONFIG_HMC_DRV=m CONFIG_SCLP_OFB=y # CONFIG_S390_UV_UAPI is not set # CONFIG_S390_TAPE is not set CONFIG_VMCP=y CONFIG_VMCP_CMA_SIZE=4 CONFIG_MONWRITER=y CONFIG_S390_VMUR=m CONFIG_XILLYBUS_CLASS=y CONFIG_XILLYBUS=y CONFIG_XILLYBUS_PCIE=y CONFIG_RANDOM_TRUST_CPU=y CONFIG_RANDOM_TRUST_BOOTLOADER=y # end of Character devices # # I2C support # CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y # # Multiplexer I2C Chip support # CONFIG_I2C_MUX_GPIO=m CONFIG_I2C_MUX_LTC4306=y CONFIG_I2C_MUX_PCA9541=m # CONFIG_I2C_MUX_PCA954x is not set # CONFIG_I2C_MUX_REG is not set CONFIG_I2C_MUX_MLXCPLD=m # end of Multiplexer I2C Chip support # CONFIG_I2C_HELPER_AUTO is not set CONFIG_I2C_SMBUS=y # # I2C Algorithms # CONFIG_I2C_ALGOBIT=y CONFIG_I2C_ALGOPCF=m # CONFIG_I2C_ALGOPCA is not set # end of I2C Algorithms # # I2C Hardware Bus support # # # PC SMBus host controller drivers # CONFIG_I2C_CCGX_UCSI=y CONFIG_I2C_ALI1535=m # CONFIG_I2C_ALI1563 is not set CONFIG_I2C_ALI15X3=y CONFIG_I2C_AMD756=y CONFIG_I2C_AMD8111=m # CONFIG_I2C_HIX5HD2 is not set # CONFIG_I2C_I801 is not set # CONFIG_I2C_ISCH is not set CONFIG_I2C_PIIX4=y CONFIG_I2C_NFORCE2=y CONFIG_I2C_NVIDIA_GPU=y # CONFIG_I2C_SIS5595 is not set # CONFIG_I2C_SIS630 is not set CONFIG_I2C_SIS96X=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set # # I2C system bus drivers (mostly embedded / system-on-chip) # # CONFIG_I2C_ASPEED is not set # CONFIG_I2C_AT91 is not set # CONFIG_I2C_AXXIA is not set # CONFIG_I2C_BCM_IPROC is not set # CONFIG_I2C_BCM_KONA is not set CONFIG_I2C_BRCMSTB=y # CONFIG_I2C_CADENCE is not set CONFIG_I2C_CBUS_GPIO=m # CONFIG_I2C_DAVINCI is not set CONFIG_I2C_DESIGNWARE_CORE=y CONFIG_I2C_DESIGNWARE_SLAVE=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_DESIGNWARE_PCI=m # CONFIG_I2C_DIGICOLOR is not set # CONFIG_I2C_EG20T is not set CONFIG_I2C_GPIO=m CONFIG_I2C_GPIO_FAULT_INJECTOR=y # CONFIG_I2C_HIGHLANDER is not set # CONFIG_I2C_HISI is not set # CONFIG_I2C_IMG is not set # CONFIG_I2C_IMX is not set # CONFIG_I2C_IMX_LPI2C is not set # CONFIG_I2C_IOP3XX is not set # CONFIG_I2C_JZ4780 is not set # CONFIG_I2C_MT65XX is not set # CONFIG_I2C_MT7621 is not set # CONFIG_I2C_MV64XXX is not set # CONFIG_I2C_MXS is not set # CONFIG_I2C_NPCM is not set CONFIG_I2C_OCORES=y # CONFIG_I2C_OMAP is not set # CONFIG_I2C_OWL is not set # CONFIG_I2C_APPLE is not set # CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_PNX is not set # CONFIG_I2C_PXA is not set # CONFIG_I2C_QCOM_CCI is not set # CONFIG_I2C_QUP is not set # CONFIG_I2C_RIIC is not set # CONFIG_I2C_RZV2M is not set # CONFIG_I2C_S3C2410 is not set # CONFIG_I2C_SH_MOBILE is not set CONFIG_I2C_SIMTEC=m # CONFIG_I2C_ST is not set # CONFIG_I2C_STM32F4 is not set # CONFIG_I2C_STM32F7 is not set # CONFIG_I2C_SYNQUACER is not set # CONFIG_I2C_TEGRA_BPMP is not set # CONFIG_I2C_UNIPHIER is not set # CONFIG_I2C_UNIPHIER_F is not set # CONFIG_I2C_VERSATILE is not set # CONFIG_I2C_WMT is not set # CONFIG_I2C_THUNDERX is not set CONFIG_I2C_XILINX=m # CONFIG_I2C_XLP9XX is not set # CONFIG_I2C_RCAR is not set # # External I2C/SMBus adapter drivers # # CONFIG_I2C_PARPORT is not set CONFIG_I2C_PCI1XXXX=m # CONFIG_I2C_TAOS_EVM is not set # # Other I2C/SMBus bus drivers # # CONFIG_I2C_MLXCPLD is not set CONFIG_I2C_VIRTIO=y # end of I2C Hardware Bus support CONFIG_I2C_STUB=m CONFIG_I2C_SLAVE=y # CONFIG_I2C_SLAVE_EEPROM is not set CONFIG_I2C_SLAVE_TESTUNIT=m # CONFIG_I2C_DEBUG_CORE is not set CONFIG_I2C_DEBUG_ALGO=y # CONFIG_I2C_DEBUG_BUS is not set # end of I2C support CONFIG_I3C=y # CONFIG_CDNS_I3C_MASTER is not set # CONFIG_DW_I3C_MASTER is not set CONFIG_SVC_I3C_MASTER=y CONFIG_MIPI_I3C_HCI=m CONFIG_SPI=y CONFIG_SPI_DEBUG=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y # # SPI Master Controller Drivers # CONFIG_SPI_ALTERA=m CONFIG_SPI_ALTERA_CORE=m # CONFIG_SPI_ALTERA_DFL is not set # CONFIG_SPI_AR934X is not set # CONFIG_SPI_ATH79 is not set # CONFIG_SPI_ARMADA_3700 is not set CONFIG_SPI_AXI_SPI_ENGINE=y # CONFIG_SPI_BCM2835 is not set # CONFIG_SPI_BCM2835AUX is not set # CONFIG_SPI_BCM63XX is not set # CONFIG_SPI_BCM63XX_HSSPI is not set # CONFIG_SPI_BCM_QSPI is not set CONFIG_SPI_BITBANG=y CONFIG_SPI_BUTTERFLY=m # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_XSPI is not set # CONFIG_SPI_CLPS711X is not set CONFIG_SPI_DESIGNWARE=y CONFIG_SPI_DW_DMA=y CONFIG_SPI_DW_PCI=m CONFIG_SPI_DW_MMIO=y # CONFIG_SPI_DW_BT1 is not set # CONFIG_SPI_EP93XX is not set # CONFIG_SPI_FSL_LPSPI is not set # CONFIG_SPI_FSL_QUADSPI is not set # CONFIG_SPI_GXP is not set # CONFIG_SPI_HISI_KUNPENG is not set # CONFIG_SPI_HISI_SFC_V3XX is not set CONFIG_SPI_NXP_FLEXSPI=y CONFIG_SPI_GPIO=y # CONFIG_SPI_IMG_SPFI is not set # CONFIG_SPI_IMX is not set # CONFIG_SPI_INGENIC is not set # CONFIG_SPI_INTEL_PCI is not set # CONFIG_SPI_INTEL_PLATFORM is not set CONFIG_SPI_LM70_LLP=m # CONFIG_SPI_LP8841_RTC is not set # CONFIG_SPI_FSL_DSPI is not set # CONFIG_SPI_MESON_SPIFC is not set CONFIG_SPI_MICROCHIP_CORE=y CONFIG_SPI_MICROCHIP_CORE_QSPI=y # CONFIG_SPI_MT65XX is not set # CONFIG_SPI_MT7621 is not set # CONFIG_SPI_MTK_NOR is not set # CONFIG_SPI_NPCM_PSPI is not set # CONFIG_SPI_LANTIQ_SSC is not set # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_OMAP24XX is not set # CONFIG_SPI_TI_QSPI is not set # CONFIG_SPI_OMAP_100K is not set # CONFIG_SPI_ORION is not set # CONFIG_SPI_PIC32 is not set # CONFIG_SPI_PIC32_SQI is not set CONFIG_SPI_PXA2XX=m CONFIG_SPI_ROCKCHIP=y # CONFIG_SPI_ROCKCHIP_SFC is not set # CONFIG_SPI_RSPI is not set # CONFIG_SPI_QUP is not set # CONFIG_SPI_S3C64XX is not set CONFIG_SPI_SC18IS602=y # CONFIG_SPI_SH is not set # CONFIG_SPI_SH_HSPI is not set CONFIG_SPI_SIFIVE=y # CONFIG_SPI_SLAVE_MT27XX is not set # CONFIG_SPI_SPRD is not set # CONFIG_SPI_SPRD_ADI is not set # CONFIG_SPI_STM32 is not set # CONFIG_SPI_ST_SSC4 is not set # CONFIG_SPI_SUN4I is not set # CONFIG_SPI_SUNPLUS_SP7021 is not set # CONFIG_SPI_SYNQUACER is not set CONFIG_SPI_MXIC=m # CONFIG_SPI_THUNDERX is not set # CONFIG_SPI_TOPCLIFF_PCH is not set CONFIG_SPI_XCOMM=y # CONFIG_SPI_XILINX is not set # CONFIG_SPI_XLP is not set # CONFIG_SPI_XTENSA_XTFPGA is not set # CONFIG_SPI_ZYNQ_QSPI is not set CONFIG_SPI_ZYNQMP_GQSPI=m CONFIG_SPI_AMD=m # # SPI Multiplexer support # CONFIG_SPI_MUX=y # # SPI Protocol Masters # CONFIG_SPI_SPIDEV=y CONFIG_SPI_LOOPBACK_TEST=m # CONFIG_SPI_TLE62X0 is not set CONFIG_SPI_SLAVE=y # CONFIG_SPI_SLAVE_TIME is not set CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y CONFIG_SPI_DYNAMIC=y CONFIG_SPMI=m # CONFIG_SPMI_HISI3670 is not set # CONFIG_SPMI_MSM_PMIC_ARB is not set # CONFIG_SPMI_MTK_PMIF is not set # CONFIG_HSI is not set CONFIG_PPS=y CONFIG_PPS_DEBUG=y # # PPS clients support # CONFIG_PPS_CLIENT_KTIMER=y # CONFIG_PPS_CLIENT_LDISC is not set # CONFIG_PPS_CLIENT_PARPORT is not set # CONFIG_PPS_CLIENT_GPIO is not set # # PPS generators support # # # PTP clock support # CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # # end of PTP clock support CONFIG_PINCTRL=y CONFIG_PINMUX=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set # CONFIG_PINCTRL_AMD is not set # CONFIG_PINCTRL_CY8C95X0 is not set CONFIG_PINCTRL_MCP23S08_I2C=y CONFIG_PINCTRL_MCP23S08_SPI=y CONFIG_PINCTRL_MCP23S08=y CONFIG_PINCTRL_SX150X=y CONFIG_PINCTRL_MADERA=m CONFIG_PINCTRL_CS47L15=y CONFIG_PINCTRL_CS47L35=y CONFIG_PINCTRL_CS47L92=y CONFIG_PINCTRL_CS48L32=y # # Intel pinctrl drivers # # end of Intel pinctrl drivers # # MediaTek pinctrl drivers # # CONFIG_EINT_MTK is not set # end of MediaTek pinctrl drivers # CONFIG_PINCTRL_PXA25X is not set # CONFIG_PINCTRL_PXA27X is not set # CONFIG_PINCTRL_MSM is not set # CONFIG_PINCTRL_LPASS_LPI is not set # # Renesas pinctrl drivers # # CONFIG_PINCTRL_RENESAS is not set # CONFIG_PINCTRL_PFC_EMEV2 is not set # CONFIG_PINCTRL_PFC_R8A77995 is not set # CONFIG_PINCTRL_PFC_R8A7794 is not set # CONFIG_PINCTRL_PFC_R8A77990 is not set # CONFIG_PINCTRL_PFC_R8A7779 is not set # CONFIG_PINCTRL_PFC_R8A7790 is not set # CONFIG_PINCTRL_PFC_R8A77950 is not set # CONFIG_PINCTRL_PFC_R8A77951 is not set # CONFIG_PINCTRL_PFC_R8A7778 is not set # CONFIG_PINCTRL_PFC_R8A7793 is not set # CONFIG_PINCTRL_PFC_R8A7791 is not set # CONFIG_PINCTRL_PFC_R8A77965 is not set # CONFIG_PINCTRL_PFC_R8A77960 is not set # CONFIG_PINCTRL_PFC_R8A77961 is not set # CONFIG_PINCTRL_PFC_R8A779F0 is not set # CONFIG_PINCTRL_PFC_R8A7792 is not set # CONFIG_PINCTRL_PFC_R8A77980 is not set # CONFIG_PINCTRL_PFC_R8A77970 is not set # CONFIG_PINCTRL_PFC_R8A779A0 is not set # CONFIG_PINCTRL_PFC_R8A779G0 is not set # CONFIG_PINCTRL_PFC_R8A7740 is not set # CONFIG_PINCTRL_PFC_R8A73A4 is not set # CONFIG_PINCTRL_PFC_R8A77470 is not set # CONFIG_PINCTRL_PFC_R8A7745 is not set # CONFIG_PINCTRL_PFC_R8A7742 is not set # CONFIG_PINCTRL_PFC_R8A7743 is not set # CONFIG_PINCTRL_PFC_R8A7744 is not set # CONFIG_PINCTRL_PFC_R8A774C0 is not set # CONFIG_PINCTRL_PFC_R8A774E1 is not set # CONFIG_PINCTRL_PFC_R8A774A1 is not set # CONFIG_PINCTRL_PFC_R8A774B1 is not set # CONFIG_PINCTRL_PFC_SH7203 is not set # CONFIG_PINCTRL_PFC_SH7264 is not set # CONFIG_PINCTRL_PFC_SH7269 is not set # CONFIG_PINCTRL_PFC_SH7720 is not set # CONFIG_PINCTRL_PFC_SH7722 is not set # CONFIG_PINCTRL_PFC_SH7734 is not set # CONFIG_PINCTRL_PFC_SH7757 is not set # CONFIG_PINCTRL_PFC_SH7785 is not set # CONFIG_PINCTRL_PFC_SH7786 is not set # CONFIG_PINCTRL_PFC_SH73A0 is not set # CONFIG_PINCTRL_PFC_SH7723 is not set # CONFIG_PINCTRL_PFC_SH7724 is not set # CONFIG_PINCTRL_PFC_SHX3 is not set # end of Renesas pinctrl drivers CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_GPIOLIB_IRQCHIP=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y # # Memory mapped GPIO drivers # # CONFIG_GPIO_ATH79 is not set # CONFIG_GPIO_CLPS711X is not set CONFIG_GPIO_DWAPB=y # CONFIG_GPIO_GENERIC_PLATFORM is not set # CONFIG_GPIO_HISI is not set # CONFIG_GPIO_IOP is not set CONFIG_GPIO_MB86S7X=y # CONFIG_GPIO_MENZ127 is not set # CONFIG_GPIO_MPC8XXX is not set # CONFIG_GPIO_MXC is not set # CONFIG_GPIO_MXS is not set # CONFIG_GPIO_PXA is not set # CONFIG_GPIO_RCAR is not set # CONFIG_GPIO_ROCKCHIP is not set # CONFIG_GPIO_THUNDERX is not set # CONFIG_GPIO_VX855 is not set # CONFIG_GPIO_XGENE_SB is not set # CONFIG_GPIO_XLP is not set CONFIG_GPIO_AMD_FCH=m # CONFIG_GPIO_IDT3243X is not set # end of Memory mapped GPIO drivers # # I2C GPIO expanders # # CONFIG_GPIO_MAX7300 is not set CONFIG_GPIO_MAX732X=m # CONFIG_GPIO_PCA953X is not set CONFIG_GPIO_PCA9570=y # CONFIG_GPIO_PCF857X is not set CONFIG_GPIO_TPIC2810=m # CONFIG_GPIO_TS4900 is not set # end of I2C GPIO expanders # # MFD GPIO expanders # CONFIG_GPIO_ARIZONA=y # CONFIG_GPIO_BD9571MWV is not set # CONFIG_GPIO_DA9052 is not set # CONFIG_GPIO_LP3943 is not set CONFIG_GPIO_LP873X=m # CONFIG_GPIO_MADERA is not set CONFIG_GPIO_PALMAS=y # CONFIG_GPIO_SL28CPLD is not set CONFIG_GPIO_TPS65086=m CONFIG_GPIO_TPS65910=y CONFIG_GPIO_TPS65912=m CONFIG_GPIO_TWL4030=m CONFIG_GPIO_TWL6040=y CONFIG_GPIO_WM831X=y # CONFIG_GPIO_WM8350 is not set CONFIG_GPIO_WM8994=m # end of MFD GPIO expanders # # PCI GPIO expanders # # CONFIG_GPIO_BT8XX is not set # CONFIG_GPIO_MLXBF is not set # CONFIG_GPIO_MLXBF2 is not set # CONFIG_GPIO_ML_IOH is not set # CONFIG_GPIO_PCH is not set CONFIG_GPIO_PCI_IDIO_16=y CONFIG_GPIO_PCIE_IDIO_24=m CONFIG_GPIO_RDC321X=m # end of PCI GPIO expanders # # SPI GPIO expanders # CONFIG_GPIO_MAX3191X=m # CONFIG_GPIO_MAX7301 is not set # CONFIG_GPIO_MC33880 is not set CONFIG_GPIO_PISOSR=y CONFIG_GPIO_XRA1403=y # end of SPI GPIO expanders # # Virtual GPIO drivers # CONFIG_GPIO_AGGREGATOR=y # CONFIG_GPIO_MOCKUP is not set CONFIG_GPIO_VIRTIO=y CONFIG_GPIO_SIM=y # end of Virtual GPIO drivers CONFIG_W1=y # # 1-wire Bus Masters # CONFIG_W1_MASTER_MATROX=y CONFIG_W1_MASTER_DS2482=m # CONFIG_W1_MASTER_MXC is not set CONFIG_W1_MASTER_DS1WM=y # CONFIG_W1_MASTER_GPIO is not set CONFIG_W1_MASTER_SGI=y # end of 1-wire Bus Masters # # 1-wire Slaves # CONFIG_W1_SLAVE_THERM=m CONFIG_W1_SLAVE_SMEM=m CONFIG_W1_SLAVE_DS2405=y CONFIG_W1_SLAVE_DS2408=m CONFIG_W1_SLAVE_DS2408_READBACK=y CONFIG_W1_SLAVE_DS2413=m CONFIG_W1_SLAVE_DS2406=y # CONFIG_W1_SLAVE_DS2423 is not set CONFIG_W1_SLAVE_DS2805=m # CONFIG_W1_SLAVE_DS2430 is not set # CONFIG_W1_SLAVE_DS2431 is not set # CONFIG_W1_SLAVE_DS2433 is not set # CONFIG_W1_SLAVE_DS2438 is not set CONFIG_W1_SLAVE_DS250X=m CONFIG_W1_SLAVE_DS2780=y CONFIG_W1_SLAVE_DS2781=y # CONFIG_W1_SLAVE_DS28E04 is not set # CONFIG_W1_SLAVE_DS28E17 is not set # end of 1-wire Slaves # CONFIG_POWER_RESET is not set CONFIG_POWER_SUPPLY=y CONFIG_POWER_SUPPLY_DEBUG=y CONFIG_POWER_SUPPLY_HWMON=y CONFIG_GENERIC_ADC_BATTERY=m CONFIG_IP5XXX_POWER=y CONFIG_MAX8925_POWER=y CONFIG_WM831X_BACKUP=m CONFIG_WM831X_POWER=m CONFIG_WM8350_POWER=m CONFIG_TEST_POWER=m CONFIG_BATTERY_88PM860X=y CONFIG_CHARGER_ADP5061=y # CONFIG_BATTERY_ACT8945A is not set # CONFIG_BATTERY_CW2015 is not set CONFIG_BATTERY_DS2760=y # CONFIG_BATTERY_DS2780 is not set CONFIG_BATTERY_DS2781=y CONFIG_BATTERY_DS2782=m # CONFIG_BATTERY_SAMSUNG_SDI is not set CONFIG_BATTERY_SBS=y CONFIG_CHARGER_SBS=y CONFIG_MANAGER_SBS=y CONFIG_BATTERY_BQ27XXX=m # CONFIG_BATTERY_BQ27XXX_I2C is not set CONFIG_BATTERY_BQ27XXX_HDQ=m CONFIG_BATTERY_DA9030=y CONFIG_BATTERY_DA9052=m CONFIG_CHARGER_DA9150=m # CONFIG_BATTERY_DA9150 is not set CONFIG_BATTERY_MAX17040=y # CONFIG_BATTERY_MAX17042 is not set CONFIG_BATTERY_MAX1721X=y CONFIG_BATTERY_TWL4030_MADC=m CONFIG_CHARGER_88PM860X=m CONFIG_CHARGER_PCF50633=m CONFIG_BATTERY_RX51=m # CONFIG_CHARGER_MAX8903 is not set CONFIG_CHARGER_TWL4030=m CONFIG_CHARGER_LP8727=y CONFIG_CHARGER_GPIO=m CONFIG_CHARGER_LT3651=m CONFIG_CHARGER_LTC4162L=y # CONFIG_CHARGER_MAX14577 is not set # CONFIG_CHARGER_MAX77693 is not set CONFIG_CHARGER_MAX77976=m CONFIG_CHARGER_BQ2415X=y CONFIG_CHARGER_BQ24257=m CONFIG_CHARGER_BQ24735=m CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ25890=y CONFIG_CHARGER_BQ25980=m CONFIG_CHARGER_BQ256XX=m # CONFIG_CHARGER_TPS65090 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set CONFIG_BATTERY_GOLDFISH=m CONFIG_BATTERY_RT5033=m # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_SC2731 is not set # CONFIG_FUEL_GAUGE_SC27XX is not set CONFIG_CHARGER_BD99954=m # CONFIG_BATTERY_UG3105 is not set CONFIG_HWMON=y CONFIG_HWMON_VID=y CONFIG_HWMON_DEBUG_CHIP=y # # Native drivers # CONFIG_SENSORS_AD7314=y # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set CONFIG_SENSORS_ADM1025=y # CONFIG_SENSORS_ADM1026 is not set CONFIG_SENSORS_ADM1029=y CONFIG_SENSORS_ADM1031=m # CONFIG_SENSORS_ADM1177 is not set CONFIG_SENSORS_ADM9240=m CONFIG_SENSORS_ADT7X10=y CONFIG_SENSORS_ADT7310=y CONFIG_SENSORS_ADT7410=m CONFIG_SENSORS_ADT7411=y # CONFIG_SENSORS_ADT7462 is not set CONFIG_SENSORS_ADT7470=y CONFIG_SENSORS_ADT7475=m # CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ASB100 is not set # CONFIG_SENSORS_ASPEED is not set CONFIG_SENSORS_ATXP1=y # CONFIG_SENSORS_BT1_PVT is not set CONFIG_SENSORS_DS620=m CONFIG_SENSORS_DS1621=m # CONFIG_SENSORS_DA9052_ADC is not set # CONFIG_SENSORS_I5K_AMB is not set # CONFIG_SENSORS_SPARX5 is not set CONFIG_SENSORS_F71805F=y # CONFIG_SENSORS_F71882FG is not set CONFIG_SENSORS_F75375S=y CONFIG_SENSORS_MC13783_ADC=m # CONFIG_SENSORS_FSCHMD is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set CONFIG_SENSORS_G760A=m CONFIG_SENSORS_G762=y CONFIG_SENSORS_HIH6130=y CONFIG_SENSORS_IBMAEM=m CONFIG_SENSORS_IBMPEX=y CONFIG_SENSORS_IIO_HWMON=m CONFIG_SENSORS_IT87=m CONFIG_SENSORS_JC42=m CONFIG_SENSORS_POWR1220=m # CONFIG_SENSORS_LAN966X is not set # CONFIG_SENSORS_LINEAGE is not set CONFIG_SENSORS_LTC2945=y CONFIG_SENSORS_LTC2947=y CONFIG_SENSORS_LTC2947_I2C=m CONFIG_SENSORS_LTC2947_SPI=y # CONFIG_SENSORS_LTC2990 is not set CONFIG_SENSORS_LTC2992=m CONFIG_SENSORS_LTC4151=y CONFIG_SENSORS_LTC4215=m # CONFIG_SENSORS_LTC4222 is not set CONFIG_SENSORS_LTC4245=m # CONFIG_SENSORS_LTC4260 is not set CONFIG_SENSORS_LTC4261=y CONFIG_SENSORS_MAX1111=m CONFIG_SENSORS_MAX127=y CONFIG_SENSORS_MAX16065=y CONFIG_SENSORS_MAX1619=y # CONFIG_SENSORS_MAX1668 is not set CONFIG_SENSORS_MAX197=m CONFIG_SENSORS_MAX31722=m CONFIG_SENSORS_MAX31730=y # CONFIG_SENSORS_MAX31760 is not set CONFIG_SENSORS_MAX6620=m CONFIG_SENSORS_MAX6621=m # CONFIG_SENSORS_MAX6639 is not set CONFIG_SENSORS_MAX6650=y # CONFIG_SENSORS_MAX6697 is not set CONFIG_SENSORS_MAX31790=m # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set CONFIG_SENSORS_TPS23861=m CONFIG_SENSORS_MR75203=y # CONFIG_SENSORS_ADCXX is not set CONFIG_SENSORS_LM63=m CONFIG_SENSORS_LM70=m CONFIG_SENSORS_LM73=m CONFIG_SENSORS_LM75=m # CONFIG_SENSORS_LM77 is not set CONFIG_SENSORS_LM78=m CONFIG_SENSORS_LM80=y CONFIG_SENSORS_LM83=m CONFIG_SENSORS_LM85=y CONFIG_SENSORS_LM87=m CONFIG_SENSORS_LM90=m CONFIG_SENSORS_LM92=y CONFIG_SENSORS_LM93=y # CONFIG_SENSORS_LM95234 is not set # CONFIG_SENSORS_LM95241 is not set CONFIG_SENSORS_LM95245=m CONFIG_SENSORS_PC87360=m CONFIG_SENSORS_PC87427=y # CONFIG_SENSORS_NTC_THERMISTOR is not set CONFIG_SENSORS_NCT6683=y CONFIG_SENSORS_NCT6775_CORE=m CONFIG_SENSORS_NCT6775=m CONFIG_SENSORS_NCT6775_I2C=m CONFIG_SENSORS_NCT7802=m CONFIG_SENSORS_NPCM7XX=y # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set CONFIG_PMBUS=y # CONFIG_SENSORS_PMBUS is not set # CONFIG_SENSORS_ADM1266 is not set CONFIG_SENSORS_ADM1275=m # CONFIG_SENSORS_BEL_PFE is not set CONFIG_SENSORS_BPA_RS600=y CONFIG_SENSORS_DELTA_AHE50DC_FAN=y CONFIG_SENSORS_FSP_3Y=m # CONFIG_SENSORS_IBM_CFFPS is not set CONFIG_SENSORS_DPS920AB=y CONFIG_SENSORS_INSPUR_IPSPS=y # CONFIG_SENSORS_IR35221 is not set # CONFIG_SENSORS_IR36021 is not set CONFIG_SENSORS_IR38064=m # CONFIG_SENSORS_IRPS5401 is not set # CONFIG_SENSORS_ISL68137 is not set CONFIG_SENSORS_LM25066=y CONFIG_SENSORS_LT7182S=m CONFIG_SENSORS_LTC2978=y CONFIG_SENSORS_LTC3815=m # CONFIG_SENSORS_MAX15301 is not set CONFIG_SENSORS_MAX16064=m CONFIG_SENSORS_MAX16601=y # CONFIG_SENSORS_MAX20730 is not set CONFIG_SENSORS_MAX20751=m CONFIG_SENSORS_MAX31785=y CONFIG_SENSORS_MAX34440=m CONFIG_SENSORS_MAX8688=m # CONFIG_SENSORS_MP2888 is not set CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP5023=y CONFIG_SENSORS_PIM4328=m CONFIG_SENSORS_PLI1209BC=m # CONFIG_SENSORS_PM6764TR is not set # CONFIG_SENSORS_PXE1610 is not set CONFIG_SENSORS_Q54SJ108A2=y CONFIG_SENSORS_STPDDC60=y CONFIG_SENSORS_TPS40422=y # CONFIG_SENSORS_TPS53679 is not set # CONFIG_SENSORS_TPS546D24 is not set # CONFIG_SENSORS_UCD9000 is not set CONFIG_SENSORS_UCD9200=y # CONFIG_SENSORS_XDPE152 is not set CONFIG_SENSORS_XDPE122=y CONFIG_SENSORS_ZL6100=y # CONFIG_SENSORS_PWM_FAN is not set # CONFIG_SENSORS_RASPBERRYPI_HWMON is not set # CONFIG_SENSORS_SL28CPLD is not set CONFIG_SENSORS_SBTSI=m # CONFIG_SENSORS_SBRMI is not set CONFIG_SENSORS_SHT15=y CONFIG_SENSORS_SHT21=y # CONFIG_SENSORS_SHT3x is not set CONFIG_SENSORS_SHT4x=y # CONFIG_SENSORS_SHTC1 is not set CONFIG_SENSORS_SIS5595=y CONFIG_SENSORS_SY7636A=y CONFIG_SENSORS_DME1737=y # CONFIG_SENSORS_EMC1403 is not set CONFIG_SENSORS_EMC2103=y # CONFIG_SENSORS_EMC2305 is not set CONFIG_SENSORS_EMC6W201=m # CONFIG_SENSORS_SMSC47M1 is not set CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47B397=y # CONFIG_SENSORS_STTS751 is not set CONFIG_SENSORS_SMM665=m CONFIG_SENSORS_ADC128D818=y CONFIG_SENSORS_ADS7828=y CONFIG_SENSORS_ADS7871=y CONFIG_SENSORS_AMC6821=y # CONFIG_SENSORS_INA209 is not set CONFIG_SENSORS_INA2XX=y CONFIG_SENSORS_INA238=m CONFIG_SENSORS_INA3221=y CONFIG_SENSORS_TC74=y # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP102 is not set CONFIG_SENSORS_TMP103=y # CONFIG_SENSORS_TMP108 is not set CONFIG_SENSORS_TMP401=m CONFIG_SENSORS_TMP421=y CONFIG_SENSORS_TMP464=m CONFIG_SENSORS_TMP513=m CONFIG_SENSORS_VIA686A=y CONFIG_SENSORS_VT1211=m CONFIG_SENSORS_VT8231=m CONFIG_SENSORS_W83773G=m # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set # CONFIG_SENSORS_W83792D is not set CONFIG_SENSORS_W83793=m CONFIG_SENSORS_W83795=m # CONFIG_SENSORS_W83795_FANCTRL is not set CONFIG_SENSORS_W83L785TS=m # CONFIG_SENSORS_W83L786NG is not set CONFIG_SENSORS_W83627HF=y # CONFIG_SENSORS_W83627EHF is not set CONFIG_SENSORS_WM831X=y CONFIG_SENSORS_WM8350=y # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y CONFIG_SSB=y CONFIG_SSB_SPROM=y CONFIG_SSB_PCIHOST_POSSIBLE=y # CONFIG_SSB_PCIHOST is not set CONFIG_SSB_PCMCIAHOST_POSSIBLE=y CONFIG_SSB_PCMCIAHOST=y CONFIG_SSB_SDIOHOST_POSSIBLE=y CONFIG_SSB_SDIOHOST=y CONFIG_SSB_DRIVER_GPIO=y CONFIG_BCMA_POSSIBLE=y # CONFIG_BCMA is not set # # Multifunction device drivers # CONFIG_MFD_CORE=y # CONFIG_MFD_SUN4I_GPADC is not set # CONFIG_MFD_AS3711 is not set # CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_AT91_USART is not set CONFIG_MFD_BCM590XX=y CONFIG_MFD_BD9571MWV=y # CONFIG_MFD_AXP20X_I2C is not set CONFIG_MFD_MADERA=m CONFIG_MFD_MADERA_I2C=m CONFIG_MFD_MADERA_SPI=m CONFIG_MFD_CS47L15=y CONFIG_MFD_CS47L35=y # CONFIG_MFD_CS47L85 is not set # CONFIG_MFD_CS47L90 is not set CONFIG_MFD_CS47L92=y CONFIG_MFD_CS48L32=y # CONFIG_MFD_ASIC3 is not set CONFIG_PMIC_DA903X=y CONFIG_PMIC_DA9052=y CONFIG_MFD_DA9052_SPI=y # CONFIG_MFD_DA9052_I2C is not set # CONFIG_MFD_DA9055 is not set # CONFIG_MFD_DA9062 is not set CONFIG_MFD_DA9063=y CONFIG_MFD_DA9150=m # CONFIG_MFD_ENE_KB3930 is not set # CONFIG_MFD_EXYNOS_LPASS is not set CONFIG_MFD_MC13XXX=y CONFIG_MFD_MC13XXX_SPI=y CONFIG_MFD_MC13XXX_I2C=m # CONFIG_MFD_MP2629 is not set # CONFIG_MFD_MXS_LRADC is not set # CONFIG_MFD_MX25_TSADC is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_HTC_I2CPLD is not set CONFIG_LPC_ICH=m CONFIG_LPC_SCH=m # CONFIG_MFD_IQS62X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set CONFIG_MFD_88PM800=m # CONFIG_MFD_88PM805 is not set CONFIG_MFD_88PM860X=y CONFIG_MFD_MAX14577=y # CONFIG_MFD_MAX77620 is not set # CONFIG_MFD_MAX77650 is not set # CONFIG_MFD_MAX77686 is not set CONFIG_MFD_MAX77693=y # CONFIG_MFD_MAX77714 is not set # CONFIG_MFD_MAX77843 is not set CONFIG_MFD_MAX8907=y CONFIG_MFD_MAX8925=y # CONFIG_MFD_MAX8997 is not set CONFIG_MFD_MAX8998=y CONFIG_MFD_MT6360=m CONFIG_MFD_MT6370=m CONFIG_MFD_MT6397=y # CONFIG_MFD_MENF21BMC is not set CONFIG_MFD_OCELOT=y CONFIG_EZX_PCAP=y # CONFIG_MFD_CPCAP is not set # CONFIG_MFD_NTXEC is not set # CONFIG_MFD_RETU is not set CONFIG_MFD_PCF50633=y # CONFIG_PCF50633_ADC is not set CONFIG_PCF50633_GPIO=y # CONFIG_MFD_PM8XXX is not set CONFIG_MFD_SY7636A=y CONFIG_MFD_RDC321X=y # CONFIG_MFD_RT4831 is not set CONFIG_MFD_RT5033=y # CONFIG_MFD_RT5120 is not set # CONFIG_MFD_RC5T583 is not set # CONFIG_MFD_SEC_CORE is not set CONFIG_MFD_SI476X_CORE=y CONFIG_MFD_SIMPLE_MFD_I2C=y # CONFIG_MFD_SL28CPLD is not set # CONFIG_MFD_SM501 is not set CONFIG_MFD_SKY81452=y # CONFIG_MFD_SC27XX_PMIC is not set # CONFIG_ABX500_CORE is not set # CONFIG_MFD_SUN6I_PRCM is not set CONFIG_MFD_SYSCON=y CONFIG_MFD_TI_AM335X_TSCADC=m CONFIG_MFD_LP3943=y # CONFIG_MFD_LP8788 is not set CONFIG_MFD_TI_LMU=y CONFIG_MFD_PALMAS=y # CONFIG_TPS6105X is not set # CONFIG_TPS65010 is not set # CONFIG_TPS6507X is not set CONFIG_MFD_TPS65086=m CONFIG_MFD_TPS65090=y CONFIG_MFD_TI_LP873X=m # CONFIG_MFD_TPS6586X is not set CONFIG_MFD_TPS65910=y CONFIG_MFD_TPS65912=m # CONFIG_MFD_TPS65912_I2C is not set CONFIG_MFD_TPS65912_SPI=m CONFIG_TWL4030_CORE=y # CONFIG_MFD_TWL4030_AUDIO is not set CONFIG_TWL6040_CORE=y CONFIG_MFD_WL1273_CORE=m CONFIG_MFD_LM3533=m # CONFIG_MFD_TIMBERDALE is not set CONFIG_MFD_TQMX86=y CONFIG_MFD_VX855=y CONFIG_MFD_ARIZONA=y CONFIG_MFD_ARIZONA_I2C=m CONFIG_MFD_ARIZONA_SPI=y CONFIG_MFD_CS47L24=y CONFIG_MFD_WM5102=y # CONFIG_MFD_WM5110 is not set # CONFIG_MFD_WM8997 is not set # CONFIG_MFD_WM8998 is not set # CONFIG_MFD_WM8400 is not set CONFIG_MFD_WM831X=y CONFIG_MFD_WM831X_I2C=y CONFIG_MFD_WM831X_SPI=y CONFIG_MFD_WM8350=y CONFIG_MFD_WM8350_I2C=y CONFIG_MFD_WM8994=m # CONFIG_MFD_STW481X is not set # CONFIG_MFD_STM32_LPTIMER is not set # CONFIG_MFD_STM32_TIMERS is not set # CONFIG_MFD_STMFX is not set # CONFIG_MFD_WCD934X is not set CONFIG_MFD_ATC260X=m CONFIG_MFD_ATC260X_I2C=m # CONFIG_MFD_KHADAS_MCU is not set # CONFIG_MFD_ACER_A500_EC is not set # CONFIG_MFD_INTEL_M10_BMC is not set # end of Multifunction device drivers # CONFIG_REGULATOR is not set CONFIG_RC_CORE=m # CONFIG_LIRC is not set # CONFIG_RC_MAP is not set CONFIG_RC_DECODERS=y CONFIG_IR_IMON_DECODER=m # CONFIG_IR_JVC_DECODER is not set CONFIG_IR_MCE_KBD_DECODER=m CONFIG_IR_NEC_DECODER=m # CONFIG_IR_RC5_DECODER is not set # CONFIG_IR_RC6_DECODER is not set # CONFIG_IR_RCMM_DECODER is not set CONFIG_IR_SANYO_DECODER=m # CONFIG_IR_SHARP_DECODER is not set CONFIG_IR_SONY_DECODER=m CONFIG_IR_XMP_DECODER=m # CONFIG_RC_DEVICES is not set # # CEC support # # CONFIG_MEDIA_CEC_SUPPORT is not set # end of CEC support # CONFIG_MEDIA_SUPPORT is not set # # Graphics support # CONFIG_APERTURE_HELPERS=y # CONFIG_IMX_IPUV3_CORE is not set # CONFIG_DRM is not set CONFIG_DRM_DEBUG_MODESET_LOCK=y # # ARM devices # # end of ARM devices # # Frame buffer Devices # CONFIG_FB_CMDLINE=y CONFIG_FB_NOTIFY=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_DDC=y CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y CONFIG_FB_SYS_FILLRECT=y CONFIG_FB_SYS_COPYAREA=y CONFIG_FB_SYS_IMAGEBLIT=y CONFIG_FB_FOREIGN_ENDIAN=y # CONFIG_FB_BOTH_ENDIAN is not set CONFIG_FB_BIG_ENDIAN=y # CONFIG_FB_LITTLE_ENDIAN is not set CONFIG_FB_SYS_FOPS=y CONFIG_FB_DEFERRED_IO=y CONFIG_FB_SVGALIB=m CONFIG_FB_BACKLIGHT=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y # # Frame buffer hardware drivers # CONFIG_FB_CIRRUS=y # CONFIG_FB_PM2 is not set # CONFIG_FB_CLPS711X is not set # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_ARC is not set # CONFIG_FB_CONTROL is not set CONFIG_FB_ASILIANT=y CONFIG_FB_IMSTT=y # CONFIG_FB_GBE is not set # CONFIG_FB_PVR2 is not set CONFIG_FB_OPENCORES=y CONFIG_FB_S1D13XXX=y # CONFIG_FB_NVIDIA is not set CONFIG_FB_RIVA=m CONFIG_FB_RIVA_I2C=y # CONFIG_FB_RIVA_DEBUG is not set # CONFIG_FB_RIVA_BACKLIGHT is not set # CONFIG_FB_I740 is not set # CONFIG_FB_MATROX is not set # CONFIG_FB_RADEON is not set CONFIG_FB_ATY128=m # CONFIG_FB_ATY128_BACKLIGHT is not set CONFIG_FB_ATY=y CONFIG_FB_ATY_CT=y # CONFIG_FB_ATY_GENERIC_LCD is not set CONFIG_FB_ATY_GX=y CONFIG_FB_ATY_BACKLIGHT=y CONFIG_FB_S3=m CONFIG_FB_S3_DDC=y CONFIG_FB_SAVAGE=m CONFIG_FB_SAVAGE_I2C=y CONFIG_FB_SAVAGE_ACCEL=y # CONFIG_FB_SIS is not set # CONFIG_FB_VIA is not set CONFIG_FB_NEOMAGIC=y # CONFIG_FB_KYRO is not set CONFIG_FB_3DFX=y CONFIG_FB_3DFX_ACCEL=y # CONFIG_FB_3DFX_I2C is not set CONFIG_FB_VOODOO1=m # CONFIG_FB_VT8623 is not set CONFIG_FB_TRIDENT=y CONFIG_FB_ARK=m CONFIG_FB_PM3=y CONFIG_FB_CARMINE=m CONFIG_FB_CARMINE_DRAM_EVAL=y # CONFIG_CARMINE_DRAM_CUSTOM is not set # CONFIG_FB_WM8505 is not set # CONFIG_FB_W100 is not set # CONFIG_FB_TMIO is not set CONFIG_FB_IBM_GXT4500=m # CONFIG_FB_GOLDFISH is not set CONFIG_FB_VIRTUAL=y # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set # CONFIG_FB_BROADSHEET is not set CONFIG_FB_SIMPLE=y CONFIG_FB_SSD1307=y CONFIG_FB_SM712=y # CONFIG_MMP_DISP is not set # end of Frame buffer Devices # # Backlight & LCD device support # CONFIG_LCD_CLASS_DEVICE=y # CONFIG_LCD_L4F00242T03 is not set CONFIG_LCD_LMS283GF05=m CONFIG_LCD_LTV350QV=y # CONFIG_LCD_ILI922X is not set CONFIG_LCD_ILI9320=y # CONFIG_LCD_TDO24M is not set CONFIG_LCD_VGG2432A4=y CONFIG_LCD_PLATFORM=m CONFIG_LCD_AMS369FG06=m CONFIG_LCD_LMS501KF03=y CONFIG_LCD_HX8357=y CONFIG_LCD_OTM3225A=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_KTD253=y CONFIG_BACKLIGHT_LM3533=m # CONFIG_BACKLIGHT_OMAP1 is not set CONFIG_BACKLIGHT_PWM=m # CONFIG_BACKLIGHT_DA903X is not set # CONFIG_BACKLIGHT_DA9052 is not set # CONFIG_BACKLIGHT_MAX8925 is not set CONFIG_BACKLIGHT_MT6370=m CONFIG_BACKLIGHT_QCOM_WLED=y # CONFIG_BACKLIGHT_WM831X is not set # CONFIG_BACKLIGHT_ADP8860 is not set CONFIG_BACKLIGHT_ADP8870=m # CONFIG_BACKLIGHT_88PM860X is not set CONFIG_BACKLIGHT_PCF50633=y CONFIG_BACKLIGHT_LM3630A=m CONFIG_BACKLIGHT_LM3639=y CONFIG_BACKLIGHT_LP855X=y CONFIG_BACKLIGHT_PANDORA=m CONFIG_BACKLIGHT_SKY81452=y CONFIG_BACKLIGHT_GPIO=m CONFIG_BACKLIGHT_LV5207LP=y # CONFIG_BACKLIGHT_BD6107 is not set CONFIG_BACKLIGHT_ARCXCNN=y # end of Backlight & LCD device support CONFIG_VGASTATE=y # # Console display driver support # CONFIG_DUMMY_CONSOLE=y CONFIG_DUMMY_CONSOLE_COLUMNS=80 CONFIG_DUMMY_CONSOLE_ROWS=25 # CONFIG_FRAMEBUFFER_CONSOLE is not set # end of Console display driver support # CONFIG_LOGO is not set # end of Graphics support # CONFIG_SOUND is not set # # HID support # # CONFIG_HID is not set # # I2C HID support # # end of I2C HID support # # Intel ISH HID support # # end of Intel ISH HID support # end of HID support CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y # CONFIG_MMC_BLOCK is not set # CONFIG_SDIO_UART is not set # CONFIG_MMC_TEST is not set # # MMC/SD/SDIO Host Controller Drivers # CONFIG_MMC_DEBUG=y # CONFIG_MMC_SDHCI is not set # CONFIG_MMC_MOXART is not set # CONFIG_MMC_OMAP_HS is not set CONFIG_MMC_ALCOR=y CONFIG_MMC_TIFM_SD=y # CONFIG_MMC_DAVINCI is not set # CONFIG_MMC_SPI is not set # CONFIG_MMC_S3C is not set CONFIG_MMC_SDRICOH_CS=m # CONFIG_MMC_TMIO is not set # CONFIG_MMC_SDHI is not set # CONFIG_MMC_CB710 is not set # CONFIG_MMC_VIA_SDMMC is not set # CONFIG_MMC_DW is not set # CONFIG_MMC_SH_MMCIF is not set CONFIG_MMC_USDHI6ROL0=m # CONFIG_MMC_REALTEK_PCI is not set CONFIG_MMC_CQHCI=y CONFIG_MMC_HSQ=m CONFIG_MMC_TOSHIBA_PCI=m # CONFIG_MMC_BCM2835 is not set # CONFIG_MMC_OWL is not set # CONFIG_MMC_LITEX is not set CONFIG_SCSI_UFSHCD=m # CONFIG_SCSI_UFS_BSG is not set # CONFIG_SCSI_UFS_HPB is not set # CONFIG_SCSI_UFS_FAULT_INJECTION is not set # CONFIG_SCSI_UFS_HWMON is not set CONFIG_SCSI_UFSHCD_PCI=m CONFIG_SCSI_UFS_DWC_TC_PCI=m CONFIG_SCSI_UFSHCD_PLATFORM=m # CONFIG_SCSI_UFS_CDNS_PLATFORM is not set # CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set # CONFIG_SCSI_UFS_HISI is not set # CONFIG_SCSI_UFS_RENESAS is not set # CONFIG_SCSI_UFS_EXYNOS is not set CONFIG_MEMSTICK=y # CONFIG_MEMSTICK_DEBUG is not set # # MemoryStick drivers # # CONFIG_MEMSTICK_UNSAFE_RESUME is not set CONFIG_MSPRO_BLOCK=m # CONFIG_MS_BLOCK is not set # # MemoryStick Host Controller Drivers # CONFIG_MEMSTICK_TIFM_MS=m # CONFIG_MEMSTICK_JMICRON_38X is not set # CONFIG_MEMSTICK_R592 is not set CONFIG_MEMSTICK_REALTEK_PCI=m CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y # CONFIG_LEDS_CLASS_FLASH is not set CONFIG_LEDS_CLASS_MULTICOLOR=m # CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set # # LED drivers # CONFIG_LEDS_88PM860X=y # CONFIG_LEDS_ARIEL is not set CONFIG_LEDS_LM3530=m CONFIG_LEDS_LM3532=m CONFIG_LEDS_LM3533=m # CONFIG_LEDS_LM3642 is not set # CONFIG_LEDS_MT6323 is not set # CONFIG_LEDS_S3C24XX is not set # CONFIG_LEDS_COBALT_QUBE is not set # CONFIG_LEDS_COBALT_RAQ is not set CONFIG_LEDS_PCA9532=m CONFIG_LEDS_PCA9532_GPIO=y # CONFIG_LEDS_GPIO is not set # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_LP3952 is not set CONFIG_LEDS_LP50XX=m # CONFIG_LEDS_PCA955X is not set CONFIG_LEDS_PCA963X=m CONFIG_LEDS_WM831X_STATUS=y # CONFIG_LEDS_WM8350 is not set CONFIG_LEDS_DA903X=y CONFIG_LEDS_DA9052=y # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_PWM is not set CONFIG_LEDS_BD2802=y # CONFIG_LEDS_LT3593 is not set CONFIG_LEDS_MC13783=m CONFIG_LEDS_NS2=y # CONFIG_LEDS_TCA6507 is not set CONFIG_LEDS_TLC591XX=y CONFIG_LEDS_LM355x=y # CONFIG_LEDS_OT200 is not set CONFIG_LEDS_IS31FL319X=m # # LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) # CONFIG_LEDS_BLINKM=m CONFIG_LEDS_MLXREG=m CONFIG_LEDS_USER=y CONFIG_LEDS_TI_LMU_COMMON=y CONFIG_LEDS_LM36274=y # CONFIG_LEDS_IP30 is not set # # Flash and Torch LED drivers # # # RGB LED drivers # CONFIG_LEDS_PWM_MULTICOLOR=m # # LED Triggers # # CONFIG_LEDS_TRIGGERS is not set # # Simple LED drivers # # CONFIG_ACCESSIBILITY is not set # CONFIG_DMADEVICES is not set # # DMABUF options # CONFIG_SYNC_FILE=y CONFIG_SW_SYNC=y # CONFIG_UDMABUF is not set CONFIG_DMABUF_MOVE_NOTIFY=y CONFIG_DMABUF_DEBUG=y # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_SYSFS_STATS=y # CONFIG_DMABUF_HEAPS_SYSTEM is not set # end of DMABUF options CONFIG_AUXDISPLAY=y CONFIG_CHARLCD=m CONFIG_LINEDISP=m CONFIG_HD44780_COMMON=m # CONFIG_HD44780 is not set CONFIG_IMG_ASCII_LCD=m # CONFIG_HT16K33 is not set # CONFIG_LCD2S is not set CONFIG_PARPORT_PANEL=m CONFIG_PANEL_PARPORT=0 CONFIG_PANEL_PROFILE=5 CONFIG_PANEL_CHANGE_MESSAGE=y CONFIG_PANEL_BOOT_MESSAGE="" # CONFIG_CHARLCD_BL_OFF is not set CONFIG_CHARLCD_BL_ON=y # CONFIG_CHARLCD_BL_FLASH is not set # CONFIG_PANEL is not set CONFIG_UIO=y # CONFIG_UIO_CIF is not set CONFIG_UIO_PDRV_GENIRQ=y CONFIG_UIO_DMEM_GENIRQ=m # CONFIG_UIO_AEC is not set CONFIG_UIO_SERCOS3=m # CONFIG_UIO_PCI_GENERIC is not set CONFIG_UIO_NETX=m CONFIG_UIO_PRUSS=m CONFIG_UIO_MF624=m # CONFIG_UIO_DFL is not set CONFIG_VFIO=y CONFIG_VFIO_IOMMU_TYPE1=y CONFIG_VFIO_VIRQFD=y CONFIG_VFIO_NOIOMMU=y CONFIG_VFIO_PCI_CORE=y CONFIG_VFIO_PCI=y # CONFIG_VFIO_PLATFORM is not set # CONFIG_VFIO_MDEV is not set CONFIG_IRQ_BYPASS_MANAGER=y # CONFIG_VIRT_DRIVERS is not set CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO=y CONFIG_VIRTIO_PCI_LIB=m CONFIG_VIRTIO_MENU=y CONFIG_VIRTIO_PCI=m # CONFIG_VIRTIO_PCI_LEGACY is not set CONFIG_VIRTIO_PMEM=m # CONFIG_VIRTIO_BALLOON is not set CONFIG_VIRTIO_INPUT=y # CONFIG_VIRTIO_MMIO is not set CONFIG_VHOST_MENU=y CONFIG_VHOST_CROSS_ENDIAN_LEGACY=y # # Microsoft Hyper-V guest support # # end of Microsoft Hyper-V guest support CONFIG_GREYBUS=m # CONFIG_COMEDI is not set # CONFIG_STAGING is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set # CONFIG_OLPC_XO175 is not set CONFIG_SURFACE_PLATFORMS=y # CONFIG_COMMON_CLK is not set # CONFIG_HWSPINLOCK is not set # # Clock Source drivers # # CONFIG_BCM2835_TIMER is not set # CONFIG_BCM_KONA_TIMER is not set # CONFIG_DAVINCI_TIMER is not set # CONFIG_DIGICOLOR_TIMER is not set # CONFIG_OMAP_DM_TIMER is not set # CONFIG_DW_APB_TIMER is not set # CONFIG_FTTMR010_TIMER is not set # CONFIG_IXP4XX_TIMER is not set # CONFIG_MESON6_TIMER is not set # CONFIG_OWL_TIMER is not set # CONFIG_RDA_TIMER is not set # CONFIG_SUN4I_TIMER is not set # CONFIG_TEGRA_TIMER is not set # CONFIG_VT8500_TIMER is not set # CONFIG_NPCM7XX_TIMER is not set # CONFIG_ASM9260_TIMER is not set # CONFIG_CLKSRC_DBX500_PRCMU is not set # CONFIG_CLPS711X_TIMER is not set # CONFIG_MXS_TIMER is not set # CONFIG_NSPIRE_TIMER is not set # CONFIG_INTEGRATOR_AP_TIMER is not set # CONFIG_CLKSRC_PISTACHIO is not set # CONFIG_CLKSRC_STM32_LP is not set # CONFIG_ARMV7M_SYSTICK is not set # CONFIG_ATMEL_PIT is not set # CONFIG_ATMEL_ST is not set # CONFIG_CLKSRC_SAMSUNG_PWM is not set # CONFIG_FSL_FTM_TIMER is not set # CONFIG_OXNAS_RPS_TIMER is not set # CONFIG_MTK_TIMER is not set # CONFIG_SPRD_TIMER is not set # CONFIG_SH_TIMER_CMT is not set # CONFIG_SH_TIMER_MTU2 is not set # CONFIG_RENESAS_OSTM is not set # CONFIG_SH_TIMER_TMU is not set # CONFIG_EM_TIMER_STI is not set # CONFIG_CLKSRC_PXA is not set # CONFIG_TIMER_IMX_SYS_CTR is not set # CONFIG_CLKSRC_ST_LPC is not set # CONFIG_GXP_TIMER is not set # CONFIG_MSC313E_TIMER is not set # CONFIG_MICROCHIP_PIT64B is not set # end of Clock Source drivers # CONFIG_MAILBOX is not set CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y # # Generic IOMMU Pagetable Support # # CONFIG_IOMMU_IO_PGTABLE_LPAE is not set # CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set # CONFIG_IOMMU_IO_PGTABLE_DART is not set # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set CONFIG_IOMMU_DEFAULT_DMA_STRICT=y # CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set # CONFIG_OMAP_IOMMU is not set # CONFIG_ROCKCHIP_IOMMU is not set # CONFIG_SUN50I_IOMMU is not set # CONFIG_IPMMU_VMSA is not set # CONFIG_APPLE_DART is not set # CONFIG_ARM_SMMU is not set CONFIG_S390_IOMMU=y # CONFIG_S390_CCW_IOMMU is not set # CONFIG_S390_AP_IOMMU is not set # CONFIG_MTK_IOMMU is not set # CONFIG_QCOM_IOMMU is not set # CONFIG_SPRD_IOMMU is not set # # Remoteproc drivers # # CONFIG_REMOTEPROC is not set # end of Remoteproc drivers # # Rpmsg drivers # CONFIG_RPMSG=m CONFIG_RPMSG_CTRL=m CONFIG_RPMSG_NS=m CONFIG_RPMSG_VIRTIO=m # end of Rpmsg drivers # # SOC (System On Chip) specific Drivers # # # Amlogic SoC drivers # # CONFIG_MESON_CANVAS is not set # CONFIG_MESON_CLK_MEASURE is not set # CONFIG_MESON_GX_SOCINFO is not set # CONFIG_MESON_MX_SOCINFO is not set # end of Amlogic SoC drivers # # Apple SoC drivers # # CONFIG_APPLE_SART is not set # end of Apple SoC drivers # # ASPEED SoC drivers # # CONFIG_ASPEED_LPC_CTRL is not set # CONFIG_ASPEED_LPC_SNOOP is not set # CONFIG_ASPEED_UART_ROUTING is not set # CONFIG_ASPEED_P2A_CTRL is not set # CONFIG_ASPEED_SOCINFO is not set # end of ASPEED SoC drivers # CONFIG_AT91_SOC_ID is not set # CONFIG_AT91_SOC_SFR is not set # # Broadcom SoC drivers # # CONFIG_SOC_BCM63XX is not set # CONFIG_SOC_BRCMSTB is not set # end of Broadcom SoC drivers # # NXP/Freescale QorIQ SoC drivers # # end of NXP/Freescale QorIQ SoC drivers # # fujitsu SoC drivers # # end of fujitsu SoC drivers # # i.MX SoC drivers # # CONFIG_SOC_IMX8M is not set # CONFIG_SOC_IMX9 is not set # end of i.MX SoC drivers # # IXP4xx SoC drivers # # CONFIG_IXP4XX_QMGR is not set # CONFIG_IXP4XX_NPE is not set # end of IXP4xx SoC drivers # # Enable LiteX SoC Builder specific drivers # # CONFIG_LITEX_SOC_CONTROLLER is not set # end of Enable LiteX SoC Builder specific drivers # # MediaTek SoC drivers # # CONFIG_MTK_CMDQ is not set # CONFIG_MTK_DEVAPC is not set # CONFIG_MTK_INFRACFG is not set # CONFIG_MTK_MMSYS is not set # end of MediaTek SoC drivers # # Qualcomm SoC drivers # # CONFIG_QCOM_GENI_SE is not set # CONFIG_QCOM_GSBI is not set # CONFIG_QCOM_LLCC is not set # CONFIG_QCOM_RPMH is not set # CONFIG_QCOM_SMD_RPM is not set # CONFIG_QCOM_SPM is not set # CONFIG_QCOM_WCNSS_CTRL is not set # CONFIG_QCOM_ICC_BWMON is not set # end of Qualcomm SoC drivers # CONFIG_SOC_RENESAS is not set # CONFIG_ROCKCHIP_GRF is not set # CONFIG_SOC_SAMSUNG is not set # CONFIG_SOC_TI is not set # CONFIG_UX500_SOC_ID is not set # # Xilinx SoC drivers # # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers CONFIG_PM_DEVFREQ=y # # DEVFREQ Governors # CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=m CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_DEVFREQ_GOV_PASSIVE=y # # DEVFREQ Drivers # # CONFIG_ARM_EXYNOS_BUS_DEVFREQ is not set # CONFIG_ARM_IMX_BUS_DEVFREQ is not set # CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set CONFIG_PM_DEVFREQ_EVENT=y # CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP is not set # CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU is not set # CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI is not set # CONFIG_EXTCON is not set CONFIG_MEMORY=y # CONFIG_BRCMSTB_DPFE is not set # CONFIG_BRCMSTB_MEMC is not set # CONFIG_BT1_L2_CTL is not set # CONFIG_TI_EMIF is not set CONFIG_FPGA_DFL_EMIF=m # CONFIG_FSL_CORENET_CF is not set # CONFIG_FSL_IFC is not set # CONFIG_MTK_SMI is not set # CONFIG_DA8XX_DDRCTL is not set # CONFIG_RENESAS_RPCIF is not set # CONFIG_STM32_FMC2_EBI is not set # CONFIG_SAMSUNG_MC is not set CONFIG_IIO=y CONFIG_IIO_BUFFER=y CONFIG_IIO_BUFFER_CB=y CONFIG_IIO_BUFFER_DMA=m CONFIG_IIO_BUFFER_DMAENGINE=m CONFIG_IIO_BUFFER_HW_CONSUMER=y CONFIG_IIO_KFIFO_BUF=y CONFIG_IIO_TRIGGERED_BUFFER=y CONFIG_IIO_CONFIGFS=m CONFIG_IIO_TRIGGER=y CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 CONFIG_IIO_SW_DEVICE=m # CONFIG_IIO_SW_TRIGGER is not set # CONFIG_IIO_TRIGGERED_EVENT is not set # # Accelerometers # # CONFIG_ADIS16201 is not set CONFIG_ADIS16209=m CONFIG_ADXL313=m CONFIG_ADXL313_I2C=m # CONFIG_ADXL313_SPI is not set # CONFIG_ADXL345_I2C is not set # CONFIG_ADXL345_SPI is not set CONFIG_ADXL355=y CONFIG_ADXL355_I2C=m CONFIG_ADXL355_SPI=y # CONFIG_ADXL367_SPI is not set # CONFIG_ADXL367_I2C is not set CONFIG_ADXL372=y CONFIG_ADXL372_SPI=m CONFIG_ADXL372_I2C=y CONFIG_BMA180=m # CONFIG_BMA220 is not set # CONFIG_BMA400 is not set # CONFIG_BMC150_ACCEL is not set CONFIG_BMI088_ACCEL=y CONFIG_BMI088_ACCEL_SPI=y # CONFIG_DA280 is not set CONFIG_DA311=m CONFIG_DMARD06=m CONFIG_DMARD09=y # CONFIG_DMARD10 is not set CONFIG_FXLS8962AF=y CONFIG_FXLS8962AF_I2C=m CONFIG_FXLS8962AF_SPI=y CONFIG_KXSD9=y CONFIG_KXSD9_SPI=m # CONFIG_KXSD9_I2C is not set # CONFIG_KXCJK1013 is not set CONFIG_MC3230=y # CONFIG_MMA7455_I2C is not set # CONFIG_MMA7455_SPI is not set CONFIG_MMA7660=m CONFIG_MMA8452=y CONFIG_MMA9551_CORE=m CONFIG_MMA9551=m # CONFIG_MMA9553 is not set CONFIG_MSA311=m CONFIG_MXC4005=m # CONFIG_MXC6255 is not set # CONFIG_SCA3000 is not set # CONFIG_SCA3300 is not set CONFIG_STK8312=y CONFIG_STK8BA50=m # end of Accelerometers # # Analog to digital converters # CONFIG_AD_SIGMA_DELTA=y CONFIG_AD7091R5=m CONFIG_AD7124=m CONFIG_AD7192=y CONFIG_AD7266=y CONFIG_AD7280=m CONFIG_AD7291=y # CONFIG_AD7292 is not set CONFIG_AD7298=y # CONFIG_AD7476 is not set CONFIG_AD7606=m CONFIG_AD7606_IFACE_PARALLEL=m # CONFIG_AD7606_IFACE_SPI is not set CONFIG_AD7766=m CONFIG_AD7768_1=m CONFIG_AD7780=m CONFIG_AD7791=y CONFIG_AD7793=y # CONFIG_AD7887 is not set # CONFIG_AD7923 is not set CONFIG_AD7949=y CONFIG_AD799X=y # CONFIG_AT91_SAMA5D2_ADC is not set # CONFIG_BCM_IPROC_ADC is not set # CONFIG_BERLIN2_ADC is not set CONFIG_DA9150_GPADC=m # CONFIG_ENVELOPE_DETECTOR is not set # CONFIG_HI8435 is not set # CONFIG_HX711 is not set # CONFIG_INGENIC_ADC is not set # CONFIG_IMX7D_ADC is not set # CONFIG_IMX8QXP_ADC is not set # CONFIG_LPC18XX_ADC is not set # CONFIG_LPC32XX_ADC is not set CONFIG_LTC2471=y CONFIG_LTC2485=y CONFIG_LTC2496=m CONFIG_LTC2497=m CONFIG_MAX1027=m CONFIG_MAX11100=m # CONFIG_MAX1118 is not set # CONFIG_MAX11205 is not set CONFIG_MAX1241=y # CONFIG_MAX1363 is not set CONFIG_MAX9611=m CONFIG_MCP320X=m CONFIG_MCP3422=m # CONFIG_MCP3911 is not set # CONFIG_MEDIATEK_MT6360_ADC is not set # CONFIG_MEDIATEK_MT6577_AUXADC is not set CONFIG_MEN_Z188_ADC=y CONFIG_NAU7802=m # CONFIG_NPCM_ADC is not set CONFIG_PALMAS_GPADC=y CONFIG_QCOM_VADC_COMMON=m # CONFIG_QCOM_SPMI_IADC is not set CONFIG_QCOM_SPMI_VADC=m # CONFIG_QCOM_SPMI_ADC5 is not set # CONFIG_RCAR_GYRO_ADC is not set CONFIG_RICHTEK_RTQ6056=m # CONFIG_RZG2L_ADC is not set # CONFIG_SC27XX_ADC is not set # CONFIG_SPEAR_ADC is not set CONFIG_SD_ADC_MODULATOR=m # CONFIG_STM32_DFSDM_CORE is not set # CONFIG_STM32_DFSDM_ADC is not set # CONFIG_TI_ADC081C is not set # CONFIG_TI_ADC0832 is not set CONFIG_TI_ADC084S021=y CONFIG_TI_ADC12138=y CONFIG_TI_ADC108S102=m # CONFIG_TI_ADC128S052 is not set CONFIG_TI_ADC161S626=m # CONFIG_TI_ADS1015 is not set CONFIG_TI_ADS7950=m CONFIG_TI_ADS8344=m # CONFIG_TI_ADS8688 is not set CONFIG_TI_ADS124S08=y CONFIG_TI_ADS131E08=m # CONFIG_TI_AM335X_ADC is not set CONFIG_TI_TLC4541=y CONFIG_TI_TSC2046=y CONFIG_TWL4030_MADC=m # CONFIG_TWL6030_GPADC is not set # CONFIG_VF610_ADC is not set CONFIG_XILINX_XADC=y # CONFIG_XILINX_AMS is not set # end of Analog to digital converters # # Analog to digital and digital to analog converters # CONFIG_AD74413R=y # end of Analog to digital and digital to analog converters # # Analog Front Ends # CONFIG_IIO_RESCALE=m # end of Analog Front Ends # # Amplifiers # CONFIG_AD8366=m CONFIG_ADA4250=m CONFIG_HMC425=y # end of Amplifiers # # Capacitance to digital converters # CONFIG_AD7150=m # CONFIG_AD7746 is not set # end of Capacitance to digital converters # # Chemical Sensors # CONFIG_ATLAS_PH_SENSOR=m # CONFIG_ATLAS_EZO_SENSOR is not set # CONFIG_BME680 is not set CONFIG_CCS811=y CONFIG_IAQCORE=y # CONFIG_SCD30_CORE is not set CONFIG_SCD4X=m CONFIG_SENSIRION_SGP30=m CONFIG_SENSIRION_SGP40=y CONFIG_SPS30=m CONFIG_SPS30_I2C=m CONFIG_SENSEAIR_SUNRISE_CO2=m CONFIG_VZ89X=m # end of Chemical Sensors # # Hid Sensor IIO Common # # end of Hid Sensor IIO Common CONFIG_IIO_MS_SENSORS_I2C=y # # IIO SCMI Sensors # # end of IIO SCMI Sensors # # SSP Sensor Common # CONFIG_IIO_SSP_SENSORS_COMMONS=m CONFIG_IIO_SSP_SENSORHUB=m # end of SSP Sensor Common CONFIG_IIO_ST_SENSORS_I2C=m CONFIG_IIO_ST_SENSORS_SPI=y CONFIG_IIO_ST_SENSORS_CORE=y # # Digital to analog converters # CONFIG_AD3552R=m # CONFIG_AD5064 is not set # CONFIG_AD5360 is not set CONFIG_AD5380=m CONFIG_AD5421=m # CONFIG_AD5446 is not set CONFIG_AD5449=y CONFIG_AD5592R_BASE=m # CONFIG_AD5592R is not set CONFIG_AD5593R=m CONFIG_AD5504=m CONFIG_AD5624R_SPI=m CONFIG_LTC2688=m CONFIG_AD5686=y # CONFIG_AD5686_SPI is not set CONFIG_AD5696_I2C=y # CONFIG_AD5755 is not set # CONFIG_AD5758 is not set CONFIG_AD5761=m CONFIG_AD5764=m CONFIG_AD5766=y CONFIG_AD5770R=m # CONFIG_AD5791 is not set CONFIG_AD7293=y CONFIG_AD7303=m CONFIG_AD8801=y # CONFIG_DPOT_DAC is not set CONFIG_DS4424=y # CONFIG_LPC18XX_DAC is not set # CONFIG_LTC1660 is not set CONFIG_LTC2632=m # CONFIG_M62332 is not set CONFIG_MAX517=m # CONFIG_MAX5821 is not set CONFIG_MCP4725=m # CONFIG_MCP4922 is not set CONFIG_TI_DAC082S085=y CONFIG_TI_DAC5571=y CONFIG_TI_DAC7311=y CONFIG_TI_DAC7612=y CONFIG_VF610_DAC=y # end of Digital to analog converters # # IIO dummy driver # CONFIG_IIO_SIMPLE_DUMMY=m # CONFIG_IIO_SIMPLE_DUMMY_EVENTS is not set CONFIG_IIO_SIMPLE_DUMMY_BUFFER=y # end of IIO dummy driver # # Filters # # end of Filters # # Frequency Synthesizers DDS/PLL # # # Clock Generator/Distribution # # CONFIG_AD9523 is not set # end of Clock Generator/Distribution # # Phase-Locked Loop (PLL) frequency synthesizers # CONFIG_ADF4350=y # CONFIG_ADF4371 is not set # CONFIG_ADMV4420 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL # # Digital gyroscope sensors # # CONFIG_ADIS16080 is not set CONFIG_ADIS16130=m CONFIG_ADIS16136=y # CONFIG_ADIS16260 is not set CONFIG_ADXRS290=m # CONFIG_ADXRS450 is not set # CONFIG_BMG160 is not set CONFIG_FXAS21002C=y CONFIG_FXAS21002C_I2C=y CONFIG_FXAS21002C_SPI=y CONFIG_MPU3050=y CONFIG_MPU3050_I2C=y CONFIG_IIO_ST_GYRO_3AXIS=y # CONFIG_IIO_ST_GYRO_I2C_3AXIS is not set # CONFIG_IIO_ST_GYRO_SPI_3AXIS is not set CONFIG_ITG3200=m # end of Digital gyroscope sensors # # Health Sensors # # # Heart Rate Monitors # CONFIG_AFE4403=y CONFIG_AFE4404=y CONFIG_MAX30100=m CONFIG_MAX30102=y # end of Heart Rate Monitors # end of Health Sensors # # Humidity sensors # CONFIG_AM2315=m # CONFIG_DHT11 is not set # CONFIG_HDC100X is not set CONFIG_HDC2010=y # CONFIG_HTS221 is not set CONFIG_HTU21=y CONFIG_SI7005=m CONFIG_SI7020=y # end of Humidity sensors # # Inertial measurement units # # CONFIG_ADIS16400 is not set # CONFIG_ADIS16460 is not set CONFIG_ADIS16475=y CONFIG_ADIS16480=y CONFIG_BMI160=y CONFIG_BMI160_I2C=m CONFIG_BMI160_SPI=y CONFIG_BOSCH_BNO055=m CONFIG_BOSCH_BNO055_I2C=m CONFIG_FXOS8700=m # CONFIG_FXOS8700_I2C is not set CONFIG_FXOS8700_SPI=m # CONFIG_KMX61 is not set CONFIG_INV_ICM42600=y CONFIG_INV_ICM42600_I2C=y # CONFIG_INV_ICM42600_SPI is not set CONFIG_INV_MPU6050_IIO=m CONFIG_INV_MPU6050_I2C=m CONFIG_INV_MPU6050_SPI=m # CONFIG_IIO_ST_LSM6DSX is not set # end of Inertial measurement units CONFIG_IIO_ADIS_LIB=y CONFIG_IIO_ADIS_LIB_BUFFER=y # # Light sensors # # CONFIG_ADJD_S311 is not set CONFIG_ADUX1020=m CONFIG_AL3010=y CONFIG_AL3320A=m CONFIG_APDS9300=y CONFIG_APDS9960=y CONFIG_AS73211=m CONFIG_BH1750=m CONFIG_BH1780=y CONFIG_CM32181=y CONFIG_CM3232=y CONFIG_CM3323=y CONFIG_CM3605=y # CONFIG_CM36651 is not set CONFIG_GP2AP002=y # CONFIG_GP2AP020A00F is not set # CONFIG_IQS621_ALS is not set # CONFIG_SENSORS_ISL29018 is not set # CONFIG_SENSORS_ISL29028 is not set # CONFIG_ISL29125 is not set CONFIG_JSA1212=m CONFIG_RPR0521=y # CONFIG_SENSORS_LM3533 is not set CONFIG_LTR501=m CONFIG_LTRF216A=m # CONFIG_LV0104CS is not set CONFIG_MAX44000=m # CONFIG_MAX44009 is not set CONFIG_NOA1305=m CONFIG_OPT3001=m # CONFIG_PA12203001 is not set # CONFIG_SI1133 is not set # CONFIG_SI1145 is not set CONFIG_STK3310=y CONFIG_ST_UVIS25=y CONFIG_ST_UVIS25_I2C=y CONFIG_ST_UVIS25_SPI=y CONFIG_TCS3414=y # CONFIG_TCS3472 is not set # CONFIG_SENSORS_TSL2563 is not set CONFIG_TSL2583=m CONFIG_TSL2591=y # CONFIG_TSL2772 is not set CONFIG_TSL4531=y CONFIG_US5182D=m CONFIG_VCNL4000=m CONFIG_VCNL4035=m CONFIG_VEML6030=m CONFIG_VEML6070=m # CONFIG_VL6180 is not set CONFIG_ZOPT2201=y # end of Light sensors # # Magnetometer sensors # CONFIG_AK8974=m CONFIG_AK8975=y CONFIG_AK09911=m CONFIG_BMC150_MAGN=m CONFIG_BMC150_MAGN_I2C=m # CONFIG_BMC150_MAGN_SPI is not set CONFIG_MAG3110=m CONFIG_MMC35240=m CONFIG_IIO_ST_MAGN_3AXIS=m CONFIG_IIO_ST_MAGN_I2C_3AXIS=m CONFIG_IIO_ST_MAGN_SPI_3AXIS=m # CONFIG_SENSORS_HMC5843_I2C is not set # CONFIG_SENSORS_HMC5843_SPI is not set CONFIG_SENSORS_RM3100=m CONFIG_SENSORS_RM3100_I2C=m # CONFIG_SENSORS_RM3100_SPI is not set # CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors # # Multiplexers # # CONFIG_IIO_MUX is not set # end of Multiplexers # # Inclinometer sensors # # end of Inclinometer sensors CONFIG_IIO_RESCALE_KUNIT_TEST=m CONFIG_IIO_FORMAT_KUNIT_TEST=m # # Triggers - standalone # CONFIG_IIO_INTERRUPT_TRIGGER=y # CONFIG_IIO_STM32_LPTIMER_TRIGGER is not set # CONFIG_IIO_STM32_TIMER_TRIGGER is not set # CONFIG_IIO_SYSFS_TRIGGER is not set # end of Triggers - standalone # # Linear and angular position sensors # # CONFIG_IQS624_POS is not set # end of Linear and angular position sensors # # Digital potentiometers # CONFIG_AD5110=y CONFIG_AD5272=y CONFIG_DS1803=m CONFIG_MAX5432=y # CONFIG_MAX5481 is not set CONFIG_MAX5487=y CONFIG_MCP4018=y CONFIG_MCP4131=y CONFIG_MCP4531=m CONFIG_MCP41010=y CONFIG_TPL0102=y # end of Digital potentiometers # # Digital potentiostats # CONFIG_LMP91000=y # end of Digital potentiostats # # Pressure sensors # # CONFIG_ABP060MG is not set CONFIG_BMP280=y CONFIG_BMP280_I2C=y CONFIG_BMP280_SPI=y CONFIG_DLHL60D=m CONFIG_DPS310=m # CONFIG_HP03 is not set # CONFIG_ICP10100 is not set CONFIG_MPL115=y CONFIG_MPL115_I2C=y CONFIG_MPL115_SPI=m CONFIG_MPL3115=m CONFIG_MS5611=y CONFIG_MS5611_I2C=m CONFIG_MS5611_SPI=y CONFIG_MS5637=m CONFIG_IIO_ST_PRESS=y CONFIG_IIO_ST_PRESS_I2C=m CONFIG_IIO_ST_PRESS_SPI=y # CONFIG_T5403 is not set CONFIG_HP206C=m CONFIG_ZPA2326=y CONFIG_ZPA2326_I2C=y CONFIG_ZPA2326_SPI=y # end of Pressure sensors # # Lightning sensors # CONFIG_AS3935=y # end of Lightning sensors # # Proximity and distance sensors # CONFIG_ISL29501=y # CONFIG_LIDAR_LITE_V2 is not set CONFIG_MB1232=m # CONFIG_PING is not set CONFIG_RFD77402=y CONFIG_SRF04=y CONFIG_SX_COMMON=m CONFIG_SX9310=m CONFIG_SX9324=m CONFIG_SX9360=m CONFIG_SX9500=y CONFIG_SRF08=y CONFIG_VCNL3020=m CONFIG_VL53L0X_I2C=m # end of Proximity and distance sensors # # Resolver to digital converters # CONFIG_AD2S90=y # CONFIG_AD2S1200 is not set # end of Resolver to digital converters # # Temperature sensors # # CONFIG_IQS620AT_TEMP is not set CONFIG_LTC2983=m # CONFIG_MAXIM_THERMOCOUPLE is not set CONFIG_MLX90614=m CONFIG_MLX90632=y CONFIG_TMP006=m # CONFIG_TMP007 is not set CONFIG_TMP117=m # CONFIG_TSYS01 is not set CONFIG_TSYS02D=m CONFIG_MAX31856=m CONFIG_MAX31865=m # end of Temperature sensors # CONFIG_NTB is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_BCM2835 is not set # CONFIG_PWM_BERLIN is not set # CONFIG_PWM_BRCMSTB is not set # CONFIG_PWM_CLK is not set # CONFIG_PWM_CLPS711X is not set CONFIG_PWM_DWC=m # CONFIG_PWM_EP93XX is not set # CONFIG_PWM_HIBVT is not set # CONFIG_PWM_IMX1 is not set # CONFIG_PWM_IMX27 is not set # CONFIG_PWM_INTEL_LGM is not set # CONFIG_PWM_IQS620A is not set CONFIG_PWM_LP3943=m # CONFIG_PWM_LPC18XX_SCT is not set # CONFIG_PWM_LPC32XX is not set # CONFIG_PWM_LPSS_PCI is not set # CONFIG_PWM_LPSS_PLATFORM is not set # CONFIG_PWM_MTK_DISP is not set # CONFIG_PWM_MEDIATEK is not set CONFIG_PWM_PCA9685=y # CONFIG_PWM_PXA is not set # CONFIG_PWM_RASPBERRYPI_POE is not set # CONFIG_PWM_RCAR is not set # CONFIG_PWM_RENESAS_TPU is not set # CONFIG_PWM_ROCKCHIP is not set # CONFIG_PWM_SAMSUNG is not set # CONFIG_PWM_SL28CPLD is not set # CONFIG_PWM_SPRD is not set # CONFIG_PWM_STM32 is not set # CONFIG_PWM_STM32_LP is not set # CONFIG_PWM_TEGRA is not set # CONFIG_PWM_TIECAP is not set # CONFIG_PWM_TIEHRPWM is not set CONFIG_PWM_TWL=m CONFIG_PWM_TWL_LED=y # CONFIG_PWM_VISCONTI is not set # CONFIG_PWM_VT8500 is not set # # IRQ chip support # # CONFIG_AL_FIC is not set CONFIG_MADERA_IRQ=m # CONFIG_RENESAS_INTC_IRQPIN is not set # CONFIG_RENESAS_IRQC is not set # CONFIG_RENESAS_RZA1_IRQC is not set # CONFIG_RENESAS_RZG2L_IRQC is not set # CONFIG_SL28CPLD_INTC is not set # CONFIG_TS4800_IRQ is not set # CONFIG_INGENIC_TCU_IRQ is not set # CONFIG_IRQ_UNIPHIER_AIDET is not set # CONFIG_MESON_IRQ_GPIO is not set # CONFIG_IMX_IRQSTEER is not set # CONFIG_IMX_INTMUX is not set # CONFIG_EXYNOS_IRQ_COMBINER is not set # CONFIG_MST_IRQ is not set # CONFIG_MCHP_EIC is not set # CONFIG_SUNPLUS_SP7021_INTC is not set # end of IRQ chip support # CONFIG_IPACK_BUS is not set # CONFIG_RESET_CONTROLLER is not set # # PHY Subsystem # CONFIG_GENERIC_PHY=y # CONFIG_PHY_PISTACHIO_USB is not set CONFIG_PHY_CAN_TRANSCEIVER=y # # PHY drivers for Broadcom platforms # # CONFIG_PHY_BCM63XX_USBH is not set # CONFIG_BCM_KONA_USB2_PHY is not set # end of PHY drivers for Broadcom platforms # CONFIG_PHY_HI6220_USB is not set # CONFIG_PHY_HI3660_USB is not set # CONFIG_PHY_HI3670_USB is not set # CONFIG_PHY_HI3670_PCIE is not set # CONFIG_PHY_HISTB_COMBPHY is not set # CONFIG_PHY_HISI_INNO_USB2 is not set CONFIG_PHY_PXA_28NM_HSIC=y # CONFIG_PHY_PXA_28NM_USB2 is not set # CONFIG_PHY_PXA_USB is not set # CONFIG_PHY_MMP3_USB is not set # CONFIG_PHY_MMP3_HSIC is not set # CONFIG_PHY_MT7621_PCI is not set # CONFIG_PHY_RALINK_USB is not set # CONFIG_PHY_RCAR_GEN3_USB3 is not set # CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set # CONFIG_PHY_ROCKCHIP_PCIE is not set # CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 is not set # CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set # CONFIG_PHY_SAMSUNG_USB2 is not set # CONFIG_PHY_ST_SPEAR1310_MIPHY is not set # CONFIG_PHY_ST_SPEAR1340_MIPHY is not set # CONFIG_PHY_TEGRA194_P2U is not set # CONFIG_PHY_DA8XX_USB is not set # CONFIG_OMAP_CONTROL_PHY is not set # CONFIG_TI_PIPE3 is not set # CONFIG_PHY_INTEL_KEEMBAY_EMMC is not set # CONFIG_PHY_INTEL_KEEMBAY_USB is not set # CONFIG_PHY_INTEL_LGM_EMMC is not set # CONFIG_PHY_XILINX_ZYNQMP is not set # end of PHY Subsystem CONFIG_POWERCAP=y CONFIG_MCB=y # CONFIG_MCB_PCI is not set CONFIG_MCB_LPC=y # # Performance monitor support # # CONFIG_ARM_CCN is not set # CONFIG_ARM_CMN is not set # CONFIG_ARM_SMMU_V3_PMU is not set # CONFIG_FSL_IMX8_DDR_PMU is not set # CONFIG_XGENE_PMU is not set # CONFIG_ARM_DMC620_PMU is not set # CONFIG_MARVELL_CN10K_TAD_PMU is not set # CONFIG_ALIBABA_UNCORE_DRW_PMU is not set # CONFIG_HNS3_PMU is not set # CONFIG_MARVELL_CN10K_DDR_PMU is not set # end of Performance monitor support # CONFIG_RAS is not set # CONFIG_USB4 is not set # # Android # # CONFIG_ANDROID_BINDER_IPC is not set # end of Android CONFIG_LIBNVDIMM=m # CONFIG_BLK_DEV_PMEM is not set # CONFIG_BTT is not set CONFIG_DAX=y CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y # CONFIG_NVMEM_APPLE_EFUSES is not set # CONFIG_NVMEM_BCM_OCOTP is not set # CONFIG_NVMEM_BRCM_NVRAM is not set # CONFIG_NVMEM_IMX_IIM is not set # CONFIG_NVMEM_IMX_OCOTP is not set # CONFIG_NVMEM_LAN9662_OTPC is not set # CONFIG_NVMEM_LAYERSCAPE_SFP is not set # CONFIG_NVMEM_LPC18XX_EEPROM is not set # CONFIG_NVMEM_LPC18XX_OTP is not set # CONFIG_NVMEM_MESON_MX_EFUSE is not set # CONFIG_NVMEM_MICROCHIP_OTPC is not set # CONFIG_NVMEM_MTK_EFUSE is not set # CONFIG_NVMEM_MXS_OCOTP is not set # CONFIG_NVMEM_NINTENDO_OTP is not set # CONFIG_NVMEM_QCOM_QFPROM is not set CONFIG_NVMEM_RMEM=y # CONFIG_NVMEM_ROCKCHIP_EFUSE is not set # CONFIG_NVMEM_ROCKCHIP_OTP is not set # CONFIG_NVMEM_SC27XX_EFUSE is not set # CONFIG_NVMEM_SNVS_LPGPR is not set # CONFIG_NVMEM_SPMI_SDAM is not set # CONFIG_NVMEM_SPRD_EFUSE is not set # CONFIG_NVMEM_STM32_ROMEM is not set # CONFIG_NVMEM_SUNPLUS_OCOTP is not set # CONFIG_NVMEM_UNIPHIER_EFUSE is not set # CONFIG_NVMEM_VF610_OCOTP is not set # # HW tracing support # # CONFIG_STM is not set CONFIG_INTEL_TH=y CONFIG_INTEL_TH_PCI=m CONFIG_INTEL_TH_GTH=y # CONFIG_INTEL_TH_MSU is not set CONFIG_INTEL_TH_PTI=y # CONFIG_INTEL_TH_DEBUG is not set # CONFIG_HISI_PTT is not set # end of HW tracing support CONFIG_FPGA=y # CONFIG_FPGA_MGR_SOCFPGA is not set # CONFIG_FPGA_MGR_SOCFPGA_A10 is not set CONFIG_ALTERA_PR_IP_CORE=m CONFIG_FPGA_MGR_ALTERA_PS_SPI=m CONFIG_FPGA_MGR_ALTERA_CVP=y # CONFIG_FPGA_MGR_ZYNQ_FPGA is not set CONFIG_FPGA_MGR_XILINX_SPI=y CONFIG_FPGA_MGR_MACHXO2_SPI=y CONFIG_FPGA_BRIDGE=y CONFIG_ALTERA_FREEZE_BRIDGE=y CONFIG_XILINX_PR_DECOUPLER=m CONFIG_FPGA_REGION=m CONFIG_FPGA_DFL=m # CONFIG_FPGA_DFL_FME is not set # CONFIG_FPGA_DFL_AFU is not set CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m # CONFIG_FPGA_DFL_PCI is not set # CONFIG_FPGA_MGR_ZYNQMP_FPGA is not set # CONFIG_FPGA_MGR_VERSAL_FPGA is not set # CONFIG_FPGA_MGR_MICROCHIP_SPI is not set # CONFIG_TEE is not set CONFIG_MULTIPLEXER=y # # Multiplexer drivers # CONFIG_MUX_ADG792A=y # CONFIG_MUX_ADGS1408 is not set CONFIG_MUX_GPIO=y # CONFIG_MUX_MMIO is not set # end of Multiplexer drivers CONFIG_PM_OPP=y # CONFIG_SIOX is not set CONFIG_SLIMBUS=y CONFIG_SLIM_QCOM_CTRL=y # CONFIG_INTERCONNECT is not set # CONFIG_COUNTER is not set # CONFIG_MOST is not set # CONFIG_PECI is not set CONFIG_HTE=y # end of Device Drivers # # File systems # CONFIG_VALIDATE_FS_PARSER=y CONFIG_FS_IOMAP=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y # CONFIG_EXT2_FS_POSIX_ACL is not set # CONFIG_EXT2_FS_SECURITY is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_FS_POSIX_ACL is not set CONFIG_EXT3_FS_SECURITY=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y # CONFIG_EXT4_DEBUG is not set CONFIG_EXT4_KUNIT_TESTS=y CONFIG_JBD2=y CONFIG_JBD2_DEBUG=y CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=m CONFIG_REISERFS_CHECK=y # CONFIG_REISERFS_FS_XATTR is not set CONFIG_JFS_FS=y # CONFIG_JFS_POSIX_ACL is not set CONFIG_JFS_SECURITY=y # CONFIG_JFS_DEBUG is not set CONFIG_JFS_STATISTICS=y CONFIG_XFS_FS=m CONFIG_XFS_SUPPORT_V4=y # CONFIG_XFS_QUOTA is not set CONFIG_XFS_POSIX_ACL=y # CONFIG_XFS_RT is not set CONFIG_XFS_ONLINE_SCRUB=y # CONFIG_XFS_ONLINE_REPAIR is not set CONFIG_XFS_DEBUG=y CONFIG_XFS_ASSERT_FATAL=y # CONFIG_GFS2_FS is not set CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y # CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set # CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set # CONFIG_BTRFS_DEBUG is not set CONFIG_BTRFS_ASSERT=y CONFIG_BTRFS_FS_REF_VERIFY=y CONFIG_NILFS2_FS=y CONFIG_F2FS_FS=m # CONFIG_F2FS_STAT_FS is not set CONFIG_F2FS_FS_XATTR=y # CONFIG_F2FS_FS_POSIX_ACL is not set # CONFIG_F2FS_FS_SECURITY is not set CONFIG_F2FS_CHECK_FS=y CONFIG_F2FS_FAULT_INJECTION=y CONFIG_F2FS_FS_COMPRESSION=y CONFIG_F2FS_FS_LZO=y CONFIG_F2FS_FS_LZORLE=y CONFIG_F2FS_FS_LZ4=y CONFIG_F2FS_FS_LZ4HC=y CONFIG_F2FS_FS_ZSTD=y CONFIG_F2FS_IOSTAT=y CONFIG_F2FS_UNFAIR_RWSEM=y # CONFIG_ZONEFS_FS is not set CONFIG_FS_DAX=y CONFIG_FS_DAX_LIMITED=y CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y CONFIG_EXPORTFS_BLOCK_OPS=y # CONFIG_FILE_LOCKING is not set # CONFIG_FS_ENCRYPTION is not set CONFIG_FS_VERITY=y CONFIG_FS_VERITY_DEBUG=y # CONFIG_FS_VERITY_BUILTIN_SIGNATURES is not set # CONFIG_DNOTIFY is not set # CONFIG_INOTIFY_USER is not set # CONFIG_FANOTIFY is not set # CONFIG_QUOTA is not set CONFIG_AUTOFS4_FS=y CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=y CONFIG_CUSE=y # CONFIG_VIRTIO_FS is not set # CONFIG_OVERLAY_FS is not set # # Caches # CONFIG_NETFS_SUPPORT=m CONFIG_FSCACHE=m # CONFIG_FSCACHE_DEBUG is not set CONFIG_CACHEFILES=m CONFIG_CACHEFILES_DEBUG=y # CONFIG_CACHEFILES_ONDEMAND is not set # end of Caches # # CD-ROM/DVD Filesystems # CONFIG_ISO9660_FS=y # CONFIG_JOLIET is not set CONFIG_ZISOFS=y CONFIG_UDF_FS=m # end of CD-ROM/DVD Filesystems # # DOS/FAT/EXFAT/NT Filesystems # CONFIG_FAT_FS=m CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_FAT_DEFAULT_UTF8=y # CONFIG_FAT_KUNIT_TEST is not set # CONFIG_EXFAT_FS is not set # CONFIG_NTFS_FS is not set CONFIG_NTFS3_FS=m # CONFIG_NTFS3_64BIT_CLUSTER is not set # CONFIG_NTFS3_LZX_XPRESS is not set # CONFIG_NTFS3_FS_POSIX_ACL is not set # end of DOS/FAT/EXFAT/NT Filesystems # # Pseudo filesystems # # CONFIG_PROC_FS is not set CONFIG_KERNFS=y CONFIG_SYSFS=y # CONFIG_TMPFS is not set CONFIG_ARCH_SUPPORTS_HUGETLBFS=y CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y CONFIG_MEMFD_CREATE=y CONFIG_ARCH_HAS_GIGANTIC_PAGE=y CONFIG_CONFIGFS_FS=y # end of Pseudo filesystems # CONFIG_MISC_FILESYSTEMS is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_CODEPAGE_737=y CONFIG_NLS_CODEPAGE_775=m # CONFIG_NLS_CODEPAGE_850 is not set CONFIG_NLS_CODEPAGE_852=m CONFIG_NLS_CODEPAGE_855=m # CONFIG_NLS_CODEPAGE_857 is not set CONFIG_NLS_CODEPAGE_860=m CONFIG_NLS_CODEPAGE_861=y CONFIG_NLS_CODEPAGE_862=y CONFIG_NLS_CODEPAGE_863=m CONFIG_NLS_CODEPAGE_864=y # CONFIG_NLS_CODEPAGE_865 is not set # CONFIG_NLS_CODEPAGE_866 is not set CONFIG_NLS_CODEPAGE_869=y CONFIG_NLS_CODEPAGE_936=y # CONFIG_NLS_CODEPAGE_950 is not set # CONFIG_NLS_CODEPAGE_932 is not set CONFIG_NLS_CODEPAGE_949=m CONFIG_NLS_CODEPAGE_874=y CONFIG_NLS_ISO8859_8=y # CONFIG_NLS_CODEPAGE_1250 is not set CONFIG_NLS_CODEPAGE_1251=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_2=y # CONFIG_NLS_ISO8859_3 is not set CONFIG_NLS_ISO8859_4=m CONFIG_NLS_ISO8859_5=m # CONFIG_NLS_ISO8859_6 is not set CONFIG_NLS_ISO8859_7=m CONFIG_NLS_ISO8859_9=m CONFIG_NLS_ISO8859_13=y CONFIG_NLS_ISO8859_14=m # CONFIG_NLS_ISO8859_15 is not set CONFIG_NLS_KOI8_R=y CONFIG_NLS_KOI8_U=m CONFIG_NLS_MAC_ROMAN=m # CONFIG_NLS_MAC_CELTIC is not set # CONFIG_NLS_MAC_CENTEURO is not set # CONFIG_NLS_MAC_CROATIAN is not set CONFIG_NLS_MAC_CYRILLIC=m CONFIG_NLS_MAC_GAELIC=y # CONFIG_NLS_MAC_GREEK is not set CONFIG_NLS_MAC_ICELAND=y CONFIG_NLS_MAC_INUIT=y CONFIG_NLS_MAC_ROMANIAN=y # CONFIG_NLS_MAC_TURKISH is not set CONFIG_NLS_UTF8=y # CONFIG_UNICODE is not set CONFIG_IO_WQ=y # end of File systems # # Security options # CONFIG_KEYS=y CONFIG_KEYS_REQUEST_CACHE=y # CONFIG_PERSISTENT_KEYRINGS is not set CONFIG_TRUSTED_KEYS=y # # No trust source selected! # # CONFIG_ENCRYPTED_KEYS is not set CONFIG_KEY_DH_OPERATIONS=y CONFIG_SECURITY_DMESG_RESTRICT=y # CONFIG_SECURITYFS is not set # CONFIG_FORTIFY_SOURCE is not set CONFIG_STATIC_USERMODEHELPER=y CONFIG_STATIC_USERMODEHELPER_PATH="/sbin/usermode-helper" # CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf" # # Kernel hardening options # # # Memory initialization # CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y # CONFIG_INIT_STACK_NONE is not set # CONFIG_INIT_STACK_ALL_PATTERN is not set CONFIG_INIT_STACK_ALL_ZERO=y # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y CONFIG_ZERO_CALL_USED_REGS=y # end of Memory initialization CONFIG_RANDSTRUCT_NONE=y # end of Kernel hardening options # end of Security options CONFIG_XOR_BLOCKS=m CONFIG_CRYPTO=y # # Crypto core or helper # # CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_AKCIPHER2=y CONFIG_CRYPTO_AKCIPHER=y CONFIG_CRYPTO_KPP2=y CONFIG_CRYPTO_KPP=y CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_PCRYPT=y CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_AUTHENC=m CONFIG_CRYPTO_TEST=y # end of Crypto core or helper # # Public-key cryptography # CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_ECC=y CONFIG_CRYPTO_ECDH=m CONFIG_CRYPTO_ECDSA=y # CONFIG_CRYPTO_ECRDSA is not set # CONFIG_CRYPTO_SM2 is not set CONFIG_CRYPTO_CURVE25519=m # end of Public-key cryptography # # Block ciphers # CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_AES_TI=y CONFIG_CRYPTO_ARIA=m CONFIG_CRYPTO_BLOWFISH=y CONFIG_CRYPTO_BLOWFISH_COMMON=y CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST_COMMON=m # CONFIG_CRYPTO_CAST5 is not set CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_SM4=y CONFIG_CRYPTO_SM4_GENERIC=y # CONFIG_CRYPTO_TWOFISH is not set # end of Block ciphers # # Length-preserving ciphers and modes # CONFIG_CRYPTO_ADIANTUM=y CONFIG_CRYPTO_CHACHA20=y CONFIG_CRYPTO_CBC=m # CONFIG_CRYPTO_CFB is not set CONFIG_CRYPTO_CTR=y # CONFIG_CRYPTO_CTS is not set CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_HCTR2=m CONFIG_CRYPTO_KEYWRAP=m CONFIG_CRYPTO_LRW=y CONFIG_CRYPTO_OFB=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XCTR=m CONFIG_CRYPTO_XTS=y CONFIG_CRYPTO_NHPOLY1305=y # end of Length-preserving ciphers and modes # # AEAD (authenticated encryption with associated data) ciphers # CONFIG_CRYPTO_AEGIS128=y CONFIG_CRYPTO_CHACHA20POLY1305=m CONFIG_CRYPTO_CCM=y # CONFIG_CRYPTO_GCM is not set # CONFIG_CRYPTO_SEQIV is not set CONFIG_CRYPTO_ECHAINIV=y CONFIG_CRYPTO_ESSIV=m # end of AEAD (authenticated encryption with associated data) ciphers # # Hashes, digests, and MACs # CONFIG_CRYPTO_BLAKE2B=m # CONFIG_CRYPTO_CMAC is not set CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_MD4=m # CONFIG_CRYPTO_MD5 is not set CONFIG_CRYPTO_MICHAEL_MIC=y CONFIG_CRYPTO_POLYVAL=m CONFIG_CRYPTO_POLY1305=y CONFIG_CRYPTO_RMD160=y CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA3=m CONFIG_CRYPTO_SM3=m CONFIG_CRYPTO_SM3_GENERIC=m # CONFIG_CRYPTO_STREEBOG is not set CONFIG_CRYPTO_VMAC=y CONFIG_CRYPTO_WP512=m CONFIG_CRYPTO_XCBC=m CONFIG_CRYPTO_XXHASH=m # end of Hashes, digests, and MACs # # CRCs (cyclic redundancy checks) # CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRCT10DIF=m CONFIG_CRYPTO_CRC64_ROCKSOFT=m # end of CRCs (cyclic redundancy checks) # # Compression # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_842=m CONFIG_CRYPTO_LZ4=m # CONFIG_CRYPTO_LZ4HC is not set CONFIG_CRYPTO_ZSTD=y # end of Compression # # Random number generation # CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_DRBG_MENU=y CONFIG_CRYPTO_DRBG_HMAC=y CONFIG_CRYPTO_DRBG_HASH=y CONFIG_CRYPTO_DRBG_CTR=y CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_KDF800108_CTR=y # end of Random number generation # # Userspace interface # # end of Userspace interface CONFIG_CRYPTO_HASH_INFO=y # # Accelerated Cryptographic Algorithms for CPU (s390) # # CONFIG_CRYPTO_CRC32_S390 is not set # CONFIG_CRYPTO_SHA512_S390 is not set # CONFIG_CRYPTO_SHA1_S390 is not set # CONFIG_CRYPTO_SHA256_S390 is not set CONFIG_CRYPTO_SHA3_256_S390=y CONFIG_CRYPTO_SHA3_512_S390=m CONFIG_CRYPTO_GHASH_S390=m CONFIG_CRYPTO_AES_S390=m CONFIG_CRYPTO_DES_S390=y CONFIG_CRYPTO_CHACHA_S390=m # end of Accelerated Cryptographic Algorithms for CPU (s390) # CONFIG_CRYPTO_HW is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y CONFIG_PKCS8_PRIVATE_KEY_PARSER=m CONFIG_PKCS7_MESSAGE_PARSER=y # CONFIG_PKCS7_TEST_KEY is not set CONFIG_SIGNED_PE_FILE_VERIFICATION=y CONFIG_FIPS_SIGNATURE_SELFTEST=y # # Certificates for signature checking # CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" # CONFIG_MODULE_SIG_KEY_TYPE_RSA is not set CONFIG_MODULE_SIG_KEY_TYPE_ECDSA=y CONFIG_SYSTEM_TRUSTED_KEYRING=y CONFIG_SYSTEM_TRUSTED_KEYS="" CONFIG_SYSTEM_EXTRA_CERTIFICATE=y CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096 # CONFIG_SECONDARY_TRUSTED_KEYRING is not set CONFIG_SYSTEM_BLACKLIST_KEYRING=y CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" # CONFIG_SYSTEM_REVOCATION_LIST is not set CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y # end of Certificates for signature checking CONFIG_BINARY_PRINTF=y # # Library routines # CONFIG_RAID6_PQ=m # CONFIG_RAID6_PQ_BENCHMARK is not set CONFIG_LINEAR_RANGES=m CONFIG_PACKING=y CONFIG_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_CORDIC=m CONFIG_PRIME_NUMBERS=m CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y # # Crypto library routines # CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y # CONFIG_CRYPTO_LIB_CHACHA is not set CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m # CONFIG_CRYPTO_LIB_CURVE25519 is not set CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y # CONFIG_CRYPTO_LIB_POLY1305 is not set # CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set CONFIG_CRYPTO_LIB_SHA1=m CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC_T10DIF=m # CONFIG_CRC64_ROCKSOFT is not set CONFIG_CRC_ITU_T=y CONFIG_CRC32=y CONFIG_CRC32_SELFTEST=y # CONFIG_CRC32_SLICEBY8 is not set CONFIG_CRC32_SLICEBY4=y # CONFIG_CRC32_SARWATE is not set # CONFIG_CRC32_BIT is not set CONFIG_CRC64=m CONFIG_CRC4=m CONFIG_CRC7=y CONFIG_LIBCRC32C=m CONFIG_CRC8=y CONFIG_XXHASH=y CONFIG_RANDOM32_SELFTEST=y CONFIG_842_COMPRESS=m CONFIG_842_DECOMPRESS=m CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m # CONFIG_ZLIB_DFLTCC is not set CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4_COMPRESS=m CONFIG_LZ4HC_COMPRESS=m CONFIG_LZ4_DECOMPRESS=m CONFIG_ZSTD_COMMON=y CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y CONFIG_XZ_DEC_POWERPC=y # CONFIG_XZ_DEC_IA64 is not set # CONFIG_XZ_DEC_ARM is not set CONFIG_XZ_DEC_ARMTHUMB=y # CONFIG_XZ_DEC_SPARC is not set # CONFIG_XZ_DEC_MICROLZMA is not set CONFIG_XZ_DEC_BCJ=y CONFIG_XZ_DEC_TEST=m CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_LZMA=y CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_BCH=m CONFIG_INTERVAL_TREE=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_DMA=y CONFIG_DMA_OPS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED=y CONFIG_SWIOTLB=y # CONFIG_DMA_CMA is not set # CONFIG_DMA_API_DEBUG is not set CONFIG_DMA_MAP_BENCHMARK=y CONFIG_SGL_ALLOC=y CONFIG_IOMMU_HELPER=y CONFIG_CHECK_SIGNATURE=y # CONFIG_CPUMASK_OFFSTACK is not set # CONFIG_FORCE_NR_CPUS is not set CONFIG_GLOB=y # CONFIG_GLOB_SELFTEST is not set CONFIG_CLZ_TAB=y CONFIG_IRQ_POLL=y CONFIG_MPILIB=y CONFIG_OID_REGISTRY=y CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_VDSO_TIME_NS=y CONFIG_SG_POOL=y CONFIG_MEMREGION=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y CONFIG_SBITMAP=y # CONFIG_PARMAN is not set # CONFIG_OBJAGG is not set # end of Library routines # # Kernel hacking # # # printk and dmesg options # CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_SYMBOLIC_ERRNAME is not set # end of printk and dmesg options CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_MISC is not set # # Compile-time checks and compiler options # CONFIG_AS_HAS_NON_CONST_LEB128=y CONFIG_DEBUG_INFO_NONE=y # CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set # CONFIG_DEBUG_INFO_DWARF4 is not set # CONFIG_DEBUG_INFO_DWARF5 is not set CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set # CONFIG_HEADERS_INSTALL is not set CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_SECTION_MISMATCH_WARN_ONLY=y # CONFIG_VMLINUX_MAP is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options # # Generic Kernel Debugging Instruments # # CONFIG_MAGIC_SYSRQ is not set CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y CONFIG_UBSAN=y CONFIG_CC_HAS_UBSAN_BOUNDS=y # CONFIG_UBSAN_BOUNDS is not set CONFIG_UBSAN_SHIFT=y # CONFIG_UBSAN_DIV_ZERO is not set CONFIG_UBSAN_UNREACHABLE=y # CONFIG_UBSAN_BOOL is not set CONFIG_UBSAN_ENUM=y CONFIG_UBSAN_SANITIZE_ALL=y CONFIG_TEST_UBSAN=m CONFIG_HAVE_ARCH_KCSAN=y CONFIG_HAVE_KCSAN_COMPILER=y # CONFIG_KCSAN is not set # end of Generic Kernel Debugging Instruments # # Networking Debugging # # end of Networking Debugging # # Memory Debugging # CONFIG_PAGE_EXTENSION=y CONFIG_DEBUG_PAGEALLOC=y CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y # CONFIG_PAGE_OWNER is not set CONFIG_PAGE_POISONING=y CONFIG_DEBUG_PAGE_REF=y CONFIG_DEBUG_RODATA_TEST=y CONFIG_ARCH_HAS_DEBUG_WX=y # CONFIG_DEBUG_WX is not set CONFIG_GENERIC_PTDUMP=y CONFIG_PTDUMP_CORE=y CONFIG_PTDUMP_DEBUGFS=y CONFIG_DEBUG_OBJECTS=y # CONFIG_DEBUG_OBJECTS_SELFTEST is not set # CONFIG_DEBUG_OBJECTS_FREE is not set # CONFIG_DEBUG_OBJECTS_TIMERS is not set # CONFIG_DEBUG_OBJECTS_WORK is not set # CONFIG_DEBUG_OBJECTS_RCU_HEAD is not set # CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER is not set CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 CONFIG_SHRINKER_DEBUG=y CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set CONFIG_DEBUG_STACK_USAGE=y # CONFIG_SCHED_STACK_END_CHECK is not set CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y # CONFIG_DEBUG_VM is not set CONFIG_DEBUG_VM_PGTABLE=y # CONFIG_DEBUG_MEMORY_INIT is not set CONFIG_DEBUG_PER_CPU_MAPS=y CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y CONFIG_HAVE_ARCH_KFENCE=y # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set # # Debug Oops, Lockups and Hangs # # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 CONFIG_DETECT_HUNG_TASK=y CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y # CONFIG_WQ_WATCHDOG is not set CONFIG_TEST_LOCKUP=m # end of Debug Oops, Lockups and Hangs # # Scheduler Debugging # # end of Scheduler Debugging CONFIG_DEBUG_TIMEKEEPING=y # # Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_PROVE_LOCKING=y CONFIG_PROVE_RAW_LOCK_NESTING=y CONFIG_LOCK_STAT=y CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y CONFIG_DEBUG_RWSEMS=y CONFIG_DEBUG_LOCK_ALLOC=y CONFIG_LOCKDEP=y CONFIG_LOCKDEP_BITS=15 CONFIG_LOCKDEP_CHAINS_BITS=16 CONFIG_LOCKDEP_STACK_TRACE_BITS=19 CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 # CONFIG_DEBUG_LOCKDEP is not set CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_DEBUG_LOCKING_API_SELFTESTS=y CONFIG_LOCK_TORTURE_TEST=y CONFIG_WW_MUTEX_SELFTEST=m CONFIG_SCF_TORTURE_TEST=y # CONFIG_CSD_LOCK_WAIT_DEBUG is not set # end of Lock Debugging (spinlocks, mutexes, etc...) CONFIG_TRACE_IRQFLAGS=y # CONFIG_DEBUG_IRQFLAGS is not set CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set CONFIG_DEBUG_KOBJECT=y # # Debug kernel data structures # CONFIG_DEBUG_LIST=y # CONFIG_DEBUG_PLIST is not set CONFIG_DEBUG_SG=y # CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_BUG_ON_DATA_CORRUPTION is not set # CONFIG_DEBUG_MAPLE_TREE is not set # end of Debug kernel data structures # CONFIG_DEBUG_CREDENTIALS is not set # # RCU Debugging # CONFIG_PROVE_RCU=y CONFIG_PROVE_RCU_LIST=y CONFIG_TORTURE_TEST=y # CONFIG_RCU_SCALE_TEST is not set # CONFIG_RCU_TORTURE_TEST is not set CONFIG_RCU_REF_SCALE_TEST=y CONFIG_RCU_CPU_STALL_TIMEOUT=21 CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 CONFIG_RCU_TRACE=y CONFIG_RCU_EQS_DEBUG=y # end of RCU Debugging CONFIG_DEBUG_WQ_FORCE_RR_CPU=y # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set CONFIG_NOP_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_FENTRY=y CONFIG_HAVE_NOP_MCOUNT=y CONFIG_TRACER_MAX_TRACE=y CONFIG_TRACE_CLOCK=y CONFIG_RING_BUFFER=y CONFIG_EVENT_TRACING=y CONFIG_CONTEXT_SWITCH_TRACER=y CONFIG_RING_BUFFER_ALLOW_SWAP=y CONFIG_PREEMPTIRQ_TRACEPOINTS=y CONFIG_TRACING=y CONFIG_GENERIC_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y CONFIG_BOOTTIME_TRACING=y # CONFIG_FUNCTION_TRACER is not set # CONFIG_STACK_TRACER is not set CONFIG_IRQSOFF_TRACER=y # CONFIG_SCHED_TRACER is not set # CONFIG_HWLAT_TRACER is not set CONFIG_OSNOISE_TRACER=y # CONFIG_TIMERLAT_TRACER is not set CONFIG_FTRACE_SYSCALLS=y CONFIG_TRACER_SNAPSHOT=y CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y CONFIG_TRACE_BRANCH_PROFILING=y # CONFIG_BRANCH_PROFILE_NONE is not set CONFIG_PROFILE_ANNOTATED_BRANCHES=y # CONFIG_PROFILE_ALL_BRANCHES is not set CONFIG_TRACING_BRANCHES=y CONFIG_BRANCH_TRACER=y CONFIG_BLK_DEV_IO_TRACE=y # CONFIG_UPROBE_EVENTS is not set CONFIG_DYNAMIC_EVENTS=y CONFIG_SYNTH_EVENTS=y # CONFIG_USER_EVENTS is not set # CONFIG_HIST_TRIGGERS is not set CONFIG_TRACE_EVENT_INJECT=y # CONFIG_TRACEPOINT_BENCHMARK is not set CONFIG_RING_BUFFER_BENCHMARK=y # CONFIG_TRACE_EVAL_MAP_FILE is not set CONFIG_FTRACE_SELFTEST=y CONFIG_FTRACE_STARTUP_TEST=y CONFIG_EVENT_TRACE_STARTUP_TEST=y # CONFIG_EVENT_TRACE_TEST_SYSCALLS is not set CONFIG_RING_BUFFER_STARTUP_TEST=y # CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set CONFIG_PREEMPTIRQ_DELAY_TEST=m CONFIG_SYNTH_EVENT_GEN_TEST=y CONFIG_DA_MON_EVENTS=y CONFIG_DA_MON_EVENTS_ID=y CONFIG_RV=y CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PRINTK=y CONFIG_RV_REACT_PANIC=y # CONFIG_SAMPLES is not set CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y CONFIG_STRICT_DEVMEM=y CONFIG_IO_STRICT_DEVMEM=y # # s390 Debugging # CONFIG_EARLY_PRINTK=y CONFIG_DEBUG_ENTRY=y # CONFIG_CIO_INJECT is not set # end of s390 Debugging # # Kernel Testing and Coverage # CONFIG_KUNIT=y CONFIG_KUNIT_DEBUGFS=y # CONFIG_KUNIT_TEST is not set CONFIG_KUNIT_EXAMPLE_TEST=y # CONFIG_KUNIT_ALL_TESTS is not set CONFIG_KUNIT_DEFAULT_ENABLED=y # CONFIG_NOTIFIER_ERROR_INJECTION is not set CONFIG_FAULT_INJECTION=y CONFIG_FAIL_PAGE_ALLOC=y # CONFIG_FAULT_INJECTION_USERCOPY is not set CONFIG_FAIL_MAKE_REQUEST=y # CONFIG_FAIL_IO_TIMEOUT is not set # CONFIG_FAULT_INJECTION_DEBUG_FS is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set # end of Kernel Testing and Coverage # # Rust hacking # # end of Rust hacking # CONFIG_WARN_MISSING_DOCUMENTS is not set # CONFIG_WARN_ABI_ERRORS is not set # end of Kernel hacking ^ permalink raw reply [flat|nested] 98+ messages in thread
* [PATCH 06/12] regulator: arizona-micsupp: Don't hardcode use of ARIZONA defines 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-09 16:53 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches, Richard Fitzgerald When Madera support was added to this driver the code was left using ARIZONA_* defines. This wasn't causing any problem because those defines just happened to have the same value as the equivalent MADERA_* defines. But it is not ideal to assume this, and future devices that can share this driver do not have the same register map. Fix the code to refer to the register data in struct regulator_desc. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- drivers/regulator/arizona-micsupp.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/regulator/arizona-micsupp.c b/drivers/regulator/arizona-micsupp.c index f6cfd3f6f0dd..21c36972a8e9 100644 --- a/drivers/regulator/arizona-micsupp.c +++ b/drivers/regulator/arizona-micsupp.c @@ -34,7 +34,7 @@ struct arizona_micsupp { struct regulator_dev *regulator; struct regmap *regmap; struct snd_soc_dapm_context **dapm; - unsigned int enable_reg; + const struct regulator_desc *desc; struct device *dev; struct regulator_consumer_supply supply; @@ -49,10 +49,11 @@ static void arizona_micsupp_check_cp(struct work_struct *work) container_of(work, struct arizona_micsupp, check_cp_work); struct snd_soc_dapm_context *dapm = *micsupp->dapm; struct snd_soc_component *component; + const struct regulator_desc *desc = micsupp->desc; unsigned int val; int ret; - ret = regmap_read(micsupp->regmap, micsupp->enable_reg, &val); + ret = regmap_read(micsupp->regmap, desc->enable_reg, &val); if (ret != 0) { dev_err(micsupp->dev, "Failed to read CP state: %d\n", ret); @@ -62,8 +63,8 @@ static void arizona_micsupp_check_cp(struct work_struct *work) if (dapm) { component = snd_soc_dapm_to_component(dapm); - if ((val & (ARIZONA_CPMIC_ENA | ARIZONA_CPMIC_BYPASS)) == - ARIZONA_CPMIC_ENA) + if ((val & (desc->enable_mask | desc->bypass_mask)) == + desc->enable_mask) snd_soc_component_force_enable_pin(component, "MICSUPP"); else @@ -209,7 +210,6 @@ static const struct regulator_desc madera_micsupp = { .type = REGULATOR_VOLTAGE, .n_voltages = 40, .ops = &arizona_micsupp_ops, - .vsel_reg = MADERA_LDO2_CONTROL_1, .vsel_mask = MADERA_LDO2_VSEL_MASK, .enable_reg = MADERA_MIC_CHARGE_PUMP_1, @@ -264,7 +264,7 @@ static int arizona_micsupp_common_init(struct platform_device *pdev, micsupp->init_data.consumer_supplies = &micsupp->supply; micsupp->supply.supply = "MICVDD"; micsupp->supply.dev_name = dev_name(micsupp->dev); - micsupp->enable_reg = desc->enable_reg; + micsupp->desc = desc; config.dev = micsupp->dev; config.driver_data = micsupp; @@ -285,8 +285,7 @@ static int arizona_micsupp_common_init(struct platform_device *pdev, config.init_data = &micsupp->init_data; /* Default to regulated mode */ - regmap_update_bits(micsupp->regmap, micsupp->enable_reg, - ARIZONA_CPMIC_BYPASS, 0); + regmap_update_bits(micsupp->regmap, desc->enable_reg, desc->bypass_mask, 0); micsupp->regulator = devm_regulator_register(&pdev->dev, desc, -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 06/12] regulator: arizona-micsupp: Don't hardcode use of ARIZONA defines @ 2022-11-09 16:53 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio, Richard Fitzgerald When Madera support was added to this driver the code was left using ARIZONA_* defines. This wasn't causing any problem because those defines just happened to have the same value as the equivalent MADERA_* defines. But it is not ideal to assume this, and future devices that can share this driver do not have the same register map. Fix the code to refer to the register data in struct regulator_desc. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- drivers/regulator/arizona-micsupp.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/regulator/arizona-micsupp.c b/drivers/regulator/arizona-micsupp.c index f6cfd3f6f0dd..21c36972a8e9 100644 --- a/drivers/regulator/arizona-micsupp.c +++ b/drivers/regulator/arizona-micsupp.c @@ -34,7 +34,7 @@ struct arizona_micsupp { struct regulator_dev *regulator; struct regmap *regmap; struct snd_soc_dapm_context **dapm; - unsigned int enable_reg; + const struct regulator_desc *desc; struct device *dev; struct regulator_consumer_supply supply; @@ -49,10 +49,11 @@ static void arizona_micsupp_check_cp(struct work_struct *work) container_of(work, struct arizona_micsupp, check_cp_work); struct snd_soc_dapm_context *dapm = *micsupp->dapm; struct snd_soc_component *component; + const struct regulator_desc *desc = micsupp->desc; unsigned int val; int ret; - ret = regmap_read(micsupp->regmap, micsupp->enable_reg, &val); + ret = regmap_read(micsupp->regmap, desc->enable_reg, &val); if (ret != 0) { dev_err(micsupp->dev, "Failed to read CP state: %d\n", ret); @@ -62,8 +63,8 @@ static void arizona_micsupp_check_cp(struct work_struct *work) if (dapm) { component = snd_soc_dapm_to_component(dapm); - if ((val & (ARIZONA_CPMIC_ENA | ARIZONA_CPMIC_BYPASS)) == - ARIZONA_CPMIC_ENA) + if ((val & (desc->enable_mask | desc->bypass_mask)) == + desc->enable_mask) snd_soc_component_force_enable_pin(component, "MICSUPP"); else @@ -209,7 +210,6 @@ static const struct regulator_desc madera_micsupp = { .type = REGULATOR_VOLTAGE, .n_voltages = 40, .ops = &arizona_micsupp_ops, - .vsel_reg = MADERA_LDO2_CONTROL_1, .vsel_mask = MADERA_LDO2_VSEL_MASK, .enable_reg = MADERA_MIC_CHARGE_PUMP_1, @@ -264,7 +264,7 @@ static int arizona_micsupp_common_init(struct platform_device *pdev, micsupp->init_data.consumer_supplies = &micsupp->supply; micsupp->supply.supply = "MICVDD"; micsupp->supply.dev_name = dev_name(micsupp->dev); - micsupp->enable_reg = desc->enable_reg; + micsupp->desc = desc; config.dev = micsupp->dev; config.driver_data = micsupp; @@ -285,8 +285,7 @@ static int arizona_micsupp_common_init(struct platform_device *pdev, config.init_data = &micsupp->init_data; /* Default to regulated mode */ - regmap_update_bits(micsupp->regmap, micsupp->enable_reg, - ARIZONA_CPMIC_BYPASS, 0); + regmap_update_bits(micsupp->regmap, desc->enable_reg, desc->bypass_mask, 0); micsupp->regulator = devm_regulator_register(&pdev->dev, desc, -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 07/12] regulator: arizona-micsupp: Don't use a common regulator name 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-09 16:53 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches, Richard Fitzgerald The Arizona and Madera codecs all have a datasheet name of "MICVDD" for the regulator output. But future codecs with a regulator that can be controlled by this driver have different naming convention for the output of the regulator. Move the setting of the supply name from arizona_micsupp_common_init() to arizona_micsupp_probe() and madera_micsupp_probe(). Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- drivers/regulator/arizona-micsupp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/regulator/arizona-micsupp.c b/drivers/regulator/arizona-micsupp.c index 21c36972a8e9..596ecd8041cd 100644 --- a/drivers/regulator/arizona-micsupp.c +++ b/drivers/regulator/arizona-micsupp.c @@ -262,7 +262,6 @@ static int arizona_micsupp_common_init(struct platform_device *pdev, INIT_WORK(&micsupp->check_cp_work, arizona_micsupp_check_cp); micsupp->init_data.consumer_supplies = &micsupp->supply; - micsupp->supply.supply = "MICVDD"; micsupp->supply.dev_name = dev_name(micsupp->dev); micsupp->desc = desc; @@ -319,6 +318,8 @@ static int arizona_micsupp_probe(struct platform_device *pdev) micsupp->dapm = &arizona->dapm; micsupp->dev = arizona->dev; + micsupp->supply.supply = "MICVDD"; + /* * Since the chip usually supplies itself we provide some * default init_data for it. This will be overridden with @@ -354,6 +355,8 @@ static int madera_micsupp_probe(struct platform_device *pdev) micsupp->dev = madera->dev; micsupp->init_data = arizona_micsupp_ext_default; + micsupp->supply.supply = "MICVDD"; + return arizona_micsupp_common_init(pdev, micsupp, &madera_micsupp, &madera->pdata.micvdd); } -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 07/12] regulator: arizona-micsupp: Don't use a common regulator name @ 2022-11-09 16:53 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio, Richard Fitzgerald The Arizona and Madera codecs all have a datasheet name of "MICVDD" for the regulator output. But future codecs with a regulator that can be controlled by this driver have different naming convention for the output of the regulator. Move the setting of the supply name from arizona_micsupp_common_init() to arizona_micsupp_probe() and madera_micsupp_probe(). Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- drivers/regulator/arizona-micsupp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/regulator/arizona-micsupp.c b/drivers/regulator/arizona-micsupp.c index 21c36972a8e9..596ecd8041cd 100644 --- a/drivers/regulator/arizona-micsupp.c +++ b/drivers/regulator/arizona-micsupp.c @@ -262,7 +262,6 @@ static int arizona_micsupp_common_init(struct platform_device *pdev, INIT_WORK(&micsupp->check_cp_work, arizona_micsupp_check_cp); micsupp->init_data.consumer_supplies = &micsupp->supply; - micsupp->supply.supply = "MICVDD"; micsupp->supply.dev_name = dev_name(micsupp->dev); micsupp->desc = desc; @@ -319,6 +318,8 @@ static int arizona_micsupp_probe(struct platform_device *pdev) micsupp->dapm = &arizona->dapm; micsupp->dev = arizona->dev; + micsupp->supply.supply = "MICVDD"; + /* * Since the chip usually supplies itself we provide some * default init_data for it. This will be overridden with @@ -354,6 +355,8 @@ static int madera_micsupp_probe(struct platform_device *pdev) micsupp->dev = madera->dev; micsupp->init_data = arizona_micsupp_ext_default; + micsupp->supply.supply = "MICVDD"; + return arizona_micsupp_common_init(pdev, micsupp, &madera_micsupp, &madera->pdata.micvdd); } -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 08/12] regulator: arizona-micsupp: Support Cirrus Logic CS48L31/32/33 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-09 16:53 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches, Richard Fitzgerald This adds a new driver identity "cs48l32-micsupp" and probe function so that this driver can be used to control the micsupp regulator on Cirrus Logic CS48L31/32/33 audio codecs. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- drivers/regulator/Kconfig | 8 ++-- drivers/regulator/arizona-micsupp.c | 58 +++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 4 deletions(-) diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 070e4403c6c2..1d6813b24f85 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -139,12 +139,12 @@ config REGULATOR_ARIZONA_LDO1 config REGULATOR_ARIZONA_MICSUPP tristate "Cirrus Madera and Wolfson Arizona class devices MICSUPP" - depends on MFD_ARIZONA || MFD_MADERA + depends on MFD_ARIZONA || MFD_MADERA || MFD_CS48L32 depends on SND_SOC help - Support for the MICSUPP regulators found on Cirrus Logic Madera codecs - and Wolfson Microelectronic Arizona codecs - devices. + Support for the MICSUPP regulators found on Cirrus Logic Madera, + Cirrus Logic CS48L31/32/33, and on Wolfson Microelectronic + Arizona codecs. config REGULATOR_ARM_SCMI tristate "SCMI based regulator driver" diff --git a/drivers/regulator/arizona-micsupp.c b/drivers/regulator/arizona-micsupp.c index 596ecd8041cd..bf154067ed34 100644 --- a/drivers/regulator/arizona-micsupp.c +++ b/drivers/regulator/arizona-micsupp.c @@ -24,6 +24,9 @@ #include <linux/mfd/arizona/pdata.h> #include <linux/mfd/arizona/registers.h> +#include <linux/mfd/cs48l32/core.h> +#include <linux/mfd/cs48l32/registers.h> + #include <linux/mfd/madera/core.h> #include <linux/mfd/madera/pdata.h> #include <linux/mfd/madera/registers.h> @@ -225,6 +228,28 @@ static const struct regulator_desc madera_micsupp = { .owner = THIS_MODULE, }; +static const struct regulator_desc cs48l32_micsupp = { + .name = "VOUT_MIC", + .supply_name = "VDD_CP", + .type = REGULATOR_VOLTAGE, + .n_voltages = 40, + .ops = &arizona_micsupp_ops, + + .vsel_reg = CS48L32_LDO2_CTRL1, + .vsel_mask = CS48L32_LDO2_VSEL_MASK, + .enable_reg = CS48L32_CHARGE_PUMP1, + .enable_mask = CS48L32_CP2_EN_MASK, + .bypass_reg = CS48L32_CHARGE_PUMP1, + .bypass_mask = CS48L32_CP2_BYPASS_MASK, + + .linear_ranges = arizona_micsupp_ext_ranges, + .n_linear_ranges = ARRAY_SIZE(arizona_micsupp_ext_ranges), + + .enable_time = 3000, + + .owner = THIS_MODULE, +}; + static int arizona_micsupp_of_get_pdata(struct arizona_micsupp_pdata *pdata, struct regulator_config *config, const struct regulator_desc *desc) @@ -361,6 +386,29 @@ static int madera_micsupp_probe(struct platform_device *pdev) &madera->pdata.micvdd); } +static int cs48l32_micsupp_probe(struct platform_device *pdev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(pdev->dev.parent); + struct arizona_micsupp *micsupp; + struct arizona_micsupp_pdata *pdata; + + micsupp = devm_kzalloc(&pdev->dev, sizeof(*micsupp), GFP_KERNEL); + if (!micsupp) + return -ENOMEM; + + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + micsupp->regmap = mfd->regmap; + micsupp->dapm = &mfd->dapm; + micsupp->dev = mfd->dev; + micsupp->init_data = arizona_micsupp_ext_default; + micsupp->supply.supply = "VOUT_MIC"; + + return arizona_micsupp_common_init(pdev, micsupp, &cs48l32_micsupp, pdata); +} + static struct platform_driver arizona_micsupp_driver = { .probe = arizona_micsupp_probe, .driver = { @@ -375,9 +423,17 @@ static struct platform_driver madera_micsupp_driver = { }, }; +static struct platform_driver cs48l32_micsupp_driver = { + .probe = cs48l32_micsupp_probe, + .driver = { + .name = "cs48l32-micsupp", + }, +}; + static struct platform_driver * const arizona_micsupp_drivers[] = { &arizona_micsupp_driver, &madera_micsupp_driver, + &cs48l32_micsupp_driver, }; static int __init arizona_micsupp_init(void) @@ -396,7 +452,9 @@ module_exit(arizona_micsupp_exit); /* Module information */ MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); +MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); MODULE_DESCRIPTION("Arizona microphone supply driver"); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:arizona-micsupp"); +MODULE_ALIAS("platform:cs48l32-micsupp"); MODULE_ALIAS("platform:madera-micsupp"); -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 08/12] regulator: arizona-micsupp: Support Cirrus Logic CS48L31/32/33 @ 2022-11-09 16:53 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio, Richard Fitzgerald This adds a new driver identity "cs48l32-micsupp" and probe function so that this driver can be used to control the micsupp regulator on Cirrus Logic CS48L31/32/33 audio codecs. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- drivers/regulator/Kconfig | 8 ++-- drivers/regulator/arizona-micsupp.c | 58 +++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 4 deletions(-) diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 070e4403c6c2..1d6813b24f85 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -139,12 +139,12 @@ config REGULATOR_ARIZONA_LDO1 config REGULATOR_ARIZONA_MICSUPP tristate "Cirrus Madera and Wolfson Arizona class devices MICSUPP" - depends on MFD_ARIZONA || MFD_MADERA + depends on MFD_ARIZONA || MFD_MADERA || MFD_CS48L32 depends on SND_SOC help - Support for the MICSUPP regulators found on Cirrus Logic Madera codecs - and Wolfson Microelectronic Arizona codecs - devices. + Support for the MICSUPP regulators found on Cirrus Logic Madera, + Cirrus Logic CS48L31/32/33, and on Wolfson Microelectronic + Arizona codecs. config REGULATOR_ARM_SCMI tristate "SCMI based regulator driver" diff --git a/drivers/regulator/arizona-micsupp.c b/drivers/regulator/arizona-micsupp.c index 596ecd8041cd..bf154067ed34 100644 --- a/drivers/regulator/arizona-micsupp.c +++ b/drivers/regulator/arizona-micsupp.c @@ -24,6 +24,9 @@ #include <linux/mfd/arizona/pdata.h> #include <linux/mfd/arizona/registers.h> +#include <linux/mfd/cs48l32/core.h> +#include <linux/mfd/cs48l32/registers.h> + #include <linux/mfd/madera/core.h> #include <linux/mfd/madera/pdata.h> #include <linux/mfd/madera/registers.h> @@ -225,6 +228,28 @@ static const struct regulator_desc madera_micsupp = { .owner = THIS_MODULE, }; +static const struct regulator_desc cs48l32_micsupp = { + .name = "VOUT_MIC", + .supply_name = "VDD_CP", + .type = REGULATOR_VOLTAGE, + .n_voltages = 40, + .ops = &arizona_micsupp_ops, + + .vsel_reg = CS48L32_LDO2_CTRL1, + .vsel_mask = CS48L32_LDO2_VSEL_MASK, + .enable_reg = CS48L32_CHARGE_PUMP1, + .enable_mask = CS48L32_CP2_EN_MASK, + .bypass_reg = CS48L32_CHARGE_PUMP1, + .bypass_mask = CS48L32_CP2_BYPASS_MASK, + + .linear_ranges = arizona_micsupp_ext_ranges, + .n_linear_ranges = ARRAY_SIZE(arizona_micsupp_ext_ranges), + + .enable_time = 3000, + + .owner = THIS_MODULE, +}; + static int arizona_micsupp_of_get_pdata(struct arizona_micsupp_pdata *pdata, struct regulator_config *config, const struct regulator_desc *desc) @@ -361,6 +386,29 @@ static int madera_micsupp_probe(struct platform_device *pdev) &madera->pdata.micvdd); } +static int cs48l32_micsupp_probe(struct platform_device *pdev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(pdev->dev.parent); + struct arizona_micsupp *micsupp; + struct arizona_micsupp_pdata *pdata; + + micsupp = devm_kzalloc(&pdev->dev, sizeof(*micsupp), GFP_KERNEL); + if (!micsupp) + return -ENOMEM; + + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + micsupp->regmap = mfd->regmap; + micsupp->dapm = &mfd->dapm; + micsupp->dev = mfd->dev; + micsupp->init_data = arizona_micsupp_ext_default; + micsupp->supply.supply = "VOUT_MIC"; + + return arizona_micsupp_common_init(pdev, micsupp, &cs48l32_micsupp, pdata); +} + static struct platform_driver arizona_micsupp_driver = { .probe = arizona_micsupp_probe, .driver = { @@ -375,9 +423,17 @@ static struct platform_driver madera_micsupp_driver = { }, }; +static struct platform_driver cs48l32_micsupp_driver = { + .probe = cs48l32_micsupp_probe, + .driver = { + .name = "cs48l32-micsupp", + }, +}; + static struct platform_driver * const arizona_micsupp_drivers[] = { &arizona_micsupp_driver, &madera_micsupp_driver, + &cs48l32_micsupp_driver, }; static int __init arizona_micsupp_init(void) @@ -396,7 +452,9 @@ module_exit(arizona_micsupp_exit); /* Module information */ MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); +MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); MODULE_DESCRIPTION("Arizona microphone supply driver"); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:arizona-micsupp"); +MODULE_ALIAS("platform:cs48l32-micsupp"); MODULE_ALIAS("platform:madera-micsupp"); -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-09 16:53 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches, Richard Fitzgerald The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable interrupt controller with a variety of interrupt sources, including GPIOs that can be used as interrupt inputs. This driver provides the handling for the interrupt controller. As the codec is accessed via regmap, the generic regmap_irq functionality is used to do most of the work. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- MAINTAINERS | 2 + drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-cirrus-cs48l32.c | 281 +++++++++++++++++++++ drivers/irqchip/irq-cirrus-cs48l32.h | 74 ++++++ include/linux/irqchip/irq-cirrus-cs48l32.h | 101 ++++++++ 6 files changed, 462 insertions(+) create mode 100644 drivers/irqchip/irq-cirrus-cs48l32.c create mode 100644 drivers/irqchip/irq-cirrus-cs48l32.h create mode 100644 include/linux/irqchip/irq-cirrus-cs48l32.h diff --git a/MAINTAINERS b/MAINTAINERS index cd1773d39dd8..f52e9a6e290c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5015,12 +5015,14 @@ F: Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml F: Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml F: Documentation/devicetree/bindings/sound/cirrus,madera.yaml F: drivers/gpio/gpio-madera* +F: drivers/irqchip/irq-cirrus-cs48l32* F: drivers/irqchip/irq-madera* F: drivers/mfd/cs47l* F: drivers/mfd/cs48l* F: drivers/mfd/madera* F: drivers/pinctrl/cirrus/* F: include/dt-bindings/sound/madera* +F: include/linux/irqchip/irq-cirrus-cs48l32* F: include/linux/irqchip/irq-madera* F: include/linux/mfd/cs48l32/* F: include/linux/mfd/madera/* diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 7ef9f5e696d3..d4521158849c 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -136,6 +136,9 @@ config BRCMSTB_L2_IRQ select GENERIC_IRQ_CHIP select IRQ_DOMAIN +config CIRRUS_CS48L32_IRQ + tristate + config DAVINCI_AINTC bool select GENERIC_IRQ_CHIP diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 87b49a10962c..049796365232 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -121,3 +121,4 @@ obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o +obj-$(CONFIG_CIRRUS_CS48L32_IRQ) += irq-cirrus-cs48l32.o diff --git a/drivers/irqchip/irq-cirrus-cs48l32.c b/drivers/irqchip/irq-cirrus-cs48l32.c new file mode 100644 index 000000000000..3ca9f34a6289 --- /dev/null +++ b/drivers/irqchip/irq-cirrus-cs48l32.c @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Interrupt support for Cirrus Logic CS48L32 audio codec +// +// Copyright (C) 2020, 2022 Cirrus Logic, Inc. and +// Cirrus Logic International Semiconductor Ltd. + +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/irqchip/irq-cirrus-cs48l32.h> +#include <linux/irqdomain.h> +#include <linux/mfd/cs48l32/core.h> +#include <linux/mfd/cs48l32/registers.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <linux/slab.h> + +#include "irq-cirrus-cs48l32.h" + +#define CS48L32_IRQ(_irq, _reg) \ + [CS48L32_IRQ_ ## _irq] = { \ + .reg_offset = (_reg) - CS48L32_IRQ1_EINT_1, \ + .mask = CS48L32_ ## _irq ## _EINT1_MASK \ + } + +static const struct regmap_irq cs48l32_irqs[] = { + CS48L32_IRQ(DSP1_IRQ0, CS48L32_IRQ1_EINT_9), + CS48L32_IRQ(DSP1_IRQ1, CS48L32_IRQ1_EINT_9), + CS48L32_IRQ(DSP1_IRQ2, CS48L32_IRQ1_EINT_9), + CS48L32_IRQ(DSP1_IRQ3, CS48L32_IRQ1_EINT_9), + + CS48L32_IRQ(US1_ACT_DET_RISE, CS48L32_IRQ1_EINT_5), + CS48L32_IRQ(US1_ACT_DET_FALL, CS48L32_IRQ1_EINT_5), + CS48L32_IRQ(US2_ACT_DET_RISE, CS48L32_IRQ1_EINT_5), + CS48L32_IRQ(US2_ACT_DET_FALL, CS48L32_IRQ1_EINT_5), + + CS48L32_IRQ(INPUTS_SIG_DET_RISE, CS48L32_IRQ1_EINT_5), + CS48L32_IRQ(INPUTS_SIG_DET_FALL, CS48L32_IRQ1_EINT_5), + + CS48L32_IRQ(GPIO1_RISE, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO1_FALL, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO2_RISE, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO2_FALL, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO3_RISE, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO3_FALL, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO4_RISE, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO4_FALL, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO5_RISE, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO5_FALL, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO6_RISE, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO6_FALL, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO7_RISE, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO7_FALL, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO8_RISE, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO8_FALL, CS48L32_IRQ1_EINT_11), + + CS48L32_IRQ(DRC1_SIG_DET_RISE, CS48L32_IRQ1_EINT_5), + CS48L32_IRQ(DRC1_SIG_DET_FALL, CS48L32_IRQ1_EINT_5), + CS48L32_IRQ(DRC2_SIG_DET_RISE, CS48L32_IRQ1_EINT_5), + CS48L32_IRQ(DRC2_SIG_DET_FALL, CS48L32_IRQ1_EINT_5), + + CS48L32_IRQ(FLL1_LOCK_RISE, CS48L32_IRQ1_EINT_6), + CS48L32_IRQ(FLL1_LOCK_FALL, CS48L32_IRQ1_EINT_6), + CS48L32_IRQ(FLL1_REF_LOST, CS48L32_IRQ1_EINT_6), + + CS48L32_IRQ(SYSCLK_FAIL, CS48L32_IRQ1_EINT_1), + CS48L32_IRQ(CTRLIF_ERR, CS48L32_IRQ1_EINT_1), + CS48L32_IRQ(SYSCLK_ERR, CS48L32_IRQ1_EINT_1), + CS48L32_IRQ(DSPCLK_ERR, CS48L32_IRQ1_EINT_1), + + CS48L32_IRQ(DSP1_NMI_ERR, CS48L32_IRQ1_EINT_7), + CS48L32_IRQ(DSP1_WDT_EXPIRE, CS48L32_IRQ1_EINT_7), + CS48L32_IRQ(DSP1_MPU_ERR, CS48L32_IRQ1_EINT_7), + + CS48L32_IRQ(BOOT_DONE, CS48L32_IRQ1_EINT_2), +}; + +static const struct regmap_irq_chip cs48l32_irqchip = { + .name = "CS48L32 IRQ", + .status_base = CS48L32_IRQ1_EINT_1, + .mask_base = CS48L32_IRQ1_MASK_1, + .ack_base = CS48L32_IRQ1_EINT_1, + .runtime_pm = true, + .num_regs = 11, + .irqs = cs48l32_irqs, + .num_irqs = ARRAY_SIZE(cs48l32_irqs), +}; + +static int __maybe_unused cs48l32_suspend(struct device *dev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(dev->parent); + + dev_dbg(mfd->irq_dev, "Suspend, disabling IRQ\n"); + + /* + * A runtime resume would be needed to access the chip interrupt + * controller but runtime pm doesn't function during suspend. + * Temporarily disable interrupts until we reach suspend_noirq state. + */ + disable_irq(mfd->irq); + + return 0; +} + +static int __maybe_unused cs48l32_suspend_noirq(struct device *dev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(dev->parent); + + dev_dbg(mfd->irq_dev, "No IRQ suspend, reenabling IRQ\n"); + + /* Re-enable interrupts to service wakeup interrupts from the chip */ + enable_irq(mfd->irq); + + return 0; +} + +static int __maybe_unused cs48l32_resume_noirq(struct device *dev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(dev->parent); + + dev_dbg(mfd->irq_dev, "No IRQ resume, disabling IRQ\n"); + + /* + * We can't handle interrupts until runtime pm is available again. + * Disable them temporarily. + */ + disable_irq(mfd->irq); + + return 0; +} + +static int __maybe_unused cs48l32_resume(struct device *dev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(dev->parent); + + dev_dbg(mfd->irq_dev, "Resume, enabling IRQ\n"); + + /* Interrupts can now be handled */ + enable_irq(mfd->irq); + + return 0; +} + +static const struct dev_pm_ops cs48l32_irq_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(cs48l32_suspend, cs48l32_resume) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cs48l32_suspend_noirq, cs48l32_resume_noirq) +}; + +static irqreturn_t cs48l32_sysclk_fail(int irq, void *data) +{ + struct cs48l32_mfd *mfd = data; + + dev_warn(mfd->dev, "SYSCLK fail\n"); + + return IRQ_HANDLED; +} + +static irqreturn_t cs48l32_sysclk_error(int irq, void *data) +{ + struct cs48l32_mfd *mfd = data; + + dev_warn(mfd->dev, "SYSCLK error\n"); + + return IRQ_HANDLED; +} + +static irqreturn_t cs48l32_ctrlif_error(int irq, void *data) +{ + struct cs48l32_mfd *mfd = data; + + dev_warn(mfd->dev, "CTRLIF error\n"); + + return IRQ_HANDLED; +} + +static irqreturn_t cs48l32_boot_done(int irq, void *data) +{ + struct cs48l32_mfd *mfd = data; + + dev_dbg(mfd->dev, "BOOT_DONE\n"); + + return IRQ_HANDLED; +} + +static int cs48l32_irq_probe(struct platform_device *pdev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(pdev->dev.parent); + struct irq_data *irq_data; + unsigned int irq_flags; + int ret; + + irq_data = irq_get_irq_data(mfd->irq); + if (!irq_data) + return dev_err_probe(&pdev->dev, -EINVAL, "Invalid IRQ: %d\n", mfd->irq); + + irq_flags = irqd_get_trigger_type(irq_data); + + /* Codec defaults to trigger low, use this if no flags given */ + if (irq_flags == IRQ_TYPE_NONE) + irq_flags = IRQF_TRIGGER_LOW; + + if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) + return dev_err_probe(&pdev->dev, -EINVAL, "Host interrupt not level-triggered\n"); + + /* + * The silicon always starts at active-low, check if we need to + * switch to active-high. + */ + if (irq_flags & IRQF_TRIGGER_HIGH) + ret = regmap_clear_bits(mfd->regmap, CS48L32_IRQ1_CTRL_AOD, + CS48L32_IRQ_POL_MASK); + else + ret = regmap_set_bits(mfd->regmap, CS48L32_IRQ1_CTRL_AOD, + CS48L32_IRQ_POL_MASK); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Failed to set IRQ polarity\n"); + + /* + * NOTE: regmap registers this against the OF node of the parent of + * the regmap - that is, against the mfd driver + */ + ret = regmap_add_irq_chip(mfd->regmap, mfd->irq, IRQF_ONESHOT, 0, + &cs48l32_irqchip, &mfd->irq_data); + if (ret) + return dev_err_probe(&pdev->dev, ret, "add_irq_chip failed\n"); + + /* Save dev in parent MFD struct so it is accessible to siblings */ + mfd->irq_dev = &pdev->dev; + + /* + * Log global chip error conditions that aren't specific to + * any particular sibling driver. + */ + cs48l32_request_irq(mfd, CS48L32_IRQ_SYSCLK_FAIL, "SYSCLK fail", + cs48l32_sysclk_fail, mfd); + cs48l32_request_irq(mfd, CS48L32_IRQ_SYSCLK_ERR, "SYSCLK error", + cs48l32_sysclk_error, mfd); + cs48l32_request_irq(mfd, CS48L32_IRQ_CTRLIF_ERR, "CTRLIF error", + cs48l32_ctrlif_error, mfd); + cs48l32_request_irq(mfd, CS48L32_IRQ_BOOT_DONE, "BOOT_DONE", + cs48l32_boot_done, mfd); + + return 0; +} + +static int cs48l32_irq_remove(struct platform_device *pdev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(pdev->dev.parent); + + /* + * The IRQ is disabled by the parent MFD driver before + * it starts cleaning up all child drivers + */ + cs48l32_free_irq(mfd, CS48L32_IRQ_BOOT_DONE, mfd); + cs48l32_free_irq(mfd, CS48L32_IRQ_CTRLIF_ERR, mfd); + cs48l32_free_irq(mfd, CS48L32_IRQ_SYSCLK_ERR, mfd); + cs48l32_free_irq(mfd, CS48L32_IRQ_SYSCLK_FAIL, mfd); + + mfd->irq_dev = NULL; + regmap_del_irq_chip(mfd->irq, mfd->irq_data); + + return 0; +} + +static struct platform_driver cs48l32_irq_driver = { + .probe = &cs48l32_irq_probe, + .remove = &cs48l32_irq_remove, + .driver = { + .name = "cs48l32-irq", + .pm = &cs48l32_irq_pm_ops, + } +}; + +module_platform_driver(cs48l32_irq_driver); + +MODULE_DESCRIPTION("CS48L32 IRQ driver"); +MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/irqchip/irq-cirrus-cs48l32.h b/drivers/irqchip/irq-cirrus-cs48l32.h new file mode 100644 index 000000000000..6dae6ddf724d --- /dev/null +++ b/drivers/irqchip/irq-cirrus-cs48l32.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Interrupt support for Cirrus Logic CS48L32 audio codec + * + * Copyright (C) 2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef IRQ_CIRRUS_CS48L32_H +#define IRQ_CIRRUS_CS48L32_H + +/* (0x18010) IRQ1_EINT_1 */ +#define CS48L32_DSPCLK_ERR_EINT1_MASK 0x00001000 +#define CS48L32_SYSCLK_ERR_EINT1_MASK 0x00000400 +#define CS48L32_CTRLIF_ERR_EINT1_MASK 0x00000200 +#define CS48L32_SYSCLK_FAIL_EINT1_MASK 0x00000100 + +/* (0x18014) IRQ1_EINT_2 */ +#define CS48L32_BOOT_DONE_EINT1_MASK 0x00000008 + +/* (0x18020) IRQ1_EINT_5 */ +#define CS48L32_US2_ACT_DET_FALL_EINT1_MASK 0x02000000 +#define CS48L32_US2_ACT_DET_RISE_EINT1_MASK 0x01000000 +#define CS48L32_US1_ACT_DET_FALL_EINT1_MASK 0x00800000 +#define CS48L32_US1_ACT_DET_RISE_EINT1_MASK 0x00400000 +#define CS48L32_INPUTS_SIG_DET_FALL_EINT1_MASK 0x00200000 +#define CS48L32_INPUTS_SIG_DET_RISE_EINT1_MASK 0x00100000 +#define CS48L32_DRC2_SIG_DET_FALL_EINT1_MASK 0x00080000 +#define CS48L32_DRC2_SIG_DET_RISE_EINT1_MASK 0x00040000 +#define CS48L32_DRC1_SIG_DET_FALL_EINT1_MASK 0x00020000 +#define CS48L32_DRC1_SIG_DET_RISE_EINT1_MASK 0x00010000 + +/* (0x18024) IRQ1_EINT_6 */ +#define CS48L32_FLL1_REF_LOST_EINT1_MASK 0x00000100 +#define CS48L32_FLL1_LOCK_FALL_EINT1_MASK 0x00000002 +#define CS48L32_FLL1_LOCK_RISE_EINT1_MASK 0x00000001 + +/* (0x18028) IRQ1_EINT_7 */ +#define CS48L32_DSP1_MPU_ERR_EINT1_MASK 0x00200000 +#define CS48L32_DSP1_WDT_EXPIRE_EINT1_MASK 0x00100000 +#define CS48L32_DSP1_IHB_ERR_EINT1_MASK 0x00080000 +#define CS48L32_DSP1_AHB_SYS_ERR_EINT1_MASK 0x00040000 +#define CS48L32_DSP1_AHB_PACK_ERR_EINT1_MASK 0x00020000 +#define CS48L32_DSP1_NMI_ERR_EINT1_MASK 0x00010000 + +/* (0x18030) IRQ1_EINT_9 */ +#define CS48L32_MCU_HWERR_IRQ_OUT_EINT1_MASK 0x80000000 +#define CS48L32_DSP1_IRQ3_EINT1_MASK 0x00000008 +#define CS48L32_DSP1_IRQ2_EINT1_MASK 0x00000004 +#define CS48L32_DSP1_IRQ1_EINT1_MASK 0x00000002 +#define CS48L32_DSP1_IRQ0_EINT1_MASK 0x00000001 + +/* (0x18034) IRQ1_EINT_10 */ +#define CS48L32_CLOCK_DETECT_EINT1_MASK 0x01000000 + +/* (0x18038) IRQ1_EINT_11 */ +#define CS48L32_GPIO8_FALL_EINT1_MASK 0x80000000 +#define CS48L32_GPIO8_RISE_EINT1_MASK 0x40000000 +#define CS48L32_GPIO7_FALL_EINT1_MASK 0x20000000 +#define CS48L32_GPIO7_RISE_EINT1_MASK 0x10000000 +#define CS48L32_GPIO6_FALL_EINT1_MASK 0x08000000 +#define CS48L32_GPIO6_RISE_EINT1_MASK 0x04000000 +#define CS48L32_GPIO5_FALL_EINT1_MASK 0x02000000 +#define CS48L32_GPIO5_RISE_EINT1_MASK 0x01000000 +#define CS48L32_GPIO4_FALL_EINT1_MASK 0x00800000 +#define CS48L32_GPIO4_RISE_EINT1_MASK 0x00400000 +#define CS48L32_GPIO3_FALL_EINT1_MASK 0x00200000 +#define CS48L32_GPIO3_RISE_EINT1_MASK 0x00100000 +#define CS48L32_GPIO2_FALL_EINT1_MASK 0x00080000 +#define CS48L32_GPIO2_RISE_EINT1_MASK 0x00040000 +#define CS48L32_GPIO1_FALL_EINT1_MASK 0x00020000 +#define CS48L32_GPIO1_RISE_EINT1_MASK 0x00010000 + +#endif diff --git a/include/linux/irqchip/irq-cirrus-cs48l32.h b/include/linux/irqchip/irq-cirrus-cs48l32.h new file mode 100644 index 000000000000..c94d31cef96f --- /dev/null +++ b/include/linux/irqchip/irq-cirrus-cs48l32.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Interrupt support for Cirrus Logic CS48L32 audio codec + * + * Copyright (C) 2017-2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef IRQCHIP_CIRRUS_CS48L32_H +#define IRQCHIP_CIRRUS_CS48L32_H + +#include <linux/interrupt.h> +#include <linux/mfd/cs48l32/core.h> + +/* Main interrupts, organized by priority order - highest first */ +#define CS48L32_IRQ_DSP1_IRQ0 0 +#define CS48L32_IRQ_DSP1_IRQ1 1 +#define CS48L32_IRQ_DSP1_IRQ2 2 +#define CS48L32_IRQ_DSP1_IRQ3 3 +#define CS48L32_IRQ_US1_ACT_DET_RISE 4 +#define CS48L32_IRQ_US1_ACT_DET_FALL 5 +#define CS48L32_IRQ_US2_ACT_DET_RISE 6 +#define CS48L32_IRQ_US2_ACT_DET_FALL 7 +#define CS48L32_IRQ_INPUTS_SIG_DET_RISE 8 +#define CS48L32_IRQ_INPUTS_SIG_DET_FALL 9 +#define CS48L32_IRQ_GPIO1_RISE 10 +#define CS48L32_IRQ_GPIO1_FALL 11 +#define CS48L32_IRQ_GPIO2_RISE 12 +#define CS48L32_IRQ_GPIO2_FALL 13 +#define CS48L32_IRQ_GPIO3_RISE 14 +#define CS48L32_IRQ_GPIO3_FALL 15 +#define CS48L32_IRQ_GPIO4_RISE 16 +#define CS48L32_IRQ_GPIO4_FALL 17 +#define CS48L32_IRQ_GPIO5_RISE 18 +#define CS48L32_IRQ_GPIO5_FALL 19 +#define CS48L32_IRQ_GPIO6_RISE 20 +#define CS48L32_IRQ_GPIO6_FALL 21 +#define CS48L32_IRQ_GPIO7_RISE 22 +#define CS48L32_IRQ_GPIO7_FALL 23 +#define CS48L32_IRQ_GPIO8_RISE 24 +#define CS48L32_IRQ_GPIO8_FALL 25 +#define CS48L32_IRQ_DRC1_SIG_DET_RISE 26 +#define CS48L32_IRQ_DRC1_SIG_DET_FALL 27 +#define CS48L32_IRQ_DRC2_SIG_DET_RISE 28 +#define CS48L32_IRQ_DRC2_SIG_DET_FALL 29 +#define CS48L32_IRQ_FLL1_LOCK_RISE 30 +#define CS48L32_IRQ_FLL1_LOCK_FALL 31 +#define CS48L32_IRQ_FLL1_REF_LOST 32 +#define CS48L32_IRQ_SYSCLK_FAIL 33 +#define CS48L32_IRQ_CTRLIF_ERR 34 +#define CS48L32_IRQ_SYSCLK_ERR 35 +#define CS48L32_IRQ_DSPCLK_ERR 36 +#define CS48L32_IRQ_DSP1_NMI_ERR 37 +#define CS48L32_IRQ_DSP1_WDT_EXPIRE 38 +#define CS48L32_IRQ_DSP1_MPU_ERR 39 +#define CS48L32_IRQ_BOOT_DONE 40 + +struct cs48l32_mfd; + +/* + * These wrapper functions are for use by other child drivers of the + * same parent MFD. + */ +static inline int cs48l32_get_irq_mapping(struct cs48l32_mfd *cs48l32, int irq) +{ + if (!cs48l32->irq_dev) + return -ENODEV; + + return regmap_irq_get_virq(cs48l32->irq_data, irq); +} + +static inline int cs48l32_request_irq(struct cs48l32_mfd *cs48l32, int irq, + const char *name, + irq_handler_t handler, void *data) +{ + irq = cs48l32_get_irq_mapping(cs48l32, irq); + if (irq < 0) + return irq; + + return request_threaded_irq(irq, NULL, handler, IRQF_ONESHOT, name, data); +} + +static inline void cs48l32_free_irq(struct cs48l32_mfd *cs48l32, int irq, void *data) +{ + irq = cs48l32_get_irq_mapping(cs48l32, irq); + if (irq < 0) + return; + + free_irq(irq, data); +} + +static inline int cs48l32_set_irq_wake(struct cs48l32_mfd *cs48l32, int irq, int on) +{ + irq = cs48l32_get_irq_mapping(cs48l32, irq); + if (irq < 0) + return irq; + + return irq_set_irq_wake(irq, on); +} + +#endif -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-09 16:53 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio, Richard Fitzgerald The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable interrupt controller with a variety of interrupt sources, including GPIOs that can be used as interrupt inputs. This driver provides the handling for the interrupt controller. As the codec is accessed via regmap, the generic regmap_irq functionality is used to do most of the work. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- MAINTAINERS | 2 + drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-cirrus-cs48l32.c | 281 +++++++++++++++++++++ drivers/irqchip/irq-cirrus-cs48l32.h | 74 ++++++ include/linux/irqchip/irq-cirrus-cs48l32.h | 101 ++++++++ 6 files changed, 462 insertions(+) create mode 100644 drivers/irqchip/irq-cirrus-cs48l32.c create mode 100644 drivers/irqchip/irq-cirrus-cs48l32.h create mode 100644 include/linux/irqchip/irq-cirrus-cs48l32.h diff --git a/MAINTAINERS b/MAINTAINERS index cd1773d39dd8..f52e9a6e290c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5015,12 +5015,14 @@ F: Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml F: Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml F: Documentation/devicetree/bindings/sound/cirrus,madera.yaml F: drivers/gpio/gpio-madera* +F: drivers/irqchip/irq-cirrus-cs48l32* F: drivers/irqchip/irq-madera* F: drivers/mfd/cs47l* F: drivers/mfd/cs48l* F: drivers/mfd/madera* F: drivers/pinctrl/cirrus/* F: include/dt-bindings/sound/madera* +F: include/linux/irqchip/irq-cirrus-cs48l32* F: include/linux/irqchip/irq-madera* F: include/linux/mfd/cs48l32/* F: include/linux/mfd/madera/* diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 7ef9f5e696d3..d4521158849c 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -136,6 +136,9 @@ config BRCMSTB_L2_IRQ select GENERIC_IRQ_CHIP select IRQ_DOMAIN +config CIRRUS_CS48L32_IRQ + tristate + config DAVINCI_AINTC bool select GENERIC_IRQ_CHIP diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 87b49a10962c..049796365232 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -121,3 +121,4 @@ obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o +obj-$(CONFIG_CIRRUS_CS48L32_IRQ) += irq-cirrus-cs48l32.o diff --git a/drivers/irqchip/irq-cirrus-cs48l32.c b/drivers/irqchip/irq-cirrus-cs48l32.c new file mode 100644 index 000000000000..3ca9f34a6289 --- /dev/null +++ b/drivers/irqchip/irq-cirrus-cs48l32.c @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Interrupt support for Cirrus Logic CS48L32 audio codec +// +// Copyright (C) 2020, 2022 Cirrus Logic, Inc. and +// Cirrus Logic International Semiconductor Ltd. + +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/irqchip/irq-cirrus-cs48l32.h> +#include <linux/irqdomain.h> +#include <linux/mfd/cs48l32/core.h> +#include <linux/mfd/cs48l32/registers.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <linux/slab.h> + +#include "irq-cirrus-cs48l32.h" + +#define CS48L32_IRQ(_irq, _reg) \ + [CS48L32_IRQ_ ## _irq] = { \ + .reg_offset = (_reg) - CS48L32_IRQ1_EINT_1, \ + .mask = CS48L32_ ## _irq ## _EINT1_MASK \ + } + +static const struct regmap_irq cs48l32_irqs[] = { + CS48L32_IRQ(DSP1_IRQ0, CS48L32_IRQ1_EINT_9), + CS48L32_IRQ(DSP1_IRQ1, CS48L32_IRQ1_EINT_9), + CS48L32_IRQ(DSP1_IRQ2, CS48L32_IRQ1_EINT_9), + CS48L32_IRQ(DSP1_IRQ3, CS48L32_IRQ1_EINT_9), + + CS48L32_IRQ(US1_ACT_DET_RISE, CS48L32_IRQ1_EINT_5), + CS48L32_IRQ(US1_ACT_DET_FALL, CS48L32_IRQ1_EINT_5), + CS48L32_IRQ(US2_ACT_DET_RISE, CS48L32_IRQ1_EINT_5), + CS48L32_IRQ(US2_ACT_DET_FALL, CS48L32_IRQ1_EINT_5), + + CS48L32_IRQ(INPUTS_SIG_DET_RISE, CS48L32_IRQ1_EINT_5), + CS48L32_IRQ(INPUTS_SIG_DET_FALL, CS48L32_IRQ1_EINT_5), + + CS48L32_IRQ(GPIO1_RISE, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO1_FALL, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO2_RISE, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO2_FALL, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO3_RISE, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO3_FALL, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO4_RISE, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO4_FALL, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO5_RISE, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO5_FALL, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO6_RISE, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO6_FALL, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO7_RISE, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO7_FALL, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO8_RISE, CS48L32_IRQ1_EINT_11), + CS48L32_IRQ(GPIO8_FALL, CS48L32_IRQ1_EINT_11), + + CS48L32_IRQ(DRC1_SIG_DET_RISE, CS48L32_IRQ1_EINT_5), + CS48L32_IRQ(DRC1_SIG_DET_FALL, CS48L32_IRQ1_EINT_5), + CS48L32_IRQ(DRC2_SIG_DET_RISE, CS48L32_IRQ1_EINT_5), + CS48L32_IRQ(DRC2_SIG_DET_FALL, CS48L32_IRQ1_EINT_5), + + CS48L32_IRQ(FLL1_LOCK_RISE, CS48L32_IRQ1_EINT_6), + CS48L32_IRQ(FLL1_LOCK_FALL, CS48L32_IRQ1_EINT_6), + CS48L32_IRQ(FLL1_REF_LOST, CS48L32_IRQ1_EINT_6), + + CS48L32_IRQ(SYSCLK_FAIL, CS48L32_IRQ1_EINT_1), + CS48L32_IRQ(CTRLIF_ERR, CS48L32_IRQ1_EINT_1), + CS48L32_IRQ(SYSCLK_ERR, CS48L32_IRQ1_EINT_1), + CS48L32_IRQ(DSPCLK_ERR, CS48L32_IRQ1_EINT_1), + + CS48L32_IRQ(DSP1_NMI_ERR, CS48L32_IRQ1_EINT_7), + CS48L32_IRQ(DSP1_WDT_EXPIRE, CS48L32_IRQ1_EINT_7), + CS48L32_IRQ(DSP1_MPU_ERR, CS48L32_IRQ1_EINT_7), + + CS48L32_IRQ(BOOT_DONE, CS48L32_IRQ1_EINT_2), +}; + +static const struct regmap_irq_chip cs48l32_irqchip = { + .name = "CS48L32 IRQ", + .status_base = CS48L32_IRQ1_EINT_1, + .mask_base = CS48L32_IRQ1_MASK_1, + .ack_base = CS48L32_IRQ1_EINT_1, + .runtime_pm = true, + .num_regs = 11, + .irqs = cs48l32_irqs, + .num_irqs = ARRAY_SIZE(cs48l32_irqs), +}; + +static int __maybe_unused cs48l32_suspend(struct device *dev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(dev->parent); + + dev_dbg(mfd->irq_dev, "Suspend, disabling IRQ\n"); + + /* + * A runtime resume would be needed to access the chip interrupt + * controller but runtime pm doesn't function during suspend. + * Temporarily disable interrupts until we reach suspend_noirq state. + */ + disable_irq(mfd->irq); + + return 0; +} + +static int __maybe_unused cs48l32_suspend_noirq(struct device *dev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(dev->parent); + + dev_dbg(mfd->irq_dev, "No IRQ suspend, reenabling IRQ\n"); + + /* Re-enable interrupts to service wakeup interrupts from the chip */ + enable_irq(mfd->irq); + + return 0; +} + +static int __maybe_unused cs48l32_resume_noirq(struct device *dev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(dev->parent); + + dev_dbg(mfd->irq_dev, "No IRQ resume, disabling IRQ\n"); + + /* + * We can't handle interrupts until runtime pm is available again. + * Disable them temporarily. + */ + disable_irq(mfd->irq); + + return 0; +} + +static int __maybe_unused cs48l32_resume(struct device *dev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(dev->parent); + + dev_dbg(mfd->irq_dev, "Resume, enabling IRQ\n"); + + /* Interrupts can now be handled */ + enable_irq(mfd->irq); + + return 0; +} + +static const struct dev_pm_ops cs48l32_irq_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(cs48l32_suspend, cs48l32_resume) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cs48l32_suspend_noirq, cs48l32_resume_noirq) +}; + +static irqreturn_t cs48l32_sysclk_fail(int irq, void *data) +{ + struct cs48l32_mfd *mfd = data; + + dev_warn(mfd->dev, "SYSCLK fail\n"); + + return IRQ_HANDLED; +} + +static irqreturn_t cs48l32_sysclk_error(int irq, void *data) +{ + struct cs48l32_mfd *mfd = data; + + dev_warn(mfd->dev, "SYSCLK error\n"); + + return IRQ_HANDLED; +} + +static irqreturn_t cs48l32_ctrlif_error(int irq, void *data) +{ + struct cs48l32_mfd *mfd = data; + + dev_warn(mfd->dev, "CTRLIF error\n"); + + return IRQ_HANDLED; +} + +static irqreturn_t cs48l32_boot_done(int irq, void *data) +{ + struct cs48l32_mfd *mfd = data; + + dev_dbg(mfd->dev, "BOOT_DONE\n"); + + return IRQ_HANDLED; +} + +static int cs48l32_irq_probe(struct platform_device *pdev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(pdev->dev.parent); + struct irq_data *irq_data; + unsigned int irq_flags; + int ret; + + irq_data = irq_get_irq_data(mfd->irq); + if (!irq_data) + return dev_err_probe(&pdev->dev, -EINVAL, "Invalid IRQ: %d\n", mfd->irq); + + irq_flags = irqd_get_trigger_type(irq_data); + + /* Codec defaults to trigger low, use this if no flags given */ + if (irq_flags == IRQ_TYPE_NONE) + irq_flags = IRQF_TRIGGER_LOW; + + if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) + return dev_err_probe(&pdev->dev, -EINVAL, "Host interrupt not level-triggered\n"); + + /* + * The silicon always starts at active-low, check if we need to + * switch to active-high. + */ + if (irq_flags & IRQF_TRIGGER_HIGH) + ret = regmap_clear_bits(mfd->regmap, CS48L32_IRQ1_CTRL_AOD, + CS48L32_IRQ_POL_MASK); + else + ret = regmap_set_bits(mfd->regmap, CS48L32_IRQ1_CTRL_AOD, + CS48L32_IRQ_POL_MASK); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Failed to set IRQ polarity\n"); + + /* + * NOTE: regmap registers this against the OF node of the parent of + * the regmap - that is, against the mfd driver + */ + ret = regmap_add_irq_chip(mfd->regmap, mfd->irq, IRQF_ONESHOT, 0, + &cs48l32_irqchip, &mfd->irq_data); + if (ret) + return dev_err_probe(&pdev->dev, ret, "add_irq_chip failed\n"); + + /* Save dev in parent MFD struct so it is accessible to siblings */ + mfd->irq_dev = &pdev->dev; + + /* + * Log global chip error conditions that aren't specific to + * any particular sibling driver. + */ + cs48l32_request_irq(mfd, CS48L32_IRQ_SYSCLK_FAIL, "SYSCLK fail", + cs48l32_sysclk_fail, mfd); + cs48l32_request_irq(mfd, CS48L32_IRQ_SYSCLK_ERR, "SYSCLK error", + cs48l32_sysclk_error, mfd); + cs48l32_request_irq(mfd, CS48L32_IRQ_CTRLIF_ERR, "CTRLIF error", + cs48l32_ctrlif_error, mfd); + cs48l32_request_irq(mfd, CS48L32_IRQ_BOOT_DONE, "BOOT_DONE", + cs48l32_boot_done, mfd); + + return 0; +} + +static int cs48l32_irq_remove(struct platform_device *pdev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(pdev->dev.parent); + + /* + * The IRQ is disabled by the parent MFD driver before + * it starts cleaning up all child drivers + */ + cs48l32_free_irq(mfd, CS48L32_IRQ_BOOT_DONE, mfd); + cs48l32_free_irq(mfd, CS48L32_IRQ_CTRLIF_ERR, mfd); + cs48l32_free_irq(mfd, CS48L32_IRQ_SYSCLK_ERR, mfd); + cs48l32_free_irq(mfd, CS48L32_IRQ_SYSCLK_FAIL, mfd); + + mfd->irq_dev = NULL; + regmap_del_irq_chip(mfd->irq, mfd->irq_data); + + return 0; +} + +static struct platform_driver cs48l32_irq_driver = { + .probe = &cs48l32_irq_probe, + .remove = &cs48l32_irq_remove, + .driver = { + .name = "cs48l32-irq", + .pm = &cs48l32_irq_pm_ops, + } +}; + +module_platform_driver(cs48l32_irq_driver); + +MODULE_DESCRIPTION("CS48L32 IRQ driver"); +MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/irqchip/irq-cirrus-cs48l32.h b/drivers/irqchip/irq-cirrus-cs48l32.h new file mode 100644 index 000000000000..6dae6ddf724d --- /dev/null +++ b/drivers/irqchip/irq-cirrus-cs48l32.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Interrupt support for Cirrus Logic CS48L32 audio codec + * + * Copyright (C) 2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef IRQ_CIRRUS_CS48L32_H +#define IRQ_CIRRUS_CS48L32_H + +/* (0x18010) IRQ1_EINT_1 */ +#define CS48L32_DSPCLK_ERR_EINT1_MASK 0x00001000 +#define CS48L32_SYSCLK_ERR_EINT1_MASK 0x00000400 +#define CS48L32_CTRLIF_ERR_EINT1_MASK 0x00000200 +#define CS48L32_SYSCLK_FAIL_EINT1_MASK 0x00000100 + +/* (0x18014) IRQ1_EINT_2 */ +#define CS48L32_BOOT_DONE_EINT1_MASK 0x00000008 + +/* (0x18020) IRQ1_EINT_5 */ +#define CS48L32_US2_ACT_DET_FALL_EINT1_MASK 0x02000000 +#define CS48L32_US2_ACT_DET_RISE_EINT1_MASK 0x01000000 +#define CS48L32_US1_ACT_DET_FALL_EINT1_MASK 0x00800000 +#define CS48L32_US1_ACT_DET_RISE_EINT1_MASK 0x00400000 +#define CS48L32_INPUTS_SIG_DET_FALL_EINT1_MASK 0x00200000 +#define CS48L32_INPUTS_SIG_DET_RISE_EINT1_MASK 0x00100000 +#define CS48L32_DRC2_SIG_DET_FALL_EINT1_MASK 0x00080000 +#define CS48L32_DRC2_SIG_DET_RISE_EINT1_MASK 0x00040000 +#define CS48L32_DRC1_SIG_DET_FALL_EINT1_MASK 0x00020000 +#define CS48L32_DRC1_SIG_DET_RISE_EINT1_MASK 0x00010000 + +/* (0x18024) IRQ1_EINT_6 */ +#define CS48L32_FLL1_REF_LOST_EINT1_MASK 0x00000100 +#define CS48L32_FLL1_LOCK_FALL_EINT1_MASK 0x00000002 +#define CS48L32_FLL1_LOCK_RISE_EINT1_MASK 0x00000001 + +/* (0x18028) IRQ1_EINT_7 */ +#define CS48L32_DSP1_MPU_ERR_EINT1_MASK 0x00200000 +#define CS48L32_DSP1_WDT_EXPIRE_EINT1_MASK 0x00100000 +#define CS48L32_DSP1_IHB_ERR_EINT1_MASK 0x00080000 +#define CS48L32_DSP1_AHB_SYS_ERR_EINT1_MASK 0x00040000 +#define CS48L32_DSP1_AHB_PACK_ERR_EINT1_MASK 0x00020000 +#define CS48L32_DSP1_NMI_ERR_EINT1_MASK 0x00010000 + +/* (0x18030) IRQ1_EINT_9 */ +#define CS48L32_MCU_HWERR_IRQ_OUT_EINT1_MASK 0x80000000 +#define CS48L32_DSP1_IRQ3_EINT1_MASK 0x00000008 +#define CS48L32_DSP1_IRQ2_EINT1_MASK 0x00000004 +#define CS48L32_DSP1_IRQ1_EINT1_MASK 0x00000002 +#define CS48L32_DSP1_IRQ0_EINT1_MASK 0x00000001 + +/* (0x18034) IRQ1_EINT_10 */ +#define CS48L32_CLOCK_DETECT_EINT1_MASK 0x01000000 + +/* (0x18038) IRQ1_EINT_11 */ +#define CS48L32_GPIO8_FALL_EINT1_MASK 0x80000000 +#define CS48L32_GPIO8_RISE_EINT1_MASK 0x40000000 +#define CS48L32_GPIO7_FALL_EINT1_MASK 0x20000000 +#define CS48L32_GPIO7_RISE_EINT1_MASK 0x10000000 +#define CS48L32_GPIO6_FALL_EINT1_MASK 0x08000000 +#define CS48L32_GPIO6_RISE_EINT1_MASK 0x04000000 +#define CS48L32_GPIO5_FALL_EINT1_MASK 0x02000000 +#define CS48L32_GPIO5_RISE_EINT1_MASK 0x01000000 +#define CS48L32_GPIO4_FALL_EINT1_MASK 0x00800000 +#define CS48L32_GPIO4_RISE_EINT1_MASK 0x00400000 +#define CS48L32_GPIO3_FALL_EINT1_MASK 0x00200000 +#define CS48L32_GPIO3_RISE_EINT1_MASK 0x00100000 +#define CS48L32_GPIO2_FALL_EINT1_MASK 0x00080000 +#define CS48L32_GPIO2_RISE_EINT1_MASK 0x00040000 +#define CS48L32_GPIO1_FALL_EINT1_MASK 0x00020000 +#define CS48L32_GPIO1_RISE_EINT1_MASK 0x00010000 + +#endif diff --git a/include/linux/irqchip/irq-cirrus-cs48l32.h b/include/linux/irqchip/irq-cirrus-cs48l32.h new file mode 100644 index 000000000000..c94d31cef96f --- /dev/null +++ b/include/linux/irqchip/irq-cirrus-cs48l32.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Interrupt support for Cirrus Logic CS48L32 audio codec + * + * Copyright (C) 2017-2020, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef IRQCHIP_CIRRUS_CS48L32_H +#define IRQCHIP_CIRRUS_CS48L32_H + +#include <linux/interrupt.h> +#include <linux/mfd/cs48l32/core.h> + +/* Main interrupts, organized by priority order - highest first */ +#define CS48L32_IRQ_DSP1_IRQ0 0 +#define CS48L32_IRQ_DSP1_IRQ1 1 +#define CS48L32_IRQ_DSP1_IRQ2 2 +#define CS48L32_IRQ_DSP1_IRQ3 3 +#define CS48L32_IRQ_US1_ACT_DET_RISE 4 +#define CS48L32_IRQ_US1_ACT_DET_FALL 5 +#define CS48L32_IRQ_US2_ACT_DET_RISE 6 +#define CS48L32_IRQ_US2_ACT_DET_FALL 7 +#define CS48L32_IRQ_INPUTS_SIG_DET_RISE 8 +#define CS48L32_IRQ_INPUTS_SIG_DET_FALL 9 +#define CS48L32_IRQ_GPIO1_RISE 10 +#define CS48L32_IRQ_GPIO1_FALL 11 +#define CS48L32_IRQ_GPIO2_RISE 12 +#define CS48L32_IRQ_GPIO2_FALL 13 +#define CS48L32_IRQ_GPIO3_RISE 14 +#define CS48L32_IRQ_GPIO3_FALL 15 +#define CS48L32_IRQ_GPIO4_RISE 16 +#define CS48L32_IRQ_GPIO4_FALL 17 +#define CS48L32_IRQ_GPIO5_RISE 18 +#define CS48L32_IRQ_GPIO5_FALL 19 +#define CS48L32_IRQ_GPIO6_RISE 20 +#define CS48L32_IRQ_GPIO6_FALL 21 +#define CS48L32_IRQ_GPIO7_RISE 22 +#define CS48L32_IRQ_GPIO7_FALL 23 +#define CS48L32_IRQ_GPIO8_RISE 24 +#define CS48L32_IRQ_GPIO8_FALL 25 +#define CS48L32_IRQ_DRC1_SIG_DET_RISE 26 +#define CS48L32_IRQ_DRC1_SIG_DET_FALL 27 +#define CS48L32_IRQ_DRC2_SIG_DET_RISE 28 +#define CS48L32_IRQ_DRC2_SIG_DET_FALL 29 +#define CS48L32_IRQ_FLL1_LOCK_RISE 30 +#define CS48L32_IRQ_FLL1_LOCK_FALL 31 +#define CS48L32_IRQ_FLL1_REF_LOST 32 +#define CS48L32_IRQ_SYSCLK_FAIL 33 +#define CS48L32_IRQ_CTRLIF_ERR 34 +#define CS48L32_IRQ_SYSCLK_ERR 35 +#define CS48L32_IRQ_DSPCLK_ERR 36 +#define CS48L32_IRQ_DSP1_NMI_ERR 37 +#define CS48L32_IRQ_DSP1_WDT_EXPIRE 38 +#define CS48L32_IRQ_DSP1_MPU_ERR 39 +#define CS48L32_IRQ_BOOT_DONE 40 + +struct cs48l32_mfd; + +/* + * These wrapper functions are for use by other child drivers of the + * same parent MFD. + */ +static inline int cs48l32_get_irq_mapping(struct cs48l32_mfd *cs48l32, int irq) +{ + if (!cs48l32->irq_dev) + return -ENODEV; + + return regmap_irq_get_virq(cs48l32->irq_data, irq); +} + +static inline int cs48l32_request_irq(struct cs48l32_mfd *cs48l32, int irq, + const char *name, + irq_handler_t handler, void *data) +{ + irq = cs48l32_get_irq_mapping(cs48l32, irq); + if (irq < 0) + return irq; + + return request_threaded_irq(irq, NULL, handler, IRQF_ONESHOT, name, data); +} + +static inline void cs48l32_free_irq(struct cs48l32_mfd *cs48l32, int irq, void *data) +{ + irq = cs48l32_get_irq_mapping(cs48l32, irq); + if (irq < 0) + return; + + free_irq(irq, data); +} + +static inline int cs48l32_set_irq_wake(struct cs48l32_mfd *cs48l32, int irq, int on) +{ + irq = cs48l32_get_irq_mapping(cs48l32, irq); + if (irq < 0) + return irq; + + return irq_set_irq_wake(irq, on); +} + +#endif -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-10 8:02 ` Marc Zyngier -1 siblings, 0 replies; 98+ messages in thread From: Marc Zyngier @ 2022-11-10 8:02 UTC (permalink / raw) To: Richard Fitzgerald Cc: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On Wed, 09 Nov 2022 16:53:28 +0000, Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > > The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable > interrupt controller with a variety of interrupt sources, including > GPIOs that can be used as interrupt inputs. > > This driver provides the handling for the interrupt controller. As the > codec is accessed via regmap, the generic regmap_irq functionality > is used to do most of the work. > I cannot spot a shred of interrupt controller code in there. This belongs IMO to the MFD code. It is also a direct copy of the existing irq-madera.c code, duplicated for no obvious reason. M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-10 8:02 ` Marc Zyngier 0 siblings, 0 replies; 98+ messages in thread From: Marc Zyngier @ 2022-11-10 8:02 UTC (permalink / raw) To: Richard Fitzgerald Cc: devicetree, alsa-devel, patches, linus.walleij, lee, linux-kernel, robh+dt, linux-gpio, broonie, krzysztof.kozlowski+dt, tglx On Wed, 09 Nov 2022 16:53:28 +0000, Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > > The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable > interrupt controller with a variety of interrupt sources, including > GPIOs that can be used as interrupt inputs. > > This driver provides the handling for the interrupt controller. As the > codec is accessed via regmap, the generic regmap_irq functionality > is used to do most of the work. > I cannot spot a shred of interrupt controller code in there. This belongs IMO to the MFD code. It is also a direct copy of the existing irq-madera.c code, duplicated for no obvious reason. M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-10 8:02 ` Marc Zyngier @ 2022-11-10 11:22 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-10 11:22 UTC (permalink / raw) To: Marc Zyngier Cc: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On 10/11/2022 08:02, Marc Zyngier wrote: > On Wed, 09 Nov 2022 16:53:28 +0000, > Richard Fitzgerald <rf@opensource.cirrus.com> wrote: >> >> The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable >> interrupt controller with a variety of interrupt sources, including >> GPIOs that can be used as interrupt inputs. >> >> This driver provides the handling for the interrupt controller. As the >> codec is accessed via regmap, the generic regmap_irq functionality >> is used to do most of the work. >> > > I cannot spot a shred of interrupt controller code in there. This It is providing support for handling an interrupt controller so that other drivers can bind to those interrupts. It's just that regmap provides a lot of generic implementation for SPI-connected interrupt controllers so we don't need to open-code all that in the irqchip driver. > belongs IMO to the MFD code. We did once put interrupt support in MFD for an older product line but the MFD maintainer doesn't like the MFD being a dumping-ground for random other functionality that have their own subsystems. > It is also a direct copy of the existing > irq-madera.c code, duplicated for no obvious reason. It's not a duplicate. The register map of this device is different (different addressing, 32-bit registers not 16-bit) > > M. > ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-10 11:22 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-10 11:22 UTC (permalink / raw) To: Marc Zyngier Cc: devicetree, alsa-devel, patches, linus.walleij, lee, linux-kernel, robh+dt, linux-gpio, broonie, krzysztof.kozlowski+dt, tglx On 10/11/2022 08:02, Marc Zyngier wrote: > On Wed, 09 Nov 2022 16:53:28 +0000, > Richard Fitzgerald <rf@opensource.cirrus.com> wrote: >> >> The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable >> interrupt controller with a variety of interrupt sources, including >> GPIOs that can be used as interrupt inputs. >> >> This driver provides the handling for the interrupt controller. As the >> codec is accessed via regmap, the generic regmap_irq functionality >> is used to do most of the work. >> > > I cannot spot a shred of interrupt controller code in there. This It is providing support for handling an interrupt controller so that other drivers can bind to those interrupts. It's just that regmap provides a lot of generic implementation for SPI-connected interrupt controllers so we don't need to open-code all that in the irqchip driver. > belongs IMO to the MFD code. We did once put interrupt support in MFD for an older product line but the MFD maintainer doesn't like the MFD being a dumping-ground for random other functionality that have their own subsystems. > It is also a direct copy of the existing > irq-madera.c code, duplicated for no obvious reason. It's not a duplicate. The register map of this device is different (different addressing, 32-bit registers not 16-bit) > > M. > ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-10 11:22 ` Richard Fitzgerald @ 2022-11-10 12:01 ` Marc Zyngier -1 siblings, 0 replies; 98+ messages in thread From: Marc Zyngier @ 2022-11-10 12:01 UTC (permalink / raw) To: Richard Fitzgerald Cc: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On Thu, 10 Nov 2022 11:22:26 +0000, Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > > On 10/11/2022 08:02, Marc Zyngier wrote: > > On Wed, 09 Nov 2022 16:53:28 +0000, > > Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > >> > >> The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable > >> interrupt controller with a variety of interrupt sources, including > >> GPIOs that can be used as interrupt inputs. > >> > >> This driver provides the handling for the interrupt controller. As the > >> codec is accessed via regmap, the generic regmap_irq functionality > >> is used to do most of the work. > >> > > > > I cannot spot a shred of interrupt controller code in there. This > > It is providing support for handling an interrupt controller so that > other drivers can bind to those interrupts. It's just that regmap > provides a lot of generic implementation for SPI-connected interrupt > controllers so we don't need to open-code all that in the > irqchip driver. And thus none of that code needs to live in drivers/irqchip. > > > belongs IMO to the MFD code. > > We did once put interrupt support in MFD for an older product line but > the MFD maintainer doesn't like the MFD being a dumping-ground for > random other functionality that have their own subsystems. I don't like this stuff either. All this code is a glorified set of interrupt handlers and #defines that only hide the lack of a proper DT binding to express the interrupt routing (it feels like looking at board files from 10 years ago). None of that belongs in the irqchip code. > > > It is also a direct copy of the existing > > irq-madera.c code, duplicated for no obvious reason. > > It's not a duplicate. The register map of this device is different > (different addressing, 32-bit registers not 16-bit) And? How hard is it to implement an indirection containing the register map and the relevant callbacks? /roll-eyes M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-10 12:01 ` Marc Zyngier 0 siblings, 0 replies; 98+ messages in thread From: Marc Zyngier @ 2022-11-10 12:01 UTC (permalink / raw) To: Richard Fitzgerald Cc: devicetree, alsa-devel, patches, linus.walleij, lee, linux-kernel, robh+dt, linux-gpio, broonie, krzysztof.kozlowski+dt, tglx On Thu, 10 Nov 2022 11:22:26 +0000, Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > > On 10/11/2022 08:02, Marc Zyngier wrote: > > On Wed, 09 Nov 2022 16:53:28 +0000, > > Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > >> > >> The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable > >> interrupt controller with a variety of interrupt sources, including > >> GPIOs that can be used as interrupt inputs. > >> > >> This driver provides the handling for the interrupt controller. As the > >> codec is accessed via regmap, the generic regmap_irq functionality > >> is used to do most of the work. > >> > > > > I cannot spot a shred of interrupt controller code in there. This > > It is providing support for handling an interrupt controller so that > other drivers can bind to those interrupts. It's just that regmap > provides a lot of generic implementation for SPI-connected interrupt > controllers so we don't need to open-code all that in the > irqchip driver. And thus none of that code needs to live in drivers/irqchip. > > > belongs IMO to the MFD code. > > We did once put interrupt support in MFD for an older product line but > the MFD maintainer doesn't like the MFD being a dumping-ground for > random other functionality that have their own subsystems. I don't like this stuff either. All this code is a glorified set of interrupt handlers and #defines that only hide the lack of a proper DT binding to express the interrupt routing (it feels like looking at board files from 10 years ago). None of that belongs in the irqchip code. > > > It is also a direct copy of the existing > > irq-madera.c code, duplicated for no obvious reason. > > It's not a duplicate. The register map of this device is different > (different addressing, 32-bit registers not 16-bit) And? How hard is it to implement an indirection containing the register map and the relevant callbacks? /roll-eyes M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-10 12:01 ` Marc Zyngier @ 2022-11-10 13:00 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-10 13:00 UTC (permalink / raw) To: Marc Zyngier Cc: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On 10/11/2022 12:01, Marc Zyngier wrote: > On Thu, 10 Nov 2022 11:22:26 +0000, > Richard Fitzgerald <rf@opensource.cirrus.com> wrote: >> >> On 10/11/2022 08:02, Marc Zyngier wrote: >>> On Wed, 09 Nov 2022 16:53:28 +0000, >>> Richard Fitzgerald <rf@opensource.cirrus.com> wrote: >>>> >>>> The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable >>>> interrupt controller with a variety of interrupt sources, including >>>> GPIOs that can be used as interrupt inputs. >>>> >>>> This driver provides the handling for the interrupt controller. As the >>>> codec is accessed via regmap, the generic regmap_irq functionality >>>> is used to do most of the work. >>>> >>> >>> I cannot spot a shred of interrupt controller code in there. This >> >> It is providing support for handling an interrupt controller so that >> other drivers can bind to those interrupts. It's just that regmap >> provides a lot of generic implementation for SPI-connected interrupt >> controllers so we don't need to open-code all that in the >> irqchip driver. > > And thus none of that code needs to live in drivers/irqchip. > >> >>> belongs IMO to the MFD code. >> >> We did once put interrupt support in MFD for an older product line but >> the MFD maintainer doesn't like the MFD being a dumping-ground for >> random other functionality that have their own subsystems. > > I don't like this stuff either. All this code is a glorified set of > interrupt handlers and #defines that only hide the lack of a proper DT > binding to express the interrupt routing (it feels like looking at > board files from 10 years ago). > I didn't understand this. The whole purpose of this is to instantiate Linux interrupts for the PIC interrupt sources so that other drivers that want to use the interrupts from the CS48L32 PIC can use standard kernel APIs or DT to bind against them. The four handlers registered within the driver are done here simply because they don't belong to any particular child driver. Since they are a fixed feature of the chip that we know we want to handle we may as well just register them. If we put them in the MFD with DT definitions it would make a circular dependency between MFD and its child, which is not a great situation. If it's these handlers that are bothering you, we could move them to the audio driver. > None of that belongs in the irqchip code. > I don't really understand here what the criteria is that makes this not a irqchip driver but it was ok for madera. We have a PIC and we need to handle that and export those interrupts so other drivers can bind against them. Is the problem that the PIC is on a SPI bus and irqchip is only for memory-mapped PICs? Or is it that we have re-used existing library code instead of open-coding it, so you aren't seeing the actual handling code? As Lee has already objected in the past to having the interrupt controller implementation in MFD I don't want to move it there without Lee's agreement that it's ok to put the PIC IRQ implementation in MFD for CS48L32. >> >>> It is also a direct copy of the existing >>> irq-madera.c code, duplicated for no obvious reason. >> >> It's not a duplicate. The register map of this device is different >> (different addressing, 32-bit registers not 16-bit) > > And? How hard is it to implement an indirection containing the > register map and the relevant callbacks? /roll-eyes > > M. > ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-10 13:00 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-10 13:00 UTC (permalink / raw) To: Marc Zyngier Cc: devicetree, alsa-devel, patches, linus.walleij, lee, linux-kernel, robh+dt, linux-gpio, broonie, krzysztof.kozlowski+dt, tglx On 10/11/2022 12:01, Marc Zyngier wrote: > On Thu, 10 Nov 2022 11:22:26 +0000, > Richard Fitzgerald <rf@opensource.cirrus.com> wrote: >> >> On 10/11/2022 08:02, Marc Zyngier wrote: >>> On Wed, 09 Nov 2022 16:53:28 +0000, >>> Richard Fitzgerald <rf@opensource.cirrus.com> wrote: >>>> >>>> The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable >>>> interrupt controller with a variety of interrupt sources, including >>>> GPIOs that can be used as interrupt inputs. >>>> >>>> This driver provides the handling for the interrupt controller. As the >>>> codec is accessed via regmap, the generic regmap_irq functionality >>>> is used to do most of the work. >>>> >>> >>> I cannot spot a shred of interrupt controller code in there. This >> >> It is providing support for handling an interrupt controller so that >> other drivers can bind to those interrupts. It's just that regmap >> provides a lot of generic implementation for SPI-connected interrupt >> controllers so we don't need to open-code all that in the >> irqchip driver. > > And thus none of that code needs to live in drivers/irqchip. > >> >>> belongs IMO to the MFD code. >> >> We did once put interrupt support in MFD for an older product line but >> the MFD maintainer doesn't like the MFD being a dumping-ground for >> random other functionality that have their own subsystems. > > I don't like this stuff either. All this code is a glorified set of > interrupt handlers and #defines that only hide the lack of a proper DT > binding to express the interrupt routing (it feels like looking at > board files from 10 years ago). > I didn't understand this. The whole purpose of this is to instantiate Linux interrupts for the PIC interrupt sources so that other drivers that want to use the interrupts from the CS48L32 PIC can use standard kernel APIs or DT to bind against them. The four handlers registered within the driver are done here simply because they don't belong to any particular child driver. Since they are a fixed feature of the chip that we know we want to handle we may as well just register them. If we put them in the MFD with DT definitions it would make a circular dependency between MFD and its child, which is not a great situation. If it's these handlers that are bothering you, we could move them to the audio driver. > None of that belongs in the irqchip code. > I don't really understand here what the criteria is that makes this not a irqchip driver but it was ok for madera. We have a PIC and we need to handle that and export those interrupts so other drivers can bind against them. Is the problem that the PIC is on a SPI bus and irqchip is only for memory-mapped PICs? Or is it that we have re-used existing library code instead of open-coding it, so you aren't seeing the actual handling code? As Lee has already objected in the past to having the interrupt controller implementation in MFD I don't want to move it there without Lee's agreement that it's ok to put the PIC IRQ implementation in MFD for CS48L32. >> >>> It is also a direct copy of the existing >>> irq-madera.c code, duplicated for no obvious reason. >> >> It's not a duplicate. The register map of this device is different >> (different addressing, 32-bit registers not 16-bit) > > And? How hard is it to implement an indirection containing the > register map and the relevant callbacks? /roll-eyes > > M. > ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-10 13:00 ` Richard Fitzgerald @ 2022-11-10 15:13 ` Marc Zyngier -1 siblings, 0 replies; 98+ messages in thread From: Marc Zyngier @ 2022-11-10 15:13 UTC (permalink / raw) To: Richard Fitzgerald Cc: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On Thu, 10 Nov 2022 13:00:50 +0000, Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > > On 10/11/2022 12:01, Marc Zyngier wrote: > > On Thu, 10 Nov 2022 11:22:26 +0000, > > Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > >> > >> On 10/11/2022 08:02, Marc Zyngier wrote: > >>> On Wed, 09 Nov 2022 16:53:28 +0000, > >>> Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > >>>> > >>>> The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable > >>>> interrupt controller with a variety of interrupt sources, including > >>>> GPIOs that can be used as interrupt inputs. > >>>> > >>>> This driver provides the handling for the interrupt controller. As the > >>>> codec is accessed via regmap, the generic regmap_irq functionality > >>>> is used to do most of the work. > >>>> > >>> > >>> I cannot spot a shred of interrupt controller code in there. This > >> > >> It is providing support for handling an interrupt controller so that > >> other drivers can bind to those interrupts. It's just that regmap > >> provides a lot of generic implementation for SPI-connected interrupt > >> controllers so we don't need to open-code all that in the > >> irqchip driver. > > > > And thus none of that code needs to live in drivers/irqchip. > > > >> > >>> belongs IMO to the MFD code. > >> > >> We did once put interrupt support in MFD for an older product line but > >> the MFD maintainer doesn't like the MFD being a dumping-ground for > >> random other functionality that have their own subsystems. > > > > I don't like this stuff either. All this code is a glorified set of > > interrupt handlers and #defines that only hide the lack of a proper DT > > binding to express the interrupt routing (it feels like looking at > > board files from 10 years ago). > > > > I didn't understand this. The whole purpose of this is to instantiate > Linux interrupts for the PIC interrupt sources so that other drivers > that want to use the interrupts from the CS48L32 PIC can use standard > kernel APIs or DT to bind against them. There is zero standard APIs in this patch. Does cs48l32_request_irq() look standard to you? This whole thing makes a mockery of the interrupt model and of firmware-based interrupt description which we spent years to build. > > The four handlers registered within the driver are done here simply > because they don't belong to any particular child driver. Since they > are a fixed feature of the chip that we know we want to handle we may as > well just register them. Again, they have no purpose in an interrupt controller driver. > If we put them in the MFD with DT definitions it would make a > circular dependency between MFD and its child, which is not a great > situation. If it's these handlers that are bothering you, we could move > them to the audio driver. And what's left? Nothing. > > > None of that belongs in the irqchip code. > > > > I don't really understand here what the criteria is that makes this not > a irqchip driver but it was ok for madera. We have a PIC and we need to > handle that and export those interrupts so other drivers can bind > against them. Is the problem that the PIC is on a SPI bus and irqchip is > only for memory-mapped PICs? Or is it that we have re-used existing > library code instead of open-coding it, so you aren't seeing the actual > handling code? An irqchip driver uses the irq_chip structure, uses irq domains to abstract the device-specific interrupt numbering from clients, and doesn't force the use of an esoteric API on these clients. What I see here is the exact opposite. Was it OK for madera? No. A moment of weakness, I presume. Do I want to repeat the same mistake? Neither. > As Lee has already objected in the past to having the interrupt > controller implementation in MFD I don't want to move it there without > Lee's agreement that it's ok to put the PIC IRQ implementation in MFD > for CS48L32. If you were implementing an actual interrupt controller driver, I'd take it without any question. The fact that this code mandates the use of its own homegrown API rules it out. Thanks, M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-10 15:13 ` Marc Zyngier 0 siblings, 0 replies; 98+ messages in thread From: Marc Zyngier @ 2022-11-10 15:13 UTC (permalink / raw) To: Richard Fitzgerald Cc: devicetree, alsa-devel, patches, linus.walleij, lee, linux-kernel, robh+dt, linux-gpio, broonie, krzysztof.kozlowski+dt, tglx On Thu, 10 Nov 2022 13:00:50 +0000, Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > > On 10/11/2022 12:01, Marc Zyngier wrote: > > On Thu, 10 Nov 2022 11:22:26 +0000, > > Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > >> > >> On 10/11/2022 08:02, Marc Zyngier wrote: > >>> On Wed, 09 Nov 2022 16:53:28 +0000, > >>> Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > >>>> > >>>> The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable > >>>> interrupt controller with a variety of interrupt sources, including > >>>> GPIOs that can be used as interrupt inputs. > >>>> > >>>> This driver provides the handling for the interrupt controller. As the > >>>> codec is accessed via regmap, the generic regmap_irq functionality > >>>> is used to do most of the work. > >>>> > >>> > >>> I cannot spot a shred of interrupt controller code in there. This > >> > >> It is providing support for handling an interrupt controller so that > >> other drivers can bind to those interrupts. It's just that regmap > >> provides a lot of generic implementation for SPI-connected interrupt > >> controllers so we don't need to open-code all that in the > >> irqchip driver. > > > > And thus none of that code needs to live in drivers/irqchip. > > > >> > >>> belongs IMO to the MFD code. > >> > >> We did once put interrupt support in MFD for an older product line but > >> the MFD maintainer doesn't like the MFD being a dumping-ground for > >> random other functionality that have their own subsystems. > > > > I don't like this stuff either. All this code is a glorified set of > > interrupt handlers and #defines that only hide the lack of a proper DT > > binding to express the interrupt routing (it feels like looking at > > board files from 10 years ago). > > > > I didn't understand this. The whole purpose of this is to instantiate > Linux interrupts for the PIC interrupt sources so that other drivers > that want to use the interrupts from the CS48L32 PIC can use standard > kernel APIs or DT to bind against them. There is zero standard APIs in this patch. Does cs48l32_request_irq() look standard to you? This whole thing makes a mockery of the interrupt model and of firmware-based interrupt description which we spent years to build. > > The four handlers registered within the driver are done here simply > because they don't belong to any particular child driver. Since they > are a fixed feature of the chip that we know we want to handle we may as > well just register them. Again, they have no purpose in an interrupt controller driver. > If we put them in the MFD with DT definitions it would make a > circular dependency between MFD and its child, which is not a great > situation. If it's these handlers that are bothering you, we could move > them to the audio driver. And what's left? Nothing. > > > None of that belongs in the irqchip code. > > > > I don't really understand here what the criteria is that makes this not > a irqchip driver but it was ok for madera. We have a PIC and we need to > handle that and export those interrupts so other drivers can bind > against them. Is the problem that the PIC is on a SPI bus and irqchip is > only for memory-mapped PICs? Or is it that we have re-used existing > library code instead of open-coding it, so you aren't seeing the actual > handling code? An irqchip driver uses the irq_chip structure, uses irq domains to abstract the device-specific interrupt numbering from clients, and doesn't force the use of an esoteric API on these clients. What I see here is the exact opposite. Was it OK for madera? No. A moment of weakness, I presume. Do I want to repeat the same mistake? Neither. > As Lee has already objected in the past to having the interrupt > controller implementation in MFD I don't want to move it there without > Lee's agreement that it's ok to put the PIC IRQ implementation in MFD > for CS48L32. If you were implementing an actual interrupt controller driver, I'd take it without any question. The fact that this code mandates the use of its own homegrown API rules it out. Thanks, M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-10 15:13 ` Marc Zyngier @ 2022-11-10 16:31 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-10 16:31 UTC (permalink / raw) To: Marc Zyngier Cc: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On 10/11/2022 15:13, Marc Zyngier wrote: > On Thu, 10 Nov 2022 13:00:50 +0000, > Richard Fitzgerald <rf@opensource.cirrus.com> wrote: >> >> On 10/11/2022 12:01, Marc Zyngier wrote: >>> On Thu, 10 Nov 2022 11:22:26 +0000, >>> Richard Fitzgerald <rf@opensource.cirrus.com> wrote: >>>> >>>> On 10/11/2022 08:02, Marc Zyngier wrote: >>>>> On Wed, 09 Nov 2022 16:53:28 +0000, >>>>> Richard Fitzgerald <rf@opensource.cirrus.com> wrote: >>>>>> >>>>>> The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable >>>>>> interrupt controller with a variety of interrupt sources, including >>>>>> GPIOs that can be used as interrupt inputs. >>>>>> >>>>>> This driver provides the handling for the interrupt controller. As the >>>>>> codec is accessed via regmap, the generic regmap_irq functionality >>>>>> is used to do most of the work. >>>>>> >>>>> >>>>> I cannot spot a shred of interrupt controller code in there. This >>>> >>>> It is providing support for handling an interrupt controller so that >>>> other drivers can bind to those interrupts. It's just that regmap >>>> provides a lot of generic implementation for SPI-connected interrupt >>>> controllers so we don't need to open-code all that in the >>>> irqchip driver. >>> >>> And thus none of that code needs to live in drivers/irqchip. >>> >>>> >>>>> belongs IMO to the MFD code. >>>> >>>> We did once put interrupt support in MFD for an older product line but >>>> the MFD maintainer doesn't like the MFD being a dumping-ground for >>>> random other functionality that have their own subsystems. >>> >>> I don't like this stuff either. All this code is a glorified set of >>> interrupt handlers and #defines that only hide the lack of a proper DT >>> binding to express the interrupt routing (it feels like looking at >>> board files from 10 years ago). >>> >> >> I didn't understand this. The whole purpose of this is to instantiate >> Linux interrupts for the PIC interrupt sources so that other drivers >> that want to use the interrupts from the CS48L32 PIC can use standard >> kernel APIs or DT to bind against them. > > There is zero standard APIs in this patch. Does cs48l32_request_irq() > look standard to you? This whole thing makes a mockery of the > interrupt model and of firmware-based interrupt description which we > spent years to build. > >> >> The four handlers registered within the driver are done here simply >> because they don't belong to any particular child driver. Since they >> are a fixed feature of the chip that we know we want to handle we may as >> well just register them. > > Again, they have no purpose in an interrupt controller driver. > >> If we put them in the MFD with DT definitions it would make a >> circular dependency between MFD and its child, which is not a great >> situation. If it's these handlers that are bothering you, we could move >> them to the audio driver. > > And what's left? Nothing. Ah, I see. You've missed that the bulk of the implementation re-uses existing library code from regmap. It does say this in the commit message. "the generic regmap_irq functionality is used to do most of the work." and I've also said this in previous replies. This is no way driver that does nothing. There's over 1000 lines of code handling the PIC and dispatching its interrupts to other drivers that want to bind to them. It's just that it makes no sense to duplicate 1300 lines of interrupt handling code from elsewhere when we can re-use that by calling regmap_add_irq_chip(). That gives us all the interrupt- controller-handling code in drivers/base/regmap/regmap-irq.c Perhaps you could re-review this taking into account that regmap_add_irq_chip() is significant. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-10 16:31 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-10 16:31 UTC (permalink / raw) To: Marc Zyngier Cc: devicetree, alsa-devel, patches, linus.walleij, lee, linux-kernel, robh+dt, linux-gpio, broonie, krzysztof.kozlowski+dt, tglx On 10/11/2022 15:13, Marc Zyngier wrote: > On Thu, 10 Nov 2022 13:00:50 +0000, > Richard Fitzgerald <rf@opensource.cirrus.com> wrote: >> >> On 10/11/2022 12:01, Marc Zyngier wrote: >>> On Thu, 10 Nov 2022 11:22:26 +0000, >>> Richard Fitzgerald <rf@opensource.cirrus.com> wrote: >>>> >>>> On 10/11/2022 08:02, Marc Zyngier wrote: >>>>> On Wed, 09 Nov 2022 16:53:28 +0000, >>>>> Richard Fitzgerald <rf@opensource.cirrus.com> wrote: >>>>>> >>>>>> The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable >>>>>> interrupt controller with a variety of interrupt sources, including >>>>>> GPIOs that can be used as interrupt inputs. >>>>>> >>>>>> This driver provides the handling for the interrupt controller. As the >>>>>> codec is accessed via regmap, the generic regmap_irq functionality >>>>>> is used to do most of the work. >>>>>> >>>>> >>>>> I cannot spot a shred of interrupt controller code in there. This >>>> >>>> It is providing support for handling an interrupt controller so that >>>> other drivers can bind to those interrupts. It's just that regmap >>>> provides a lot of generic implementation for SPI-connected interrupt >>>> controllers so we don't need to open-code all that in the >>>> irqchip driver. >>> >>> And thus none of that code needs to live in drivers/irqchip. >>> >>>> >>>>> belongs IMO to the MFD code. >>>> >>>> We did once put interrupt support in MFD for an older product line but >>>> the MFD maintainer doesn't like the MFD being a dumping-ground for >>>> random other functionality that have their own subsystems. >>> >>> I don't like this stuff either. All this code is a glorified set of >>> interrupt handlers and #defines that only hide the lack of a proper DT >>> binding to express the interrupt routing (it feels like looking at >>> board files from 10 years ago). >>> >> >> I didn't understand this. The whole purpose of this is to instantiate >> Linux interrupts for the PIC interrupt sources so that other drivers >> that want to use the interrupts from the CS48L32 PIC can use standard >> kernel APIs or DT to bind against them. > > There is zero standard APIs in this patch. Does cs48l32_request_irq() > look standard to you? This whole thing makes a mockery of the > interrupt model and of firmware-based interrupt description which we > spent years to build. > >> >> The four handlers registered within the driver are done here simply >> because they don't belong to any particular child driver. Since they >> are a fixed feature of the chip that we know we want to handle we may as >> well just register them. > > Again, they have no purpose in an interrupt controller driver. > >> If we put them in the MFD with DT definitions it would make a >> circular dependency between MFD and its child, which is not a great >> situation. If it's these handlers that are bothering you, we could move >> them to the audio driver. > > And what's left? Nothing. Ah, I see. You've missed that the bulk of the implementation re-uses existing library code from regmap. It does say this in the commit message. "the generic regmap_irq functionality is used to do most of the work." and I've also said this in previous replies. This is no way driver that does nothing. There's over 1000 lines of code handling the PIC and dispatching its interrupts to other drivers that want to bind to them. It's just that it makes no sense to duplicate 1300 lines of interrupt handling code from elsewhere when we can re-use that by calling regmap_add_irq_chip(). That gives us all the interrupt- controller-handling code in drivers/base/regmap/regmap-irq.c Perhaps you could re-review this taking into account that regmap_add_irq_chip() is significant. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-10 16:31 ` Richard Fitzgerald @ 2022-11-10 16:55 ` Mark Brown -1 siblings, 0 replies; 98+ messages in thread From: Mark Brown @ 2022-11-10 16:55 UTC (permalink / raw) To: Richard Fitzgerald Cc: Marc Zyngier, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches [-- Attachment #1: Type: text/plain, Size: 1926 bytes --] On Thu, Nov 10, 2022 at 04:31:06PM +0000, Richard Fitzgerald wrote: > On 10/11/2022 15:13, Marc Zyngier wrote: > > > If we put them in the MFD with DT definitions it would make a > > > circular dependency between MFD and its child, which is not a great > > > situation. If it's these handlers that are bothering you, we could move > > > them to the audio driver. > > And what's left? Nothing. > Ah, I see. You've missed that the bulk of the implementation re-uses > existing library code from regmap. It does say this in the commit > message. > "the generic regmap_irq functionality is used to do most of the work." > and I've also said this in previous replies. The thread prompted me to have a look at regmap-irq earlier today and see what it's still doing that peers into the regmap core internals and it seems it's just getting the register stride which has had an external API added already and getting the device for the regmap. It should be straightforward to repaint it and move it into the irqchip subsystem which would be a much more sensible home for a library for implementing irqchips in this day and age. I started looking at the code changes for that a bit. > This is no way driver that does nothing. There's over 1000 lines of code > handling the PIC and dispatching its interrupts to other drivers that > want to bind to them. It's just that it makes no sense to duplicate 1300 > lines of interrupt handling code from elsewhere when we can re-use that > by calling regmap_add_irq_chip(). That gives us all the interrupt- > controller-handling code in drivers/base/regmap/regmap-irq.c TBF that's 1000 lines of overly generic code, a bunch of it is conditional stuff and it's unlikely that any individual driver would want all of it. Equally it does mean that all the users are just providing data rather than writing any code which generally makes things easier to maintain and was the main goal. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-10 16:55 ` Mark Brown 0 siblings, 0 replies; 98+ messages in thread From: Mark Brown @ 2022-11-10 16:55 UTC (permalink / raw) To: Richard Fitzgerald Cc: devicetree, alsa-devel, Marc Zyngier, linus.walleij, lee, linux-kernel, linux-gpio, robh+dt, krzysztof.kozlowski+dt, patches, tglx [-- Attachment #1: Type: text/plain, Size: 1926 bytes --] On Thu, Nov 10, 2022 at 04:31:06PM +0000, Richard Fitzgerald wrote: > On 10/11/2022 15:13, Marc Zyngier wrote: > > > If we put them in the MFD with DT definitions it would make a > > > circular dependency between MFD and its child, which is not a great > > > situation. If it's these handlers that are bothering you, we could move > > > them to the audio driver. > > And what's left? Nothing. > Ah, I see. You've missed that the bulk of the implementation re-uses > existing library code from regmap. It does say this in the commit > message. > "the generic regmap_irq functionality is used to do most of the work." > and I've also said this in previous replies. The thread prompted me to have a look at regmap-irq earlier today and see what it's still doing that peers into the regmap core internals and it seems it's just getting the register stride which has had an external API added already and getting the device for the regmap. It should be straightforward to repaint it and move it into the irqchip subsystem which would be a much more sensible home for a library for implementing irqchips in this day and age. I started looking at the code changes for that a bit. > This is no way driver that does nothing. There's over 1000 lines of code > handling the PIC and dispatching its interrupts to other drivers that > want to bind to them. It's just that it makes no sense to duplicate 1300 > lines of interrupt handling code from elsewhere when we can re-use that > by calling regmap_add_irq_chip(). That gives us all the interrupt- > controller-handling code in drivers/base/regmap/regmap-irq.c TBF that's 1000 lines of overly generic code, a bunch of it is conditional stuff and it's unlikely that any individual driver would want all of it. Equally it does mean that all the users are just providing data rather than writing any code which generally makes things easier to maintain and was the main goal. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-10 16:31 ` Richard Fitzgerald @ 2022-11-10 18:47 ` Marc Zyngier -1 siblings, 0 replies; 98+ messages in thread From: Marc Zyngier @ 2022-11-10 18:47 UTC (permalink / raw) To: Richard Fitzgerald Cc: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On Thu, 10 Nov 2022 16:31:06 +0000, Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > > On 10/11/2022 15:13, Marc Zyngier wrote: > > On Thu, 10 Nov 2022 13:00:50 +0000, > > Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > >> > >> On 10/11/2022 12:01, Marc Zyngier wrote: > >>> On Thu, 10 Nov 2022 11:22:26 +0000, > >>> Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > >>>> > >>>> On 10/11/2022 08:02, Marc Zyngier wrote: > >>>>> On Wed, 09 Nov 2022 16:53:28 +0000, > >>>>> Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > >>>>>> > >>>>>> The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable > >>>>>> interrupt controller with a variety of interrupt sources, including > >>>>>> GPIOs that can be used as interrupt inputs. > >>>>>> > >>>>>> This driver provides the handling for the interrupt controller. As the > >>>>>> codec is accessed via regmap, the generic regmap_irq functionality > >>>>>> is used to do most of the work. > >>>>>> > >>>>> > >>>>> I cannot spot a shred of interrupt controller code in there. This > >>>> > >>>> It is providing support for handling an interrupt controller so that > >>>> other drivers can bind to those interrupts. It's just that regmap > >>>> provides a lot of generic implementation for SPI-connected interrupt > >>>> controllers so we don't need to open-code all that in the > >>>> irqchip driver. > >>> > >>> And thus none of that code needs to live in drivers/irqchip. > >>> > >>>> > >>>>> belongs IMO to the MFD code. > >>>> > >>>> We did once put interrupt support in MFD for an older product line but > >>>> the MFD maintainer doesn't like the MFD being a dumping-ground for > >>>> random other functionality that have their own subsystems. > >>> > >>> I don't like this stuff either. All this code is a glorified set of > >>> interrupt handlers and #defines that only hide the lack of a proper DT > >>> binding to express the interrupt routing (it feels like looking at > >>> board files from 10 years ago). > >>> > >> > >> I didn't understand this. The whole purpose of this is to instantiate > >> Linux interrupts for the PIC interrupt sources so that other drivers > >> that want to use the interrupts from the CS48L32 PIC can use standard > >> kernel APIs or DT to bind against them. > > > > There is zero standard APIs in this patch. Does cs48l32_request_irq() > > look standard to you? This whole thing makes a mockery of the > > interrupt model and of firmware-based interrupt description which we > > spent years to build. > > > >> > >> The four handlers registered within the driver are done here simply > >> because they don't belong to any particular child driver. Since they > >> are a fixed feature of the chip that we know we want to handle we may as > >> well just register them. > > > > Again, they have no purpose in an interrupt controller driver. > > > >> If we put them in the MFD with DT definitions it would make a > >> circular dependency between MFD and its child, which is not a great > >> situation. If it's these handlers that are bothering you, we could move > >> them to the audio driver. > > > > And what's left? Nothing. > > Ah, I see. You've missed that the bulk of the implementation re-uses > existing library code from regmap. It does say this in the commit > message. > > "the generic regmap_irq functionality is used to do most of the work." > > and I've also said this in previous replies. > > This is no way driver that does nothing. There's over 1000 lines of code > handling the PIC and dispatching its interrupts to other drivers that > want to bind to them. It's just that it makes no sense to duplicate 1300 > lines of interrupt handling code from elsewhere when we can re-use that > by calling regmap_add_irq_chip(). That gives us all the interrupt- > controller-handling code in drivers/base/regmap/regmap-irq.c > > Perhaps you could re-review this taking into account that > regmap_add_irq_chip() is significant. Read again what I have written. Having to expose a device-specific API for endpoint drivers to obtain their interrupts, and requiring them to know about some magic values that describe the interrupts source are not a acceptable constructs. We have firmware descriptions to expose interrupt linkages, and your HW is not special enough to deserve its own top level API. Yes, we accepted such drivers in the past, but it has to stop. Either you describe the internal structure of your device in DT or ACPI, and make all client drivers use the standard API, or you make this a codec library, purely specific to your device and only used by it. But the current shape is not something I'm prepared to accept. M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-10 18:47 ` Marc Zyngier 0 siblings, 0 replies; 98+ messages in thread From: Marc Zyngier @ 2022-11-10 18:47 UTC (permalink / raw) To: Richard Fitzgerald Cc: devicetree, alsa-devel, patches, linus.walleij, lee, linux-kernel, robh+dt, linux-gpio, broonie, krzysztof.kozlowski+dt, tglx On Thu, 10 Nov 2022 16:31:06 +0000, Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > > On 10/11/2022 15:13, Marc Zyngier wrote: > > On Thu, 10 Nov 2022 13:00:50 +0000, > > Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > >> > >> On 10/11/2022 12:01, Marc Zyngier wrote: > >>> On Thu, 10 Nov 2022 11:22:26 +0000, > >>> Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > >>>> > >>>> On 10/11/2022 08:02, Marc Zyngier wrote: > >>>>> On Wed, 09 Nov 2022 16:53:28 +0000, > >>>>> Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > >>>>>> > >>>>>> The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable > >>>>>> interrupt controller with a variety of interrupt sources, including > >>>>>> GPIOs that can be used as interrupt inputs. > >>>>>> > >>>>>> This driver provides the handling for the interrupt controller. As the > >>>>>> codec is accessed via regmap, the generic regmap_irq functionality > >>>>>> is used to do most of the work. > >>>>>> > >>>>> > >>>>> I cannot spot a shred of interrupt controller code in there. This > >>>> > >>>> It is providing support for handling an interrupt controller so that > >>>> other drivers can bind to those interrupts. It's just that regmap > >>>> provides a lot of generic implementation for SPI-connected interrupt > >>>> controllers so we don't need to open-code all that in the > >>>> irqchip driver. > >>> > >>> And thus none of that code needs to live in drivers/irqchip. > >>> > >>>> > >>>>> belongs IMO to the MFD code. > >>>> > >>>> We did once put interrupt support in MFD for an older product line but > >>>> the MFD maintainer doesn't like the MFD being a dumping-ground for > >>>> random other functionality that have their own subsystems. > >>> > >>> I don't like this stuff either. All this code is a glorified set of > >>> interrupt handlers and #defines that only hide the lack of a proper DT > >>> binding to express the interrupt routing (it feels like looking at > >>> board files from 10 years ago). > >>> > >> > >> I didn't understand this. The whole purpose of this is to instantiate > >> Linux interrupts for the PIC interrupt sources so that other drivers > >> that want to use the interrupts from the CS48L32 PIC can use standard > >> kernel APIs or DT to bind against them. > > > > There is zero standard APIs in this patch. Does cs48l32_request_irq() > > look standard to you? This whole thing makes a mockery of the > > interrupt model and of firmware-based interrupt description which we > > spent years to build. > > > >> > >> The four handlers registered within the driver are done here simply > >> because they don't belong to any particular child driver. Since they > >> are a fixed feature of the chip that we know we want to handle we may as > >> well just register them. > > > > Again, they have no purpose in an interrupt controller driver. > > > >> If we put them in the MFD with DT definitions it would make a > >> circular dependency between MFD and its child, which is not a great > >> situation. If it's these handlers that are bothering you, we could move > >> them to the audio driver. > > > > And what's left? Nothing. > > Ah, I see. You've missed that the bulk of the implementation re-uses > existing library code from regmap. It does say this in the commit > message. > > "the generic regmap_irq functionality is used to do most of the work." > > and I've also said this in previous replies. > > This is no way driver that does nothing. There's over 1000 lines of code > handling the PIC and dispatching its interrupts to other drivers that > want to bind to them. It's just that it makes no sense to duplicate 1300 > lines of interrupt handling code from elsewhere when we can re-use that > by calling regmap_add_irq_chip(). That gives us all the interrupt- > controller-handling code in drivers/base/regmap/regmap-irq.c > > Perhaps you could re-review this taking into account that > regmap_add_irq_chip() is significant. Read again what I have written. Having to expose a device-specific API for endpoint drivers to obtain their interrupts, and requiring them to know about some magic values that describe the interrupts source are not a acceptable constructs. We have firmware descriptions to expose interrupt linkages, and your HW is not special enough to deserve its own top level API. Yes, we accepted such drivers in the past, but it has to stop. Either you describe the internal structure of your device in DT or ACPI, and make all client drivers use the standard API, or you make this a codec library, purely specific to your device and only used by it. But the current shape is not something I'm prepared to accept. M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-10 18:47 ` Marc Zyngier @ 2022-11-10 20:36 ` Mark Brown -1 siblings, 0 replies; 98+ messages in thread From: Mark Brown @ 2022-11-10 20:36 UTC (permalink / raw) To: Marc Zyngier Cc: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches [-- Attachment #1: Type: text/plain, Size: 2946 bytes --] On Thu, Nov 10, 2022 at 06:47:20PM +0000, Marc Zyngier wrote: > Read again what I have written. Having to expose a device-specific API > for endpoint drivers to obtain their interrupts, and requiring them to > know about some magic values that describe the interrupts source are > not a acceptable constructs. > We have firmware descriptions to expose interrupt linkages, and your > HW is not special enough to deserve its own top level API. Yes, we > accepted such drivers in the past, but it has to stop. > Either you describe the internal structure of your device in DT or > ACPI, and make all client drivers use the standard API, or you make > this a codec library, purely specific to your device and only used by > it. But the current shape is not something I'm prepared to accept. ACPI gets to be a lot of fun here, it's just not idiomatic to describe the internals of these devices in firmware there and a lot of the systems shipping this stuff are targeted at other OSs and system integrators are therefore not in the least worried about Linux preferences. You'd need to look at having the MFD add additional description via swnode or something to try to get things going. MFD does have support for that, though it's currently mainly used with devices that only have ACPI use (axp20x looks like the only potentially DT user, from the git history the swnode bits are apparently for use on ACPI systems). That might get fragile in the DT case since you could have multiple sources for description of the same thing unless you do something like suppress the swnode stuff on DT systems. Given that swnode is basically DT written out in C code I'm not actually convinced it's that much of a win, unless someone writes some tooling to generate swnode data from DT files you're not getting the benefit of any of the schema validation work that's being done. We'd also need to do some work for regulators to make sure that if we are parsing DT properties on ACPI systems we don't do so from _DSD since ACPI has strong ideas about how power works and we don't want to end up with systems with firmware providing mixed ACPI/DT models without a clear understanding of what we're geting into. I do also have other concerns in the purely DT case, especially with chip functions like the CODEC where there's a very poor mapping between physical IPs and how Linux is tending to describe things internally at the minute. In particular these devices often have a clock tree portions of which can be visible and useful off chip but which tends to get lumped in with the audio IPs in our current code. Ideally we'd describe that as a clock subdevice (or subdevices if that fits the hardware) using the clock bindings but then that has a bunch of knock on effects the way the code currently is which probably it's probably disproportionate to force an individual driver author to work through. OTOH the DT bindings should be OS neutral ABI so... [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-10 20:36 ` Mark Brown 0 siblings, 0 replies; 98+ messages in thread From: Mark Brown @ 2022-11-10 20:36 UTC (permalink / raw) To: Marc Zyngier Cc: devicetree, alsa-devel, patches, linus.walleij, lee, linux-kernel, linux-gpio, Richard Fitzgerald, robh+dt, krzysztof.kozlowski+dt, tglx [-- Attachment #1: Type: text/plain, Size: 2946 bytes --] On Thu, Nov 10, 2022 at 06:47:20PM +0000, Marc Zyngier wrote: > Read again what I have written. Having to expose a device-specific API > for endpoint drivers to obtain their interrupts, and requiring them to > know about some magic values that describe the interrupts source are > not a acceptable constructs. > We have firmware descriptions to expose interrupt linkages, and your > HW is not special enough to deserve its own top level API. Yes, we > accepted such drivers in the past, but it has to stop. > Either you describe the internal structure of your device in DT or > ACPI, and make all client drivers use the standard API, or you make > this a codec library, purely specific to your device and only used by > it. But the current shape is not something I'm prepared to accept. ACPI gets to be a lot of fun here, it's just not idiomatic to describe the internals of these devices in firmware there and a lot of the systems shipping this stuff are targeted at other OSs and system integrators are therefore not in the least worried about Linux preferences. You'd need to look at having the MFD add additional description via swnode or something to try to get things going. MFD does have support for that, though it's currently mainly used with devices that only have ACPI use (axp20x looks like the only potentially DT user, from the git history the swnode bits are apparently for use on ACPI systems). That might get fragile in the DT case since you could have multiple sources for description of the same thing unless you do something like suppress the swnode stuff on DT systems. Given that swnode is basically DT written out in C code I'm not actually convinced it's that much of a win, unless someone writes some tooling to generate swnode data from DT files you're not getting the benefit of any of the schema validation work that's being done. We'd also need to do some work for regulators to make sure that if we are parsing DT properties on ACPI systems we don't do so from _DSD since ACPI has strong ideas about how power works and we don't want to end up with systems with firmware providing mixed ACPI/DT models without a clear understanding of what we're geting into. I do also have other concerns in the purely DT case, especially with chip functions like the CODEC where there's a very poor mapping between physical IPs and how Linux is tending to describe things internally at the minute. In particular these devices often have a clock tree portions of which can be visible and useful off chip but which tends to get lumped in with the audio IPs in our current code. Ideally we'd describe that as a clock subdevice (or subdevices if that fits the hardware) using the clock bindings but then that has a bunch of knock on effects the way the code currently is which probably it's probably disproportionate to force an individual driver author to work through. OTOH the DT bindings should be OS neutral ABI so... [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-10 20:36 ` Mark Brown @ 2022-11-11 8:00 ` Marc Zyngier -1 siblings, 0 replies; 98+ messages in thread From: Marc Zyngier @ 2022-11-11 8:00 UTC (permalink / raw) To: Mark Brown Cc: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On Thu, 10 Nov 2022 20:36:16 +0000, Mark Brown <broonie@kernel.org> wrote: > > On Thu, Nov 10, 2022 at 06:47:20PM +0000, Marc Zyngier wrote: > > > Read again what I have written. Having to expose a device-specific API > > for endpoint drivers to obtain their interrupts, and requiring them to > > know about some magic values that describe the interrupts source are > > not a acceptable constructs. > > > We have firmware descriptions to expose interrupt linkages, and your > > HW is not special enough to deserve its own top level API. Yes, we > > accepted such drivers in the past, but it has to stop. > > > Either you describe the internal structure of your device in DT or > > ACPI, and make all client drivers use the standard API, or you make > > this a codec library, purely specific to your device and only used by > > it. But the current shape is not something I'm prepared to accept. > > ACPI gets to be a lot of fun here, it's just not idiomatic to describe > the internals of these devices in firmware there and a lot of the > systems shipping this stuff are targeted at other OSs and system > integrators are therefore not in the least worried about Linux > preferences. Let me reassure the vendors that I do not care about them either. By this standard, we'd all run Windows on x86. > You'd need to look at having the MFD add additional > description via swnode or something to try to get things going. MFD > does have support for that, though it's currently mainly used with > devices that only have ACPI use (axp20x looks like the only potentially > DT user, from the git history the swnode bits are apparently for use on > ACPI systems). That might get fragile in the DT case since you could > have multiple sources for description of the same thing unless you do > something like suppress the swnode stuff on DT systems. > > Given that swnode is basically DT written out in C code I'm not actually > convinced it's that much of a win, unless someone writes some tooling to > generate swnode data from DT files you're not getting the benefit of any > of the schema validation work that's being done. We'd also need to do > some work for regulators to make sure that if we are parsing DT > properties on ACPI systems we don't do so from _DSD since ACPI has > strong ideas about how power works and we don't want to end up with > systems with firmware providing mixed ACPI/DT models without a clear > understanding of what we're geting into. > > I do also have other concerns in the purely DT case, especially with > chip functions like the CODEC where there's a very poor mapping between > physical IPs and how Linux is tending to describe things internally at > the minute. In particular these devices often have a clock tree > portions of which can be visible and useful off chip but which tends to > get lumped in with the audio IPs in our current code. Ideally we'd > describe that as a clock subdevice (or subdevices if that fits the > hardware) using the clock bindings but then that has a bunch of knock on > effects the way the code currently is which probably it's probably > disproportionate to force an individual driver author to work through. > OTOH the DT bindings should be OS neutral ABI so... I don't think this is a reason to continue on the current path that pretends to have something generic, but instead is literally a board file fragment with baked-in magic numbers. An irqchip is supposed to offer services to arbitrary clients (endpoint drivers) that are oblivious of the irqchip itself, of the hwirq mapping, and use the standard APIs to obtain a virtual interrupt number. None of that here. This is a monolithic driver, only split across multiple subsystem to satisfy a "not in my backyard" requirement. If the vendors/authors want to keep the shape of the code as is, they can do it outside of the irqchip code and have some library code with an internal API. At least they will stop pretending that this is a general purpose driver. And the existing madera code can also go in the process. M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-11 8:00 ` Marc Zyngier 0 siblings, 0 replies; 98+ messages in thread From: Marc Zyngier @ 2022-11-11 8:00 UTC (permalink / raw) To: Mark Brown Cc: devicetree, alsa-devel, patches, linus.walleij, lee, linux-kernel, linux-gpio, Richard Fitzgerald, robh+dt, krzysztof.kozlowski+dt, tglx On Thu, 10 Nov 2022 20:36:16 +0000, Mark Brown <broonie@kernel.org> wrote: > > On Thu, Nov 10, 2022 at 06:47:20PM +0000, Marc Zyngier wrote: > > > Read again what I have written. Having to expose a device-specific API > > for endpoint drivers to obtain their interrupts, and requiring them to > > know about some magic values that describe the interrupts source are > > not a acceptable constructs. > > > We have firmware descriptions to expose interrupt linkages, and your > > HW is not special enough to deserve its own top level API. Yes, we > > accepted such drivers in the past, but it has to stop. > > > Either you describe the internal structure of your device in DT or > > ACPI, and make all client drivers use the standard API, or you make > > this a codec library, purely specific to your device and only used by > > it. But the current shape is not something I'm prepared to accept. > > ACPI gets to be a lot of fun here, it's just not idiomatic to describe > the internals of these devices in firmware there and a lot of the > systems shipping this stuff are targeted at other OSs and system > integrators are therefore not in the least worried about Linux > preferences. Let me reassure the vendors that I do not care about them either. By this standard, we'd all run Windows on x86. > You'd need to look at having the MFD add additional > description via swnode or something to try to get things going. MFD > does have support for that, though it's currently mainly used with > devices that only have ACPI use (axp20x looks like the only potentially > DT user, from the git history the swnode bits are apparently for use on > ACPI systems). That might get fragile in the DT case since you could > have multiple sources for description of the same thing unless you do > something like suppress the swnode stuff on DT systems. > > Given that swnode is basically DT written out in C code I'm not actually > convinced it's that much of a win, unless someone writes some tooling to > generate swnode data from DT files you're not getting the benefit of any > of the schema validation work that's being done. We'd also need to do > some work for regulators to make sure that if we are parsing DT > properties on ACPI systems we don't do so from _DSD since ACPI has > strong ideas about how power works and we don't want to end up with > systems with firmware providing mixed ACPI/DT models without a clear > understanding of what we're geting into. > > I do also have other concerns in the purely DT case, especially with > chip functions like the CODEC where there's a very poor mapping between > physical IPs and how Linux is tending to describe things internally at > the minute. In particular these devices often have a clock tree > portions of which can be visible and useful off chip but which tends to > get lumped in with the audio IPs in our current code. Ideally we'd > describe that as a clock subdevice (or subdevices if that fits the > hardware) using the clock bindings but then that has a bunch of knock on > effects the way the code currently is which probably it's probably > disproportionate to force an individual driver author to work through. > OTOH the DT bindings should be OS neutral ABI so... I don't think this is a reason to continue on the current path that pretends to have something generic, but instead is literally a board file fragment with baked-in magic numbers. An irqchip is supposed to offer services to arbitrary clients (endpoint drivers) that are oblivious of the irqchip itself, of the hwirq mapping, and use the standard APIs to obtain a virtual interrupt number. None of that here. This is a monolithic driver, only split across multiple subsystem to satisfy a "not in my backyard" requirement. If the vendors/authors want to keep the shape of the code as is, they can do it outside of the irqchip code and have some library code with an internal API. At least they will stop pretending that this is a general purpose driver. And the existing madera code can also go in the process. M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-11 8:00 ` Marc Zyngier @ 2022-11-11 11:16 ` Charles Keepax -1 siblings, 0 replies; 98+ messages in thread From: Charles Keepax @ 2022-11-11 11:16 UTC (permalink / raw) To: Marc Zyngier Cc: Mark Brown, Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On Fri, Nov 11, 2022 at 08:00:10AM +0000, Marc Zyngier wrote: > On Thu, 10 Nov 2022 20:36:16 +0000, > Mark Brown <broonie@kernel.org> wrote: > > On Thu, Nov 10, 2022 at 06:47:20PM +0000, Marc Zyngier wrote: Apologies this ended up getting quite long. Cirrus has no trouble changing how the IRQ driver works I just think we are struggling a little to understand exactly what parts of the code need reworking in what way, we appreciate your patience in helping us through. > > > If you were implementing an actual interrupt controller driver, I'd > > > take it without any question. The fact that this code mandates > > > the use of its own homegrown API rules it out. I think this is part of the crossed wires here, the code does not mandate the use of its own home grown API, although it does provide one. For example our CODECs often provide GPIO/IRQ services for other devices such as say speaker amps attached along side them. Here is a DT example from one of my dev systems with GPIO1 on cs47l35 (a madera CODEC) handling the IRQ for cs35l35 (a speaker amp): cs35l35_left: cs35l35@40 { compatible = "cirrus,cs35l35"; reg = <0x40>; #sound-dai-cells = <1>; reset-gpios = <&axi_gpio0 0 0>; interrupt-parent = <&cs47l35>; interrupts = <57 0>; }; No special code is required in the cs35l35 driver (it is fully upstreamed sound/soc/codecs/cs35l35.c). So if we are missing some actual interrupt controller API we need to be supporting that we are not please point us at it and we will happily add support? So I think your objections are mostly regarding the cs48l32_request_irq function (and friends) that are being used by the other parts of the MFD. I don't think it would be super hard to remove these functions and move the IRQ into DT if that is the preferred way. > > ACPI gets to be a lot of fun here, it's just not idiomatic to describe > > the internals of these devices in firmware there and a lot of the > > systems shipping this stuff are targeted at other OSs and system > > integrators are therefore not in the least worried about Linux > > preferences. I would echo Mark's statement that going the way of moving this into DT/ACPI will actually likely necessitate the addition of a lot of "board file" stuff in the future. If the part gets used in any ACPI systems (granted support is not in yet but this is not a super unlikely addition in the future for cs48l32) we will need to support the laptops containing the part in Linux and the vendors are extremely unlikely to put internal CODEC IRQs into the ACPI tables. But that aside I guess my main question about this approach would be what the DT binding would look like for the CODEC. Currently our devices use a single DT node for the device. Again pulling a Madera example from my dev setup, this is what the DT binding for one of our CODECs currently looks vaguely like: cs47l35: cs47l35@1 { compatible = "cirrus,cs47l35"; reg = <0x1>; spi-max-frequency = <11000000>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&gpio0>; interrupts = <56 8>; gpio-controller; #gpio-cells = <2>; #sound-dai-cells = <1>; AVDD-supply = <&lochnagar_vdd1v8>; DBVDD1-supply = <&lochnagar_vdd1v8>; DBVDD2-supply = <&lochnagar_vdd1v8>; CPVDD1-supply = <&lochnagar_vdd1v8>; CPVDD2-supply = <&lochnagar_vddcore>; DCVDD-supply = <&lochnagar_vddcore>; SPKVDD-supply = <&wallvdd>; reset-gpios = <&lochnagar_pin 0 0>; clocks = <&lochnagar_clk LOCHNAGAR_CDC_MCLK1>, <&lochnagar_clk LOCHNAGAR_CDC_MCLK2>; clock-names = "mclk1", "mclk2"; pinctrl-names = "default"; pinctrl-0 = <&cs47l35_defaults>; }; The interrupt-parent points at who our IRQ is connected to, and we are an interrupt-controller so people can use our IRQs. I think it is not currently supported to have more than a single interrupt-parent for a device so with the current binding is it actually possible for the device to refer to its own IRQs in DT? An alternative approach would be to actually represent the MFD in device tree, I think this would allow things to work and look something like (totally not tested just for discussion): cs47l35: cs47l35@1 { compatible = "cirrus,cs47l35"; reg = <0x1>; spi-max-frequency = <11000000>; irq: madera-irq { compatible = "cirrus,madera-irq"; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&gpio0>; interrupts = <56 8>; }; gpio: madera-gpio { compatible = "cirrus,madera-gpio"; gpio-controller; #gpio-cells = <2>; }; sound: madera-sound { compatible = "cirrus,cs47l35-sound"; interrupt-parent = <&madera-irq>; interrupts = <55 0>, <56 0>; #sound-dai-cells = <1>; }; }; Historically I believe we have been discouraged (by upstream, not from our customers) from explicitly representing the parts of the MFD in device tree separately, as it was viewed that this is just an external SPI CODEC and one node mapped much more logically to the hardware, which is what DT should be describing. However, are you saying this would be a preferrable approach from your side? Or am I missing some alternative solution? Again thank you kindly for you time looking at this. Thanks, Charles ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-11 11:16 ` Charles Keepax 0 siblings, 0 replies; 98+ messages in thread From: Charles Keepax @ 2022-11-11 11:16 UTC (permalink / raw) To: Marc Zyngier Cc: devicetree, alsa-devel, patches, linus.walleij, lee, linux-kernel, robh+dt, linux-gpio, Richard Fitzgerald, Mark Brown, krzysztof.kozlowski+dt, tglx On Fri, Nov 11, 2022 at 08:00:10AM +0000, Marc Zyngier wrote: > On Thu, 10 Nov 2022 20:36:16 +0000, > Mark Brown <broonie@kernel.org> wrote: > > On Thu, Nov 10, 2022 at 06:47:20PM +0000, Marc Zyngier wrote: Apologies this ended up getting quite long. Cirrus has no trouble changing how the IRQ driver works I just think we are struggling a little to understand exactly what parts of the code need reworking in what way, we appreciate your patience in helping us through. > > > If you were implementing an actual interrupt controller driver, I'd > > > take it without any question. The fact that this code mandates > > > the use of its own homegrown API rules it out. I think this is part of the crossed wires here, the code does not mandate the use of its own home grown API, although it does provide one. For example our CODECs often provide GPIO/IRQ services for other devices such as say speaker amps attached along side them. Here is a DT example from one of my dev systems with GPIO1 on cs47l35 (a madera CODEC) handling the IRQ for cs35l35 (a speaker amp): cs35l35_left: cs35l35@40 { compatible = "cirrus,cs35l35"; reg = <0x40>; #sound-dai-cells = <1>; reset-gpios = <&axi_gpio0 0 0>; interrupt-parent = <&cs47l35>; interrupts = <57 0>; }; No special code is required in the cs35l35 driver (it is fully upstreamed sound/soc/codecs/cs35l35.c). So if we are missing some actual interrupt controller API we need to be supporting that we are not please point us at it and we will happily add support? So I think your objections are mostly regarding the cs48l32_request_irq function (and friends) that are being used by the other parts of the MFD. I don't think it would be super hard to remove these functions and move the IRQ into DT if that is the preferred way. > > ACPI gets to be a lot of fun here, it's just not idiomatic to describe > > the internals of these devices in firmware there and a lot of the > > systems shipping this stuff are targeted at other OSs and system > > integrators are therefore not in the least worried about Linux > > preferences. I would echo Mark's statement that going the way of moving this into DT/ACPI will actually likely necessitate the addition of a lot of "board file" stuff in the future. If the part gets used in any ACPI systems (granted support is not in yet but this is not a super unlikely addition in the future for cs48l32) we will need to support the laptops containing the part in Linux and the vendors are extremely unlikely to put internal CODEC IRQs into the ACPI tables. But that aside I guess my main question about this approach would be what the DT binding would look like for the CODEC. Currently our devices use a single DT node for the device. Again pulling a Madera example from my dev setup, this is what the DT binding for one of our CODECs currently looks vaguely like: cs47l35: cs47l35@1 { compatible = "cirrus,cs47l35"; reg = <0x1>; spi-max-frequency = <11000000>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&gpio0>; interrupts = <56 8>; gpio-controller; #gpio-cells = <2>; #sound-dai-cells = <1>; AVDD-supply = <&lochnagar_vdd1v8>; DBVDD1-supply = <&lochnagar_vdd1v8>; DBVDD2-supply = <&lochnagar_vdd1v8>; CPVDD1-supply = <&lochnagar_vdd1v8>; CPVDD2-supply = <&lochnagar_vddcore>; DCVDD-supply = <&lochnagar_vddcore>; SPKVDD-supply = <&wallvdd>; reset-gpios = <&lochnagar_pin 0 0>; clocks = <&lochnagar_clk LOCHNAGAR_CDC_MCLK1>, <&lochnagar_clk LOCHNAGAR_CDC_MCLK2>; clock-names = "mclk1", "mclk2"; pinctrl-names = "default"; pinctrl-0 = <&cs47l35_defaults>; }; The interrupt-parent points at who our IRQ is connected to, and we are an interrupt-controller so people can use our IRQs. I think it is not currently supported to have more than a single interrupt-parent for a device so with the current binding is it actually possible for the device to refer to its own IRQs in DT? An alternative approach would be to actually represent the MFD in device tree, I think this would allow things to work and look something like (totally not tested just for discussion): cs47l35: cs47l35@1 { compatible = "cirrus,cs47l35"; reg = <0x1>; spi-max-frequency = <11000000>; irq: madera-irq { compatible = "cirrus,madera-irq"; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&gpio0>; interrupts = <56 8>; }; gpio: madera-gpio { compatible = "cirrus,madera-gpio"; gpio-controller; #gpio-cells = <2>; }; sound: madera-sound { compatible = "cirrus,cs47l35-sound"; interrupt-parent = <&madera-irq>; interrupts = <55 0>, <56 0>; #sound-dai-cells = <1>; }; }; Historically I believe we have been discouraged (by upstream, not from our customers) from explicitly representing the parts of the MFD in device tree separately, as it was viewed that this is just an external SPI CODEC and one node mapped much more logically to the hardware, which is what DT should be describing. However, are you saying this would be a preferrable approach from your side? Or am I missing some alternative solution? Again thank you kindly for you time looking at this. Thanks, Charles ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-11 11:16 ` Charles Keepax @ 2022-11-11 11:49 ` Mark Brown -1 siblings, 0 replies; 98+ messages in thread From: Mark Brown @ 2022-11-11 11:49 UTC (permalink / raw) To: Charles Keepax Cc: Marc Zyngier, Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches [-- Attachment #1: Type: text/plain, Size: 1819 bytes --] On Fri, Nov 11, 2022 at 11:16:11AM +0000, Charles Keepax wrote: > On Fri, Nov 11, 2022 at 08:00:10AM +0000, Marc Zyngier wrote: > > > > ACPI gets to be a lot of fun here, it's just not idiomatic to describe > > > the internals of these devices in firmware there and a lot of the > > > systems shipping this stuff are targeted at other OSs and system > > > integrators are therefore not in the least worried about Linux > > > preferences. > I would echo Mark's statement that going the way of moving this > into DT/ACPI will actually likely necessitate the addition of a > lot of "board file" stuff in the future. If the part gets used in > any ACPI systems (granted support is not in yet but this is not a > super unlikely addition in the future for cs48l32) we will need to > support the laptops containing the part in Linux and the vendors are > extremely unlikely to put internal CODEC IRQs into the ACPI tables. It's a bit of a stronger issue than that in that it's not how ACPI is usually expected to work (it draws more from the PCI model where you just get a top level ID from the device and have to figure the rest out yourself). > An alternative approach would be to actually represent the MFD in > device tree, I think this would allow things to work and look > something like (totally not tested just for discussion): That's what Marc's pushing for - there is an idea to do that which works well enough for cases (like this irqchip for the most part, modulo how to handle the top level interrupts for the chip) where the way Linux wants to model the device maps clearly onto the hardware but like I was mentioning with the audio/clocking split it gets tricky where things are more up in the air and potentially changable since it's much harder to define a suitable ABI. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-11 11:49 ` Mark Brown 0 siblings, 0 replies; 98+ messages in thread From: Mark Brown @ 2022-11-11 11:49 UTC (permalink / raw) To: Charles Keepax Cc: devicetree, alsa-devel, Marc Zyngier, linus.walleij, lee, linux-kernel, linux-gpio, Richard Fitzgerald, robh+dt, krzysztof.kozlowski+dt, patches, tglx [-- Attachment #1: Type: text/plain, Size: 1819 bytes --] On Fri, Nov 11, 2022 at 11:16:11AM +0000, Charles Keepax wrote: > On Fri, Nov 11, 2022 at 08:00:10AM +0000, Marc Zyngier wrote: > > > > ACPI gets to be a lot of fun here, it's just not idiomatic to describe > > > the internals of these devices in firmware there and a lot of the > > > systems shipping this stuff are targeted at other OSs and system > > > integrators are therefore not in the least worried about Linux > > > preferences. > I would echo Mark's statement that going the way of moving this > into DT/ACPI will actually likely necessitate the addition of a > lot of "board file" stuff in the future. If the part gets used in > any ACPI systems (granted support is not in yet but this is not a > super unlikely addition in the future for cs48l32) we will need to > support the laptops containing the part in Linux and the vendors are > extremely unlikely to put internal CODEC IRQs into the ACPI tables. It's a bit of a stronger issue than that in that it's not how ACPI is usually expected to work (it draws more from the PCI model where you just get a top level ID from the device and have to figure the rest out yourself). > An alternative approach would be to actually represent the MFD in > device tree, I think this would allow things to work and look > something like (totally not tested just for discussion): That's what Marc's pushing for - there is an idea to do that which works well enough for cases (like this irqchip for the most part, modulo how to handle the top level interrupts for the chip) where the way Linux wants to model the device maps clearly onto the hardware but like I was mentioning with the audio/clocking split it gets tricky where things are more up in the air and potentially changable since it's much harder to define a suitable ABI. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-11 11:49 ` Mark Brown @ 2022-11-11 13:01 ` Charles Keepax -1 siblings, 0 replies; 98+ messages in thread From: Charles Keepax @ 2022-11-11 13:01 UTC (permalink / raw) To: Mark Brown Cc: Marc Zyngier, Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On Fri, Nov 11, 2022 at 11:49:25AM +0000, Mark Brown wrote: > On Fri, Nov 11, 2022 at 11:16:11AM +0000, Charles Keepax wrote: > > On Fri, Nov 11, 2022 at 08:00:10AM +0000, Marc Zyngier wrote: > > > > > > ACPI gets to be a lot of fun here, it's just not idiomatic to describe > > > > the internals of these devices in firmware there and a lot of the > > > > systems shipping this stuff are targeted at other OSs and system > > > > integrators are therefore not in the least worried about Linux > > > > preferences. > > > I would echo Mark's statement that going the way of moving this > > into DT/ACPI will actually likely necessitate the addition of a > > lot of "board file" stuff in the future. If the part gets used in > > any ACPI systems (granted support is not in yet but this is not a > > super unlikely addition in the future for cs48l32) we will need to > > support the laptops containing the part in Linux and the vendors are > > extremely unlikely to put internal CODEC IRQs into the ACPI tables. > > It's a bit of a stronger issue than that in that it's not how ACPI is > usually expected to work (it draws more from the PCI model where you > just get a top level ID from the device and have to figure the rest out > yourself). > Hmm... yes ok true ACPI isn't going to put the elements of the MFD in either so we would then need something to bind all those in as well. Thanks, Charles ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-11 13:01 ` Charles Keepax 0 siblings, 0 replies; 98+ messages in thread From: Charles Keepax @ 2022-11-11 13:01 UTC (permalink / raw) To: Mark Brown Cc: devicetree, alsa-devel, Marc Zyngier, linus.walleij, lee, linux-kernel, linux-gpio, Richard Fitzgerald, robh+dt, krzysztof.kozlowski+dt, patches, tglx On Fri, Nov 11, 2022 at 11:49:25AM +0000, Mark Brown wrote: > On Fri, Nov 11, 2022 at 11:16:11AM +0000, Charles Keepax wrote: > > On Fri, Nov 11, 2022 at 08:00:10AM +0000, Marc Zyngier wrote: > > > > > > ACPI gets to be a lot of fun here, it's just not idiomatic to describe > > > > the internals of these devices in firmware there and a lot of the > > > > systems shipping this stuff are targeted at other OSs and system > > > > integrators are therefore not in the least worried about Linux > > > > preferences. > > > I would echo Mark's statement that going the way of moving this > > into DT/ACPI will actually likely necessitate the addition of a > > lot of "board file" stuff in the future. If the part gets used in > > any ACPI systems (granted support is not in yet but this is not a > > super unlikely addition in the future for cs48l32) we will need to > > support the laptops containing the part in Linux and the vendors are > > extremely unlikely to put internal CODEC IRQs into the ACPI tables. > > It's a bit of a stronger issue than that in that it's not how ACPI is > usually expected to work (it draws more from the PCI model where you > just get a top level ID from the device and have to figure the rest out > yourself). > Hmm... yes ok true ACPI isn't going to put the elements of the MFD in either so we would then need something to bind all those in as well. Thanks, Charles ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-11 11:16 ` Charles Keepax @ 2022-11-11 13:00 ` Charles Keepax -1 siblings, 0 replies; 98+ messages in thread From: Charles Keepax @ 2022-11-11 13:00 UTC (permalink / raw) To: Marc Zyngier Cc: Mark Brown, Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On Fri, Nov 11, 2022 at 11:16:11AM +0000, Charles Keepax wrote: > On Fri, Nov 11, 2022 at 08:00:10AM +0000, Marc Zyngier wrote: > > On Thu, 10 Nov 2022 20:36:16 +0000, > > Mark Brown <broonie@kernel.org> wrote: > > > On Thu, Nov 10, 2022 at 06:47:20PM +0000, Marc Zyngier wrote: > The interrupt-parent points at who our IRQ is connected to, and > we are an interrupt-controller so people can use our IRQs. I > think it is not currently supported to have more than a single > interrupt-parent for a device so with the current binding is it > actually possible for the device to refer to its own IRQs in DT? > I see there is actually interrupts-extended which would let us refer to ourselves although its a little unclear to be if that would actually work but might be worth a look. Thanks, Charles ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-11 13:00 ` Charles Keepax 0 siblings, 0 replies; 98+ messages in thread From: Charles Keepax @ 2022-11-11 13:00 UTC (permalink / raw) To: Marc Zyngier Cc: devicetree, alsa-devel, patches, linus.walleij, lee, linux-kernel, robh+dt, linux-gpio, Richard Fitzgerald, Mark Brown, krzysztof.kozlowski+dt, tglx On Fri, Nov 11, 2022 at 11:16:11AM +0000, Charles Keepax wrote: > On Fri, Nov 11, 2022 at 08:00:10AM +0000, Marc Zyngier wrote: > > On Thu, 10 Nov 2022 20:36:16 +0000, > > Mark Brown <broonie@kernel.org> wrote: > > > On Thu, Nov 10, 2022 at 06:47:20PM +0000, Marc Zyngier wrote: > The interrupt-parent points at who our IRQ is connected to, and > we are an interrupt-controller so people can use our IRQs. I > think it is not currently supported to have more than a single > interrupt-parent for a device so with the current binding is it > actually possible for the device to refer to its own IRQs in DT? > I see there is actually interrupts-extended which would let us refer to ourselves although its a little unclear to be if that would actually work but might be worth a look. Thanks, Charles ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-11 8:00 ` Marc Zyngier @ 2022-11-16 16:44 ` Mark Brown -1 siblings, 0 replies; 98+ messages in thread From: Mark Brown @ 2022-11-16 16:44 UTC (permalink / raw) To: Marc Zyngier Cc: devicetree, alsa-devel, patches, linus.walleij, lee, linux-kernel, linux-gpio, Richard Fitzgerald, robh+dt, krzysztof.kozlowski+dt, tglx [-- Attachment #1: Type: text/plain, Size: 2925 bytes --] On Fri, Nov 11, 2022 at 08:00:10AM +0000, Marc Zyngier wrote: > Mark Brown <broonie@kernel.org> wrote: > > On Thu, Nov 10, 2022 at 06:47:20PM +0000, Marc Zyngier wrote: > > > Either you describe the internal structure of your device in DT or > > > ACPI, and make all client drivers use the standard API, or you make > > > this a codec library, purely specific to your device and only used by > > > it. But the current shape is not something I'm prepared to accept. > > ACPI gets to be a lot of fun here, it's just not idiomatic to describe > > the internals of these devices in firmware there and a lot of the > > systems shipping this stuff are targeted at other OSs and system > > integrators are therefore not in the least worried about Linux > > preferences. > Let me reassure the vendors that I do not care about them either. By > this standard, we'd all run Windows on x86. It turns out a bunch of these systems are intended to be used with Linux, and even where the vendor does care about Linux we also have to consider what's tasteful for ACPI. > > You'd need to look at having the MFD add additional > > description via swnode or something to try to get things going. MFD ... > > Given that swnode is basically DT written out in C code I'm not actually > > convinced it's that much of a win, unless someone writes some tooling to > > generate swnode data from DT files you're not getting the benefit of any ... > > I do also have other concerns in the purely DT case, especially with > > chip functions like the CODEC where there's a very poor mapping between > > physical IPs and how Linux is tending to describe things internally at > > the minute. In particular these devices often have a clock tree > I don't think this is a reason to continue on the current path that > pretends to have something generic, but instead is literally a board > file fragment with baked-in magic numbers. > An irqchip is supposed to offer services to arbitrary clients > (endpoint drivers) that are oblivious of the irqchip itself, of the > hwirq mapping, and use the standard APIs to obtain a virtual interrupt > number. None of that here. This is a monolithic driver, only split > across multiple subsystem to satisfy a "not in my backyard" > requirement. > If the vendors/authors want to keep the shape of the code as is, they > can do it outside of the irqchip code and have some library code with > an internal API. At least they will stop pretending that this is a > general purpose driver. And the existing madera code can also go in > the process. Yeah, I'm definitely not in the least bit convinced that the irqchip code is a good home for this sort of glue (especially the interrupt consumers) for the reasons you mention - my concern was more that the firmware interface also has issues, and that putting things into firmware is also putting them into ABI which is much harder to do a good job with later. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-16 16:44 ` Mark Brown 0 siblings, 0 replies; 98+ messages in thread From: Mark Brown @ 2022-11-16 16:44 UTC (permalink / raw) To: Marc Zyngier Cc: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches [-- Attachment #1: Type: text/plain, Size: 2925 bytes --] On Fri, Nov 11, 2022 at 08:00:10AM +0000, Marc Zyngier wrote: > Mark Brown <broonie@kernel.org> wrote: > > On Thu, Nov 10, 2022 at 06:47:20PM +0000, Marc Zyngier wrote: > > > Either you describe the internal structure of your device in DT or > > > ACPI, and make all client drivers use the standard API, or you make > > > this a codec library, purely specific to your device and only used by > > > it. But the current shape is not something I'm prepared to accept. > > ACPI gets to be a lot of fun here, it's just not idiomatic to describe > > the internals of these devices in firmware there and a lot of the > > systems shipping this stuff are targeted at other OSs and system > > integrators are therefore not in the least worried about Linux > > preferences. > Let me reassure the vendors that I do not care about them either. By > this standard, we'd all run Windows on x86. It turns out a bunch of these systems are intended to be used with Linux, and even where the vendor does care about Linux we also have to consider what's tasteful for ACPI. > > You'd need to look at having the MFD add additional > > description via swnode or something to try to get things going. MFD ... > > Given that swnode is basically DT written out in C code I'm not actually > > convinced it's that much of a win, unless someone writes some tooling to > > generate swnode data from DT files you're not getting the benefit of any ... > > I do also have other concerns in the purely DT case, especially with > > chip functions like the CODEC where there's a very poor mapping between > > physical IPs and how Linux is tending to describe things internally at > > the minute. In particular these devices often have a clock tree > I don't think this is a reason to continue on the current path that > pretends to have something generic, but instead is literally a board > file fragment with baked-in magic numbers. > An irqchip is supposed to offer services to arbitrary clients > (endpoint drivers) that are oblivious of the irqchip itself, of the > hwirq mapping, and use the standard APIs to obtain a virtual interrupt > number. None of that here. This is a monolithic driver, only split > across multiple subsystem to satisfy a "not in my backyard" > requirement. > If the vendors/authors want to keep the shape of the code as is, they > can do it outside of the irqchip code and have some library code with > an internal API. At least they will stop pretending that this is a > general purpose driver. And the existing madera code can also go in > the process. Yeah, I'm definitely not in the least bit convinced that the irqchip code is a good home for this sort of glue (especially the interrupt consumers) for the reasons you mention - my concern was more that the firmware interface also has issues, and that putting things into firmware is also putting them into ABI which is much harder to do a good job with later. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-10 12:01 ` Marc Zyngier @ 2022-11-10 13:14 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-10 13:14 UTC (permalink / raw) To: Marc Zyngier Cc: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On 10/11/2022 12:01, Marc Zyngier wrote: > On Thu, 10 Nov 2022 11:22:26 +0000, > Richard Fitzgerald <rf@opensource.cirrus.com> wrote: >> >> On 10/11/2022 08:02, Marc Zyngier wrote: >>> On Wed, 09 Nov 2022 16:53:28 +0000, >>> Richard Fitzgerald <rf@opensource.cirrus.com> wrote: >>>> >>>> The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable >>>> interrupt controller with a variety of interrupt sources, including >>>> GPIOs that can be used as interrupt inputs. >>>> >>>> This driver provides the handling for the interrupt controller. As the >>>> codec is accessed via regmap, the generic regmap_irq functionality >>>> is used to do most of the work. >>>> >>> >>> I cannot spot a shred of interrupt controller code in there. This >> >> It is providing support for handling an interrupt controller so that >> other drivers can bind to those interrupts. It's just that regmap >> provides a lot of generic implementation for SPI-connected interrupt >> controllers so we don't need to open-code all that in the >> irqchip driver. > > And thus none of that code needs to live in drivers/irqchip. > >> >>> belongs IMO to the MFD code. >> >> We did once put interrupt support in MFD for an older product line but >> the MFD maintainer doesn't like the MFD being a dumping-ground for >> random other functionality that have their own subsystems. > > I don't like this stuff either. All this code is a glorified set of > interrupt handlers and #defines that only hide the lack of a proper DT > binding to express the interrupt routing (it feels like looking at > board files from 10 years ago). > > None of that belongs in the irqchip code. > >> >>> It is also a direct copy of the existing >>> irq-madera.c code, duplicated for no obvious reason. >> >> It's not a duplicate. The register map of this device is different >> (different addressing, 32-bit registers not 16-bit) > > And? How hard is it to implement an indirection containing the > register map and the relevant callbacks? /roll-eyes > I note your accusation that we were too lazy (or too stupid?) to think of this. > M. > ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-10 13:14 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-10 13:14 UTC (permalink / raw) To: Marc Zyngier Cc: devicetree, alsa-devel, patches, linus.walleij, lee, linux-kernel, robh+dt, linux-gpio, broonie, krzysztof.kozlowski+dt, tglx On 10/11/2022 12:01, Marc Zyngier wrote: > On Thu, 10 Nov 2022 11:22:26 +0000, > Richard Fitzgerald <rf@opensource.cirrus.com> wrote: >> >> On 10/11/2022 08:02, Marc Zyngier wrote: >>> On Wed, 09 Nov 2022 16:53:28 +0000, >>> Richard Fitzgerald <rf@opensource.cirrus.com> wrote: >>>> >>>> The Cirrus Logic CS48L31/32/33 audio codecs contain a programmable >>>> interrupt controller with a variety of interrupt sources, including >>>> GPIOs that can be used as interrupt inputs. >>>> >>>> This driver provides the handling for the interrupt controller. As the >>>> codec is accessed via regmap, the generic regmap_irq functionality >>>> is used to do most of the work. >>>> >>> >>> I cannot spot a shred of interrupt controller code in there. This >> >> It is providing support for handling an interrupt controller so that >> other drivers can bind to those interrupts. It's just that regmap >> provides a lot of generic implementation for SPI-connected interrupt >> controllers so we don't need to open-code all that in the >> irqchip driver. > > And thus none of that code needs to live in drivers/irqchip. > >> >>> belongs IMO to the MFD code. >> >> We did once put interrupt support in MFD for an older product line but >> the MFD maintainer doesn't like the MFD being a dumping-ground for >> random other functionality that have their own subsystems. > > I don't like this stuff either. All this code is a glorified set of > interrupt handlers and #defines that only hide the lack of a proper DT > binding to express the interrupt routing (it feels like looking at > board files from 10 years ago). > > None of that belongs in the irqchip code. > >> >>> It is also a direct copy of the existing >>> irq-madera.c code, duplicated for no obvious reason. >> >> It's not a duplicate. The register map of this device is different >> (different addressing, 32-bit registers not 16-bit) > > And? How hard is it to implement an indirection containing the > register map and the relevant callbacks? /roll-eyes > I note your accusation that we were too lazy (or too stupid?) to think of this. > M. > ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-10 13:14 ` Richard Fitzgerald @ 2022-11-10 15:40 ` Marc Zyngier -1 siblings, 0 replies; 98+ messages in thread From: Marc Zyngier @ 2022-11-10 15:40 UTC (permalink / raw) To: Richard Fitzgerald Cc: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On Thu, 10 Nov 2022 13:14:30 +0000, Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > > I note your accusation that we were too lazy (or too stupid?) > to think of this. Take it the way you want. But I criticise the code, not the author. And I'm merely pointed out that there was significant room for improvement. M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-10 15:40 ` Marc Zyngier 0 siblings, 0 replies; 98+ messages in thread From: Marc Zyngier @ 2022-11-10 15:40 UTC (permalink / raw) To: Richard Fitzgerald Cc: devicetree, alsa-devel, patches, linus.walleij, lee, linux-kernel, robh+dt, linux-gpio, broonie, krzysztof.kozlowski+dt, tglx On Thu, 10 Nov 2022 13:14:30 +0000, Richard Fitzgerald <rf@opensource.cirrus.com> wrote: > > I note your accusation that we were too lazy (or too stupid?) > to think of this. Take it the way you want. But I criticise the code, not the author. And I'm merely pointed out that there was significant room for improvement. M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs 2022-11-10 11:22 ` Richard Fitzgerald @ 2022-11-10 13:01 ` Mark Brown -1 siblings, 0 replies; 98+ messages in thread From: Mark Brown @ 2022-11-10 13:01 UTC (permalink / raw) To: Richard Fitzgerald Cc: Marc Zyngier, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, tglx, alsa-devel, devicetree, linux-gpio, linux-kernel, patches [-- Attachment #1: Type: text/plain, Size: 946 bytes --] On Thu, Nov 10, 2022 at 11:22:26AM +0000, Richard Fitzgerald wrote: > On 10/11/2022 08:02, Marc Zyngier wrote: > > belongs IMO to the MFD code. > We did once put interrupt support in MFD for an older product line but > the MFD maintainer doesn't like the MFD being a dumping-ground for > random other functionality that have their own subsystems. There's bits of this like logging the top level error interrupts that seem like they clearly fit in the driver for the top level chip (SYSCLK possibly in the audio driver, dunno if it gets used by other functions), they're users of the interrupt controller rather than part of the interrupt controller. > > It is also a direct copy of the existing > > irq-madera.c code, duplicated for no obvious reason. > It's not a duplicate. The register map of this device is different > (different addressing, 32-bit registers not 16-bit) Isn't that just a data difference which could be parameterised? [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs @ 2022-11-10 13:01 ` Mark Brown 0 siblings, 0 replies; 98+ messages in thread From: Mark Brown @ 2022-11-10 13:01 UTC (permalink / raw) To: Richard Fitzgerald Cc: devicetree, alsa-devel, Marc Zyngier, linus.walleij, lee, linux-kernel, linux-gpio, robh+dt, krzysztof.kozlowski+dt, patches, tglx [-- Attachment #1: Type: text/plain, Size: 946 bytes --] On Thu, Nov 10, 2022 at 11:22:26AM +0000, Richard Fitzgerald wrote: > On 10/11/2022 08:02, Marc Zyngier wrote: > > belongs IMO to the MFD code. > We did once put interrupt support in MFD for an older product line but > the MFD maintainer doesn't like the MFD being a dumping-ground for > random other functionality that have their own subsystems. There's bits of this like logging the top level error interrupts that seem like they clearly fit in the driver for the top level chip (SYSCLK possibly in the audio driver, dunno if it gets used by other functions), they're users of the interrupt controller rather than part of the interrupt controller. > > It is also a direct copy of the existing > > irq-madera.c code, duplicated for no obvious reason. > It's not a duplicate. The register map of this device is different > (different addressing, 32-bit registers not 16-bit) Isn't that just a data difference which could be parameterised? [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 98+ messages in thread
* [PATCH 10/12] ASoC: wm_adsp: Allow client to hook into pre_run callback 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-09 16:53 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches, Richard Fitzgerald Some HALO-based codecs need some additional custom setup in the pre_run stage of cs_dsp. Implement the callback in wm_adsp to call an optional codec driver callback. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- sound/soc/codecs/wm_adsp.c | 11 +++++++++++ sound/soc/codecs/wm_adsp.h | 1 + 2 files changed, 12 insertions(+) diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c index 8a2e9771bb50..34a94b011518 100644 --- a/sound/soc/codecs/wm_adsp.c +++ b/sound/soc/codecs/wm_adsp.c @@ -1035,6 +1035,16 @@ int wm_adsp_early_event(struct snd_soc_dapm_widget *w, } EXPORT_SYMBOL_GPL(wm_adsp_early_event); +static int wm_adsp_pre_run(struct cs_dsp *cs_dsp) +{ + struct wm_adsp *dsp = container_of(cs_dsp, struct wm_adsp, cs_dsp); + + if (!dsp->pre_run) + return 0; + + return (*dsp->pre_run)(dsp); +} + static int wm_adsp_event_post_run(struct cs_dsp *cs_dsp) { struct wm_adsp *dsp = container_of(cs_dsp, struct wm_adsp, cs_dsp); @@ -2043,6 +2053,7 @@ static const struct cs_dsp_client_ops wm_adsp1_client_ops = { static const struct cs_dsp_client_ops wm_adsp2_client_ops = { .control_add = wm_adsp_control_add, .control_remove = wm_adsp_control_remove, + .pre_run = wm_adsp_pre_run, .post_run = wm_adsp_event_post_run, .post_stop = wm_adsp_event_post_stop, .watchdog_expired = wm_adsp_fatal_error, diff --git a/sound/soc/codecs/wm_adsp.h b/sound/soc/codecs/wm_adsp.h index 375009a65828..dc2f7a096e26 100644 --- a/sound/soc/codecs/wm_adsp.h +++ b/sound/soc/codecs/wm_adsp.h @@ -36,6 +36,7 @@ struct wm_adsp { int fw; struct work_struct boot_work; + int (*pre_run)(struct wm_adsp *dsp); bool preloaded; bool fatal_error; -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 10/12] ASoC: wm_adsp: Allow client to hook into pre_run callback @ 2022-11-09 16:53 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio, Richard Fitzgerald Some HALO-based codecs need some additional custom setup in the pre_run stage of cs_dsp. Implement the callback in wm_adsp to call an optional codec driver callback. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- sound/soc/codecs/wm_adsp.c | 11 +++++++++++ sound/soc/codecs/wm_adsp.h | 1 + 2 files changed, 12 insertions(+) diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c index 8a2e9771bb50..34a94b011518 100644 --- a/sound/soc/codecs/wm_adsp.c +++ b/sound/soc/codecs/wm_adsp.c @@ -1035,6 +1035,16 @@ int wm_adsp_early_event(struct snd_soc_dapm_widget *w, } EXPORT_SYMBOL_GPL(wm_adsp_early_event); +static int wm_adsp_pre_run(struct cs_dsp *cs_dsp) +{ + struct wm_adsp *dsp = container_of(cs_dsp, struct wm_adsp, cs_dsp); + + if (!dsp->pre_run) + return 0; + + return (*dsp->pre_run)(dsp); +} + static int wm_adsp_event_post_run(struct cs_dsp *cs_dsp) { struct wm_adsp *dsp = container_of(cs_dsp, struct wm_adsp, cs_dsp); @@ -2043,6 +2053,7 @@ static const struct cs_dsp_client_ops wm_adsp1_client_ops = { static const struct cs_dsp_client_ops wm_adsp2_client_ops = { .control_add = wm_adsp_control_add, .control_remove = wm_adsp_control_remove, + .pre_run = wm_adsp_pre_run, .post_run = wm_adsp_event_post_run, .post_stop = wm_adsp_event_post_stop, .watchdog_expired = wm_adsp_fatal_error, diff --git a/sound/soc/codecs/wm_adsp.h b/sound/soc/codecs/wm_adsp.h index 375009a65828..dc2f7a096e26 100644 --- a/sound/soc/codecs/wm_adsp.h +++ b/sound/soc/codecs/wm_adsp.h @@ -36,6 +36,7 @@ struct wm_adsp { int fw; struct work_struct boot_work; + int (*pre_run)(struct wm_adsp *dsp); bool preloaded; bool fatal_error; -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 11/12] dt-bindings: sound: Add Cirrus Logic CS48L31/32/33 codecs 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-09 16:53 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches, Richard Fitzgerald Codecs in this family have multiple digital and analog audio I/O that support a variety of external hardware connections and configurations. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- .../bindings/sound/cirrus,cs48l32.yaml | 96 +++++++++++++++++++ include/dt-bindings/sound/cs48l32.h | 25 +++++ 2 files changed, 121 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml create mode 100644 include/dt-bindings/sound/cs48l32.h diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml new file mode 100644 index 000000000000..70fb294c6dc1 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/cirrus,cs48l32.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CS48L31/32/33 audio CODECs + +maintainers: + - patches@opensource.cirrus.com + +description: | + This describes audio configuration bindings for these codecs. + + See also the core bindings for the parent MFD driver: + + Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml + + and defines for values used in these bindings: + + include/dt-bindings/sound/cs48l32.h + + The properties are all contained in the parent MFD node. + +properties: + '#sound-dai-cells': + const: 1 + + cirrus,in-type: + description: + A list of input type settings for each input. A maximum of 8 cells, + with four cells per input in the order INnL_1, INnR_1 INnL_2 INnR_2. + (where _1 and _2 are the alternative mux selections for that INn). + If the array is shorter than the number of inputs the unspecified + inputs default to CS48L32_IN_TYPE_DIFF. + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + minItems: 1 + maxItems: 8 + items: + items: + - description: + The first cell is INnL_1 input type. One of the CS48L32_IN_TYPE_xxx. + For non-muxed inputs this sets the type of INnL. + minimum: 0 + maximum: 1 + - description: + The second cell is INnR_1 input type. One of the CS48L32_IN_TYPE_xxx. + For non-muxed inputs this sets the type of INnR. + minimum: 0 + maximum: 1 + - description: + The third cell is INnL_2 input type. One of the CS48L32_IN_TYPE_xxx. + For non-muxed inputs this cell must be 0. + minimum: 0 + maximum: 1 + - description: + The fourth cell is INnR_2 input type. One of the CS48L32_IN_TYPE_xxx. + For non-muxed inputs this cell must be 0. + minimum: 0 + maximum: 1 + + cirrus,max-channels-clocked: + description: + Maximum number of channels that clocks will be generated for. When using + multiple data lines, every sample slot can transfer multiple channels + (one per data line). This pdata sets the maximum number of slots. + One cell for each ASP, use a value of zero for ASPs that should be + handled normally. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + items: + default: 0 + + cirrus,pdm-sup: + description: + Indicates how the MICBIAS pins have been externally connected to DMICs + on each input. One cell per input (IN1, IN2, ...). One of the + CS48L32_MICBIAS_xxx values. + See the INn_PDM_SUP field in the datasheet for a description. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + +examples: + - | + cs48l32@0 { + compatible = "cirrus,cs48l32"; + + cirrus,in-type = < + CS48L32_IN_TYPE_DIFF CS48L32_IN_TYPE_DIFF /* IN1[LR]_1 differential */ + CS48L32_IN_TYPE_SE CS48L32_IN_TYPE_SE /* IN1[LR]_2 single-ended */ + CS48L32_IN_TYPE_DIFF CS48L32_IN_TYPE_DIFF /* IN2[LR]_1 differential */ + >; + cirrus,max-channels-clocked = <2 0 0>; + }; diff --git a/include/dt-bindings/sound/cs48l32.h b/include/dt-bindings/sound/cs48l32.h new file mode 100644 index 000000000000..0b774da0a6c8 --- /dev/null +++ b/include/dt-bindings/sound/cs48l32.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Device Tree defines for CS48L32 codec. + * + * Copyright (C) 2016-2018, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef DT_BINDINGS_SOUND_CS48L32_H +#define DT_BINDINGS_SOUND_CS48L32_H + +#define CS48L32_IN_TYPE_DIFF 0 +#define CS48L32_IN_TYPE_SE 1 + +#define CS48L32_PDM_SUP_VOUT_MIC 0 +#define CS48L32_PDM_SUP_MICBIAS1 1 +#define CS48L32_PDM_SUP_MICBIAS2 2 +#define CS48L32_PDM_SUP_MICBIAS3 3 + +#define CS48L32_PDM_FMT_MODE_A_LSB_FIRST 0x0000 +#define CS48L32_PDM_FMT_MODE_B_LSB_FIRST 0x4000 +#define CS48L32_PDM_FMT_MODE_A_MSB_FIRST 0x8000 +#define CS48L32_PDM_FMT_MODE_B_MSB_FIRST 0xc000 + +#endif -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 11/12] dt-bindings: sound: Add Cirrus Logic CS48L31/32/33 codecs @ 2022-11-09 16:53 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio, Richard Fitzgerald Codecs in this family have multiple digital and analog audio I/O that support a variety of external hardware connections and configurations. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- .../bindings/sound/cirrus,cs48l32.yaml | 96 +++++++++++++++++++ include/dt-bindings/sound/cs48l32.h | 25 +++++ 2 files changed, 121 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml create mode 100644 include/dt-bindings/sound/cs48l32.h diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml new file mode 100644 index 000000000000..70fb294c6dc1 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/cirrus,cs48l32.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CS48L31/32/33 audio CODECs + +maintainers: + - patches@opensource.cirrus.com + +description: | + This describes audio configuration bindings for these codecs. + + See also the core bindings for the parent MFD driver: + + Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml + + and defines for values used in these bindings: + + include/dt-bindings/sound/cs48l32.h + + The properties are all contained in the parent MFD node. + +properties: + '#sound-dai-cells': + const: 1 + + cirrus,in-type: + description: + A list of input type settings for each input. A maximum of 8 cells, + with four cells per input in the order INnL_1, INnR_1 INnL_2 INnR_2. + (where _1 and _2 are the alternative mux selections for that INn). + If the array is shorter than the number of inputs the unspecified + inputs default to CS48L32_IN_TYPE_DIFF. + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + minItems: 1 + maxItems: 8 + items: + items: + - description: + The first cell is INnL_1 input type. One of the CS48L32_IN_TYPE_xxx. + For non-muxed inputs this sets the type of INnL. + minimum: 0 + maximum: 1 + - description: + The second cell is INnR_1 input type. One of the CS48L32_IN_TYPE_xxx. + For non-muxed inputs this sets the type of INnR. + minimum: 0 + maximum: 1 + - description: + The third cell is INnL_2 input type. One of the CS48L32_IN_TYPE_xxx. + For non-muxed inputs this cell must be 0. + minimum: 0 + maximum: 1 + - description: + The fourth cell is INnR_2 input type. One of the CS48L32_IN_TYPE_xxx. + For non-muxed inputs this cell must be 0. + minimum: 0 + maximum: 1 + + cirrus,max-channels-clocked: + description: + Maximum number of channels that clocks will be generated for. When using + multiple data lines, every sample slot can transfer multiple channels + (one per data line). This pdata sets the maximum number of slots. + One cell for each ASP, use a value of zero for ASPs that should be + handled normally. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + items: + default: 0 + + cirrus,pdm-sup: + description: + Indicates how the MICBIAS pins have been externally connected to DMICs + on each input. One cell per input (IN1, IN2, ...). One of the + CS48L32_MICBIAS_xxx values. + See the INn_PDM_SUP field in the datasheet for a description. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + +examples: + - | + cs48l32@0 { + compatible = "cirrus,cs48l32"; + + cirrus,in-type = < + CS48L32_IN_TYPE_DIFF CS48L32_IN_TYPE_DIFF /* IN1[LR]_1 differential */ + CS48L32_IN_TYPE_SE CS48L32_IN_TYPE_SE /* IN1[LR]_2 single-ended */ + CS48L32_IN_TYPE_DIFF CS48L32_IN_TYPE_DIFF /* IN2[LR]_1 differential */ + >; + cirrus,max-channels-clocked = <2 0 0>; + }; diff --git a/include/dt-bindings/sound/cs48l32.h b/include/dt-bindings/sound/cs48l32.h new file mode 100644 index 000000000000..0b774da0a6c8 --- /dev/null +++ b/include/dt-bindings/sound/cs48l32.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Device Tree defines for CS48L32 codec. + * + * Copyright (C) 2016-2018, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef DT_BINDINGS_SOUND_CS48L32_H +#define DT_BINDINGS_SOUND_CS48L32_H + +#define CS48L32_IN_TYPE_DIFF 0 +#define CS48L32_IN_TYPE_SE 1 + +#define CS48L32_PDM_SUP_VOUT_MIC 0 +#define CS48L32_PDM_SUP_MICBIAS1 1 +#define CS48L32_PDM_SUP_MICBIAS2 2 +#define CS48L32_PDM_SUP_MICBIAS3 3 + +#define CS48L32_PDM_FMT_MODE_A_LSB_FIRST 0x0000 +#define CS48L32_PDM_FMT_MODE_B_LSB_FIRST 0x4000 +#define CS48L32_PDM_FMT_MODE_A_MSB_FIRST 0x8000 +#define CS48L32_PDM_FMT_MODE_B_MSB_FIRST 0xc000 + +#endif -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* Re: [PATCH 11/12] dt-bindings: sound: Add Cirrus Logic CS48L31/32/33 codecs 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-09 21:09 ` Rob Herring -1 siblings, 0 replies; 98+ messages in thread From: Rob Herring @ 2022-11-09 21:09 UTC (permalink / raw) To: Richard Fitzgerald Cc: broonie, alsa-devel, tglx, linux-gpio, maz, lee, linus.walleij, devicetree, robh+dt, krzysztof.kozlowski+dt, linux-kernel, patches On Wed, 09 Nov 2022 16:53:30 +0000, Richard Fitzgerald wrote: > Codecs in this family have multiple digital and analog audio I/O that > support a variety of external hardware connections and configurations. > > Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> > --- > .../bindings/sound/cirrus,cs48l32.yaml | 96 +++++++++++++++++++ > include/dt-bindings/sound/cs48l32.h | 25 +++++ > 2 files changed, 121 insertions(+) > create mode 100644 Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml > create mode 100644 include/dt-bindings/sound/cs48l32.h > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml:44:20: [error] syntax error: mapping values are not allowed here (syntax) dtschema/dtc warnings/errors: make[1]: *** Deleting file 'Documentation/devicetree/bindings/sound/cirrus,cs48l32.example.dts' Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml:44:20: mapping values are not allowed here make[1]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/sound/cirrus,cs48l32.example.dts] Error 1 make[1]: *** Waiting for unfinished jobs.... ./Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml:44:20: mapping values are not allowed here /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml: ignoring, error parsing file make: *** [Makefile:1492: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml: Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 11/12] dt-bindings: sound: Add Cirrus Logic CS48L31/32/33 codecs @ 2022-11-09 21:09 ` Rob Herring 0 siblings, 0 replies; 98+ messages in thread From: Rob Herring @ 2022-11-09 21:09 UTC (permalink / raw) To: Richard Fitzgerald Cc: devicetree, alsa-devel, maz, linus.walleij, lee, linux-kernel, robh+dt, linux-gpio, broonie, krzysztof.kozlowski+dt, patches, tglx On Wed, 09 Nov 2022 16:53:30 +0000, Richard Fitzgerald wrote: > Codecs in this family have multiple digital and analog audio I/O that > support a variety of external hardware connections and configurations. > > Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> > --- > .../bindings/sound/cirrus,cs48l32.yaml | 96 +++++++++++++++++++ > include/dt-bindings/sound/cs48l32.h | 25 +++++ > 2 files changed, 121 insertions(+) > create mode 100644 Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml > create mode 100644 include/dt-bindings/sound/cs48l32.h > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml:44:20: [error] syntax error: mapping values are not allowed here (syntax) dtschema/dtc warnings/errors: make[1]: *** Deleting file 'Documentation/devicetree/bindings/sound/cirrus,cs48l32.example.dts' Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml:44:20: mapping values are not allowed here make[1]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/sound/cirrus,cs48l32.example.dts] Error 1 make[1]: *** Waiting for unfinished jobs.... ./Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml:44:20: mapping values are not allowed here /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml: ignoring, error parsing file make: *** [Makefile:1492: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml: Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 11/12] dt-bindings: sound: Add Cirrus Logic CS48L31/32/33 codecs 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-14 8:45 ` Krzysztof Kozlowski -1 siblings, 0 replies; 98+ messages in thread From: Krzysztof Kozlowski @ 2022-11-14 8:45 UTC (permalink / raw) To: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches On 09/11/2022 17:53, Richard Fitzgerald wrote: > Codecs in this family have multiple digital and analog audio I/O that > support a variety of external hardware connections and configurations. > > Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> > --- > .../bindings/sound/cirrus,cs48l32.yaml | 96 +++++++++++++++++++ > include/dt-bindings/sound/cs48l32.h | 25 +++++ > 2 files changed, 121 insertions(+) > create mode 100644 Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml > create mode 100644 include/dt-bindings/sound/cs48l32.h > > diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml > new file mode 100644 > index 000000000000..70fb294c6dc1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml > @@ -0,0 +1,96 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/sound/cirrus,cs48l32.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Cirrus Logic CS48L31/32/33 audio CODECs > + > +maintainers: > + - patches@opensource.cirrus.com > + > +description: | > + This describes audio configuration bindings for these codecs. Don't start with "This". Instead describe the hardware. > + > + See also the core bindings for the parent MFD driver: > + > + Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml Same comment as for pinctrl patch. > + > + and defines for values used in these bindings: > + > + include/dt-bindings/sound/cs48l32.h > + > + The properties are all contained in the parent MFD node. > + > +properties: Missing compatible. What's the point to organize bindings like that? The schema on its own does nothing - does not match anything. > + '#sound-dai-cells': > + const: 1 > + > + cirrus,in-type: > + description: > + A list of input type settings for each input. A maximum of 8 cells, > + with four cells per input in the order INnL_1, INnR_1 INnL_2 INnR_2. > + (where _1 and _2 are the alternative mux selections for that INn). > + If the array is shorter than the number of inputs the unspecified > + inputs default to CS48L32_IN_TYPE_DIFF. > + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" Drop quotes. > + minItems: 1 > + maxItems: 8 > + items: > + items: > + - description: > + The first cell is INnL_1 input type. One of the CS48L32_IN_TYPE_xxx. > + For non-muxed inputs this sets the type of INnL. What is the "input type"? Referring to constants is not enough, especially that they are not descriptive. Explain here the values. > + minimum: 0 > + maximum: 1 > + - description: > + The second cell is INnR_1 input type. One of the CS48L32_IN_TYPE_xxx. > + For non-muxed inputs this sets the type of INnR. > + minimum: 0 > + maximum: 1 > + - description: > + The third cell is INnL_2 input type. One of the CS48L32_IN_TYPE_xxx. > + For non-muxed inputs this cell must be 0. > + minimum: 0 > + maximum: 1 > + - description: > + The fourth cell is INnR_2 input type. One of the CS48L32_IN_TYPE_xxx. > + For non-muxed inputs this cell must be 0. > + minimum: 0 > + maximum: 1 > + > + cirrus,max-channels-clocked: > + description: > + Maximum number of channels that clocks will be generated for. When using > + multiple data lines, every sample slot can transfer multiple channels > + (one per data line). This pdata sets the maximum number of slots. > + One cell for each ASP, use a value of zero for ASPs that should be > + handled normally. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 1 > + maxItems: 4 > + items: > + default: 0 > + > + cirrus,pdm-sup: > + description: > + Indicates how the MICBIAS pins have been externally connected to DMICs > + on each input. One cell per input (IN1, IN2, ...). One of the > + CS48L32_MICBIAS_xxx values. > + See the INn_PDM_SUP field in the datasheet for a description. No, explain here. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 1 > + maxItems: 4 > + > +examples: > + - | > + cs48l32@0 { Node names should be generic. https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation > + compatible = "cirrus,cs48l32"; > + Use 4 spaces for example indentation. > + cirrus,in-type = < > + CS48L32_IN_TYPE_DIFF CS48L32_IN_TYPE_DIFF /* IN1[LR]_1 differential */ > + CS48L32_IN_TYPE_SE CS48L32_IN_TYPE_SE /* IN1[LR]_2 single-ended */ > + CS48L32_IN_TYPE_DIFF CS48L32_IN_TYPE_DIFF /* IN2[LR]_1 differential */ > + >; > + cirrus,max-channels-clocked = <2 0 0>; > + }; > diff --git a/include/dt-bindings/sound/cs48l32.h b/include/dt-bindings/sound/cs48l32.h > new file mode 100644 > index 000000000000..0b774da0a6c8 > --- /dev/null > +++ b/include/dt-bindings/sound/cs48l32.h > @@ -0,0 +1,25 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ Dual license. > +/* > + * Device Tree defines for CS48L32 codec. > + * > + * Copyright (C) 2016-2018, 2022 Cirrus Logic, Inc. and > + * Cirrus Logic International Semiconductor Ltd. > + */ > + > +#ifndef DT_BINDINGS_SOUND_CS48L32_H > +#define DT_BINDINGS_SOUND_CS48L32_H > + > +#define CS48L32_IN_TYPE_DIFF 0 > +#define CS48L32_IN_TYPE_SE 1 > + > +#define CS48L32_PDM_SUP_VOUT_MIC 0 > +#define CS48L32_PDM_SUP_MICBIAS1 1 > +#define CS48L32_PDM_SUP_MICBIAS2 2 > +#define CS48L32_PDM_SUP_MICBIAS3 3 > + > +#define CS48L32_PDM_FMT_MODE_A_LSB_FIRST 0x0000 > +#define CS48L32_PDM_FMT_MODE_B_LSB_FIRST 0x4000 > +#define CS48L32_PDM_FMT_MODE_A_MSB_FIRST 0x8000 > +#define CS48L32_PDM_FMT_MODE_B_MSB_FIRST 0xc000 Register values do not belong to bindings. > + > +#endif Best regards, Krzysztof ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 11/12] dt-bindings: sound: Add Cirrus Logic CS48L31/32/33 codecs @ 2022-11-14 8:45 ` Krzysztof Kozlowski 0 siblings, 0 replies; 98+ messages in thread From: Krzysztof Kozlowski @ 2022-11-14 8:45 UTC (permalink / raw) To: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio On 09/11/2022 17:53, Richard Fitzgerald wrote: > Codecs in this family have multiple digital and analog audio I/O that > support a variety of external hardware connections and configurations. > > Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> > --- > .../bindings/sound/cirrus,cs48l32.yaml | 96 +++++++++++++++++++ > include/dt-bindings/sound/cs48l32.h | 25 +++++ > 2 files changed, 121 insertions(+) > create mode 100644 Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml > create mode 100644 include/dt-bindings/sound/cs48l32.h > > diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml > new file mode 100644 > index 000000000000..70fb294c6dc1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml > @@ -0,0 +1,96 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/sound/cirrus,cs48l32.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Cirrus Logic CS48L31/32/33 audio CODECs > + > +maintainers: > + - patches@opensource.cirrus.com > + > +description: | > + This describes audio configuration bindings for these codecs. Don't start with "This". Instead describe the hardware. > + > + See also the core bindings for the parent MFD driver: > + > + Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml Same comment as for pinctrl patch. > + > + and defines for values used in these bindings: > + > + include/dt-bindings/sound/cs48l32.h > + > + The properties are all contained in the parent MFD node. > + > +properties: Missing compatible. What's the point to organize bindings like that? The schema on its own does nothing - does not match anything. > + '#sound-dai-cells': > + const: 1 > + > + cirrus,in-type: > + description: > + A list of input type settings for each input. A maximum of 8 cells, > + with four cells per input in the order INnL_1, INnR_1 INnL_2 INnR_2. > + (where _1 and _2 are the alternative mux selections for that INn). > + If the array is shorter than the number of inputs the unspecified > + inputs default to CS48L32_IN_TYPE_DIFF. > + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" Drop quotes. > + minItems: 1 > + maxItems: 8 > + items: > + items: > + - description: > + The first cell is INnL_1 input type. One of the CS48L32_IN_TYPE_xxx. > + For non-muxed inputs this sets the type of INnL. What is the "input type"? Referring to constants is not enough, especially that they are not descriptive. Explain here the values. > + minimum: 0 > + maximum: 1 > + - description: > + The second cell is INnR_1 input type. One of the CS48L32_IN_TYPE_xxx. > + For non-muxed inputs this sets the type of INnR. > + minimum: 0 > + maximum: 1 > + - description: > + The third cell is INnL_2 input type. One of the CS48L32_IN_TYPE_xxx. > + For non-muxed inputs this cell must be 0. > + minimum: 0 > + maximum: 1 > + - description: > + The fourth cell is INnR_2 input type. One of the CS48L32_IN_TYPE_xxx. > + For non-muxed inputs this cell must be 0. > + minimum: 0 > + maximum: 1 > + > + cirrus,max-channels-clocked: > + description: > + Maximum number of channels that clocks will be generated for. When using > + multiple data lines, every sample slot can transfer multiple channels > + (one per data line). This pdata sets the maximum number of slots. > + One cell for each ASP, use a value of zero for ASPs that should be > + handled normally. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 1 > + maxItems: 4 > + items: > + default: 0 > + > + cirrus,pdm-sup: > + description: > + Indicates how the MICBIAS pins have been externally connected to DMICs > + on each input. One cell per input (IN1, IN2, ...). One of the > + CS48L32_MICBIAS_xxx values. > + See the INn_PDM_SUP field in the datasheet for a description. No, explain here. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 1 > + maxItems: 4 > + > +examples: > + - | > + cs48l32@0 { Node names should be generic. https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation > + compatible = "cirrus,cs48l32"; > + Use 4 spaces for example indentation. > + cirrus,in-type = < > + CS48L32_IN_TYPE_DIFF CS48L32_IN_TYPE_DIFF /* IN1[LR]_1 differential */ > + CS48L32_IN_TYPE_SE CS48L32_IN_TYPE_SE /* IN1[LR]_2 single-ended */ > + CS48L32_IN_TYPE_DIFF CS48L32_IN_TYPE_DIFF /* IN2[LR]_1 differential */ > + >; > + cirrus,max-channels-clocked = <2 0 0>; > + }; > diff --git a/include/dt-bindings/sound/cs48l32.h b/include/dt-bindings/sound/cs48l32.h > new file mode 100644 > index 000000000000..0b774da0a6c8 > --- /dev/null > +++ b/include/dt-bindings/sound/cs48l32.h > @@ -0,0 +1,25 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ Dual license. > +/* > + * Device Tree defines for CS48L32 codec. > + * > + * Copyright (C) 2016-2018, 2022 Cirrus Logic, Inc. and > + * Cirrus Logic International Semiconductor Ltd. > + */ > + > +#ifndef DT_BINDINGS_SOUND_CS48L32_H > +#define DT_BINDINGS_SOUND_CS48L32_H > + > +#define CS48L32_IN_TYPE_DIFF 0 > +#define CS48L32_IN_TYPE_SE 1 > + > +#define CS48L32_PDM_SUP_VOUT_MIC 0 > +#define CS48L32_PDM_SUP_MICBIAS1 1 > +#define CS48L32_PDM_SUP_MICBIAS2 2 > +#define CS48L32_PDM_SUP_MICBIAS3 3 > + > +#define CS48L32_PDM_FMT_MODE_A_LSB_FIRST 0x0000 > +#define CS48L32_PDM_FMT_MODE_B_LSB_FIRST 0x4000 > +#define CS48L32_PDM_FMT_MODE_A_MSB_FIRST 0x8000 > +#define CS48L32_PDM_FMT_MODE_B_MSB_FIRST 0xc000 Register values do not belong to bindings. > + > +#endif Best regards, Krzysztof ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 11/12] dt-bindings: sound: Add Cirrus Logic CS48L31/32/33 codecs 2022-11-14 8:45 ` Krzysztof Kozlowski @ 2022-11-14 11:00 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-14 11:00 UTC (permalink / raw) To: Krzysztof Kozlowski, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches On 14/11/2022 08:45, Krzysztof Kozlowski wrote: > On 09/11/2022 17:53, Richard Fitzgerald wrote: >> Codecs in this family have multiple digital and analog audio I/O that >> support a variety of external hardware connections and configurations. >> >> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> >> --- >> .../bindings/sound/cirrus,cs48l32.yaml | 96 +++++++++++++++++++ >> include/dt-bindings/sound/cs48l32.h | 25 +++++ >> 2 files changed, 121 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >> create mode 100644 include/dt-bindings/sound/cs48l32.h >> >> diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >> new file mode 100644 >> index 000000000000..70fb294c6dc1 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >> @@ -0,0 +1,96 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/sound/cirrus,cs48l32.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Cirrus Logic CS48L31/32/33 audio CODECs >> + >> +maintainers: >> + - patches@opensource.cirrus.com >> + >> +description: | >> + This describes audio configuration bindings for these codecs. > > Don't start with "This". Instead describe the hardware. > >> + >> + See also the core bindings for the parent MFD driver: >> + >> + Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml > > Same comment as for pinctrl patch. > >> + >> + and defines for values used in these bindings: >> + >> + include/dt-bindings/sound/cs48l32.h >> + >> + The properties are all contained in the parent MFD node. >> + >> +properties: > > Missing compatible. What's the point to organize bindings like that? The > schema on its own does nothing - does not match anything. Do you mean child drivers should not share the MFD node? Or do you mean that if they share the MFD node all the child driver bindings should be documented in the MFD schema instead of having a sub-schema for each class of hardware functionality? I'm certainly willing to collapse all the bindings into a single MFD schema yaml. For this driver we followed the same structure that was accepted for madera (and there was some discussion when we upstreamed madera about how the bindings should be organized which resulted in them being changed). We pretty much assumed that the safe bet was to do the same that was accepted by the maintainer last time around. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 11/12] dt-bindings: sound: Add Cirrus Logic CS48L31/32/33 codecs @ 2022-11-14 11:00 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-14 11:00 UTC (permalink / raw) To: Krzysztof Kozlowski, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio On 14/11/2022 08:45, Krzysztof Kozlowski wrote: > On 09/11/2022 17:53, Richard Fitzgerald wrote: >> Codecs in this family have multiple digital and analog audio I/O that >> support a variety of external hardware connections and configurations. >> >> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> >> --- >> .../bindings/sound/cirrus,cs48l32.yaml | 96 +++++++++++++++++++ >> include/dt-bindings/sound/cs48l32.h | 25 +++++ >> 2 files changed, 121 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >> create mode 100644 include/dt-bindings/sound/cs48l32.h >> >> diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >> new file mode 100644 >> index 000000000000..70fb294c6dc1 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >> @@ -0,0 +1,96 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/sound/cirrus,cs48l32.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Cirrus Logic CS48L31/32/33 audio CODECs >> + >> +maintainers: >> + - patches@opensource.cirrus.com >> + >> +description: | >> + This describes audio configuration bindings for these codecs. > > Don't start with "This". Instead describe the hardware. > >> + >> + See also the core bindings for the parent MFD driver: >> + >> + Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml > > Same comment as for pinctrl patch. > >> + >> + and defines for values used in these bindings: >> + >> + include/dt-bindings/sound/cs48l32.h >> + >> + The properties are all contained in the parent MFD node. >> + >> +properties: > > Missing compatible. What's the point to organize bindings like that? The > schema on its own does nothing - does not match anything. Do you mean child drivers should not share the MFD node? Or do you mean that if they share the MFD node all the child driver bindings should be documented in the MFD schema instead of having a sub-schema for each class of hardware functionality? I'm certainly willing to collapse all the bindings into a single MFD schema yaml. For this driver we followed the same structure that was accepted for madera (and there was some discussion when we upstreamed madera about how the bindings should be organized which resulted in them being changed). We pretty much assumed that the safe bet was to do the same that was accepted by the maintainer last time around. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 11/12] dt-bindings: sound: Add Cirrus Logic CS48L31/32/33 codecs 2022-11-14 11:00 ` Richard Fitzgerald @ 2022-11-14 11:03 ` Krzysztof Kozlowski -1 siblings, 0 replies; 98+ messages in thread From: Krzysztof Kozlowski @ 2022-11-14 11:03 UTC (permalink / raw) To: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches On 14/11/2022 12:00, Richard Fitzgerald wrote: > On 14/11/2022 08:45, Krzysztof Kozlowski wrote: >> On 09/11/2022 17:53, Richard Fitzgerald wrote: >>> Codecs in this family have multiple digital and analog audio I/O that >>> support a variety of external hardware connections and configurations. >>> >>> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> >>> --- >>> .../bindings/sound/cirrus,cs48l32.yaml | 96 +++++++++++++++++++ >>> include/dt-bindings/sound/cs48l32.h | 25 +++++ >>> 2 files changed, 121 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >>> create mode 100644 include/dt-bindings/sound/cs48l32.h >>> >>> diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >>> new file mode 100644 >>> index 000000000000..70fb294c6dc1 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >>> @@ -0,0 +1,96 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/sound/cirrus,cs48l32.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Cirrus Logic CS48L31/32/33 audio CODECs >>> + >>> +maintainers: >>> + - patches@opensource.cirrus.com >>> + >>> +description: | >>> + This describes audio configuration bindings for these codecs. >> >> Don't start with "This". Instead describe the hardware. >> >>> + >>> + See also the core bindings for the parent MFD driver: >>> + >>> + Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml >> >> Same comment as for pinctrl patch. >> >>> + >>> + and defines for values used in these bindings: >>> + >>> + include/dt-bindings/sound/cs48l32.h >>> + >>> + The properties are all contained in the parent MFD node. >>> + >>> +properties: >> >> Missing compatible. What's the point to organize bindings like that? The >> schema on its own does nothing - does not match anything. > > Do you mean child drivers should not share the MFD node? Or do you mean > that if they share the MFD node all the child driver bindings should be > documented in the MFD schema instead of having a sub-schema for each > class of hardware functionality? I mean, that regular binding has a compatible which allows the schema to be matched. Splitting parts from top-level properties is used only for re-usable shared/common schemas, which does not seem the case here. > > I'm certainly willing to collapse all the bindings into a single MFD > schema yaml. For this driver we followed the same structure that was > accepted for madera (and there was some discussion when we upstreamed > madera about how the bindings should be organized which resulted in > them being changed). We pretty much assumed that the safe bet was to do > the same that was accepted by the maintainer last time around. Just merge it with MFD binding. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 11/12] dt-bindings: sound: Add Cirrus Logic CS48L31/32/33 codecs @ 2022-11-14 11:03 ` Krzysztof Kozlowski 0 siblings, 0 replies; 98+ messages in thread From: Krzysztof Kozlowski @ 2022-11-14 11:03 UTC (permalink / raw) To: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio On 14/11/2022 12:00, Richard Fitzgerald wrote: > On 14/11/2022 08:45, Krzysztof Kozlowski wrote: >> On 09/11/2022 17:53, Richard Fitzgerald wrote: >>> Codecs in this family have multiple digital and analog audio I/O that >>> support a variety of external hardware connections and configurations. >>> >>> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> >>> --- >>> .../bindings/sound/cirrus,cs48l32.yaml | 96 +++++++++++++++++++ >>> include/dt-bindings/sound/cs48l32.h | 25 +++++ >>> 2 files changed, 121 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >>> create mode 100644 include/dt-bindings/sound/cs48l32.h >>> >>> diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >>> new file mode 100644 >>> index 000000000000..70fb294c6dc1 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >>> @@ -0,0 +1,96 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/sound/cirrus,cs48l32.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Cirrus Logic CS48L31/32/33 audio CODECs >>> + >>> +maintainers: >>> + - patches@opensource.cirrus.com >>> + >>> +description: | >>> + This describes audio configuration bindings for these codecs. >> >> Don't start with "This". Instead describe the hardware. >> >>> + >>> + See also the core bindings for the parent MFD driver: >>> + >>> + Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml >> >> Same comment as for pinctrl patch. >> >>> + >>> + and defines for values used in these bindings: >>> + >>> + include/dt-bindings/sound/cs48l32.h >>> + >>> + The properties are all contained in the parent MFD node. >>> + >>> +properties: >> >> Missing compatible. What's the point to organize bindings like that? The >> schema on its own does nothing - does not match anything. > > Do you mean child drivers should not share the MFD node? Or do you mean > that if they share the MFD node all the child driver bindings should be > documented in the MFD schema instead of having a sub-schema for each > class of hardware functionality? I mean, that regular binding has a compatible which allows the schema to be matched. Splitting parts from top-level properties is used only for re-usable shared/common schemas, which does not seem the case here. > > I'm certainly willing to collapse all the bindings into a single MFD > schema yaml. For this driver we followed the same structure that was > accepted for madera (and there was some discussion when we upstreamed > madera about how the bindings should be organized which resulted in > them being changed). We pretty much assumed that the safe bet was to do > the same that was accepted by the maintainer last time around. Just merge it with MFD binding. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 11/12] dt-bindings: sound: Add Cirrus Logic CS48L31/32/33 codecs 2022-11-14 11:03 ` Krzysztof Kozlowski @ 2022-11-14 12:34 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-14 12:34 UTC (permalink / raw) To: Krzysztof Kozlowski, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches On 14/11/2022 11:03, Krzysztof Kozlowski wrote: > On 14/11/2022 12:00, Richard Fitzgerald wrote: >> On 14/11/2022 08:45, Krzysztof Kozlowski wrote: >>> On 09/11/2022 17:53, Richard Fitzgerald wrote: >>>> Codecs in this family have multiple digital and analog audio I/O that >>>> support a variety of external hardware connections and configurations. >>>> >>>> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> >>>> --- >>>> .../bindings/sound/cirrus,cs48l32.yaml | 96 +++++++++++++++++++ >>>> include/dt-bindings/sound/cs48l32.h | 25 +++++ >>>> 2 files changed, 121 insertions(+) >>>> create mode 100644 Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >>>> create mode 100644 include/dt-bindings/sound/cs48l32.h >>>> >>>> diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >>>> new file mode 100644 >>>> index 000000000000..70fb294c6dc1 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >>>> @@ -0,0 +1,96 @@ >>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/sound/cirrus,cs48l32.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Cirrus Logic CS48L31/32/33 audio CODECs >>>> + >>>> +maintainers: >>>> + - patches@opensource.cirrus.com >>>> + >>>> +description: | >>>> + This describes audio configuration bindings for these codecs. >>> >>> Don't start with "This". Instead describe the hardware. >>> >>>> + >>>> + See also the core bindings for the parent MFD driver: >>>> + >>>> + Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml >>> >>> Same comment as for pinctrl patch. >>> >>>> + >>>> + and defines for values used in these bindings: >>>> + >>>> + include/dt-bindings/sound/cs48l32.h >>>> + >>>> + The properties are all contained in the parent MFD node. >>>> + >>>> +properties: >>> >>> Missing compatible. What's the point to organize bindings like that? The >>> schema on its own does nothing - does not match anything. >> >> Do you mean child drivers should not share the MFD node? Or do you mean >> that if they share the MFD node all the child driver bindings should be >> documented in the MFD schema instead of having a sub-schema for each >> class of hardware functionality? > > I mean, that regular binding has a compatible which allows the schema to > be matched. > > Splitting parts from top-level properties is used only for re-usable > shared/common schemas, which does not seem the case here. > Ok, that's good. None of these drivers are re-useable standalone. I'll squash the bindings all into MFD schema for V2. >> >> I'm certainly willing to collapse all the bindings into a single MFD >> schema yaml. For this driver we followed the same structure that was >> accepted for madera (and there was some discussion when we upstreamed >> madera about how the bindings should be organized which resulted in >> them being changed). We pretty much assumed that the safe bet was to do >> the same that was accepted by the maintainer last time around. > > Just merge it with MFD binding. > > Best regards, > Krzysztof > ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 11/12] dt-bindings: sound: Add Cirrus Logic CS48L31/32/33 codecs @ 2022-11-14 12:34 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-14 12:34 UTC (permalink / raw) To: Krzysztof Kozlowski, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio On 14/11/2022 11:03, Krzysztof Kozlowski wrote: > On 14/11/2022 12:00, Richard Fitzgerald wrote: >> On 14/11/2022 08:45, Krzysztof Kozlowski wrote: >>> On 09/11/2022 17:53, Richard Fitzgerald wrote: >>>> Codecs in this family have multiple digital and analog audio I/O that >>>> support a variety of external hardware connections and configurations. >>>> >>>> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> >>>> --- >>>> .../bindings/sound/cirrus,cs48l32.yaml | 96 +++++++++++++++++++ >>>> include/dt-bindings/sound/cs48l32.h | 25 +++++ >>>> 2 files changed, 121 insertions(+) >>>> create mode 100644 Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >>>> create mode 100644 include/dt-bindings/sound/cs48l32.h >>>> >>>> diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >>>> new file mode 100644 >>>> index 000000000000..70fb294c6dc1 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml >>>> @@ -0,0 +1,96 @@ >>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/sound/cirrus,cs48l32.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Cirrus Logic CS48L31/32/33 audio CODECs >>>> + >>>> +maintainers: >>>> + - patches@opensource.cirrus.com >>>> + >>>> +description: | >>>> + This describes audio configuration bindings for these codecs. >>> >>> Don't start with "This". Instead describe the hardware. >>> >>>> + >>>> + See also the core bindings for the parent MFD driver: >>>> + >>>> + Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml >>> >>> Same comment as for pinctrl patch. >>> >>>> + >>>> + and defines for values used in these bindings: >>>> + >>>> + include/dt-bindings/sound/cs48l32.h >>>> + >>>> + The properties are all contained in the parent MFD node. >>>> + >>>> +properties: >>> >>> Missing compatible. What's the point to organize bindings like that? The >>> schema on its own does nothing - does not match anything. >> >> Do you mean child drivers should not share the MFD node? Or do you mean >> that if they share the MFD node all the child driver bindings should be >> documented in the MFD schema instead of having a sub-schema for each >> class of hardware functionality? > > I mean, that regular binding has a compatible which allows the schema to > be matched. > > Splitting parts from top-level properties is used only for re-usable > shared/common schemas, which does not seem the case here. > Ok, that's good. None of these drivers are re-useable standalone. I'll squash the bindings all into MFD schema for V2. >> >> I'm certainly willing to collapse all the bindings into a single MFD >> schema yaml. For this driver we followed the same structure that was >> accepted for madera (and there was some discussion when we upstreamed >> madera about how the bindings should be organized which resulted in >> them being changed). We pretty much assumed that the safe bet was to do >> the same that was accepted by the maintainer last time around. > > Just merge it with MFD binding. > > Best regards, > Krzysztof > ^ permalink raw reply [flat|nested] 98+ messages in thread
* [PATCH 12/12] ASoC: cs48l32: Add codec driver for Cirrus Logic CS48L31/32/33 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-09 16:53 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: alsa-devel, devicetree, linux-gpio, linux-kernel, patches, Richard Fitzgerald From: Stuart Henderson <stuarth@opensource.cirrus.com> The CS48L32 is a high-performance low-power audio DSP for smartphones and other portable audio devices. The CS48L32 combines a programmable Halo Core DSP with a variety of power-efficient fixed-function audio processors. Signed-off-by: Piotr Stankiewicz <piotrs@opensource.cirrus.com> Signed-off-by: Stuart Henderson <stuarth@opensource.cirrus.com> Signed-off-by: Qi Zhou <qi.zhou@cirrus.com> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- MAINTAINERS | 4 + include/sound/cs48l32.h | 89 + sound/soc/codecs/Kconfig | 9 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/cs48l32-core.c | 2782 +++++++++++++++++++++++++++++++ sound/soc/codecs/cs48l32.c | 1211 ++++++++++++++ sound/soc/codecs/cs48l32.h | 386 +++++ 7 files changed, 4483 insertions(+) create mode 100644 include/sound/cs48l32.h create mode 100644 sound/soc/codecs/cs48l32-core.c create mode 100644 sound/soc/codecs/cs48l32.c create mode 100644 sound/soc/codecs/cs48l32.h diff --git a/MAINTAINERS b/MAINTAINERS index f52e9a6e290c..9d5ddb50f388 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5013,6 +5013,7 @@ F: Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml F: Documentation/devicetree/bindings/mfd/cirrus,madera.yaml F: Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml F: Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml +F: Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml F: Documentation/devicetree/bindings/sound/cirrus,madera.yaml F: drivers/gpio/gpio-madera* F: drivers/irqchip/irq-cirrus-cs48l32* @@ -5021,13 +5022,16 @@ F: drivers/mfd/cs47l* F: drivers/mfd/cs48l* F: drivers/mfd/madera* F: drivers/pinctrl/cirrus/* +F: include/dt-bindings/sound/cs48l32.h F: include/dt-bindings/sound/madera* F: include/linux/irqchip/irq-cirrus-cs48l32* F: include/linux/irqchip/irq-madera* F: include/linux/mfd/cs48l32/* F: include/linux/mfd/madera/* +F: include/sound/cs48l32.h F: include/sound/madera* F: sound/soc/codecs/cs47l* +F: sound/soc/codecs/cs48l32* F: sound/soc/codecs/madera* CISCO FCOE HBA DRIVER diff --git a/include/sound/cs48l32.h b/include/sound/cs48l32.h new file mode 100644 index 000000000000..3078bb520dae --- /dev/null +++ b/include/sound/cs48l32.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Cirrus Logic CS48L32 codec + * + * Copyright (C) 2016-2018, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef SOUND_CS48L32_H +#define SOUND_CS48L32_H + +#include <linux/mfd/cs48l32/core.h> +#include <linux/notifier.h> +#include <sound/soc-component.h> + +/* pll_id for snd_soc_component_set_pll() */ +#define CS48L32_FLL1_REFCLK 1 + +/* source for snd_soc_component_set_pll() */ +#define CS48L32_FLL_SRC_NONE -1 +#define CS48L32_FLL_SRC_MCLK1 0 +#define CS48L32_FLL_SRC_PDMCLK 5 +#define CS48L32_FLL_SRC_ASP1_BCLK 8 +#define CS48L32_FLL_SRC_ASP2_BCLK 9 +#define CS48L32_FLL_SRC_ASP1_FSYNC 12 +#define CS48L32_FLL_SRC_ASP2_FSYNC 13 + +/* clk_id for snd_soc_component_set_sysclk() and snd_soc_dai_set_sysclk() */ +#define CS48L32_CLK_SYSCLK_1 1 +#define CS48L32_CLK_SYSCLK_2 2 +#define CS48L32_CLK_SYSCLK_3 3 +#define CS48L32_CLK_SYSCLK_4 4 +#define CS48L32_CLK_DSPCLK 7 +#define CS48L32_CLK_OPCLK 9 +#define CS48L32_CLK_PDM_FLLCLK 13 + +/* source for snd_soc_component_set_sysclk() */ +#define CS48L32_CLK_SRC_MCLK1 0x0 +#define CS48L32_CLK_SRC_FLL1 0x4 +#define CS48L32_CLK_SRC_ASP1_BCLK 0x8 +#define CS48L32_CLK_SRC_ASP2_BCLK 0x9 + +/* Notifier events */ +#define CS48L32_NOTIFY_ULTRASONIC 0x1 + +/** + * struct cs48l32_us_notify_data - Ultrasonic event notification data + * @us_no: Index of ultrasonic block that reported the event. + * + * Data passed in an ultrasonic notification event callback. + */ +struct cs48l32_us_notify_data { + unsigned int us_no; +}; + +/** + * cs48l32_register_notifier() - Register notification event callback + * @component: ASoC component of the cs48l32 driver. + * @nb: Client struct notifier_block. + * + * Return: 0 on success else standard negative error code. + */ +static inline int cs48l32_register_notifier(struct snd_soc_component *component, + struct notifier_block *nb) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(component->dev->parent); + + return blocking_notifier_chain_register(&mfd->notifier, nb); +} + +/** + * cs48l32_unregister_notifier() - Unregister notification event callback + * @component: ASoC component of the cs48l32 driver. + * @nb: Client struct notifier_block. + * + * Unregister an event notifier callback that was registered by + * cs48l32_register_notifier(). + * + * Return: 0 on success else standard negative error code. + */ +static inline int cs48l32_unregister_notifier(struct snd_soc_component *component, + struct notifier_block *nb) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(component->dev->parent); + + return blocking_notifier_chain_unregister(&mfd->notifier, nb); +} + +#endif diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 7a13e750751a..aadbdf33b373 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -87,6 +87,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_CS47L85 imply SND_SOC_CS47L90 imply SND_SOC_CS47L92 + imply SND_SOC_CS48L32 imply SND_SOC_CS53L30 imply SND_SOC_CX20442 imply SND_SOC_CX2072X @@ -351,6 +352,7 @@ config SND_SOC_WM_ADSP select CS_DSP select SND_SOC_COMPRESS default y if SND_SOC_MADERA=y + default y if SND_SOC_CS48L32=y default y if SND_SOC_CS47L24=y default y if SND_SOC_WM5102=y default y if SND_SOC_WM5110=y @@ -358,6 +360,7 @@ config SND_SOC_WM_ADSP default y if SND_SOC_CS35L41_SPI=y default y if SND_SOC_CS35L41_I2C=y default m if SND_SOC_MADERA=m + default m if SND_SOC_CS48L32=m default m if SND_SOC_CS47L24=m default m if SND_SOC_WM5102=m default m if SND_SOC_WM5110=m @@ -816,6 +819,12 @@ config SND_SOC_CS47L92 tristate depends on MFD_CS47L92 +config SND_SOC_CS48L32 + tristate "Cirrus Logic CS48L32 CODEC" + depends on MFD_CS48L32 + help + Enable support for the Cirrus Logic CS48L32 codec. + # Cirrus Logic Quad-Channel ADC config SND_SOC_CS53L30 tristate "Cirrus Logic CS53L30 CODEC" diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 9170ee1447dd..2c59463d1085 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -89,6 +89,7 @@ snd-soc-cs47l35-objs := cs47l35.o snd-soc-cs47l85-objs := cs47l85.o snd-soc-cs47l90-objs := cs47l90.o snd-soc-cs47l92-objs := cs47l92.o +snd-soc-cs48l32-objs := cs48l32.o cs48l32-core.o snd-soc-cs53l30-objs := cs53l30.o snd-soc-cx20442-objs := cx20442.o snd-soc-cx2072x-objs := cx2072x.o @@ -449,6 +450,7 @@ obj-$(CONFIG_SND_SOC_CS47L35) += snd-soc-cs47l35.o obj-$(CONFIG_SND_SOC_CS47L85) += snd-soc-cs47l85.o obj-$(CONFIG_SND_SOC_CS47L90) += snd-soc-cs47l90.o obj-$(CONFIG_SND_SOC_CS47L92) += snd-soc-cs47l92.o +obj-$(CONFIG_SND_SOC_CS48L32) += snd-soc-cs48l32.o obj-$(CONFIG_SND_SOC_CS53L30) += snd-soc-cs53l30.o obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o obj-$(CONFIG_SND_SOC_CX2072X) += snd-soc-cx2072x.o diff --git a/sound/soc/codecs/cs48l32-core.c b/sound/soc/codecs/cs48l32-core.c new file mode 100644 index 000000000000..8daebbb0ea50 --- /dev/null +++ b/sound/soc/codecs/cs48l32-core.c @@ -0,0 +1,2782 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Cirrus Logic CS48L32 codec core support +// +// Copyright (C) 2016-2018, 2020, 2022 Cirrus Logic, Inc. and +// Cirrus Logic International Semiconductor Ltd. +// + +#include <dt-bindings/sound/cs48l32.h> +#include <linux/delay.h> +#include <linux/gcd.h> +#include <linux/mfd/cs48l32/core.h> +#include <linux/mfd/cs48l32/registers.h> +#include <linux/minmax.h> +#include <linux/module.h> +#include <linux/pm_runtime.h> +#include <linux/slab.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/tlv.h> + +#include "cs48l32.h" + +#define CS48L32_ASP_ENABLES1 0x00 +#define CS48L32_ASP_CONTROL1 0x04 +#define CS48L32_ASP_CONTROL2 0x08 +#define CS48L32_ASP_CONTROL3 0x0c +#define CS48L32_ASP_FRAME_CONTROL1 0x10 +#define CS48L32_ASP_FRAME_CONTROL2 0x14 +#define CS48L32_ASP_FRAME_CONTROL5 0x20 +#define CS48L32_ASP_FRAME_CONTROL6 0x24 +#define CS48L32_ASP_DATA_CONTROL1 0x30 +#define CS48L32_ASP_DATA_CONTROL5 0x40 + +#define CS48L32_SYSCLK_RATE_6MHZ 0 +#define CS48L32_SYSCLK_RATE_12MHZ 1 +#define CS48L32_SYSCLK_RATE_24MHZ 2 +#define CS48L32_SYSCLK_RATE_49MHZ 3 +#define CS48L32_SYSCLK_RATE_98MHZ 4 + +#define CS48L32_FLLHJ_INT_MAX_N 1023 +#define CS48L32_FLLHJ_INT_MIN_N 1 +#define CS48L32_FLLHJ_FRAC_MAX_N 255 +#define CS48L32_FLLHJ_FRAC_MIN_N 2 +#define CS48L32_FLLHJ_LP_INT_MODE_THRESH 100000 +#define CS48L32_FLLHJ_LOW_THRESH 192000 +#define CS48L32_FLLHJ_MID_THRESH 1152000 +#define CS48L32_FLLHJ_MAX_THRESH 13000000 +#define CS48L32_FLLHJ_LOW_GAINS 0x23f0 +#define CS48L32_FLLHJ_MID_GAINS 0x22f2 +#define CS48L32_FLLHJ_HIGH_GAINS 0x21f0 +#define CS48L32_FLL_MAX_FOUT 50000000 +#define CS48L32_FLL_MAX_REFDIV 8 + +#define CS48L32_FLL_CONTROL1_OFFS 0x00 +#define CS48L32_FLL_CONTROL2_OFFS 0x04 +#define CS48L32_FLL_CONTROL3_OFFS 0x08 +#define CS48L32_FLL_CONTROL4_OFFS 0x0c +#define CS48L32_FLL_CONTROL5_OFFS 0x10 +#define CS48L32_FLL_CONTROL6_OFFS 0x14 +#define CS48L32_FLL_DIGITAL_TEST2_OFFS 0x34 +#define CS48L32_FLL_GPIO_CLOCK_OFFS 0xa0 + +#define CS48L32_DSP_CLOCK_FREQ_OFFS 0x00000 + +#define CS48L32_ASP_FMT_DSP_MODE_A 0 +#define CS48L32_ASP_FMT_DSP_MODE_B 1 +#define CS48L32_ASP_FMT_I2S_MODE 2 +#define CS48L32_ASP_FMT_LEFT_JUSTIFIED_MODE 3 + +#define CS48L32_HALO_SAMPLE_RATE_RX1 0x00080 +#define CS48L32_HALO_SAMPLE_RATE_TX1 0x00280 +#define CS48L32_HALO_DSP_RATE_MASK 0x1f + +#define cs48l32_fll_err(_fll, fmt, ...) \ + dev_err(_fll->cs48l32->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) +#define cs48l32_fll_warn(_fll, fmt, ...) \ + dev_warn(_fll->cs48l32->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) +#define cs48l32_fll_dbg(_fll, fmt, ...) \ + dev_dbg(_fll->cs48l32->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) + +#define cs48l32_asp_err(_dai, fmt, ...) \ + dev_err(_dai->component->dev, "ASP%d: " fmt, _dai->id, ##__VA_ARGS__) +#define cs48l32_asp_warn(_dai, fmt, ...) \ + dev_warn(_dai->component->dev, "ASP%d: " fmt, _dai->id, ##__VA_ARGS__) +#define cs48l32_asp_dbg(_dai, fmt, ...) \ + dev_dbg(_dai->component->dev, "ASP%d: " fmt, _dai->id, ##__VA_ARGS__) + +const char * const cs48l32_mixer_texts[] = { + "None", + "Tone Generator 1", + "Tone Generator 2", + "Noise Generator", + "IN1L", + "IN1R", + "IN2L", + "IN2R", + "ASP1RX1", + "ASP1RX2", + "ASP1RX3", + "ASP1RX4", + "ASP1RX5", + "ASP1RX6", + "ASP1RX7", + "ASP1RX8", + "ASP2RX1", + "ASP2RX2", + "ASP2RX3", + "ASP2RX4", + "ISRC1INT1", + "ISRC1INT2", + "ISRC1INT3", + "ISRC1INT4", + "ISRC1DEC1", + "ISRC1DEC2", + "ISRC1DEC3", + "ISRC1DEC4", + "ISRC2INT1", + "ISRC2INT2", + "ISRC2DEC1", + "ISRC2DEC2", + "ISRC3INT1", + "ISRC3INT2", + "ISRC3DEC1", + "ISRC3DEC2", + "EQ1", + "EQ2", + "EQ3", + "EQ4", + "DRC1L", + "DRC1R", + "DRC2L", + "DRC2R", + "LHPF1", + "LHPF2", + "LHPF3", + "LHPF4", + "Ultrasonic 1", + "Ultrasonic 2", + "DSP1.1", + "DSP1.2", + "DSP1.3", + "DSP1.4", + "DSP1.5", + "DSP1.6", + "DSP1.7", + "DSP1.8", +}; + +unsigned int cs48l32_mixer_values[] = { + 0x000, /* Silence (mute) */ + 0x004, /* Tone generator 1 */ + 0x005, /* Tone generator 2 */ + 0x00C, /* Noise Generator */ + 0x010, /* IN1L signal path */ + 0x011, /* IN1R signal path */ + 0x012, /* IN2L signal path */ + 0x013, /* IN2R signal path */ + 0x020, /* ASP1 RX1 */ + 0x021, /* ASP1 RX2 */ + 0x022, /* ASP1 RX3 */ + 0x023, /* ASP1 RX4 */ + 0x024, /* ASP1 RX5 */ + 0x025, /* ASP1 RX6 */ + 0x026, /* ASP1 RX7 */ + 0x027, /* ASP1 RX8 */ + 0x030, /* ASP2 RX1 */ + 0x031, /* ASP2 RX2 */ + 0x032, /* ASP2 RX3 */ + 0x033, /* ASP2 RX4 */ + 0x098, /* ISRC1 INT1 */ + 0x099, /* ISRC1 INT2 */ + 0x09a, /* ISRC1 INT3 */ + 0x09b, /* ISRC1 INT4 */ + 0x09C, /* ISRC1 DEC1 */ + 0x09D, /* ISRC1 DEC2 */ + 0x09e, /* ISRC1 DEC3 */ + 0x09f, /* ISRC1 DEC4 */ + 0x0A0, /* ISRC2 INT1 */ + 0x0A1, /* ISRC2 INT2 */ + 0x0A4, /* ISRC2 DEC1 */ + 0x0A5, /* ISRC2 DEC2 */ + 0x0A8, /* ISRC3 INT1 */ + 0x0A9, /* ISRC3 INT2 */ + 0x0AC, /* ISRC3 DEC1 */ + 0x0AD, /* ISRC3 DEC2 */ + 0x0B8, /* EQ1 */ + 0x0B9, /* EQ2 */ + 0x0BA, /* EQ3 */ + 0x0BB, /* EQ4 */ + 0x0C0, /* DRC1 Left */ + 0x0C1, /* DRC1 Right */ + 0x0C2, /* DRC2 Left */ + 0x0C3, /* DRC2 Right */ + 0x0C8, /* LHPF1 */ + 0x0C9, /* LHPF2 */ + 0x0CA, /* LHPF3 */ + 0x0CB, /* LHPF4 */ + 0x0D8, /* Ultrasonic 1 */ + 0x0D9, /* Ultrasonic 2 */ + 0x100, /* DSP1 channel 1 */ + 0x101, /* DSP1 channel 2 */ + 0x102, /* DSP1 channel 3 */ + 0x103, /* DSP1 channel 4 */ + 0x104, /* DSP1 channel 5 */ + 0x105, /* DSP1 channel 6 */ + 0x106, /* DSP1 channel 7 */ + 0x107, /* DSP1 channel 8 */ +}; + +const DECLARE_TLV_DB_SCALE(cs48l32_ana_tlv, 0, 100, 0); +const DECLARE_TLV_DB_SCALE(cs48l32_eq_tlv, -1200, 100, 0); +const DECLARE_TLV_DB_SCALE(cs48l32_digital_tlv, -6400, 50, 0); +const DECLARE_TLV_DB_SCALE(cs48l32_noise_tlv, -10800, 600, 0); +const DECLARE_TLV_DB_SCALE(cs48l32_mixer_tlv, -3200, 100, 0); +const DECLARE_TLV_DB_SCALE(cs48l32_us_tlv, 0, 600, 0); + +static void cs48l32_spin_sysclk(struct cs48l32 *cs48l32) +{ + struct cs48l32_mfd *mfd = cs48l32->mfd; + unsigned int val; + int ret, i; + + /* Skip this if the chip is down */ + if (pm_runtime_suspended(mfd->dev)) + return; + + /* + * Just read a register a few times to ensure the internal + * oscillator sends out a some clocks. + */ + for (i = 0; i < 4; i++) { + ret = regmap_read(mfd->regmap, CS48L32_DEVID, &val); + if (ret) + dev_err(cs48l32->dev, "%s Failed to read register: %d (%d)\n", + __func__, ret, i); + } + + udelay(300); +} + +static const char * const cs48l32_rate_text[] = { + "Sample Rate 1", + "Sample Rate 2", + "Sample Rate 3", + "Sample Rate 4", +}; + +static const unsigned int cs48l32_rate_val[] = { + 0x0, 0x1, 0x2, 0x3, +}; + +int cs48l32_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + int ret; + + /* Prevent any mixer mux changes while we do this */ + mutex_lock(&cs48l32->rate_lock); + + /* The write must be guarded by a number of SYSCLK cycles */ + cs48l32_spin_sysclk(cs48l32); + ret = snd_soc_put_enum_double(kcontrol, ucontrol); + cs48l32_spin_sysclk(cs48l32); + + mutex_unlock(&cs48l32->rate_lock); + + return ret; +} + +static const char * const cs48l32_sample_rate_text[] = { + "12kHz", + "24kHz", + "48kHz", + "96kHz", + "192kHz", + "384kHz", + "768kHz", + "11.025kHz", + "22.05kHz", + "44.1kHz", + "88.2kHz", + "176.4kHz", + "352.8kHz", + "705.6kHz", + "8kHz", + "16kHz", + "32kHz", +}; + +static const unsigned int cs48l32_sample_rate_val[] = { + 0x01, /* 12kHz */ + 0x02, /* 24kHz */ + 0x03, /* 48kHz */ + 0x04, /* 96kHz */ + 0x05, /* 192kHz */ + 0x06, /* 384kHz */ + 0x07, /* 768kHz */ + 0x09, /* 11.025kHz */ + 0x0a, /* 22.05kHz */ + 0x0b, /* 44.1kHz */ + 0x0c, /* 88.2kHz */ + 0x0d, /* 176.4kHz */ + 0x0e, /* 352.8kHz */ + 0x0f, /* 705.6kHz */ + 0x11, /* 8kHz */ + 0x12, /* 16kHz */ + 0x13, /* 32kHz */ +}; + +const struct soc_enum cs48l32_sample_rate[] = { + SOC_VALUE_ENUM_SINGLE(CS48L32_SAMPLE_RATE1, + CS48L32_SAMPLE_RATE_1_SHIFT, + CS48L32_SAMPLE_RATE_1_MASK >> CS48L32_SAMPLE_RATE_1_SHIFT, + CS48L32_SAMPLE_RATE_ENUM_SIZE, + cs48l32_sample_rate_text, + cs48l32_sample_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_SAMPLE_RATE2, + CS48L32_SAMPLE_RATE_1_SHIFT, + CS48L32_SAMPLE_RATE_1_MASK >> CS48L32_SAMPLE_RATE_1_SHIFT, + CS48L32_SAMPLE_RATE_ENUM_SIZE, + cs48l32_sample_rate_text, + cs48l32_sample_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_SAMPLE_RATE3, + CS48L32_SAMPLE_RATE_1_SHIFT, + CS48L32_SAMPLE_RATE_1_MASK >> CS48L32_SAMPLE_RATE_1_SHIFT, + CS48L32_SAMPLE_RATE_ENUM_SIZE, + cs48l32_sample_rate_text, + cs48l32_sample_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_SAMPLE_RATE4, + CS48L32_SAMPLE_RATE_1_SHIFT, + CS48L32_SAMPLE_RATE_1_MASK >> CS48L32_SAMPLE_RATE_1_SHIFT, + CS48L32_SAMPLE_RATE_ENUM_SIZE, + cs48l32_sample_rate_text, + cs48l32_sample_rate_val), +}; + +static int cs48l32_inmux_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol); + struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; + unsigned int mux, src_val, in_type; + int ret; + + mux = ucontrol->value.enumerated.item[0]; + if (mux > 1) + return -EINVAL; + + switch (e->reg) { + case CS48L32_IN1L_CONTROL1: + in_type = cs48l32->in_type[0][2 * mux]; + break; + case CS48L32_IN1R_CONTROL1: + in_type = cs48l32->in_type[0][1 + (2 * mux)]; + break; + case CS48L32_IN2L_CONTROL1: + in_type = cs48l32->in_type[1][2 * mux]; + break; + case CS48L32_IN2R_CONTROL1: + in_type = cs48l32->in_type[1][1 + (2 * mux)]; + break; + default: + return -EINVAL; + } + + src_val = mux << e->shift_l; + + if (in_type == CS48L32_IN_TYPE_SE) + src_val |= 1 << CS48L32_INx_SRC_SHIFT; + + dev_dbg(cs48l32->dev, "mux=%u reg=0x%x in_type=0x%x val=0x%x\n", + mux, e->reg, in_type, src_val); + + ret = snd_soc_component_update_bits(dapm->component, + e->reg, + CS48L32_INx_SRC_MASK, + src_val); + if (ret > 0) + snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL); + + return ret; +} + +static const char * const cs48l32_inmux_texts[] = { + "Analog 1", "Analog 2", +}; + +static SOC_ENUM_SINGLE_DECL(cs48l32_in1muxl_enum, + CS48L32_IN1L_CONTROL1, + CS48L32_INx_SRC_SHIFT + 1, + cs48l32_inmux_texts); + +static SOC_ENUM_SINGLE_DECL(cs48l32_in1muxr_enum, + CS48L32_IN1R_CONTROL1, + CS48L32_INx_SRC_SHIFT + 1, + cs48l32_inmux_texts); + +static SOC_ENUM_SINGLE_DECL(cs48l32_in2muxl_enum, + CS48L32_IN2L_CONTROL1, + CS48L32_INx_SRC_SHIFT + 1, + cs48l32_inmux_texts); + +static SOC_ENUM_SINGLE_DECL(cs48l32_in2muxr_enum, + CS48L32_IN2R_CONTROL1, + CS48L32_INx_SRC_SHIFT + 1, + cs48l32_inmux_texts); + +const struct snd_kcontrol_new cs48l32_inmux[] = { + SOC_DAPM_ENUM_EXT("IN1L Mux", cs48l32_in1muxl_enum, + snd_soc_dapm_get_enum_double, cs48l32_inmux_put), + SOC_DAPM_ENUM_EXT("IN1R Mux", cs48l32_in1muxr_enum, + snd_soc_dapm_get_enum_double, cs48l32_inmux_put), + SOC_DAPM_ENUM_EXT("IN2L Mux", cs48l32_in2muxl_enum, + snd_soc_dapm_get_enum_double, cs48l32_inmux_put), + SOC_DAPM_ENUM_EXT("IN2R Mux", cs48l32_in2muxr_enum, + snd_soc_dapm_get_enum_double, cs48l32_inmux_put), +}; + +static const char * const cs48l32_dmode_texts[] = { + "Analog", "Digital", +}; + +static int cs48l32_dmode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol); + struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); + struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; + unsigned int mode; + int ret, result; + + mode = ucontrol->value.enumerated.item[0]; + switch (mode) { + case 0: + ret = snd_soc_component_update_bits(component, + CS48L32_ADC1L_ANA_CONTROL1, + CS48L32_ADC1x_INT_ENA_FRC_MASK, + CS48L32_ADC1x_INT_ENA_FRC_MASK); + if (ret < 0) { + dev_err(component->dev, + "Failed to set ADC1L_INT_ENA_FRC: %d\n", ret); + return ret; + } + + ret = snd_soc_component_update_bits(component, + CS48L32_ADC1R_ANA_CONTROL1, + CS48L32_ADC1x_INT_ENA_FRC_MASK, + CS48L32_ADC1x_INT_ENA_FRC_MASK); + if (ret < 0) { + dev_err(component->dev, + "Failed to set ADC1R_INT_ENA_FRC: %d\n", ret); + return ret; + } + + result = snd_soc_component_update_bits(component, + e->reg, + BIT(CS48L32_IN1_MODE_SHIFT), + 0); + if (result < 0) { + dev_err(component->dev, "Failed to set input mode: %d\n", result); + return result; + } + + usleep_range(200, 300); + + ret = snd_soc_component_update_bits(component, + CS48L32_ADC1L_ANA_CONTROL1, + CS48L32_ADC1x_INT_ENA_FRC_MASK, + 0); + if (ret < 0) { + dev_err(component->dev, + "Failed to clear ADC1L_INT_ENA_FRC: %d\n", ret); + return ret; + } + + ret = snd_soc_component_update_bits(component, + CS48L32_ADC1R_ANA_CONTROL1, + CS48L32_ADC1x_INT_ENA_FRC_MASK, + 0); + if (ret < 0) { + dev_err(component->dev, + "Failed to clear ADC1R_INT_ENA_FRC: %d\n", ret); + return ret; + } + + if (result > 0) + snd_soc_dapm_mux_update_power(dapm, kcontrol, mode, e, NULL); + + return result; + case 1: + return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); + default: + return -EINVAL; + } +} + +static SOC_ENUM_SINGLE_DECL(cs48l32_in1dmode_enum, + CS48L32_INPUT1_CONTROL1, + CS48L32_IN1_MODE_SHIFT, + cs48l32_dmode_texts); + +const struct snd_kcontrol_new cs48l32_dmode_mux[] = { + SOC_DAPM_ENUM_EXT("IN1 Mode", cs48l32_in1dmode_enum, + snd_soc_dapm_get_enum_double, cs48l32_dmode_put), +}; + +static const char * const cs48l32_in_texts[] = { + "IN1L", "IN1R", "IN2L", "IN2R", +}; + +static const char * const cs48l32_us_freq_texts[] = { + "24.5-40.5kHz", "18-22kHz", "16-24kHz", "20-28kHz", +}; + +static const unsigned int cs48l32_us_freq_val[] = { + 0x2, 0x3, +}; + +const struct soc_enum cs48l32_us_freq[] = { + SOC_VALUE_ENUM_SINGLE(CS48L32_US1_CONTROL, + CS48L32_US1_FREQ_SHIFT, + CS48L32_US1_FREQ_MASK >> CS48L32_US1_FREQ_SHIFT, + ARRAY_SIZE(cs48l32_us_freq_val), + &cs48l32_us_freq_texts[2], + cs48l32_us_freq_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_US2_CONTROL, + CS48L32_US1_FREQ_SHIFT, + CS48L32_US1_FREQ_MASK >> CS48L32_US1_FREQ_SHIFT, + ARRAY_SIZE(cs48l32_us_freq_val), + &cs48l32_us_freq_texts[2], + cs48l32_us_freq_val), +}; + +static const unsigned int cs48l32_us_in_val[] = { + 0x0, 0x1, 0x2, 0x3, +}; + +static const struct soc_enum cs48l32_us_inmux_enum[] = { + SOC_VALUE_ENUM_SINGLE(CS48L32_US1_CONTROL, + CS48L32_US1_SRC_SHIFT, + CS48L32_US1_SRC_MASK >> CS48L32_US1_SRC_SHIFT, + ARRAY_SIZE(cs48l32_us_in_val), + cs48l32_in_texts, + cs48l32_us_in_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_US2_CONTROL, + CS48L32_US1_SRC_SHIFT, + CS48L32_US1_SRC_MASK >> CS48L32_US1_SRC_SHIFT, + ARRAY_SIZE(cs48l32_us_in_val), + cs48l32_in_texts, + cs48l32_us_in_val), +}; + +const struct snd_kcontrol_new cs48l32_us_inmux[] = { + SOC_DAPM_ENUM("Ultrasonic 1 Input", cs48l32_us_inmux_enum[0]), + SOC_DAPM_ENUM("Ultrasonic 2 Input", cs48l32_us_inmux_enum[1]), +}; + +static const char * const cs48l32_us_det_thr_texts[] = { + "-6dB", "-9dB", "-12dB", "-15dB", "-18dB", "-21dB", "-24dB", "-27dB", +}; + +const struct soc_enum cs48l32_us_det_thr[] = { + SOC_ENUM_SINGLE(CS48L32_US1_DET_CONTROL, + CS48L32_US1_DET_THR_SHIFT, + ARRAY_SIZE(cs48l32_us_det_thr_texts), + cs48l32_us_det_thr_texts), + SOC_ENUM_SINGLE(CS48L32_US2_DET_CONTROL, + CS48L32_US1_DET_THR_SHIFT, + ARRAY_SIZE(cs48l32_us_det_thr_texts), + cs48l32_us_det_thr_texts), +}; + +static const char * const cs48l32_us_det_num_texts[] = { + "1 Sample", + "2 Samples", + "4 Samples", + "8 Samples", + "16 Samples", + "32 Samples", + "64 Samples", + "128 Samples", + "256 Samples", + "512 Samples", + "1024 Samples", + "2048 Samples", + "4096 Samples", + "8192 Samples", + "16384 Samples", + "32768 Samples", +}; + +const struct soc_enum cs48l32_us_det_num[] = { + SOC_ENUM_SINGLE(CS48L32_US1_DET_CONTROL, + CS48L32_US1_DET_NUM_SHIFT, + ARRAY_SIZE(cs48l32_us_det_num_texts), + cs48l32_us_det_num_texts), + SOC_ENUM_SINGLE(CS48L32_US2_DET_CONTROL, + CS48L32_US1_DET_NUM_SHIFT, + ARRAY_SIZE(cs48l32_us_det_num_texts), + cs48l32_us_det_num_texts), +}; + +static const char * const cs48l32_us_det_hold_texts[] = { + "0 Samples", + "31 Samples", + "63 Samples", + "127 Samples", + "255 Samples", + "511 Samples", + "1023 Samples", + "2047 Samples", + "4095 Samples", + "8191 Samples", + "16383 Samples", + "32767 Samples", + "65535 Samples", + "131071 Samples", + "262143 Samples", + "524287 Samples", +}; + +const struct soc_enum cs48l32_us_det_hold[] = { + SOC_ENUM_SINGLE(CS48L32_US1_DET_CONTROL, + CS48L32_US1_DET_HOLD_SHIFT, + ARRAY_SIZE(cs48l32_us_det_hold_texts), + cs48l32_us_det_hold_texts), + SOC_ENUM_SINGLE(CS48L32_US2_DET_CONTROL, + CS48L32_US1_DET_HOLD_SHIFT, + ARRAY_SIZE(cs48l32_us_det_hold_texts), + cs48l32_us_det_hold_texts), +}; + +const struct soc_enum cs48l32_us_output_rate[] = { + SOC_VALUE_ENUM_SINGLE(CS48L32_US1_CONTROL, + CS48L32_US1_RATE_SHIFT, + CS48L32_US1_RATE_MASK >> CS48L32_US1_RATE_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_US2_CONTROL, + CS48L32_US1_RATE_SHIFT, + CS48L32_US1_RATE_MASK >> CS48L32_US1_RATE_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), +}; + +static const char * const cs48l32_us_det_lpf_cut_texts[] = { + "1722Hz", "833Hz", "408Hz", "203Hz", +}; + +const struct soc_enum cs48l32_us_det_lpf_cut[] = { + SOC_ENUM_SINGLE(CS48L32_US1_DET_CONTROL, + CS48L32_US1_DET_LPF_CUT_SHIFT, + ARRAY_SIZE(cs48l32_us_det_lpf_cut_texts), + cs48l32_us_det_lpf_cut_texts), + SOC_ENUM_SINGLE(CS48L32_US2_DET_CONTROL, + CS48L32_US1_DET_LPF_CUT_SHIFT, + ARRAY_SIZE(cs48l32_us_det_lpf_cut_texts), + cs48l32_us_det_lpf_cut_texts), +}; + +static const char * const cs48l32_us_det_dcy_texts[] = { + "0 ms", "0.79 ms", "1.58 ms", "3.16 ms", "6.33 ms", "12.67 ms", + "25.34 ms", "50.69 ms", +}; + +const struct soc_enum cs48l32_us_det_dcy[] = { + SOC_ENUM_SINGLE(CS48L32_US1_DET_CONTROL, + CS48L32_US1_DET_DCY_SHIFT, + ARRAY_SIZE(cs48l32_us_det_dcy_texts), + cs48l32_us_det_dcy_texts), + SOC_ENUM_SINGLE(CS48L32_US2_DET_CONTROL, + CS48L32_US1_DET_DCY_SHIFT, + ARRAY_SIZE(cs48l32_us_det_dcy_texts), + cs48l32_us_det_dcy_texts), +}; + +const struct snd_kcontrol_new cs48l32_us_switch[] = { + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), +}; + +static const char * const cs48l32_vol_ramp_text[] = { + "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB", + "16ms/6dB", "32ms/6dB", +}; + +irqreturn_t cs48l32_us1_activity(int irq, void *data) +{ + struct cs48l32 *cs48l32 = data; + struct cs48l32_us_notify_data us_data; + + us_data.us_no = 1; + cs48l32_call_notifiers(cs48l32->mfd, CS48L32_NOTIFY_ULTRASONIC, &us_data); + + return IRQ_HANDLED; +} + +irqreturn_t cs48l32_us2_activity(int irq, void *data) +{ + struct cs48l32 *cs48l32 = data; + struct cs48l32_us_notify_data us_data; + + us_data.us_no = 2; + cs48l32_call_notifiers(cs48l32->mfd, CS48L32_NOTIFY_ULTRASONIC, &us_data); + + return IRQ_HANDLED; +} + +SOC_ENUM_SINGLE_DECL(cs48l32_in_vd_ramp, + CS48L32_INPUT_VOL_CONTROL, + CS48L32_IN_VD_RAMP_SHIFT, + cs48l32_vol_ramp_text); + +SOC_ENUM_SINGLE_DECL(cs48l32_in_vi_ramp, + CS48L32_INPUT_VOL_CONTROL, + CS48L32_IN_VI_RAMP_SHIFT, + cs48l32_vol_ramp_text); + +static const char * const cs48l32_in_hpf_cut_text[] = { + "2.5Hz", "5Hz", "10Hz", "20Hz", "40Hz" +}; + +SOC_ENUM_SINGLE_DECL(cs48l32_in_hpf_cut_enum, + CS48L32_INPUT_HPF_CONTROL, + CS48L32_IN_HPF_CUT_SHIFT, + cs48l32_in_hpf_cut_text); + +static const char * const cs48l32_in_dmic_osr_text[] = { + "384kHz", "768kHz", "1.536MHz", "2.048MHz", "2.4576MHz", "3.072MHz", + "6.144MHz", +}; + +const struct soc_enum cs48l32_in_dmic_osr[] = { + SOC_ENUM_SINGLE(CS48L32_INPUT1_CONTROL1, + CS48L32_IN1_OSR_SHIFT, + ARRAY_SIZE(cs48l32_in_dmic_osr_text), + cs48l32_in_dmic_osr_text), + SOC_ENUM_SINGLE(CS48L32_INPUT2_CONTROL1, + CS48L32_IN1_OSR_SHIFT, + ARRAY_SIZE(cs48l32_in_dmic_osr_text), + cs48l32_in_dmic_osr_text), +}; + +int cs48l32_in_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int reg, shift; + int ret = 0; + + snd_soc_dapm_mutex_lock(dapm); + + /* Cannot change rate on an active input */ + reg = snd_soc_component_read(component, CS48L32_INPUT_CONTROL); + shift = (e->reg - CS48L32_IN1L_CONTROL1) / 0x20; + shift ^= 0x1; /* Flip bottom bit for channel order */ + + if ((reg) & (1 << shift)) { + ret = -EBUSY; + goto exit; + } + + ret = snd_soc_put_enum_double(kcontrol, ucontrol); +exit: + snd_soc_dapm_mutex_unlock(dapm); + return ret; +} + +const struct soc_enum cs48l32_input_rate[] = { + SOC_VALUE_ENUM_SINGLE(CS48L32_IN1L_CONTROL1, + CS48L32_INx_RATE_SHIFT, + CS48L32_INx_RATE_MASK >> CS48L32_INx_RATE_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_IN1R_CONTROL1, + CS48L32_INx_RATE_SHIFT, + CS48L32_INx_RATE_MASK >> CS48L32_INx_RATE_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_IN2L_CONTROL1, + CS48L32_INx_RATE_SHIFT, + CS48L32_INx_RATE_MASK >> CS48L32_INx_RATE_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_IN2R_CONTROL1, + CS48L32_INx_RATE_SHIFT, + CS48L32_INx_RATE_MASK >> CS48L32_INx_RATE_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), +}; + +int cs48l32_low_power_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + unsigned int reg, mask; + int ret; + + snd_soc_dapm_mutex_lock(dapm); + + /* Cannot change low power mode on an active input */ + reg = snd_soc_component_read(component, CS48L32_INPUT_CONTROL); + mask = (mc->reg - CS48L32_IN1L_CONTROL1) / 0x20; + mask ^= 0x1; /* Flip bottom bit for channel order */ + + if ((reg) & (1 << mask)) { + ret = -EBUSY; + dev_err(component->dev, "Can't change lp mode on an active input\n"); + goto exit; + } + + ret = snd_soc_put_volsw(kcontrol, ucontrol); + +exit: + snd_soc_dapm_mutex_unlock(dapm); + return ret; +} + +const struct soc_enum noise_gen_rate = + SOC_VALUE_ENUM_SINGLE(CS48L32_COMFORT_NOISE_GENERATOR, + CS48L32_NOISE_GEN_RATE_SHIFT, + CS48L32_NOISE_GEN_RATE_MASK >> CS48L32_NOISE_GEN_RATE_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val); + +static const char * const cs48l32_auxpdm_freq_texts[] = { + "3.072MHz", "2.048MHz", "1.536MHz", "768kHz", +}; + +SOC_ENUM_SINGLE_DECL(cs48l32_auxpdm1_freq, + CS48L32_AUXPDM1_CONTROL1, + CS48L32_AUXPDM1_FREQ_SHIFT, + cs48l32_auxpdm_freq_texts); + +SOC_ENUM_SINGLE_DECL(cs48l32_auxpdm2_freq, + CS48L32_AUXPDM2_CONTROL1, + CS48L32_AUXPDM1_FREQ_SHIFT, + cs48l32_auxpdm_freq_texts); + +static const char * const cs48l32_auxpdm_src_texts[] = { + "Analog", "IN1 Digital", "IN2 Digital", +}; + +static SOC_ENUM_SINGLE_DECL(cs48l32_auxpdm1_in, + CS48L32_AUXPDM_CTRL2, + CS48L32_AUXPDMDAT1_SRC_SHIFT, + cs48l32_auxpdm_src_texts); + +static SOC_ENUM_SINGLE_DECL(cs48l32_auxpdm2_in, + CS48L32_AUXPDM_CTRL2, + CS48L32_AUXPDMDAT2_SRC_SHIFT, + cs48l32_auxpdm_src_texts); + +const struct snd_kcontrol_new cs48l32_auxpdm_inmux[] = { + SOC_DAPM_ENUM("AUXPDM1 Input", cs48l32_auxpdm1_in), + SOC_DAPM_ENUM("AUXPDM2 Input", cs48l32_auxpdm2_in), +}; + +static const unsigned int cs48l32_auxpdm_analog_in_val[] = { + 0x0, 0x1, +}; + +static const struct soc_enum cs48l32_auxpdm_analog_inmux_enum[] = { + SOC_VALUE_ENUM_SINGLE(CS48L32_AUXPDM1_CONTROL1, + CS48L32_AUXPDM1_SRC_SHIFT, + CS48L32_AUXPDM1_SRC_MASK >> CS48L32_AUXPDM1_SRC_SHIFT, + ARRAY_SIZE(cs48l32_auxpdm_analog_in_val), + cs48l32_in_texts, + cs48l32_auxpdm_analog_in_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_AUXPDM2_CONTROL1, + CS48L32_AUXPDM1_SRC_SHIFT, + CS48L32_AUXPDM1_SRC_MASK >> CS48L32_AUXPDM1_SRC_SHIFT, + ARRAY_SIZE(cs48l32_auxpdm_analog_in_val), + cs48l32_in_texts, + cs48l32_auxpdm_analog_in_val), +}; + +const struct snd_kcontrol_new cs48l32_auxpdm_analog_inmux[] = { + SOC_DAPM_ENUM("AUXPDM1 Analog Input", cs48l32_auxpdm_analog_inmux_enum[0]), + SOC_DAPM_ENUM("AUXPDM2 Analog Input", cs48l32_auxpdm_analog_inmux_enum[1]), +}; + +const struct snd_kcontrol_new cs48l32_auxpdm_switch[] = { + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), +}; + +const struct soc_enum cs48l32_isrc_fsh[] = { + SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC1_CONTROL1, + CS48L32_ISRC1_FSH_SHIFT, + CS48L32_ISRC1_FSH_MASK >> CS48L32_ISRC1_FSH_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC2_CONTROL1, + CS48L32_ISRC1_FSH_SHIFT, + CS48L32_ISRC1_FSH_MASK >> CS48L32_ISRC1_FSH_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC3_CONTROL1, + CS48L32_ISRC1_FSH_SHIFT, + CS48L32_ISRC1_FSH_MASK >> CS48L32_ISRC1_FSH_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), +}; + +const struct soc_enum cs48l32_isrc_fsl[] = { + SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC1_CONTROL1, + CS48L32_ISRC1_FSL_SHIFT, + CS48L32_ISRC1_FSL_MASK >> CS48L32_ISRC1_FSL_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC2_CONTROL1, + CS48L32_ISRC1_FSL_SHIFT, + CS48L32_ISRC1_FSL_MASK >> CS48L32_ISRC1_FSL_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC3_CONTROL1, + CS48L32_ISRC1_FSL_SHIFT, + CS48L32_ISRC1_FSL_MASK >> CS48L32_ISRC1_FSL_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), +}; + +const struct soc_enum cs48l32_fx_rate = + SOC_VALUE_ENUM_SINGLE(CS48L32_FX_SAMPLE_RATE, + CS48L32_FX_RATE_SHIFT, + CS48L32_FX_RATE_MASK >> CS48L32_FX_RATE_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val); + +static const char * const cs48l32_lhpf_mode_text[] = { + "Low-pass", "High-pass" +}; + +const struct soc_enum cs48l32_lhpf_mode[] = { + SOC_ENUM_SINGLE(CS48L32_LHPF_CONTROL2, 0, + ARRAY_SIZE(cs48l32_lhpf_mode_text), cs48l32_lhpf_mode_text), + SOC_ENUM_SINGLE(CS48L32_LHPF_CONTROL2, 1, + ARRAY_SIZE(cs48l32_lhpf_mode_text), cs48l32_lhpf_mode_text), + SOC_ENUM_SINGLE(CS48L32_LHPF_CONTROL2, 2, + ARRAY_SIZE(cs48l32_lhpf_mode_text), cs48l32_lhpf_mode_text), + SOC_ENUM_SINGLE(CS48L32_LHPF_CONTROL2, 3, + ARRAY_SIZE(cs48l32_lhpf_mode_text), cs48l32_lhpf_mode_text), +}; + +int cs48l32_lhpf_coeff_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + __be32 *data = (__be32 *)ucontrol->value.bytes.data; + s16 val = (s16)be32_to_cpu(*data); + + if (abs(val) >= 4096) { + dev_err(cs48l32->dev, "Rejecting unstable LHPF coefficients\n"); + return -EINVAL; + } + + return snd_soc_bytes_put(kcontrol, ucontrol); +} + +static const char * const cs48l32_eq_mode_text[] = { + "Low-pass", "High-pass", +}; + +const struct soc_enum cs48l32_eq_mode[] = { + SOC_ENUM_SINGLE(CS48L32_EQ_CONTROL2, 0, + ARRAY_SIZE(cs48l32_eq_mode_text), + cs48l32_eq_mode_text), + SOC_ENUM_SINGLE(CS48L32_EQ_CONTROL2, 1, + ARRAY_SIZE(cs48l32_eq_mode_text), + cs48l32_eq_mode_text), + SOC_ENUM_SINGLE(CS48L32_EQ_CONTROL2, 2, + ARRAY_SIZE(cs48l32_eq_mode_text), + cs48l32_eq_mode_text), + SOC_ENUM_SINGLE(CS48L32_EQ_CONTROL2, 3, + ARRAY_SIZE(cs48l32_eq_mode_text), + cs48l32_eq_mode_text), +}; + +int cs48l32_eq_mode_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; + unsigned int item; + + item = snd_soc_enum_val_to_item(e, cs48l32->eq_mode[e->shift_l]); + ucontrol->value.enumerated.item[0] = item; + + return 0; +} + +int cs48l32_eq_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; + unsigned int *item = ucontrol->value.enumerated.item; + unsigned int val; + bool changed = false; + + if (item[0] >= e->items) + return -EINVAL; + + val = snd_soc_enum_item_to_val(e, item[0]); + + snd_soc_dapm_mutex_lock(dapm); + if (cs48l32->eq_mode[e->shift_l] != val) { + cs48l32->eq_mode[e->shift_l] = val; + changed = true; + } + snd_soc_dapm_mutex_unlock(dapm); + + return changed; +} + +int cs48l32_eq_coeff_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + struct cs48l32_eq_control *ctl = (void *) kcontrol->private_value; + + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = ctl->max; + + return 0; +} + +int cs48l32_eq_coeff_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_eq_control *params = (void *)kcontrol->private_value; + __be16 *coeffs; + unsigned int coeff_idx; + int block_idx; + + block_idx = ((int) params->block_base - (int) CS48L32_EQ1_BAND1_COEFF1); + block_idx /= 68; + + coeffs = &cs48l32->eq_coefficients[block_idx][0]; + + coeff_idx = (params->reg - params->block_base) / 2; + coeff_idx += ((params->shift == 0) ? 1 : 0); + + ucontrol->value.integer.value[0] = be16_to_cpu(coeffs[coeff_idx]); + + return 0; +} + +int cs48l32_eq_coeff_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_eq_control *params = (void *)kcontrol->private_value; + __be16 *coeffs; + unsigned int coeff_idx; + int block_idx; + + block_idx = ((int) params->block_base - (int) CS48L32_EQ1_BAND1_COEFF1); + block_idx /= 68; + + coeffs = &cs48l32->eq_coefficients[block_idx][0]; + + coeff_idx = (params->reg - params->block_base) / 2; + coeff_idx += ((params->shift == 0) ? 1 : 0); + + snd_soc_dapm_mutex_lock(dapm); + coeffs[coeff_idx] = cpu_to_be16(ucontrol->value.integer.value[0]); + snd_soc_dapm_mutex_unlock(dapm); + + return 0; +} + +const struct snd_kcontrol_new cs48l32_drc_activity_output_mux[] = { + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), +}; + +const struct snd_kcontrol_new cs48l32_dsp_trigger_output_mux[] = { + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), +}; + +int cs48l32_dsp_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; + unsigned int cached_rate; + const unsigned int rate_num = e->mask; + int item; + + if (rate_num >= ARRAY_SIZE(cs48l32->dsp_dma_rates)) + return -EINVAL; + + cached_rate = cs48l32->dsp_dma_rates[rate_num]; + item = snd_soc_enum_val_to_item(e, cached_rate); + ucontrol->value.enumerated.item[0] = item; + + return 0; +} + +int cs48l32_dsp_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; + const unsigned int rate_num = e->mask; + const unsigned int item = ucontrol->value.enumerated.item[0]; + unsigned int val; + bool changed = false; + + if (item >= e->items) + return -EINVAL; + + if (rate_num >= ARRAY_SIZE(cs48l32->dsp_dma_rates)) + return -EINVAL; + + val = snd_soc_enum_item_to_val(e, item); + + snd_soc_dapm_mutex_lock(dapm); + if (cs48l32->dsp_dma_rates[rate_num] != val) { + cs48l32->dsp_dma_rates[rate_num] = val; + changed = true; + } + snd_soc_dapm_mutex_unlock(dapm); + + return changed; +} + +const struct soc_enum cs48l32_dsp_rate_enum[] = { + /* RX rates */ + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 0, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 1, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 2, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 3, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 4, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 5, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 6, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 7, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + /* TX rates */ + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 8, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 9, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 10, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 11, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 12, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 13, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 14, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 15, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), +}; + +int cs48l32_dsp_pre_run(struct wm_adsp *dsp) +{ + struct cs48l32 *cs48l32 = container_of(dsp, struct cs48l32, dsp); + unsigned int reg; + const u8 *rate = cs48l32->dsp_dma_rates; + int i; + + reg = dsp->cs_dsp.base + CS48L32_HALO_SAMPLE_RATE_RX1; + for (i = 0; i < CS48L32_DSP_N_RX_CHANNELS; ++i) { + regmap_update_bits(dsp->cs_dsp.regmap, reg, CS48L32_HALO_DSP_RATE_MASK, *rate); + reg += 8; + rate++; + } + + reg = dsp->cs_dsp.base + CS48L32_HALO_SAMPLE_RATE_TX1; + for (i = 0; i < CS48L32_DSP_N_TX_CHANNELS; ++i) { + regmap_update_bits(dsp->cs_dsp.regmap, reg, CS48L32_HALO_DSP_RATE_MASK, *rate); + reg += 8; + rate++; + } + + usleep_range(300, 600); + + return 0; +} + +int cs48l32_dsp_memory_enable(struct cs48l32 *cs48l32, + const struct cs48l32_dsp_power_regs *regs) +{ + struct regmap *regmap = cs48l32->mfd->regmap; + int i, j, ret; + + /* disable power-off */ + for (i = 0; i < regs->n_ext; ++i) { + for (j = regs->ext[i].start; j <= regs->ext[i].end; j += 4) { + ret = regmap_write(regmap, j, 0x3); + if (ret) + goto err; + } + } + + /* power-up the banks in sequence */ + for (i = 0; i < regs->n_pwd; ++i) { + ret = regmap_write(regmap, regs->pwd[i], 0x1); + if (ret) + goto err; + + udelay(1); /* allow bank to power-up */ + + ret = regmap_write(regmap, regs->pwd[i], 0x3); + if (ret) + goto err; + + udelay(1); /* allow bank to power-up */ + } + + return 0; + +err: + dev_err(cs48l32->dev, "Failed to write SRAM enables (%d)\n", ret); + cs48l32_dsp_memory_disable(cs48l32, regs); + + return ret; +} + +void cs48l32_dsp_memory_disable(struct cs48l32 *cs48l32, + const struct cs48l32_dsp_power_regs *regs) +{ + struct regmap *regmap = cs48l32->mfd->regmap; + int i, j, ret; + + for (i = 0; i < regs->n_pwd; ++i) { + ret = regmap_write(regmap, regs->pwd[i], 0); + if (ret) + dev_warn(cs48l32->dev, "Failed to write SRAM enables (%d)\n", ret); + } + + for (i = 0; i < regs->n_ext; ++i) { + for (j = regs->ext[i].start; j <= regs->ext[i].end; j += 4) { + ret = regmap_write(regmap, j, 0); + if (ret) + dev_warn(cs48l32->dev, "Failed to write SRAM enables (%d)\n", ret); + } + } +} + +static int cs48l32_dsp_freq_update(struct snd_soc_dapm_widget *w, unsigned int freq_reg, + unsigned int freqsel_reg) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_mfd *mfd = cs48l32->mfd; + struct wm_adsp *dsp = &cs48l32->dsp; + int ret; + unsigned int freq, freq_sel, freq_sts; + + if (!freq_reg) + return -EINVAL; + + ret = regmap_read(mfd->regmap, freq_reg, &freq); + if (ret) { + dev_err(component->dev, "Failed to read 0x%x: %d\n", freq_reg, ret); + return ret; + } + + if (freqsel_reg) { + freq_sts = (freq & CS48L32_SYSCLK_FREQ_STS_MASK) >> CS48L32_SYSCLK_FREQ_STS_SHIFT; + + ret = regmap_read(mfd->regmap, freqsel_reg, &freq_sel); + if (ret) { + dev_err(component->dev, "Failed to read 0x%x: %d\n", freqsel_reg, ret); + return ret; + } + freq_sel = (freq_sel & CS48L32_SYSCLK_FREQ_MASK) >> CS48L32_SYSCLK_FREQ_SHIFT; + + if (freq_sts != freq_sel) { + dev_err(component->dev, "SYSCLK FREQ (0x%x) != FREQ STS (0x%x)\n", + freq_sel, freq_sts); + return -ETIMEDOUT; + } + } + + freq &= CS48L32_DSP_CLK_FREQ_MASK; + freq >>= CS48L32_DSP_CLK_FREQ_SHIFT; + + ret = regmap_write(dsp->cs_dsp.regmap, + dsp->cs_dsp.base + CS48L32_DSP_CLOCK_FREQ_OFFS, freq); + if (ret) { + dev_err(component->dev, "Failed to set HALO clock freq: %d\n", ret); + return ret; + } + + return 0; +} + +int cs48l32_dsp_freq_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + switch (event) { + case SND_SOC_DAPM_POST_PMU: + return cs48l32_dsp_freq_update(w, CS48L32_SYSTEM_CLOCK2, CS48L32_SYSTEM_CLOCK1); + default: + return 0; + } +} + +irqreturn_t cs48l32_dsp1_irq(int irq, void *data) +{ + struct cs48l32 *cs48l32 = data; + int ret; + + ret = wm_adsp_compr_handle_irq(&cs48l32->dsp); + if (ret == -ENODEV) { + dev_err(cs48l32->dev, "Spurious compressed data IRQ\n"); + return IRQ_NONE; + } + + return IRQ_HANDLED; +} + +static const unsigned int cs48l32_opclk_ref_48k_rates[] = { + 6144000, + 12288000, + 24576000, + 49152000, +}; + +static const unsigned int cs48l32_opclk_ref_44k1_rates[] = { + 5644800, + 11289600, + 22579200, + 45158400, +}; + +static int cs48l32_set_opclk(struct snd_soc_component *component, unsigned int clk, + unsigned int freq) +{ + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + unsigned int reg; + const unsigned int *rates; + int ref, div, refclk; + + BUILD_BUG_ON(ARRAY_SIZE(cs48l32_opclk_ref_48k_rates) != + ARRAY_SIZE(cs48l32_opclk_ref_44k1_rates)); + + switch (clk) { + case CS48L32_CLK_OPCLK: + reg = CS48L32_OUTPUT_SYS_CLK; + refclk = cs48l32->sysclk; + break; + default: + return -EINVAL; + } + + if (refclk % 4000) + rates = cs48l32_opclk_ref_44k1_rates; + else + rates = cs48l32_opclk_ref_48k_rates; + + for (ref = 0; ref < ARRAY_SIZE(cs48l32_opclk_ref_48k_rates); ++ref) { + if (rates[ref] > refclk) + continue; + + div = 2; + while ((rates[ref] / div >= freq) && (div <= 30)) { + if (rates[ref] / div == freq) { + dev_dbg(component->dev, "Configured %dHz OPCLK\n", freq); + snd_soc_component_update_bits(component, reg, + CS48L32_OPCLK_DIV_MASK | + CS48L32_OPCLK_SEL_MASK, + (div << CS48L32_OPCLK_DIV_SHIFT) | + ref); + return 0; + } + div += 2; + } + } + + dev_err(component->dev, "Unable to generate %dHz OPCLK\n", freq); + return -EINVAL; +} + +static int cs48l32_get_dspclk_setting(struct cs48l32 *cs48l32, unsigned int freq, + int src, unsigned int *val) +{ + freq /= 15625; /* convert to 1/64ths of 1MHz */ + *val |= freq << CS48L32_DSP_CLK_FREQ_SHIFT; + + return 0; +} + +static int cs48l32_get_sysclk_setting(unsigned int freq) +{ + switch (freq) { + case 0: + case 5644800: + case 6144000: + return CS48L32_SYSCLK_RATE_6MHZ; + case 11289600: + case 12288000: + return CS48L32_SYSCLK_RATE_12MHZ << CS48L32_SYSCLK_FREQ_SHIFT; + case 22579200: + case 24576000: + return CS48L32_SYSCLK_RATE_24MHZ << CS48L32_SYSCLK_FREQ_SHIFT; + case 45158400: + case 49152000: + return CS48L32_SYSCLK_RATE_49MHZ << CS48L32_SYSCLK_FREQ_SHIFT; + case 90316800: + case 98304000: + return CS48L32_SYSCLK_RATE_98MHZ << CS48L32_SYSCLK_FREQ_SHIFT; + default: + return -EINVAL; + } +} + +static int cs48l32_set_pdm_fllclk(struct snd_soc_component *component, int source) +{ + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_mfd *mfd = cs48l32->mfd; + unsigned int val; + + switch (source) { + case CS48L32_PDMCLK_SRC_IN1_PDMCLK: + case CS48L32_PDMCLK_SRC_IN2_PDMCLK: + case CS48L32_PDMCLK_SRC_IN3_PDMCLK: + case CS48L32_PDMCLK_SRC_IN4_PDMCLK: + case CS48L32_PDMCLK_SRC_AUXPDM1_CLK: + case CS48L32_PDMCLK_SRC_AUXPDM2_CLK: + val = source << CS48L32_PDM_FLLCLK_SRC_SHIFT; + break; + default: + dev_err(cs48l32->dev, "Invalid PDM FLLCLK src %d\n", source); + return -EINVAL; + } + + return regmap_update_bits(mfd->regmap, CS48L32_INPUT_CONTROL2, + CS48L32_PDM_FLLCLK_SRC_MASK, val); +} + +int cs48l32_set_sysclk(struct snd_soc_component *component, int clk_id, int source, + unsigned int freq, int dir) +{ + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_mfd *mfd = cs48l32->mfd; + char *name; + unsigned int reg; + unsigned int mask = CS48L32_SYSCLK_SRC_MASK; + unsigned int val = source << CS48L32_SYSCLK_SRC_SHIFT; + int clk_freq_sel, *clk; + + switch (clk_id) { + case CS48L32_CLK_SYSCLK_1: + name = "SYSCLK"; + reg = CS48L32_SYSTEM_CLOCK1; + clk = &cs48l32->sysclk; + clk_freq_sel = cs48l32_get_sysclk_setting(freq); + mask |= CS48L32_SYSCLK_FREQ_MASK | CS48L32_SYSCLK_FRAC_MASK; + break; + case CS48L32_CLK_DSPCLK: + name = "DSPCLK"; + reg = CS48L32_DSP_CLOCK1; + clk = &cs48l32->dspclk; + clk_freq_sel = cs48l32_get_dspclk_setting(cs48l32, freq, source, &val); + mask |= CS48L32_DSP_CLK_FREQ_MASK; + break; + case CS48L32_CLK_OPCLK: + return cs48l32_set_opclk(component, clk_id, freq); + case CS48L32_CLK_PDM_FLLCLK: + return cs48l32_set_pdm_fllclk(component, source); + default: + return -EINVAL; + } + + if (clk_freq_sel < 0) { + dev_err(cs48l32->dev, "Failed to get %s setting for %dHZ\n", name, freq); + return clk_freq_sel; + } + + *clk = freq; + + if (freq == 0) { + dev_dbg(cs48l32->dev, "%s cleared\n", name); + return 0; + } + + val |= clk_freq_sel; + + if (freq % 6144000) + val |= CS48L32_SYSCLK_FRAC_MASK; + + dev_dbg(cs48l32->dev, "%s set to %uHz", name, freq); + + return regmap_update_bits(mfd->regmap, reg, mask, val); +} + +static int cs48l32_is_enabled_fll(struct cs48l32_fll *fll, int base) +{ + struct cs48l32_mfd *mfd = fll->cs48l32->mfd; + unsigned int reg; + int ret; + + ret = regmap_read(mfd->regmap, base + CS48L32_FLL_CONTROL1_OFFS, ®); + if (ret != 0) { + cs48l32_fll_err(fll, "Failed to read current state: %d\n", ret); + return ret; + } + + return reg & CS48L32_FLL_EN_MASK; +} + +static int cs48l32_wait_for_fll(struct cs48l32_fll *fll, bool requested) +{ + struct cs48l32_mfd *mfd = fll->cs48l32->mfd; + unsigned int val = 0; + int i; + + cs48l32_fll_dbg(fll, "Waiting for FLL...\n"); + + for (i = 0; i < 30; i++) { + regmap_read(mfd->regmap, fll->sts_addr, &val); + if (!!(val & fll->sts_mask) == requested) + return 0; + + switch (i) { + case 0 ... 5: + usleep_range(75, 125); + break; + case 11 ... 20: + usleep_range(750, 1250); + break; + default: + msleep(20); + break; + } + } + + cs48l32_fll_warn(fll, "Timed out waiting for %s\n", requested ? "lock" : "unlock"); + + return -ETIMEDOUT; +} + +static int cs48l32_fllhj_disable(struct cs48l32_fll *fll) +{ + struct cs48l32_mfd *mfd = fll->cs48l32->mfd; + bool change; + + cs48l32_fll_dbg(fll, "Disabling FLL\n"); + + /* + * Disable lockdet, but don't set ctrl_upd update bit. This allows the + * lock status bit to clear as normal, but should the FLL be enabled + * again due to a control clock being required, the lock won't re-assert + * as the FLL config registers are automatically applied when the FLL + * enables. + */ + regmap_set_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL1_OFFS, + CS48L32_FLL_HOLD_MASK); + regmap_clear_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL2_OFFS, + CS48L32_FLL_LOCKDET_MASK); + regmap_set_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL5_OFFS, + CS48L32_FLL_FRC_INTEG_UPD_MASK); + regmap_update_bits_check(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL1_OFFS, + CS48L32_FLL_EN_MASK, + 0, + &change); + + cs48l32_wait_for_fll(fll, false); + + /* + * ctrl_up gates the writes to all the fll's registers, setting it to 0 + * here ensures that after a runtime suspend/resume cycle when one + * enables the fll then ctrl_up is the last bit that is configured + * by the fll enable code rather than the cache sync operation which + * would have updated it much earlier before writing out all fll + * registers + */ + regmap_clear_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL1_OFFS, + CS48L32_FLL_CTRL_UPD_MASK); + + if (change) + pm_runtime_put_autosuspend(mfd->dev); + + return 0; +} + +static int cs48l32_fllhj_apply(struct cs48l32_fll *fll, int fin) +{ + struct cs48l32_mfd *mfd = fll->cs48l32->mfd; + int refdiv, fref, fout, lockdet_thr, fbdiv, fllgcd; + bool frac = false; + unsigned int fll_n, min_n, max_n, ratio, theta, lambda, hp; + unsigned int gains, num; + + cs48l32_fll_dbg(fll, "fin=%d, fout=%d\n", fin, fll->fout); + + for (refdiv = 0; refdiv < 4; refdiv++) { + if ((fin / (1 << refdiv)) <= CS48L32_FLLHJ_MAX_THRESH) + break; + } + + fref = fin / (1 << refdiv); + fout = fll->fout; + frac = fout % fref; + + if (frac && fll->integer_only) { + cs48l32_fll_err(fll, "%u:%u not an integer ratio\n", fin, fout); + return -EINVAL; + } + + if (fll->max_fref && (fref > fll->max_fref)) { + cs48l32_fll_err(fll, "fref=%u too high (max %u)\n", + fref, fll->max_fref); + return -EINVAL; + } + + /* + * Use simple heuristic approach to find a configuration that + * should work for most input clocks. + */ + if (fref < CS48L32_FLLHJ_LOW_THRESH) { + lockdet_thr = 2; + gains = CS48L32_FLLHJ_LOW_GAINS; + + if (frac) + fbdiv = 256; + else + fbdiv = 4; + } else if (fref < CS48L32_FLLHJ_MID_THRESH) { + lockdet_thr = 8; + gains = CS48L32_FLLHJ_MID_GAINS; + fbdiv = (frac) ? 16 : 2; + } else { + lockdet_thr = 8; + gains = CS48L32_FLLHJ_HIGH_GAINS; + fbdiv = 1; + } + /* Use high performance mode for fractional configurations. */ + if (frac) { + hp = 0x3; + min_n = CS48L32_FLLHJ_FRAC_MIN_N; + max_n = CS48L32_FLLHJ_FRAC_MAX_N; + } else { + if (fll->has_lp && (fref < CS48L32_FLLHJ_LP_INT_MODE_THRESH)) + hp = 0x0; + else + hp = 0x1; + + min_n = CS48L32_FLLHJ_INT_MIN_N; + max_n = CS48L32_FLLHJ_INT_MAX_N; + } + + ratio = fout / fref; + + cs48l32_fll_dbg(fll, "refdiv=%d, fref=%d, frac:%d\n", refdiv, fref, frac); + + while (ratio / fbdiv < min_n) { + fbdiv /= 2; + if (fbdiv < min_n) { + cs48l32_fll_err(fll, "FBDIV (%u) < minimum N (%u)\n", fbdiv, min_n); + return -EINVAL; + } + } + while (frac && (ratio / fbdiv > max_n)) { + fbdiv *= 2; + if (fbdiv >= 1024) { + cs48l32_fll_err(fll, "FBDIV (%u) >= 1024\n", fbdiv); + return -EINVAL; + } + } + + cs48l32_fll_dbg(fll, "lockdet=%d, hp=0x%x, fbdiv:%d\n", lockdet_thr, hp, fbdiv); + + /* Calculate N.K values */ + fllgcd = gcd(fout, fbdiv * fref); + num = fout / fllgcd; + lambda = (fref * fbdiv) / fllgcd; + fll_n = num / lambda; + theta = num % lambda; + + cs48l32_fll_dbg(fll, "fll_n=%d, gcd=%d, theta=%d, lambda=%d\n", + fll_n, fllgcd, theta, lambda); + + /* Some sanity checks before any registers are written. */ + if (fll_n < min_n || fll_n > max_n) { + cs48l32_fll_err(fll, "N not in valid %s mode range %d-%d: %d\n", + frac ? "fractional" : "integer", min_n, max_n, fll_n); + return -EINVAL; + } + if (fbdiv < 1 || (frac && fbdiv >= 1024) || (!frac && fbdiv >= 256)) { + cs48l32_fll_err(fll, "Invalid fbdiv for %s mode (%u)\n", + frac ? "fractional" : "integer", fbdiv); + return -EINVAL; + } + + /* clear the ctrl_upd bit to guarantee we write to it later. */ + regmap_update_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL2_OFFS, + CS48L32_FLL_LOCKDET_THR_MASK | + CS48L32_FLL_PHASEDET_MASK | + CS48L32_FLL_REFCLK_DIV_MASK | + CS48L32_FLL_N_MASK | + CS48L32_FLL_CTRL_UPD_MASK, + (lockdet_thr << CS48L32_FLL_LOCKDET_THR_SHIFT) | + (1 << CS48L32_FLL_PHASEDET_SHIFT) | + (refdiv << CS48L32_FLL_REFCLK_DIV_SHIFT) | + (fll_n << CS48L32_FLL_N_SHIFT)); + + regmap_update_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL3_OFFS, + CS48L32_FLL_LAMBDA_MASK | + CS48L32_FLL_THETA_MASK, + (lambda << CS48L32_FLL_LAMBDA_SHIFT) | + (theta << CS48L32_FLL_THETA_SHIFT)); + + regmap_update_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL4_OFFS, + (0xffff << CS48L32_FLL_FD_GAIN_COARSE_SHIFT) | + CS48L32_FLL_HP_MASK | + CS48L32_FLL_FB_DIV_MASK, + (gains << CS48L32_FLL_FD_GAIN_COARSE_SHIFT) | + (hp << CS48L32_FLL_HP_SHIFT) | + (fbdiv << CS48L32_FLL_FB_DIV_SHIFT)); + + return 0; +} + +static int cs48l32_fllhj_enable(struct cs48l32_fll *fll) +{ + struct cs48l32_mfd *mfd = fll->cs48l32->mfd; + int already_enabled = cs48l32_is_enabled_fll(fll, fll->base); + int ret; + + if (already_enabled < 0) + return already_enabled; + + if (!already_enabled) + pm_runtime_get_sync(mfd->dev); + + cs48l32_fll_dbg(fll, "Enabling FLL, initially %s\n", + already_enabled ? "enabled" : "disabled"); + + /* FLLn_HOLD must be set before configuring any registers */ + regmap_set_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL1_OFFS, + CS48L32_FLL_HOLD_MASK); + + /* Apply refclk */ + ret = cs48l32_fllhj_apply(fll, fll->ref_freq); + if (ret) { + cs48l32_fll_err(fll, "Failed to set FLL: %d\n", ret); + goto out; + } + regmap_update_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL2_OFFS, + CS48L32_FLL_REFCLK_SRC_MASK, + fll->ref_src << CS48L32_FLL_REFCLK_SRC_SHIFT); + + regmap_set_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL1_OFFS, + CS48L32_FLL_EN_MASK); + +out: + regmap_set_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL2_OFFS, + CS48L32_FLL_LOCKDET_MASK); + + regmap_set_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL1_OFFS, + CS48L32_FLL_CTRL_UPD_MASK); + + /* Release the hold so that flln locks to external frequency */ + regmap_clear_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL1_OFFS, + CS48L32_FLL_HOLD_MASK); + + if (!already_enabled) + cs48l32_wait_for_fll(fll, true); + + return 0; +} + +static int cs48l32_fllhj_validate(struct cs48l32_fll *fll, + unsigned int ref_in, + unsigned int fout) +{ + if (fout && !ref_in) { + cs48l32_fll_err(fll, "fllout set without valid input clk\n"); + return -EINVAL; + } + + if (fll->fout && fout != fll->fout) { + cs48l32_fll_err(fll, "Can't change output on active FLL\n"); + return -EINVAL; + } + + if (ref_in / CS48L32_FLL_MAX_REFDIV > CS48L32_FLLHJ_MAX_THRESH) { + cs48l32_fll_err(fll, "Can't scale %dMHz to <=13MHz\n", ref_in); + return -EINVAL; + } + + if (fout > CS48L32_FLL_MAX_FOUT) { + cs48l32_fll_err(fll, "Fout=%dMHz exceeeds maximum %dMHz\n", + fout, CS48L32_FLL_MAX_FOUT); + return -EINVAL; + } + + return 0; +} + +int cs48l32_fllhj_set_refclk(struct cs48l32_fll *fll, int source, + unsigned int fin, unsigned int fout) +{ + int ret = 0; + + if (fll->ref_src == source && fll->ref_freq == fin && fll->fout == fout) + return 0; + + if (fin && fout && cs48l32_fllhj_validate(fll, fin, fout)) + return -EINVAL; + + fll->ref_src = source; + fll->ref_freq = fin; + fll->fout = fout; + + if (fout) + ret = cs48l32_fllhj_enable(fll); + else + cs48l32_fllhj_disable(fll); + + return ret; +} + +int cs48l32_init_fll(struct cs48l32_fll *fll) +{ + fll->ref_src = CS48L32_FLL_SRC_NONE; + + return 0; +} + +static int cs48l32_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_component *component = dai->component; + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_mfd *mfd = cs48l32->mfd; + unsigned int val = 0U; + unsigned int base = dai->driver->base; + unsigned int mask = CS48L32_ASP_FMT_MASK | CS48L32_ASP_BCLK_INV_MASK | + CS48L32_ASP_BCLK_MSTR_MASK | + CS48L32_ASP_FSYNC_INV_MASK | + CS48L32_ASP_FSYNC_MSTR_MASK; + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_DSP_A: + val |= (CS48L32_ASP_FMT_DSP_MODE_A << CS48L32_ASP_FMT_SHIFT); + break; + case SND_SOC_DAIFMT_DSP_B: + if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_BP_FP) { + cs48l32_asp_err(dai, "DSP_B cannot be clock consumer\n"); + return -EINVAL; + } + val |= (CS48L32_ASP_FMT_DSP_MODE_B << CS48L32_ASP_FMT_SHIFT); + break; + case SND_SOC_DAIFMT_I2S: + val |= (CS48L32_ASP_FMT_I2S_MODE << CS48L32_ASP_FMT_SHIFT); + break; + case SND_SOC_DAIFMT_LEFT_J: + if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_BP_FP) { + cs48l32_asp_err(dai, "LEFT_J cannot be clock consumer\n"); + return -EINVAL; + } + val |= (CS48L32_ASP_FMT_LEFT_JUSTIFIED_MODE << CS48L32_ASP_FMT_SHIFT); + break; + default: + cs48l32_asp_err(dai, "Unsupported DAI format %d\n", + fmt & SND_SOC_DAIFMT_FORMAT_MASK); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { + case SND_SOC_DAIFMT_BC_FC: + break; + case SND_SOC_DAIFMT_BC_FP: + val |= CS48L32_ASP_FSYNC_MSTR_MASK; + break; + case SND_SOC_DAIFMT_BP_FC: + val |= CS48L32_ASP_BCLK_MSTR_MASK; + break; + case SND_SOC_DAIFMT_BP_FP: + val |= CS48L32_ASP_BCLK_MSTR_MASK; + val |= CS48L32_ASP_FSYNC_MSTR_MASK; + break; + default: + cs48l32_asp_err(dai, "Unsupported clock direction %d\n", + fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_IF: + val |= CS48L32_ASP_BCLK_INV_MASK; + val |= CS48L32_ASP_FSYNC_INV_MASK; + break; + case SND_SOC_DAIFMT_IB_NF: + val |= CS48L32_ASP_BCLK_INV_MASK; + break; + case SND_SOC_DAIFMT_NB_IF: + val |= CS48L32_ASP_FSYNC_INV_MASK; + break; + default: + return -EINVAL; + } + + regmap_update_bits(mfd->regmap, base + CS48L32_ASP_CONTROL2, mask, val); + + return 0; +} + +static const struct { + u32 freq; + u32 id; +} cs48l32_sclk_rates[] = { + { 128000, 12 }, + { 176400, 13 }, + { 192000, 14 }, + { 256000, 15 }, + { 352800, 16 }, + { 384000, 17 }, + { 512000, 18 }, + { 705600, 19 }, + { 768000, 21 }, + { 1024000, 23 }, + { 1411200, 25 }, + { 1536000, 27 }, + { 2048000, 29 }, + { 2822400, 31 }, + { 3072000, 33 }, + { 4096000, 36 }, + { 5644800, 38 }, + { 6144000, 40 }, + { 8192000, 47 }, + { 11289600, 49 }, + { 12288000, 51 }, + { 22579200, 57 }, + { 24576000, 59 }, +}; + +#define CS48L32_48K_RATE_MASK 0x0e00fe +#define CS48L32_44K1_RATE_MASK 0x00fe00 +#define CS48L32_RATE_MASK (CS48L32_48K_RATE_MASK | CS48L32_44K1_RATE_MASK) + +static const unsigned int cs48l32_sr_vals[] = { + 0, + 12000, /* CS48L32_48K_RATE_MASK */ + 24000, /* CS48L32_48K_RATE_MASK */ + 48000, /* CS48L32_48K_RATE_MASK */ + 96000, /* CS48L32_48K_RATE_MASK */ + 192000, /* CS48L32_48K_RATE_MASK */ + 384000, /* CS48L32_48K_RATE_MASK */ + 768000, /* CS48L32_48K_RATE_MASK */ + 0, + 11025, /* CS48L32_44K1_RATE_MASK */ + 22050, /* CS48L32_44K1_RATE_MASK */ + 44100, /* CS48L32_44K1_RATE_MASK */ + 88200, /* CS48L32_44K1_RATE_MASK */ + 176400, /* CS48L32_44K1_RATE_MASK */ + 352800, /* CS48L32_44K1_RATE_MASK */ + 705600, /* CS48L32_44K1_RATE_MASK */ + 0, + 8000, /* CS48L32_48K_RATE_MASK */ + 16000, /* CS48L32_48K_RATE_MASK */ + 32000, /* CS48L32_48K_RATE_MASK */ +}; + +static const struct snd_pcm_hw_constraint_list cs48l32_constraint = { + .count = ARRAY_SIZE(cs48l32_sr_vals), + .list = cs48l32_sr_vals, +}; + +static int cs48l32_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_dai_priv *dai_priv = &cs48l32->dai[dai->id - 1]; + unsigned int base_rate; + + if (!substream->runtime) + return 0; + + switch (dai_priv->clk) { + case CS48L32_CLK_SYSCLK_1: + case CS48L32_CLK_SYSCLK_2: + case CS48L32_CLK_SYSCLK_3: + case CS48L32_CLK_SYSCLK_4: + base_rate = cs48l32->sysclk; + break; + default: + return 0; + } + + if (base_rate == 0) + dai_priv->constraint.mask = CS48L32_RATE_MASK; + else if (base_rate % 4000) + dai_priv->constraint.mask = CS48L32_44K1_RATE_MASK; + else + dai_priv->constraint.mask = CS48L32_48K_RATE_MASK; + + return snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + &dai_priv->constraint); +} + +static int cs48l32_hw_params_rate(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_dai_priv *dai_priv = &cs48l32->dai[dai->id - 1]; + unsigned int sr_val, sr_reg, rate; + + rate = params_rate(params); + for (sr_val = 0; sr_val < ARRAY_SIZE(cs48l32_sr_vals); sr_val++) + if (cs48l32_sr_vals[sr_val] == rate) + break; + + if (sr_val == ARRAY_SIZE(cs48l32_sr_vals)) { + cs48l32_asp_err(dai, "Unsupported sample rate %dHz\n", rate); + return -EINVAL; + } + + switch (dai_priv->clk) { + case CS48L32_CLK_SYSCLK_1: + sr_reg = CS48L32_SAMPLE_RATE1; + break; + case CS48L32_CLK_SYSCLK_2: + sr_reg = CS48L32_SAMPLE_RATE2; + break; + case CS48L32_CLK_SYSCLK_3: + sr_reg = CS48L32_SAMPLE_RATE3; + break; + case CS48L32_CLK_SYSCLK_4: + sr_reg = CS48L32_SAMPLE_RATE3; + break; + default: + return -EINVAL; + } + + snd_soc_component_update_bits(component, sr_reg, CS48L32_SAMPLE_RATE_1_MASK, sr_val); + + return 0; +} + +static bool cs48l32_asp_cfg_changed(struct snd_soc_component *component, + unsigned int base, unsigned int sclk, + unsigned int slotws, unsigned int dataw) +{ + unsigned int val; + + val = snd_soc_component_read(component, base + CS48L32_ASP_CONTROL1); + if (sclk != (val & CS48L32_ASP_BCLK_FREQ_MASK)) + return true; + + val = snd_soc_component_read(component, base + CS48L32_ASP_CONTROL2); + if (slotws != (val & (CS48L32_ASP_RX_WIDTH_MASK | CS48L32_ASP_TX_WIDTH_MASK))) + return true; + + val = snd_soc_component_read(component, base + CS48L32_ASP_DATA_CONTROL1); + if (dataw != (val & (CS48L32_ASP_TX_WL_MASK))) + return true; + + val = snd_soc_component_read(component, base + CS48L32_ASP_DATA_CONTROL5); + if (dataw != (val & (CS48L32_ASP_RX_WL_MASK))) + return true; + + return false; +} + +static int cs48l32_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_mfd *mfd = cs48l32->mfd; + int base = dai->driver->base; + int dai_id = dai->id - 1; + unsigned int rate = params_rate(params); + unsigned int dataw = snd_pcm_format_width(params_format(params)); + unsigned int chan_limit = cs48l32->max_channels_clocked[dai_id]; + unsigned int asp_state = 0; + int sclk, sclk_target; + unsigned int slotw, n_slots, n_slots_multiple, val; + int i, ret; + + cs48l32_asp_dbg(dai, "hwparams in: ch:%u dataw:%u rate:%u\n", + params_channels(params), dataw, rate); + /* + * The following calculations hold only under the assumption that + * symmetric_[rates|channels|samplebits] are set to 1 + */ + if (cs48l32->tdm_slots[dai_id]) { + n_slots = cs48l32->tdm_slots[dai_id]; + slotw = cs48l32->tdm_width[dai_id]; + } else { + n_slots = params_channels(params); + slotw = dataw; + } + + if (chan_limit) + n_slots = min(n_slots, chan_limit); + + val = snd_soc_component_read(component, base + CS48L32_ASP_CONTROL2); + val = (val & CS48L32_ASP_FMT_MASK) >> CS48L32_ASP_FMT_SHIFT; + if (val == CS48L32_ASP_FMT_I2S_MODE) + n_slots_multiple = 2; + else + n_slots_multiple = 1; + + sclk_target = snd_soc_tdm_params_to_bclk(params, slotw, n_slots, n_slots_multiple); + + for (i = 0; i < ARRAY_SIZE(cs48l32_sclk_rates); i++) { + if ((cs48l32_sclk_rates[i].freq >= sclk_target) && + (cs48l32_sclk_rates[i].freq % rate == 0)) { + sclk = cs48l32_sclk_rates[i].id; + break; + } + } + if (i == ARRAY_SIZE(cs48l32_sclk_rates)) { + cs48l32_asp_err(dai, "Unsupported sample rate %dHz\n", rate); + return -EINVAL; + } + + cs48l32_asp_dbg(dai, "hwparams out: n_slots:%u dataw:%u slotw:%u bclk:%u bclkid:%u\n", + n_slots, dataw, slotw, sclk_target, sclk); + + slotw = (slotw << CS48L32_ASP_TX_WIDTH_SHIFT) | + (slotw << CS48L32_ASP_RX_WIDTH_SHIFT); + + if (!cs48l32_asp_cfg_changed(component, base, sclk, slotw, dataw)) + return cs48l32_hw_params_rate(substream, params, dai); + + /* ASP must be disabled while changing configuration */ + asp_state = snd_soc_component_read(component, base + CS48L32_ASP_ENABLES1); + regmap_clear_bits(mfd->regmap, base + CS48L32_ASP_ENABLES1, 0xff00ff); + + ret = cs48l32_hw_params_rate(substream, params, dai); + if (ret != 0) + goto restore_asp; + + regmap_update_bits_async(mfd->regmap, + base + CS48L32_ASP_CONTROL1, + CS48L32_ASP_BCLK_FREQ_MASK, + sclk); + regmap_update_bits_async(mfd->regmap, + base + CS48L32_ASP_CONTROL2, + CS48L32_ASP_RX_WIDTH_MASK | CS48L32_ASP_TX_WIDTH_MASK, + slotw); + regmap_update_bits_async(mfd->regmap, + base + CS48L32_ASP_DATA_CONTROL1, + CS48L32_ASP_TX_WL_MASK, + dataw); + regmap_update_bits(mfd->regmap, + base + CS48L32_ASP_DATA_CONTROL5, + CS48L32_ASP_RX_WL_MASK, + dataw); + +restore_asp: + /* Restore ASP TX/RX enable state */ + regmap_update_bits(mfd->regmap, + base + CS48L32_ASP_ENABLES1, + 0xff00ff, + asp_state); + return ret; +} + +static const char * const cs48l32_dai_clk_str(int clk_id) +{ + switch (clk_id) { + case CS48L32_CLK_SYSCLK_1: + case CS48L32_CLK_SYSCLK_2: + case CS48L32_CLK_SYSCLK_3: + case CS48L32_CLK_SYSCLK_4: + return "SYSCLK"; + default: + return "Unknown clock"; + } +} + +static int cs48l32_dai_set_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_component *component = dai->component; + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_dai_priv *dai_priv = &cs48l32->dai[dai->id - 1]; + unsigned int base = dai->driver->base; + unsigned int current_asp_rate, target_asp_rate; + bool change_rate_domain = false; + int ret; + + if (clk_id == dai_priv->clk) + return 0; + + if (snd_soc_dai_active(dai)) { + cs48l32_asp_err(dai, "Can't change clock on active DAI\n"); + return -EBUSY; + } + + switch (clk_id) { + case CS48L32_CLK_SYSCLK_1: + target_asp_rate = 0U << CS48L32_ASP_RATE_SHIFT; + break; + case CS48L32_CLK_SYSCLK_2: + target_asp_rate = 1U << CS48L32_ASP_RATE_SHIFT; + break; + case CS48L32_CLK_SYSCLK_3: + target_asp_rate = 2U << CS48L32_ASP_RATE_SHIFT; + break; + case CS48L32_CLK_SYSCLK_4: + target_asp_rate = 3U << CS48L32_ASP_RATE_SHIFT; + break; + default: + return -EINVAL; + } + + dai_priv->clk = clk_id; + cs48l32_asp_dbg(dai, "Setting to %s\n", cs48l32_dai_clk_str(clk_id)); + + if (base) { + ret = regmap_read(cs48l32->mfd->regmap, + base + CS48L32_ASP_CONTROL1, + ¤t_asp_rate); + if (ret != 0) { + cs48l32_asp_err(dai, "Failed to check rate: %d\n", ret); + return ret; + } + + if ((current_asp_rate & CS48L32_ASP_RATE_MASK) != + (target_asp_rate & CS48L32_ASP_RATE_MASK)) { + change_rate_domain = true; + + mutex_lock(&cs48l32->rate_lock); + /* Guard the rate change with SYSCLK cycles */ + cs48l32_spin_sysclk(cs48l32); + } + + snd_soc_component_update_bits(component, base + CS48L32_ASP_CONTROL1, + CS48L32_ASP_RATE_MASK, target_asp_rate); + + if (change_rate_domain) { + cs48l32_spin_sysclk(cs48l32); + mutex_unlock(&cs48l32->rate_lock); + } + } + + return 0; +} + +static void cs48l32_set_channels_to_mask(struct snd_soc_dai *dai, + unsigned int base, + int channels, unsigned int mask) +{ + struct snd_soc_component *component = dai->component; + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_mfd *mfd = cs48l32->mfd; + int slot, i, j = 0, shift; + unsigned int frame_ctls[2] = {0, 0}; + + for (i = 0; i < channels; ++i) { + slot = ffs(mask) - 1; + if (slot < 0) + return; + + if (i - (j * 4) >= 4) { + ++j; + if (j >= 2) + break; + } + + shift = (8 * (i - j * 4)); + + frame_ctls[j] |= slot << shift; + + mask &= ~(1 << slot); /* ? mask ^= 1 << slot ? */ + } + + regmap_write(mfd->regmap, base, frame_ctls[0]); + regmap_write(mfd->regmap, base + 0x4, frame_ctls[1]); + + if (mask) + cs48l32_asp_warn(dai, "Too many channels in TDM mask\n"); +} + +static int cs48l32_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, + unsigned int rx_mask, int slots, int slot_width) +{ + struct snd_soc_component *component = dai->component; + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + int base = dai->driver->base; + int rx_max_chan = dai->driver->playback.channels_max; + int tx_max_chan = dai->driver->capture.channels_max; + + /* Only support TDM for the physical ASPs */ + if (dai->id > CS48L32_MAX_ASP) + return -EINVAL; + + if (slots == 0) { + tx_mask = (1 << tx_max_chan) - 1; + rx_mask = (1 << rx_max_chan) - 1; + } + + cs48l32_set_channels_to_mask(dai, base + CS48L32_ASP_FRAME_CONTROL1, + tx_max_chan, tx_mask); + cs48l32_set_channels_to_mask(dai, base + CS48L32_ASP_FRAME_CONTROL5, + rx_max_chan, rx_mask); + + cs48l32->tdm_width[dai->id - 1] = slot_width; + cs48l32->tdm_slots[dai->id - 1] = slots; + + return 0; +} + +const struct snd_soc_dai_ops cs48l32_dai_ops = { + .startup = &cs48l32_startup, + .set_fmt = &cs48l32_set_fmt, + .set_tdm_slot = &cs48l32_set_tdm_slot, + .hw_params = &cs48l32_hw_params, + .set_sysclk = &cs48l32_dai_set_sysclk, +}; + +int cs48l32_sysclk_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + + cs48l32_spin_sysclk(cs48l32); + + return 0; +} + +int cs48l32_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + unsigned int reg; + + if (w->shift % 2) + reg = CS48L32_IN1L_CONTROL2 + ((w->shift / 2) * 0x40); + else + reg = CS48L32_IN1R_CONTROL2 + ((w->shift / 2) * 0x40); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + switch (w->shift) { + case CS48L32_IN1L_EN_SHIFT: + snd_soc_component_update_bits(component, + CS48L32_ADC1L_ANA_CONTROL1, + CS48L32_ADC1x_INT_ENA_FRC_MASK, + CS48L32_ADC1x_INT_ENA_FRC_MASK); + break; + case CS48L32_IN1R_EN_SHIFT: + snd_soc_component_update_bits(component, + CS48L32_ADC1R_ANA_CONTROL1, + CS48L32_ADC1x_INT_ENA_FRC_MASK, + CS48L32_ADC1x_INT_ENA_FRC_MASK); + break; + default: + break; + } + cs48l32->in_up_pending++; + break; + case SND_SOC_DAPM_POST_PMU: + usleep_range(200, 300); + + switch (w->shift) { + case CS48L32_IN1L_EN_SHIFT: + snd_soc_component_update_bits(component, + CS48L32_ADC1L_ANA_CONTROL1, + CS48L32_ADC1x_INT_ENA_FRC_MASK, + 0); + break; + case CS48L32_IN1R_EN_SHIFT: + snd_soc_component_update_bits(component, + CS48L32_ADC1R_ANA_CONTROL1, + CS48L32_ADC1x_INT_ENA_FRC_MASK, + 0); + break; + + default: + break; + } + cs48l32->in_up_pending--; + snd_soc_component_update_bits(component, reg, CS48L32_INx_MUTE_MASK, 0); + + /* Uncached write-only register, no need for update_bits */ + if (!cs48l32->in_up_pending) + snd_soc_component_write(component, cs48l32->in_vu_reg, CS48L32_IN_VU_MASK); + break; + case SND_SOC_DAPM_PRE_PMD: + snd_soc_component_update_bits(component, reg, + CS48L32_INx_MUTE_MASK, CS48L32_INx_MUTE_MASK); + snd_soc_component_write(component, cs48l32->in_vu_reg, CS48L32_IN_VU_MASK); + break; + default: + break; + } + + return 0; +} + +int cs48l32_in_put_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + int ret; + + ret = snd_soc_put_volsw(kcontrol, ucontrol); + if (ret < 0) + return ret; + + /* + * Uncached write-only register, no need for update_bits. + * Will fail if codec is off but that will be handled by cs48l32_in_ev + */ + snd_soc_component_write(component, cs48l32->in_vu_reg, CS48L32_IN_VU); + + return ret; +} + +static bool cs48l32_eq_filter_unstable(bool mode, __be16 in_a, __be16 in_b) +{ + s16 a = be16_to_cpu(in_a); + s16 b = be16_to_cpu(in_b); + + if (!mode) + return abs(a) >= 4096; + + if (abs(b) >= 4096) + return true; + + return (abs((a << 16) / (4096 - b)) >= 4096 << 4); +} + +int cs48l32_eq_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_mfd *mfd = cs48l32->mfd; + unsigned int mode = cs48l32->eq_mode[w->shift]; + unsigned int reg = CS48L32_EQ1_BAND1_COEFF1 + (68 * w->shift); + __be16 *data = &cs48l32->eq_coefficients[w->shift][0]; + int ret = 0; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (cs48l32_eq_filter_unstable(!!mode, data[1], data[0]) || + cs48l32_eq_filter_unstable(true, data[7], data[6]) || + cs48l32_eq_filter_unstable(true, data[13], data[12]) || + cs48l32_eq_filter_unstable(true, data[19], data[18]) || + cs48l32_eq_filter_unstable(false, data[25], data[24])) { + dev_err(cs48l32->dev, "Rejecting unstable EQ coefficients.\n"); + ret = -EINVAL; + } else { + ret = regmap_raw_write(mfd->regmap, reg, data, + CS48L32_EQ_BLOCK_SZ); + if (ret < 0) { + dev_err(cs48l32->dev, "Error writing EQ coefficients: %d\n", ret); + goto out; + } + + ret = snd_soc_component_update_bits(component, + CS48L32_EQ_CONTROL2, + w->mask, + mode << w->shift); + if (ret < 0) + dev_err(cs48l32->dev, "Error writing EQ mode: %d\n", ret); + } + break; + default: + break; + } + +out: + return ret; +} + +static int cs48l32_get_variable_u32_array(struct cs48l32 *cs48l32, + const char *propname, + u32 *dest, + int n_max, + int multiple) +{ + struct cs48l32_mfd *mfd = cs48l32->mfd; + int n, ret; + + n = device_property_read_u32_array(mfd->dev, propname, NULL, 0); + if (n == -EINVAL) { + return 0; /* missing, ignore */ + } else if (n < 0) { + dev_warn(cs48l32->dev, "%s malformed (%d)\n", propname, n); + return -EINVAL; + } else if ((n % multiple) != 0) { + dev_warn(cs48l32->dev, "%s not a multiple of %d entries\n", propname, multiple); + return -EINVAL; + } + + if (n > n_max) + n = n_max; + + ret = device_property_read_u32_array(mfd->dev, propname, dest, n); + + if (ret < 0) + return ret; + else + return n; +} + +static void cs48l32_prop_get_in_type(struct cs48l32 *cs48l32) +{ + u32 tmp[CS48L32_MAX_INPUT * CS48L32_MAX_MUXED_IN_CHANNELS]; + int n, i, in_idx, ch_idx; + + BUILD_BUG_ON(ARRAY_SIZE(cs48l32->in_type) != CS48L32_MAX_INPUT); + BUILD_BUG_ON(ARRAY_SIZE(cs48l32->in_type[0]) != + CS48L32_MAX_MUXED_IN_CHANNELS); + + n = cs48l32_get_variable_u32_array(cs48l32, + "cirrus,in-type", + tmp, + ARRAY_SIZE(tmp), + CS48L32_MAX_MUXED_IN_CHANNELS); + if (n < 0) + return; + + in_idx = 0; + ch_idx = 0; + for (i = 0; i < n; ++i) { + cs48l32->in_type[in_idx][ch_idx] = tmp[i]; + + if (++ch_idx == CS48L32_MAX_MUXED_IN_CHANNELS) { + ch_idx = 0; + ++in_idx; + } + } +} + +static void cs48l32_prop_get(struct cs48l32 *cs48l32) +{ + int ret; + + ret = cs48l32_get_variable_u32_array(cs48l32, + "cirrus,max-channels-clocked", + cs48l32->max_channels_clocked, + ARRAY_SIZE(cs48l32->max_channels_clocked), + 1); + if (ret < 0) + return; + + cs48l32_prop_get_in_type(cs48l32); + + cs48l32_get_variable_u32_array(cs48l32, + "cirrus,pdm-sup", + cs48l32->pdm_sup, + ARRAY_SIZE(cs48l32->pdm_sup), + 1); +} + +int cs48l32_init_inputs(struct snd_soc_component *component) +{ + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_mfd *mfd = cs48l32->mfd; + unsigned int ana_mode_l, ana_mode_r, dig_mode; + int i; + + /* + * Initialize input modes from the A settings. For muxed inputs the + * B settings will be applied if the mux is changed + */ + for (i = 0; i < cs48l32->max_analogue_inputs; i++) { + dev_dbg(cs48l32->dev, "IN%d type %u:%u:%u:%u\n", i + 1, + cs48l32->in_type[i][0], + cs48l32->in_type[i][1], + cs48l32->in_type[i][2], + cs48l32->in_type[i][3]); + + switch (cs48l32->in_type[i][0]) { + case CS48L32_IN_TYPE_DIFF: + ana_mode_l = 0; + break; + case CS48L32_IN_TYPE_SE: + ana_mode_l = 1 << CS48L32_INx_SRC_SHIFT; + break; + default: + dev_warn(cs48l32->dev, "IN%dL_1 Illegal in_type %u ignored\n", + i + 1, cs48l32->in_type[i][0]); + continue; + } + + switch (cs48l32->in_type[i][1]) { + case CS48L32_IN_TYPE_DIFF: + ana_mode_r = 0; + break; + case CS48L32_IN_TYPE_SE: + ana_mode_r = 1 << CS48L32_INx_SRC_SHIFT; + break; + default: + dev_warn(cs48l32->dev, "IN%dR_1 Illegal in_type %u ignored\n", + i + 1, cs48l32->in_type[i][1]); + continue; + } + + dev_dbg(cs48l32->dev, "IN%d_1 Analogue mode=0x%x,0x%x\n", + i + 1, ana_mode_l, ana_mode_r); + + regmap_update_bits(mfd->regmap, + CS48L32_IN1L_CONTROL1 + (i * 0x40), + CS48L32_INx_SRC_MASK, + ana_mode_l); + + regmap_update_bits(mfd->regmap, + CS48L32_IN1R_CONTROL1 + (i * 0x40), + CS48L32_INx_SRC_MASK, + ana_mode_r); + } + + for (i = 0; i < cs48l32->max_pdm_sup; i++) { + dig_mode = cs48l32->pdm_sup[i] << CS48L32_IN1_PDM_SUP_SHIFT; + + dev_dbg(cs48l32->dev, "IN%d PDM_SUP=0x%x\n", i + 1, dig_mode); + + regmap_update_bits(mfd->regmap, + CS48L32_INPUT1_CONTROL1 + (i * 0x40), + CS48L32_IN1_PDM_SUP_MASK, dig_mode); + } + + return 0; +} + +int cs48l32_init_dai(struct cs48l32 *cs48l32, int id) +{ + struct cs48l32_dai_priv *dai_priv = &cs48l32->dai[id]; + + dai_priv->clk = CS48L32_CLK_SYSCLK_1; + dai_priv->constraint = cs48l32_constraint; + + return 0; +} + +int cs48l32_init_eq(struct cs48l32 *cs48l32) +{ + struct cs48l32_mfd *mfd = cs48l32->mfd; + unsigned int reg = CS48L32_EQ1_BAND1_COEFF1, mode; + __be16 *data; + int i, ret; + + ret = regmap_read(mfd->regmap, CS48L32_EQ_CONTROL2, &mode); + if (ret < 0) { + dev_err(cs48l32->dev, "Error reading EQ mode: %d\n", ret); + goto out; + } + + for (i = 0; i < 4; ++i) { + cs48l32->eq_mode[i] = (mode >> i) & 0x1; + + data = &cs48l32->eq_coefficients[i][0]; + ret = regmap_raw_read(mfd->regmap, reg + (i * 68), data, + CS48L32_EQ_BLOCK_SZ); + if (ret < 0) { + dev_err(cs48l32->dev, "Error reading EQ coefficients: %d\n", ret); + goto out; + } + } + +out: + return ret; +} + +int cs48l32_core_init(struct cs48l32 *cs48l32) +{ + BUILD_BUG_ON(ARRAY_SIZE(cs48l32_mixer_texts) != CS48L32_NUM_MIXER_INPUTS); + BUILD_BUG_ON(ARRAY_SIZE(cs48l32_mixer_values) != CS48L32_NUM_MIXER_INPUTS); + BUILD_BUG_ON(cs48l32_sample_rate_text[CS48L32_SAMPLE_RATE_ENUM_SIZE - 1] == NULL); + BUILD_BUG_ON(cs48l32_sample_rate_val[CS48L32_SAMPLE_RATE_ENUM_SIZE - 1] == 0); + BUILD_BUG_ON(ARRAY_SIZE(cs48l32_in_texts) != CS48L32_MAX_INPUT); + + cs48l32_prop_get(cs48l32); + + mutex_init(&cs48l32->rate_lock); + + return 0; +} + +int cs48l32_core_destroy(struct cs48l32 *cs48l32) +{ + mutex_destroy(&cs48l32->rate_lock); + + return 0; +} diff --git a/sound/soc/codecs/cs48l32.c b/sound/soc/codecs/cs48l32.c new file mode 100644 index 000000000000..64763772b881 --- /dev/null +++ b/sound/soc/codecs/cs48l32.c @@ -0,0 +1,1211 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// ALSA SoC Audio driver for CS48L32 codec. +// +// Copyright (C) 2018-2020, 2022 Cirrus Logic, Inc. and +// Cirrus Logic International Semiconductor Ltd. + +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/init.h> +#include <linux/irqchip/irq-cirrus-cs48l32.h> +#include <linux/mfd/cs48l32/core.h> +#include <linux/mfd/cs48l32/registers.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pm.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/tlv.h> + +#include "cs48l32.h" +#include "wm_adsp.h" + +static const struct cs_dsp_region cs48l32_dsp1_regions[] = { + { .type = WMFW_HALO_PM_PACKED, .base = 0x3800000 }, + { .type = WMFW_HALO_XM_PACKED, .base = 0x2000000 }, + { .type = WMFW_ADSP2_XM, .base = 0x2800000 }, + { .type = WMFW_HALO_YM_PACKED, .base = 0x2C00000 }, + { .type = WMFW_ADSP2_YM, .base = 0x3400000 }, +}; + +static const struct cs48l32_dsp_power_reg_block cs48l32_dsp1_sram_ext_regs[] = { + { CS48L32_DSP1_XM_SRAM_IBUS_SETUP_1, CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24 }, + { CS48L32_DSP1_YM_SRAM_IBUS_SETUP_1, CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8 }, + { CS48L32_DSP1_PM_SRAM_IBUS_SETUP_1, CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7 }, +}; + +static const unsigned int cs48l32_dsp1_sram_pwd_regs[] = { + CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0, + CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0, + CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0, +}; + +static const struct cs48l32_dsp_power_regs cs48l32_dsp_sram_regs = { + .ext = cs48l32_dsp1_sram_ext_regs, + .n_ext = ARRAY_SIZE(cs48l32_dsp1_sram_ext_regs), + .pwd = cs48l32_dsp1_sram_pwd_regs, + .n_pwd = ARRAY_SIZE(cs48l32_dsp1_sram_pwd_regs), +}; + +static const struct snd_kcontrol_new cs48l32_snd_controls[] = { +SOC_ENUM("IN1 OSR", cs48l32_in_dmic_osr[0]), +SOC_ENUM("IN2 OSR", cs48l32_in_dmic_osr[1]), + +SOC_SINGLE_RANGE_TLV("IN1L Volume", CS48L32_IN1L_CONTROL2, + CS48L32_INx_PGA_VOL_SHIFT, 0x40, 0x5f, 0, cs48l32_ana_tlv), +SOC_SINGLE_RANGE_TLV("IN1R Volume", CS48L32_IN1R_CONTROL2, + CS48L32_INx_PGA_VOL_SHIFT, 0x40, 0x5f, 0, cs48l32_ana_tlv), + +SOC_ENUM("IN HPF Cutoff Frequency", cs48l32_in_hpf_cut_enum), + +SOC_SINGLE_EXT("IN1L LP Switch", CS48L32_IN1L_CONTROL1, CS48L32_INx_LP_MODE_SHIFT, + 1, 0, snd_soc_get_volsw, cs48l32_low_power_mode_put), +SOC_SINGLE_EXT("IN1R LP Switch", CS48L32_IN1R_CONTROL1, CS48L32_INx_LP_MODE_SHIFT, + 1, 0, snd_soc_get_volsw, cs48l32_low_power_mode_put), + +SOC_SINGLE("IN1L HPF Switch", CS48L32_IN1L_CONTROL1, CS48L32_INx_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN1R HPF Switch", CS48L32_IN1R_CONTROL1, CS48L32_INx_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2L HPF Switch", CS48L32_IN2L_CONTROL1, CS48L32_INx_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2R HPF Switch", CS48L32_IN2R_CONTROL1, CS48L32_INx_HPF_SHIFT, 1, 0), + +SOC_SINGLE_EXT_TLV("IN1L Digital Volume", CS48L32_IN1L_CONTROL2, + CS48L32_INx_VOL_SHIFT, 0xbf, 0, snd_soc_get_volsw, + cs48l32_in_put_volsw, cs48l32_digital_tlv), +SOC_SINGLE_EXT_TLV("IN1R Digital Volume", CS48L32_IN1R_CONTROL2, + CS48L32_INx_VOL_SHIFT, 0xbf, 0, snd_soc_get_volsw, + cs48l32_in_put_volsw, cs48l32_digital_tlv), +SOC_SINGLE_EXT_TLV("IN2L Digital Volume", CS48L32_IN2L_CONTROL2, + CS48L32_INx_VOL_SHIFT, 0xbf, 0, snd_soc_get_volsw, + cs48l32_in_put_volsw, cs48l32_digital_tlv), +SOC_SINGLE_EXT_TLV("IN2R Digital Volume", CS48L32_IN2R_CONTROL2, + CS48L32_INx_VOL_SHIFT, 0xbf, 0, snd_soc_get_volsw, + cs48l32_in_put_volsw, cs48l32_digital_tlv), + +SOC_ENUM("Input Ramp Up", cs48l32_in_vi_ramp), +SOC_ENUM("Input Ramp Down", cs48l32_in_vd_ramp), + +CS48L32_RATE_ENUM("Ultrasonic 1 Rate", cs48l32_us_output_rate[0]), +CS48L32_RATE_ENUM("Ultrasonic 2 Rate", cs48l32_us_output_rate[1]), + +SOC_ENUM("Ultrasonic 1 Freq", cs48l32_us_freq[0]), +SOC_ENUM("Ultrasonic 2 Freq", cs48l32_us_freq[1]), + +SOC_SINGLE_TLV("Ultrasonic 1 Volume", CS48L32_US1_CONTROL, CS48L32_US1_GAIN_SHIFT, + 3, 0, cs48l32_us_tlv), +SOC_SINGLE_TLV("Ultrasonic 2 Volume", CS48L32_US2_CONTROL, CS48L32_US1_GAIN_SHIFT, + 3, 0, cs48l32_us_tlv), + +SOC_ENUM("Ultrasonic 1 Activity Detect Threshold", cs48l32_us_det_thr[0]), +SOC_ENUM("Ultrasonic 2 Activity Detect Threshold", cs48l32_us_det_thr[1]), + +SOC_ENUM("Ultrasonic 1 Activity Detect Pulse Length", cs48l32_us_det_num[0]), +SOC_ENUM("Ultrasonic 2 Activity Detect Pulse Length", cs48l32_us_det_num[1]), + +SOC_ENUM("Ultrasonic 1 Activity Detect Hold", cs48l32_us_det_hold[0]), +SOC_ENUM("Ultrasonic 2 Activity Detect Hold", cs48l32_us_det_hold[1]), + +SOC_ENUM("Ultrasonic 1 Activity Detect Decay", cs48l32_us_det_dcy[0]), +SOC_ENUM("Ultrasonic 2 Activity Detect Decay", cs48l32_us_det_dcy[1]), + +SOC_SINGLE("Ultrasonic 1 Activity Detect LPF Switch", + CS48L32_US1_DET_CONTROL, CS48L32_US1_DET_LPF_SHIFT, 1, 0), +SOC_SINGLE("Ultrasonic 2 Activity Detect LPF Switch", + CS48L32_US2_DET_CONTROL, CS48L32_US1_DET_LPF_SHIFT, 1, 0), + +SOC_ENUM("Ultrasonic 1 Activity Detect LPF Cut-off", cs48l32_us_det_lpf_cut[0]), +SOC_ENUM("Ultrasonic 2 Activity Detect LPF Cut-off", cs48l32_us_det_lpf_cut[1]), + +CS48L32_MIXER_CONTROLS("EQ1", CS48L32_EQ1_INPUT1), +CS48L32_MIXER_CONTROLS("EQ2", CS48L32_EQ2_INPUT1), +CS48L32_MIXER_CONTROLS("EQ3", CS48L32_EQ3_INPUT1), +CS48L32_MIXER_CONTROLS("EQ4", CS48L32_EQ4_INPUT1), + +SOC_ENUM_EXT("EQ1 Mode", cs48l32_eq_mode[0], cs48l32_eq_mode_get, cs48l32_eq_mode_put), + +CS48L32_EQ_COEFF_CONTROLS(EQ1), + +SOC_SINGLE_TLV("EQ1 B1 Volume", CS48L32_EQ1_GAIN1, 0, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ1 B2 Volume", CS48L32_EQ1_GAIN1, 8, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ1 B3 Volume", CS48L32_EQ1_GAIN1, 16, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ1 B4 Volume", CS48L32_EQ1_GAIN1, 24, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ1 B5 Volume", CS48L32_EQ1_GAIN2, 0, 24, 0, cs48l32_eq_tlv), + +SOC_ENUM_EXT("EQ2 Mode", cs48l32_eq_mode[1], cs48l32_eq_mode_get, cs48l32_eq_mode_put), +CS48L32_EQ_COEFF_CONTROLS(EQ2), +SOC_SINGLE_TLV("EQ2 B1 Volume", CS48L32_EQ2_GAIN1, 0, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ2 B2 Volume", CS48L32_EQ2_GAIN1, 8, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ2 B3 Volume", CS48L32_EQ2_GAIN1, 16, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ2 B4 Volume", CS48L32_EQ2_GAIN1, 24, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ2 B5 Volume", CS48L32_EQ2_GAIN2, 0, 24, 0, cs48l32_eq_tlv), + +SOC_ENUM_EXT("EQ3 Mode", cs48l32_eq_mode[2], cs48l32_eq_mode_get, cs48l32_eq_mode_put), +CS48L32_EQ_COEFF_CONTROLS(EQ3), +SOC_SINGLE_TLV("EQ3 B1 Volume", CS48L32_EQ3_GAIN1, 0, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ3 B2 Volume", CS48L32_EQ3_GAIN1, 8, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ3 B3 Volume", CS48L32_EQ3_GAIN1, 16, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ3 B4 Volume", CS48L32_EQ3_GAIN1, 24, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ3 B5 Volume", CS48L32_EQ3_GAIN2, 0, 24, 0, cs48l32_eq_tlv), + +SOC_ENUM_EXT("EQ4 Mode", cs48l32_eq_mode[3], cs48l32_eq_mode_get, cs48l32_eq_mode_put), +CS48L32_EQ_COEFF_CONTROLS(EQ4), +SOC_SINGLE_TLV("EQ4 B1 Volume", CS48L32_EQ4_GAIN1, 0, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ4 B2 Volume", CS48L32_EQ4_GAIN1, 8, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ4 B3 Volume", CS48L32_EQ4_GAIN1, 16, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ4 B4 Volume", CS48L32_EQ4_GAIN1, 24, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ4 B5 Volume", CS48L32_EQ4_GAIN2, 0, 24, 0, cs48l32_eq_tlv), + +CS48L32_MIXER_CONTROLS("DRC1L", CS48L32_DRC1L_INPUT1), +CS48L32_MIXER_CONTROLS("DRC1R", CS48L32_DRC1R_INPUT1), +CS48L32_MIXER_CONTROLS("DRC2L", CS48L32_DRC2L_INPUT1), +CS48L32_MIXER_CONTROLS("DRC2R", CS48L32_DRC2R_INPUT1), + +SND_SOC_BYTES_MASK("DRC1 Coefficients", CS48L32_DRC1_CONTROL1, 4, + BIT(CS48L32_DRC1R_EN_SHIFT) | BIT(CS48L32_DRC1L_EN_SHIFT)), +SND_SOC_BYTES_MASK("DRC2 Coefficients", CS48L32_DRC2_CONTROL1, 4, + BIT(CS48L32_DRC1R_EN_SHIFT) | BIT(CS48L32_DRC1L_EN_SHIFT)), + +CS48L32_MIXER_CONTROLS("LHPF1", CS48L32_LHPF1_INPUT1), +CS48L32_MIXER_CONTROLS("LHPF2", CS48L32_LHPF2_INPUT1), +CS48L32_MIXER_CONTROLS("LHPF3", CS48L32_LHPF3_INPUT1), +CS48L32_MIXER_CONTROLS("LHPF4", CS48L32_LHPF4_INPUT1), + +CS48L32_LHPF_CONTROL("LHPF1 Coefficients", CS48L32_LHPF1_COEFF), +CS48L32_LHPF_CONTROL("LHPF2 Coefficients", CS48L32_LHPF2_COEFF), +CS48L32_LHPF_CONTROL("LHPF3 Coefficients", CS48L32_LHPF3_COEFF), +CS48L32_LHPF_CONTROL("LHPF4 Coefficients", CS48L32_LHPF4_COEFF), + +SOC_ENUM("LHPF1 Mode", cs48l32_lhpf_mode[0]), +SOC_ENUM("LHPF2 Mode", cs48l32_lhpf_mode[1]), +SOC_ENUM("LHPF3 Mode", cs48l32_lhpf_mode[2]), +SOC_ENUM("LHPF4 Mode", cs48l32_lhpf_mode[3]), + +CS48L32_RATE_CONTROL("Sample Rate 1", 1), +CS48L32_RATE_CONTROL("Sample Rate 2", 2), +CS48L32_RATE_CONTROL("Sample Rate 3", 3), +CS48L32_RATE_CONTROL("Sample Rate 4", 4), + +CS48L32_RATE_ENUM("FX Rate", cs48l32_fx_rate), + +CS48L32_RATE_ENUM("ISRC1 FSL", cs48l32_isrc_fsl[0]), +CS48L32_RATE_ENUM("ISRC2 FSL", cs48l32_isrc_fsl[1]), +CS48L32_RATE_ENUM("ISRC3 FSL", cs48l32_isrc_fsl[2]), +CS48L32_RATE_ENUM("ISRC1 FSH", cs48l32_isrc_fsh[0]), +CS48L32_RATE_ENUM("ISRC2 FSH", cs48l32_isrc_fsh[1]), +CS48L32_RATE_ENUM("ISRC3 FSH", cs48l32_isrc_fsh[2]), + +SOC_ENUM("AUXPDM1 Rate", cs48l32_auxpdm1_freq), +SOC_ENUM("AUXPDM2 Rate", cs48l32_auxpdm2_freq), + +SOC_ENUM_EXT("IN1L Rate", cs48l32_input_rate[0], snd_soc_get_enum_double, cs48l32_in_rate_put), +SOC_ENUM_EXT("IN1R Rate", cs48l32_input_rate[1], snd_soc_get_enum_double, cs48l32_in_rate_put), +SOC_ENUM_EXT("IN2L Rate", cs48l32_input_rate[2], snd_soc_get_enum_double, cs48l32_in_rate_put), +SOC_ENUM_EXT("IN2R Rate", cs48l32_input_rate[3], snd_soc_get_enum_double, cs48l32_in_rate_put), + +CS48L32_RATE_ENUM("Noise Generator Rate", noise_gen_rate), + +SOC_SINGLE_TLV("Noise Generator Volume", CS48L32_COMFORT_NOISE_GENERATOR, + CS48L32_NOISE_GEN_GAIN_SHIFT, 0x12, 0, cs48l32_noise_tlv), + +CS48L32_MIXER_CONTROLS("ASP1TX1", CS48L32_ASP1TX1_INPUT1), +CS48L32_MIXER_CONTROLS("ASP1TX2", CS48L32_ASP1TX2_INPUT1), +CS48L32_MIXER_CONTROLS("ASP1TX3", CS48L32_ASP1TX3_INPUT1), +CS48L32_MIXER_CONTROLS("ASP1TX4", CS48L32_ASP1TX4_INPUT1), +CS48L32_MIXER_CONTROLS("ASP1TX5", CS48L32_ASP1TX5_INPUT1), +CS48L32_MIXER_CONTROLS("ASP1TX6", CS48L32_ASP1TX6_INPUT1), +CS48L32_MIXER_CONTROLS("ASP1TX7", CS48L32_ASP1TX7_INPUT1), +CS48L32_MIXER_CONTROLS("ASP1TX8", CS48L32_ASP1TX8_INPUT1), + +CS48L32_MIXER_CONTROLS("ASP2TX1", CS48L32_ASP2TX1_INPUT1), +CS48L32_MIXER_CONTROLS("ASP2TX2", CS48L32_ASP2TX2_INPUT1), +CS48L32_MIXER_CONTROLS("ASP2TX3", CS48L32_ASP2TX3_INPUT1), +CS48L32_MIXER_CONTROLS("ASP2TX4", CS48L32_ASP2TX4_INPUT1), + +WM_ADSP2_PRELOAD_SWITCH("DSP1", 1), + +CS48L32_MIXER_CONTROLS("DSP1RX1", CS48L32_DSP1RX1_INPUT1), +CS48L32_MIXER_CONTROLS("DSP1RX2", CS48L32_DSP1RX2_INPUT1), +CS48L32_MIXER_CONTROLS("DSP1RX3", CS48L32_DSP1RX3_INPUT1), +CS48L32_MIXER_CONTROLS("DSP1RX4", CS48L32_DSP1RX4_INPUT1), +CS48L32_MIXER_CONTROLS("DSP1RX5", CS48L32_DSP1RX5_INPUT1), +CS48L32_MIXER_CONTROLS("DSP1RX6", CS48L32_DSP1RX6_INPUT1), +CS48L32_MIXER_CONTROLS("DSP1RX7", CS48L32_DSP1RX7_INPUT1), +CS48L32_MIXER_CONTROLS("DSP1RX8", CS48L32_DSP1RX8_INPUT1), + +WM_ADSP_FW_CONTROL("DSP1", 0), + +CS48L32_DSP_RATE_CONTROL("DSP1RX1", 0), +CS48L32_DSP_RATE_CONTROL("DSP1RX2", 1), +CS48L32_DSP_RATE_CONTROL("DSP1RX3", 2), +CS48L32_DSP_RATE_CONTROL("DSP1RX4", 3), +CS48L32_DSP_RATE_CONTROL("DSP1RX5", 4), +CS48L32_DSP_RATE_CONTROL("DSP1RX6", 5), +CS48L32_DSP_RATE_CONTROL("DSP1RX7", 6), +CS48L32_DSP_RATE_CONTROL("DSP1RX8", 7), +CS48L32_DSP_RATE_CONTROL("DSP1TX1", 8), +CS48L32_DSP_RATE_CONTROL("DSP1TX2", 9), +CS48L32_DSP_RATE_CONTROL("DSP1TX3", 10), +CS48L32_DSP_RATE_CONTROL("DSP1TX4", 11), +CS48L32_DSP_RATE_CONTROL("DSP1TX5", 12), +CS48L32_DSP_RATE_CONTROL("DSP1TX6", 13), +CS48L32_DSP_RATE_CONTROL("DSP1TX7", 14), +CS48L32_DSP_RATE_CONTROL("DSP1TX8", 15), +}; + +CS48L32_MIXER_ENUMS(EQ1, CS48L32_EQ1_INPUT1); +CS48L32_MIXER_ENUMS(EQ2, CS48L32_EQ2_INPUT1); +CS48L32_MIXER_ENUMS(EQ3, CS48L32_EQ3_INPUT1); +CS48L32_MIXER_ENUMS(EQ4, CS48L32_EQ4_INPUT1); + +CS48L32_MIXER_ENUMS(DRC1L, CS48L32_DRC1L_INPUT1); +CS48L32_MIXER_ENUMS(DRC1R, CS48L32_DRC1R_INPUT1); +CS48L32_MIXER_ENUMS(DRC2L, CS48L32_DRC2L_INPUT1); +CS48L32_MIXER_ENUMS(DRC2R, CS48L32_DRC2R_INPUT1); + +CS48L32_MIXER_ENUMS(LHPF1, CS48L32_LHPF1_INPUT1); +CS48L32_MIXER_ENUMS(LHPF2, CS48L32_LHPF2_INPUT1); +CS48L32_MIXER_ENUMS(LHPF3, CS48L32_LHPF3_INPUT1); +CS48L32_MIXER_ENUMS(LHPF4, CS48L32_LHPF4_INPUT1); + +CS48L32_MIXER_ENUMS(ASP1TX1, CS48L32_ASP1TX1_INPUT1); +CS48L32_MIXER_ENUMS(ASP1TX2, CS48L32_ASP1TX2_INPUT1); +CS48L32_MIXER_ENUMS(ASP1TX3, CS48L32_ASP1TX3_INPUT1); +CS48L32_MIXER_ENUMS(ASP1TX4, CS48L32_ASP1TX4_INPUT1); +CS48L32_MIXER_ENUMS(ASP1TX5, CS48L32_ASP1TX5_INPUT1); +CS48L32_MIXER_ENUMS(ASP1TX6, CS48L32_ASP1TX6_INPUT1); +CS48L32_MIXER_ENUMS(ASP1TX7, CS48L32_ASP1TX7_INPUT1); +CS48L32_MIXER_ENUMS(ASP1TX8, CS48L32_ASP1TX8_INPUT1); + +CS48L32_MIXER_ENUMS(ASP2TX1, CS48L32_ASP2TX1_INPUT1); +CS48L32_MIXER_ENUMS(ASP2TX2, CS48L32_ASP2TX2_INPUT1); +CS48L32_MIXER_ENUMS(ASP2TX3, CS48L32_ASP2TX3_INPUT1); +CS48L32_MIXER_ENUMS(ASP2TX4, CS48L32_ASP2TX4_INPUT1); + +CS48L32_MUX_ENUMS(ISRC1INT1, CS48L32_ISRC1INT1_INPUT1); +CS48L32_MUX_ENUMS(ISRC1INT2, CS48L32_ISRC1INT2_INPUT1); +CS48L32_MUX_ENUMS(ISRC1INT3, CS48L32_ISRC1INT3_INPUT1); +CS48L32_MUX_ENUMS(ISRC1INT4, CS48L32_ISRC1INT4_INPUT1); + +CS48L32_MUX_ENUMS(ISRC1DEC1, CS48L32_ISRC1DEC1_INPUT1); +CS48L32_MUX_ENUMS(ISRC1DEC2, CS48L32_ISRC1DEC2_INPUT1); +CS48L32_MUX_ENUMS(ISRC1DEC3, CS48L32_ISRC1DEC3_INPUT1); +CS48L32_MUX_ENUMS(ISRC1DEC4, CS48L32_ISRC1DEC4_INPUT1); + +CS48L32_MUX_ENUMS(ISRC2INT1, CS48L32_ISRC2INT1_INPUT1); +CS48L32_MUX_ENUMS(ISRC2INT2, CS48L32_ISRC2INT2_INPUT1); + +CS48L32_MUX_ENUMS(ISRC2DEC1, CS48L32_ISRC2DEC1_INPUT1); +CS48L32_MUX_ENUMS(ISRC2DEC2, CS48L32_ISRC2DEC2_INPUT1); + +CS48L32_MUX_ENUMS(ISRC3INT1, CS48L32_ISRC3INT1_INPUT1); +CS48L32_MUX_ENUMS(ISRC3INT2, CS48L32_ISRC3INT2_INPUT1); + +CS48L32_MUX_ENUMS(ISRC3DEC1, CS48L32_ISRC3DEC1_INPUT1); +CS48L32_MUX_ENUMS(ISRC3DEC2, CS48L32_ISRC3DEC2_INPUT1); + +CS48L32_MIXER_ENUMS(DSP1RX1, CS48L32_DSP1RX1_INPUT1); +CS48L32_MIXER_ENUMS(DSP1RX2, CS48L32_DSP1RX2_INPUT1); +CS48L32_MIXER_ENUMS(DSP1RX3, CS48L32_DSP1RX3_INPUT1); +CS48L32_MIXER_ENUMS(DSP1RX4, CS48L32_DSP1RX4_INPUT1); +CS48L32_MIXER_ENUMS(DSP1RX5, CS48L32_DSP1RX5_INPUT1); +CS48L32_MIXER_ENUMS(DSP1RX6, CS48L32_DSP1RX6_INPUT1); +CS48L32_MIXER_ENUMS(DSP1RX7, CS48L32_DSP1RX7_INPUT1); +CS48L32_MIXER_ENUMS(DSP1RX8, CS48L32_DSP1RX8_INPUT1); + +static int cs48l32_dsp_mem_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + return cs48l32_dsp_memory_enable(cs48l32, &cs48l32_dsp_sram_regs); + case SND_SOC_DAPM_PRE_PMD: + cs48l32_dsp_memory_disable(cs48l32, &cs48l32_dsp_sram_regs); + return 0; + default: + return 0; + } +} + +static const struct snd_soc_dapm_widget cs48l32_dapm_widgets[] = { +SND_SOC_DAPM_SUPPLY("SYSCLK", CS48L32_SYSTEM_CLOCK1, CS48L32_SYSCLK_EN_SHIFT, 0, + cs48l32_sysclk_ev, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_SUPPLY("OPCLK", CS48L32_OUTPUT_SYS_CLK, CS48L32_OPCLK_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_REGULATOR_SUPPLY("VDD_CP", 20, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("VOUT_MIC", 0, SND_SOC_DAPM_REGULATOR_BYPASS), + +SND_SOC_DAPM_SUPPLY("MICBIAS1", CS48L32_MICBIAS_CTRL1, CS48L32_MICB1_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_SUPPLY("MICBIAS1A", CS48L32_MICBIAS_CTRL5, CS48L32_MICB1A_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS1B", CS48L32_MICBIAS_CTRL5, CS48L32_MICB1B_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS1C", CS48L32_MICBIAS_CTRL5, CS48L32_MICB1C_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_SUPPLY("DSP1MEM", SND_SOC_NOPM, 0, 0, cs48l32_dsp_mem_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + +CS48L32_DSP_FREQ_WIDGET_EV("DSP1", 0, cs48l32_dsp_freq_ev), + +SND_SOC_DAPM_SIGGEN("TONE"), +SND_SOC_DAPM_SIGGEN("NOISE"), + +SND_SOC_DAPM_INPUT("IN1LN_1"), +SND_SOC_DAPM_INPUT("IN1LN_2"), +SND_SOC_DAPM_INPUT("IN1LP_1"), +SND_SOC_DAPM_INPUT("IN1LP_2"), +SND_SOC_DAPM_INPUT("IN1RN_1"), +SND_SOC_DAPM_INPUT("IN1RN_2"), +SND_SOC_DAPM_INPUT("IN1RP_1"), +SND_SOC_DAPM_INPUT("IN1RP_2"), +SND_SOC_DAPM_INPUT("IN1_PDMCLK"), +SND_SOC_DAPM_INPUT("IN1_PDMDATA"), + +SND_SOC_DAPM_INPUT("IN2_PDMCLK"), +SND_SOC_DAPM_INPUT("IN2_PDMDATA"), + +SND_SOC_DAPM_MUX("Ultrasonic 1 Input", SND_SOC_NOPM, 0, 0, &cs48l32_us_inmux[0]), +SND_SOC_DAPM_MUX("Ultrasonic 2 Input", SND_SOC_NOPM, 0, 0, &cs48l32_us_inmux[1]), + +SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"), +SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"), + +SND_SOC_DAPM_OUTPUT("DSP Trigger Out"), + +SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &cs48l32_inmux[0]), +SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &cs48l32_inmux[1]), + +SND_SOC_DAPM_MUX("IN1L Mode", SND_SOC_NOPM, 0, 0, &cs48l32_dmode_mux[0]), +SND_SOC_DAPM_MUX("IN1R Mode", SND_SOC_NOPM, 0, 0, &cs48l32_dmode_mux[0]), + +SND_SOC_DAPM_AIF_OUT("ASP1TX1", NULL, 0, CS48L32_ASP1_ENABLES1, 0, 0), +SND_SOC_DAPM_AIF_OUT("ASP1TX2", NULL, 1, CS48L32_ASP1_ENABLES1, 1, 0), +SND_SOC_DAPM_AIF_OUT("ASP1TX3", NULL, 2, CS48L32_ASP1_ENABLES1, 2, 0), +SND_SOC_DAPM_AIF_OUT("ASP1TX4", NULL, 3, CS48L32_ASP1_ENABLES1, 3, 0), +SND_SOC_DAPM_AIF_OUT("ASP1TX5", NULL, 4, CS48L32_ASP1_ENABLES1, 4, 0), +SND_SOC_DAPM_AIF_OUT("ASP1TX6", NULL, 5, CS48L32_ASP1_ENABLES1, 5, 0), +SND_SOC_DAPM_AIF_OUT("ASP1TX7", NULL, 6, CS48L32_ASP1_ENABLES1, 6, 0), +SND_SOC_DAPM_AIF_OUT("ASP1TX8", NULL, 7, CS48L32_ASP1_ENABLES1, 7, 0), + +SND_SOC_DAPM_AIF_OUT("ASP2TX1", NULL, 0, CS48L32_ASP2_ENABLES1, 0, 0), +SND_SOC_DAPM_AIF_OUT("ASP2TX2", NULL, 1, CS48L32_ASP2_ENABLES1, 1, 0), +SND_SOC_DAPM_AIF_OUT("ASP2TX3", NULL, 2, CS48L32_ASP2_ENABLES1, 2, 0), +SND_SOC_DAPM_AIF_OUT("ASP2TX4", NULL, 3, CS48L32_ASP2_ENABLES1, 3, 0), + +SND_SOC_DAPM_SWITCH("AUXPDM1 Output", CS48L32_AUXPDM_CONTROL1, 0, 0, &cs48l32_auxpdm_switch[0]), +SND_SOC_DAPM_SWITCH("AUXPDM2 Output", CS48L32_AUXPDM_CONTROL1, 1, 0, &cs48l32_auxpdm_switch[1]), + +SND_SOC_DAPM_MUX("AUXPDM1 Input", SND_SOC_NOPM, 0, 0, &cs48l32_auxpdm_inmux[0]), +SND_SOC_DAPM_MUX("AUXPDM2 Input", SND_SOC_NOPM, 0, 0, &cs48l32_auxpdm_inmux[1]), + +SND_SOC_DAPM_MUX("AUXPDM1 Analog Input", SND_SOC_NOPM, 0, 0, + &cs48l32_auxpdm_analog_inmux[0]), +SND_SOC_DAPM_MUX("AUXPDM2 Analog Input", SND_SOC_NOPM, 0, 0, + &cs48l32_auxpdm_analog_inmux[1]), + +SND_SOC_DAPM_SWITCH("Ultrasonic 1 Activity Detect", CS48L32_US_CONTROL, + CS48L32_US1_DET_EN_SHIFT, 0, &cs48l32_us_switch[0]), +SND_SOC_DAPM_SWITCH("Ultrasonic 2 Activity Detect", CS48L32_US_CONTROL, + CS48L32_US1_DET_EN_SHIFT, 0, &cs48l32_us_switch[1]), + +/* + * mux_in widgets : arranged in the order of sources + * specified in CS48L32_MIXER_INPUT_ROUTES + */ +SND_SOC_DAPM_PGA("Tone Generator 1", CS48L32_TONE_GENERATOR1, 0, 0, NULL, 0), +SND_SOC_DAPM_PGA("Tone Generator 2", CS48L32_TONE_GENERATOR1, 1, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Noise Generator", CS48L32_COMFORT_NOISE_GENERATOR, + CS48L32_NOISE_GEN_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA_E("IN1L PGA", CS48L32_INPUT_CONTROL, CS48L32_IN1L_EN_SHIFT, + 0, NULL, 0, cs48l32_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN1R PGA", CS48L32_INPUT_CONTROL, CS48L32_IN1R_EN_SHIFT, + 0, NULL, 0, cs48l32_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2L PGA", CS48L32_INPUT_CONTROL, CS48L32_IN2L_EN_SHIFT, + 0, NULL, 0, cs48l32_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2R PGA", CS48L32_INPUT_CONTROL, CS48L32_IN2R_EN_SHIFT, + 0, NULL, 0, cs48l32_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + +SND_SOC_DAPM_AIF_IN("ASP1RX1", NULL, 0, CS48L32_ASP1_ENABLES1, 16, 0), +SND_SOC_DAPM_AIF_IN("ASP1RX2", NULL, 1, CS48L32_ASP1_ENABLES1, 17, 0), +SND_SOC_DAPM_AIF_IN("ASP1RX3", NULL, 2, CS48L32_ASP1_ENABLES1, 18, 0), +SND_SOC_DAPM_AIF_IN("ASP1RX4", NULL, 3, CS48L32_ASP1_ENABLES1, 19, 0), +SND_SOC_DAPM_AIF_IN("ASP1RX5", NULL, 4, CS48L32_ASP1_ENABLES1, 20, 0), +SND_SOC_DAPM_AIF_IN("ASP1RX6", NULL, 5, CS48L32_ASP1_ENABLES1, 21, 0), +SND_SOC_DAPM_AIF_IN("ASP1RX7", NULL, 6, CS48L32_ASP1_ENABLES1, 22, 0), +SND_SOC_DAPM_AIF_IN("ASP1RX8", NULL, 7, CS48L32_ASP1_ENABLES1, 23, 0), + +SND_SOC_DAPM_AIF_IN("ASP2RX1", NULL, 0, CS48L32_ASP2_ENABLES1, 16, 0), +SND_SOC_DAPM_AIF_IN("ASP2RX2", NULL, 1, CS48L32_ASP2_ENABLES1, 17, 0), +SND_SOC_DAPM_AIF_IN("ASP2RX3", NULL, 2, CS48L32_ASP2_ENABLES1, 18, 0), +SND_SOC_DAPM_AIF_IN("ASP2RX4", NULL, 3, CS48L32_ASP2_ENABLES1, 19, 0), + +SND_SOC_DAPM_PGA("ISRC1DEC1", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_DEC1_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC2", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_DEC2_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC3", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_DEC3_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC4", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_DEC4_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC1INT1", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_INT1_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT2", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_INT2_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT3", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_INT3_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT4", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_INT4_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2DEC1", CS48L32_ISRC2_CONTROL2, CS48L32_ISRC1_DEC1_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC2", CS48L32_ISRC2_CONTROL2, CS48L32_ISRC1_DEC2_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2INT1", CS48L32_ISRC2_CONTROL2, CS48L32_ISRC1_INT1_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT2", CS48L32_ISRC2_CONTROL2, CS48L32_ISRC1_INT2_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC3DEC1", CS48L32_ISRC3_CONTROL2, CS48L32_ISRC1_DEC1_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3DEC2", CS48L32_ISRC3_CONTROL2, CS48L32_ISRC1_DEC2_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC3INT1", CS48L32_ISRC3_CONTROL2, CS48L32_ISRC1_INT1_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3INT2", CS48L32_ISRC3_CONTROL2, CS48L32_ISRC1_INT2_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA_E("EQ1", CS48L32_EQ_CONTROL1, 0, 0, NULL, 0, cs48l32_eq_ev, SND_SOC_DAPM_PRE_PMU), +SND_SOC_DAPM_PGA_E("EQ2", CS48L32_EQ_CONTROL1, 1, 0, NULL, 0, cs48l32_eq_ev, SND_SOC_DAPM_PRE_PMU), +SND_SOC_DAPM_PGA_E("EQ3", CS48L32_EQ_CONTROL1, 2, 0, NULL, 0, cs48l32_eq_ev, SND_SOC_DAPM_PRE_PMU), +SND_SOC_DAPM_PGA_E("EQ4", CS48L32_EQ_CONTROL1, 3, 0, NULL, 0, cs48l32_eq_ev, SND_SOC_DAPM_PRE_PMU), + +SND_SOC_DAPM_PGA("DRC1L", CS48L32_DRC1_CONTROL1, CS48L32_DRC1L_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("DRC1R", CS48L32_DRC1_CONTROL1, CS48L32_DRC1R_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("DRC2L", CS48L32_DRC2_CONTROL1, CS48L32_DRC1L_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("DRC2R", CS48L32_DRC2_CONTROL1, CS48L32_DRC1R_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("LHPF1", CS48L32_LHPF_CONTROL1, 0, 0, NULL, 0), +SND_SOC_DAPM_PGA("LHPF2", CS48L32_LHPF_CONTROL1, 1, 0, NULL, 0), +SND_SOC_DAPM_PGA("LHPF3", CS48L32_LHPF_CONTROL1, 2, 0, NULL, 0), +SND_SOC_DAPM_PGA("LHPF4", CS48L32_LHPF_CONTROL1, 3, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Ultrasonic 1", CS48L32_US_CONTROL, 0, 0, NULL, 0), +SND_SOC_DAPM_PGA("Ultrasonic 2", CS48L32_US_CONTROL, 1, 0, NULL, 0), + +WM_ADSP2("DSP1", 0, wm_adsp_early_event), + +/* end of ordered widget list */ + +CS48L32_MIXER_WIDGETS(EQ1, "EQ1"), +CS48L32_MIXER_WIDGETS(EQ2, "EQ2"), +CS48L32_MIXER_WIDGETS(EQ3, "EQ3"), +CS48L32_MIXER_WIDGETS(EQ4, "EQ4"), + +CS48L32_MIXER_WIDGETS(DRC1L, "DRC1L"), +CS48L32_MIXER_WIDGETS(DRC1R, "DRC1R"), +CS48L32_MIXER_WIDGETS(DRC2L, "DRC2L"), +CS48L32_MIXER_WIDGETS(DRC2R, "DRC2R"), + +SND_SOC_DAPM_SWITCH("DRC1 Activity Output", SND_SOC_NOPM, 0, 0, + &cs48l32_drc_activity_output_mux[0]), +SND_SOC_DAPM_SWITCH("DRC2 Activity Output", SND_SOC_NOPM, 0, 0, + &cs48l32_drc_activity_output_mux[1]), + +CS48L32_MIXER_WIDGETS(LHPF1, "LHPF1"), +CS48L32_MIXER_WIDGETS(LHPF2, "LHPF2"), +CS48L32_MIXER_WIDGETS(LHPF3, "LHPF3"), +CS48L32_MIXER_WIDGETS(LHPF4, "LHPF4"), + +CS48L32_MIXER_WIDGETS(ASP1TX1, "ASP1TX1"), +CS48L32_MIXER_WIDGETS(ASP1TX2, "ASP1TX2"), +CS48L32_MIXER_WIDGETS(ASP1TX3, "ASP1TX3"), +CS48L32_MIXER_WIDGETS(ASP1TX4, "ASP1TX4"), +CS48L32_MIXER_WIDGETS(ASP1TX5, "ASP1TX5"), +CS48L32_MIXER_WIDGETS(ASP1TX6, "ASP1TX6"), +CS48L32_MIXER_WIDGETS(ASP1TX7, "ASP1TX7"), +CS48L32_MIXER_WIDGETS(ASP1TX8, "ASP1TX8"), + +CS48L32_MIXER_WIDGETS(ASP2TX1, "ASP2TX1"), +CS48L32_MIXER_WIDGETS(ASP2TX2, "ASP2TX2"), +CS48L32_MIXER_WIDGETS(ASP2TX3, "ASP2TX3"), +CS48L32_MIXER_WIDGETS(ASP2TX4, "ASP2TX4"), + +CS48L32_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"), +CS48L32_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"), +CS48L32_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"), +CS48L32_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"), + +CS48L32_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"), +CS48L32_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"), +CS48L32_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"), +CS48L32_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"), + +CS48L32_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"), +CS48L32_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"), + +CS48L32_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"), +CS48L32_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"), + +CS48L32_MUX_WIDGETS(ISRC3DEC1, "ISRC3DEC1"), +CS48L32_MUX_WIDGETS(ISRC3DEC2, "ISRC3DEC2"), + +CS48L32_MUX_WIDGETS(ISRC3INT1, "ISRC3INT1"), +CS48L32_MUX_WIDGETS(ISRC3INT2, "ISRC3INT2"), + +CS48L32_MIXER_WIDGETS(DSP1RX1, "DSP1RX1"), +CS48L32_MIXER_WIDGETS(DSP1RX2, "DSP1RX2"), +CS48L32_MIXER_WIDGETS(DSP1RX3, "DSP1RX3"), +CS48L32_MIXER_WIDGETS(DSP1RX4, "DSP1RX4"), +CS48L32_MIXER_WIDGETS(DSP1RX5, "DSP1RX5"), +CS48L32_MIXER_WIDGETS(DSP1RX6, "DSP1RX6"), +CS48L32_MIXER_WIDGETS(DSP1RX7, "DSP1RX7"), +CS48L32_MIXER_WIDGETS(DSP1RX8, "DSP1RX8"), + +SND_SOC_DAPM_SWITCH("DSP1 Trigger Output", SND_SOC_NOPM, 0, 0, + &cs48l32_dsp_trigger_output_mux[0]), + +SND_SOC_DAPM_OUTPUT("AUXPDM1_CLK"), +SND_SOC_DAPM_OUTPUT("AUXPDM1_DOUT"), +SND_SOC_DAPM_OUTPUT("AUXPDM2_CLK"), +SND_SOC_DAPM_OUTPUT("AUXPDM2_DOUT"), + +SND_SOC_DAPM_OUTPUT("MICSUPP"), + +SND_SOC_DAPM_OUTPUT("Ultrasonic Dummy Output"), +}; + +#define CS48L32_MIXER_INPUT_ROUTES(name) \ + { name, "Tone Generator 1", "Tone Generator 1" }, \ + { name, "Tone Generator 2", "Tone Generator 2" }, \ + { name, "Noise Generator", "Noise Generator" }, \ + { name, "IN1L", "IN1L PGA" }, \ + { name, "IN1R", "IN1R PGA" }, \ + { name, "IN2L", "IN2L PGA" }, \ + { name, "IN2R", "IN2R PGA" }, \ + { name, "ASP1RX1", "ASP1RX1" }, \ + { name, "ASP1RX2", "ASP1RX2" }, \ + { name, "ASP1RX3", "ASP1RX3" }, \ + { name, "ASP1RX4", "ASP1RX4" }, \ + { name, "ASP1RX5", "ASP1RX5" }, \ + { name, "ASP1RX6", "ASP1RX6" }, \ + { name, "ASP1RX7", "ASP1RX7" }, \ + { name, "ASP1RX8", "ASP1RX8" }, \ + { name, "ASP2RX1", "ASP2RX1" }, \ + { name, "ASP2RX2", "ASP2RX2" }, \ + { name, "ASP2RX3", "ASP2RX3" }, \ + { name, "ASP2RX4", "ASP2RX4" }, \ + { name, "ISRC1DEC1", "ISRC1DEC1" }, \ + { name, "ISRC1DEC2", "ISRC1DEC2" }, \ + { name, "ISRC1DEC3", "ISRC1DEC3" }, \ + { name, "ISRC1DEC4", "ISRC1DEC4" }, \ + { name, "ISRC1INT1", "ISRC1INT1" }, \ + { name, "ISRC1INT2", "ISRC1INT2" }, \ + { name, "ISRC1INT3", "ISRC1INT3" }, \ + { name, "ISRC1INT4", "ISRC1INT4" }, \ + { name, "ISRC2DEC1", "ISRC2DEC1" }, \ + { name, "ISRC2DEC2", "ISRC2DEC2" }, \ + { name, "ISRC2INT1", "ISRC2INT1" }, \ + { name, "ISRC2INT2", "ISRC2INT2" }, \ + { name, "ISRC3DEC1", "ISRC3DEC1" }, \ + { name, "ISRC3DEC2", "ISRC3DEC2" }, \ + { name, "ISRC3INT1", "ISRC3INT1" }, \ + { name, "ISRC3INT2", "ISRC3INT2" }, \ + { name, "EQ1", "EQ1" }, \ + { name, "EQ2", "EQ2" }, \ + { name, "EQ3", "EQ3" }, \ + { name, "EQ4", "EQ4" }, \ + { name, "DRC1L", "DRC1L" }, \ + { name, "DRC1R", "DRC1R" }, \ + { name, "DRC2L", "DRC2L" }, \ + { name, "DRC2R", "DRC2R" }, \ + { name, "LHPF1", "LHPF1" }, \ + { name, "LHPF2", "LHPF2" }, \ + { name, "LHPF3", "LHPF3" }, \ + { name, "LHPF4", "LHPF4" }, \ + { name, "Ultrasonic 1", "Ultrasonic 1" }, \ + { name, "Ultrasonic 2", "Ultrasonic 2" }, \ + { name, "DSP1.1", "DSP1" }, \ + { name, "DSP1.2", "DSP1" }, \ + { name, "DSP1.3", "DSP1" }, \ + { name, "DSP1.4", "DSP1" }, \ + { name, "DSP1.5", "DSP1" }, \ + { name, "DSP1.6", "DSP1" }, \ + { name, "DSP1.7", "DSP1" }, \ + { name, "DSP1.8", "DSP1" } + +static const struct snd_soc_dapm_route cs48l32_dapm_routes[] = { + { "OPCLK", NULL, "SYSCLK" }, + + { "IN1LN_1", NULL, "SYSCLK" }, + { "IN1LN_2", NULL, "SYSCLK" }, + { "IN1LP_1", NULL, "SYSCLK" }, + { "IN1LP_2", NULL, "SYSCLK" }, + { "IN1RN_1", NULL, "SYSCLK" }, + { "IN1RN_2", NULL, "SYSCLK" }, + { "IN1RP_1", NULL, "SYSCLK" }, + { "IN1RP_2", NULL, "SYSCLK" }, + + { "IN1_PDMCLK", NULL, "SYSCLK" }, + { "IN1_PDMDATA", NULL, "SYSCLK" }, + { "IN2_PDMCLK", NULL, "SYSCLK" }, + { "IN2_PDMDATA", NULL, "SYSCLK" }, + + { "DSP1 Preloader", NULL, "DSP1MEM" }, + { "DSP1", NULL, "DSP1FREQ" }, + + { "Audio Trace DSP", NULL, "DSP1" }, + { "Voice Ctrl DSP", NULL, "DSP1" }, + + { "MICBIAS1", NULL, "VOUT_MIC" }, + + { "MICBIAS1A", NULL, "MICBIAS1" }, + { "MICBIAS1B", NULL, "MICBIAS1" }, + { "MICBIAS1C", NULL, "MICBIAS1" }, + + { "Tone Generator 1", NULL, "SYSCLK" }, + { "Tone Generator 2", NULL, "SYSCLK" }, + { "Noise Generator", NULL, "SYSCLK" }, + + { "Tone Generator 1", NULL, "TONE" }, + { "Tone Generator 2", NULL, "TONE" }, + { "Noise Generator", NULL, "NOISE" }, + + { "ASP1 Capture", NULL, "ASP1TX1" }, + { "ASP1 Capture", NULL, "ASP1TX2" }, + { "ASP1 Capture", NULL, "ASP1TX3" }, + { "ASP1 Capture", NULL, "ASP1TX4" }, + { "ASP1 Capture", NULL, "ASP1TX5" }, + { "ASP1 Capture", NULL, "ASP1TX6" }, + { "ASP1 Capture", NULL, "ASP1TX7" }, + { "ASP1 Capture", NULL, "ASP1TX8" }, + + { "ASP1RX1", NULL, "ASP1 Playback" }, + { "ASP1RX2", NULL, "ASP1 Playback" }, + { "ASP1RX3", NULL, "ASP1 Playback" }, + { "ASP1RX4", NULL, "ASP1 Playback" }, + { "ASP1RX5", NULL, "ASP1 Playback" }, + { "ASP1RX6", NULL, "ASP1 Playback" }, + { "ASP1RX7", NULL, "ASP1 Playback" }, + { "ASP1RX8", NULL, "ASP1 Playback" }, + + { "ASP2 Capture", NULL, "ASP2TX1" }, + { "ASP2 Capture", NULL, "ASP2TX2" }, + { "ASP2 Capture", NULL, "ASP2TX3" }, + { "ASP2 Capture", NULL, "ASP2TX4" }, + + { "ASP2RX1", NULL, "ASP2 Playback" }, + { "ASP2RX2", NULL, "ASP2 Playback" }, + { "ASP2RX3", NULL, "ASP2 Playback" }, + { "ASP2RX4", NULL, "ASP2 Playback" }, + + { "ASP1 Playback", NULL, "SYSCLK" }, + { "ASP2 Playback", NULL, "SYSCLK" }, + + { "ASP1 Capture", NULL, "SYSCLK" }, + { "ASP2 Capture", NULL, "SYSCLK" }, + + { "IN1L Mux", "Analog 1", "IN1LN_1" }, + { "IN1L Mux", "Analog 2", "IN1LN_2" }, + { "IN1L Mux", "Analog 1", "IN1LP_1" }, + { "IN1L Mux", "Analog 2", "IN1LP_2" }, + { "IN1R Mux", "Analog 1", "IN1RN_1" }, + { "IN1R Mux", "Analog 2", "IN1RN_2" }, + { "IN1R Mux", "Analog 1", "IN1RP_1" }, + { "IN1R Mux", "Analog 2", "IN1RP_2" }, + + { "IN1L PGA", NULL, "IN1L Mode" }, + { "IN1R PGA", NULL, "IN1R Mode" }, + + { "IN1L Mode", "Analog", "IN1L Mux" }, + { "IN1R Mode", "Analog", "IN1R Mux" }, + + { "IN1L Mode", "Digital", "IN1_PDMCLK" }, + { "IN1L Mode", "Digital", "IN1_PDMDATA" }, + { "IN1R Mode", "Digital", "IN1_PDMCLK" }, + { "IN1R Mode", "Digital", "IN1_PDMDATA" }, + + { "IN1L PGA", NULL, "VOUT_MIC" }, + { "IN1R PGA", NULL, "VOUT_MIC" }, + + { "IN2L PGA", NULL, "VOUT_MIC" }, + { "IN2R PGA", NULL, "VOUT_MIC" }, + + { "IN2L PGA", NULL, "IN2_PDMCLK" }, + { "IN2R PGA", NULL, "IN2_PDMCLK" }, + { "IN2L PGA", NULL, "IN2_PDMDATA" }, + { "IN2R PGA", NULL, "IN2_PDMDATA" }, + + { "Ultrasonic 1", NULL, "Ultrasonic 1 Input" }, + { "Ultrasonic 2", NULL, "Ultrasonic 2 Input" }, + + { "Ultrasonic 1 Input", "IN1L", "IN1L PGA" }, + { "Ultrasonic 1 Input", "IN1R", "IN1R PGA" }, + { "Ultrasonic 1 Input", "IN2L", "IN2L PGA" }, + { "Ultrasonic 1 Input", "IN2R", "IN2R PGA" }, + + { "Ultrasonic 2 Input", "IN1L", "IN1L PGA" }, + { "Ultrasonic 2 Input", "IN1R", "IN1R PGA" }, + { "Ultrasonic 2 Input", "IN2L", "IN2L PGA" }, + { "Ultrasonic 2 Input", "IN2R", "IN2R PGA" }, + + { "Ultrasonic 1 Activity Detect", "Switch", "Ultrasonic 1 Input" }, + { "Ultrasonic 2 Activity Detect", "Switch", "Ultrasonic 2 Input" }, + + { "Ultrasonic Dummy Output", NULL, "Ultrasonic 1 Activity Detect" }, + { "Ultrasonic Dummy Output", NULL, "Ultrasonic 2 Activity Detect" }, + + CS48L32_MIXER_ROUTES("ASP1TX1", "ASP1TX1"), + CS48L32_MIXER_ROUTES("ASP1TX2", "ASP1TX2"), + CS48L32_MIXER_ROUTES("ASP1TX3", "ASP1TX3"), + CS48L32_MIXER_ROUTES("ASP1TX4", "ASP1TX4"), + CS48L32_MIXER_ROUTES("ASP1TX5", "ASP1TX5"), + CS48L32_MIXER_ROUTES("ASP1TX6", "ASP1TX6"), + CS48L32_MIXER_ROUTES("ASP1TX7", "ASP1TX7"), + CS48L32_MIXER_ROUTES("ASP1TX8", "ASP1TX8"), + + CS48L32_MIXER_ROUTES("ASP2TX1", "ASP2TX1"), + CS48L32_MIXER_ROUTES("ASP2TX2", "ASP2TX2"), + CS48L32_MIXER_ROUTES("ASP2TX3", "ASP2TX3"), + CS48L32_MIXER_ROUTES("ASP2TX4", "ASP2TX4"), + + CS48L32_MIXER_ROUTES("EQ1", "EQ1"), + CS48L32_MIXER_ROUTES("EQ2", "EQ2"), + CS48L32_MIXER_ROUTES("EQ3", "EQ3"), + CS48L32_MIXER_ROUTES("EQ4", "EQ4"), + + CS48L32_MIXER_ROUTES("DRC1L", "DRC1L"), + CS48L32_MIXER_ROUTES("DRC1R", "DRC1R"), + CS48L32_MIXER_ROUTES("DRC2L", "DRC2L"), + CS48L32_MIXER_ROUTES("DRC2R", "DRC2R"), + + CS48L32_MIXER_ROUTES("LHPF1", "LHPF1"), + CS48L32_MIXER_ROUTES("LHPF2", "LHPF2"), + CS48L32_MIXER_ROUTES("LHPF3", "LHPF3"), + CS48L32_MIXER_ROUTES("LHPF4", "LHPF4"), + + CS48L32_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), + CS48L32_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), + CS48L32_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"), + CS48L32_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"), + + CS48L32_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), + CS48L32_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), + CS48L32_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"), + CS48L32_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"), + + CS48L32_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), + CS48L32_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), + + CS48L32_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), + CS48L32_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), + + CS48L32_MUX_ROUTES("ISRC3INT1", "ISRC3INT1"), + CS48L32_MUX_ROUTES("ISRC3INT2", "ISRC3INT2"), + + CS48L32_MUX_ROUTES("ISRC3DEC1", "ISRC3DEC1"), + CS48L32_MUX_ROUTES("ISRC3DEC2", "ISRC3DEC2"), + + CS48L32_DSP_ROUTES_1_8_SYSCLK("DSP1"), + + { "DSP Trigger Out", NULL, "DSP1 Trigger Output" }, + + { "DSP1 Trigger Output", "Switch", "DSP1" }, + + { "AUXPDM1 Analog Input", "IN1L", "IN1L PGA" }, + { "AUXPDM1 Analog Input", "IN1R", "IN1R PGA" }, + + { "AUXPDM2 Analog Input", "IN1L", "IN1L PGA" }, + { "AUXPDM2 Analog Input", "IN1R", "IN1R PGA" }, + + { "AUXPDM1 Input", "Analog", "AUXPDM1 Analog Input" }, + { "AUXPDM1 Input", "IN1 Digital", "IN1L PGA" }, + { "AUXPDM1 Input", "IN1 Digital", "IN1R PGA" }, + { "AUXPDM1 Input", "IN2 Digital", "IN2L PGA" }, + { "AUXPDM1 Input", "IN2 Digital", "IN2R PGA" }, + + { "AUXPDM2 Input", "Analog", "AUXPDM2 Analog Input" }, + { "AUXPDM2 Input", "IN1 Digital", "IN1L PGA" }, + { "AUXPDM2 Input", "IN1 Digital", "IN1R PGA" }, + { "AUXPDM2 Input", "IN2 Digital", "IN2L PGA" }, + { "AUXPDM2 Input", "IN2 Digital", "IN2R PGA" }, + + { "AUXPDM1 Output", "Switch", "AUXPDM1 Input" }, + { "AUXPDM1_CLK", NULL, "AUXPDM1 Output" }, + { "AUXPDM1_DOUT", NULL, "AUXPDM1 Output" }, + + { "AUXPDM2 Output", "Switch", "AUXPDM2 Input" }, + { "AUXPDM2_CLK", NULL, "AUXPDM2 Output" }, + { "AUXPDM2_DOUT", NULL, "AUXPDM2 Output" }, + + { "MICSUPP", NULL, "SYSCLK" }, + + { "DRC1 Signal Activity", NULL, "DRC1 Activity Output" }, + { "DRC2 Signal Activity", NULL, "DRC2 Activity Output" }, + { "DRC1 Activity Output", "Switch", "DRC1L" }, + { "DRC1 Activity Output", "Switch", "DRC1R" }, + { "DRC2 Activity Output", "Switch", "DRC2L" }, + { "DRC2 Activity Output", "Switch", "DRC2R" }, +}; + +static struct snd_soc_dai_driver cs48l32_dai[] = { + { + .name = "cs48l32-asp1", + .id = 1, + .base = CS48L32_ASP1_ENABLES1, + .playback = { + .stream_name = "ASP1 Playback", + .channels_min = 1, + .channels_max = 8, + .rates = CS48L32_RATES, + .formats = CS48L32_FORMATS, + }, + .capture = { + .stream_name = "ASP1 Capture", + .channels_min = 1, + .channels_max = 8, + .rates = CS48L32_RATES, + .formats = CS48L32_FORMATS, + }, + .ops = &cs48l32_dai_ops, + .symmetric_rate = 1, + .symmetric_sample_bits = 1, + }, + { + .name = "cs48l32-asp2", + .id = 2, + .base = CS48L32_ASP2_ENABLES1, + .playback = { + .stream_name = "ASP2 Playback", + .channels_min = 1, + .channels_max = 4, + .rates = CS48L32_RATES, + .formats = CS48L32_FORMATS, + }, + .capture = { + .stream_name = "ASP2 Capture", + .channels_min = 1, + .channels_max = 4, + .rates = CS48L32_RATES, + .formats = CS48L32_FORMATS, + }, + .ops = &cs48l32_dai_ops, + .symmetric_rate = 1, + .symmetric_sample_bits = 1, + }, + { + .name = "cs48l32-cpu-trace", + .id = 3, + .capture = { + .stream_name = "Audio Trace CPU", + .channels_min = 1, + .channels_max = 8, + .rates = CS48L32_RATES, + .formats = CS48L32_FORMATS, + }, + .compress_new = &snd_soc_new_compress, + }, + { + .name = "cs48l32-dsp-trace", + .id = 4, + .capture = { + .stream_name = "Audio Trace DSP", + .channels_min = 1, + .channels_max = 8, + .rates = CS48L32_RATES, + .formats = CS48L32_FORMATS, + }, + }, + { + .name = "cs48l32-cpu-voicectrl", + .id = 5, + .capture = { + .stream_name = "Voice Ctrl CPU", + .channels_min = 1, + .channels_max = 8, + .rates = CS48L32_RATES, + .formats = CS48L32_FORMATS, + }, + .compress_new = &snd_soc_new_compress, + }, + { + .name = "cs48l32-dsp-voicectrl", + .id = 6, + .capture = { + .stream_name = "Voice Ctrl DSP", + .channels_min = 1, + .channels_max = 8, + .rates = CS48L32_RATES, + .formats = CS48L32_FORMATS, + }, + }, +}; + +static int cs48l32_compr_open(struct snd_soc_component *component, + struct snd_compr_stream *stream) +{ + struct snd_soc_pcm_runtime *rtd = stream->private_data; + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + + if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs48l32-dsp-trace") && + strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs48l32-dsp-voicectrl")) { + dev_err(cs48l32->dev, "No suitable compressed stream for DAI '%s'\n", + asoc_rtd_to_codec(rtd, 0)->name); + return -EINVAL; + } + + return wm_adsp_compr_open(&cs48l32->dsp, stream); +} + +static int cs48l32_component_probe(struct snd_soc_component *component) +{ + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + int ret; + + snd_soc_component_init_regmap(component, cs48l32->mfd->regmap); + cs48l32->mfd->dapm = snd_soc_component_get_dapm(component); + + ret = cs48l32_init_inputs(component); + if (ret) + return ret; + + ret = cs48l32_init_eq(cs48l32); + if (ret) + return ret; + + wm_adsp2_component_probe(&cs48l32->dsp, component); + + return 0; +} + +static void cs48l32_component_remove(struct snd_soc_component *component) +{ + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + + wm_adsp2_component_remove(&cs48l32->dsp, component); + cs48l32->mfd->dapm = NULL; +} + +static int cs48l32_set_fll(struct snd_soc_component *component, int fll_id, + int source, unsigned int fref, unsigned int fout) +{ + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + + switch (fll_id) { + case CS48L32_FLL1_REFCLK: + break; + default: + return -EINVAL; + } + + return cs48l32_fllhj_set_refclk(&cs48l32->fll, source, fref, fout); +} + +static const struct snd_compress_ops cs48l32_compress_ops = { + .open = &cs48l32_compr_open, + .free = &wm_adsp_compr_free, + .set_params = &wm_adsp_compr_set_params, + .get_caps = &wm_adsp_compr_get_caps, + .trigger = &wm_adsp_compr_trigger, + .pointer = &wm_adsp_compr_pointer, + .copy = &wm_adsp_compr_copy, +}; + +static const struct snd_soc_component_driver soc_component_dev_cs48l32 = { + .probe = &cs48l32_component_probe, + .remove = &cs48l32_component_remove, + .set_sysclk = &cs48l32_set_sysclk, + .set_pll = &cs48l32_set_fll, + .name = "cs48l32-codec", + .compress_ops = &cs48l32_compress_ops, + .controls = cs48l32_snd_controls, + .num_controls = ARRAY_SIZE(cs48l32_snd_controls), + .dapm_widgets = cs48l32_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(cs48l32_dapm_widgets), + .dapm_routes = cs48l32_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(cs48l32_dapm_routes), + .use_pmdown_time = 1, + .endianness = 1, +}; + +static const struct { + int id; + bool wake_source; + const char * const name; + irq_handler_t handler; +} cs48l32_interrupts[] = { + { CS48L32_IRQ_US1_ACT_DET_RISE, false, "US1 activity", cs48l32_us1_activity }, + { CS48L32_IRQ_US2_ACT_DET_RISE, false, "US2 activity", cs48l32_us2_activity }, + { CS48L32_IRQ_DSP1_IRQ0, true, "DSP1 Buffer IRQ", cs48l32_dsp1_irq }, + { CS48L32_IRQ_DSP1_MPU_ERR, false, "DSP1 MPU", wm_halo_bus_error }, + { CS48L32_IRQ_DSP1_WDT_EXPIRE, false, "DSP1 WDT", wm_halo_wdt_expire }, +}; + +static void cs48l32_free_interrupts(struct cs48l32 *cs48l32, int num) +{ + for (--num; num >= 0; --num) { + cs48l32_free_irq(cs48l32->mfd, cs48l32_interrupts[num].id, cs48l32); + if (cs48l32_interrupts[num].wake_source) + cs48l32_set_irq_wake(cs48l32->mfd, cs48l32_interrupts[num].id, 0); + } +} + +static int cs48l32_request_interrupts(struct cs48l32 *cs48l32) +{ + int i, ret; + + for (i = 0; i < ARRAY_SIZE(cs48l32_interrupts); ++i) { + ret = cs48l32_request_irq(cs48l32->mfd, + cs48l32_interrupts[i].id, + cs48l32_interrupts[i].name, + cs48l32_interrupts[i].handler, + cs48l32); + if (ret != 0) + goto err; + + if (cs48l32_interrupts[i].wake_source) { + ret = cs48l32_set_irq_wake(cs48l32->mfd, cs48l32_interrupts[i].id, 1); + if (ret) + dev_warn(cs48l32->dev, "Failed to set %s wake: %d\n", + cs48l32_interrupts[i].name, ret); + } + } + + return 0; +err: + dev_err_probe(cs48l32->dev, ret, "Failed to get %s IRQ\n", cs48l32_interrupts[i].name); + cs48l32_free_interrupts(cs48l32, i); + + return ret; +} + +static int cs48l32_probe(struct platform_device *pdev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(pdev->dev.parent); + struct cs48l32 *cs48l32; + struct wm_adsp *dsp; + int i, ret; + + BUILD_BUG_ON(offsetof(struct cs48l32, dsp) != 0); + BUILD_BUG_ON(ARRAY_SIZE(cs48l32_dai) > CS48L32_MAX_DAI); + + /* quick exit if irqchip driver hasn't completed probe */ + if (!mfd->irq_dev) { + dev_dbg(&pdev->dev, "irqchip driver not ready\n"); + return -EPROBE_DEFER; + } + + cs48l32 = devm_kzalloc(&pdev->dev, sizeof(struct cs48l32), GFP_KERNEL); + if (!cs48l32) + return -ENOMEM; + + platform_set_drvdata(pdev, cs48l32); + pdev->dev.of_node = of_node_get(mfd->dev->of_node); + + cs48l32->mfd = mfd; + cs48l32->dev = &pdev->dev; + cs48l32->max_analogue_inputs = 1; + cs48l32->max_pdm_sup = 2; + cs48l32->in_vu_reg = CS48L32_INPUT_CONTROL3; + + ret = cs48l32_core_init(cs48l32); + if (ret) + return ret; + + ret = cs48l32_request_interrupts(cs48l32); + if (ret) + goto err; + + dsp = &cs48l32->dsp; + + switch (mfd->part) { + case 0x31: + dsp->part = "cs48l31"; + break; + case 0x32: + dsp->part = "cs48l32"; + break; + case 0x33: + dsp->part = "cs48l33"; + break; + default: + ret = -EINVAL; + goto err; + } + + dsp->cs_dsp.num = 1; + dsp->cs_dsp.type = WMFW_HALO; + dsp->cs_dsp.rev = 0; + dsp->cs_dsp.dev = mfd->dev; + dsp->cs_dsp.regmap = mfd->regmap; + + dsp->cs_dsp.base = CS48L32_DSP1_CLOCK_FREQ; + dsp->cs_dsp.base_sysinfo = CS48L32_DSP1_SYS_INFO_ID; + + dsp->cs_dsp.mem = cs48l32_dsp1_regions; + dsp->cs_dsp.num_mems = ARRAY_SIZE(cs48l32_dsp1_regions); + dsp->pre_run = cs48l32_dsp_pre_run; + + ret = wm_halo_init(dsp); + if (ret != 0) + goto err; + + cs48l32->fll.cs48l32 = cs48l32; + cs48l32->fll.id = 1; + cs48l32->fll.base = CS48L32_FLL1_CONTROL1; + cs48l32->fll.sts_addr = CS48L32_IRQ1_STS_6; + cs48l32->fll.sts_mask = CS48L32_FLL1_LOCK_STS1_MASK; + cs48l32->fll.has_lp = 1; + cs48l32_init_fll(&cs48l32->fll); + + for (i = 0; i < ARRAY_SIZE(cs48l32_dai); i++) + cs48l32_init_dai(cs48l32, i); + + pm_runtime_enable(&pdev->dev); + pm_runtime_idle(&pdev->dev); + + ret = devm_snd_soc_register_component(&pdev->dev, + &soc_component_dev_cs48l32, + cs48l32_dai, + ARRAY_SIZE(cs48l32_dai)); + if (ret < 0) { + dev_err_probe(&pdev->dev, ret, "Failed to register component\n"); + goto err_dsp; + } + + return ret; +err_dsp: + wm_adsp2_remove(&cs48l32->dsp); +err: + cs48l32_core_destroy(cs48l32); + + return ret; +} + +static int cs48l32_remove(struct platform_device *pdev) +{ + struct cs48l32 *cs48l32 = platform_get_drvdata(pdev); + + pm_runtime_disable(&pdev->dev); + + cs48l32_free_interrupts(cs48l32, ARRAY_SIZE(cs48l32_interrupts)); + wm_adsp2_remove(&cs48l32->dsp); + + cs48l32_core_destroy(cs48l32); + + return 0; +} + +static struct platform_driver cs48l32_codec_driver = { + .driver = { + .name = "cs48l32-codec", + }, + .probe = &cs48l32_probe, + .remove = &cs48l32_remove, +}; + +module_platform_driver(cs48l32_codec_driver); + +MODULE_SOFTDEP("pre: cs48l32 irq-cirrus-cs48l32 arizona-micsupp"); +MODULE_DESCRIPTION("ASoC CS48L32 driver"); +MODULE_AUTHOR("Stuart Henderson <stuarth@opensource.cirrus.com>"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:cs48l32-codec"); diff --git a/sound/soc/codecs/cs48l32.h b/sound/soc/codecs/cs48l32.h new file mode 100644 index 000000000000..7cbd85077902 --- /dev/null +++ b/sound/soc/codecs/cs48l32.h @@ -0,0 +1,386 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Cirrus Logic CS48L32 codec core support + * + * Copyright (C) 2016-2018, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef ASOC_CS48L32_H +#define ASOC_CS48L32_H + +#include <linux/mfd/cs48l32/core.h> +#include <sound/cs48l32.h> +#include <sound/soc.h> + +#include "wm_adsp.h" + +#define CS48L32_PDMCLK_SRC_IN1_PDMCLK 0x0 +#define CS48L32_PDMCLK_SRC_IN2_PDMCLK 0x1 +#define CS48L32_PDMCLK_SRC_IN3_PDMCLK 0x2 +#define CS48L32_PDMCLK_SRC_IN4_PDMCLK 0x3 +#define CS48L32_PDMCLK_SRC_AUXPDM1_CLK 0x8 +#define CS48L32_PDMCLK_SRC_AUXPDM2_CLK 0x9 + +#define CS48L32_MAX_DAI 12 +#define CS48L32_MAX_INPUT 4 +#define CS48L32_MAX_MUXED_IN_CHANNELS 4 +#define CS48L32_MAX_ASP 2 + +#define CS48L32_NUM_MIXER_INPUTS 58 + +#define CS48L32_EQ_BLOCK_SZ 60 +#define CS48L32_N_EQ_BLOCKS 4 + +#define CS48L32_DSP_N_RX_CHANNELS 8 +#define CS48L32_DSP_N_TX_CHANNELS 8 + +#define CS48L32_SAMPLE_RATE_ENUM_SIZE 17 + +#define CS48L32_MIXER_CONTROLS(name, base) \ + SOC_SINGLE_RANGE_TLV(name " Input 1 Volume", base, \ + CS48L32_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ + cs48l32_mixer_tlv), \ + SOC_SINGLE_RANGE_TLV(name " Input 2 Volume", base + 4, \ + CS48L32_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ + cs48l32_mixer_tlv), \ + SOC_SINGLE_RANGE_TLV(name " Input 3 Volume", base + 8, \ + CS48L32_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ + cs48l32_mixer_tlv), \ + SOC_SINGLE_RANGE_TLV(name " Input 4 Volume", base + 12, \ + CS48L32_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ + cs48l32_mixer_tlv) + +#define CS48L32_MUX_ENUM_DECL(name, reg) \ + SOC_VALUE_ENUM_SINGLE_DECL( \ + name, reg, 0, CS48L32_MIXER_SRC_MASK, \ + cs48l32_mixer_texts, cs48l32_mixer_values) + +#define CS48L32_MUX_CTL_DECL(name) \ + const struct snd_kcontrol_new name##_mux = SOC_DAPM_ENUM("Route", name##_enum) + +#define CS48L32_MUX_ENUMS(name, base_reg) \ + static CS48L32_MUX_ENUM_DECL(name##_enum, base_reg); \ + static CS48L32_MUX_CTL_DECL(name) + +#define CS48L32_MIXER_ENUMS(name, base_reg) \ + CS48L32_MUX_ENUMS(name##_in1, base_reg); \ + CS48L32_MUX_ENUMS(name##_in2, base_reg + 4); \ + CS48L32_MUX_ENUMS(name##_in3, base_reg + 8); \ + CS48L32_MUX_ENUMS(name##_in4, base_reg + 12) + +#define CS48L32_MUX(name, ctrl) SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl) + +#define CS48L32_MUX_WIDGETS(name, name_str) CS48L32_MUX(name_str " Input 1", &name##_mux) + +#define CS48L32_MIXER_WIDGETS(name, name_str) \ + CS48L32_MUX(name_str " Input 1", &name##_in1_mux), \ + CS48L32_MUX(name_str " Input 2", &name##_in2_mux), \ + CS48L32_MUX(name_str " Input 3", &name##_in3_mux), \ + CS48L32_MUX(name_str " Input 4", &name##_in4_mux), \ + SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0) + +#define CS48L32_MUX_ROUTES(widget, name) \ + { widget, NULL, name " Input 1" }, \ + CS48L32_MIXER_INPUT_ROUTES(name " Input 1") + +#define CS48L32_MIXER_ROUTES(widget, name) \ + { widget, NULL, name " Mixer" }, \ + { name " Mixer", NULL, name " Input 1" }, \ + { name " Mixer", NULL, name " Input 2" }, \ + { name " Mixer", NULL, name " Input 3" }, \ + { name " Mixer", NULL, name " Input 4" }, \ + CS48L32_MIXER_INPUT_ROUTES(name " Input 1"), \ + CS48L32_MIXER_INPUT_ROUTES(name " Input 2"), \ + CS48L32_MIXER_INPUT_ROUTES(name " Input 3"), \ + CS48L32_MIXER_INPUT_ROUTES(name " Input 4") + +#define CS48L32_DSP_ROUTES_1_8_SYSCLK(name) \ + { name, NULL, name " Preloader" }, \ + { name, NULL, "SYSCLK" }, \ + { name " Preload", NULL, name " Preloader" }, \ + CS48L32_MIXER_ROUTES(name, name "RX1"), \ + CS48L32_MIXER_ROUTES(name, name "RX2"), \ + CS48L32_MIXER_ROUTES(name, name "RX3"), \ + CS48L32_MIXER_ROUTES(name, name "RX4"), \ + CS48L32_MIXER_ROUTES(name, name "RX5"), \ + CS48L32_MIXER_ROUTES(name, name "RX6"), \ + CS48L32_MIXER_ROUTES(name, name "RX7"), \ + CS48L32_MIXER_ROUTES(name, name "RX8") \ + +#define CS48L32_DSP_ROUTES_1_8(name) \ + { name, NULL, "DSPCLK" }, \ + CS48L32_DSP_ROUTES_1_8_SYSCLK(name) \ + +#define CS48L32_RATE_CONTROL(name, domain) SOC_ENUM(name, cs48l32_sample_rate[(domain) - 1]) + +#define CS48L32_RATE_ENUM(name, enum) \ + SOC_ENUM_EXT(name, enum, snd_soc_get_enum_double, cs48l32_rate_put) + +#define CS48L32_DSP_RATE_CONTROL(name, num) \ + SOC_ENUM_EXT(name " Rate", cs48l32_dsp_rate_enum[num], \ + cs48l32_dsp_rate_get, cs48l32_dsp_rate_put) + +#define CS48L32_EQ_COEFF_CONTROL(xname, xreg, xbase, xshift) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = cs48l32_eq_coeff_info, .get = cs48l32_eq_coeff_get, \ + .put = cs48l32_eq_coeff_put, .private_value = \ + (unsigned long)&(struct cs48l32_eq_control) { .reg = xreg,\ + .shift = xshift, .block_base = xbase, .max = 65535 } } + +#define CS48L32_EQ_REG_NAME_PASTER(eq, band, type) \ + CS48L32_ ## eq ## _ ## band ## _ ## type + +#define CS48L32_EQ_BAND_COEFF_CONTROLS(name, band) \ + CS48L32_EQ_COEFF_CONTROL(#name " " #band " A", \ + CS48L32_EQ_REG_NAME_PASTER(name, band, COEFF1), \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ + 0), \ + CS48L32_EQ_COEFF_CONTROL(#name " " #band " B", \ + CS48L32_EQ_REG_NAME_PASTER(name, band, COEFF1), \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ + 16), \ + CS48L32_EQ_COEFF_CONTROL(#name " " #band " C", \ + CS48L32_EQ_REG_NAME_PASTER(name, band, COEFF2), \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ + 0), \ + CS48L32_EQ_COEFF_CONTROL(#name " " #band " PG", \ + CS48L32_EQ_REG_NAME_PASTER(name, band, PG), \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ + 0) + +#define CS48L32_EQ_COEFF_CONTROLS(name) \ + CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND1), \ + CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND2), \ + CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND3), \ + CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND4), \ + CS48L32_EQ_COEFF_CONTROL(#name " BAND5 A", \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND5, COEFF1), \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ + 0), \ + CS48L32_EQ_COEFF_CONTROL(#name " BAND5 B", \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND5, COEFF1), \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ + 16), \ + CS48L32_EQ_COEFF_CONTROL(#name " BAND5 PG", \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND5, PG), \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ + 0) + +#define CS48L32_LHPF_CONTROL(xname, xbase) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_bytes_info, .get = snd_soc_bytes_get, \ + .put = cs48l32_lhpf_coeff_put, .private_value = \ + ((unsigned long)&(struct soc_bytes) { .base = xbase, \ + .num_regs = 1 }) } + +/* these have a subseq number so they run after SYSCLK and DSPCLK widgets */ +#define CS48L32_DSP_FREQ_WIDGET_EV(name, num, event) \ + SND_SOC_DAPM_SUPPLY_S(name "FREQ", 100, SND_SOC_NOPM, num, 0, \ + event, SND_SOC_DAPM_POST_PMU) + +#define CS48L32_RATES SNDRV_PCM_RATE_KNOT + +#define CS48L32_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +struct cs48l32_dai_priv { + int clk; + struct snd_pcm_hw_constraint_list constraint; +}; + +struct cs48l32_dsp_power_reg_block { + unsigned int start; + unsigned int end; +}; + +struct cs48l32_dsp_power_regs { + const unsigned int *pwd; + unsigned int n_pwd; + const struct cs48l32_dsp_power_reg_block *ext; + unsigned int n_ext; +}; + +struct cs48l32; + +struct cs48l32_fll_cfg { + int n; + unsigned int theta; + unsigned int lambda; + int refdiv; + int fratio; + int gain; + int alt_gain; +}; + +struct cs48l32_fll { + struct cs48l32 *cs48l32; + int id; + unsigned int base; + + unsigned int sts_addr; + unsigned int sts_mask; + + unsigned int fout; + + int ref_src; + unsigned int ref_freq; + struct cs48l32_fll_cfg ref_cfg; + + unsigned int max_fref; + + unsigned int integer_only:1; + unsigned int has_lp:1; +}; + +struct cs48l32 { + struct wm_adsp dsp; + struct cs48l32_mfd *mfd; + struct device *dev; + int sysclk; + int dspclk; + struct cs48l32_dai_priv dai[CS48L32_MAX_DAI]; + struct cs48l32_fll fll; + + int max_analogue_inputs; + int max_pdm_sup; + int num_dmic_clksrc; + u32 max_channels_clocked[CS48L32_MAX_ASP]; + u32 pdm_sup[CS48L32_MAX_INPUT]; + u32 in_type[CS48L32_MAX_INPUT][CS48L32_MAX_MUXED_IN_CHANNELS]; + + unsigned int in_up_pending; + unsigned int in_vu_reg; + + struct mutex rate_lock; + + u8 dsp_dma_rates[CS48L32_DSP_N_RX_CHANNELS + CS48L32_DSP_N_TX_CHANNELS]; + + int tdm_width[CS48L32_MAX_ASP]; + int tdm_slots[CS48L32_MAX_ASP]; + + unsigned int eq_mode[CS48L32_N_EQ_BLOCKS]; + __be16 eq_coefficients[CS48L32_N_EQ_BLOCKS][CS48L32_EQ_BLOCK_SZ / 2]; + + const struct cs48l32_dsp_power_regs *dsp_power_regs; +}; + +struct cs48l32_enum { + struct soc_enum mixer_enum; + int val; +}; + +struct cs48l32_eq_control { + unsigned int reg; + unsigned int shift; + unsigned int block_base; + unsigned int max; +}; + +extern const char * const cs48l32_mixer_texts[CS48L32_NUM_MIXER_INPUTS]; +extern unsigned int cs48l32_mixer_values[CS48L32_NUM_MIXER_INPUTS]; + +extern const unsigned int cs48l32_ana_tlv[]; +extern const unsigned int cs48l32_eq_tlv[]; +extern const unsigned int cs48l32_digital_tlv[]; +extern const unsigned int cs48l32_noise_tlv[]; +extern const unsigned int cs48l32_mixer_tlv[]; +extern const unsigned int cs48l32_us_tlv[]; + +int cs48l32_rate_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); + +extern const struct soc_enum cs48l32_sample_rate[]; + +extern const struct snd_kcontrol_new cs48l32_inmux[]; +extern const struct snd_kcontrol_new cs48l32_dmode_mux[]; + +extern const struct soc_enum cs48l32_us_freq[]; +extern const struct snd_kcontrol_new cs48l32_us_inmux[]; +extern const struct soc_enum cs48l32_us_output_rate[]; +extern const struct soc_enum cs48l32_us_det_lpf_cut[]; +extern const struct soc_enum cs48l32_us_det_dcy[]; +extern const struct snd_kcontrol_new cs48l32_us_switch[]; +extern const struct soc_enum cs48l32_us_det_thr[]; +extern const struct soc_enum cs48l32_us_det_num[]; +extern const struct soc_enum cs48l32_us_det_hold[]; + +extern const struct soc_enum cs48l32_in_vi_ramp; +extern const struct soc_enum cs48l32_in_vd_ramp; +extern const struct soc_enum cs48l32_in_hpf_cut_enum; +extern const struct soc_enum cs48l32_in_dmic_osr[]; + +irqreturn_t cs48l32_us1_activity(int irq, void *data); +irqreturn_t cs48l32_us2_activity(int irq, void *data); + +int cs48l32_in_rate_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +extern const struct soc_enum cs48l32_input_rate[]; +int cs48l32_low_power_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +extern const struct soc_enum noise_gen_rate; + +extern const struct soc_enum cs48l32_auxpdm1_freq; +extern const struct soc_enum cs48l32_auxpdm2_freq; +extern const struct snd_kcontrol_new cs48l32_auxpdm_inmux[]; +extern const struct snd_kcontrol_new cs48l32_auxpdm_analog_inmux[]; +extern const struct snd_kcontrol_new cs48l32_auxpdm_switch[]; + +extern const struct soc_enum cs48l32_isrc_fsl[]; +extern const struct soc_enum cs48l32_isrc_fsh[]; + +extern const struct soc_enum cs48l32_fx_rate; + +extern const struct soc_enum cs48l32_lhpf_mode[]; + +int cs48l32_lhpf_coeff_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +extern const struct soc_enum cs48l32_eq_mode[]; +int cs48l32_eq_mode_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int cs48l32_eq_mode_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int cs48l32_eq_coeff_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo); +int cs48l32_eq_coeff_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int cs48l32_eq_coeff_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); + +extern const struct snd_kcontrol_new cs48l32_drc_activity_output_mux[]; +extern const struct snd_kcontrol_new cs48l32_dsp_trigger_output_mux[]; +int cs48l32_dsp_rate_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int cs48l32_dsp_rate_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +extern const struct soc_enum cs48l32_dsp_rate_enum[]; + +int cs48l32_dsp_pre_run(struct wm_adsp *dsp); +int cs48l32_dsp_memory_enable(struct cs48l32 *priv, + const struct cs48l32_dsp_power_regs *regs); +void cs48l32_dsp_memory_disable(struct cs48l32 *priv, + const struct cs48l32_dsp_power_regs *regs); +int cs48l32_dsp_freq_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +irqreturn_t cs48l32_dsp1_irq(int irq, void *data); + +int cs48l32_set_sysclk(struct snd_soc_component *component, int clk_id, + int source, unsigned int freq, int dir); + +extern const struct snd_soc_dai_ops cs48l32_dai_ops; + +int cs48l32_sysclk_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event); +int cs48l32_in_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event); +int cs48l32_in_put_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int cs48l32_eq_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event); + +int cs48l32_fllhj_set_refclk(struct cs48l32_fll *fll, int source, + unsigned int fin, unsigned int fout); +int cs48l32_init_fll(struct cs48l32_fll *fll); +int cs48l32_init_inputs(struct snd_soc_component *component); +int cs48l32_init_dai(struct cs48l32 *priv, int dai); +int cs48l32_init_eq(struct cs48l32 *priv); +int cs48l32_core_init(struct cs48l32 *priv); +int cs48l32_core_destroy(struct cs48l32 *priv); + +#endif -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* [PATCH 12/12] ASoC: cs48l32: Add codec driver for Cirrus Logic CS48L31/32/33 @ 2022-11-09 16:53 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-09 16:53 UTC (permalink / raw) To: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio, Richard Fitzgerald From: Stuart Henderson <stuarth@opensource.cirrus.com> The CS48L32 is a high-performance low-power audio DSP for smartphones and other portable audio devices. The CS48L32 combines a programmable Halo Core DSP with a variety of power-efficient fixed-function audio processors. Signed-off-by: Piotr Stankiewicz <piotrs@opensource.cirrus.com> Signed-off-by: Stuart Henderson <stuarth@opensource.cirrus.com> Signed-off-by: Qi Zhou <qi.zhou@cirrus.com> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> --- MAINTAINERS | 4 + include/sound/cs48l32.h | 89 + sound/soc/codecs/Kconfig | 9 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/cs48l32-core.c | 2782 +++++++++++++++++++++++++++++++ sound/soc/codecs/cs48l32.c | 1211 ++++++++++++++ sound/soc/codecs/cs48l32.h | 386 +++++ 7 files changed, 4483 insertions(+) create mode 100644 include/sound/cs48l32.h create mode 100644 sound/soc/codecs/cs48l32-core.c create mode 100644 sound/soc/codecs/cs48l32.c create mode 100644 sound/soc/codecs/cs48l32.h diff --git a/MAINTAINERS b/MAINTAINERS index f52e9a6e290c..9d5ddb50f388 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5013,6 +5013,7 @@ F: Documentation/devicetree/bindings/mfd/cirrus,cs48l32.yaml F: Documentation/devicetree/bindings/mfd/cirrus,madera.yaml F: Documentation/devicetree/bindings/pinctrl/cirrus,cs48l32.yaml F: Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml +F: Documentation/devicetree/bindings/sound/cirrus,cs48l32.yaml F: Documentation/devicetree/bindings/sound/cirrus,madera.yaml F: drivers/gpio/gpio-madera* F: drivers/irqchip/irq-cirrus-cs48l32* @@ -5021,13 +5022,16 @@ F: drivers/mfd/cs47l* F: drivers/mfd/cs48l* F: drivers/mfd/madera* F: drivers/pinctrl/cirrus/* +F: include/dt-bindings/sound/cs48l32.h F: include/dt-bindings/sound/madera* F: include/linux/irqchip/irq-cirrus-cs48l32* F: include/linux/irqchip/irq-madera* F: include/linux/mfd/cs48l32/* F: include/linux/mfd/madera/* +F: include/sound/cs48l32.h F: include/sound/madera* F: sound/soc/codecs/cs47l* +F: sound/soc/codecs/cs48l32* F: sound/soc/codecs/madera* CISCO FCOE HBA DRIVER diff --git a/include/sound/cs48l32.h b/include/sound/cs48l32.h new file mode 100644 index 000000000000..3078bb520dae --- /dev/null +++ b/include/sound/cs48l32.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Cirrus Logic CS48L32 codec + * + * Copyright (C) 2016-2018, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef SOUND_CS48L32_H +#define SOUND_CS48L32_H + +#include <linux/mfd/cs48l32/core.h> +#include <linux/notifier.h> +#include <sound/soc-component.h> + +/* pll_id for snd_soc_component_set_pll() */ +#define CS48L32_FLL1_REFCLK 1 + +/* source for snd_soc_component_set_pll() */ +#define CS48L32_FLL_SRC_NONE -1 +#define CS48L32_FLL_SRC_MCLK1 0 +#define CS48L32_FLL_SRC_PDMCLK 5 +#define CS48L32_FLL_SRC_ASP1_BCLK 8 +#define CS48L32_FLL_SRC_ASP2_BCLK 9 +#define CS48L32_FLL_SRC_ASP1_FSYNC 12 +#define CS48L32_FLL_SRC_ASP2_FSYNC 13 + +/* clk_id for snd_soc_component_set_sysclk() and snd_soc_dai_set_sysclk() */ +#define CS48L32_CLK_SYSCLK_1 1 +#define CS48L32_CLK_SYSCLK_2 2 +#define CS48L32_CLK_SYSCLK_3 3 +#define CS48L32_CLK_SYSCLK_4 4 +#define CS48L32_CLK_DSPCLK 7 +#define CS48L32_CLK_OPCLK 9 +#define CS48L32_CLK_PDM_FLLCLK 13 + +/* source for snd_soc_component_set_sysclk() */ +#define CS48L32_CLK_SRC_MCLK1 0x0 +#define CS48L32_CLK_SRC_FLL1 0x4 +#define CS48L32_CLK_SRC_ASP1_BCLK 0x8 +#define CS48L32_CLK_SRC_ASP2_BCLK 0x9 + +/* Notifier events */ +#define CS48L32_NOTIFY_ULTRASONIC 0x1 + +/** + * struct cs48l32_us_notify_data - Ultrasonic event notification data + * @us_no: Index of ultrasonic block that reported the event. + * + * Data passed in an ultrasonic notification event callback. + */ +struct cs48l32_us_notify_data { + unsigned int us_no; +}; + +/** + * cs48l32_register_notifier() - Register notification event callback + * @component: ASoC component of the cs48l32 driver. + * @nb: Client struct notifier_block. + * + * Return: 0 on success else standard negative error code. + */ +static inline int cs48l32_register_notifier(struct snd_soc_component *component, + struct notifier_block *nb) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(component->dev->parent); + + return blocking_notifier_chain_register(&mfd->notifier, nb); +} + +/** + * cs48l32_unregister_notifier() - Unregister notification event callback + * @component: ASoC component of the cs48l32 driver. + * @nb: Client struct notifier_block. + * + * Unregister an event notifier callback that was registered by + * cs48l32_register_notifier(). + * + * Return: 0 on success else standard negative error code. + */ +static inline int cs48l32_unregister_notifier(struct snd_soc_component *component, + struct notifier_block *nb) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(component->dev->parent); + + return blocking_notifier_chain_unregister(&mfd->notifier, nb); +} + +#endif diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 7a13e750751a..aadbdf33b373 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -87,6 +87,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_CS47L85 imply SND_SOC_CS47L90 imply SND_SOC_CS47L92 + imply SND_SOC_CS48L32 imply SND_SOC_CS53L30 imply SND_SOC_CX20442 imply SND_SOC_CX2072X @@ -351,6 +352,7 @@ config SND_SOC_WM_ADSP select CS_DSP select SND_SOC_COMPRESS default y if SND_SOC_MADERA=y + default y if SND_SOC_CS48L32=y default y if SND_SOC_CS47L24=y default y if SND_SOC_WM5102=y default y if SND_SOC_WM5110=y @@ -358,6 +360,7 @@ config SND_SOC_WM_ADSP default y if SND_SOC_CS35L41_SPI=y default y if SND_SOC_CS35L41_I2C=y default m if SND_SOC_MADERA=m + default m if SND_SOC_CS48L32=m default m if SND_SOC_CS47L24=m default m if SND_SOC_WM5102=m default m if SND_SOC_WM5110=m @@ -816,6 +819,12 @@ config SND_SOC_CS47L92 tristate depends on MFD_CS47L92 +config SND_SOC_CS48L32 + tristate "Cirrus Logic CS48L32 CODEC" + depends on MFD_CS48L32 + help + Enable support for the Cirrus Logic CS48L32 codec. + # Cirrus Logic Quad-Channel ADC config SND_SOC_CS53L30 tristate "Cirrus Logic CS53L30 CODEC" diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 9170ee1447dd..2c59463d1085 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -89,6 +89,7 @@ snd-soc-cs47l35-objs := cs47l35.o snd-soc-cs47l85-objs := cs47l85.o snd-soc-cs47l90-objs := cs47l90.o snd-soc-cs47l92-objs := cs47l92.o +snd-soc-cs48l32-objs := cs48l32.o cs48l32-core.o snd-soc-cs53l30-objs := cs53l30.o snd-soc-cx20442-objs := cx20442.o snd-soc-cx2072x-objs := cx2072x.o @@ -449,6 +450,7 @@ obj-$(CONFIG_SND_SOC_CS47L35) += snd-soc-cs47l35.o obj-$(CONFIG_SND_SOC_CS47L85) += snd-soc-cs47l85.o obj-$(CONFIG_SND_SOC_CS47L90) += snd-soc-cs47l90.o obj-$(CONFIG_SND_SOC_CS47L92) += snd-soc-cs47l92.o +obj-$(CONFIG_SND_SOC_CS48L32) += snd-soc-cs48l32.o obj-$(CONFIG_SND_SOC_CS53L30) += snd-soc-cs53l30.o obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o obj-$(CONFIG_SND_SOC_CX2072X) += snd-soc-cx2072x.o diff --git a/sound/soc/codecs/cs48l32-core.c b/sound/soc/codecs/cs48l32-core.c new file mode 100644 index 000000000000..8daebbb0ea50 --- /dev/null +++ b/sound/soc/codecs/cs48l32-core.c @@ -0,0 +1,2782 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Cirrus Logic CS48L32 codec core support +// +// Copyright (C) 2016-2018, 2020, 2022 Cirrus Logic, Inc. and +// Cirrus Logic International Semiconductor Ltd. +// + +#include <dt-bindings/sound/cs48l32.h> +#include <linux/delay.h> +#include <linux/gcd.h> +#include <linux/mfd/cs48l32/core.h> +#include <linux/mfd/cs48l32/registers.h> +#include <linux/minmax.h> +#include <linux/module.h> +#include <linux/pm_runtime.h> +#include <linux/slab.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/tlv.h> + +#include "cs48l32.h" + +#define CS48L32_ASP_ENABLES1 0x00 +#define CS48L32_ASP_CONTROL1 0x04 +#define CS48L32_ASP_CONTROL2 0x08 +#define CS48L32_ASP_CONTROL3 0x0c +#define CS48L32_ASP_FRAME_CONTROL1 0x10 +#define CS48L32_ASP_FRAME_CONTROL2 0x14 +#define CS48L32_ASP_FRAME_CONTROL5 0x20 +#define CS48L32_ASP_FRAME_CONTROL6 0x24 +#define CS48L32_ASP_DATA_CONTROL1 0x30 +#define CS48L32_ASP_DATA_CONTROL5 0x40 + +#define CS48L32_SYSCLK_RATE_6MHZ 0 +#define CS48L32_SYSCLK_RATE_12MHZ 1 +#define CS48L32_SYSCLK_RATE_24MHZ 2 +#define CS48L32_SYSCLK_RATE_49MHZ 3 +#define CS48L32_SYSCLK_RATE_98MHZ 4 + +#define CS48L32_FLLHJ_INT_MAX_N 1023 +#define CS48L32_FLLHJ_INT_MIN_N 1 +#define CS48L32_FLLHJ_FRAC_MAX_N 255 +#define CS48L32_FLLHJ_FRAC_MIN_N 2 +#define CS48L32_FLLHJ_LP_INT_MODE_THRESH 100000 +#define CS48L32_FLLHJ_LOW_THRESH 192000 +#define CS48L32_FLLHJ_MID_THRESH 1152000 +#define CS48L32_FLLHJ_MAX_THRESH 13000000 +#define CS48L32_FLLHJ_LOW_GAINS 0x23f0 +#define CS48L32_FLLHJ_MID_GAINS 0x22f2 +#define CS48L32_FLLHJ_HIGH_GAINS 0x21f0 +#define CS48L32_FLL_MAX_FOUT 50000000 +#define CS48L32_FLL_MAX_REFDIV 8 + +#define CS48L32_FLL_CONTROL1_OFFS 0x00 +#define CS48L32_FLL_CONTROL2_OFFS 0x04 +#define CS48L32_FLL_CONTROL3_OFFS 0x08 +#define CS48L32_FLL_CONTROL4_OFFS 0x0c +#define CS48L32_FLL_CONTROL5_OFFS 0x10 +#define CS48L32_FLL_CONTROL6_OFFS 0x14 +#define CS48L32_FLL_DIGITAL_TEST2_OFFS 0x34 +#define CS48L32_FLL_GPIO_CLOCK_OFFS 0xa0 + +#define CS48L32_DSP_CLOCK_FREQ_OFFS 0x00000 + +#define CS48L32_ASP_FMT_DSP_MODE_A 0 +#define CS48L32_ASP_FMT_DSP_MODE_B 1 +#define CS48L32_ASP_FMT_I2S_MODE 2 +#define CS48L32_ASP_FMT_LEFT_JUSTIFIED_MODE 3 + +#define CS48L32_HALO_SAMPLE_RATE_RX1 0x00080 +#define CS48L32_HALO_SAMPLE_RATE_TX1 0x00280 +#define CS48L32_HALO_DSP_RATE_MASK 0x1f + +#define cs48l32_fll_err(_fll, fmt, ...) \ + dev_err(_fll->cs48l32->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) +#define cs48l32_fll_warn(_fll, fmt, ...) \ + dev_warn(_fll->cs48l32->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) +#define cs48l32_fll_dbg(_fll, fmt, ...) \ + dev_dbg(_fll->cs48l32->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) + +#define cs48l32_asp_err(_dai, fmt, ...) \ + dev_err(_dai->component->dev, "ASP%d: " fmt, _dai->id, ##__VA_ARGS__) +#define cs48l32_asp_warn(_dai, fmt, ...) \ + dev_warn(_dai->component->dev, "ASP%d: " fmt, _dai->id, ##__VA_ARGS__) +#define cs48l32_asp_dbg(_dai, fmt, ...) \ + dev_dbg(_dai->component->dev, "ASP%d: " fmt, _dai->id, ##__VA_ARGS__) + +const char * const cs48l32_mixer_texts[] = { + "None", + "Tone Generator 1", + "Tone Generator 2", + "Noise Generator", + "IN1L", + "IN1R", + "IN2L", + "IN2R", + "ASP1RX1", + "ASP1RX2", + "ASP1RX3", + "ASP1RX4", + "ASP1RX5", + "ASP1RX6", + "ASP1RX7", + "ASP1RX8", + "ASP2RX1", + "ASP2RX2", + "ASP2RX3", + "ASP2RX4", + "ISRC1INT1", + "ISRC1INT2", + "ISRC1INT3", + "ISRC1INT4", + "ISRC1DEC1", + "ISRC1DEC2", + "ISRC1DEC3", + "ISRC1DEC4", + "ISRC2INT1", + "ISRC2INT2", + "ISRC2DEC1", + "ISRC2DEC2", + "ISRC3INT1", + "ISRC3INT2", + "ISRC3DEC1", + "ISRC3DEC2", + "EQ1", + "EQ2", + "EQ3", + "EQ4", + "DRC1L", + "DRC1R", + "DRC2L", + "DRC2R", + "LHPF1", + "LHPF2", + "LHPF3", + "LHPF4", + "Ultrasonic 1", + "Ultrasonic 2", + "DSP1.1", + "DSP1.2", + "DSP1.3", + "DSP1.4", + "DSP1.5", + "DSP1.6", + "DSP1.7", + "DSP1.8", +}; + +unsigned int cs48l32_mixer_values[] = { + 0x000, /* Silence (mute) */ + 0x004, /* Tone generator 1 */ + 0x005, /* Tone generator 2 */ + 0x00C, /* Noise Generator */ + 0x010, /* IN1L signal path */ + 0x011, /* IN1R signal path */ + 0x012, /* IN2L signal path */ + 0x013, /* IN2R signal path */ + 0x020, /* ASP1 RX1 */ + 0x021, /* ASP1 RX2 */ + 0x022, /* ASP1 RX3 */ + 0x023, /* ASP1 RX4 */ + 0x024, /* ASP1 RX5 */ + 0x025, /* ASP1 RX6 */ + 0x026, /* ASP1 RX7 */ + 0x027, /* ASP1 RX8 */ + 0x030, /* ASP2 RX1 */ + 0x031, /* ASP2 RX2 */ + 0x032, /* ASP2 RX3 */ + 0x033, /* ASP2 RX4 */ + 0x098, /* ISRC1 INT1 */ + 0x099, /* ISRC1 INT2 */ + 0x09a, /* ISRC1 INT3 */ + 0x09b, /* ISRC1 INT4 */ + 0x09C, /* ISRC1 DEC1 */ + 0x09D, /* ISRC1 DEC2 */ + 0x09e, /* ISRC1 DEC3 */ + 0x09f, /* ISRC1 DEC4 */ + 0x0A0, /* ISRC2 INT1 */ + 0x0A1, /* ISRC2 INT2 */ + 0x0A4, /* ISRC2 DEC1 */ + 0x0A5, /* ISRC2 DEC2 */ + 0x0A8, /* ISRC3 INT1 */ + 0x0A9, /* ISRC3 INT2 */ + 0x0AC, /* ISRC3 DEC1 */ + 0x0AD, /* ISRC3 DEC2 */ + 0x0B8, /* EQ1 */ + 0x0B9, /* EQ2 */ + 0x0BA, /* EQ3 */ + 0x0BB, /* EQ4 */ + 0x0C0, /* DRC1 Left */ + 0x0C1, /* DRC1 Right */ + 0x0C2, /* DRC2 Left */ + 0x0C3, /* DRC2 Right */ + 0x0C8, /* LHPF1 */ + 0x0C9, /* LHPF2 */ + 0x0CA, /* LHPF3 */ + 0x0CB, /* LHPF4 */ + 0x0D8, /* Ultrasonic 1 */ + 0x0D9, /* Ultrasonic 2 */ + 0x100, /* DSP1 channel 1 */ + 0x101, /* DSP1 channel 2 */ + 0x102, /* DSP1 channel 3 */ + 0x103, /* DSP1 channel 4 */ + 0x104, /* DSP1 channel 5 */ + 0x105, /* DSP1 channel 6 */ + 0x106, /* DSP1 channel 7 */ + 0x107, /* DSP1 channel 8 */ +}; + +const DECLARE_TLV_DB_SCALE(cs48l32_ana_tlv, 0, 100, 0); +const DECLARE_TLV_DB_SCALE(cs48l32_eq_tlv, -1200, 100, 0); +const DECLARE_TLV_DB_SCALE(cs48l32_digital_tlv, -6400, 50, 0); +const DECLARE_TLV_DB_SCALE(cs48l32_noise_tlv, -10800, 600, 0); +const DECLARE_TLV_DB_SCALE(cs48l32_mixer_tlv, -3200, 100, 0); +const DECLARE_TLV_DB_SCALE(cs48l32_us_tlv, 0, 600, 0); + +static void cs48l32_spin_sysclk(struct cs48l32 *cs48l32) +{ + struct cs48l32_mfd *mfd = cs48l32->mfd; + unsigned int val; + int ret, i; + + /* Skip this if the chip is down */ + if (pm_runtime_suspended(mfd->dev)) + return; + + /* + * Just read a register a few times to ensure the internal + * oscillator sends out a some clocks. + */ + for (i = 0; i < 4; i++) { + ret = regmap_read(mfd->regmap, CS48L32_DEVID, &val); + if (ret) + dev_err(cs48l32->dev, "%s Failed to read register: %d (%d)\n", + __func__, ret, i); + } + + udelay(300); +} + +static const char * const cs48l32_rate_text[] = { + "Sample Rate 1", + "Sample Rate 2", + "Sample Rate 3", + "Sample Rate 4", +}; + +static const unsigned int cs48l32_rate_val[] = { + 0x0, 0x1, 0x2, 0x3, +}; + +int cs48l32_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + int ret; + + /* Prevent any mixer mux changes while we do this */ + mutex_lock(&cs48l32->rate_lock); + + /* The write must be guarded by a number of SYSCLK cycles */ + cs48l32_spin_sysclk(cs48l32); + ret = snd_soc_put_enum_double(kcontrol, ucontrol); + cs48l32_spin_sysclk(cs48l32); + + mutex_unlock(&cs48l32->rate_lock); + + return ret; +} + +static const char * const cs48l32_sample_rate_text[] = { + "12kHz", + "24kHz", + "48kHz", + "96kHz", + "192kHz", + "384kHz", + "768kHz", + "11.025kHz", + "22.05kHz", + "44.1kHz", + "88.2kHz", + "176.4kHz", + "352.8kHz", + "705.6kHz", + "8kHz", + "16kHz", + "32kHz", +}; + +static const unsigned int cs48l32_sample_rate_val[] = { + 0x01, /* 12kHz */ + 0x02, /* 24kHz */ + 0x03, /* 48kHz */ + 0x04, /* 96kHz */ + 0x05, /* 192kHz */ + 0x06, /* 384kHz */ + 0x07, /* 768kHz */ + 0x09, /* 11.025kHz */ + 0x0a, /* 22.05kHz */ + 0x0b, /* 44.1kHz */ + 0x0c, /* 88.2kHz */ + 0x0d, /* 176.4kHz */ + 0x0e, /* 352.8kHz */ + 0x0f, /* 705.6kHz */ + 0x11, /* 8kHz */ + 0x12, /* 16kHz */ + 0x13, /* 32kHz */ +}; + +const struct soc_enum cs48l32_sample_rate[] = { + SOC_VALUE_ENUM_SINGLE(CS48L32_SAMPLE_RATE1, + CS48L32_SAMPLE_RATE_1_SHIFT, + CS48L32_SAMPLE_RATE_1_MASK >> CS48L32_SAMPLE_RATE_1_SHIFT, + CS48L32_SAMPLE_RATE_ENUM_SIZE, + cs48l32_sample_rate_text, + cs48l32_sample_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_SAMPLE_RATE2, + CS48L32_SAMPLE_RATE_1_SHIFT, + CS48L32_SAMPLE_RATE_1_MASK >> CS48L32_SAMPLE_RATE_1_SHIFT, + CS48L32_SAMPLE_RATE_ENUM_SIZE, + cs48l32_sample_rate_text, + cs48l32_sample_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_SAMPLE_RATE3, + CS48L32_SAMPLE_RATE_1_SHIFT, + CS48L32_SAMPLE_RATE_1_MASK >> CS48L32_SAMPLE_RATE_1_SHIFT, + CS48L32_SAMPLE_RATE_ENUM_SIZE, + cs48l32_sample_rate_text, + cs48l32_sample_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_SAMPLE_RATE4, + CS48L32_SAMPLE_RATE_1_SHIFT, + CS48L32_SAMPLE_RATE_1_MASK >> CS48L32_SAMPLE_RATE_1_SHIFT, + CS48L32_SAMPLE_RATE_ENUM_SIZE, + cs48l32_sample_rate_text, + cs48l32_sample_rate_val), +}; + +static int cs48l32_inmux_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol); + struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; + unsigned int mux, src_val, in_type; + int ret; + + mux = ucontrol->value.enumerated.item[0]; + if (mux > 1) + return -EINVAL; + + switch (e->reg) { + case CS48L32_IN1L_CONTROL1: + in_type = cs48l32->in_type[0][2 * mux]; + break; + case CS48L32_IN1R_CONTROL1: + in_type = cs48l32->in_type[0][1 + (2 * mux)]; + break; + case CS48L32_IN2L_CONTROL1: + in_type = cs48l32->in_type[1][2 * mux]; + break; + case CS48L32_IN2R_CONTROL1: + in_type = cs48l32->in_type[1][1 + (2 * mux)]; + break; + default: + return -EINVAL; + } + + src_val = mux << e->shift_l; + + if (in_type == CS48L32_IN_TYPE_SE) + src_val |= 1 << CS48L32_INx_SRC_SHIFT; + + dev_dbg(cs48l32->dev, "mux=%u reg=0x%x in_type=0x%x val=0x%x\n", + mux, e->reg, in_type, src_val); + + ret = snd_soc_component_update_bits(dapm->component, + e->reg, + CS48L32_INx_SRC_MASK, + src_val); + if (ret > 0) + snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL); + + return ret; +} + +static const char * const cs48l32_inmux_texts[] = { + "Analog 1", "Analog 2", +}; + +static SOC_ENUM_SINGLE_DECL(cs48l32_in1muxl_enum, + CS48L32_IN1L_CONTROL1, + CS48L32_INx_SRC_SHIFT + 1, + cs48l32_inmux_texts); + +static SOC_ENUM_SINGLE_DECL(cs48l32_in1muxr_enum, + CS48L32_IN1R_CONTROL1, + CS48L32_INx_SRC_SHIFT + 1, + cs48l32_inmux_texts); + +static SOC_ENUM_SINGLE_DECL(cs48l32_in2muxl_enum, + CS48L32_IN2L_CONTROL1, + CS48L32_INx_SRC_SHIFT + 1, + cs48l32_inmux_texts); + +static SOC_ENUM_SINGLE_DECL(cs48l32_in2muxr_enum, + CS48L32_IN2R_CONTROL1, + CS48L32_INx_SRC_SHIFT + 1, + cs48l32_inmux_texts); + +const struct snd_kcontrol_new cs48l32_inmux[] = { + SOC_DAPM_ENUM_EXT("IN1L Mux", cs48l32_in1muxl_enum, + snd_soc_dapm_get_enum_double, cs48l32_inmux_put), + SOC_DAPM_ENUM_EXT("IN1R Mux", cs48l32_in1muxr_enum, + snd_soc_dapm_get_enum_double, cs48l32_inmux_put), + SOC_DAPM_ENUM_EXT("IN2L Mux", cs48l32_in2muxl_enum, + snd_soc_dapm_get_enum_double, cs48l32_inmux_put), + SOC_DAPM_ENUM_EXT("IN2R Mux", cs48l32_in2muxr_enum, + snd_soc_dapm_get_enum_double, cs48l32_inmux_put), +}; + +static const char * const cs48l32_dmode_texts[] = { + "Analog", "Digital", +}; + +static int cs48l32_dmode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol); + struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); + struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; + unsigned int mode; + int ret, result; + + mode = ucontrol->value.enumerated.item[0]; + switch (mode) { + case 0: + ret = snd_soc_component_update_bits(component, + CS48L32_ADC1L_ANA_CONTROL1, + CS48L32_ADC1x_INT_ENA_FRC_MASK, + CS48L32_ADC1x_INT_ENA_FRC_MASK); + if (ret < 0) { + dev_err(component->dev, + "Failed to set ADC1L_INT_ENA_FRC: %d\n", ret); + return ret; + } + + ret = snd_soc_component_update_bits(component, + CS48L32_ADC1R_ANA_CONTROL1, + CS48L32_ADC1x_INT_ENA_FRC_MASK, + CS48L32_ADC1x_INT_ENA_FRC_MASK); + if (ret < 0) { + dev_err(component->dev, + "Failed to set ADC1R_INT_ENA_FRC: %d\n", ret); + return ret; + } + + result = snd_soc_component_update_bits(component, + e->reg, + BIT(CS48L32_IN1_MODE_SHIFT), + 0); + if (result < 0) { + dev_err(component->dev, "Failed to set input mode: %d\n", result); + return result; + } + + usleep_range(200, 300); + + ret = snd_soc_component_update_bits(component, + CS48L32_ADC1L_ANA_CONTROL1, + CS48L32_ADC1x_INT_ENA_FRC_MASK, + 0); + if (ret < 0) { + dev_err(component->dev, + "Failed to clear ADC1L_INT_ENA_FRC: %d\n", ret); + return ret; + } + + ret = snd_soc_component_update_bits(component, + CS48L32_ADC1R_ANA_CONTROL1, + CS48L32_ADC1x_INT_ENA_FRC_MASK, + 0); + if (ret < 0) { + dev_err(component->dev, + "Failed to clear ADC1R_INT_ENA_FRC: %d\n", ret); + return ret; + } + + if (result > 0) + snd_soc_dapm_mux_update_power(dapm, kcontrol, mode, e, NULL); + + return result; + case 1: + return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); + default: + return -EINVAL; + } +} + +static SOC_ENUM_SINGLE_DECL(cs48l32_in1dmode_enum, + CS48L32_INPUT1_CONTROL1, + CS48L32_IN1_MODE_SHIFT, + cs48l32_dmode_texts); + +const struct snd_kcontrol_new cs48l32_dmode_mux[] = { + SOC_DAPM_ENUM_EXT("IN1 Mode", cs48l32_in1dmode_enum, + snd_soc_dapm_get_enum_double, cs48l32_dmode_put), +}; + +static const char * const cs48l32_in_texts[] = { + "IN1L", "IN1R", "IN2L", "IN2R", +}; + +static const char * const cs48l32_us_freq_texts[] = { + "24.5-40.5kHz", "18-22kHz", "16-24kHz", "20-28kHz", +}; + +static const unsigned int cs48l32_us_freq_val[] = { + 0x2, 0x3, +}; + +const struct soc_enum cs48l32_us_freq[] = { + SOC_VALUE_ENUM_SINGLE(CS48L32_US1_CONTROL, + CS48L32_US1_FREQ_SHIFT, + CS48L32_US1_FREQ_MASK >> CS48L32_US1_FREQ_SHIFT, + ARRAY_SIZE(cs48l32_us_freq_val), + &cs48l32_us_freq_texts[2], + cs48l32_us_freq_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_US2_CONTROL, + CS48L32_US1_FREQ_SHIFT, + CS48L32_US1_FREQ_MASK >> CS48L32_US1_FREQ_SHIFT, + ARRAY_SIZE(cs48l32_us_freq_val), + &cs48l32_us_freq_texts[2], + cs48l32_us_freq_val), +}; + +static const unsigned int cs48l32_us_in_val[] = { + 0x0, 0x1, 0x2, 0x3, +}; + +static const struct soc_enum cs48l32_us_inmux_enum[] = { + SOC_VALUE_ENUM_SINGLE(CS48L32_US1_CONTROL, + CS48L32_US1_SRC_SHIFT, + CS48L32_US1_SRC_MASK >> CS48L32_US1_SRC_SHIFT, + ARRAY_SIZE(cs48l32_us_in_val), + cs48l32_in_texts, + cs48l32_us_in_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_US2_CONTROL, + CS48L32_US1_SRC_SHIFT, + CS48L32_US1_SRC_MASK >> CS48L32_US1_SRC_SHIFT, + ARRAY_SIZE(cs48l32_us_in_val), + cs48l32_in_texts, + cs48l32_us_in_val), +}; + +const struct snd_kcontrol_new cs48l32_us_inmux[] = { + SOC_DAPM_ENUM("Ultrasonic 1 Input", cs48l32_us_inmux_enum[0]), + SOC_DAPM_ENUM("Ultrasonic 2 Input", cs48l32_us_inmux_enum[1]), +}; + +static const char * const cs48l32_us_det_thr_texts[] = { + "-6dB", "-9dB", "-12dB", "-15dB", "-18dB", "-21dB", "-24dB", "-27dB", +}; + +const struct soc_enum cs48l32_us_det_thr[] = { + SOC_ENUM_SINGLE(CS48L32_US1_DET_CONTROL, + CS48L32_US1_DET_THR_SHIFT, + ARRAY_SIZE(cs48l32_us_det_thr_texts), + cs48l32_us_det_thr_texts), + SOC_ENUM_SINGLE(CS48L32_US2_DET_CONTROL, + CS48L32_US1_DET_THR_SHIFT, + ARRAY_SIZE(cs48l32_us_det_thr_texts), + cs48l32_us_det_thr_texts), +}; + +static const char * const cs48l32_us_det_num_texts[] = { + "1 Sample", + "2 Samples", + "4 Samples", + "8 Samples", + "16 Samples", + "32 Samples", + "64 Samples", + "128 Samples", + "256 Samples", + "512 Samples", + "1024 Samples", + "2048 Samples", + "4096 Samples", + "8192 Samples", + "16384 Samples", + "32768 Samples", +}; + +const struct soc_enum cs48l32_us_det_num[] = { + SOC_ENUM_SINGLE(CS48L32_US1_DET_CONTROL, + CS48L32_US1_DET_NUM_SHIFT, + ARRAY_SIZE(cs48l32_us_det_num_texts), + cs48l32_us_det_num_texts), + SOC_ENUM_SINGLE(CS48L32_US2_DET_CONTROL, + CS48L32_US1_DET_NUM_SHIFT, + ARRAY_SIZE(cs48l32_us_det_num_texts), + cs48l32_us_det_num_texts), +}; + +static const char * const cs48l32_us_det_hold_texts[] = { + "0 Samples", + "31 Samples", + "63 Samples", + "127 Samples", + "255 Samples", + "511 Samples", + "1023 Samples", + "2047 Samples", + "4095 Samples", + "8191 Samples", + "16383 Samples", + "32767 Samples", + "65535 Samples", + "131071 Samples", + "262143 Samples", + "524287 Samples", +}; + +const struct soc_enum cs48l32_us_det_hold[] = { + SOC_ENUM_SINGLE(CS48L32_US1_DET_CONTROL, + CS48L32_US1_DET_HOLD_SHIFT, + ARRAY_SIZE(cs48l32_us_det_hold_texts), + cs48l32_us_det_hold_texts), + SOC_ENUM_SINGLE(CS48L32_US2_DET_CONTROL, + CS48L32_US1_DET_HOLD_SHIFT, + ARRAY_SIZE(cs48l32_us_det_hold_texts), + cs48l32_us_det_hold_texts), +}; + +const struct soc_enum cs48l32_us_output_rate[] = { + SOC_VALUE_ENUM_SINGLE(CS48L32_US1_CONTROL, + CS48L32_US1_RATE_SHIFT, + CS48L32_US1_RATE_MASK >> CS48L32_US1_RATE_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_US2_CONTROL, + CS48L32_US1_RATE_SHIFT, + CS48L32_US1_RATE_MASK >> CS48L32_US1_RATE_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), +}; + +static const char * const cs48l32_us_det_lpf_cut_texts[] = { + "1722Hz", "833Hz", "408Hz", "203Hz", +}; + +const struct soc_enum cs48l32_us_det_lpf_cut[] = { + SOC_ENUM_SINGLE(CS48L32_US1_DET_CONTROL, + CS48L32_US1_DET_LPF_CUT_SHIFT, + ARRAY_SIZE(cs48l32_us_det_lpf_cut_texts), + cs48l32_us_det_lpf_cut_texts), + SOC_ENUM_SINGLE(CS48L32_US2_DET_CONTROL, + CS48L32_US1_DET_LPF_CUT_SHIFT, + ARRAY_SIZE(cs48l32_us_det_lpf_cut_texts), + cs48l32_us_det_lpf_cut_texts), +}; + +static const char * const cs48l32_us_det_dcy_texts[] = { + "0 ms", "0.79 ms", "1.58 ms", "3.16 ms", "6.33 ms", "12.67 ms", + "25.34 ms", "50.69 ms", +}; + +const struct soc_enum cs48l32_us_det_dcy[] = { + SOC_ENUM_SINGLE(CS48L32_US1_DET_CONTROL, + CS48L32_US1_DET_DCY_SHIFT, + ARRAY_SIZE(cs48l32_us_det_dcy_texts), + cs48l32_us_det_dcy_texts), + SOC_ENUM_SINGLE(CS48L32_US2_DET_CONTROL, + CS48L32_US1_DET_DCY_SHIFT, + ARRAY_SIZE(cs48l32_us_det_dcy_texts), + cs48l32_us_det_dcy_texts), +}; + +const struct snd_kcontrol_new cs48l32_us_switch[] = { + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), +}; + +static const char * const cs48l32_vol_ramp_text[] = { + "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB", + "16ms/6dB", "32ms/6dB", +}; + +irqreturn_t cs48l32_us1_activity(int irq, void *data) +{ + struct cs48l32 *cs48l32 = data; + struct cs48l32_us_notify_data us_data; + + us_data.us_no = 1; + cs48l32_call_notifiers(cs48l32->mfd, CS48L32_NOTIFY_ULTRASONIC, &us_data); + + return IRQ_HANDLED; +} + +irqreturn_t cs48l32_us2_activity(int irq, void *data) +{ + struct cs48l32 *cs48l32 = data; + struct cs48l32_us_notify_data us_data; + + us_data.us_no = 2; + cs48l32_call_notifiers(cs48l32->mfd, CS48L32_NOTIFY_ULTRASONIC, &us_data); + + return IRQ_HANDLED; +} + +SOC_ENUM_SINGLE_DECL(cs48l32_in_vd_ramp, + CS48L32_INPUT_VOL_CONTROL, + CS48L32_IN_VD_RAMP_SHIFT, + cs48l32_vol_ramp_text); + +SOC_ENUM_SINGLE_DECL(cs48l32_in_vi_ramp, + CS48L32_INPUT_VOL_CONTROL, + CS48L32_IN_VI_RAMP_SHIFT, + cs48l32_vol_ramp_text); + +static const char * const cs48l32_in_hpf_cut_text[] = { + "2.5Hz", "5Hz", "10Hz", "20Hz", "40Hz" +}; + +SOC_ENUM_SINGLE_DECL(cs48l32_in_hpf_cut_enum, + CS48L32_INPUT_HPF_CONTROL, + CS48L32_IN_HPF_CUT_SHIFT, + cs48l32_in_hpf_cut_text); + +static const char * const cs48l32_in_dmic_osr_text[] = { + "384kHz", "768kHz", "1.536MHz", "2.048MHz", "2.4576MHz", "3.072MHz", + "6.144MHz", +}; + +const struct soc_enum cs48l32_in_dmic_osr[] = { + SOC_ENUM_SINGLE(CS48L32_INPUT1_CONTROL1, + CS48L32_IN1_OSR_SHIFT, + ARRAY_SIZE(cs48l32_in_dmic_osr_text), + cs48l32_in_dmic_osr_text), + SOC_ENUM_SINGLE(CS48L32_INPUT2_CONTROL1, + CS48L32_IN1_OSR_SHIFT, + ARRAY_SIZE(cs48l32_in_dmic_osr_text), + cs48l32_in_dmic_osr_text), +}; + +int cs48l32_in_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int reg, shift; + int ret = 0; + + snd_soc_dapm_mutex_lock(dapm); + + /* Cannot change rate on an active input */ + reg = snd_soc_component_read(component, CS48L32_INPUT_CONTROL); + shift = (e->reg - CS48L32_IN1L_CONTROL1) / 0x20; + shift ^= 0x1; /* Flip bottom bit for channel order */ + + if ((reg) & (1 << shift)) { + ret = -EBUSY; + goto exit; + } + + ret = snd_soc_put_enum_double(kcontrol, ucontrol); +exit: + snd_soc_dapm_mutex_unlock(dapm); + return ret; +} + +const struct soc_enum cs48l32_input_rate[] = { + SOC_VALUE_ENUM_SINGLE(CS48L32_IN1L_CONTROL1, + CS48L32_INx_RATE_SHIFT, + CS48L32_INx_RATE_MASK >> CS48L32_INx_RATE_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_IN1R_CONTROL1, + CS48L32_INx_RATE_SHIFT, + CS48L32_INx_RATE_MASK >> CS48L32_INx_RATE_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_IN2L_CONTROL1, + CS48L32_INx_RATE_SHIFT, + CS48L32_INx_RATE_MASK >> CS48L32_INx_RATE_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_IN2R_CONTROL1, + CS48L32_INx_RATE_SHIFT, + CS48L32_INx_RATE_MASK >> CS48L32_INx_RATE_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), +}; + +int cs48l32_low_power_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + unsigned int reg, mask; + int ret; + + snd_soc_dapm_mutex_lock(dapm); + + /* Cannot change low power mode on an active input */ + reg = snd_soc_component_read(component, CS48L32_INPUT_CONTROL); + mask = (mc->reg - CS48L32_IN1L_CONTROL1) / 0x20; + mask ^= 0x1; /* Flip bottom bit for channel order */ + + if ((reg) & (1 << mask)) { + ret = -EBUSY; + dev_err(component->dev, "Can't change lp mode on an active input\n"); + goto exit; + } + + ret = snd_soc_put_volsw(kcontrol, ucontrol); + +exit: + snd_soc_dapm_mutex_unlock(dapm); + return ret; +} + +const struct soc_enum noise_gen_rate = + SOC_VALUE_ENUM_SINGLE(CS48L32_COMFORT_NOISE_GENERATOR, + CS48L32_NOISE_GEN_RATE_SHIFT, + CS48L32_NOISE_GEN_RATE_MASK >> CS48L32_NOISE_GEN_RATE_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val); + +static const char * const cs48l32_auxpdm_freq_texts[] = { + "3.072MHz", "2.048MHz", "1.536MHz", "768kHz", +}; + +SOC_ENUM_SINGLE_DECL(cs48l32_auxpdm1_freq, + CS48L32_AUXPDM1_CONTROL1, + CS48L32_AUXPDM1_FREQ_SHIFT, + cs48l32_auxpdm_freq_texts); + +SOC_ENUM_SINGLE_DECL(cs48l32_auxpdm2_freq, + CS48L32_AUXPDM2_CONTROL1, + CS48L32_AUXPDM1_FREQ_SHIFT, + cs48l32_auxpdm_freq_texts); + +static const char * const cs48l32_auxpdm_src_texts[] = { + "Analog", "IN1 Digital", "IN2 Digital", +}; + +static SOC_ENUM_SINGLE_DECL(cs48l32_auxpdm1_in, + CS48L32_AUXPDM_CTRL2, + CS48L32_AUXPDMDAT1_SRC_SHIFT, + cs48l32_auxpdm_src_texts); + +static SOC_ENUM_SINGLE_DECL(cs48l32_auxpdm2_in, + CS48L32_AUXPDM_CTRL2, + CS48L32_AUXPDMDAT2_SRC_SHIFT, + cs48l32_auxpdm_src_texts); + +const struct snd_kcontrol_new cs48l32_auxpdm_inmux[] = { + SOC_DAPM_ENUM("AUXPDM1 Input", cs48l32_auxpdm1_in), + SOC_DAPM_ENUM("AUXPDM2 Input", cs48l32_auxpdm2_in), +}; + +static const unsigned int cs48l32_auxpdm_analog_in_val[] = { + 0x0, 0x1, +}; + +static const struct soc_enum cs48l32_auxpdm_analog_inmux_enum[] = { + SOC_VALUE_ENUM_SINGLE(CS48L32_AUXPDM1_CONTROL1, + CS48L32_AUXPDM1_SRC_SHIFT, + CS48L32_AUXPDM1_SRC_MASK >> CS48L32_AUXPDM1_SRC_SHIFT, + ARRAY_SIZE(cs48l32_auxpdm_analog_in_val), + cs48l32_in_texts, + cs48l32_auxpdm_analog_in_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_AUXPDM2_CONTROL1, + CS48L32_AUXPDM1_SRC_SHIFT, + CS48L32_AUXPDM1_SRC_MASK >> CS48L32_AUXPDM1_SRC_SHIFT, + ARRAY_SIZE(cs48l32_auxpdm_analog_in_val), + cs48l32_in_texts, + cs48l32_auxpdm_analog_in_val), +}; + +const struct snd_kcontrol_new cs48l32_auxpdm_analog_inmux[] = { + SOC_DAPM_ENUM("AUXPDM1 Analog Input", cs48l32_auxpdm_analog_inmux_enum[0]), + SOC_DAPM_ENUM("AUXPDM2 Analog Input", cs48l32_auxpdm_analog_inmux_enum[1]), +}; + +const struct snd_kcontrol_new cs48l32_auxpdm_switch[] = { + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), +}; + +const struct soc_enum cs48l32_isrc_fsh[] = { + SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC1_CONTROL1, + CS48L32_ISRC1_FSH_SHIFT, + CS48L32_ISRC1_FSH_MASK >> CS48L32_ISRC1_FSH_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC2_CONTROL1, + CS48L32_ISRC1_FSH_SHIFT, + CS48L32_ISRC1_FSH_MASK >> CS48L32_ISRC1_FSH_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC3_CONTROL1, + CS48L32_ISRC1_FSH_SHIFT, + CS48L32_ISRC1_FSH_MASK >> CS48L32_ISRC1_FSH_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), +}; + +const struct soc_enum cs48l32_isrc_fsl[] = { + SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC1_CONTROL1, + CS48L32_ISRC1_FSL_SHIFT, + CS48L32_ISRC1_FSL_MASK >> CS48L32_ISRC1_FSL_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC2_CONTROL1, + CS48L32_ISRC1_FSL_SHIFT, + CS48L32_ISRC1_FSL_MASK >> CS48L32_ISRC1_FSL_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(CS48L32_ISRC3_CONTROL1, + CS48L32_ISRC1_FSL_SHIFT, + CS48L32_ISRC1_FSL_MASK >> CS48L32_ISRC1_FSL_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val), +}; + +const struct soc_enum cs48l32_fx_rate = + SOC_VALUE_ENUM_SINGLE(CS48L32_FX_SAMPLE_RATE, + CS48L32_FX_RATE_SHIFT, + CS48L32_FX_RATE_MASK >> CS48L32_FX_RATE_SHIFT, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, + cs48l32_rate_val); + +static const char * const cs48l32_lhpf_mode_text[] = { + "Low-pass", "High-pass" +}; + +const struct soc_enum cs48l32_lhpf_mode[] = { + SOC_ENUM_SINGLE(CS48L32_LHPF_CONTROL2, 0, + ARRAY_SIZE(cs48l32_lhpf_mode_text), cs48l32_lhpf_mode_text), + SOC_ENUM_SINGLE(CS48L32_LHPF_CONTROL2, 1, + ARRAY_SIZE(cs48l32_lhpf_mode_text), cs48l32_lhpf_mode_text), + SOC_ENUM_SINGLE(CS48L32_LHPF_CONTROL2, 2, + ARRAY_SIZE(cs48l32_lhpf_mode_text), cs48l32_lhpf_mode_text), + SOC_ENUM_SINGLE(CS48L32_LHPF_CONTROL2, 3, + ARRAY_SIZE(cs48l32_lhpf_mode_text), cs48l32_lhpf_mode_text), +}; + +int cs48l32_lhpf_coeff_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + __be32 *data = (__be32 *)ucontrol->value.bytes.data; + s16 val = (s16)be32_to_cpu(*data); + + if (abs(val) >= 4096) { + dev_err(cs48l32->dev, "Rejecting unstable LHPF coefficients\n"); + return -EINVAL; + } + + return snd_soc_bytes_put(kcontrol, ucontrol); +} + +static const char * const cs48l32_eq_mode_text[] = { + "Low-pass", "High-pass", +}; + +const struct soc_enum cs48l32_eq_mode[] = { + SOC_ENUM_SINGLE(CS48L32_EQ_CONTROL2, 0, + ARRAY_SIZE(cs48l32_eq_mode_text), + cs48l32_eq_mode_text), + SOC_ENUM_SINGLE(CS48L32_EQ_CONTROL2, 1, + ARRAY_SIZE(cs48l32_eq_mode_text), + cs48l32_eq_mode_text), + SOC_ENUM_SINGLE(CS48L32_EQ_CONTROL2, 2, + ARRAY_SIZE(cs48l32_eq_mode_text), + cs48l32_eq_mode_text), + SOC_ENUM_SINGLE(CS48L32_EQ_CONTROL2, 3, + ARRAY_SIZE(cs48l32_eq_mode_text), + cs48l32_eq_mode_text), +}; + +int cs48l32_eq_mode_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; + unsigned int item; + + item = snd_soc_enum_val_to_item(e, cs48l32->eq_mode[e->shift_l]); + ucontrol->value.enumerated.item[0] = item; + + return 0; +} + +int cs48l32_eq_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; + unsigned int *item = ucontrol->value.enumerated.item; + unsigned int val; + bool changed = false; + + if (item[0] >= e->items) + return -EINVAL; + + val = snd_soc_enum_item_to_val(e, item[0]); + + snd_soc_dapm_mutex_lock(dapm); + if (cs48l32->eq_mode[e->shift_l] != val) { + cs48l32->eq_mode[e->shift_l] = val; + changed = true; + } + snd_soc_dapm_mutex_unlock(dapm); + + return changed; +} + +int cs48l32_eq_coeff_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + struct cs48l32_eq_control *ctl = (void *) kcontrol->private_value; + + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = ctl->max; + + return 0; +} + +int cs48l32_eq_coeff_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_eq_control *params = (void *)kcontrol->private_value; + __be16 *coeffs; + unsigned int coeff_idx; + int block_idx; + + block_idx = ((int) params->block_base - (int) CS48L32_EQ1_BAND1_COEFF1); + block_idx /= 68; + + coeffs = &cs48l32->eq_coefficients[block_idx][0]; + + coeff_idx = (params->reg - params->block_base) / 2; + coeff_idx += ((params->shift == 0) ? 1 : 0); + + ucontrol->value.integer.value[0] = be16_to_cpu(coeffs[coeff_idx]); + + return 0; +} + +int cs48l32_eq_coeff_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_eq_control *params = (void *)kcontrol->private_value; + __be16 *coeffs; + unsigned int coeff_idx; + int block_idx; + + block_idx = ((int) params->block_base - (int) CS48L32_EQ1_BAND1_COEFF1); + block_idx /= 68; + + coeffs = &cs48l32->eq_coefficients[block_idx][0]; + + coeff_idx = (params->reg - params->block_base) / 2; + coeff_idx += ((params->shift == 0) ? 1 : 0); + + snd_soc_dapm_mutex_lock(dapm); + coeffs[coeff_idx] = cpu_to_be16(ucontrol->value.integer.value[0]); + snd_soc_dapm_mutex_unlock(dapm); + + return 0; +} + +const struct snd_kcontrol_new cs48l32_drc_activity_output_mux[] = { + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), +}; + +const struct snd_kcontrol_new cs48l32_dsp_trigger_output_mux[] = { + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0), +}; + +int cs48l32_dsp_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; + unsigned int cached_rate; + const unsigned int rate_num = e->mask; + int item; + + if (rate_num >= ARRAY_SIZE(cs48l32->dsp_dma_rates)) + return -EINVAL; + + cached_rate = cs48l32->dsp_dma_rates[rate_num]; + item = snd_soc_enum_val_to_item(e, cached_rate); + ucontrol->value.enumerated.item[0] = item; + + return 0; +} + +int cs48l32_dsp_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; + const unsigned int rate_num = e->mask; + const unsigned int item = ucontrol->value.enumerated.item[0]; + unsigned int val; + bool changed = false; + + if (item >= e->items) + return -EINVAL; + + if (rate_num >= ARRAY_SIZE(cs48l32->dsp_dma_rates)) + return -EINVAL; + + val = snd_soc_enum_item_to_val(e, item); + + snd_soc_dapm_mutex_lock(dapm); + if (cs48l32->dsp_dma_rates[rate_num] != val) { + cs48l32->dsp_dma_rates[rate_num] = val; + changed = true; + } + snd_soc_dapm_mutex_unlock(dapm); + + return changed; +} + +const struct soc_enum cs48l32_dsp_rate_enum[] = { + /* RX rates */ + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 0, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 1, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 2, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 3, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 4, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 5, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 6, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 7, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + /* TX rates */ + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 8, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 9, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 10, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 11, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 12, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 13, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 14, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), + SOC_VALUE_ENUM_SINGLE(SND_SOC_NOPM, 0, + 15, + ARRAY_SIZE(cs48l32_rate_text), + cs48l32_rate_text, cs48l32_rate_val), +}; + +int cs48l32_dsp_pre_run(struct wm_adsp *dsp) +{ + struct cs48l32 *cs48l32 = container_of(dsp, struct cs48l32, dsp); + unsigned int reg; + const u8 *rate = cs48l32->dsp_dma_rates; + int i; + + reg = dsp->cs_dsp.base + CS48L32_HALO_SAMPLE_RATE_RX1; + for (i = 0; i < CS48L32_DSP_N_RX_CHANNELS; ++i) { + regmap_update_bits(dsp->cs_dsp.regmap, reg, CS48L32_HALO_DSP_RATE_MASK, *rate); + reg += 8; + rate++; + } + + reg = dsp->cs_dsp.base + CS48L32_HALO_SAMPLE_RATE_TX1; + for (i = 0; i < CS48L32_DSP_N_TX_CHANNELS; ++i) { + regmap_update_bits(dsp->cs_dsp.regmap, reg, CS48L32_HALO_DSP_RATE_MASK, *rate); + reg += 8; + rate++; + } + + usleep_range(300, 600); + + return 0; +} + +int cs48l32_dsp_memory_enable(struct cs48l32 *cs48l32, + const struct cs48l32_dsp_power_regs *regs) +{ + struct regmap *regmap = cs48l32->mfd->regmap; + int i, j, ret; + + /* disable power-off */ + for (i = 0; i < regs->n_ext; ++i) { + for (j = regs->ext[i].start; j <= regs->ext[i].end; j += 4) { + ret = regmap_write(regmap, j, 0x3); + if (ret) + goto err; + } + } + + /* power-up the banks in sequence */ + for (i = 0; i < regs->n_pwd; ++i) { + ret = regmap_write(regmap, regs->pwd[i], 0x1); + if (ret) + goto err; + + udelay(1); /* allow bank to power-up */ + + ret = regmap_write(regmap, regs->pwd[i], 0x3); + if (ret) + goto err; + + udelay(1); /* allow bank to power-up */ + } + + return 0; + +err: + dev_err(cs48l32->dev, "Failed to write SRAM enables (%d)\n", ret); + cs48l32_dsp_memory_disable(cs48l32, regs); + + return ret; +} + +void cs48l32_dsp_memory_disable(struct cs48l32 *cs48l32, + const struct cs48l32_dsp_power_regs *regs) +{ + struct regmap *regmap = cs48l32->mfd->regmap; + int i, j, ret; + + for (i = 0; i < regs->n_pwd; ++i) { + ret = regmap_write(regmap, regs->pwd[i], 0); + if (ret) + dev_warn(cs48l32->dev, "Failed to write SRAM enables (%d)\n", ret); + } + + for (i = 0; i < regs->n_ext; ++i) { + for (j = regs->ext[i].start; j <= regs->ext[i].end; j += 4) { + ret = regmap_write(regmap, j, 0); + if (ret) + dev_warn(cs48l32->dev, "Failed to write SRAM enables (%d)\n", ret); + } + } +} + +static int cs48l32_dsp_freq_update(struct snd_soc_dapm_widget *w, unsigned int freq_reg, + unsigned int freqsel_reg) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_mfd *mfd = cs48l32->mfd; + struct wm_adsp *dsp = &cs48l32->dsp; + int ret; + unsigned int freq, freq_sel, freq_sts; + + if (!freq_reg) + return -EINVAL; + + ret = regmap_read(mfd->regmap, freq_reg, &freq); + if (ret) { + dev_err(component->dev, "Failed to read 0x%x: %d\n", freq_reg, ret); + return ret; + } + + if (freqsel_reg) { + freq_sts = (freq & CS48L32_SYSCLK_FREQ_STS_MASK) >> CS48L32_SYSCLK_FREQ_STS_SHIFT; + + ret = regmap_read(mfd->regmap, freqsel_reg, &freq_sel); + if (ret) { + dev_err(component->dev, "Failed to read 0x%x: %d\n", freqsel_reg, ret); + return ret; + } + freq_sel = (freq_sel & CS48L32_SYSCLK_FREQ_MASK) >> CS48L32_SYSCLK_FREQ_SHIFT; + + if (freq_sts != freq_sel) { + dev_err(component->dev, "SYSCLK FREQ (0x%x) != FREQ STS (0x%x)\n", + freq_sel, freq_sts); + return -ETIMEDOUT; + } + } + + freq &= CS48L32_DSP_CLK_FREQ_MASK; + freq >>= CS48L32_DSP_CLK_FREQ_SHIFT; + + ret = regmap_write(dsp->cs_dsp.regmap, + dsp->cs_dsp.base + CS48L32_DSP_CLOCK_FREQ_OFFS, freq); + if (ret) { + dev_err(component->dev, "Failed to set HALO clock freq: %d\n", ret); + return ret; + } + + return 0; +} + +int cs48l32_dsp_freq_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + switch (event) { + case SND_SOC_DAPM_POST_PMU: + return cs48l32_dsp_freq_update(w, CS48L32_SYSTEM_CLOCK2, CS48L32_SYSTEM_CLOCK1); + default: + return 0; + } +} + +irqreturn_t cs48l32_dsp1_irq(int irq, void *data) +{ + struct cs48l32 *cs48l32 = data; + int ret; + + ret = wm_adsp_compr_handle_irq(&cs48l32->dsp); + if (ret == -ENODEV) { + dev_err(cs48l32->dev, "Spurious compressed data IRQ\n"); + return IRQ_NONE; + } + + return IRQ_HANDLED; +} + +static const unsigned int cs48l32_opclk_ref_48k_rates[] = { + 6144000, + 12288000, + 24576000, + 49152000, +}; + +static const unsigned int cs48l32_opclk_ref_44k1_rates[] = { + 5644800, + 11289600, + 22579200, + 45158400, +}; + +static int cs48l32_set_opclk(struct snd_soc_component *component, unsigned int clk, + unsigned int freq) +{ + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + unsigned int reg; + const unsigned int *rates; + int ref, div, refclk; + + BUILD_BUG_ON(ARRAY_SIZE(cs48l32_opclk_ref_48k_rates) != + ARRAY_SIZE(cs48l32_opclk_ref_44k1_rates)); + + switch (clk) { + case CS48L32_CLK_OPCLK: + reg = CS48L32_OUTPUT_SYS_CLK; + refclk = cs48l32->sysclk; + break; + default: + return -EINVAL; + } + + if (refclk % 4000) + rates = cs48l32_opclk_ref_44k1_rates; + else + rates = cs48l32_opclk_ref_48k_rates; + + for (ref = 0; ref < ARRAY_SIZE(cs48l32_opclk_ref_48k_rates); ++ref) { + if (rates[ref] > refclk) + continue; + + div = 2; + while ((rates[ref] / div >= freq) && (div <= 30)) { + if (rates[ref] / div == freq) { + dev_dbg(component->dev, "Configured %dHz OPCLK\n", freq); + snd_soc_component_update_bits(component, reg, + CS48L32_OPCLK_DIV_MASK | + CS48L32_OPCLK_SEL_MASK, + (div << CS48L32_OPCLK_DIV_SHIFT) | + ref); + return 0; + } + div += 2; + } + } + + dev_err(component->dev, "Unable to generate %dHz OPCLK\n", freq); + return -EINVAL; +} + +static int cs48l32_get_dspclk_setting(struct cs48l32 *cs48l32, unsigned int freq, + int src, unsigned int *val) +{ + freq /= 15625; /* convert to 1/64ths of 1MHz */ + *val |= freq << CS48L32_DSP_CLK_FREQ_SHIFT; + + return 0; +} + +static int cs48l32_get_sysclk_setting(unsigned int freq) +{ + switch (freq) { + case 0: + case 5644800: + case 6144000: + return CS48L32_SYSCLK_RATE_6MHZ; + case 11289600: + case 12288000: + return CS48L32_SYSCLK_RATE_12MHZ << CS48L32_SYSCLK_FREQ_SHIFT; + case 22579200: + case 24576000: + return CS48L32_SYSCLK_RATE_24MHZ << CS48L32_SYSCLK_FREQ_SHIFT; + case 45158400: + case 49152000: + return CS48L32_SYSCLK_RATE_49MHZ << CS48L32_SYSCLK_FREQ_SHIFT; + case 90316800: + case 98304000: + return CS48L32_SYSCLK_RATE_98MHZ << CS48L32_SYSCLK_FREQ_SHIFT; + default: + return -EINVAL; + } +} + +static int cs48l32_set_pdm_fllclk(struct snd_soc_component *component, int source) +{ + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_mfd *mfd = cs48l32->mfd; + unsigned int val; + + switch (source) { + case CS48L32_PDMCLK_SRC_IN1_PDMCLK: + case CS48L32_PDMCLK_SRC_IN2_PDMCLK: + case CS48L32_PDMCLK_SRC_IN3_PDMCLK: + case CS48L32_PDMCLK_SRC_IN4_PDMCLK: + case CS48L32_PDMCLK_SRC_AUXPDM1_CLK: + case CS48L32_PDMCLK_SRC_AUXPDM2_CLK: + val = source << CS48L32_PDM_FLLCLK_SRC_SHIFT; + break; + default: + dev_err(cs48l32->dev, "Invalid PDM FLLCLK src %d\n", source); + return -EINVAL; + } + + return regmap_update_bits(mfd->regmap, CS48L32_INPUT_CONTROL2, + CS48L32_PDM_FLLCLK_SRC_MASK, val); +} + +int cs48l32_set_sysclk(struct snd_soc_component *component, int clk_id, int source, + unsigned int freq, int dir) +{ + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_mfd *mfd = cs48l32->mfd; + char *name; + unsigned int reg; + unsigned int mask = CS48L32_SYSCLK_SRC_MASK; + unsigned int val = source << CS48L32_SYSCLK_SRC_SHIFT; + int clk_freq_sel, *clk; + + switch (clk_id) { + case CS48L32_CLK_SYSCLK_1: + name = "SYSCLK"; + reg = CS48L32_SYSTEM_CLOCK1; + clk = &cs48l32->sysclk; + clk_freq_sel = cs48l32_get_sysclk_setting(freq); + mask |= CS48L32_SYSCLK_FREQ_MASK | CS48L32_SYSCLK_FRAC_MASK; + break; + case CS48L32_CLK_DSPCLK: + name = "DSPCLK"; + reg = CS48L32_DSP_CLOCK1; + clk = &cs48l32->dspclk; + clk_freq_sel = cs48l32_get_dspclk_setting(cs48l32, freq, source, &val); + mask |= CS48L32_DSP_CLK_FREQ_MASK; + break; + case CS48L32_CLK_OPCLK: + return cs48l32_set_opclk(component, clk_id, freq); + case CS48L32_CLK_PDM_FLLCLK: + return cs48l32_set_pdm_fllclk(component, source); + default: + return -EINVAL; + } + + if (clk_freq_sel < 0) { + dev_err(cs48l32->dev, "Failed to get %s setting for %dHZ\n", name, freq); + return clk_freq_sel; + } + + *clk = freq; + + if (freq == 0) { + dev_dbg(cs48l32->dev, "%s cleared\n", name); + return 0; + } + + val |= clk_freq_sel; + + if (freq % 6144000) + val |= CS48L32_SYSCLK_FRAC_MASK; + + dev_dbg(cs48l32->dev, "%s set to %uHz", name, freq); + + return regmap_update_bits(mfd->regmap, reg, mask, val); +} + +static int cs48l32_is_enabled_fll(struct cs48l32_fll *fll, int base) +{ + struct cs48l32_mfd *mfd = fll->cs48l32->mfd; + unsigned int reg; + int ret; + + ret = regmap_read(mfd->regmap, base + CS48L32_FLL_CONTROL1_OFFS, ®); + if (ret != 0) { + cs48l32_fll_err(fll, "Failed to read current state: %d\n", ret); + return ret; + } + + return reg & CS48L32_FLL_EN_MASK; +} + +static int cs48l32_wait_for_fll(struct cs48l32_fll *fll, bool requested) +{ + struct cs48l32_mfd *mfd = fll->cs48l32->mfd; + unsigned int val = 0; + int i; + + cs48l32_fll_dbg(fll, "Waiting for FLL...\n"); + + for (i = 0; i < 30; i++) { + regmap_read(mfd->regmap, fll->sts_addr, &val); + if (!!(val & fll->sts_mask) == requested) + return 0; + + switch (i) { + case 0 ... 5: + usleep_range(75, 125); + break; + case 11 ... 20: + usleep_range(750, 1250); + break; + default: + msleep(20); + break; + } + } + + cs48l32_fll_warn(fll, "Timed out waiting for %s\n", requested ? "lock" : "unlock"); + + return -ETIMEDOUT; +} + +static int cs48l32_fllhj_disable(struct cs48l32_fll *fll) +{ + struct cs48l32_mfd *mfd = fll->cs48l32->mfd; + bool change; + + cs48l32_fll_dbg(fll, "Disabling FLL\n"); + + /* + * Disable lockdet, but don't set ctrl_upd update bit. This allows the + * lock status bit to clear as normal, but should the FLL be enabled + * again due to a control clock being required, the lock won't re-assert + * as the FLL config registers are automatically applied when the FLL + * enables. + */ + regmap_set_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL1_OFFS, + CS48L32_FLL_HOLD_MASK); + regmap_clear_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL2_OFFS, + CS48L32_FLL_LOCKDET_MASK); + regmap_set_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL5_OFFS, + CS48L32_FLL_FRC_INTEG_UPD_MASK); + regmap_update_bits_check(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL1_OFFS, + CS48L32_FLL_EN_MASK, + 0, + &change); + + cs48l32_wait_for_fll(fll, false); + + /* + * ctrl_up gates the writes to all the fll's registers, setting it to 0 + * here ensures that after a runtime suspend/resume cycle when one + * enables the fll then ctrl_up is the last bit that is configured + * by the fll enable code rather than the cache sync operation which + * would have updated it much earlier before writing out all fll + * registers + */ + regmap_clear_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL1_OFFS, + CS48L32_FLL_CTRL_UPD_MASK); + + if (change) + pm_runtime_put_autosuspend(mfd->dev); + + return 0; +} + +static int cs48l32_fllhj_apply(struct cs48l32_fll *fll, int fin) +{ + struct cs48l32_mfd *mfd = fll->cs48l32->mfd; + int refdiv, fref, fout, lockdet_thr, fbdiv, fllgcd; + bool frac = false; + unsigned int fll_n, min_n, max_n, ratio, theta, lambda, hp; + unsigned int gains, num; + + cs48l32_fll_dbg(fll, "fin=%d, fout=%d\n", fin, fll->fout); + + for (refdiv = 0; refdiv < 4; refdiv++) { + if ((fin / (1 << refdiv)) <= CS48L32_FLLHJ_MAX_THRESH) + break; + } + + fref = fin / (1 << refdiv); + fout = fll->fout; + frac = fout % fref; + + if (frac && fll->integer_only) { + cs48l32_fll_err(fll, "%u:%u not an integer ratio\n", fin, fout); + return -EINVAL; + } + + if (fll->max_fref && (fref > fll->max_fref)) { + cs48l32_fll_err(fll, "fref=%u too high (max %u)\n", + fref, fll->max_fref); + return -EINVAL; + } + + /* + * Use simple heuristic approach to find a configuration that + * should work for most input clocks. + */ + if (fref < CS48L32_FLLHJ_LOW_THRESH) { + lockdet_thr = 2; + gains = CS48L32_FLLHJ_LOW_GAINS; + + if (frac) + fbdiv = 256; + else + fbdiv = 4; + } else if (fref < CS48L32_FLLHJ_MID_THRESH) { + lockdet_thr = 8; + gains = CS48L32_FLLHJ_MID_GAINS; + fbdiv = (frac) ? 16 : 2; + } else { + lockdet_thr = 8; + gains = CS48L32_FLLHJ_HIGH_GAINS; + fbdiv = 1; + } + /* Use high performance mode for fractional configurations. */ + if (frac) { + hp = 0x3; + min_n = CS48L32_FLLHJ_FRAC_MIN_N; + max_n = CS48L32_FLLHJ_FRAC_MAX_N; + } else { + if (fll->has_lp && (fref < CS48L32_FLLHJ_LP_INT_MODE_THRESH)) + hp = 0x0; + else + hp = 0x1; + + min_n = CS48L32_FLLHJ_INT_MIN_N; + max_n = CS48L32_FLLHJ_INT_MAX_N; + } + + ratio = fout / fref; + + cs48l32_fll_dbg(fll, "refdiv=%d, fref=%d, frac:%d\n", refdiv, fref, frac); + + while (ratio / fbdiv < min_n) { + fbdiv /= 2; + if (fbdiv < min_n) { + cs48l32_fll_err(fll, "FBDIV (%u) < minimum N (%u)\n", fbdiv, min_n); + return -EINVAL; + } + } + while (frac && (ratio / fbdiv > max_n)) { + fbdiv *= 2; + if (fbdiv >= 1024) { + cs48l32_fll_err(fll, "FBDIV (%u) >= 1024\n", fbdiv); + return -EINVAL; + } + } + + cs48l32_fll_dbg(fll, "lockdet=%d, hp=0x%x, fbdiv:%d\n", lockdet_thr, hp, fbdiv); + + /* Calculate N.K values */ + fllgcd = gcd(fout, fbdiv * fref); + num = fout / fllgcd; + lambda = (fref * fbdiv) / fllgcd; + fll_n = num / lambda; + theta = num % lambda; + + cs48l32_fll_dbg(fll, "fll_n=%d, gcd=%d, theta=%d, lambda=%d\n", + fll_n, fllgcd, theta, lambda); + + /* Some sanity checks before any registers are written. */ + if (fll_n < min_n || fll_n > max_n) { + cs48l32_fll_err(fll, "N not in valid %s mode range %d-%d: %d\n", + frac ? "fractional" : "integer", min_n, max_n, fll_n); + return -EINVAL; + } + if (fbdiv < 1 || (frac && fbdiv >= 1024) || (!frac && fbdiv >= 256)) { + cs48l32_fll_err(fll, "Invalid fbdiv for %s mode (%u)\n", + frac ? "fractional" : "integer", fbdiv); + return -EINVAL; + } + + /* clear the ctrl_upd bit to guarantee we write to it later. */ + regmap_update_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL2_OFFS, + CS48L32_FLL_LOCKDET_THR_MASK | + CS48L32_FLL_PHASEDET_MASK | + CS48L32_FLL_REFCLK_DIV_MASK | + CS48L32_FLL_N_MASK | + CS48L32_FLL_CTRL_UPD_MASK, + (lockdet_thr << CS48L32_FLL_LOCKDET_THR_SHIFT) | + (1 << CS48L32_FLL_PHASEDET_SHIFT) | + (refdiv << CS48L32_FLL_REFCLK_DIV_SHIFT) | + (fll_n << CS48L32_FLL_N_SHIFT)); + + regmap_update_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL3_OFFS, + CS48L32_FLL_LAMBDA_MASK | + CS48L32_FLL_THETA_MASK, + (lambda << CS48L32_FLL_LAMBDA_SHIFT) | + (theta << CS48L32_FLL_THETA_SHIFT)); + + regmap_update_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL4_OFFS, + (0xffff << CS48L32_FLL_FD_GAIN_COARSE_SHIFT) | + CS48L32_FLL_HP_MASK | + CS48L32_FLL_FB_DIV_MASK, + (gains << CS48L32_FLL_FD_GAIN_COARSE_SHIFT) | + (hp << CS48L32_FLL_HP_SHIFT) | + (fbdiv << CS48L32_FLL_FB_DIV_SHIFT)); + + return 0; +} + +static int cs48l32_fllhj_enable(struct cs48l32_fll *fll) +{ + struct cs48l32_mfd *mfd = fll->cs48l32->mfd; + int already_enabled = cs48l32_is_enabled_fll(fll, fll->base); + int ret; + + if (already_enabled < 0) + return already_enabled; + + if (!already_enabled) + pm_runtime_get_sync(mfd->dev); + + cs48l32_fll_dbg(fll, "Enabling FLL, initially %s\n", + already_enabled ? "enabled" : "disabled"); + + /* FLLn_HOLD must be set before configuring any registers */ + regmap_set_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL1_OFFS, + CS48L32_FLL_HOLD_MASK); + + /* Apply refclk */ + ret = cs48l32_fllhj_apply(fll, fll->ref_freq); + if (ret) { + cs48l32_fll_err(fll, "Failed to set FLL: %d\n", ret); + goto out; + } + regmap_update_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL2_OFFS, + CS48L32_FLL_REFCLK_SRC_MASK, + fll->ref_src << CS48L32_FLL_REFCLK_SRC_SHIFT); + + regmap_set_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL1_OFFS, + CS48L32_FLL_EN_MASK); + +out: + regmap_set_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL2_OFFS, + CS48L32_FLL_LOCKDET_MASK); + + regmap_set_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL1_OFFS, + CS48L32_FLL_CTRL_UPD_MASK); + + /* Release the hold so that flln locks to external frequency */ + regmap_clear_bits(mfd->regmap, + fll->base + CS48L32_FLL_CONTROL1_OFFS, + CS48L32_FLL_HOLD_MASK); + + if (!already_enabled) + cs48l32_wait_for_fll(fll, true); + + return 0; +} + +static int cs48l32_fllhj_validate(struct cs48l32_fll *fll, + unsigned int ref_in, + unsigned int fout) +{ + if (fout && !ref_in) { + cs48l32_fll_err(fll, "fllout set without valid input clk\n"); + return -EINVAL; + } + + if (fll->fout && fout != fll->fout) { + cs48l32_fll_err(fll, "Can't change output on active FLL\n"); + return -EINVAL; + } + + if (ref_in / CS48L32_FLL_MAX_REFDIV > CS48L32_FLLHJ_MAX_THRESH) { + cs48l32_fll_err(fll, "Can't scale %dMHz to <=13MHz\n", ref_in); + return -EINVAL; + } + + if (fout > CS48L32_FLL_MAX_FOUT) { + cs48l32_fll_err(fll, "Fout=%dMHz exceeeds maximum %dMHz\n", + fout, CS48L32_FLL_MAX_FOUT); + return -EINVAL; + } + + return 0; +} + +int cs48l32_fllhj_set_refclk(struct cs48l32_fll *fll, int source, + unsigned int fin, unsigned int fout) +{ + int ret = 0; + + if (fll->ref_src == source && fll->ref_freq == fin && fll->fout == fout) + return 0; + + if (fin && fout && cs48l32_fllhj_validate(fll, fin, fout)) + return -EINVAL; + + fll->ref_src = source; + fll->ref_freq = fin; + fll->fout = fout; + + if (fout) + ret = cs48l32_fllhj_enable(fll); + else + cs48l32_fllhj_disable(fll); + + return ret; +} + +int cs48l32_init_fll(struct cs48l32_fll *fll) +{ + fll->ref_src = CS48L32_FLL_SRC_NONE; + + return 0; +} + +static int cs48l32_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_component *component = dai->component; + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_mfd *mfd = cs48l32->mfd; + unsigned int val = 0U; + unsigned int base = dai->driver->base; + unsigned int mask = CS48L32_ASP_FMT_MASK | CS48L32_ASP_BCLK_INV_MASK | + CS48L32_ASP_BCLK_MSTR_MASK | + CS48L32_ASP_FSYNC_INV_MASK | + CS48L32_ASP_FSYNC_MSTR_MASK; + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_DSP_A: + val |= (CS48L32_ASP_FMT_DSP_MODE_A << CS48L32_ASP_FMT_SHIFT); + break; + case SND_SOC_DAIFMT_DSP_B: + if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_BP_FP) { + cs48l32_asp_err(dai, "DSP_B cannot be clock consumer\n"); + return -EINVAL; + } + val |= (CS48L32_ASP_FMT_DSP_MODE_B << CS48L32_ASP_FMT_SHIFT); + break; + case SND_SOC_DAIFMT_I2S: + val |= (CS48L32_ASP_FMT_I2S_MODE << CS48L32_ASP_FMT_SHIFT); + break; + case SND_SOC_DAIFMT_LEFT_J: + if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_BP_FP) { + cs48l32_asp_err(dai, "LEFT_J cannot be clock consumer\n"); + return -EINVAL; + } + val |= (CS48L32_ASP_FMT_LEFT_JUSTIFIED_MODE << CS48L32_ASP_FMT_SHIFT); + break; + default: + cs48l32_asp_err(dai, "Unsupported DAI format %d\n", + fmt & SND_SOC_DAIFMT_FORMAT_MASK); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { + case SND_SOC_DAIFMT_BC_FC: + break; + case SND_SOC_DAIFMT_BC_FP: + val |= CS48L32_ASP_FSYNC_MSTR_MASK; + break; + case SND_SOC_DAIFMT_BP_FC: + val |= CS48L32_ASP_BCLK_MSTR_MASK; + break; + case SND_SOC_DAIFMT_BP_FP: + val |= CS48L32_ASP_BCLK_MSTR_MASK; + val |= CS48L32_ASP_FSYNC_MSTR_MASK; + break; + default: + cs48l32_asp_err(dai, "Unsupported clock direction %d\n", + fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_IB_IF: + val |= CS48L32_ASP_BCLK_INV_MASK; + val |= CS48L32_ASP_FSYNC_INV_MASK; + break; + case SND_SOC_DAIFMT_IB_NF: + val |= CS48L32_ASP_BCLK_INV_MASK; + break; + case SND_SOC_DAIFMT_NB_IF: + val |= CS48L32_ASP_FSYNC_INV_MASK; + break; + default: + return -EINVAL; + } + + regmap_update_bits(mfd->regmap, base + CS48L32_ASP_CONTROL2, mask, val); + + return 0; +} + +static const struct { + u32 freq; + u32 id; +} cs48l32_sclk_rates[] = { + { 128000, 12 }, + { 176400, 13 }, + { 192000, 14 }, + { 256000, 15 }, + { 352800, 16 }, + { 384000, 17 }, + { 512000, 18 }, + { 705600, 19 }, + { 768000, 21 }, + { 1024000, 23 }, + { 1411200, 25 }, + { 1536000, 27 }, + { 2048000, 29 }, + { 2822400, 31 }, + { 3072000, 33 }, + { 4096000, 36 }, + { 5644800, 38 }, + { 6144000, 40 }, + { 8192000, 47 }, + { 11289600, 49 }, + { 12288000, 51 }, + { 22579200, 57 }, + { 24576000, 59 }, +}; + +#define CS48L32_48K_RATE_MASK 0x0e00fe +#define CS48L32_44K1_RATE_MASK 0x00fe00 +#define CS48L32_RATE_MASK (CS48L32_48K_RATE_MASK | CS48L32_44K1_RATE_MASK) + +static const unsigned int cs48l32_sr_vals[] = { + 0, + 12000, /* CS48L32_48K_RATE_MASK */ + 24000, /* CS48L32_48K_RATE_MASK */ + 48000, /* CS48L32_48K_RATE_MASK */ + 96000, /* CS48L32_48K_RATE_MASK */ + 192000, /* CS48L32_48K_RATE_MASK */ + 384000, /* CS48L32_48K_RATE_MASK */ + 768000, /* CS48L32_48K_RATE_MASK */ + 0, + 11025, /* CS48L32_44K1_RATE_MASK */ + 22050, /* CS48L32_44K1_RATE_MASK */ + 44100, /* CS48L32_44K1_RATE_MASK */ + 88200, /* CS48L32_44K1_RATE_MASK */ + 176400, /* CS48L32_44K1_RATE_MASK */ + 352800, /* CS48L32_44K1_RATE_MASK */ + 705600, /* CS48L32_44K1_RATE_MASK */ + 0, + 8000, /* CS48L32_48K_RATE_MASK */ + 16000, /* CS48L32_48K_RATE_MASK */ + 32000, /* CS48L32_48K_RATE_MASK */ +}; + +static const struct snd_pcm_hw_constraint_list cs48l32_constraint = { + .count = ARRAY_SIZE(cs48l32_sr_vals), + .list = cs48l32_sr_vals, +}; + +static int cs48l32_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_dai_priv *dai_priv = &cs48l32->dai[dai->id - 1]; + unsigned int base_rate; + + if (!substream->runtime) + return 0; + + switch (dai_priv->clk) { + case CS48L32_CLK_SYSCLK_1: + case CS48L32_CLK_SYSCLK_2: + case CS48L32_CLK_SYSCLK_3: + case CS48L32_CLK_SYSCLK_4: + base_rate = cs48l32->sysclk; + break; + default: + return 0; + } + + if (base_rate == 0) + dai_priv->constraint.mask = CS48L32_RATE_MASK; + else if (base_rate % 4000) + dai_priv->constraint.mask = CS48L32_44K1_RATE_MASK; + else + dai_priv->constraint.mask = CS48L32_48K_RATE_MASK; + + return snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + &dai_priv->constraint); +} + +static int cs48l32_hw_params_rate(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_dai_priv *dai_priv = &cs48l32->dai[dai->id - 1]; + unsigned int sr_val, sr_reg, rate; + + rate = params_rate(params); + for (sr_val = 0; sr_val < ARRAY_SIZE(cs48l32_sr_vals); sr_val++) + if (cs48l32_sr_vals[sr_val] == rate) + break; + + if (sr_val == ARRAY_SIZE(cs48l32_sr_vals)) { + cs48l32_asp_err(dai, "Unsupported sample rate %dHz\n", rate); + return -EINVAL; + } + + switch (dai_priv->clk) { + case CS48L32_CLK_SYSCLK_1: + sr_reg = CS48L32_SAMPLE_RATE1; + break; + case CS48L32_CLK_SYSCLK_2: + sr_reg = CS48L32_SAMPLE_RATE2; + break; + case CS48L32_CLK_SYSCLK_3: + sr_reg = CS48L32_SAMPLE_RATE3; + break; + case CS48L32_CLK_SYSCLK_4: + sr_reg = CS48L32_SAMPLE_RATE3; + break; + default: + return -EINVAL; + } + + snd_soc_component_update_bits(component, sr_reg, CS48L32_SAMPLE_RATE_1_MASK, sr_val); + + return 0; +} + +static bool cs48l32_asp_cfg_changed(struct snd_soc_component *component, + unsigned int base, unsigned int sclk, + unsigned int slotws, unsigned int dataw) +{ + unsigned int val; + + val = snd_soc_component_read(component, base + CS48L32_ASP_CONTROL1); + if (sclk != (val & CS48L32_ASP_BCLK_FREQ_MASK)) + return true; + + val = snd_soc_component_read(component, base + CS48L32_ASP_CONTROL2); + if (slotws != (val & (CS48L32_ASP_RX_WIDTH_MASK | CS48L32_ASP_TX_WIDTH_MASK))) + return true; + + val = snd_soc_component_read(component, base + CS48L32_ASP_DATA_CONTROL1); + if (dataw != (val & (CS48L32_ASP_TX_WL_MASK))) + return true; + + val = snd_soc_component_read(component, base + CS48L32_ASP_DATA_CONTROL5); + if (dataw != (val & (CS48L32_ASP_RX_WL_MASK))) + return true; + + return false; +} + +static int cs48l32_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_mfd *mfd = cs48l32->mfd; + int base = dai->driver->base; + int dai_id = dai->id - 1; + unsigned int rate = params_rate(params); + unsigned int dataw = snd_pcm_format_width(params_format(params)); + unsigned int chan_limit = cs48l32->max_channels_clocked[dai_id]; + unsigned int asp_state = 0; + int sclk, sclk_target; + unsigned int slotw, n_slots, n_slots_multiple, val; + int i, ret; + + cs48l32_asp_dbg(dai, "hwparams in: ch:%u dataw:%u rate:%u\n", + params_channels(params), dataw, rate); + /* + * The following calculations hold only under the assumption that + * symmetric_[rates|channels|samplebits] are set to 1 + */ + if (cs48l32->tdm_slots[dai_id]) { + n_slots = cs48l32->tdm_slots[dai_id]; + slotw = cs48l32->tdm_width[dai_id]; + } else { + n_slots = params_channels(params); + slotw = dataw; + } + + if (chan_limit) + n_slots = min(n_slots, chan_limit); + + val = snd_soc_component_read(component, base + CS48L32_ASP_CONTROL2); + val = (val & CS48L32_ASP_FMT_MASK) >> CS48L32_ASP_FMT_SHIFT; + if (val == CS48L32_ASP_FMT_I2S_MODE) + n_slots_multiple = 2; + else + n_slots_multiple = 1; + + sclk_target = snd_soc_tdm_params_to_bclk(params, slotw, n_slots, n_slots_multiple); + + for (i = 0; i < ARRAY_SIZE(cs48l32_sclk_rates); i++) { + if ((cs48l32_sclk_rates[i].freq >= sclk_target) && + (cs48l32_sclk_rates[i].freq % rate == 0)) { + sclk = cs48l32_sclk_rates[i].id; + break; + } + } + if (i == ARRAY_SIZE(cs48l32_sclk_rates)) { + cs48l32_asp_err(dai, "Unsupported sample rate %dHz\n", rate); + return -EINVAL; + } + + cs48l32_asp_dbg(dai, "hwparams out: n_slots:%u dataw:%u slotw:%u bclk:%u bclkid:%u\n", + n_slots, dataw, slotw, sclk_target, sclk); + + slotw = (slotw << CS48L32_ASP_TX_WIDTH_SHIFT) | + (slotw << CS48L32_ASP_RX_WIDTH_SHIFT); + + if (!cs48l32_asp_cfg_changed(component, base, sclk, slotw, dataw)) + return cs48l32_hw_params_rate(substream, params, dai); + + /* ASP must be disabled while changing configuration */ + asp_state = snd_soc_component_read(component, base + CS48L32_ASP_ENABLES1); + regmap_clear_bits(mfd->regmap, base + CS48L32_ASP_ENABLES1, 0xff00ff); + + ret = cs48l32_hw_params_rate(substream, params, dai); + if (ret != 0) + goto restore_asp; + + regmap_update_bits_async(mfd->regmap, + base + CS48L32_ASP_CONTROL1, + CS48L32_ASP_BCLK_FREQ_MASK, + sclk); + regmap_update_bits_async(mfd->regmap, + base + CS48L32_ASP_CONTROL2, + CS48L32_ASP_RX_WIDTH_MASK | CS48L32_ASP_TX_WIDTH_MASK, + slotw); + regmap_update_bits_async(mfd->regmap, + base + CS48L32_ASP_DATA_CONTROL1, + CS48L32_ASP_TX_WL_MASK, + dataw); + regmap_update_bits(mfd->regmap, + base + CS48L32_ASP_DATA_CONTROL5, + CS48L32_ASP_RX_WL_MASK, + dataw); + +restore_asp: + /* Restore ASP TX/RX enable state */ + regmap_update_bits(mfd->regmap, + base + CS48L32_ASP_ENABLES1, + 0xff00ff, + asp_state); + return ret; +} + +static const char * const cs48l32_dai_clk_str(int clk_id) +{ + switch (clk_id) { + case CS48L32_CLK_SYSCLK_1: + case CS48L32_CLK_SYSCLK_2: + case CS48L32_CLK_SYSCLK_3: + case CS48L32_CLK_SYSCLK_4: + return "SYSCLK"; + default: + return "Unknown clock"; + } +} + +static int cs48l32_dai_set_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_component *component = dai->component; + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_dai_priv *dai_priv = &cs48l32->dai[dai->id - 1]; + unsigned int base = dai->driver->base; + unsigned int current_asp_rate, target_asp_rate; + bool change_rate_domain = false; + int ret; + + if (clk_id == dai_priv->clk) + return 0; + + if (snd_soc_dai_active(dai)) { + cs48l32_asp_err(dai, "Can't change clock on active DAI\n"); + return -EBUSY; + } + + switch (clk_id) { + case CS48L32_CLK_SYSCLK_1: + target_asp_rate = 0U << CS48L32_ASP_RATE_SHIFT; + break; + case CS48L32_CLK_SYSCLK_2: + target_asp_rate = 1U << CS48L32_ASP_RATE_SHIFT; + break; + case CS48L32_CLK_SYSCLK_3: + target_asp_rate = 2U << CS48L32_ASP_RATE_SHIFT; + break; + case CS48L32_CLK_SYSCLK_4: + target_asp_rate = 3U << CS48L32_ASP_RATE_SHIFT; + break; + default: + return -EINVAL; + } + + dai_priv->clk = clk_id; + cs48l32_asp_dbg(dai, "Setting to %s\n", cs48l32_dai_clk_str(clk_id)); + + if (base) { + ret = regmap_read(cs48l32->mfd->regmap, + base + CS48L32_ASP_CONTROL1, + ¤t_asp_rate); + if (ret != 0) { + cs48l32_asp_err(dai, "Failed to check rate: %d\n", ret); + return ret; + } + + if ((current_asp_rate & CS48L32_ASP_RATE_MASK) != + (target_asp_rate & CS48L32_ASP_RATE_MASK)) { + change_rate_domain = true; + + mutex_lock(&cs48l32->rate_lock); + /* Guard the rate change with SYSCLK cycles */ + cs48l32_spin_sysclk(cs48l32); + } + + snd_soc_component_update_bits(component, base + CS48L32_ASP_CONTROL1, + CS48L32_ASP_RATE_MASK, target_asp_rate); + + if (change_rate_domain) { + cs48l32_spin_sysclk(cs48l32); + mutex_unlock(&cs48l32->rate_lock); + } + } + + return 0; +} + +static void cs48l32_set_channels_to_mask(struct snd_soc_dai *dai, + unsigned int base, + int channels, unsigned int mask) +{ + struct snd_soc_component *component = dai->component; + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_mfd *mfd = cs48l32->mfd; + int slot, i, j = 0, shift; + unsigned int frame_ctls[2] = {0, 0}; + + for (i = 0; i < channels; ++i) { + slot = ffs(mask) - 1; + if (slot < 0) + return; + + if (i - (j * 4) >= 4) { + ++j; + if (j >= 2) + break; + } + + shift = (8 * (i - j * 4)); + + frame_ctls[j] |= slot << shift; + + mask &= ~(1 << slot); /* ? mask ^= 1 << slot ? */ + } + + regmap_write(mfd->regmap, base, frame_ctls[0]); + regmap_write(mfd->regmap, base + 0x4, frame_ctls[1]); + + if (mask) + cs48l32_asp_warn(dai, "Too many channels in TDM mask\n"); +} + +static int cs48l32_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, + unsigned int rx_mask, int slots, int slot_width) +{ + struct snd_soc_component *component = dai->component; + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + int base = dai->driver->base; + int rx_max_chan = dai->driver->playback.channels_max; + int tx_max_chan = dai->driver->capture.channels_max; + + /* Only support TDM for the physical ASPs */ + if (dai->id > CS48L32_MAX_ASP) + return -EINVAL; + + if (slots == 0) { + tx_mask = (1 << tx_max_chan) - 1; + rx_mask = (1 << rx_max_chan) - 1; + } + + cs48l32_set_channels_to_mask(dai, base + CS48L32_ASP_FRAME_CONTROL1, + tx_max_chan, tx_mask); + cs48l32_set_channels_to_mask(dai, base + CS48L32_ASP_FRAME_CONTROL5, + rx_max_chan, rx_mask); + + cs48l32->tdm_width[dai->id - 1] = slot_width; + cs48l32->tdm_slots[dai->id - 1] = slots; + + return 0; +} + +const struct snd_soc_dai_ops cs48l32_dai_ops = { + .startup = &cs48l32_startup, + .set_fmt = &cs48l32_set_fmt, + .set_tdm_slot = &cs48l32_set_tdm_slot, + .hw_params = &cs48l32_hw_params, + .set_sysclk = &cs48l32_dai_set_sysclk, +}; + +int cs48l32_sysclk_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + + cs48l32_spin_sysclk(cs48l32); + + return 0; +} + +int cs48l32_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + unsigned int reg; + + if (w->shift % 2) + reg = CS48L32_IN1L_CONTROL2 + ((w->shift / 2) * 0x40); + else + reg = CS48L32_IN1R_CONTROL2 + ((w->shift / 2) * 0x40); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + switch (w->shift) { + case CS48L32_IN1L_EN_SHIFT: + snd_soc_component_update_bits(component, + CS48L32_ADC1L_ANA_CONTROL1, + CS48L32_ADC1x_INT_ENA_FRC_MASK, + CS48L32_ADC1x_INT_ENA_FRC_MASK); + break; + case CS48L32_IN1R_EN_SHIFT: + snd_soc_component_update_bits(component, + CS48L32_ADC1R_ANA_CONTROL1, + CS48L32_ADC1x_INT_ENA_FRC_MASK, + CS48L32_ADC1x_INT_ENA_FRC_MASK); + break; + default: + break; + } + cs48l32->in_up_pending++; + break; + case SND_SOC_DAPM_POST_PMU: + usleep_range(200, 300); + + switch (w->shift) { + case CS48L32_IN1L_EN_SHIFT: + snd_soc_component_update_bits(component, + CS48L32_ADC1L_ANA_CONTROL1, + CS48L32_ADC1x_INT_ENA_FRC_MASK, + 0); + break; + case CS48L32_IN1R_EN_SHIFT: + snd_soc_component_update_bits(component, + CS48L32_ADC1R_ANA_CONTROL1, + CS48L32_ADC1x_INT_ENA_FRC_MASK, + 0); + break; + + default: + break; + } + cs48l32->in_up_pending--; + snd_soc_component_update_bits(component, reg, CS48L32_INx_MUTE_MASK, 0); + + /* Uncached write-only register, no need for update_bits */ + if (!cs48l32->in_up_pending) + snd_soc_component_write(component, cs48l32->in_vu_reg, CS48L32_IN_VU_MASK); + break; + case SND_SOC_DAPM_PRE_PMD: + snd_soc_component_update_bits(component, reg, + CS48L32_INx_MUTE_MASK, CS48L32_INx_MUTE_MASK); + snd_soc_component_write(component, cs48l32->in_vu_reg, CS48L32_IN_VU_MASK); + break; + default: + break; + } + + return 0; +} + +int cs48l32_in_put_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + int ret; + + ret = snd_soc_put_volsw(kcontrol, ucontrol); + if (ret < 0) + return ret; + + /* + * Uncached write-only register, no need for update_bits. + * Will fail if codec is off but that will be handled by cs48l32_in_ev + */ + snd_soc_component_write(component, cs48l32->in_vu_reg, CS48L32_IN_VU); + + return ret; +} + +static bool cs48l32_eq_filter_unstable(bool mode, __be16 in_a, __be16 in_b) +{ + s16 a = be16_to_cpu(in_a); + s16 b = be16_to_cpu(in_b); + + if (!mode) + return abs(a) >= 4096; + + if (abs(b) >= 4096) + return true; + + return (abs((a << 16) / (4096 - b)) >= 4096 << 4); +} + +int cs48l32_eq_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_mfd *mfd = cs48l32->mfd; + unsigned int mode = cs48l32->eq_mode[w->shift]; + unsigned int reg = CS48L32_EQ1_BAND1_COEFF1 + (68 * w->shift); + __be16 *data = &cs48l32->eq_coefficients[w->shift][0]; + int ret = 0; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (cs48l32_eq_filter_unstable(!!mode, data[1], data[0]) || + cs48l32_eq_filter_unstable(true, data[7], data[6]) || + cs48l32_eq_filter_unstable(true, data[13], data[12]) || + cs48l32_eq_filter_unstable(true, data[19], data[18]) || + cs48l32_eq_filter_unstable(false, data[25], data[24])) { + dev_err(cs48l32->dev, "Rejecting unstable EQ coefficients.\n"); + ret = -EINVAL; + } else { + ret = regmap_raw_write(mfd->regmap, reg, data, + CS48L32_EQ_BLOCK_SZ); + if (ret < 0) { + dev_err(cs48l32->dev, "Error writing EQ coefficients: %d\n", ret); + goto out; + } + + ret = snd_soc_component_update_bits(component, + CS48L32_EQ_CONTROL2, + w->mask, + mode << w->shift); + if (ret < 0) + dev_err(cs48l32->dev, "Error writing EQ mode: %d\n", ret); + } + break; + default: + break; + } + +out: + return ret; +} + +static int cs48l32_get_variable_u32_array(struct cs48l32 *cs48l32, + const char *propname, + u32 *dest, + int n_max, + int multiple) +{ + struct cs48l32_mfd *mfd = cs48l32->mfd; + int n, ret; + + n = device_property_read_u32_array(mfd->dev, propname, NULL, 0); + if (n == -EINVAL) { + return 0; /* missing, ignore */ + } else if (n < 0) { + dev_warn(cs48l32->dev, "%s malformed (%d)\n", propname, n); + return -EINVAL; + } else if ((n % multiple) != 0) { + dev_warn(cs48l32->dev, "%s not a multiple of %d entries\n", propname, multiple); + return -EINVAL; + } + + if (n > n_max) + n = n_max; + + ret = device_property_read_u32_array(mfd->dev, propname, dest, n); + + if (ret < 0) + return ret; + else + return n; +} + +static void cs48l32_prop_get_in_type(struct cs48l32 *cs48l32) +{ + u32 tmp[CS48L32_MAX_INPUT * CS48L32_MAX_MUXED_IN_CHANNELS]; + int n, i, in_idx, ch_idx; + + BUILD_BUG_ON(ARRAY_SIZE(cs48l32->in_type) != CS48L32_MAX_INPUT); + BUILD_BUG_ON(ARRAY_SIZE(cs48l32->in_type[0]) != + CS48L32_MAX_MUXED_IN_CHANNELS); + + n = cs48l32_get_variable_u32_array(cs48l32, + "cirrus,in-type", + tmp, + ARRAY_SIZE(tmp), + CS48L32_MAX_MUXED_IN_CHANNELS); + if (n < 0) + return; + + in_idx = 0; + ch_idx = 0; + for (i = 0; i < n; ++i) { + cs48l32->in_type[in_idx][ch_idx] = tmp[i]; + + if (++ch_idx == CS48L32_MAX_MUXED_IN_CHANNELS) { + ch_idx = 0; + ++in_idx; + } + } +} + +static void cs48l32_prop_get(struct cs48l32 *cs48l32) +{ + int ret; + + ret = cs48l32_get_variable_u32_array(cs48l32, + "cirrus,max-channels-clocked", + cs48l32->max_channels_clocked, + ARRAY_SIZE(cs48l32->max_channels_clocked), + 1); + if (ret < 0) + return; + + cs48l32_prop_get_in_type(cs48l32); + + cs48l32_get_variable_u32_array(cs48l32, + "cirrus,pdm-sup", + cs48l32->pdm_sup, + ARRAY_SIZE(cs48l32->pdm_sup), + 1); +} + +int cs48l32_init_inputs(struct snd_soc_component *component) +{ + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + struct cs48l32_mfd *mfd = cs48l32->mfd; + unsigned int ana_mode_l, ana_mode_r, dig_mode; + int i; + + /* + * Initialize input modes from the A settings. For muxed inputs the + * B settings will be applied if the mux is changed + */ + for (i = 0; i < cs48l32->max_analogue_inputs; i++) { + dev_dbg(cs48l32->dev, "IN%d type %u:%u:%u:%u\n", i + 1, + cs48l32->in_type[i][0], + cs48l32->in_type[i][1], + cs48l32->in_type[i][2], + cs48l32->in_type[i][3]); + + switch (cs48l32->in_type[i][0]) { + case CS48L32_IN_TYPE_DIFF: + ana_mode_l = 0; + break; + case CS48L32_IN_TYPE_SE: + ana_mode_l = 1 << CS48L32_INx_SRC_SHIFT; + break; + default: + dev_warn(cs48l32->dev, "IN%dL_1 Illegal in_type %u ignored\n", + i + 1, cs48l32->in_type[i][0]); + continue; + } + + switch (cs48l32->in_type[i][1]) { + case CS48L32_IN_TYPE_DIFF: + ana_mode_r = 0; + break; + case CS48L32_IN_TYPE_SE: + ana_mode_r = 1 << CS48L32_INx_SRC_SHIFT; + break; + default: + dev_warn(cs48l32->dev, "IN%dR_1 Illegal in_type %u ignored\n", + i + 1, cs48l32->in_type[i][1]); + continue; + } + + dev_dbg(cs48l32->dev, "IN%d_1 Analogue mode=0x%x,0x%x\n", + i + 1, ana_mode_l, ana_mode_r); + + regmap_update_bits(mfd->regmap, + CS48L32_IN1L_CONTROL1 + (i * 0x40), + CS48L32_INx_SRC_MASK, + ana_mode_l); + + regmap_update_bits(mfd->regmap, + CS48L32_IN1R_CONTROL1 + (i * 0x40), + CS48L32_INx_SRC_MASK, + ana_mode_r); + } + + for (i = 0; i < cs48l32->max_pdm_sup; i++) { + dig_mode = cs48l32->pdm_sup[i] << CS48L32_IN1_PDM_SUP_SHIFT; + + dev_dbg(cs48l32->dev, "IN%d PDM_SUP=0x%x\n", i + 1, dig_mode); + + regmap_update_bits(mfd->regmap, + CS48L32_INPUT1_CONTROL1 + (i * 0x40), + CS48L32_IN1_PDM_SUP_MASK, dig_mode); + } + + return 0; +} + +int cs48l32_init_dai(struct cs48l32 *cs48l32, int id) +{ + struct cs48l32_dai_priv *dai_priv = &cs48l32->dai[id]; + + dai_priv->clk = CS48L32_CLK_SYSCLK_1; + dai_priv->constraint = cs48l32_constraint; + + return 0; +} + +int cs48l32_init_eq(struct cs48l32 *cs48l32) +{ + struct cs48l32_mfd *mfd = cs48l32->mfd; + unsigned int reg = CS48L32_EQ1_BAND1_COEFF1, mode; + __be16 *data; + int i, ret; + + ret = regmap_read(mfd->regmap, CS48L32_EQ_CONTROL2, &mode); + if (ret < 0) { + dev_err(cs48l32->dev, "Error reading EQ mode: %d\n", ret); + goto out; + } + + for (i = 0; i < 4; ++i) { + cs48l32->eq_mode[i] = (mode >> i) & 0x1; + + data = &cs48l32->eq_coefficients[i][0]; + ret = regmap_raw_read(mfd->regmap, reg + (i * 68), data, + CS48L32_EQ_BLOCK_SZ); + if (ret < 0) { + dev_err(cs48l32->dev, "Error reading EQ coefficients: %d\n", ret); + goto out; + } + } + +out: + return ret; +} + +int cs48l32_core_init(struct cs48l32 *cs48l32) +{ + BUILD_BUG_ON(ARRAY_SIZE(cs48l32_mixer_texts) != CS48L32_NUM_MIXER_INPUTS); + BUILD_BUG_ON(ARRAY_SIZE(cs48l32_mixer_values) != CS48L32_NUM_MIXER_INPUTS); + BUILD_BUG_ON(cs48l32_sample_rate_text[CS48L32_SAMPLE_RATE_ENUM_SIZE - 1] == NULL); + BUILD_BUG_ON(cs48l32_sample_rate_val[CS48L32_SAMPLE_RATE_ENUM_SIZE - 1] == 0); + BUILD_BUG_ON(ARRAY_SIZE(cs48l32_in_texts) != CS48L32_MAX_INPUT); + + cs48l32_prop_get(cs48l32); + + mutex_init(&cs48l32->rate_lock); + + return 0; +} + +int cs48l32_core_destroy(struct cs48l32 *cs48l32) +{ + mutex_destroy(&cs48l32->rate_lock); + + return 0; +} diff --git a/sound/soc/codecs/cs48l32.c b/sound/soc/codecs/cs48l32.c new file mode 100644 index 000000000000..64763772b881 --- /dev/null +++ b/sound/soc/codecs/cs48l32.c @@ -0,0 +1,1211 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// ALSA SoC Audio driver for CS48L32 codec. +// +// Copyright (C) 2018-2020, 2022 Cirrus Logic, Inc. and +// Cirrus Logic International Semiconductor Ltd. + +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/init.h> +#include <linux/irqchip/irq-cirrus-cs48l32.h> +#include <linux/mfd/cs48l32/core.h> +#include <linux/mfd/cs48l32/registers.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pm.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/tlv.h> + +#include "cs48l32.h" +#include "wm_adsp.h" + +static const struct cs_dsp_region cs48l32_dsp1_regions[] = { + { .type = WMFW_HALO_PM_PACKED, .base = 0x3800000 }, + { .type = WMFW_HALO_XM_PACKED, .base = 0x2000000 }, + { .type = WMFW_ADSP2_XM, .base = 0x2800000 }, + { .type = WMFW_HALO_YM_PACKED, .base = 0x2C00000 }, + { .type = WMFW_ADSP2_YM, .base = 0x3400000 }, +}; + +static const struct cs48l32_dsp_power_reg_block cs48l32_dsp1_sram_ext_regs[] = { + { CS48L32_DSP1_XM_SRAM_IBUS_SETUP_1, CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24 }, + { CS48L32_DSP1_YM_SRAM_IBUS_SETUP_1, CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8 }, + { CS48L32_DSP1_PM_SRAM_IBUS_SETUP_1, CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7 }, +}; + +static const unsigned int cs48l32_dsp1_sram_pwd_regs[] = { + CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0, + CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0, + CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0, +}; + +static const struct cs48l32_dsp_power_regs cs48l32_dsp_sram_regs = { + .ext = cs48l32_dsp1_sram_ext_regs, + .n_ext = ARRAY_SIZE(cs48l32_dsp1_sram_ext_regs), + .pwd = cs48l32_dsp1_sram_pwd_regs, + .n_pwd = ARRAY_SIZE(cs48l32_dsp1_sram_pwd_regs), +}; + +static const struct snd_kcontrol_new cs48l32_snd_controls[] = { +SOC_ENUM("IN1 OSR", cs48l32_in_dmic_osr[0]), +SOC_ENUM("IN2 OSR", cs48l32_in_dmic_osr[1]), + +SOC_SINGLE_RANGE_TLV("IN1L Volume", CS48L32_IN1L_CONTROL2, + CS48L32_INx_PGA_VOL_SHIFT, 0x40, 0x5f, 0, cs48l32_ana_tlv), +SOC_SINGLE_RANGE_TLV("IN1R Volume", CS48L32_IN1R_CONTROL2, + CS48L32_INx_PGA_VOL_SHIFT, 0x40, 0x5f, 0, cs48l32_ana_tlv), + +SOC_ENUM("IN HPF Cutoff Frequency", cs48l32_in_hpf_cut_enum), + +SOC_SINGLE_EXT("IN1L LP Switch", CS48L32_IN1L_CONTROL1, CS48L32_INx_LP_MODE_SHIFT, + 1, 0, snd_soc_get_volsw, cs48l32_low_power_mode_put), +SOC_SINGLE_EXT("IN1R LP Switch", CS48L32_IN1R_CONTROL1, CS48L32_INx_LP_MODE_SHIFT, + 1, 0, snd_soc_get_volsw, cs48l32_low_power_mode_put), + +SOC_SINGLE("IN1L HPF Switch", CS48L32_IN1L_CONTROL1, CS48L32_INx_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN1R HPF Switch", CS48L32_IN1R_CONTROL1, CS48L32_INx_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2L HPF Switch", CS48L32_IN2L_CONTROL1, CS48L32_INx_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2R HPF Switch", CS48L32_IN2R_CONTROL1, CS48L32_INx_HPF_SHIFT, 1, 0), + +SOC_SINGLE_EXT_TLV("IN1L Digital Volume", CS48L32_IN1L_CONTROL2, + CS48L32_INx_VOL_SHIFT, 0xbf, 0, snd_soc_get_volsw, + cs48l32_in_put_volsw, cs48l32_digital_tlv), +SOC_SINGLE_EXT_TLV("IN1R Digital Volume", CS48L32_IN1R_CONTROL2, + CS48L32_INx_VOL_SHIFT, 0xbf, 0, snd_soc_get_volsw, + cs48l32_in_put_volsw, cs48l32_digital_tlv), +SOC_SINGLE_EXT_TLV("IN2L Digital Volume", CS48L32_IN2L_CONTROL2, + CS48L32_INx_VOL_SHIFT, 0xbf, 0, snd_soc_get_volsw, + cs48l32_in_put_volsw, cs48l32_digital_tlv), +SOC_SINGLE_EXT_TLV("IN2R Digital Volume", CS48L32_IN2R_CONTROL2, + CS48L32_INx_VOL_SHIFT, 0xbf, 0, snd_soc_get_volsw, + cs48l32_in_put_volsw, cs48l32_digital_tlv), + +SOC_ENUM("Input Ramp Up", cs48l32_in_vi_ramp), +SOC_ENUM("Input Ramp Down", cs48l32_in_vd_ramp), + +CS48L32_RATE_ENUM("Ultrasonic 1 Rate", cs48l32_us_output_rate[0]), +CS48L32_RATE_ENUM("Ultrasonic 2 Rate", cs48l32_us_output_rate[1]), + +SOC_ENUM("Ultrasonic 1 Freq", cs48l32_us_freq[0]), +SOC_ENUM("Ultrasonic 2 Freq", cs48l32_us_freq[1]), + +SOC_SINGLE_TLV("Ultrasonic 1 Volume", CS48L32_US1_CONTROL, CS48L32_US1_GAIN_SHIFT, + 3, 0, cs48l32_us_tlv), +SOC_SINGLE_TLV("Ultrasonic 2 Volume", CS48L32_US2_CONTROL, CS48L32_US1_GAIN_SHIFT, + 3, 0, cs48l32_us_tlv), + +SOC_ENUM("Ultrasonic 1 Activity Detect Threshold", cs48l32_us_det_thr[0]), +SOC_ENUM("Ultrasonic 2 Activity Detect Threshold", cs48l32_us_det_thr[1]), + +SOC_ENUM("Ultrasonic 1 Activity Detect Pulse Length", cs48l32_us_det_num[0]), +SOC_ENUM("Ultrasonic 2 Activity Detect Pulse Length", cs48l32_us_det_num[1]), + +SOC_ENUM("Ultrasonic 1 Activity Detect Hold", cs48l32_us_det_hold[0]), +SOC_ENUM("Ultrasonic 2 Activity Detect Hold", cs48l32_us_det_hold[1]), + +SOC_ENUM("Ultrasonic 1 Activity Detect Decay", cs48l32_us_det_dcy[0]), +SOC_ENUM("Ultrasonic 2 Activity Detect Decay", cs48l32_us_det_dcy[1]), + +SOC_SINGLE("Ultrasonic 1 Activity Detect LPF Switch", + CS48L32_US1_DET_CONTROL, CS48L32_US1_DET_LPF_SHIFT, 1, 0), +SOC_SINGLE("Ultrasonic 2 Activity Detect LPF Switch", + CS48L32_US2_DET_CONTROL, CS48L32_US1_DET_LPF_SHIFT, 1, 0), + +SOC_ENUM("Ultrasonic 1 Activity Detect LPF Cut-off", cs48l32_us_det_lpf_cut[0]), +SOC_ENUM("Ultrasonic 2 Activity Detect LPF Cut-off", cs48l32_us_det_lpf_cut[1]), + +CS48L32_MIXER_CONTROLS("EQ1", CS48L32_EQ1_INPUT1), +CS48L32_MIXER_CONTROLS("EQ2", CS48L32_EQ2_INPUT1), +CS48L32_MIXER_CONTROLS("EQ3", CS48L32_EQ3_INPUT1), +CS48L32_MIXER_CONTROLS("EQ4", CS48L32_EQ4_INPUT1), + +SOC_ENUM_EXT("EQ1 Mode", cs48l32_eq_mode[0], cs48l32_eq_mode_get, cs48l32_eq_mode_put), + +CS48L32_EQ_COEFF_CONTROLS(EQ1), + +SOC_SINGLE_TLV("EQ1 B1 Volume", CS48L32_EQ1_GAIN1, 0, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ1 B2 Volume", CS48L32_EQ1_GAIN1, 8, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ1 B3 Volume", CS48L32_EQ1_GAIN1, 16, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ1 B4 Volume", CS48L32_EQ1_GAIN1, 24, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ1 B5 Volume", CS48L32_EQ1_GAIN2, 0, 24, 0, cs48l32_eq_tlv), + +SOC_ENUM_EXT("EQ2 Mode", cs48l32_eq_mode[1], cs48l32_eq_mode_get, cs48l32_eq_mode_put), +CS48L32_EQ_COEFF_CONTROLS(EQ2), +SOC_SINGLE_TLV("EQ2 B1 Volume", CS48L32_EQ2_GAIN1, 0, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ2 B2 Volume", CS48L32_EQ2_GAIN1, 8, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ2 B3 Volume", CS48L32_EQ2_GAIN1, 16, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ2 B4 Volume", CS48L32_EQ2_GAIN1, 24, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ2 B5 Volume", CS48L32_EQ2_GAIN2, 0, 24, 0, cs48l32_eq_tlv), + +SOC_ENUM_EXT("EQ3 Mode", cs48l32_eq_mode[2], cs48l32_eq_mode_get, cs48l32_eq_mode_put), +CS48L32_EQ_COEFF_CONTROLS(EQ3), +SOC_SINGLE_TLV("EQ3 B1 Volume", CS48L32_EQ3_GAIN1, 0, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ3 B2 Volume", CS48L32_EQ3_GAIN1, 8, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ3 B3 Volume", CS48L32_EQ3_GAIN1, 16, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ3 B4 Volume", CS48L32_EQ3_GAIN1, 24, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ3 B5 Volume", CS48L32_EQ3_GAIN2, 0, 24, 0, cs48l32_eq_tlv), + +SOC_ENUM_EXT("EQ4 Mode", cs48l32_eq_mode[3], cs48l32_eq_mode_get, cs48l32_eq_mode_put), +CS48L32_EQ_COEFF_CONTROLS(EQ4), +SOC_SINGLE_TLV("EQ4 B1 Volume", CS48L32_EQ4_GAIN1, 0, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ4 B2 Volume", CS48L32_EQ4_GAIN1, 8, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ4 B3 Volume", CS48L32_EQ4_GAIN1, 16, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ4 B4 Volume", CS48L32_EQ4_GAIN1, 24, 24, 0, cs48l32_eq_tlv), +SOC_SINGLE_TLV("EQ4 B5 Volume", CS48L32_EQ4_GAIN2, 0, 24, 0, cs48l32_eq_tlv), + +CS48L32_MIXER_CONTROLS("DRC1L", CS48L32_DRC1L_INPUT1), +CS48L32_MIXER_CONTROLS("DRC1R", CS48L32_DRC1R_INPUT1), +CS48L32_MIXER_CONTROLS("DRC2L", CS48L32_DRC2L_INPUT1), +CS48L32_MIXER_CONTROLS("DRC2R", CS48L32_DRC2R_INPUT1), + +SND_SOC_BYTES_MASK("DRC1 Coefficients", CS48L32_DRC1_CONTROL1, 4, + BIT(CS48L32_DRC1R_EN_SHIFT) | BIT(CS48L32_DRC1L_EN_SHIFT)), +SND_SOC_BYTES_MASK("DRC2 Coefficients", CS48L32_DRC2_CONTROL1, 4, + BIT(CS48L32_DRC1R_EN_SHIFT) | BIT(CS48L32_DRC1L_EN_SHIFT)), + +CS48L32_MIXER_CONTROLS("LHPF1", CS48L32_LHPF1_INPUT1), +CS48L32_MIXER_CONTROLS("LHPF2", CS48L32_LHPF2_INPUT1), +CS48L32_MIXER_CONTROLS("LHPF3", CS48L32_LHPF3_INPUT1), +CS48L32_MIXER_CONTROLS("LHPF4", CS48L32_LHPF4_INPUT1), + +CS48L32_LHPF_CONTROL("LHPF1 Coefficients", CS48L32_LHPF1_COEFF), +CS48L32_LHPF_CONTROL("LHPF2 Coefficients", CS48L32_LHPF2_COEFF), +CS48L32_LHPF_CONTROL("LHPF3 Coefficients", CS48L32_LHPF3_COEFF), +CS48L32_LHPF_CONTROL("LHPF4 Coefficients", CS48L32_LHPF4_COEFF), + +SOC_ENUM("LHPF1 Mode", cs48l32_lhpf_mode[0]), +SOC_ENUM("LHPF2 Mode", cs48l32_lhpf_mode[1]), +SOC_ENUM("LHPF3 Mode", cs48l32_lhpf_mode[2]), +SOC_ENUM("LHPF4 Mode", cs48l32_lhpf_mode[3]), + +CS48L32_RATE_CONTROL("Sample Rate 1", 1), +CS48L32_RATE_CONTROL("Sample Rate 2", 2), +CS48L32_RATE_CONTROL("Sample Rate 3", 3), +CS48L32_RATE_CONTROL("Sample Rate 4", 4), + +CS48L32_RATE_ENUM("FX Rate", cs48l32_fx_rate), + +CS48L32_RATE_ENUM("ISRC1 FSL", cs48l32_isrc_fsl[0]), +CS48L32_RATE_ENUM("ISRC2 FSL", cs48l32_isrc_fsl[1]), +CS48L32_RATE_ENUM("ISRC3 FSL", cs48l32_isrc_fsl[2]), +CS48L32_RATE_ENUM("ISRC1 FSH", cs48l32_isrc_fsh[0]), +CS48L32_RATE_ENUM("ISRC2 FSH", cs48l32_isrc_fsh[1]), +CS48L32_RATE_ENUM("ISRC3 FSH", cs48l32_isrc_fsh[2]), + +SOC_ENUM("AUXPDM1 Rate", cs48l32_auxpdm1_freq), +SOC_ENUM("AUXPDM2 Rate", cs48l32_auxpdm2_freq), + +SOC_ENUM_EXT("IN1L Rate", cs48l32_input_rate[0], snd_soc_get_enum_double, cs48l32_in_rate_put), +SOC_ENUM_EXT("IN1R Rate", cs48l32_input_rate[1], snd_soc_get_enum_double, cs48l32_in_rate_put), +SOC_ENUM_EXT("IN2L Rate", cs48l32_input_rate[2], snd_soc_get_enum_double, cs48l32_in_rate_put), +SOC_ENUM_EXT("IN2R Rate", cs48l32_input_rate[3], snd_soc_get_enum_double, cs48l32_in_rate_put), + +CS48L32_RATE_ENUM("Noise Generator Rate", noise_gen_rate), + +SOC_SINGLE_TLV("Noise Generator Volume", CS48L32_COMFORT_NOISE_GENERATOR, + CS48L32_NOISE_GEN_GAIN_SHIFT, 0x12, 0, cs48l32_noise_tlv), + +CS48L32_MIXER_CONTROLS("ASP1TX1", CS48L32_ASP1TX1_INPUT1), +CS48L32_MIXER_CONTROLS("ASP1TX2", CS48L32_ASP1TX2_INPUT1), +CS48L32_MIXER_CONTROLS("ASP1TX3", CS48L32_ASP1TX3_INPUT1), +CS48L32_MIXER_CONTROLS("ASP1TX4", CS48L32_ASP1TX4_INPUT1), +CS48L32_MIXER_CONTROLS("ASP1TX5", CS48L32_ASP1TX5_INPUT1), +CS48L32_MIXER_CONTROLS("ASP1TX6", CS48L32_ASP1TX6_INPUT1), +CS48L32_MIXER_CONTROLS("ASP1TX7", CS48L32_ASP1TX7_INPUT1), +CS48L32_MIXER_CONTROLS("ASP1TX8", CS48L32_ASP1TX8_INPUT1), + +CS48L32_MIXER_CONTROLS("ASP2TX1", CS48L32_ASP2TX1_INPUT1), +CS48L32_MIXER_CONTROLS("ASP2TX2", CS48L32_ASP2TX2_INPUT1), +CS48L32_MIXER_CONTROLS("ASP2TX3", CS48L32_ASP2TX3_INPUT1), +CS48L32_MIXER_CONTROLS("ASP2TX4", CS48L32_ASP2TX4_INPUT1), + +WM_ADSP2_PRELOAD_SWITCH("DSP1", 1), + +CS48L32_MIXER_CONTROLS("DSP1RX1", CS48L32_DSP1RX1_INPUT1), +CS48L32_MIXER_CONTROLS("DSP1RX2", CS48L32_DSP1RX2_INPUT1), +CS48L32_MIXER_CONTROLS("DSP1RX3", CS48L32_DSP1RX3_INPUT1), +CS48L32_MIXER_CONTROLS("DSP1RX4", CS48L32_DSP1RX4_INPUT1), +CS48L32_MIXER_CONTROLS("DSP1RX5", CS48L32_DSP1RX5_INPUT1), +CS48L32_MIXER_CONTROLS("DSP1RX6", CS48L32_DSP1RX6_INPUT1), +CS48L32_MIXER_CONTROLS("DSP1RX7", CS48L32_DSP1RX7_INPUT1), +CS48L32_MIXER_CONTROLS("DSP1RX8", CS48L32_DSP1RX8_INPUT1), + +WM_ADSP_FW_CONTROL("DSP1", 0), + +CS48L32_DSP_RATE_CONTROL("DSP1RX1", 0), +CS48L32_DSP_RATE_CONTROL("DSP1RX2", 1), +CS48L32_DSP_RATE_CONTROL("DSP1RX3", 2), +CS48L32_DSP_RATE_CONTROL("DSP1RX4", 3), +CS48L32_DSP_RATE_CONTROL("DSP1RX5", 4), +CS48L32_DSP_RATE_CONTROL("DSP1RX6", 5), +CS48L32_DSP_RATE_CONTROL("DSP1RX7", 6), +CS48L32_DSP_RATE_CONTROL("DSP1RX8", 7), +CS48L32_DSP_RATE_CONTROL("DSP1TX1", 8), +CS48L32_DSP_RATE_CONTROL("DSP1TX2", 9), +CS48L32_DSP_RATE_CONTROL("DSP1TX3", 10), +CS48L32_DSP_RATE_CONTROL("DSP1TX4", 11), +CS48L32_DSP_RATE_CONTROL("DSP1TX5", 12), +CS48L32_DSP_RATE_CONTROL("DSP1TX6", 13), +CS48L32_DSP_RATE_CONTROL("DSP1TX7", 14), +CS48L32_DSP_RATE_CONTROL("DSP1TX8", 15), +}; + +CS48L32_MIXER_ENUMS(EQ1, CS48L32_EQ1_INPUT1); +CS48L32_MIXER_ENUMS(EQ2, CS48L32_EQ2_INPUT1); +CS48L32_MIXER_ENUMS(EQ3, CS48L32_EQ3_INPUT1); +CS48L32_MIXER_ENUMS(EQ4, CS48L32_EQ4_INPUT1); + +CS48L32_MIXER_ENUMS(DRC1L, CS48L32_DRC1L_INPUT1); +CS48L32_MIXER_ENUMS(DRC1R, CS48L32_DRC1R_INPUT1); +CS48L32_MIXER_ENUMS(DRC2L, CS48L32_DRC2L_INPUT1); +CS48L32_MIXER_ENUMS(DRC2R, CS48L32_DRC2R_INPUT1); + +CS48L32_MIXER_ENUMS(LHPF1, CS48L32_LHPF1_INPUT1); +CS48L32_MIXER_ENUMS(LHPF2, CS48L32_LHPF2_INPUT1); +CS48L32_MIXER_ENUMS(LHPF3, CS48L32_LHPF3_INPUT1); +CS48L32_MIXER_ENUMS(LHPF4, CS48L32_LHPF4_INPUT1); + +CS48L32_MIXER_ENUMS(ASP1TX1, CS48L32_ASP1TX1_INPUT1); +CS48L32_MIXER_ENUMS(ASP1TX2, CS48L32_ASP1TX2_INPUT1); +CS48L32_MIXER_ENUMS(ASP1TX3, CS48L32_ASP1TX3_INPUT1); +CS48L32_MIXER_ENUMS(ASP1TX4, CS48L32_ASP1TX4_INPUT1); +CS48L32_MIXER_ENUMS(ASP1TX5, CS48L32_ASP1TX5_INPUT1); +CS48L32_MIXER_ENUMS(ASP1TX6, CS48L32_ASP1TX6_INPUT1); +CS48L32_MIXER_ENUMS(ASP1TX7, CS48L32_ASP1TX7_INPUT1); +CS48L32_MIXER_ENUMS(ASP1TX8, CS48L32_ASP1TX8_INPUT1); + +CS48L32_MIXER_ENUMS(ASP2TX1, CS48L32_ASP2TX1_INPUT1); +CS48L32_MIXER_ENUMS(ASP2TX2, CS48L32_ASP2TX2_INPUT1); +CS48L32_MIXER_ENUMS(ASP2TX3, CS48L32_ASP2TX3_INPUT1); +CS48L32_MIXER_ENUMS(ASP2TX4, CS48L32_ASP2TX4_INPUT1); + +CS48L32_MUX_ENUMS(ISRC1INT1, CS48L32_ISRC1INT1_INPUT1); +CS48L32_MUX_ENUMS(ISRC1INT2, CS48L32_ISRC1INT2_INPUT1); +CS48L32_MUX_ENUMS(ISRC1INT3, CS48L32_ISRC1INT3_INPUT1); +CS48L32_MUX_ENUMS(ISRC1INT4, CS48L32_ISRC1INT4_INPUT1); + +CS48L32_MUX_ENUMS(ISRC1DEC1, CS48L32_ISRC1DEC1_INPUT1); +CS48L32_MUX_ENUMS(ISRC1DEC2, CS48L32_ISRC1DEC2_INPUT1); +CS48L32_MUX_ENUMS(ISRC1DEC3, CS48L32_ISRC1DEC3_INPUT1); +CS48L32_MUX_ENUMS(ISRC1DEC4, CS48L32_ISRC1DEC4_INPUT1); + +CS48L32_MUX_ENUMS(ISRC2INT1, CS48L32_ISRC2INT1_INPUT1); +CS48L32_MUX_ENUMS(ISRC2INT2, CS48L32_ISRC2INT2_INPUT1); + +CS48L32_MUX_ENUMS(ISRC2DEC1, CS48L32_ISRC2DEC1_INPUT1); +CS48L32_MUX_ENUMS(ISRC2DEC2, CS48L32_ISRC2DEC2_INPUT1); + +CS48L32_MUX_ENUMS(ISRC3INT1, CS48L32_ISRC3INT1_INPUT1); +CS48L32_MUX_ENUMS(ISRC3INT2, CS48L32_ISRC3INT2_INPUT1); + +CS48L32_MUX_ENUMS(ISRC3DEC1, CS48L32_ISRC3DEC1_INPUT1); +CS48L32_MUX_ENUMS(ISRC3DEC2, CS48L32_ISRC3DEC2_INPUT1); + +CS48L32_MIXER_ENUMS(DSP1RX1, CS48L32_DSP1RX1_INPUT1); +CS48L32_MIXER_ENUMS(DSP1RX2, CS48L32_DSP1RX2_INPUT1); +CS48L32_MIXER_ENUMS(DSP1RX3, CS48L32_DSP1RX3_INPUT1); +CS48L32_MIXER_ENUMS(DSP1RX4, CS48L32_DSP1RX4_INPUT1); +CS48L32_MIXER_ENUMS(DSP1RX5, CS48L32_DSP1RX5_INPUT1); +CS48L32_MIXER_ENUMS(DSP1RX6, CS48L32_DSP1RX6_INPUT1); +CS48L32_MIXER_ENUMS(DSP1RX7, CS48L32_DSP1RX7_INPUT1); +CS48L32_MIXER_ENUMS(DSP1RX8, CS48L32_DSP1RX8_INPUT1); + +static int cs48l32_dsp_mem_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + return cs48l32_dsp_memory_enable(cs48l32, &cs48l32_dsp_sram_regs); + case SND_SOC_DAPM_PRE_PMD: + cs48l32_dsp_memory_disable(cs48l32, &cs48l32_dsp_sram_regs); + return 0; + default: + return 0; + } +} + +static const struct snd_soc_dapm_widget cs48l32_dapm_widgets[] = { +SND_SOC_DAPM_SUPPLY("SYSCLK", CS48L32_SYSTEM_CLOCK1, CS48L32_SYSCLK_EN_SHIFT, 0, + cs48l32_sysclk_ev, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_SUPPLY("OPCLK", CS48L32_OUTPUT_SYS_CLK, CS48L32_OPCLK_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_REGULATOR_SUPPLY("VDD_CP", 20, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("VOUT_MIC", 0, SND_SOC_DAPM_REGULATOR_BYPASS), + +SND_SOC_DAPM_SUPPLY("MICBIAS1", CS48L32_MICBIAS_CTRL1, CS48L32_MICB1_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_SUPPLY("MICBIAS1A", CS48L32_MICBIAS_CTRL5, CS48L32_MICB1A_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS1B", CS48L32_MICBIAS_CTRL5, CS48L32_MICB1B_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS1C", CS48L32_MICBIAS_CTRL5, CS48L32_MICB1C_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_SUPPLY("DSP1MEM", SND_SOC_NOPM, 0, 0, cs48l32_dsp_mem_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + +CS48L32_DSP_FREQ_WIDGET_EV("DSP1", 0, cs48l32_dsp_freq_ev), + +SND_SOC_DAPM_SIGGEN("TONE"), +SND_SOC_DAPM_SIGGEN("NOISE"), + +SND_SOC_DAPM_INPUT("IN1LN_1"), +SND_SOC_DAPM_INPUT("IN1LN_2"), +SND_SOC_DAPM_INPUT("IN1LP_1"), +SND_SOC_DAPM_INPUT("IN1LP_2"), +SND_SOC_DAPM_INPUT("IN1RN_1"), +SND_SOC_DAPM_INPUT("IN1RN_2"), +SND_SOC_DAPM_INPUT("IN1RP_1"), +SND_SOC_DAPM_INPUT("IN1RP_2"), +SND_SOC_DAPM_INPUT("IN1_PDMCLK"), +SND_SOC_DAPM_INPUT("IN1_PDMDATA"), + +SND_SOC_DAPM_INPUT("IN2_PDMCLK"), +SND_SOC_DAPM_INPUT("IN2_PDMDATA"), + +SND_SOC_DAPM_MUX("Ultrasonic 1 Input", SND_SOC_NOPM, 0, 0, &cs48l32_us_inmux[0]), +SND_SOC_DAPM_MUX("Ultrasonic 2 Input", SND_SOC_NOPM, 0, 0, &cs48l32_us_inmux[1]), + +SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"), +SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"), + +SND_SOC_DAPM_OUTPUT("DSP Trigger Out"), + +SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &cs48l32_inmux[0]), +SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &cs48l32_inmux[1]), + +SND_SOC_DAPM_MUX("IN1L Mode", SND_SOC_NOPM, 0, 0, &cs48l32_dmode_mux[0]), +SND_SOC_DAPM_MUX("IN1R Mode", SND_SOC_NOPM, 0, 0, &cs48l32_dmode_mux[0]), + +SND_SOC_DAPM_AIF_OUT("ASP1TX1", NULL, 0, CS48L32_ASP1_ENABLES1, 0, 0), +SND_SOC_DAPM_AIF_OUT("ASP1TX2", NULL, 1, CS48L32_ASP1_ENABLES1, 1, 0), +SND_SOC_DAPM_AIF_OUT("ASP1TX3", NULL, 2, CS48L32_ASP1_ENABLES1, 2, 0), +SND_SOC_DAPM_AIF_OUT("ASP1TX4", NULL, 3, CS48L32_ASP1_ENABLES1, 3, 0), +SND_SOC_DAPM_AIF_OUT("ASP1TX5", NULL, 4, CS48L32_ASP1_ENABLES1, 4, 0), +SND_SOC_DAPM_AIF_OUT("ASP1TX6", NULL, 5, CS48L32_ASP1_ENABLES1, 5, 0), +SND_SOC_DAPM_AIF_OUT("ASP1TX7", NULL, 6, CS48L32_ASP1_ENABLES1, 6, 0), +SND_SOC_DAPM_AIF_OUT("ASP1TX8", NULL, 7, CS48L32_ASP1_ENABLES1, 7, 0), + +SND_SOC_DAPM_AIF_OUT("ASP2TX1", NULL, 0, CS48L32_ASP2_ENABLES1, 0, 0), +SND_SOC_DAPM_AIF_OUT("ASP2TX2", NULL, 1, CS48L32_ASP2_ENABLES1, 1, 0), +SND_SOC_DAPM_AIF_OUT("ASP2TX3", NULL, 2, CS48L32_ASP2_ENABLES1, 2, 0), +SND_SOC_DAPM_AIF_OUT("ASP2TX4", NULL, 3, CS48L32_ASP2_ENABLES1, 3, 0), + +SND_SOC_DAPM_SWITCH("AUXPDM1 Output", CS48L32_AUXPDM_CONTROL1, 0, 0, &cs48l32_auxpdm_switch[0]), +SND_SOC_DAPM_SWITCH("AUXPDM2 Output", CS48L32_AUXPDM_CONTROL1, 1, 0, &cs48l32_auxpdm_switch[1]), + +SND_SOC_DAPM_MUX("AUXPDM1 Input", SND_SOC_NOPM, 0, 0, &cs48l32_auxpdm_inmux[0]), +SND_SOC_DAPM_MUX("AUXPDM2 Input", SND_SOC_NOPM, 0, 0, &cs48l32_auxpdm_inmux[1]), + +SND_SOC_DAPM_MUX("AUXPDM1 Analog Input", SND_SOC_NOPM, 0, 0, + &cs48l32_auxpdm_analog_inmux[0]), +SND_SOC_DAPM_MUX("AUXPDM2 Analog Input", SND_SOC_NOPM, 0, 0, + &cs48l32_auxpdm_analog_inmux[1]), + +SND_SOC_DAPM_SWITCH("Ultrasonic 1 Activity Detect", CS48L32_US_CONTROL, + CS48L32_US1_DET_EN_SHIFT, 0, &cs48l32_us_switch[0]), +SND_SOC_DAPM_SWITCH("Ultrasonic 2 Activity Detect", CS48L32_US_CONTROL, + CS48L32_US1_DET_EN_SHIFT, 0, &cs48l32_us_switch[1]), + +/* + * mux_in widgets : arranged in the order of sources + * specified in CS48L32_MIXER_INPUT_ROUTES + */ +SND_SOC_DAPM_PGA("Tone Generator 1", CS48L32_TONE_GENERATOR1, 0, 0, NULL, 0), +SND_SOC_DAPM_PGA("Tone Generator 2", CS48L32_TONE_GENERATOR1, 1, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Noise Generator", CS48L32_COMFORT_NOISE_GENERATOR, + CS48L32_NOISE_GEN_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA_E("IN1L PGA", CS48L32_INPUT_CONTROL, CS48L32_IN1L_EN_SHIFT, + 0, NULL, 0, cs48l32_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN1R PGA", CS48L32_INPUT_CONTROL, CS48L32_IN1R_EN_SHIFT, + 0, NULL, 0, cs48l32_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2L PGA", CS48L32_INPUT_CONTROL, CS48L32_IN2L_EN_SHIFT, + 0, NULL, 0, cs48l32_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2R PGA", CS48L32_INPUT_CONTROL, CS48L32_IN2R_EN_SHIFT, + 0, NULL, 0, cs48l32_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + +SND_SOC_DAPM_AIF_IN("ASP1RX1", NULL, 0, CS48L32_ASP1_ENABLES1, 16, 0), +SND_SOC_DAPM_AIF_IN("ASP1RX2", NULL, 1, CS48L32_ASP1_ENABLES1, 17, 0), +SND_SOC_DAPM_AIF_IN("ASP1RX3", NULL, 2, CS48L32_ASP1_ENABLES1, 18, 0), +SND_SOC_DAPM_AIF_IN("ASP1RX4", NULL, 3, CS48L32_ASP1_ENABLES1, 19, 0), +SND_SOC_DAPM_AIF_IN("ASP1RX5", NULL, 4, CS48L32_ASP1_ENABLES1, 20, 0), +SND_SOC_DAPM_AIF_IN("ASP1RX6", NULL, 5, CS48L32_ASP1_ENABLES1, 21, 0), +SND_SOC_DAPM_AIF_IN("ASP1RX7", NULL, 6, CS48L32_ASP1_ENABLES1, 22, 0), +SND_SOC_DAPM_AIF_IN("ASP1RX8", NULL, 7, CS48L32_ASP1_ENABLES1, 23, 0), + +SND_SOC_DAPM_AIF_IN("ASP2RX1", NULL, 0, CS48L32_ASP2_ENABLES1, 16, 0), +SND_SOC_DAPM_AIF_IN("ASP2RX2", NULL, 1, CS48L32_ASP2_ENABLES1, 17, 0), +SND_SOC_DAPM_AIF_IN("ASP2RX3", NULL, 2, CS48L32_ASP2_ENABLES1, 18, 0), +SND_SOC_DAPM_AIF_IN("ASP2RX4", NULL, 3, CS48L32_ASP2_ENABLES1, 19, 0), + +SND_SOC_DAPM_PGA("ISRC1DEC1", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_DEC1_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC2", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_DEC2_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC3", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_DEC3_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC4", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_DEC4_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC1INT1", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_INT1_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT2", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_INT2_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT3", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_INT3_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT4", CS48L32_ISRC1_CONTROL2, CS48L32_ISRC1_INT4_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2DEC1", CS48L32_ISRC2_CONTROL2, CS48L32_ISRC1_DEC1_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC2", CS48L32_ISRC2_CONTROL2, CS48L32_ISRC1_DEC2_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2INT1", CS48L32_ISRC2_CONTROL2, CS48L32_ISRC1_INT1_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT2", CS48L32_ISRC2_CONTROL2, CS48L32_ISRC1_INT2_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC3DEC1", CS48L32_ISRC3_CONTROL2, CS48L32_ISRC1_DEC1_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3DEC2", CS48L32_ISRC3_CONTROL2, CS48L32_ISRC1_DEC2_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC3INT1", CS48L32_ISRC3_CONTROL2, CS48L32_ISRC1_INT1_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3INT2", CS48L32_ISRC3_CONTROL2, CS48L32_ISRC1_INT2_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA_E("EQ1", CS48L32_EQ_CONTROL1, 0, 0, NULL, 0, cs48l32_eq_ev, SND_SOC_DAPM_PRE_PMU), +SND_SOC_DAPM_PGA_E("EQ2", CS48L32_EQ_CONTROL1, 1, 0, NULL, 0, cs48l32_eq_ev, SND_SOC_DAPM_PRE_PMU), +SND_SOC_DAPM_PGA_E("EQ3", CS48L32_EQ_CONTROL1, 2, 0, NULL, 0, cs48l32_eq_ev, SND_SOC_DAPM_PRE_PMU), +SND_SOC_DAPM_PGA_E("EQ4", CS48L32_EQ_CONTROL1, 3, 0, NULL, 0, cs48l32_eq_ev, SND_SOC_DAPM_PRE_PMU), + +SND_SOC_DAPM_PGA("DRC1L", CS48L32_DRC1_CONTROL1, CS48L32_DRC1L_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("DRC1R", CS48L32_DRC1_CONTROL1, CS48L32_DRC1R_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("DRC2L", CS48L32_DRC2_CONTROL1, CS48L32_DRC1L_EN_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("DRC2R", CS48L32_DRC2_CONTROL1, CS48L32_DRC1R_EN_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("LHPF1", CS48L32_LHPF_CONTROL1, 0, 0, NULL, 0), +SND_SOC_DAPM_PGA("LHPF2", CS48L32_LHPF_CONTROL1, 1, 0, NULL, 0), +SND_SOC_DAPM_PGA("LHPF3", CS48L32_LHPF_CONTROL1, 2, 0, NULL, 0), +SND_SOC_DAPM_PGA("LHPF4", CS48L32_LHPF_CONTROL1, 3, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Ultrasonic 1", CS48L32_US_CONTROL, 0, 0, NULL, 0), +SND_SOC_DAPM_PGA("Ultrasonic 2", CS48L32_US_CONTROL, 1, 0, NULL, 0), + +WM_ADSP2("DSP1", 0, wm_adsp_early_event), + +/* end of ordered widget list */ + +CS48L32_MIXER_WIDGETS(EQ1, "EQ1"), +CS48L32_MIXER_WIDGETS(EQ2, "EQ2"), +CS48L32_MIXER_WIDGETS(EQ3, "EQ3"), +CS48L32_MIXER_WIDGETS(EQ4, "EQ4"), + +CS48L32_MIXER_WIDGETS(DRC1L, "DRC1L"), +CS48L32_MIXER_WIDGETS(DRC1R, "DRC1R"), +CS48L32_MIXER_WIDGETS(DRC2L, "DRC2L"), +CS48L32_MIXER_WIDGETS(DRC2R, "DRC2R"), + +SND_SOC_DAPM_SWITCH("DRC1 Activity Output", SND_SOC_NOPM, 0, 0, + &cs48l32_drc_activity_output_mux[0]), +SND_SOC_DAPM_SWITCH("DRC2 Activity Output", SND_SOC_NOPM, 0, 0, + &cs48l32_drc_activity_output_mux[1]), + +CS48L32_MIXER_WIDGETS(LHPF1, "LHPF1"), +CS48L32_MIXER_WIDGETS(LHPF2, "LHPF2"), +CS48L32_MIXER_WIDGETS(LHPF3, "LHPF3"), +CS48L32_MIXER_WIDGETS(LHPF4, "LHPF4"), + +CS48L32_MIXER_WIDGETS(ASP1TX1, "ASP1TX1"), +CS48L32_MIXER_WIDGETS(ASP1TX2, "ASP1TX2"), +CS48L32_MIXER_WIDGETS(ASP1TX3, "ASP1TX3"), +CS48L32_MIXER_WIDGETS(ASP1TX4, "ASP1TX4"), +CS48L32_MIXER_WIDGETS(ASP1TX5, "ASP1TX5"), +CS48L32_MIXER_WIDGETS(ASP1TX6, "ASP1TX6"), +CS48L32_MIXER_WIDGETS(ASP1TX7, "ASP1TX7"), +CS48L32_MIXER_WIDGETS(ASP1TX8, "ASP1TX8"), + +CS48L32_MIXER_WIDGETS(ASP2TX1, "ASP2TX1"), +CS48L32_MIXER_WIDGETS(ASP2TX2, "ASP2TX2"), +CS48L32_MIXER_WIDGETS(ASP2TX3, "ASP2TX3"), +CS48L32_MIXER_WIDGETS(ASP2TX4, "ASP2TX4"), + +CS48L32_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"), +CS48L32_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"), +CS48L32_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"), +CS48L32_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"), + +CS48L32_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"), +CS48L32_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"), +CS48L32_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"), +CS48L32_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"), + +CS48L32_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"), +CS48L32_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"), + +CS48L32_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"), +CS48L32_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"), + +CS48L32_MUX_WIDGETS(ISRC3DEC1, "ISRC3DEC1"), +CS48L32_MUX_WIDGETS(ISRC3DEC2, "ISRC3DEC2"), + +CS48L32_MUX_WIDGETS(ISRC3INT1, "ISRC3INT1"), +CS48L32_MUX_WIDGETS(ISRC3INT2, "ISRC3INT2"), + +CS48L32_MIXER_WIDGETS(DSP1RX1, "DSP1RX1"), +CS48L32_MIXER_WIDGETS(DSP1RX2, "DSP1RX2"), +CS48L32_MIXER_WIDGETS(DSP1RX3, "DSP1RX3"), +CS48L32_MIXER_WIDGETS(DSP1RX4, "DSP1RX4"), +CS48L32_MIXER_WIDGETS(DSP1RX5, "DSP1RX5"), +CS48L32_MIXER_WIDGETS(DSP1RX6, "DSP1RX6"), +CS48L32_MIXER_WIDGETS(DSP1RX7, "DSP1RX7"), +CS48L32_MIXER_WIDGETS(DSP1RX8, "DSP1RX8"), + +SND_SOC_DAPM_SWITCH("DSP1 Trigger Output", SND_SOC_NOPM, 0, 0, + &cs48l32_dsp_trigger_output_mux[0]), + +SND_SOC_DAPM_OUTPUT("AUXPDM1_CLK"), +SND_SOC_DAPM_OUTPUT("AUXPDM1_DOUT"), +SND_SOC_DAPM_OUTPUT("AUXPDM2_CLK"), +SND_SOC_DAPM_OUTPUT("AUXPDM2_DOUT"), + +SND_SOC_DAPM_OUTPUT("MICSUPP"), + +SND_SOC_DAPM_OUTPUT("Ultrasonic Dummy Output"), +}; + +#define CS48L32_MIXER_INPUT_ROUTES(name) \ + { name, "Tone Generator 1", "Tone Generator 1" }, \ + { name, "Tone Generator 2", "Tone Generator 2" }, \ + { name, "Noise Generator", "Noise Generator" }, \ + { name, "IN1L", "IN1L PGA" }, \ + { name, "IN1R", "IN1R PGA" }, \ + { name, "IN2L", "IN2L PGA" }, \ + { name, "IN2R", "IN2R PGA" }, \ + { name, "ASP1RX1", "ASP1RX1" }, \ + { name, "ASP1RX2", "ASP1RX2" }, \ + { name, "ASP1RX3", "ASP1RX3" }, \ + { name, "ASP1RX4", "ASP1RX4" }, \ + { name, "ASP1RX5", "ASP1RX5" }, \ + { name, "ASP1RX6", "ASP1RX6" }, \ + { name, "ASP1RX7", "ASP1RX7" }, \ + { name, "ASP1RX8", "ASP1RX8" }, \ + { name, "ASP2RX1", "ASP2RX1" }, \ + { name, "ASP2RX2", "ASP2RX2" }, \ + { name, "ASP2RX3", "ASP2RX3" }, \ + { name, "ASP2RX4", "ASP2RX4" }, \ + { name, "ISRC1DEC1", "ISRC1DEC1" }, \ + { name, "ISRC1DEC2", "ISRC1DEC2" }, \ + { name, "ISRC1DEC3", "ISRC1DEC3" }, \ + { name, "ISRC1DEC4", "ISRC1DEC4" }, \ + { name, "ISRC1INT1", "ISRC1INT1" }, \ + { name, "ISRC1INT2", "ISRC1INT2" }, \ + { name, "ISRC1INT3", "ISRC1INT3" }, \ + { name, "ISRC1INT4", "ISRC1INT4" }, \ + { name, "ISRC2DEC1", "ISRC2DEC1" }, \ + { name, "ISRC2DEC2", "ISRC2DEC2" }, \ + { name, "ISRC2INT1", "ISRC2INT1" }, \ + { name, "ISRC2INT2", "ISRC2INT2" }, \ + { name, "ISRC3DEC1", "ISRC3DEC1" }, \ + { name, "ISRC3DEC2", "ISRC3DEC2" }, \ + { name, "ISRC3INT1", "ISRC3INT1" }, \ + { name, "ISRC3INT2", "ISRC3INT2" }, \ + { name, "EQ1", "EQ1" }, \ + { name, "EQ2", "EQ2" }, \ + { name, "EQ3", "EQ3" }, \ + { name, "EQ4", "EQ4" }, \ + { name, "DRC1L", "DRC1L" }, \ + { name, "DRC1R", "DRC1R" }, \ + { name, "DRC2L", "DRC2L" }, \ + { name, "DRC2R", "DRC2R" }, \ + { name, "LHPF1", "LHPF1" }, \ + { name, "LHPF2", "LHPF2" }, \ + { name, "LHPF3", "LHPF3" }, \ + { name, "LHPF4", "LHPF4" }, \ + { name, "Ultrasonic 1", "Ultrasonic 1" }, \ + { name, "Ultrasonic 2", "Ultrasonic 2" }, \ + { name, "DSP1.1", "DSP1" }, \ + { name, "DSP1.2", "DSP1" }, \ + { name, "DSP1.3", "DSP1" }, \ + { name, "DSP1.4", "DSP1" }, \ + { name, "DSP1.5", "DSP1" }, \ + { name, "DSP1.6", "DSP1" }, \ + { name, "DSP1.7", "DSP1" }, \ + { name, "DSP1.8", "DSP1" } + +static const struct snd_soc_dapm_route cs48l32_dapm_routes[] = { + { "OPCLK", NULL, "SYSCLK" }, + + { "IN1LN_1", NULL, "SYSCLK" }, + { "IN1LN_2", NULL, "SYSCLK" }, + { "IN1LP_1", NULL, "SYSCLK" }, + { "IN1LP_2", NULL, "SYSCLK" }, + { "IN1RN_1", NULL, "SYSCLK" }, + { "IN1RN_2", NULL, "SYSCLK" }, + { "IN1RP_1", NULL, "SYSCLK" }, + { "IN1RP_2", NULL, "SYSCLK" }, + + { "IN1_PDMCLK", NULL, "SYSCLK" }, + { "IN1_PDMDATA", NULL, "SYSCLK" }, + { "IN2_PDMCLK", NULL, "SYSCLK" }, + { "IN2_PDMDATA", NULL, "SYSCLK" }, + + { "DSP1 Preloader", NULL, "DSP1MEM" }, + { "DSP1", NULL, "DSP1FREQ" }, + + { "Audio Trace DSP", NULL, "DSP1" }, + { "Voice Ctrl DSP", NULL, "DSP1" }, + + { "MICBIAS1", NULL, "VOUT_MIC" }, + + { "MICBIAS1A", NULL, "MICBIAS1" }, + { "MICBIAS1B", NULL, "MICBIAS1" }, + { "MICBIAS1C", NULL, "MICBIAS1" }, + + { "Tone Generator 1", NULL, "SYSCLK" }, + { "Tone Generator 2", NULL, "SYSCLK" }, + { "Noise Generator", NULL, "SYSCLK" }, + + { "Tone Generator 1", NULL, "TONE" }, + { "Tone Generator 2", NULL, "TONE" }, + { "Noise Generator", NULL, "NOISE" }, + + { "ASP1 Capture", NULL, "ASP1TX1" }, + { "ASP1 Capture", NULL, "ASP1TX2" }, + { "ASP1 Capture", NULL, "ASP1TX3" }, + { "ASP1 Capture", NULL, "ASP1TX4" }, + { "ASP1 Capture", NULL, "ASP1TX5" }, + { "ASP1 Capture", NULL, "ASP1TX6" }, + { "ASP1 Capture", NULL, "ASP1TX7" }, + { "ASP1 Capture", NULL, "ASP1TX8" }, + + { "ASP1RX1", NULL, "ASP1 Playback" }, + { "ASP1RX2", NULL, "ASP1 Playback" }, + { "ASP1RX3", NULL, "ASP1 Playback" }, + { "ASP1RX4", NULL, "ASP1 Playback" }, + { "ASP1RX5", NULL, "ASP1 Playback" }, + { "ASP1RX6", NULL, "ASP1 Playback" }, + { "ASP1RX7", NULL, "ASP1 Playback" }, + { "ASP1RX8", NULL, "ASP1 Playback" }, + + { "ASP2 Capture", NULL, "ASP2TX1" }, + { "ASP2 Capture", NULL, "ASP2TX2" }, + { "ASP2 Capture", NULL, "ASP2TX3" }, + { "ASP2 Capture", NULL, "ASP2TX4" }, + + { "ASP2RX1", NULL, "ASP2 Playback" }, + { "ASP2RX2", NULL, "ASP2 Playback" }, + { "ASP2RX3", NULL, "ASP2 Playback" }, + { "ASP2RX4", NULL, "ASP2 Playback" }, + + { "ASP1 Playback", NULL, "SYSCLK" }, + { "ASP2 Playback", NULL, "SYSCLK" }, + + { "ASP1 Capture", NULL, "SYSCLK" }, + { "ASP2 Capture", NULL, "SYSCLK" }, + + { "IN1L Mux", "Analog 1", "IN1LN_1" }, + { "IN1L Mux", "Analog 2", "IN1LN_2" }, + { "IN1L Mux", "Analog 1", "IN1LP_1" }, + { "IN1L Mux", "Analog 2", "IN1LP_2" }, + { "IN1R Mux", "Analog 1", "IN1RN_1" }, + { "IN1R Mux", "Analog 2", "IN1RN_2" }, + { "IN1R Mux", "Analog 1", "IN1RP_1" }, + { "IN1R Mux", "Analog 2", "IN1RP_2" }, + + { "IN1L PGA", NULL, "IN1L Mode" }, + { "IN1R PGA", NULL, "IN1R Mode" }, + + { "IN1L Mode", "Analog", "IN1L Mux" }, + { "IN1R Mode", "Analog", "IN1R Mux" }, + + { "IN1L Mode", "Digital", "IN1_PDMCLK" }, + { "IN1L Mode", "Digital", "IN1_PDMDATA" }, + { "IN1R Mode", "Digital", "IN1_PDMCLK" }, + { "IN1R Mode", "Digital", "IN1_PDMDATA" }, + + { "IN1L PGA", NULL, "VOUT_MIC" }, + { "IN1R PGA", NULL, "VOUT_MIC" }, + + { "IN2L PGA", NULL, "VOUT_MIC" }, + { "IN2R PGA", NULL, "VOUT_MIC" }, + + { "IN2L PGA", NULL, "IN2_PDMCLK" }, + { "IN2R PGA", NULL, "IN2_PDMCLK" }, + { "IN2L PGA", NULL, "IN2_PDMDATA" }, + { "IN2R PGA", NULL, "IN2_PDMDATA" }, + + { "Ultrasonic 1", NULL, "Ultrasonic 1 Input" }, + { "Ultrasonic 2", NULL, "Ultrasonic 2 Input" }, + + { "Ultrasonic 1 Input", "IN1L", "IN1L PGA" }, + { "Ultrasonic 1 Input", "IN1R", "IN1R PGA" }, + { "Ultrasonic 1 Input", "IN2L", "IN2L PGA" }, + { "Ultrasonic 1 Input", "IN2R", "IN2R PGA" }, + + { "Ultrasonic 2 Input", "IN1L", "IN1L PGA" }, + { "Ultrasonic 2 Input", "IN1R", "IN1R PGA" }, + { "Ultrasonic 2 Input", "IN2L", "IN2L PGA" }, + { "Ultrasonic 2 Input", "IN2R", "IN2R PGA" }, + + { "Ultrasonic 1 Activity Detect", "Switch", "Ultrasonic 1 Input" }, + { "Ultrasonic 2 Activity Detect", "Switch", "Ultrasonic 2 Input" }, + + { "Ultrasonic Dummy Output", NULL, "Ultrasonic 1 Activity Detect" }, + { "Ultrasonic Dummy Output", NULL, "Ultrasonic 2 Activity Detect" }, + + CS48L32_MIXER_ROUTES("ASP1TX1", "ASP1TX1"), + CS48L32_MIXER_ROUTES("ASP1TX2", "ASP1TX2"), + CS48L32_MIXER_ROUTES("ASP1TX3", "ASP1TX3"), + CS48L32_MIXER_ROUTES("ASP1TX4", "ASP1TX4"), + CS48L32_MIXER_ROUTES("ASP1TX5", "ASP1TX5"), + CS48L32_MIXER_ROUTES("ASP1TX6", "ASP1TX6"), + CS48L32_MIXER_ROUTES("ASP1TX7", "ASP1TX7"), + CS48L32_MIXER_ROUTES("ASP1TX8", "ASP1TX8"), + + CS48L32_MIXER_ROUTES("ASP2TX1", "ASP2TX1"), + CS48L32_MIXER_ROUTES("ASP2TX2", "ASP2TX2"), + CS48L32_MIXER_ROUTES("ASP2TX3", "ASP2TX3"), + CS48L32_MIXER_ROUTES("ASP2TX4", "ASP2TX4"), + + CS48L32_MIXER_ROUTES("EQ1", "EQ1"), + CS48L32_MIXER_ROUTES("EQ2", "EQ2"), + CS48L32_MIXER_ROUTES("EQ3", "EQ3"), + CS48L32_MIXER_ROUTES("EQ4", "EQ4"), + + CS48L32_MIXER_ROUTES("DRC1L", "DRC1L"), + CS48L32_MIXER_ROUTES("DRC1R", "DRC1R"), + CS48L32_MIXER_ROUTES("DRC2L", "DRC2L"), + CS48L32_MIXER_ROUTES("DRC2R", "DRC2R"), + + CS48L32_MIXER_ROUTES("LHPF1", "LHPF1"), + CS48L32_MIXER_ROUTES("LHPF2", "LHPF2"), + CS48L32_MIXER_ROUTES("LHPF3", "LHPF3"), + CS48L32_MIXER_ROUTES("LHPF4", "LHPF4"), + + CS48L32_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), + CS48L32_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), + CS48L32_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"), + CS48L32_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"), + + CS48L32_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), + CS48L32_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), + CS48L32_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"), + CS48L32_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"), + + CS48L32_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), + CS48L32_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), + + CS48L32_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), + CS48L32_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), + + CS48L32_MUX_ROUTES("ISRC3INT1", "ISRC3INT1"), + CS48L32_MUX_ROUTES("ISRC3INT2", "ISRC3INT2"), + + CS48L32_MUX_ROUTES("ISRC3DEC1", "ISRC3DEC1"), + CS48L32_MUX_ROUTES("ISRC3DEC2", "ISRC3DEC2"), + + CS48L32_DSP_ROUTES_1_8_SYSCLK("DSP1"), + + { "DSP Trigger Out", NULL, "DSP1 Trigger Output" }, + + { "DSP1 Trigger Output", "Switch", "DSP1" }, + + { "AUXPDM1 Analog Input", "IN1L", "IN1L PGA" }, + { "AUXPDM1 Analog Input", "IN1R", "IN1R PGA" }, + + { "AUXPDM2 Analog Input", "IN1L", "IN1L PGA" }, + { "AUXPDM2 Analog Input", "IN1R", "IN1R PGA" }, + + { "AUXPDM1 Input", "Analog", "AUXPDM1 Analog Input" }, + { "AUXPDM1 Input", "IN1 Digital", "IN1L PGA" }, + { "AUXPDM1 Input", "IN1 Digital", "IN1R PGA" }, + { "AUXPDM1 Input", "IN2 Digital", "IN2L PGA" }, + { "AUXPDM1 Input", "IN2 Digital", "IN2R PGA" }, + + { "AUXPDM2 Input", "Analog", "AUXPDM2 Analog Input" }, + { "AUXPDM2 Input", "IN1 Digital", "IN1L PGA" }, + { "AUXPDM2 Input", "IN1 Digital", "IN1R PGA" }, + { "AUXPDM2 Input", "IN2 Digital", "IN2L PGA" }, + { "AUXPDM2 Input", "IN2 Digital", "IN2R PGA" }, + + { "AUXPDM1 Output", "Switch", "AUXPDM1 Input" }, + { "AUXPDM1_CLK", NULL, "AUXPDM1 Output" }, + { "AUXPDM1_DOUT", NULL, "AUXPDM1 Output" }, + + { "AUXPDM2 Output", "Switch", "AUXPDM2 Input" }, + { "AUXPDM2_CLK", NULL, "AUXPDM2 Output" }, + { "AUXPDM2_DOUT", NULL, "AUXPDM2 Output" }, + + { "MICSUPP", NULL, "SYSCLK" }, + + { "DRC1 Signal Activity", NULL, "DRC1 Activity Output" }, + { "DRC2 Signal Activity", NULL, "DRC2 Activity Output" }, + { "DRC1 Activity Output", "Switch", "DRC1L" }, + { "DRC1 Activity Output", "Switch", "DRC1R" }, + { "DRC2 Activity Output", "Switch", "DRC2L" }, + { "DRC2 Activity Output", "Switch", "DRC2R" }, +}; + +static struct snd_soc_dai_driver cs48l32_dai[] = { + { + .name = "cs48l32-asp1", + .id = 1, + .base = CS48L32_ASP1_ENABLES1, + .playback = { + .stream_name = "ASP1 Playback", + .channels_min = 1, + .channels_max = 8, + .rates = CS48L32_RATES, + .formats = CS48L32_FORMATS, + }, + .capture = { + .stream_name = "ASP1 Capture", + .channels_min = 1, + .channels_max = 8, + .rates = CS48L32_RATES, + .formats = CS48L32_FORMATS, + }, + .ops = &cs48l32_dai_ops, + .symmetric_rate = 1, + .symmetric_sample_bits = 1, + }, + { + .name = "cs48l32-asp2", + .id = 2, + .base = CS48L32_ASP2_ENABLES1, + .playback = { + .stream_name = "ASP2 Playback", + .channels_min = 1, + .channels_max = 4, + .rates = CS48L32_RATES, + .formats = CS48L32_FORMATS, + }, + .capture = { + .stream_name = "ASP2 Capture", + .channels_min = 1, + .channels_max = 4, + .rates = CS48L32_RATES, + .formats = CS48L32_FORMATS, + }, + .ops = &cs48l32_dai_ops, + .symmetric_rate = 1, + .symmetric_sample_bits = 1, + }, + { + .name = "cs48l32-cpu-trace", + .id = 3, + .capture = { + .stream_name = "Audio Trace CPU", + .channels_min = 1, + .channels_max = 8, + .rates = CS48L32_RATES, + .formats = CS48L32_FORMATS, + }, + .compress_new = &snd_soc_new_compress, + }, + { + .name = "cs48l32-dsp-trace", + .id = 4, + .capture = { + .stream_name = "Audio Trace DSP", + .channels_min = 1, + .channels_max = 8, + .rates = CS48L32_RATES, + .formats = CS48L32_FORMATS, + }, + }, + { + .name = "cs48l32-cpu-voicectrl", + .id = 5, + .capture = { + .stream_name = "Voice Ctrl CPU", + .channels_min = 1, + .channels_max = 8, + .rates = CS48L32_RATES, + .formats = CS48L32_FORMATS, + }, + .compress_new = &snd_soc_new_compress, + }, + { + .name = "cs48l32-dsp-voicectrl", + .id = 6, + .capture = { + .stream_name = "Voice Ctrl DSP", + .channels_min = 1, + .channels_max = 8, + .rates = CS48L32_RATES, + .formats = CS48L32_FORMATS, + }, + }, +}; + +static int cs48l32_compr_open(struct snd_soc_component *component, + struct snd_compr_stream *stream) +{ + struct snd_soc_pcm_runtime *rtd = stream->private_data; + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + + if (strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs48l32-dsp-trace") && + strcmp(asoc_rtd_to_codec(rtd, 0)->name, "cs48l32-dsp-voicectrl")) { + dev_err(cs48l32->dev, "No suitable compressed stream for DAI '%s'\n", + asoc_rtd_to_codec(rtd, 0)->name); + return -EINVAL; + } + + return wm_adsp_compr_open(&cs48l32->dsp, stream); +} + +static int cs48l32_component_probe(struct snd_soc_component *component) +{ + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + int ret; + + snd_soc_component_init_regmap(component, cs48l32->mfd->regmap); + cs48l32->mfd->dapm = snd_soc_component_get_dapm(component); + + ret = cs48l32_init_inputs(component); + if (ret) + return ret; + + ret = cs48l32_init_eq(cs48l32); + if (ret) + return ret; + + wm_adsp2_component_probe(&cs48l32->dsp, component); + + return 0; +} + +static void cs48l32_component_remove(struct snd_soc_component *component) +{ + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + + wm_adsp2_component_remove(&cs48l32->dsp, component); + cs48l32->mfd->dapm = NULL; +} + +static int cs48l32_set_fll(struct snd_soc_component *component, int fll_id, + int source, unsigned int fref, unsigned int fout) +{ + struct cs48l32 *cs48l32 = snd_soc_component_get_drvdata(component); + + switch (fll_id) { + case CS48L32_FLL1_REFCLK: + break; + default: + return -EINVAL; + } + + return cs48l32_fllhj_set_refclk(&cs48l32->fll, source, fref, fout); +} + +static const struct snd_compress_ops cs48l32_compress_ops = { + .open = &cs48l32_compr_open, + .free = &wm_adsp_compr_free, + .set_params = &wm_adsp_compr_set_params, + .get_caps = &wm_adsp_compr_get_caps, + .trigger = &wm_adsp_compr_trigger, + .pointer = &wm_adsp_compr_pointer, + .copy = &wm_adsp_compr_copy, +}; + +static const struct snd_soc_component_driver soc_component_dev_cs48l32 = { + .probe = &cs48l32_component_probe, + .remove = &cs48l32_component_remove, + .set_sysclk = &cs48l32_set_sysclk, + .set_pll = &cs48l32_set_fll, + .name = "cs48l32-codec", + .compress_ops = &cs48l32_compress_ops, + .controls = cs48l32_snd_controls, + .num_controls = ARRAY_SIZE(cs48l32_snd_controls), + .dapm_widgets = cs48l32_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(cs48l32_dapm_widgets), + .dapm_routes = cs48l32_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(cs48l32_dapm_routes), + .use_pmdown_time = 1, + .endianness = 1, +}; + +static const struct { + int id; + bool wake_source; + const char * const name; + irq_handler_t handler; +} cs48l32_interrupts[] = { + { CS48L32_IRQ_US1_ACT_DET_RISE, false, "US1 activity", cs48l32_us1_activity }, + { CS48L32_IRQ_US2_ACT_DET_RISE, false, "US2 activity", cs48l32_us2_activity }, + { CS48L32_IRQ_DSP1_IRQ0, true, "DSP1 Buffer IRQ", cs48l32_dsp1_irq }, + { CS48L32_IRQ_DSP1_MPU_ERR, false, "DSP1 MPU", wm_halo_bus_error }, + { CS48L32_IRQ_DSP1_WDT_EXPIRE, false, "DSP1 WDT", wm_halo_wdt_expire }, +}; + +static void cs48l32_free_interrupts(struct cs48l32 *cs48l32, int num) +{ + for (--num; num >= 0; --num) { + cs48l32_free_irq(cs48l32->mfd, cs48l32_interrupts[num].id, cs48l32); + if (cs48l32_interrupts[num].wake_source) + cs48l32_set_irq_wake(cs48l32->mfd, cs48l32_interrupts[num].id, 0); + } +} + +static int cs48l32_request_interrupts(struct cs48l32 *cs48l32) +{ + int i, ret; + + for (i = 0; i < ARRAY_SIZE(cs48l32_interrupts); ++i) { + ret = cs48l32_request_irq(cs48l32->mfd, + cs48l32_interrupts[i].id, + cs48l32_interrupts[i].name, + cs48l32_interrupts[i].handler, + cs48l32); + if (ret != 0) + goto err; + + if (cs48l32_interrupts[i].wake_source) { + ret = cs48l32_set_irq_wake(cs48l32->mfd, cs48l32_interrupts[i].id, 1); + if (ret) + dev_warn(cs48l32->dev, "Failed to set %s wake: %d\n", + cs48l32_interrupts[i].name, ret); + } + } + + return 0; +err: + dev_err_probe(cs48l32->dev, ret, "Failed to get %s IRQ\n", cs48l32_interrupts[i].name); + cs48l32_free_interrupts(cs48l32, i); + + return ret; +} + +static int cs48l32_probe(struct platform_device *pdev) +{ + struct cs48l32_mfd *mfd = dev_get_drvdata(pdev->dev.parent); + struct cs48l32 *cs48l32; + struct wm_adsp *dsp; + int i, ret; + + BUILD_BUG_ON(offsetof(struct cs48l32, dsp) != 0); + BUILD_BUG_ON(ARRAY_SIZE(cs48l32_dai) > CS48L32_MAX_DAI); + + /* quick exit if irqchip driver hasn't completed probe */ + if (!mfd->irq_dev) { + dev_dbg(&pdev->dev, "irqchip driver not ready\n"); + return -EPROBE_DEFER; + } + + cs48l32 = devm_kzalloc(&pdev->dev, sizeof(struct cs48l32), GFP_KERNEL); + if (!cs48l32) + return -ENOMEM; + + platform_set_drvdata(pdev, cs48l32); + pdev->dev.of_node = of_node_get(mfd->dev->of_node); + + cs48l32->mfd = mfd; + cs48l32->dev = &pdev->dev; + cs48l32->max_analogue_inputs = 1; + cs48l32->max_pdm_sup = 2; + cs48l32->in_vu_reg = CS48L32_INPUT_CONTROL3; + + ret = cs48l32_core_init(cs48l32); + if (ret) + return ret; + + ret = cs48l32_request_interrupts(cs48l32); + if (ret) + goto err; + + dsp = &cs48l32->dsp; + + switch (mfd->part) { + case 0x31: + dsp->part = "cs48l31"; + break; + case 0x32: + dsp->part = "cs48l32"; + break; + case 0x33: + dsp->part = "cs48l33"; + break; + default: + ret = -EINVAL; + goto err; + } + + dsp->cs_dsp.num = 1; + dsp->cs_dsp.type = WMFW_HALO; + dsp->cs_dsp.rev = 0; + dsp->cs_dsp.dev = mfd->dev; + dsp->cs_dsp.regmap = mfd->regmap; + + dsp->cs_dsp.base = CS48L32_DSP1_CLOCK_FREQ; + dsp->cs_dsp.base_sysinfo = CS48L32_DSP1_SYS_INFO_ID; + + dsp->cs_dsp.mem = cs48l32_dsp1_regions; + dsp->cs_dsp.num_mems = ARRAY_SIZE(cs48l32_dsp1_regions); + dsp->pre_run = cs48l32_dsp_pre_run; + + ret = wm_halo_init(dsp); + if (ret != 0) + goto err; + + cs48l32->fll.cs48l32 = cs48l32; + cs48l32->fll.id = 1; + cs48l32->fll.base = CS48L32_FLL1_CONTROL1; + cs48l32->fll.sts_addr = CS48L32_IRQ1_STS_6; + cs48l32->fll.sts_mask = CS48L32_FLL1_LOCK_STS1_MASK; + cs48l32->fll.has_lp = 1; + cs48l32_init_fll(&cs48l32->fll); + + for (i = 0; i < ARRAY_SIZE(cs48l32_dai); i++) + cs48l32_init_dai(cs48l32, i); + + pm_runtime_enable(&pdev->dev); + pm_runtime_idle(&pdev->dev); + + ret = devm_snd_soc_register_component(&pdev->dev, + &soc_component_dev_cs48l32, + cs48l32_dai, + ARRAY_SIZE(cs48l32_dai)); + if (ret < 0) { + dev_err_probe(&pdev->dev, ret, "Failed to register component\n"); + goto err_dsp; + } + + return ret; +err_dsp: + wm_adsp2_remove(&cs48l32->dsp); +err: + cs48l32_core_destroy(cs48l32); + + return ret; +} + +static int cs48l32_remove(struct platform_device *pdev) +{ + struct cs48l32 *cs48l32 = platform_get_drvdata(pdev); + + pm_runtime_disable(&pdev->dev); + + cs48l32_free_interrupts(cs48l32, ARRAY_SIZE(cs48l32_interrupts)); + wm_adsp2_remove(&cs48l32->dsp); + + cs48l32_core_destroy(cs48l32); + + return 0; +} + +static struct platform_driver cs48l32_codec_driver = { + .driver = { + .name = "cs48l32-codec", + }, + .probe = &cs48l32_probe, + .remove = &cs48l32_remove, +}; + +module_platform_driver(cs48l32_codec_driver); + +MODULE_SOFTDEP("pre: cs48l32 irq-cirrus-cs48l32 arizona-micsupp"); +MODULE_DESCRIPTION("ASoC CS48L32 driver"); +MODULE_AUTHOR("Stuart Henderson <stuarth@opensource.cirrus.com>"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:cs48l32-codec"); diff --git a/sound/soc/codecs/cs48l32.h b/sound/soc/codecs/cs48l32.h new file mode 100644 index 000000000000..7cbd85077902 --- /dev/null +++ b/sound/soc/codecs/cs48l32.h @@ -0,0 +1,386 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Cirrus Logic CS48L32 codec core support + * + * Copyright (C) 2016-2018, 2022 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef ASOC_CS48L32_H +#define ASOC_CS48L32_H + +#include <linux/mfd/cs48l32/core.h> +#include <sound/cs48l32.h> +#include <sound/soc.h> + +#include "wm_adsp.h" + +#define CS48L32_PDMCLK_SRC_IN1_PDMCLK 0x0 +#define CS48L32_PDMCLK_SRC_IN2_PDMCLK 0x1 +#define CS48L32_PDMCLK_SRC_IN3_PDMCLK 0x2 +#define CS48L32_PDMCLK_SRC_IN4_PDMCLK 0x3 +#define CS48L32_PDMCLK_SRC_AUXPDM1_CLK 0x8 +#define CS48L32_PDMCLK_SRC_AUXPDM2_CLK 0x9 + +#define CS48L32_MAX_DAI 12 +#define CS48L32_MAX_INPUT 4 +#define CS48L32_MAX_MUXED_IN_CHANNELS 4 +#define CS48L32_MAX_ASP 2 + +#define CS48L32_NUM_MIXER_INPUTS 58 + +#define CS48L32_EQ_BLOCK_SZ 60 +#define CS48L32_N_EQ_BLOCKS 4 + +#define CS48L32_DSP_N_RX_CHANNELS 8 +#define CS48L32_DSP_N_TX_CHANNELS 8 + +#define CS48L32_SAMPLE_RATE_ENUM_SIZE 17 + +#define CS48L32_MIXER_CONTROLS(name, base) \ + SOC_SINGLE_RANGE_TLV(name " Input 1 Volume", base, \ + CS48L32_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ + cs48l32_mixer_tlv), \ + SOC_SINGLE_RANGE_TLV(name " Input 2 Volume", base + 4, \ + CS48L32_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ + cs48l32_mixer_tlv), \ + SOC_SINGLE_RANGE_TLV(name " Input 3 Volume", base + 8, \ + CS48L32_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ + cs48l32_mixer_tlv), \ + SOC_SINGLE_RANGE_TLV(name " Input 4 Volume", base + 12, \ + CS48L32_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ + cs48l32_mixer_tlv) + +#define CS48L32_MUX_ENUM_DECL(name, reg) \ + SOC_VALUE_ENUM_SINGLE_DECL( \ + name, reg, 0, CS48L32_MIXER_SRC_MASK, \ + cs48l32_mixer_texts, cs48l32_mixer_values) + +#define CS48L32_MUX_CTL_DECL(name) \ + const struct snd_kcontrol_new name##_mux = SOC_DAPM_ENUM("Route", name##_enum) + +#define CS48L32_MUX_ENUMS(name, base_reg) \ + static CS48L32_MUX_ENUM_DECL(name##_enum, base_reg); \ + static CS48L32_MUX_CTL_DECL(name) + +#define CS48L32_MIXER_ENUMS(name, base_reg) \ + CS48L32_MUX_ENUMS(name##_in1, base_reg); \ + CS48L32_MUX_ENUMS(name##_in2, base_reg + 4); \ + CS48L32_MUX_ENUMS(name##_in3, base_reg + 8); \ + CS48L32_MUX_ENUMS(name##_in4, base_reg + 12) + +#define CS48L32_MUX(name, ctrl) SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl) + +#define CS48L32_MUX_WIDGETS(name, name_str) CS48L32_MUX(name_str " Input 1", &name##_mux) + +#define CS48L32_MIXER_WIDGETS(name, name_str) \ + CS48L32_MUX(name_str " Input 1", &name##_in1_mux), \ + CS48L32_MUX(name_str " Input 2", &name##_in2_mux), \ + CS48L32_MUX(name_str " Input 3", &name##_in3_mux), \ + CS48L32_MUX(name_str " Input 4", &name##_in4_mux), \ + SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0) + +#define CS48L32_MUX_ROUTES(widget, name) \ + { widget, NULL, name " Input 1" }, \ + CS48L32_MIXER_INPUT_ROUTES(name " Input 1") + +#define CS48L32_MIXER_ROUTES(widget, name) \ + { widget, NULL, name " Mixer" }, \ + { name " Mixer", NULL, name " Input 1" }, \ + { name " Mixer", NULL, name " Input 2" }, \ + { name " Mixer", NULL, name " Input 3" }, \ + { name " Mixer", NULL, name " Input 4" }, \ + CS48L32_MIXER_INPUT_ROUTES(name " Input 1"), \ + CS48L32_MIXER_INPUT_ROUTES(name " Input 2"), \ + CS48L32_MIXER_INPUT_ROUTES(name " Input 3"), \ + CS48L32_MIXER_INPUT_ROUTES(name " Input 4") + +#define CS48L32_DSP_ROUTES_1_8_SYSCLK(name) \ + { name, NULL, name " Preloader" }, \ + { name, NULL, "SYSCLK" }, \ + { name " Preload", NULL, name " Preloader" }, \ + CS48L32_MIXER_ROUTES(name, name "RX1"), \ + CS48L32_MIXER_ROUTES(name, name "RX2"), \ + CS48L32_MIXER_ROUTES(name, name "RX3"), \ + CS48L32_MIXER_ROUTES(name, name "RX4"), \ + CS48L32_MIXER_ROUTES(name, name "RX5"), \ + CS48L32_MIXER_ROUTES(name, name "RX6"), \ + CS48L32_MIXER_ROUTES(name, name "RX7"), \ + CS48L32_MIXER_ROUTES(name, name "RX8") \ + +#define CS48L32_DSP_ROUTES_1_8(name) \ + { name, NULL, "DSPCLK" }, \ + CS48L32_DSP_ROUTES_1_8_SYSCLK(name) \ + +#define CS48L32_RATE_CONTROL(name, domain) SOC_ENUM(name, cs48l32_sample_rate[(domain) - 1]) + +#define CS48L32_RATE_ENUM(name, enum) \ + SOC_ENUM_EXT(name, enum, snd_soc_get_enum_double, cs48l32_rate_put) + +#define CS48L32_DSP_RATE_CONTROL(name, num) \ + SOC_ENUM_EXT(name " Rate", cs48l32_dsp_rate_enum[num], \ + cs48l32_dsp_rate_get, cs48l32_dsp_rate_put) + +#define CS48L32_EQ_COEFF_CONTROL(xname, xreg, xbase, xshift) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = cs48l32_eq_coeff_info, .get = cs48l32_eq_coeff_get, \ + .put = cs48l32_eq_coeff_put, .private_value = \ + (unsigned long)&(struct cs48l32_eq_control) { .reg = xreg,\ + .shift = xshift, .block_base = xbase, .max = 65535 } } + +#define CS48L32_EQ_REG_NAME_PASTER(eq, band, type) \ + CS48L32_ ## eq ## _ ## band ## _ ## type + +#define CS48L32_EQ_BAND_COEFF_CONTROLS(name, band) \ + CS48L32_EQ_COEFF_CONTROL(#name " " #band " A", \ + CS48L32_EQ_REG_NAME_PASTER(name, band, COEFF1), \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ + 0), \ + CS48L32_EQ_COEFF_CONTROL(#name " " #band " B", \ + CS48L32_EQ_REG_NAME_PASTER(name, band, COEFF1), \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ + 16), \ + CS48L32_EQ_COEFF_CONTROL(#name " " #band " C", \ + CS48L32_EQ_REG_NAME_PASTER(name, band, COEFF2), \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ + 0), \ + CS48L32_EQ_COEFF_CONTROL(#name " " #band " PG", \ + CS48L32_EQ_REG_NAME_PASTER(name, band, PG), \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ + 0) + +#define CS48L32_EQ_COEFF_CONTROLS(name) \ + CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND1), \ + CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND2), \ + CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND3), \ + CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND4), \ + CS48L32_EQ_COEFF_CONTROL(#name " BAND5 A", \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND5, COEFF1), \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ + 0), \ + CS48L32_EQ_COEFF_CONTROL(#name " BAND5 B", \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND5, COEFF1), \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ + 16), \ + CS48L32_EQ_COEFF_CONTROL(#name " BAND5 PG", \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND5, PG), \ + CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \ + 0) + +#define CS48L32_LHPF_CONTROL(xname, xbase) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_bytes_info, .get = snd_soc_bytes_get, \ + .put = cs48l32_lhpf_coeff_put, .private_value = \ + ((unsigned long)&(struct soc_bytes) { .base = xbase, \ + .num_regs = 1 }) } + +/* these have a subseq number so they run after SYSCLK and DSPCLK widgets */ +#define CS48L32_DSP_FREQ_WIDGET_EV(name, num, event) \ + SND_SOC_DAPM_SUPPLY_S(name "FREQ", 100, SND_SOC_NOPM, num, 0, \ + event, SND_SOC_DAPM_POST_PMU) + +#define CS48L32_RATES SNDRV_PCM_RATE_KNOT + +#define CS48L32_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +struct cs48l32_dai_priv { + int clk; + struct snd_pcm_hw_constraint_list constraint; +}; + +struct cs48l32_dsp_power_reg_block { + unsigned int start; + unsigned int end; +}; + +struct cs48l32_dsp_power_regs { + const unsigned int *pwd; + unsigned int n_pwd; + const struct cs48l32_dsp_power_reg_block *ext; + unsigned int n_ext; +}; + +struct cs48l32; + +struct cs48l32_fll_cfg { + int n; + unsigned int theta; + unsigned int lambda; + int refdiv; + int fratio; + int gain; + int alt_gain; +}; + +struct cs48l32_fll { + struct cs48l32 *cs48l32; + int id; + unsigned int base; + + unsigned int sts_addr; + unsigned int sts_mask; + + unsigned int fout; + + int ref_src; + unsigned int ref_freq; + struct cs48l32_fll_cfg ref_cfg; + + unsigned int max_fref; + + unsigned int integer_only:1; + unsigned int has_lp:1; +}; + +struct cs48l32 { + struct wm_adsp dsp; + struct cs48l32_mfd *mfd; + struct device *dev; + int sysclk; + int dspclk; + struct cs48l32_dai_priv dai[CS48L32_MAX_DAI]; + struct cs48l32_fll fll; + + int max_analogue_inputs; + int max_pdm_sup; + int num_dmic_clksrc; + u32 max_channels_clocked[CS48L32_MAX_ASP]; + u32 pdm_sup[CS48L32_MAX_INPUT]; + u32 in_type[CS48L32_MAX_INPUT][CS48L32_MAX_MUXED_IN_CHANNELS]; + + unsigned int in_up_pending; + unsigned int in_vu_reg; + + struct mutex rate_lock; + + u8 dsp_dma_rates[CS48L32_DSP_N_RX_CHANNELS + CS48L32_DSP_N_TX_CHANNELS]; + + int tdm_width[CS48L32_MAX_ASP]; + int tdm_slots[CS48L32_MAX_ASP]; + + unsigned int eq_mode[CS48L32_N_EQ_BLOCKS]; + __be16 eq_coefficients[CS48L32_N_EQ_BLOCKS][CS48L32_EQ_BLOCK_SZ / 2]; + + const struct cs48l32_dsp_power_regs *dsp_power_regs; +}; + +struct cs48l32_enum { + struct soc_enum mixer_enum; + int val; +}; + +struct cs48l32_eq_control { + unsigned int reg; + unsigned int shift; + unsigned int block_base; + unsigned int max; +}; + +extern const char * const cs48l32_mixer_texts[CS48L32_NUM_MIXER_INPUTS]; +extern unsigned int cs48l32_mixer_values[CS48L32_NUM_MIXER_INPUTS]; + +extern const unsigned int cs48l32_ana_tlv[]; +extern const unsigned int cs48l32_eq_tlv[]; +extern const unsigned int cs48l32_digital_tlv[]; +extern const unsigned int cs48l32_noise_tlv[]; +extern const unsigned int cs48l32_mixer_tlv[]; +extern const unsigned int cs48l32_us_tlv[]; + +int cs48l32_rate_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); + +extern const struct soc_enum cs48l32_sample_rate[]; + +extern const struct snd_kcontrol_new cs48l32_inmux[]; +extern const struct snd_kcontrol_new cs48l32_dmode_mux[]; + +extern const struct soc_enum cs48l32_us_freq[]; +extern const struct snd_kcontrol_new cs48l32_us_inmux[]; +extern const struct soc_enum cs48l32_us_output_rate[]; +extern const struct soc_enum cs48l32_us_det_lpf_cut[]; +extern const struct soc_enum cs48l32_us_det_dcy[]; +extern const struct snd_kcontrol_new cs48l32_us_switch[]; +extern const struct soc_enum cs48l32_us_det_thr[]; +extern const struct soc_enum cs48l32_us_det_num[]; +extern const struct soc_enum cs48l32_us_det_hold[]; + +extern const struct soc_enum cs48l32_in_vi_ramp; +extern const struct soc_enum cs48l32_in_vd_ramp; +extern const struct soc_enum cs48l32_in_hpf_cut_enum; +extern const struct soc_enum cs48l32_in_dmic_osr[]; + +irqreturn_t cs48l32_us1_activity(int irq, void *data); +irqreturn_t cs48l32_us2_activity(int irq, void *data); + +int cs48l32_in_rate_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +extern const struct soc_enum cs48l32_input_rate[]; +int cs48l32_low_power_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +extern const struct soc_enum noise_gen_rate; + +extern const struct soc_enum cs48l32_auxpdm1_freq; +extern const struct soc_enum cs48l32_auxpdm2_freq; +extern const struct snd_kcontrol_new cs48l32_auxpdm_inmux[]; +extern const struct snd_kcontrol_new cs48l32_auxpdm_analog_inmux[]; +extern const struct snd_kcontrol_new cs48l32_auxpdm_switch[]; + +extern const struct soc_enum cs48l32_isrc_fsl[]; +extern const struct soc_enum cs48l32_isrc_fsh[]; + +extern const struct soc_enum cs48l32_fx_rate; + +extern const struct soc_enum cs48l32_lhpf_mode[]; + +int cs48l32_lhpf_coeff_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +extern const struct soc_enum cs48l32_eq_mode[]; +int cs48l32_eq_mode_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int cs48l32_eq_mode_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int cs48l32_eq_coeff_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo); +int cs48l32_eq_coeff_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int cs48l32_eq_coeff_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); + +extern const struct snd_kcontrol_new cs48l32_drc_activity_output_mux[]; +extern const struct snd_kcontrol_new cs48l32_dsp_trigger_output_mux[]; +int cs48l32_dsp_rate_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int cs48l32_dsp_rate_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +extern const struct soc_enum cs48l32_dsp_rate_enum[]; + +int cs48l32_dsp_pre_run(struct wm_adsp *dsp); +int cs48l32_dsp_memory_enable(struct cs48l32 *priv, + const struct cs48l32_dsp_power_regs *regs); +void cs48l32_dsp_memory_disable(struct cs48l32 *priv, + const struct cs48l32_dsp_power_regs *regs); +int cs48l32_dsp_freq_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +irqreturn_t cs48l32_dsp1_irq(int irq, void *data); + +int cs48l32_set_sysclk(struct snd_soc_component *component, int clk_id, + int source, unsigned int freq, int dir); + +extern const struct snd_soc_dai_ops cs48l32_dai_ops; + +int cs48l32_sysclk_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event); +int cs48l32_in_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event); +int cs48l32_in_put_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int cs48l32_eq_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event); + +int cs48l32_fllhj_set_refclk(struct cs48l32_fll *fll, int source, + unsigned int fin, unsigned int fout); +int cs48l32_init_fll(struct cs48l32_fll *fll); +int cs48l32_init_inputs(struct snd_soc_component *component); +int cs48l32_init_dai(struct cs48l32 *priv, int dai); +int cs48l32_init_eq(struct cs48l32 *priv); +int cs48l32_core_init(struct cs48l32 *priv); +int cs48l32_core_destroy(struct cs48l32 *priv); + +#endif -- 2.30.2 ^ permalink raw reply related [flat|nested] 98+ messages in thread
* Re: [PATCH 12/12] ASoC: cs48l32: Add codec driver for Cirrus Logic CS48L31/32/33 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-10 20:20 ` kernel test robot -1 siblings, 0 replies; 98+ messages in thread From: kernel test robot @ 2022-11-10 20:20 UTC (permalink / raw) To: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: oe-kbuild-all, alsa-devel, devicetree, linux-gpio, linux-kernel, patches, Richard Fitzgerald [-- Attachment #1: Type: text/plain, Size: 2418 bytes --] Hi Richard, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on broonie-sound/for-next] [also build test WARNING on lee-mfd/for-mfd-next linusw-pinctrl/devel linusw-pinctrl/for-next broonie-regulator/for-next linus/master] [cannot apply to lee-mfd/for-mfd-fixes] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Richard-Fitzgerald/Add-support-for-the-Cirrus-Logic-CS48L32-audio-codecs/20221110-005630 base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next patch link: https://lore.kernel.org/r/20221109165331.29332-13-rf%40opensource.cirrus.com patch subject: [PATCH 12/12] ASoC: cs48l32: Add codec driver for Cirrus Logic CS48L31/32/33 config: i386-allyesconfig compiler: gcc-11 (Debian 11.3.0-8) 11.3.0 reproduce (this is a W=1 build): # https://github.com/intel-lab-lkp/linux/commit/66bc34007a7eabb0b819d76e13de3c33562b4525 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Richard-Fitzgerald/Add-support-for-the-Cirrus-Logic-CS48L32-audio-codecs/20221110-005630 git checkout 66bc34007a7eabb0b819d76e13de3c33562b4525 # save the config file mkdir build_dir && cp config build_dir/.config make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/pci/controller/cadence/ sound/soc/codecs/ sound/soc/intel/boards/ If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot <lkp@intel.com> All warnings (new ones prefixed by >>): >> sound/soc/codecs/cs48l32-core.c:2257:8: warning: type qualifiers ignored on function return type [-Wignored-qualifiers] 2257 | static const char * const cs48l32_dai_clk_str(int clk_id) | ^~~~~ vim +2257 sound/soc/codecs/cs48l32-core.c 2256 > 2257 static const char * const cs48l32_dai_clk_str(int clk_id) 2258 { 2259 switch (clk_id) { 2260 case CS48L32_CLK_SYSCLK_1: 2261 case CS48L32_CLK_SYSCLK_2: 2262 case CS48L32_CLK_SYSCLK_3: 2263 case CS48L32_CLK_SYSCLK_4: 2264 return "SYSCLK"; 2265 default: 2266 return "Unknown clock"; 2267 } 2268 } 2269 -- 0-DAY CI Kernel Test Service https://01.org/lkp [-- Attachment #2: config --] [-- Type: text/plain, Size: 288302 bytes --] # # Automatically generated file; DO NOT EDIT. # Linux/i386 6.1.0-rc1 Kernel Configuration # CONFIG_CC_VERSION_TEXT="gcc-11 (Debian 11.3.0-8) 11.3.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=110300 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y CONFIG_AS_VERSION=23900 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23900 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=123 CONFIG_CONSTRUCTORS=y CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y # # General setup # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set # CONFIG_WERROR is not set CONFIG_UAPI_HEADER_TEST=y CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_BZIP2=y CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_XZ=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_HAVE_KERNEL_LZ4=y CONFIG_HAVE_KERNEL_ZSTD=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_BZIP2 is not set # CONFIG_KERNEL_LZMA is not set # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set # CONFIG_KERNEL_ZSTD is not set CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_WATCH_QUEUE=y CONFIG_CROSS_MEMORY_ATTACH=y CONFIG_USELIB=y CONFIG_AUDIT=y CONFIG_HAVE_ARCH_AUDITSYSCALL=y CONFIG_AUDITSYSCALL=y # # IRQ subsystem # CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_PENDING_IRQ=y CONFIG_GENERIC_IRQ_MIGRATION=y CONFIG_GENERIC_IRQ_INJECTION=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_CHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_SIM=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_IRQ_MSI_IOMMU=y CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y CONFIG_GENERIC_IRQ_RESERVATION_MODE=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y CONFIG_GENERIC_IRQ_DEBUGFS=y # end of IRQ subsystem CONFIG_CLOCKSOURCE_WATCHDOG=y CONFIG_ARCH_CLOCKSOURCE_INIT=y CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_TIME_KUNIT_TEST=y CONFIG_CONTEXT_TRACKING=y CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem # CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ_COMMON=y # CONFIG_HZ_PERIODIC is not set CONFIG_NO_HZ_IDLE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 # end of Timers subsystem CONFIG_BPF=y CONFIG_HAVE_EBPF_JIT=y # # BPF subsystem # CONFIG_BPF_SYSCALL=y CONFIG_BPF_JIT=y CONFIG_BPF_JIT_ALWAYS_ON=y CONFIG_BPF_JIT_DEFAULT_ON=y CONFIG_BPF_UNPRIV_DEFAULT_OFF=y CONFIG_USERMODE_DRIVER=y # CONFIG_BPF_PRELOAD is not set CONFIG_BPF_LSM=y # end of BPF subsystem CONFIG_PREEMPT_BUILD=y CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_PREEMPT_COUNT=y CONFIG_PREEMPTION=y CONFIG_PREEMPT_DYNAMIC=y CONFIG_SCHED_CORE=y # # CPU/Task time and stats accounting # CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_SCHED_AVG_IRQ=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y CONFIG_PSI=y CONFIG_PSI_DEFAULT_DISABLED=y # end of CPU/Task time and stats accounting CONFIG_CPU_ISOLATION=y # # RCU Subsystem # CONFIG_TREE_RCU=y CONFIG_PREEMPT_RCU=y CONFIG_RCU_EXPERT=y CONFIG_SRCU=y CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU_GENERIC=y CONFIG_FORCE_TASKS_RCU=y CONFIG_TASKS_RCU=y CONFIG_FORCE_TASKS_RUDE_RCU=y CONFIG_TASKS_RUDE_RCU=y CONFIG_FORCE_TASKS_TRACE_RCU=y CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y CONFIG_RCU_FANOUT=32 CONFIG_RCU_FANOUT_LEAF=16 CONFIG_RCU_BOOST=y CONFIG_RCU_BOOST_DELAY=500 CONFIG_RCU_EXP_KTHREAD=y CONFIG_RCU_NOCB_CPU=y CONFIG_RCU_NOCB_CPU_DEFAULT_ALL=y CONFIG_RCU_NOCB_CPU_CB_BOOST=y CONFIG_TASKS_TRACE_RCU_READ_MB=y # end of RCU Subsystem CONFIG_BUILD_BIN2C=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_IKHEADERS=y CONFIG_LOG_BUF_SHIFT=17 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 CONFIG_PRINTK_INDEX=y CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y # # Scheduler features # CONFIG_UCLAMP_TASK=y CONFIG_UCLAMP_BUCKETS_COUNT=5 # end of Scheduler features CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y CONFIG_CGROUP_FAVOR_DYNMODS=y CONFIG_MEMCG=y CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y CONFIG_RT_GROUP_SCHED=y CONFIG_UCLAMP_TASK_GROUP=y CONFIG_CGROUP_PIDS=y CONFIG_CGROUP_RDMA=y CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_HUGETLB=y CONFIG_CPUSETS=y CONFIG_PROC_PID_CPUSET=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y CONFIG_CGROUP_MISC=y CONFIG_CGROUP_DEBUG=y CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y CONFIG_UTS_NS=y CONFIG_TIME_NS=y CONFIG_IPC_NS=y CONFIG_USER_NS=y CONFIG_PID_NS=y CONFIG_NET_NS=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_SCHED_AUTOGROUP=y CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y CONFIG_RD_XZ=y CONFIG_RD_LZO=y CONFIG_RD_LZ4=y CONFIG_RD_ZSTD=y CONFIG_BOOT_CONFIG=y CONFIG_BOOT_CONFIG_EMBED=y CONFIG_BOOT_CONFIG_EMBED_FILE="" CONFIG_INITRAMFS_PRESERVE_MTIME=y CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_HAVE_PCSPKR_PLATFORM=y CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_MULTIUSER=y CONFIG_SGETMASK_SYSCALL=y CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_PCSPKR_PLATFORM=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y CONFIG_RSEQ=y CONFIG_DEBUG_RSEQ=y CONFIG_EMBEDDED=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_GUEST_PERF_EVENTS=y CONFIG_PERF_USE_VMALLOC=y CONFIG_PC104=y # # Kernel Performance Events And Counters # CONFIG_PERF_EVENTS=y CONFIG_DEBUG_PERF_USE_VMALLOC=y # end of Kernel Performance Events And Counters CONFIG_SYSTEM_DATA_VERIFICATION=y CONFIG_PROFILING=y CONFIG_TRACEPOINTS=y # end of General setup CONFIG_X86_32=y CONFIG_FORCE_DYNAMIC_FTRACE=y CONFIG_X86=y CONFIG_INSTRUCTION_DECODER=y CONFIG_OUTPUT_FORMAT="elf32-i386" CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_MMU=y CONFIG_ARCH_MMAP_RND_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=16 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 CONFIG_GENERIC_ISA_DMA=y CONFIG_GENERIC_BUG=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_HAS_CPU_RELAX=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_NR_GPIO=512 CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_HAVE_INTEL_TXT=y CONFIG_X86_32_SMP=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_PGTABLE_LEVELS=2 CONFIG_CC_HAS_SANE_STACKPROTECTOR=y # # Processor type and features # CONFIG_SMP=y CONFIG_X86_FEATURE_NAMES=y CONFIG_X86_MPPARSE=y CONFIG_GOLDFISH=y CONFIG_X86_CPU_RESCTRL=y CONFIG_X86_BIGSMP=y CONFIG_X86_EXTENDED_PLATFORM=y CONFIG_X86_GOLDFISH=y CONFIG_X86_INTEL_MID=y CONFIG_X86_INTEL_QUARK=y CONFIG_X86_INTEL_LPSS=y CONFIG_X86_AMD_PLATFORM_DEVICE=y CONFIG_IOSF_MBI=y CONFIG_IOSF_MBI_DEBUG=y CONFIG_X86_RDC321X=y CONFIG_X86_32_NON_STANDARD=y CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y CONFIG_STA2X11=y CONFIG_X86_32_IRIS=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_HYPERVISOR_GUEST=y CONFIG_PARAVIRT=y CONFIG_PARAVIRT_DEBUG=y CONFIG_PARAVIRT_SPINLOCKS=y CONFIG_X86_HV_CALLBACK_VECTOR=y CONFIG_KVM_GUEST=y CONFIG_ARCH_CPUIDLE_HALTPOLL=y CONFIG_PVH=y CONFIG_PARAVIRT_TIME_ACCOUNTING=y CONFIG_PARAVIRT_CLOCK=y # CONFIG_M486SX is not set # CONFIG_M486 is not set # CONFIG_M586 is not set # CONFIG_M586TSC is not set # CONFIG_M586MMX is not set CONFIG_M686=y # CONFIG_MPENTIUMII is not set # CONFIG_MPENTIUMIII is not set # CONFIG_MPENTIUMM is not set # CONFIG_MPENTIUM4 is not set # CONFIG_MK6 is not set # CONFIG_MK7 is not set # CONFIG_MK8 is not set # CONFIG_MCRUSOE is not set # CONFIG_MEFFICEON is not set # CONFIG_MWINCHIPC6 is not set # CONFIG_MWINCHIP3D is not set # CONFIG_MELAN is not set # CONFIG_MGEODEGX1 is not set # CONFIG_MGEODE_LX is not set # CONFIG_MCYRIXIII is not set # CONFIG_MVIAC3_2 is not set # CONFIG_MVIAC7 is not set # CONFIG_MCORE2 is not set # CONFIG_MATOM is not set CONFIG_X86_GENERIC=y CONFIG_X86_INTERNODE_CACHE_SHIFT=6 CONFIG_X86_L1_CACHE_SHIFT=6 CONFIG_X86_INTEL_USERCOPY=y CONFIG_X86_USE_PPRO_CHECKSUM=y CONFIG_X86_TSC=y CONFIG_X86_CMPXCHG64=y CONFIG_X86_CMOV=y CONFIG_X86_MINIMUM_CPU_FAMILY=6 CONFIG_X86_DEBUGCTLMSR=y CONFIG_IA32_FEAT_CTL=y CONFIG_X86_VMX_FEATURE_NAMES=y CONFIG_PROCESSOR_SELECT=y CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_CYRIX_32=y CONFIG_CPU_SUP_AMD=y CONFIG_CPU_SUP_HYGON=y CONFIG_CPU_SUP_CENTAUR=y CONFIG_CPU_SUP_TRANSMETA_32=y CONFIG_CPU_SUP_UMC_32=y CONFIG_CPU_SUP_ZHAOXIN=y CONFIG_CPU_SUP_VORTEX_32=y CONFIG_HPET_TIMER=y CONFIG_HPET_EMULATE_RTC=y CONFIG_DMI=y CONFIG_BOOT_VESA_SUPPORT=y CONFIG_NR_CPUS_RANGE_BEGIN=2 CONFIG_NR_CPUS_RANGE_END=64 CONFIG_NR_CPUS_DEFAULT=32 CONFIG_NR_CPUS=32 CONFIG_SCHED_CLUSTER=y CONFIG_SCHED_SMT=y CONFIG_SCHED_MC=y CONFIG_SCHED_MC_PRIO=y CONFIG_X86_LOCAL_APIC=y CONFIG_X86_IO_APIC=y CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y CONFIG_X86_MCE=y CONFIG_X86_MCELOG_LEGACY=y CONFIG_X86_MCE_INTEL=y CONFIG_X86_MCE_AMD=y CONFIG_X86_ANCIENT_MCE=y CONFIG_X86_MCE_THRESHOLD=y CONFIG_X86_MCE_INJECT=y # # Performance monitoring # CONFIG_PERF_EVENTS_INTEL_UNCORE=y CONFIG_PERF_EVENTS_INTEL_RAPL=y CONFIG_PERF_EVENTS_INTEL_CSTATE=y CONFIG_PERF_EVENTS_AMD_POWER=y CONFIG_PERF_EVENTS_AMD_UNCORE=y CONFIG_PERF_EVENTS_AMD_BRS=y # end of Performance monitoring CONFIG_X86_LEGACY_VM86=y CONFIG_VM86=y CONFIG_X86_16BIT=y CONFIG_X86_ESPFIX32=y CONFIG_X86_IOPL_IOPERM=y CONFIG_TOSHIBA=y CONFIG_X86_REBOOTFIXUPS=y CONFIG_MICROCODE=y CONFIG_MICROCODE_INTEL=y CONFIG_MICROCODE_AMD=y CONFIG_MICROCODE_LATE_LOADING=y CONFIG_X86_MSR=y CONFIG_X86_CPUID=y # CONFIG_NOHIGHMEM is not set CONFIG_HIGHMEM4G=y # CONFIG_HIGHMEM64G is not set CONFIG_VMSPLIT_3G=y # CONFIG_VMSPLIT_3G_OPT is not set # CONFIG_VMSPLIT_2G is not set # CONFIG_VMSPLIT_2G_OPT is not set # CONFIG_VMSPLIT_1G is not set CONFIG_PAGE_OFFSET=0xC0000000 CONFIG_HIGHMEM=y CONFIG_X86_CPA_STATISTICS=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ILLEGAL_POINTER_VALUE=0 CONFIG_HIGHPTE=y CONFIG_X86_CHECK_BIOS_CORRUPTION=y CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y CONFIG_MTRR=y CONFIG_MTRR_SANITIZER=y CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0 CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 CONFIG_X86_PAT=y CONFIG_ARCH_USES_PG_UNCACHED=y CONFIG_X86_UMIP=y CONFIG_CC_HAS_IBT=y CONFIG_X86_INTEL_TSX_MODE_OFF=y # CONFIG_X86_INTEL_TSX_MODE_ON is not set # CONFIG_X86_INTEL_TSX_MODE_AUTO is not set CONFIG_EFI=y CONFIG_EFI_STUB=y # CONFIG_HZ_100 is not set CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 CONFIG_SCHED_HRTICK=y CONFIG_KEXEC=y CONFIG_CRASH_DUMP=y CONFIG_KEXEC_JUMP=y CONFIG_PHYSICAL_START=0x1000000 CONFIG_RELOCATABLE=y # CONFIG_RANDOMIZE_BASE is not set CONFIG_X86_NEED_RELOCS=y CONFIG_PHYSICAL_ALIGN=0x200000 CONFIG_HOTPLUG_CPU=y CONFIG_BOOTPARAM_HOTPLUG_CPU0=y CONFIG_DEBUG_HOTPLUG_CPU0=y CONFIG_COMPAT_VDSO=y CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="" CONFIG_MODIFY_LDT_SYSCALL=y CONFIG_STRICT_SIGALTSTACK_SIZE=y # end of Processor type and features CONFIG_CC_HAS_SLS=y CONFIG_CC_HAS_RETURN_THUNK=y CONFIG_SPECULATION_MITIGATIONS=y CONFIG_RETPOLINE=y CONFIG_RETHUNK=y CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y # # Power management and ACPI options # CONFIG_ARCH_HIBERNATION_HEADER=y CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y CONFIG_SUSPEND_SKIP_SYNC=y CONFIG_HIBERNATE_CALLBACKS=y CONFIG_HIBERNATION=y CONFIG_HIBERNATION_SNAPSHOT_DEV=y CONFIG_PM_STD_PARTITION="" CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y CONFIG_PM_AUTOSLEEP=y CONFIG_PM_USERSPACE_AUTOSLEEP=y CONFIG_PM_WAKELOCKS=y CONFIG_PM_WAKELOCKS_LIMIT=100 CONFIG_PM_WAKELOCKS_GC=y CONFIG_PM=y CONFIG_PM_DEBUG=y CONFIG_PM_ADVANCED_DEBUG=y CONFIG_PM_TEST_SUSPEND=y CONFIG_PM_SLEEP_DEBUG=y CONFIG_DPM_WATCHDOG=y CONFIG_DPM_WATCHDOG_TIMEOUT=120 CONFIG_PM_TRACE=y CONFIG_PM_TRACE_RTC=y CONFIG_PM_CLK=y CONFIG_PM_GENERIC_DOMAINS=y CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y CONFIG_PM_GENERIC_DOMAINS_SLEEP=y CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_ENERGY_MODEL=y CONFIG_ARCH_SUPPORTS_ACPI=y CONFIG_ACPI=y CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y CONFIG_ACPI_TABLE_LIB=y CONFIG_ACPI_DEBUGGER=y CONFIG_ACPI_DEBUGGER_USER=y CONFIG_ACPI_SPCR_TABLE=y CONFIG_ACPI_SLEEP=y CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y CONFIG_ACPI_EC_DEBUGFS=y CONFIG_ACPI_AC=y CONFIG_ACPI_BATTERY=y CONFIG_ACPI_BUTTON=y CONFIG_ACPI_VIDEO=y CONFIG_ACPI_FAN=y CONFIG_ACPI_TAD=y CONFIG_ACPI_DOCK=y CONFIG_ACPI_CPU_FREQ_PSS=y CONFIG_ACPI_PROCESSOR_CSTATE=y CONFIG_ACPI_PROCESSOR_IDLE=y CONFIG_ACPI_PROCESSOR=y CONFIG_ACPI_IPMI=y CONFIG_ACPI_HOTPLUG_CPU=y CONFIG_ACPI_PROCESSOR_AGGREGATOR=y CONFIG_ACPI_THERMAL=y CONFIG_ACPI_PLATFORM_PROFILE=y CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y CONFIG_ACPI_TABLE_UPGRADE=y CONFIG_ACPI_DEBUG=y CONFIG_ACPI_PCI_SLOT=y CONFIG_ACPI_CONTAINER=y CONFIG_ACPI_HOTPLUG_IOAPIC=y CONFIG_ACPI_SBS=y CONFIG_ACPI_HED=y CONFIG_ACPI_CUSTOM_METHOD=y CONFIG_ACPI_BGRT=y CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y CONFIG_HAVE_ACPI_APEI=y CONFIG_HAVE_ACPI_APEI_NMI=y CONFIG_ACPI_APEI=y CONFIG_ACPI_APEI_GHES=y CONFIG_ACPI_APEI_PCIEAER=y CONFIG_ACPI_APEI_MEMORY_FAILURE=y CONFIG_ACPI_APEI_EINJ=y CONFIG_ACPI_APEI_ERST_DEBUG=y CONFIG_ACPI_DPTF=y CONFIG_DPTF_POWER=y CONFIG_DPTF_PCH_FIVR=y CONFIG_ACPI_WATCHDOG=y CONFIG_ACPI_EXTLOG=y CONFIG_ACPI_CONFIGFS=y CONFIG_ACPI_PCC=y CONFIG_PMIC_OPREGION=y CONFIG_BYTCRC_PMIC_OPREGION=y CONFIG_CHTCRC_PMIC_OPREGION=y CONFIG_XPOWER_PMIC_OPREGION=y CONFIG_BXT_WC_PMIC_OPREGION=y CONFIG_CHT_WC_PMIC_OPREGION=y CONFIG_CHT_DC_TI_PMIC_OPREGION=y CONFIG_TPS68470_PMIC_OPREGION=y CONFIG_ACPI_VIOT=y CONFIG_X86_PM_TIMER=y CONFIG_X86_APM_BOOT=y CONFIG_APM=y CONFIG_APM_IGNORE_USER_SUSPEND=y CONFIG_APM_DO_ENABLE=y CONFIG_APM_CPU_IDLE=y CONFIG_APM_DISPLAY_BLANK=y CONFIG_APM_ALLOW_INTS=y # # CPU Frequency scaling # CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_GOV_ATTR_SET=y CONFIG_CPU_FREQ_GOV_COMMON=y CONFIG_CPU_FREQ_STAT=y # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y CONFIG_CPU_FREQ_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # # CPU frequency scaling drivers # CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y CONFIG_X86_INTEL_PSTATE=y CONFIG_X86_PCC_CPUFREQ=y CONFIG_X86_AMD_PSTATE=y CONFIG_X86_AMD_PSTATE_UT=y CONFIG_X86_ACPI_CPUFREQ=y CONFIG_X86_ACPI_CPUFREQ_CPB=y CONFIG_X86_POWERNOW_K6=y CONFIG_X86_POWERNOW_K7=y CONFIG_X86_POWERNOW_K7_ACPI=y CONFIG_X86_POWERNOW_K8=y CONFIG_X86_AMD_FREQ_SENSITIVITY=y CONFIG_X86_GX_SUSPMOD=y CONFIG_X86_SPEEDSTEP_CENTRINO=y CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE=y CONFIG_X86_SPEEDSTEP_ICH=y CONFIG_X86_SPEEDSTEP_SMI=y CONFIG_X86_P4_CLOCKMOD=y CONFIG_X86_CPUFREQ_NFORCE2=y CONFIG_X86_LONGRUN=y CONFIG_X86_LONGHAUL=y CONFIG_X86_E_POWERSAVER=y # # shared options # CONFIG_X86_SPEEDSTEP_LIB=y CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK=y # end of CPU Frequency scaling # # CPU Idle # CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_GOV_TEO=y CONFIG_CPU_IDLE_GOV_HALTPOLL=y CONFIG_HALTPOLL_CPUIDLE=y # end of CPU Idle CONFIG_INTEL_IDLE=y # end of Power management and ACPI options # # Bus options (PCI etc.) # # CONFIG_PCI_GOBIOS is not set # CONFIG_PCI_GOMMCONFIG is not set # CONFIG_PCI_GODIRECT is not set # CONFIG_PCI_GOOLPC is not set CONFIG_PCI_GOANY=y CONFIG_PCI_BIOS=y CONFIG_PCI_DIRECT=y CONFIG_PCI_MMCONFIG=y CONFIG_PCI_OLPC=y CONFIG_PCI_CNB20LE_QUIRK=y CONFIG_ISA_BUS=y CONFIG_ISA_DMA_API=y CONFIG_ISA=y CONFIG_SCx200=y CONFIG_SCx200HR_TIMER=y CONFIG_OLPC=y CONFIG_OLPC_XO1_PM=y CONFIG_OLPC_XO1_RTC=y CONFIG_OLPC_XO1_SCI=y CONFIG_OLPC_XO15_SCI=y CONFIG_ALIX=y CONFIG_NET5501=y CONFIG_GEOS=y CONFIG_AMD_NB=y # end of Bus options (PCI etc.) # # Binary Emulations # CONFIG_COMPAT_32=y # end of Binary Emulations CONFIG_HAVE_ATOMIC_IOMAP=y CONFIG_HAVE_KVM=y CONFIG_HAVE_KVM_PFNCACHE=y CONFIG_HAVE_KVM_IRQCHIP=y CONFIG_HAVE_KVM_IRQFD=y CONFIG_HAVE_KVM_IRQ_ROUTING=y CONFIG_HAVE_KVM_DIRTY_RING=y CONFIG_HAVE_KVM_DIRTY_RING_TSO=y CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y CONFIG_HAVE_KVM_EVENTFD=y CONFIG_KVM_MMIO=y CONFIG_KVM_ASYNC_PF=y CONFIG_HAVE_KVM_MSI=y CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y CONFIG_KVM_VFIO=y CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y CONFIG_HAVE_KVM_IRQ_BYPASS=y CONFIG_HAVE_KVM_NO_POLL=y CONFIG_KVM_XFER_TO_GUEST_WORK=y CONFIG_HAVE_KVM_PM_NOTIFIER=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=y # CONFIG_KVM_WERROR is not set CONFIG_KVM_INTEL=y CONFIG_KVM_AMD=y CONFIG_KVM_XEN=y CONFIG_AS_AVX512=y CONFIG_AS_SHA1_NI=y CONFIG_AS_SHA256_NI=y CONFIG_AS_TPAUSE=y # # General architecture-dependent options # CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y CONFIG_HOTPLUG_SMT=y CONFIG_GENERIC_ENTRY=y CONFIG_KPROBES=y CONFIG_JUMP_LABEL=y CONFIG_STATIC_KEYS_SELFTEST=y CONFIG_STATIC_CALL_SELFTEST=y CONFIG_OPTPROBES=y CONFIG_KPROBES_ON_FTRACE=y CONFIG_UPROBES=y CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_KRETPROBES=y CONFIG_KRETPROBE_ON_RETHOOK=y CONFIG_USER_RETURN_NOTIFIER=y CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_OPTPROBES=y CONFIG_HAVE_KPROBES_ON_FTRACE=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y CONFIG_HAVE_NMI=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_ARCH_HAS_FORTIFY_SOURCE=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_ARCH_32BIT_OFF_T=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y CONFIG_HAVE_USER_RETURN_NOTIFIER=y CONFIG_HAVE_PERF_EVENTS_NMI=y CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y CONFIG_MMU_GATHER_TABLE_FREE=y CONFIG_MMU_GATHER_RCU_TABLE_FREE=y CONFIG_MMU_GATHER_MERGE_VMAS=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y CONFIG_HAVE_CMPXCHG_LOCAL=y CONFIG_HAVE_CMPXCHG_DOUBLE=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y CONFIG_SECCOMP_CACHE_DEBUG=y CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_ARCH_SUPPORTS_LTO_CLANG=y CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y CONFIG_LTO_NONE=y CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOVE_PUD=y CONFIG_HAVE_MOVE_PMD=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_ISA_BUS_API=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y CONFIG_ARCH_USE_MEMREMAP_PROT=y CONFIG_LOCK_EVENT_COUNTS=y CONFIG_ARCH_HAS_MEM_ENCRYPT=y CONFIG_HAVE_STATIC_CALL=y CONFIG_HAVE_PREEMPT_DYNAMIC=y CONFIG_HAVE_PREEMPT_DYNAMIC_CALL=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SPLIT_ARG64=y CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y CONFIG_DYNAMIC_SIGFRAME=y # # GCOV-based kernel profiling # CONFIG_GCOV_KERNEL=y CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # CONFIG_GCOV_PROFILE_ALL is not set # end of GCOV-based kernel profiling CONFIG_HAVE_GCC_PLUGINS=y CONFIG_GCC_PLUGINS=y CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y # end of General architecture-dependent options CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULE_SIG_FORMAT=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODULE_UNLOAD_TAINT_TRACKING=y CONFIG_MODVERSIONS=y CONFIG_ASM_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_MODULE_SIG=y CONFIG_MODULE_SIG_FORCE=y CONFIG_MODULE_SIG_ALL=y CONFIG_MODULE_SIG_SHA1=y # CONFIG_MODULE_SIG_SHA224 is not set # CONFIG_MODULE_SIG_SHA256 is not set # CONFIG_MODULE_SIG_SHA384 is not set # CONFIG_MODULE_SIG_SHA512 is not set CONFIG_MODULE_SIG_HASH="sha1" CONFIG_MODULE_COMPRESS_NONE=y # CONFIG_MODULE_COMPRESS_GZIP is not set # CONFIG_MODULE_COMPRESS_XZ is not set # CONFIG_MODULE_COMPRESS_ZSTD is not set CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLOCK_LEGACY_AUTOLOAD=y CONFIG_BLK_RQ_ALLOC_TIME=y CONFIG_BLK_CGROUP_RWSTAT=y CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_ICQ=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y CONFIG_BLK_DEV_INTEGRITY_T10=y CONFIG_BLK_DEV_ZONED=y CONFIG_BLK_DEV_THROTTLING=y CONFIG_BLK_DEV_THROTTLING_LOW=y CONFIG_BLK_WBT=y CONFIG_BLK_WBT_MQ=y CONFIG_BLK_CGROUP_IOLATENCY=y CONFIG_BLK_CGROUP_FC_APPID=y CONFIG_BLK_CGROUP_IOCOST=y CONFIG_BLK_CGROUP_IOPRIO=y CONFIG_BLK_DEBUG_FS=y CONFIG_BLK_DEBUG_FS_ZONED=y CONFIG_BLK_SED_OPAL=y CONFIG_BLK_INLINE_ENCRYPTION=y CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y # # Partition Types # CONFIG_PARTITION_ADVANCED=y CONFIG_ACORN_PARTITION=y CONFIG_ACORN_PARTITION_CUMANA=y CONFIG_ACORN_PARTITION_EESOX=y CONFIG_ACORN_PARTITION_ICS=y CONFIG_ACORN_PARTITION_ADFS=y CONFIG_ACORN_PARTITION_POWERTEC=y CONFIG_ACORN_PARTITION_RISCIX=y CONFIG_AIX_PARTITION=y CONFIG_OSF_PARTITION=y CONFIG_AMIGA_PARTITION=y CONFIG_ATARI_PARTITION=y CONFIG_MAC_PARTITION=y CONFIG_MSDOS_PARTITION=y CONFIG_BSD_DISKLABEL=y CONFIG_MINIX_SUBPARTITION=y CONFIG_SOLARIS_X86_PARTITION=y CONFIG_UNIXWARE_DISKLABEL=y CONFIG_LDM_PARTITION=y CONFIG_LDM_DEBUG=y CONFIG_SGI_PARTITION=y CONFIG_ULTRIX_PARTITION=y CONFIG_SUN_PARTITION=y CONFIG_KARMA_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_SYSV68_PARTITION=y CONFIG_CMDLINE_PARTITION=y # end of Partition Types CONFIG_BLK_MQ_PCI=y CONFIG_BLK_MQ_VIRTIO=y CONFIG_BLK_MQ_RDMA=y CONFIG_BLK_PM=y CONFIG_BLOCK_HOLDER_DEPRECATED=y CONFIG_BLK_MQ_STACKING=y # # IO Schedulers # CONFIG_MQ_IOSCHED_DEADLINE=y CONFIG_MQ_IOSCHED_KYBER=y CONFIG_IOSCHED_BFQ=y CONFIG_BFQ_GROUP_IOSCHED=y CONFIG_BFQ_CGROUP_DEBUG=y # end of IO Schedulers CONFIG_PREEMPT_NOTIFIERS=y CONFIG_PADATA=y CONFIG_ASN1=y CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_RWSEM_SPIN_ON_OWNER=y CONFIG_LOCK_SPIN_ON_OWNER=y CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y CONFIG_QUEUED_SPINLOCKS=y CONFIG_ARCH_USE_QUEUED_RWLOCKS=y CONFIG_QUEUED_RWLOCKS=y CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y CONFIG_FREEZER=y # # Executable file formats # CONFIG_BINFMT_ELF=y CONFIG_BINFMT_ELF_KUNIT_TEST=y CONFIG_ELFCORE=y CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y CONFIG_BINFMT_SCRIPT=y CONFIG_BINFMT_MISC=y CONFIG_COREDUMP=y # end of Executable file formats # # Memory Management options # CONFIG_ZPOOL=y CONFIG_SWAP=y CONFIG_ZSWAP=y CONFIG_ZSWAP_DEFAULT_ON=y # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y # CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set # CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud" CONFIG_ZBUD=y CONFIG_Z3FOLD=y CONFIG_ZSMALLOC=y CONFIG_ZSMALLOC_STAT=y # # SLAB allocator options # # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set CONFIG_SLAB_MERGE_DEFAULT=y CONFIG_SLAB_FREELIST_RANDOM=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLUB_STATS=y CONFIG_SLUB_CPU_PARTIAL=y # end of SLAB allocator options CONFIG_SHUFFLE_PAGE_ALLOCATOR=y CONFIG_COMPAT_BRK=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_SPARSEMEM_STATIC=y CONFIG_HAVE_FAST_GUP=y CONFIG_MEMORY_ISOLATION=y CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MEMORY_BALLOON=y CONFIG_BALLOON_COMPACTION=y CONFIG_COMPACTION=y CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 CONFIG_PAGE_REPORTING=y CONFIG_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_BOUNCE=y CONFIG_MMU_NOTIFIER=y CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_MEMORY_FAILURE=y CONFIG_HWPOISON_INJECT=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set CONFIG_READ_ONLY_THP_FOR_FS=y CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_FRONTSWAP=y CONFIG_CMA=y CONFIG_CMA_DEBUG=y CONFIG_CMA_DEBUGFS=y CONFIG_CMA_SYSFS=y CONFIG_CMA_AREAS=7 CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_PAGE_IDLE_FLAG=y CONFIG_IDLE_PAGE_TRACKING=y CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y CONFIG_ARCH_HAS_ZONE_DMA_SET=y CONFIG_ZONE_DMA=y CONFIG_HMM_MIRROR=y CONFIG_VMAP_PFN=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_PERCPU_STATS=y CONFIG_GUP_TEST=y CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_MAPPING_DIRTY_HELPERS=y CONFIG_KMAP_LOCAL=y CONFIG_ANON_VMA_NAME=y CONFIG_USERFAULTFD=y CONFIG_LRU_GEN=y CONFIG_LRU_GEN_ENABLED=y CONFIG_LRU_GEN_STATS=y # # Data Access Monitoring # CONFIG_DAMON=y CONFIG_DAMON_KUNIT_TEST=y CONFIG_DAMON_VADDR=y CONFIG_DAMON_PADDR=y CONFIG_DAMON_VADDR_KUNIT_TEST=y CONFIG_DAMON_SYSFS=y CONFIG_DAMON_DBGFS=y CONFIG_DAMON_DBGFS_KUNIT_TEST=y CONFIG_DAMON_RECLAIM=y CONFIG_DAMON_LRU_SORT=y # end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y CONFIG_NET_INGRESS=y CONFIG_NET_EGRESS=y CONFIG_NET_REDIRECT=y CONFIG_SKB_EXTENSIONS=y # # Networking options # CONFIG_PACKET=y CONFIG_PACKET_DIAG=y CONFIG_UNIX=y CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y CONFIG_UNIX_DIAG=y CONFIG_TLS=y CONFIG_TLS_DEVICE=y CONFIG_TLS_TOE=y CONFIG_XFRM=y CONFIG_XFRM_OFFLOAD=y CONFIG_XFRM_ALGO=y CONFIG_XFRM_USER=y CONFIG_XFRM_INTERFACE=y CONFIG_XFRM_SUB_POLICY=y CONFIG_XFRM_MIGRATE=y CONFIG_XFRM_STATISTICS=y CONFIG_XFRM_AH=y CONFIG_XFRM_ESP=y CONFIG_XFRM_IPCOMP=y CONFIG_NET_KEY=y CONFIG_NET_KEY_MIGRATE=y CONFIG_XFRM_ESPINTCP=y CONFIG_SMC=y CONFIG_SMC_DIAG=y CONFIG_XDP_SOCKETS=y CONFIG_XDP_SOCKETS_DIAG=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y CONFIG_IP_FIB_TRIE_STATS=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_ROUTE_CLASSID=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=y CONFIG_NET_IPGRE_DEMUX=y CONFIG_NET_IP_TUNNEL=y CONFIG_NET_IPGRE=y CONFIG_NET_IPGRE_BROADCAST=y CONFIG_IP_MROUTE_COMMON=y CONFIG_IP_MROUTE=y CONFIG_IP_MROUTE_MULTIPLE_TABLES=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_SYN_COOKIES=y CONFIG_NET_IPVTI=y CONFIG_NET_UDP_TUNNEL=y CONFIG_NET_FOU=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_INET_AH=y CONFIG_INET_ESP=y CONFIG_INET_ESP_OFFLOAD=y CONFIG_INET_ESPINTCP=y CONFIG_INET_IPCOMP=y CONFIG_INET_XFRM_TUNNEL=y CONFIG_INET_TUNNEL=y CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y CONFIG_INET_UDP_DIAG=y CONFIG_INET_RAW_DIAG=y CONFIG_INET_DIAG_DESTROY=y CONFIG_TCP_CONG_ADVANCED=y CONFIG_TCP_CONG_BIC=y CONFIG_TCP_CONG_CUBIC=y CONFIG_TCP_CONG_WESTWOOD=y CONFIG_TCP_CONG_HTCP=y CONFIG_TCP_CONG_HSTCP=y CONFIG_TCP_CONG_HYBLA=y CONFIG_TCP_CONG_VEGAS=y CONFIG_TCP_CONG_NV=y CONFIG_TCP_CONG_SCALABLE=y CONFIG_TCP_CONG_LP=y CONFIG_TCP_CONG_VENO=y CONFIG_TCP_CONG_YEAH=y CONFIG_TCP_CONG_ILLINOIS=y CONFIG_TCP_CONG_DCTCP=y CONFIG_TCP_CONG_CDG=y CONFIG_TCP_CONG_BBR=y # CONFIG_DEFAULT_BIC is not set CONFIG_DEFAULT_CUBIC=y # CONFIG_DEFAULT_HTCP is not set # CONFIG_DEFAULT_HYBLA is not set # CONFIG_DEFAULT_VEGAS is not set # CONFIG_DEFAULT_VENO is not set # CONFIG_DEFAULT_WESTWOOD is not set # CONFIG_DEFAULT_DCTCP is not set # CONFIG_DEFAULT_CDG is not set # CONFIG_DEFAULT_BBR is not set # CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_TCP_MD5SIG=y CONFIG_IPV6=y CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTE_INFO=y CONFIG_IPV6_OPTIMISTIC_DAD=y CONFIG_INET6_AH=y CONFIG_INET6_ESP=y CONFIG_INET6_ESP_OFFLOAD=y CONFIG_INET6_ESPINTCP=y CONFIG_INET6_IPCOMP=y CONFIG_IPV6_MIP6=y CONFIG_IPV6_ILA=y CONFIG_INET6_XFRM_TUNNEL=y CONFIG_INET6_TUNNEL=y CONFIG_IPV6_VTI=y CONFIG_IPV6_SIT=y CONFIG_IPV6_SIT_6RD=y CONFIG_IPV6_NDISC_NODETYPE=y CONFIG_IPV6_TUNNEL=y CONFIG_IPV6_GRE=y CONFIG_IPV6_FOU=y CONFIG_IPV6_FOU_TUNNEL=y CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y CONFIG_IPV6_MROUTE=y CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y CONFIG_IPV6_PIMSM_V2=y CONFIG_IPV6_SEG6_LWTUNNEL=y CONFIG_IPV6_SEG6_HMAC=y CONFIG_IPV6_SEG6_BPF=y CONFIG_IPV6_RPL_LWTUNNEL=y CONFIG_IPV6_IOAM6_LWTUNNEL=y CONFIG_NETLABEL=y CONFIG_MPTCP=y CONFIG_INET_MPTCP_DIAG=y CONFIG_MPTCP_IPV6=y CONFIG_MPTCP_KUNIT_TEST=y CONFIG_NETWORK_SECMARK=y CONFIG_NET_PTP_CLASSIFY=y CONFIG_NETWORK_PHY_TIMESTAMPING=y CONFIG_NETFILTER=y CONFIG_NETFILTER_ADVANCED=y CONFIG_BRIDGE_NETFILTER=y # # Core Netfilter Configuration # CONFIG_NETFILTER_INGRESS=y CONFIG_NETFILTER_EGRESS=y CONFIG_NETFILTER_SKIP_EGRESS=y CONFIG_NETFILTER_NETLINK=y CONFIG_NETFILTER_FAMILY_BRIDGE=y CONFIG_NETFILTER_FAMILY_ARP=y CONFIG_NETFILTER_NETLINK_HOOK=y CONFIG_NETFILTER_NETLINK_ACCT=y CONFIG_NETFILTER_NETLINK_QUEUE=y CONFIG_NETFILTER_NETLINK_LOG=y CONFIG_NETFILTER_NETLINK_OSF=y CONFIG_NF_CONNTRACK=y CONFIG_NF_LOG_SYSLOG=y CONFIG_NETFILTER_CONNCOUNT=y CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_ZONES=y CONFIG_NF_CONNTRACK_PROCFS=y CONFIG_NF_CONNTRACK_EVENTS=y CONFIG_NF_CONNTRACK_TIMEOUT=y CONFIG_NF_CONNTRACK_TIMESTAMP=y CONFIG_NF_CONNTRACK_LABELS=y CONFIG_NF_CT_PROTO_DCCP=y CONFIG_NF_CT_PROTO_GRE=y CONFIG_NF_CT_PROTO_SCTP=y CONFIG_NF_CT_PROTO_UDPLITE=y CONFIG_NF_CONNTRACK_AMANDA=y CONFIG_NF_CONNTRACK_FTP=y CONFIG_NF_CONNTRACK_H323=y CONFIG_NF_CONNTRACK_IRC=y CONFIG_NF_CONNTRACK_BROADCAST=y CONFIG_NF_CONNTRACK_NETBIOS_NS=y CONFIG_NF_CONNTRACK_SNMP=y CONFIG_NF_CONNTRACK_PPTP=y CONFIG_NF_CONNTRACK_SANE=y CONFIG_NF_CONNTRACK_SIP=y CONFIG_NF_CONNTRACK_TFTP=y CONFIG_NF_CT_NETLINK=y CONFIG_NF_CT_NETLINK_TIMEOUT=y CONFIG_NF_CT_NETLINK_HELPER=y CONFIG_NETFILTER_NETLINK_GLUE_CT=y CONFIG_NF_NAT=y CONFIG_NF_NAT_AMANDA=y CONFIG_NF_NAT_FTP=y CONFIG_NF_NAT_IRC=y CONFIG_NF_NAT_SIP=y CONFIG_NF_NAT_TFTP=y CONFIG_NF_NAT_REDIRECT=y CONFIG_NF_NAT_MASQUERADE=y CONFIG_NETFILTER_SYNPROXY=y CONFIG_NF_TABLES=y CONFIG_NF_TABLES_INET=y CONFIG_NF_TABLES_NETDEV=y CONFIG_NFT_NUMGEN=y CONFIG_NFT_CT=y CONFIG_NFT_FLOW_OFFLOAD=y CONFIG_NFT_CONNLIMIT=y CONFIG_NFT_LOG=y CONFIG_NFT_LIMIT=y CONFIG_NFT_MASQ=y CONFIG_NFT_REDIR=y CONFIG_NFT_NAT=y CONFIG_NFT_TUNNEL=y # CONFIG_NFT_OBJREF is not set CONFIG_NFT_QUEUE=y CONFIG_NFT_QUOTA=y CONFIG_NFT_REJECT=y CONFIG_NFT_REJECT_INET=y CONFIG_NFT_COMPAT=y CONFIG_NFT_HASH=y CONFIG_NFT_FIB=y CONFIG_NFT_FIB_INET=y CONFIG_NFT_XFRM=y CONFIG_NFT_SOCKET=y CONFIG_NFT_OSF=y CONFIG_NFT_TPROXY=y CONFIG_NFT_SYNPROXY=y CONFIG_NF_DUP_NETDEV=y CONFIG_NFT_DUP_NETDEV=y CONFIG_NFT_FWD_NETDEV=y CONFIG_NFT_FIB_NETDEV=y CONFIG_NFT_REJECT_NETDEV=y CONFIG_NF_FLOW_TABLE_INET=y CONFIG_NF_FLOW_TABLE=y CONFIG_NF_FLOW_TABLE_PROCFS=y CONFIG_NETFILTER_XTABLES=y # # Xtables combined modules # CONFIG_NETFILTER_XT_MARK=y CONFIG_NETFILTER_XT_CONNMARK=y CONFIG_NETFILTER_XT_SET=y # # Xtables targets # CONFIG_NETFILTER_XT_TARGET_AUDIT=y CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y CONFIG_NETFILTER_XT_TARGET_CONNMARK=y CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y CONFIG_NETFILTER_XT_TARGET_CT=y CONFIG_NETFILTER_XT_TARGET_DSCP=y CONFIG_NETFILTER_XT_TARGET_HL=y CONFIG_NETFILTER_XT_TARGET_HMARK=y CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y CONFIG_NETFILTER_XT_TARGET_LED=y CONFIG_NETFILTER_XT_TARGET_LOG=y CONFIG_NETFILTER_XT_TARGET_MARK=y CONFIG_NETFILTER_XT_NAT=y CONFIG_NETFILTER_XT_TARGET_NETMAP=y CONFIG_NETFILTER_XT_TARGET_NFLOG=y CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y CONFIG_NETFILTER_XT_TARGET_NOTRACK=y CONFIG_NETFILTER_XT_TARGET_RATEEST=y CONFIG_NETFILTER_XT_TARGET_REDIRECT=y CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y CONFIG_NETFILTER_XT_TARGET_TEE=y CONFIG_NETFILTER_XT_TARGET_TPROXY=y CONFIG_NETFILTER_XT_TARGET_TRACE=y CONFIG_NETFILTER_XT_TARGET_SECMARK=y CONFIG_NETFILTER_XT_TARGET_TCPMSS=y CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y # # Xtables matches # CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y CONFIG_NETFILTER_XT_MATCH_BPF=y CONFIG_NETFILTER_XT_MATCH_CGROUP=y CONFIG_NETFILTER_XT_MATCH_CLUSTER=y CONFIG_NETFILTER_XT_MATCH_COMMENT=y CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y CONFIG_NETFILTER_XT_MATCH_CONNLABEL=y CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y CONFIG_NETFILTER_XT_MATCH_CONNMARK=y CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y CONFIG_NETFILTER_XT_MATCH_CPU=y CONFIG_NETFILTER_XT_MATCH_DCCP=y CONFIG_NETFILTER_XT_MATCH_DEVGROUP=y CONFIG_NETFILTER_XT_MATCH_DSCP=y CONFIG_NETFILTER_XT_MATCH_ECN=y CONFIG_NETFILTER_XT_MATCH_ESP=y CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y CONFIG_NETFILTER_XT_MATCH_HELPER=y CONFIG_NETFILTER_XT_MATCH_HL=y CONFIG_NETFILTER_XT_MATCH_IPCOMP=y CONFIG_NETFILTER_XT_MATCH_IPRANGE=y CONFIG_NETFILTER_XT_MATCH_IPVS=y CONFIG_NETFILTER_XT_MATCH_L2TP=y CONFIG_NETFILTER_XT_MATCH_LENGTH=y CONFIG_NETFILTER_XT_MATCH_LIMIT=y CONFIG_NETFILTER_XT_MATCH_MAC=y CONFIG_NETFILTER_XT_MATCH_MARK=y CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y CONFIG_NETFILTER_XT_MATCH_NFACCT=y CONFIG_NETFILTER_XT_MATCH_OSF=y CONFIG_NETFILTER_XT_MATCH_OWNER=y CONFIG_NETFILTER_XT_MATCH_POLICY=y CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y CONFIG_NETFILTER_XT_MATCH_QUOTA=y CONFIG_NETFILTER_XT_MATCH_RATEEST=y CONFIG_NETFILTER_XT_MATCH_REALM=y CONFIG_NETFILTER_XT_MATCH_RECENT=y CONFIG_NETFILTER_XT_MATCH_SCTP=y CONFIG_NETFILTER_XT_MATCH_SOCKET=y CONFIG_NETFILTER_XT_MATCH_STATE=y CONFIG_NETFILTER_XT_MATCH_STATISTIC=y CONFIG_NETFILTER_XT_MATCH_STRING=y CONFIG_NETFILTER_XT_MATCH_TCPMSS=y CONFIG_NETFILTER_XT_MATCH_TIME=y CONFIG_NETFILTER_XT_MATCH_U32=y # end of Core Netfilter Configuration CONFIG_IP_SET=y CONFIG_IP_SET_MAX=256 CONFIG_IP_SET_BITMAP_IP=y CONFIG_IP_SET_BITMAP_IPMAC=y CONFIG_IP_SET_BITMAP_PORT=y CONFIG_IP_SET_HASH_IP=y CONFIG_IP_SET_HASH_IPMARK=y CONFIG_IP_SET_HASH_IPPORT=y CONFIG_IP_SET_HASH_IPPORTIP=y CONFIG_IP_SET_HASH_IPPORTNET=y CONFIG_IP_SET_HASH_IPMAC=y CONFIG_IP_SET_HASH_MAC=y CONFIG_IP_SET_HASH_NETPORTNET=y CONFIG_IP_SET_HASH_NET=y CONFIG_IP_SET_HASH_NETNET=y CONFIG_IP_SET_HASH_NETPORT=y CONFIG_IP_SET_HASH_NETIFACE=y CONFIG_IP_SET_LIST_SET=y CONFIG_IP_VS=y CONFIG_IP_VS_IPV6=y CONFIG_IP_VS_DEBUG=y CONFIG_IP_VS_TAB_BITS=12 # # IPVS transport protocol load balancing support # CONFIG_IP_VS_PROTO_TCP=y CONFIG_IP_VS_PROTO_UDP=y CONFIG_IP_VS_PROTO_AH_ESP=y CONFIG_IP_VS_PROTO_ESP=y CONFIG_IP_VS_PROTO_AH=y CONFIG_IP_VS_PROTO_SCTP=y # # IPVS scheduler # CONFIG_IP_VS_RR=y CONFIG_IP_VS_WRR=y CONFIG_IP_VS_LC=y CONFIG_IP_VS_WLC=y CONFIG_IP_VS_FO=y CONFIG_IP_VS_OVF=y CONFIG_IP_VS_LBLC=y CONFIG_IP_VS_LBLCR=y CONFIG_IP_VS_DH=y CONFIG_IP_VS_SH=y CONFIG_IP_VS_MH=y CONFIG_IP_VS_SED=y CONFIG_IP_VS_NQ=y CONFIG_IP_VS_TWOS=y # # IPVS SH scheduler # CONFIG_IP_VS_SH_TAB_BITS=8 # # IPVS MH scheduler # CONFIG_IP_VS_MH_TAB_INDEX=12 # # IPVS application helper # CONFIG_IP_VS_FTP=y CONFIG_IP_VS_NFCT=y CONFIG_IP_VS_PE_SIP=y # # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=y CONFIG_NF_SOCKET_IPV4=y CONFIG_NF_TPROXY_IPV4=y CONFIG_NF_TABLES_IPV4=y CONFIG_NFT_REJECT_IPV4=y CONFIG_NFT_DUP_IPV4=y CONFIG_NFT_FIB_IPV4=y CONFIG_NF_TABLES_ARP=y CONFIG_NF_DUP_IPV4=y CONFIG_NF_LOG_ARP=y CONFIG_NF_LOG_IPV4=y CONFIG_NF_REJECT_IPV4=y CONFIG_NF_NAT_SNMP_BASIC=y CONFIG_NF_NAT_PPTP=y CONFIG_NF_NAT_H323=y CONFIG_IP_NF_IPTABLES=y CONFIG_IP_NF_MATCH_AH=y CONFIG_IP_NF_MATCH_ECN=y CONFIG_IP_NF_MATCH_RPFILTER=y CONFIG_IP_NF_MATCH_TTL=y CONFIG_IP_NF_FILTER=y CONFIG_IP_NF_TARGET_REJECT=y CONFIG_IP_NF_TARGET_SYNPROXY=y CONFIG_IP_NF_NAT=y CONFIG_IP_NF_TARGET_MASQUERADE=y CONFIG_IP_NF_TARGET_NETMAP=y CONFIG_IP_NF_TARGET_REDIRECT=y CONFIG_IP_NF_MANGLE=y CONFIG_IP_NF_TARGET_CLUSTERIP=y CONFIG_IP_NF_TARGET_ECN=y CONFIG_IP_NF_TARGET_TTL=y CONFIG_IP_NF_RAW=y CONFIG_IP_NF_SECURITY=y CONFIG_IP_NF_ARPTABLES=y CONFIG_IP_NF_ARPFILTER=y CONFIG_IP_NF_ARP_MANGLE=y # end of IP: Netfilter Configuration # # IPv6: Netfilter Configuration # CONFIG_NF_SOCKET_IPV6=y CONFIG_NF_TPROXY_IPV6=y CONFIG_NF_TABLES_IPV6=y CONFIG_NFT_REJECT_IPV6=y CONFIG_NFT_DUP_IPV6=y CONFIG_NFT_FIB_IPV6=y CONFIG_NF_DUP_IPV6=y CONFIG_NF_REJECT_IPV6=y CONFIG_NF_LOG_IPV6=y CONFIG_IP6_NF_IPTABLES=y CONFIG_IP6_NF_MATCH_AH=y CONFIG_IP6_NF_MATCH_EUI64=y CONFIG_IP6_NF_MATCH_FRAG=y CONFIG_IP6_NF_MATCH_OPTS=y CONFIG_IP6_NF_MATCH_HL=y CONFIG_IP6_NF_MATCH_IPV6HEADER=y CONFIG_IP6_NF_MATCH_MH=y CONFIG_IP6_NF_MATCH_RPFILTER=y CONFIG_IP6_NF_MATCH_RT=y CONFIG_IP6_NF_MATCH_SRH=y CONFIG_IP6_NF_TARGET_HL=y CONFIG_IP6_NF_FILTER=y CONFIG_IP6_NF_TARGET_REJECT=y CONFIG_IP6_NF_TARGET_SYNPROXY=y CONFIG_IP6_NF_MANGLE=y CONFIG_IP6_NF_RAW=y CONFIG_IP6_NF_SECURITY=y CONFIG_IP6_NF_NAT=y CONFIG_IP6_NF_TARGET_MASQUERADE=y CONFIG_IP6_NF_TARGET_NPT=y # end of IPv6: Netfilter Configuration CONFIG_NF_DEFRAG_IPV6=y CONFIG_NF_TABLES_BRIDGE=y CONFIG_NFT_BRIDGE_META=y CONFIG_NFT_BRIDGE_REJECT=y CONFIG_NF_CONNTRACK_BRIDGE=y CONFIG_BRIDGE_NF_EBTABLES=y CONFIG_BRIDGE_EBT_BROUTE=y CONFIG_BRIDGE_EBT_T_FILTER=y CONFIG_BRIDGE_EBT_T_NAT=y CONFIG_BRIDGE_EBT_802_3=y CONFIG_BRIDGE_EBT_AMONG=y CONFIG_BRIDGE_EBT_ARP=y CONFIG_BRIDGE_EBT_IP=y CONFIG_BRIDGE_EBT_IP6=y CONFIG_BRIDGE_EBT_LIMIT=y CONFIG_BRIDGE_EBT_MARK=y CONFIG_BRIDGE_EBT_PKTTYPE=y CONFIG_BRIDGE_EBT_STP=y CONFIG_BRIDGE_EBT_VLAN=y CONFIG_BRIDGE_EBT_ARPREPLY=y CONFIG_BRIDGE_EBT_DNAT=y CONFIG_BRIDGE_EBT_MARK_T=y CONFIG_BRIDGE_EBT_REDIRECT=y CONFIG_BRIDGE_EBT_SNAT=y CONFIG_BRIDGE_EBT_LOG=y CONFIG_BRIDGE_EBT_NFLOG=y CONFIG_BPFILTER=y CONFIG_BPFILTER_UMH=y CONFIG_IP_DCCP=y CONFIG_INET_DCCP_DIAG=y # # DCCP CCIDs Configuration # CONFIG_IP_DCCP_CCID2_DEBUG=y CONFIG_IP_DCCP_CCID3=y CONFIG_IP_DCCP_CCID3_DEBUG=y CONFIG_IP_DCCP_TFRC_LIB=y CONFIG_IP_DCCP_TFRC_DEBUG=y # end of DCCP CCIDs Configuration # # DCCP Kernel Hacking # CONFIG_IP_DCCP_DEBUG=y # end of DCCP Kernel Hacking CONFIG_IP_SCTP=y CONFIG_SCTP_DBG_OBJCNT=y CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set CONFIG_SCTP_COOKIE_HMAC_MD5=y CONFIG_SCTP_COOKIE_HMAC_SHA1=y CONFIG_INET_SCTP_DIAG=y CONFIG_RDS=y CONFIG_RDS_RDMA=y CONFIG_RDS_TCP=y CONFIG_RDS_DEBUG=y CONFIG_TIPC=y CONFIG_TIPC_MEDIA_IB=y CONFIG_TIPC_MEDIA_UDP=y CONFIG_TIPC_CRYPTO=y CONFIG_TIPC_DIAG=y CONFIG_ATM=y CONFIG_ATM_CLIP=y CONFIG_ATM_CLIP_NO_ICMP=y CONFIG_ATM_LANE=y CONFIG_ATM_MPOA=y CONFIG_ATM_BR2684=y CONFIG_ATM_BR2684_IPFILTER=y CONFIG_L2TP=y CONFIG_L2TP_DEBUGFS=y CONFIG_L2TP_V3=y CONFIG_L2TP_IP=y CONFIG_L2TP_ETH=y CONFIG_STP=y CONFIG_GARP=y CONFIG_MRP=y CONFIG_BRIDGE=y CONFIG_BRIDGE_IGMP_SNOOPING=y CONFIG_BRIDGE_VLAN_FILTERING=y CONFIG_BRIDGE_MRP=y CONFIG_BRIDGE_CFM=y CONFIG_NET_DSA=y CONFIG_NET_DSA_TAG_AR9331=y CONFIG_NET_DSA_TAG_BRCM_COMMON=y CONFIG_NET_DSA_TAG_BRCM=y CONFIG_NET_DSA_TAG_BRCM_LEGACY=y CONFIG_NET_DSA_TAG_BRCM_PREPEND=y CONFIG_NET_DSA_TAG_HELLCREEK=y CONFIG_NET_DSA_TAG_GSWIP=y CONFIG_NET_DSA_TAG_DSA_COMMON=y CONFIG_NET_DSA_TAG_DSA=y CONFIG_NET_DSA_TAG_EDSA=y CONFIG_NET_DSA_TAG_MTK=y CONFIG_NET_DSA_TAG_KSZ=y CONFIG_NET_DSA_TAG_OCELOT=y CONFIG_NET_DSA_TAG_OCELOT_8021Q=y CONFIG_NET_DSA_TAG_QCA=y CONFIG_NET_DSA_TAG_RTL4_A=y CONFIG_NET_DSA_TAG_RTL8_4=y CONFIG_NET_DSA_TAG_RZN1_A5PSW=y CONFIG_NET_DSA_TAG_LAN9303=y CONFIG_NET_DSA_TAG_SJA1105=y CONFIG_NET_DSA_TAG_TRAILER=y CONFIG_NET_DSA_TAG_XRS700X=y CONFIG_VLAN_8021Q=y CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y CONFIG_LLC=y CONFIG_LLC2=y CONFIG_ATALK=y CONFIG_DEV_APPLETALK=y CONFIG_COPS=y CONFIG_COPS_DAYNA=y CONFIG_COPS_TANGENT=y CONFIG_IPDDP=y CONFIG_IPDDP_ENCAP=y CONFIG_X25=y CONFIG_LAPB=y CONFIG_PHONET=y CONFIG_6LOWPAN=y CONFIG_6LOWPAN_DEBUGFS=y CONFIG_6LOWPAN_NHC=y CONFIG_6LOWPAN_NHC_DEST=y CONFIG_6LOWPAN_NHC_FRAGMENT=y CONFIG_6LOWPAN_NHC_HOP=y CONFIG_6LOWPAN_NHC_IPV6=y CONFIG_6LOWPAN_NHC_MOBILITY=y CONFIG_6LOWPAN_NHC_ROUTING=y CONFIG_6LOWPAN_NHC_UDP=y CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=y CONFIG_6LOWPAN_GHC_UDP=y CONFIG_6LOWPAN_GHC_ICMPV6=y CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=y CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=y CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=y CONFIG_IEEE802154=y CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y CONFIG_IEEE802154_SOCKET=y CONFIG_IEEE802154_6LOWPAN=y CONFIG_MAC802154=y CONFIG_NET_SCHED=y # # Queueing/Scheduling # CONFIG_NET_SCH_CBQ=y CONFIG_NET_SCH_HTB=y CONFIG_NET_SCH_HFSC=y CONFIG_NET_SCH_ATM=y CONFIG_NET_SCH_PRIO=y CONFIG_NET_SCH_MULTIQ=y CONFIG_NET_SCH_RED=y CONFIG_NET_SCH_SFB=y CONFIG_NET_SCH_SFQ=y CONFIG_NET_SCH_TEQL=y CONFIG_NET_SCH_TBF=y CONFIG_NET_SCH_CBS=y CONFIG_NET_SCH_ETF=y CONFIG_NET_SCH_TAPRIO=y CONFIG_NET_SCH_GRED=y CONFIG_NET_SCH_DSMARK=y CONFIG_NET_SCH_NETEM=y CONFIG_NET_SCH_DRR=y CONFIG_NET_SCH_MQPRIO=y CONFIG_NET_SCH_SKBPRIO=y CONFIG_NET_SCH_CHOKE=y CONFIG_NET_SCH_QFQ=y CONFIG_NET_SCH_CODEL=y CONFIG_NET_SCH_FQ_CODEL=y CONFIG_NET_SCH_CAKE=y CONFIG_NET_SCH_FQ=y CONFIG_NET_SCH_HHF=y CONFIG_NET_SCH_PIE=y CONFIG_NET_SCH_FQ_PIE=y CONFIG_NET_SCH_INGRESS=y CONFIG_NET_SCH_PLUG=y CONFIG_NET_SCH_ETS=y CONFIG_NET_SCH_DEFAULT=y # CONFIG_DEFAULT_FQ is not set # CONFIG_DEFAULT_CODEL is not set # CONFIG_DEFAULT_FQ_CODEL is not set # CONFIG_DEFAULT_FQ_PIE is not set # CONFIG_DEFAULT_SFQ is not set CONFIG_DEFAULT_PFIFO_FAST=y CONFIG_DEFAULT_NET_SCH="pfifo_fast" # # Classification # CONFIG_NET_CLS=y CONFIG_NET_CLS_BASIC=y CONFIG_NET_CLS_TCINDEX=y CONFIG_NET_CLS_ROUTE4=y CONFIG_NET_CLS_FW=y CONFIG_NET_CLS_U32=y CONFIG_CLS_U32_PERF=y CONFIG_CLS_U32_MARK=y CONFIG_NET_CLS_RSVP=y CONFIG_NET_CLS_RSVP6=y CONFIG_NET_CLS_FLOW=y CONFIG_NET_CLS_CGROUP=y CONFIG_NET_CLS_BPF=y CONFIG_NET_CLS_FLOWER=y CONFIG_NET_CLS_MATCHALL=y CONFIG_NET_EMATCH=y CONFIG_NET_EMATCH_STACK=32 CONFIG_NET_EMATCH_CMP=y CONFIG_NET_EMATCH_NBYTE=y CONFIG_NET_EMATCH_U32=y CONFIG_NET_EMATCH_META=y CONFIG_NET_EMATCH_TEXT=y CONFIG_NET_EMATCH_CANID=y CONFIG_NET_EMATCH_IPSET=y CONFIG_NET_EMATCH_IPT=y CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=y CONFIG_NET_ACT_GACT=y CONFIG_GACT_PROB=y CONFIG_NET_ACT_MIRRED=y CONFIG_NET_ACT_SAMPLE=y CONFIG_NET_ACT_IPT=y CONFIG_NET_ACT_NAT=y CONFIG_NET_ACT_PEDIT=y CONFIG_NET_ACT_SIMP=y CONFIG_NET_ACT_SKBEDIT=y CONFIG_NET_ACT_CSUM=y CONFIG_NET_ACT_MPLS=y CONFIG_NET_ACT_VLAN=y CONFIG_NET_ACT_BPF=y CONFIG_NET_ACT_CONNMARK=y CONFIG_NET_ACT_CTINFO=y CONFIG_NET_ACT_SKBMOD=y CONFIG_NET_ACT_IFE=y CONFIG_NET_ACT_TUNNEL_KEY=y CONFIG_NET_ACT_CT=y CONFIG_NET_ACT_GATE=y CONFIG_NET_IFE_SKBMARK=y CONFIG_NET_IFE_SKBPRIO=y CONFIG_NET_IFE_SKBTCINDEX=y CONFIG_NET_TC_SKB_EXT=y CONFIG_NET_SCH_FIFO=y CONFIG_DCB=y CONFIG_DNS_RESOLVER=y CONFIG_BATMAN_ADV=y CONFIG_BATMAN_ADV_BATMAN_V=y CONFIG_BATMAN_ADV_BLA=y CONFIG_BATMAN_ADV_DAT=y CONFIG_BATMAN_ADV_NC=y CONFIG_BATMAN_ADV_MCAST=y CONFIG_BATMAN_ADV_DEBUG=y CONFIG_BATMAN_ADV_TRACING=y CONFIG_OPENVSWITCH=y CONFIG_OPENVSWITCH_GRE=y CONFIG_OPENVSWITCH_VXLAN=y CONFIG_OPENVSWITCH_GENEVE=y CONFIG_VSOCKETS=y CONFIG_VSOCKETS_DIAG=y CONFIG_VSOCKETS_LOOPBACK=y CONFIG_VMWARE_VMCI_VSOCKETS=y CONFIG_VIRTIO_VSOCKETS=y CONFIG_VIRTIO_VSOCKETS_COMMON=y CONFIG_HYPERV_VSOCKETS=y CONFIG_NETLINK_DIAG=y CONFIG_MPLS=y CONFIG_NET_MPLS_GSO=y CONFIG_MPLS_ROUTING=y CONFIG_MPLS_IPTUNNEL=y CONFIG_NET_NSH=y CONFIG_HSR=y CONFIG_NET_SWITCHDEV=y CONFIG_NET_L3_MASTER_DEV=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y CONFIG_QRTR_TUN=y CONFIG_QRTR_MHI=y CONFIG_NET_NCSI=y CONFIG_NCSI_OEM_CMD_GET_MAC=y CONFIG_NCSI_OEM_CMD_KEEP_PHY=y CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y CONFIG_CGROUP_NET_PRIO=y CONFIG_CGROUP_NET_CLASSID=y CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y CONFIG_BPF_STREAM_PARSER=y CONFIG_NET_FLOW_LIMIT=y # # Network testing # CONFIG_NET_PKTGEN=y CONFIG_NET_DROP_MONITOR=y # end of Network testing # end of Networking options CONFIG_HAMRADIO=y # # Packet Radio protocols # CONFIG_AX25=y CONFIG_AX25_DAMA_SLAVE=y CONFIG_NETROM=y CONFIG_ROSE=y # # AX.25 network device drivers # CONFIG_MKISS=y CONFIG_6PACK=y CONFIG_BPQETHER=y CONFIG_SCC=y CONFIG_SCC_DELAY=y CONFIG_SCC_TRXECHO=y CONFIG_BAYCOM_SER_FDX=y CONFIG_BAYCOM_SER_HDX=y CONFIG_BAYCOM_PAR=y CONFIG_BAYCOM_EPP=y CONFIG_YAM=y # end of AX.25 network device drivers CONFIG_CAN=y CONFIG_CAN_RAW=y CONFIG_CAN_BCM=y CONFIG_CAN_GW=y CONFIG_CAN_J1939=y CONFIG_CAN_ISOTP=y CONFIG_BT=y CONFIG_BT_BREDR=y CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=y CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_CMTP=y CONFIG_BT_HIDP=y CONFIG_BT_HS=y CONFIG_BT_LE=y CONFIG_BT_6LOWPAN=y CONFIG_BT_LEDS=y CONFIG_BT_MSFTEXT=y CONFIG_BT_AOSPEXT=y CONFIG_BT_DEBUGFS=y CONFIG_BT_SELFTEST=y CONFIG_BT_SELFTEST_ECDH=y CONFIG_BT_SELFTEST_SMP=y # # Bluetooth device drivers # CONFIG_BT_INTEL=y CONFIG_BT_BCM=y CONFIG_BT_RTL=y CONFIG_BT_QCA=y CONFIG_BT_MTK=y CONFIG_BT_HCIBTUSB=y CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y CONFIG_BT_HCIBTUSB_BCM=y CONFIG_BT_HCIBTUSB_MTK=y CONFIG_BT_HCIBTUSB_RTL=y CONFIG_BT_HCIBTSDIO=y CONFIG_BT_HCIUART=y CONFIG_BT_HCIUART_SERDEV=y CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_NOKIA=y CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_ATH3K=y CONFIG_BT_HCIUART_LL=y CONFIG_BT_HCIUART_3WIRE=y CONFIG_BT_HCIUART_INTEL=y CONFIG_BT_HCIUART_BCM=y CONFIG_BT_HCIUART_RTL=y CONFIG_BT_HCIUART_QCA=y CONFIG_BT_HCIUART_AG6XX=y CONFIG_BT_HCIUART_MRVL=y CONFIG_BT_HCIBCM203X=y CONFIG_BT_HCIBPA10X=y CONFIG_BT_HCIBFUSB=y CONFIG_BT_HCIDTL1=y CONFIG_BT_HCIBT3C=y CONFIG_BT_HCIBLUECARD=y CONFIG_BT_HCIVHCI=y CONFIG_BT_MRVL=y CONFIG_BT_MRVL_SDIO=y CONFIG_BT_ATH3K=y CONFIG_BT_MTKSDIO=y CONFIG_BT_MTKUART=y CONFIG_BT_HCIRSI=y CONFIG_BT_VIRTIO=y # end of Bluetooth device drivers CONFIG_AF_RXRPC=y CONFIG_AF_RXRPC_IPV6=y CONFIG_AF_RXRPC_INJECT_LOSS=y CONFIG_AF_RXRPC_DEBUG=y CONFIG_RXKAD=y CONFIG_AF_KCM=y CONFIG_STREAM_PARSER=y CONFIG_MCTP=y CONFIG_MCTP_TEST=y CONFIG_MCTP_FLOWS=y CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y CONFIG_WEXT_CORE=y CONFIG_WEXT_PROC=y CONFIG_WEXT_SPY=y CONFIG_WEXT_PRIV=y CONFIG_CFG80211=y CONFIG_NL80211_TESTMODE=y CONFIG_CFG80211_DEVELOPER_WARNINGS=y CONFIG_CFG80211_CERTIFICATION_ONUS=y CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y CONFIG_CFG80211_EXTRA_REGDB_KEYDIR="" CONFIG_CFG80211_REG_CELLULAR_HINTS=y CONFIG_CFG80211_REG_RELAX_NO_IR=y CONFIG_CFG80211_DEFAULT_PS=y CONFIG_CFG80211_DEBUGFS=y CONFIG_CFG80211_CRDA_SUPPORT=y CONFIG_CFG80211_WEXT=y CONFIG_CFG80211_WEXT_EXPORT=y CONFIG_LIB80211=y CONFIG_LIB80211_CRYPT_WEP=y CONFIG_LIB80211_CRYPT_CCMP=y CONFIG_LIB80211_CRYPT_TKIP=y CONFIG_LIB80211_DEBUG=y CONFIG_MAC80211=y CONFIG_MAC80211_HAS_RC=y CONFIG_MAC80211_RC_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" CONFIG_MAC80211_MESH=y CONFIG_MAC80211_LEDS=y CONFIG_MAC80211_DEBUGFS=y CONFIG_MAC80211_MESSAGE_TRACING=y CONFIG_MAC80211_DEBUG_MENU=y CONFIG_MAC80211_NOINLINE=y CONFIG_MAC80211_VERBOSE_DEBUG=y CONFIG_MAC80211_MLME_DEBUG=y CONFIG_MAC80211_STA_DEBUG=y CONFIG_MAC80211_HT_DEBUG=y CONFIG_MAC80211_OCB_DEBUG=y CONFIG_MAC80211_IBSS_DEBUG=y CONFIG_MAC80211_PS_DEBUG=y CONFIG_MAC80211_MPL_DEBUG=y CONFIG_MAC80211_MPATH_DEBUG=y CONFIG_MAC80211_MHWMP_DEBUG=y CONFIG_MAC80211_MESH_SYNC_DEBUG=y CONFIG_MAC80211_MESH_CSA_DEBUG=y CONFIG_MAC80211_MESH_PS_DEBUG=y CONFIG_MAC80211_TDLS_DEBUG=y CONFIG_MAC80211_DEBUG_COUNTERS=y CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 CONFIG_RFKILL=y CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y CONFIG_RFKILL_GPIO=y CONFIG_NET_9P=y CONFIG_NET_9P_FD=y CONFIG_NET_9P_VIRTIO=y CONFIG_NET_9P_RDMA=y CONFIG_NET_9P_DEBUG=y CONFIG_CAIF=y CONFIG_CAIF_DEBUG=y CONFIG_CAIF_NETDEV=y CONFIG_CAIF_USB=y CONFIG_CEPH_LIB=y CONFIG_CEPH_LIB_PRETTYDEBUG=y CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y CONFIG_NFC=y CONFIG_NFC_DIGITAL=y CONFIG_NFC_NCI=y CONFIG_NFC_NCI_SPI=y CONFIG_NFC_NCI_UART=y CONFIG_NFC_HCI=y CONFIG_NFC_SHDLC=y # # Near Field Communication (NFC) devices # CONFIG_NFC_TRF7970A=y CONFIG_NFC_MEI_PHY=y CONFIG_NFC_SIM=y CONFIG_NFC_PORT100=y CONFIG_NFC_VIRTUAL_NCI=y CONFIG_NFC_FDP=y CONFIG_NFC_FDP_I2C=y CONFIG_NFC_PN544=y CONFIG_NFC_PN544_I2C=y CONFIG_NFC_PN544_MEI=y CONFIG_NFC_PN533=y CONFIG_NFC_PN533_USB=y CONFIG_NFC_PN533_I2C=y CONFIG_NFC_PN532_UART=y CONFIG_NFC_MICROREAD=y CONFIG_NFC_MICROREAD_I2C=y CONFIG_NFC_MICROREAD_MEI=y CONFIG_NFC_MRVL=y CONFIG_NFC_MRVL_USB=y CONFIG_NFC_MRVL_UART=y CONFIG_NFC_MRVL_I2C=y CONFIG_NFC_MRVL_SPI=y CONFIG_NFC_ST21NFCA=y CONFIG_NFC_ST21NFCA_I2C=y CONFIG_NFC_ST_NCI=y CONFIG_NFC_ST_NCI_I2C=y CONFIG_NFC_ST_NCI_SPI=y CONFIG_NFC_NXP_NCI=y CONFIG_NFC_NXP_NCI_I2C=y CONFIG_NFC_S3FWRN5=y CONFIG_NFC_S3FWRN5_I2C=y CONFIG_NFC_S3FWRN82_UART=y CONFIG_NFC_ST95HF=y # end of Near Field Communication (NFC) devices CONFIG_PSAMPLE=y CONFIG_NET_IFE=y CONFIG_LWTUNNEL=y CONFIG_LWTUNNEL_BPF=y CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y CONFIG_SOCK_VALIDATE_XMIT=y CONFIG_NET_SELFTESTS=y CONFIG_NET_SOCK_MSG=y CONFIG_NET_DEVLINK=y CONFIG_PAGE_POOL=y CONFIG_PAGE_POOL_STATS=y CONFIG_FAILOVER=y CONFIG_ETHTOOL_NETLINK=y CONFIG_NETDEV_ADDR_LIST_TEST=y # # Device Drivers # CONFIG_HAVE_EISA=y CONFIG_EISA=y CONFIG_EISA_VLB_PRIMING=y CONFIG_EISA_PCI_EISA=y CONFIG_EISA_VIRTUAL_ROOT=y CONFIG_EISA_NAMES=y CONFIG_HAVE_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCIEPORTBUS=y CONFIG_HOTPLUG_PCI_PCIE=y CONFIG_PCIEAER=y CONFIG_PCIEAER_INJECT=y CONFIG_PCIE_ECRC=y CONFIG_PCIEASPM=y CONFIG_PCIEASPM_DEFAULT=y # CONFIG_PCIEASPM_POWERSAVE is not set # CONFIG_PCIEASPM_POWER_SUPERSAVE is not set # CONFIG_PCIEASPM_PERFORMANCE is not set CONFIG_PCIE_PME=y CONFIG_PCIE_DPC=y CONFIG_PCIE_PTM=y CONFIG_PCIE_EDR=y CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCI_QUIRKS=y CONFIG_PCI_DEBUG=y CONFIG_PCI_REALLOC_ENABLE_AUTO=y CONFIG_PCI_STUB=y CONFIG_PCI_PF_STUB=y CONFIG_PCI_ATS=y CONFIG_PCI_DOE=y CONFIG_PCI_ECAM=y CONFIG_PCI_LOCKLESS_CONFIG=y CONFIG_PCI_IOV=y CONFIG_PCI_PRI=y CONFIG_PCI_PASID=y CONFIG_PCI_LABEL=y # CONFIG_PCIE_BUS_TUNE_OFF is not set CONFIG_PCIE_BUS_DEFAULT=y # CONFIG_PCIE_BUS_SAFE is not set # CONFIG_PCIE_BUS_PERFORMANCE is not set # CONFIG_PCIE_BUS_PEER2PEER is not set CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 CONFIG_HOTPLUG_PCI=y CONFIG_HOTPLUG_PCI_COMPAQ=y CONFIG_HOTPLUG_PCI_COMPAQ_NVRAM=y CONFIG_HOTPLUG_PCI_IBM=y CONFIG_HOTPLUG_PCI_ACPI=y CONFIG_HOTPLUG_PCI_ACPI_IBM=y CONFIG_HOTPLUG_PCI_CPCI=y CONFIG_HOTPLUG_PCI_CPCI_ZT5550=y CONFIG_HOTPLUG_PCI_CPCI_GENERIC=y CONFIG_HOTPLUG_PCI_SHPC=y # # PCI controller drivers # CONFIG_PCI_FTPCI100=y CONFIG_PCI_HOST_COMMON=y CONFIG_PCI_HOST_GENERIC=y CONFIG_PCIE_XILINX=y CONFIG_PCIE_MICROCHIP_HOST=y # # DesignWare PCI Core Support # CONFIG_PCIE_DW=y CONFIG_PCIE_DW_HOST=y CONFIG_PCIE_DW_EP=y CONFIG_PCIE_DW_PLAT=y CONFIG_PCIE_DW_PLAT_HOST=y CONFIG_PCIE_DW_PLAT_EP=y CONFIG_PCIE_INTEL_GW=y CONFIG_PCI_MESON=y # end of DesignWare PCI Core Support # # Mobiveil PCIe Core Support # # end of Mobiveil PCIe Core Support # # Cadence PCIe controllers support # CONFIG_PCIE_CADENCE=y CONFIG_PCIE_CADENCE_HOST=y CONFIG_PCIE_CADENCE_EP=y CONFIG_PCIE_CADENCE_PLAT=y CONFIG_PCIE_CADENCE_PLAT_HOST=y CONFIG_PCIE_CADENCE_PLAT_EP=y CONFIG_PCI_J721E=y CONFIG_PCI_J721E_HOST=y CONFIG_PCI_J721E_EP=y # end of Cadence PCIe controllers support # end of PCI controller drivers # # PCI Endpoint # CONFIG_PCI_ENDPOINT=y CONFIG_PCI_ENDPOINT_CONFIGFS=y CONFIG_PCI_EPF_TEST=y CONFIG_PCI_EPF_NTB=y CONFIG_PCI_EPF_VNTB=y # end of PCI Endpoint # # PCI switch controller drivers # CONFIG_PCI_SW_SWITCHTEC=y # end of PCI switch controller drivers CONFIG_CXL_BUS=y CONFIG_CXL_PCI=y CONFIG_CXL_MEM_RAW_COMMANDS=y CONFIG_CXL_ACPI=y CONFIG_CXL_MEM=y CONFIG_CXL_PORT=y CONFIG_CXL_SUSPEND=y CONFIG_PCCARD=y CONFIG_PCMCIA=y CONFIG_PCMCIA_LOAD_CIS=y CONFIG_CARDBUS=y # # PC-card bridges # CONFIG_YENTA=y CONFIG_YENTA_O2=y CONFIG_YENTA_RICOH=y CONFIG_YENTA_TI=y CONFIG_YENTA_ENE_TUNE=y CONFIG_YENTA_TOSHIBA=y CONFIG_PD6729=y CONFIG_I82092=y CONFIG_I82365=y CONFIG_TCIC=y CONFIG_PCMCIA_PROBE=y CONFIG_PCCARD_NONSTATIC=y CONFIG_RAPIDIO=y CONFIG_RAPIDIO_TSI721=y CONFIG_RAPIDIO_DISC_TIMEOUT=30 CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y CONFIG_RAPIDIO_DMA_ENGINE=y CONFIG_RAPIDIO_DEBUG=y CONFIG_RAPIDIO_ENUM_BASIC=y CONFIG_RAPIDIO_CHMAN=y CONFIG_RAPIDIO_MPORT_CDEV=y # # RapidIO Switch drivers # CONFIG_RAPIDIO_CPS_XX=y CONFIG_RAPIDIO_CPS_GEN2=y CONFIG_RAPIDIO_RXS_GEN3=y # end of RapidIO Switch drivers # # Generic Driver Options # CONFIG_AUXILIARY_BUS=y CONFIG_UEVENT_HELPER=y CONFIG_UEVENT_HELPER_PATH="" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # # Firmware loader # CONFIG_FW_LOADER=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_FW_LOADER_SYSFS=y CONFIG_EXTRA_FIRMWARE="" CONFIG_FW_LOADER_USER_HELPER=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_FW_LOADER_COMPRESS=y CONFIG_FW_LOADER_COMPRESS_XZ=y CONFIG_FW_LOADER_COMPRESS_ZSTD=y CONFIG_FW_CACHE=y CONFIG_FW_UPLOAD=y # end of Firmware loader CONFIG_WANT_DEV_COREDUMP=y CONFIG_ALLOW_DEV_COREDUMP=y CONFIG_DEV_COREDUMP=y CONFIG_DEBUG_DRIVER=y CONFIG_DEBUG_DEVRES=y CONFIG_DEBUG_TEST_DRIVER_REMOVE=y CONFIG_PM_QOS_KUNIT_TEST=y CONFIG_TEST_ASYNC_DRIVER_PROBE=m CONFIG_DRIVER_PE_KUNIT_TEST=y CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y CONFIG_REGMAP_SLIMBUS=y CONFIG_REGMAP_SPI=y CONFIG_REGMAP_SPMI=y CONFIG_REGMAP_W1=y CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_IRQ=y CONFIG_REGMAP_SOUNDWIRE=y CONFIG_REGMAP_SOUNDWIRE_MBQ=y CONFIG_REGMAP_SCCB=y CONFIG_REGMAP_I3C=y CONFIG_REGMAP_SPI_AVMM=y CONFIG_DMA_SHARED_BUFFER=y CONFIG_DMA_FENCE_TRACE=y # end of Generic Driver Options # # Bus devices # CONFIG_MOXTET=y CONFIG_MHI_BUS=y CONFIG_MHI_BUS_DEBUG=y CONFIG_MHI_BUS_PCI_GENERIC=y CONFIG_MHI_BUS_EP=y # end of Bus devices CONFIG_CONNECTOR=y CONFIG_PROC_EVENTS=y # # Firmware Drivers # # # ARM System Control and Management Interface Protocol # # end of ARM System Control and Management Interface Protocol CONFIG_EDD=y CONFIG_EDD_OFF=y CONFIG_FIRMWARE_MEMMAP=y CONFIG_DMIID=y CONFIG_DMI_SYSFS=y CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y CONFIG_ISCSI_IBFT_FIND=y CONFIG_ISCSI_IBFT=y CONFIG_FW_CFG_SYSFS=y CONFIG_FW_CFG_SYSFS_CMDLINE=y CONFIG_SYSFB=y CONFIG_SYSFB_SIMPLEFB=y CONFIG_CS_DSP=y CONFIG_GOOGLE_FIRMWARE=y CONFIG_GOOGLE_SMI=y CONFIG_GOOGLE_COREBOOT_TABLE=y CONFIG_GOOGLE_MEMCONSOLE=y CONFIG_GOOGLE_MEMCONSOLE_X86_LEGACY=y CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=y CONFIG_GOOGLE_VPD=y # # EFI (Extensible Firmware Interface) Support # CONFIG_EFI_ESRT=y CONFIG_EFI_VARS_PSTORE=y CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y CONFIG_EFI_RUNTIME_MAP=y CONFIG_EFI_FAKE_MEMMAP=y CONFIG_EFI_MAX_FAKE_MEM=8 CONFIG_EFI_DXE_MEM_ATTRIBUTES=y CONFIG_EFI_RUNTIME_WRAPPERS=y CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y CONFIG_EFI_BOOTLOADER_CONTROL=y CONFIG_EFI_CAPSULE_LOADER=y CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH=y CONFIG_EFI_TEST=y CONFIG_EFI_DEV_PATH_PARSER=y CONFIG_APPLE_PROPERTIES=y CONFIG_RESET_ATTACK_MITIGATION=y CONFIG_EFI_RCI2_TABLE=y CONFIG_EFI_DISABLE_PCI_DMA=y CONFIG_EFI_EARLYCON=y CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y CONFIG_EFI_DISABLE_RUNTIME=y CONFIG_EFI_COCO_SECRET=y CONFIG_EFI_EMBEDDED_FIRMWARE=y # end of EFI (Extensible Firmware Interface) Support CONFIG_UEFI_CPER=y CONFIG_UEFI_CPER_X86=y # # Tegra firmware driver # # end of Tegra firmware driver # end of Firmware Drivers CONFIG_GNSS=y CONFIG_GNSS_SERIAL=y CONFIG_GNSS_MTK_SERIAL=y CONFIG_GNSS_SIRF_SERIAL=y CONFIG_GNSS_UBX_SERIAL=y CONFIG_GNSS_USB=y CONFIG_MTD=y CONFIG_MTD_TESTS=m # # Partition parsers # CONFIG_MTD_AR7_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_OF_PARTS=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y CONFIG_MTD_REDBOOT_PARTS_READONLY=y # end of Partition parsers # # User Modules And Translation Layers # CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y # # Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. # CONFIG_FTL=y CONFIG_NFTL=y CONFIG_NFTL_RW=y CONFIG_INFTL=y CONFIG_RFD_FTL=y CONFIG_SSFDC=y CONFIG_SM_FTL=y CONFIG_MTD_OOPS=y CONFIG_MTD_PSTORE=y CONFIG_MTD_SWAP=y CONFIG_MTD_PARTITIONED_MASTER=y # # RAM/ROM/Flash chip drivers # CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y CONFIG_MTD_GEN_PROBE=y CONFIG_MTD_CFI_ADV_OPTIONS=y CONFIG_MTD_CFI_NOSWAP=y # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set CONFIG_MTD_CFI_GEOMETRY=y CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y CONFIG_MTD_MAP_BANK_WIDTH_8=y CONFIG_MTD_MAP_BANK_WIDTH_16=y CONFIG_MTD_MAP_BANK_WIDTH_32=y CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_I4=y CONFIG_MTD_CFI_I8=y CONFIG_MTD_OTP=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_STAA=y CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y CONFIG_MTD_ROM=y CONFIG_MTD_ABSENT=y # end of RAM/ROM/Flash chip drivers # # Mapping drivers for chip access # CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP_COMPAT=y CONFIG_MTD_PHYSMAP_START=0x8000000 CONFIG_MTD_PHYSMAP_LEN=0 CONFIG_MTD_PHYSMAP_BANKWIDTH=2 CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_VERSATILE=y CONFIG_MTD_PHYSMAP_GEMINI=y CONFIG_MTD_PHYSMAP_GPIO_ADDR=y CONFIG_MTD_SBC_GXX=y CONFIG_MTD_SCx200_DOCFLASH=y CONFIG_MTD_AMD76XROM=y CONFIG_MTD_ICHXROM=y CONFIG_MTD_ESB2ROM=y CONFIG_MTD_CK804XROM=y CONFIG_MTD_SCB2_FLASH=y CONFIG_MTD_NETtel=y CONFIG_MTD_L440GX=y CONFIG_MTD_PCI=y CONFIG_MTD_PCMCIA=y CONFIG_MTD_PCMCIA_ANONYMOUS=y CONFIG_MTD_INTEL_VR_NOR=y CONFIG_MTD_PLATRAM=y # end of Mapping drivers for chip access # # Self-contained MTD device drivers # CONFIG_MTD_PMC551=y CONFIG_MTD_PMC551_BUGFIX=y CONFIG_MTD_PMC551_DEBUG=y CONFIG_MTD_DATAFLASH=y CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y CONFIG_MTD_DATAFLASH_OTP=y CONFIG_MTD_MCHP23K256=y CONFIG_MTD_MCHP48L640=y CONFIG_MTD_SST25L=y CONFIG_MTD_SLRAM=y CONFIG_MTD_PHRAM=y CONFIG_MTD_MTDRAM=y CONFIG_MTDRAM_TOTAL_SIZE=4096 CONFIG_MTDRAM_ERASE_SIZE=128 CONFIG_MTD_BLOCK2MTD=y # # Disk-On-Chip Device Drivers # CONFIG_MTD_DOCG3=y CONFIG_BCH_CONST_M=14 CONFIG_BCH_CONST_T=4 # end of Self-contained MTD device drivers # # NAND # CONFIG_MTD_NAND_CORE=y CONFIG_MTD_ONENAND=y CONFIG_MTD_ONENAND_VERIFY_WRITE=y CONFIG_MTD_ONENAND_GENERIC=y CONFIG_MTD_ONENAND_OTP=y CONFIG_MTD_ONENAND_2X_PROGRAM=y CONFIG_MTD_RAW_NAND=y # # Raw/parallel NAND flash controllers # CONFIG_MTD_NAND_DENALI=y CONFIG_MTD_NAND_DENALI_PCI=y CONFIG_MTD_NAND_DENALI_DT=y CONFIG_MTD_NAND_CAFE=y CONFIG_MTD_NAND_CS553X=y CONFIG_MTD_NAND_MXIC=y CONFIG_MTD_NAND_GPIO=y CONFIG_MTD_NAND_PLATFORM=y CONFIG_MTD_NAND_CADENCE=y CONFIG_MTD_NAND_ARASAN=y CONFIG_MTD_NAND_INTEL_LGM=y # # Misc # CONFIG_MTD_SM_COMMON=y CONFIG_MTD_NAND_NANDSIM=y CONFIG_MTD_NAND_RICOH=y CONFIG_MTD_NAND_DISKONCHIP=y CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y CONFIG_MTD_SPI_NAND=y # # ECC engine support # CONFIG_MTD_NAND_ECC=y CONFIG_MTD_NAND_ECC_SW_HAMMING=y CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y CONFIG_MTD_NAND_ECC_SW_BCH=y CONFIG_MTD_NAND_ECC_MXIC=y # end of ECC engine support # end of NAND # # LPDDR & LPDDR2 PCM memory drivers # CONFIG_MTD_LPDDR=y CONFIG_MTD_QINFO_PROBE=y # end of LPDDR & LPDDR2 PCM memory drivers CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y # CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y # CONFIG_MTD_SPI_NOR_SWP_KEEP is not set CONFIG_MTD_UBI=y CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_GLUEBI=y CONFIG_MTD_UBI_BLOCK=y CONFIG_MTD_HYPERBUS=y CONFIG_DTC=y CONFIG_OF=y CONFIG_OF_UNITTEST=y CONFIG_OF_FLATTREE=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_PROMTREE=y CONFIG_OF_KOBJ=y CONFIG_OF_DYNAMIC=y CONFIG_OF_ADDRESS=y CONFIG_OF_IRQ=y CONFIG_OF_RESERVED_MEM=y CONFIG_OF_RESOLVE=y CONFIG_OF_OVERLAY=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_PARPORT=y CONFIG_PARPORT_PC=y CONFIG_PARPORT_SERIAL=y CONFIG_PARPORT_PC_FIFO=y CONFIG_PARPORT_PC_SUPERIO=y CONFIG_PARPORT_PC_PCMCIA=y CONFIG_PARPORT_AX88796=y CONFIG_PARPORT_1284=y CONFIG_PARPORT_NOT_PC=y CONFIG_PNP=y CONFIG_PNP_DEBUG_MESSAGES=y # # Protocols # CONFIG_ISAPNP=y CONFIG_PNPBIOS=y CONFIG_PNPBIOS_PROC_FS=y CONFIG_PNPACPI=y CONFIG_BLK_DEV=y CONFIG_BLK_DEV_NULL_BLK=y CONFIG_BLK_DEV_NULL_BLK_FAULT_INJECTION=y CONFIG_BLK_DEV_FD=y CONFIG_BLK_DEV_FD_RAWCMD=y CONFIG_CDROM=y CONFIG_PARIDE=y # # Parallel IDE high-level drivers # CONFIG_PARIDE_PD=y CONFIG_PARIDE_PCD=y CONFIG_PARIDE_PF=y CONFIG_PARIDE_PT=y CONFIG_PARIDE_PG=y # # Parallel IDE protocol modules # CONFIG_PARIDE_ATEN=y CONFIG_PARIDE_BPCK=y CONFIG_PARIDE_BPCK6=y CONFIG_PARIDE_COMM=y CONFIG_PARIDE_DSTR=y CONFIG_PARIDE_FIT2=y CONFIG_PARIDE_FIT3=y CONFIG_PARIDE_EPAT=y CONFIG_PARIDE_EPATC8=y CONFIG_PARIDE_EPIA=y CONFIG_PARIDE_FRIQ=y CONFIG_PARIDE_FRPW=y CONFIG_PARIDE_KBIC=y CONFIG_PARIDE_KTTI=y CONFIG_PARIDE_ON20=y CONFIG_PARIDE_ON26=y CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y CONFIG_ZRAM=y CONFIG_ZRAM_DEF_COMP_LZORLE=y # CONFIG_ZRAM_DEF_COMP_ZSTD is not set # CONFIG_ZRAM_DEF_COMP_LZ4 is not set # CONFIG_ZRAM_DEF_COMP_LZO is not set # CONFIG_ZRAM_DEF_COMP_LZ4HC is not set # CONFIG_ZRAM_DEF_COMP_842 is not set CONFIG_ZRAM_DEF_COMP="lzo-rle" CONFIG_ZRAM_WRITEBACK=y CONFIG_ZRAM_MEMORY_TRACKING=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 CONFIG_BLK_DEV_DRBD=y CONFIG_DRBD_FAULT_INJECTION=y CONFIG_BLK_DEV_NBD=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 CONFIG_CDROM_PKTCDVD=y CONFIG_CDROM_PKTCDVD_BUFFERS=8 CONFIG_CDROM_PKTCDVD_WCACHE=y CONFIG_ATA_OVER_ETH=y CONFIG_VIRTIO_BLK=y CONFIG_BLK_DEV_RBD=y CONFIG_BLK_DEV_UBLK=y CONFIG_BLK_DEV_RNBD=y CONFIG_BLK_DEV_RNBD_CLIENT=y CONFIG_BLK_DEV_RNBD_SERVER=y # # NVME Support # CONFIG_NVME_COMMON=y CONFIG_NVME_CORE=y CONFIG_BLK_DEV_NVME=y CONFIG_NVME_MULTIPATH=y CONFIG_NVME_VERBOSE_ERRORS=y CONFIG_NVME_HWMON=y CONFIG_NVME_FABRICS=y CONFIG_NVME_RDMA=y CONFIG_NVME_FC=y CONFIG_NVME_TCP=y CONFIG_NVME_AUTH=y CONFIG_NVME_TARGET=y CONFIG_NVME_TARGET_PASSTHRU=y CONFIG_NVME_TARGET_LOOP=y CONFIG_NVME_TARGET_RDMA=y CONFIG_NVME_TARGET_FC=y CONFIG_NVME_TARGET_FCLOOP=y CONFIG_NVME_TARGET_TCP=y CONFIG_NVME_TARGET_AUTH=y # end of NVME Support # # Misc devices # CONFIG_SENSORS_LIS3LV02D=y CONFIG_AD525X_DPOT=y CONFIG_AD525X_DPOT_I2C=y CONFIG_AD525X_DPOT_SPI=y CONFIG_DUMMY_IRQ=y CONFIG_IBM_ASM=y CONFIG_PHANTOM=y CONFIG_TIFM_CORE=y CONFIG_TIFM_7XX1=y CONFIG_ICS932S401=y CONFIG_ENCLOSURE_SERVICES=y CONFIG_CS5535_MFGPT=y CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7 CONFIG_CS5535_CLOCK_EVENT_SRC=y CONFIG_HI6421V600_IRQ=y CONFIG_HP_ILO=y CONFIG_APDS9802ALS=y CONFIG_ISL29003=y CONFIG_ISL29020=y CONFIG_SENSORS_TSL2550=y CONFIG_SENSORS_BH1770=y CONFIG_SENSORS_APDS990X=y CONFIG_HMC6352=y CONFIG_DS1682=y CONFIG_VMWARE_BALLOON=y CONFIG_PCH_PHUB=y CONFIG_LATTICE_ECP3_CONFIG=y CONFIG_SRAM=y CONFIG_DW_XDATA_PCIE=y CONFIG_PCI_ENDPOINT_TEST=y CONFIG_XILINX_SDFEC=y CONFIG_MISC_RTSX=y CONFIG_HISI_HIKEY_USB=y CONFIG_OPEN_DICE=y CONFIG_VCPU_STALL_DETECTOR=y CONFIG_C2PORT=y CONFIG_C2PORT_DURAMAR_2150=y # # EEPROM support # CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT25=y CONFIG_EEPROM_LEGACY=y CONFIG_EEPROM_MAX6875=y CONFIG_EEPROM_93CX6=y CONFIG_EEPROM_93XX46=y CONFIG_EEPROM_IDT_89HPESX=y CONFIG_EEPROM_EE1004=y # end of EEPROM support CONFIG_CB710_CORE=y CONFIG_CB710_DEBUG=y CONFIG_CB710_DEBUG_ASSUMPTIONS=y # # Texas Instruments shared transport line discipline # CONFIG_TI_ST=y # end of Texas Instruments shared transport line discipline CONFIG_SENSORS_LIS3_I2C=y CONFIG_ALTERA_STAPL=y CONFIG_INTEL_MEI=y CONFIG_INTEL_MEI_ME=y CONFIG_INTEL_MEI_TXE=y CONFIG_INTEL_MEI_GSC=y CONFIG_INTEL_MEI_HDCP=y CONFIG_INTEL_MEI_PXP=y CONFIG_VMWARE_VMCI=y CONFIG_ECHO=y CONFIG_BCM_VK=y CONFIG_BCM_VK_TTY=y CONFIG_MISC_ALCOR_PCI=y CONFIG_MISC_RTSX_PCI=y CONFIG_MISC_RTSX_USB=y CONFIG_HABANA_AI=y CONFIG_UACCE=y CONFIG_PVPANIC=y CONFIG_PVPANIC_MMIO=y CONFIG_PVPANIC_PCI=y CONFIG_GP_PCI1XXXX=y # end of Misc devices # # SCSI device support # CONFIG_SCSI_MOD=y CONFIG_RAID_ATTRS=y CONFIG_SCSI_COMMON=y CONFIG_SCSI=y CONFIG_SCSI_DMA=y CONFIG_SCSI_NETLINK=y CONFIG_SCSI_PROC_FS=y # # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y CONFIG_BLK_DEV_SR=y CONFIG_CHR_DEV_SG=y CONFIG_BLK_DEV_BSG=y CONFIG_CHR_DEV_SCH=y CONFIG_SCSI_ENCLOSURE=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y # # SCSI Transports # CONFIG_SCSI_SPI_ATTRS=y CONFIG_SCSI_FC_ATTRS=y CONFIG_SCSI_ISCSI_ATTRS=y CONFIG_SCSI_SAS_ATTRS=y CONFIG_SCSI_SAS_LIBSAS=y CONFIG_SCSI_SAS_ATA=y CONFIG_SCSI_SAS_HOST_SMP=y CONFIG_SCSI_SRP_ATTRS=y # end of SCSI Transports CONFIG_SCSI_LOWLEVEL=y CONFIG_ISCSI_TCP=y CONFIG_ISCSI_BOOT_SYSFS=y CONFIG_SCSI_CXGB3_ISCSI=y CONFIG_SCSI_CXGB4_ISCSI=y CONFIG_SCSI_BNX2_ISCSI=y CONFIG_SCSI_BNX2X_FCOE=y CONFIG_BE2ISCSI=y CONFIG_BLK_DEV_3W_XXXX_RAID=y CONFIG_SCSI_HPSA=y CONFIG_SCSI_3W_9XXX=y CONFIG_SCSI_3W_SAS=y CONFIG_SCSI_ACARD=y CONFIG_SCSI_AHA152X=y CONFIG_SCSI_AHA1542=y CONFIG_SCSI_AHA1740=y CONFIG_SCSI_AACRAID=y CONFIG_SCSI_AIC7XXX=y CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 CONFIG_AIC7XXX_RESET_DELAY_MS=5000 CONFIG_AIC7XXX_DEBUG_ENABLE=y CONFIG_AIC7XXX_DEBUG_MASK=0 CONFIG_AIC7XXX_REG_PRETTY_PRINT=y CONFIG_SCSI_AIC79XX=y CONFIG_AIC79XX_CMDS_PER_DEVICE=32 CONFIG_AIC79XX_RESET_DELAY_MS=5000 CONFIG_AIC79XX_DEBUG_ENABLE=y CONFIG_AIC79XX_DEBUG_MASK=0 CONFIG_AIC79XX_REG_PRETTY_PRINT=y CONFIG_SCSI_AIC94XX=y CONFIG_AIC94XX_DEBUG=y CONFIG_SCSI_MVSAS=y CONFIG_SCSI_MVSAS_DEBUG=y CONFIG_SCSI_MVSAS_TASKLET=y CONFIG_SCSI_MVUMI=y CONFIG_SCSI_ADVANSYS=y CONFIG_SCSI_ARCMSR=y CONFIG_SCSI_ESAS2R=y CONFIG_MEGARAID_NEWGEN=y CONFIG_MEGARAID_MM=y CONFIG_MEGARAID_MAILBOX=y CONFIG_MEGARAID_LEGACY=y CONFIG_MEGARAID_SAS=y CONFIG_SCSI_MPT3SAS=y CONFIG_SCSI_MPT2SAS_MAX_SGE=128 CONFIG_SCSI_MPT3SAS_MAX_SGE=128 CONFIG_SCSI_MPT2SAS=y CONFIG_SCSI_MPI3MR=y CONFIG_SCSI_SMARTPQI=y CONFIG_SCSI_HPTIOP=y CONFIG_SCSI_BUSLOGIC=y CONFIG_SCSI_FLASHPOINT=y CONFIG_SCSI_MYRB=y CONFIG_SCSI_MYRS=y CONFIG_VMWARE_PVSCSI=y CONFIG_HYPERV_STORAGE=y CONFIG_LIBFC=y CONFIG_LIBFCOE=y CONFIG_FCOE=y CONFIG_FCOE_FNIC=y CONFIG_SCSI_SNIC=y CONFIG_SCSI_SNIC_DEBUG_FS=y CONFIG_SCSI_DMX3191D=y CONFIG_SCSI_FDOMAIN=y CONFIG_SCSI_FDOMAIN_PCI=y CONFIG_SCSI_FDOMAIN_ISA=y CONFIG_SCSI_ISCI=y CONFIG_SCSI_GENERIC_NCR5380=y CONFIG_SCSI_IPS=y CONFIG_SCSI_INITIO=y CONFIG_SCSI_INIA100=y CONFIG_SCSI_PPA=y CONFIG_SCSI_IMM=y CONFIG_SCSI_IZIP_EPP16=y CONFIG_SCSI_IZIP_SLOW_CTR=y CONFIG_SCSI_STEX=y CONFIG_SCSI_SYM53C8XX_2=y CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 CONFIG_SCSI_SYM53C8XX_MMIO=y CONFIG_SCSI_IPR=y CONFIG_SCSI_IPR_TRACE=y CONFIG_SCSI_IPR_DUMP=y CONFIG_SCSI_QLOGIC_FAS=y CONFIG_SCSI_QLOGIC_1280=y CONFIG_SCSI_QLA_FC=y CONFIG_TCM_QLA2XXX=y CONFIG_TCM_QLA2XXX_DEBUG=y CONFIG_SCSI_QLA_ISCSI=y CONFIG_QEDI=y CONFIG_QEDF=y CONFIG_SCSI_LPFC=y CONFIG_SCSI_LPFC_DEBUG_FS=y CONFIG_SCSI_EFCT=y CONFIG_SCSI_SIM710=y CONFIG_SCSI_DC395x=y CONFIG_SCSI_AM53C974=y CONFIG_SCSI_NSP32=y CONFIG_SCSI_WD719X=y CONFIG_SCSI_DEBUG=y CONFIG_SCSI_PMCRAID=y CONFIG_SCSI_PM8001=y CONFIG_SCSI_BFA_FC=y CONFIG_SCSI_VIRTIO=y CONFIG_SCSI_CHELSIO_FCOE=y CONFIG_SCSI_LOWLEVEL_PCMCIA=y CONFIG_PCMCIA_AHA152X=m CONFIG_PCMCIA_FDOMAIN=m CONFIG_PCMCIA_NINJA_SCSI=m CONFIG_PCMCIA_QLOGIC=m CONFIG_PCMCIA_SYM53C500=m CONFIG_SCSI_DH=y CONFIG_SCSI_DH_RDAC=y CONFIG_SCSI_DH_HP_SW=y CONFIG_SCSI_DH_EMC=y CONFIG_SCSI_DH_ALUA=y # end of SCSI device support CONFIG_ATA=y CONFIG_SATA_HOST=y CONFIG_PATA_TIMINGS=y CONFIG_ATA_VERBOSE_ERROR=y CONFIG_ATA_FORCE=y CONFIG_ATA_ACPI=y CONFIG_SATA_ZPODD=y CONFIG_SATA_PMP=y # # Controllers with non-SFF native interface # CONFIG_SATA_AHCI=y CONFIG_SATA_MOBILE_LPM_POLICY=0 CONFIG_SATA_AHCI_PLATFORM=y CONFIG_AHCI_DWC=y CONFIG_AHCI_CEVA=y CONFIG_AHCI_QORIQ=y CONFIG_SATA_INIC162X=y CONFIG_SATA_ACARD_AHCI=y CONFIG_SATA_SIL24=y CONFIG_ATA_SFF=y # # SFF controllers with custom DMA interface # CONFIG_PDC_ADMA=y CONFIG_SATA_QSTOR=y CONFIG_SATA_SX4=y CONFIG_ATA_BMDMA=y # # SATA SFF controllers with BMDMA # CONFIG_ATA_PIIX=y CONFIG_SATA_DWC=y CONFIG_SATA_DWC_OLD_DMA=y CONFIG_SATA_MV=y CONFIG_SATA_NV=y CONFIG_SATA_PROMISE=y CONFIG_SATA_SIL=y CONFIG_SATA_SIS=y CONFIG_SATA_SVW=y CONFIG_SATA_ULI=y CONFIG_SATA_VIA=y CONFIG_SATA_VITESSE=y # # PATA SFF controllers with BMDMA # CONFIG_PATA_ALI=y CONFIG_PATA_AMD=y CONFIG_PATA_ARTOP=y CONFIG_PATA_ATIIXP=y CONFIG_PATA_ATP867X=y CONFIG_PATA_CMD64X=y CONFIG_PATA_CS5520=y CONFIG_PATA_CS5530=y CONFIG_PATA_CS5535=y CONFIG_PATA_CS5536=y CONFIG_PATA_CYPRESS=y CONFIG_PATA_EFAR=y CONFIG_PATA_HPT366=y CONFIG_PATA_HPT37X=y CONFIG_PATA_HPT3X2N=y CONFIG_PATA_HPT3X3=y CONFIG_PATA_HPT3X3_DMA=y CONFIG_PATA_IT8213=y CONFIG_PATA_IT821X=y CONFIG_PATA_JMICRON=y CONFIG_PATA_MARVELL=y CONFIG_PATA_NETCELL=y CONFIG_PATA_NINJA32=y CONFIG_PATA_NS87415=y CONFIG_PATA_OLDPIIX=y CONFIG_PATA_OPTIDMA=y CONFIG_PATA_PDC2027X=y CONFIG_PATA_PDC_OLD=y CONFIG_PATA_RADISYS=y CONFIG_PATA_RDC=y CONFIG_PATA_SC1200=y CONFIG_PATA_SCH=y CONFIG_PATA_SERVERWORKS=y CONFIG_PATA_SIL680=y CONFIG_PATA_SIS=y CONFIG_PATA_TOSHIBA=y CONFIG_PATA_TRIFLEX=y CONFIG_PATA_VIA=y CONFIG_PATA_WINBOND=y # # PIO-only SFF controllers # CONFIG_PATA_CMD640_PCI=y CONFIG_PATA_ISAPNP=y CONFIG_PATA_MPIIX=y CONFIG_PATA_NS87410=y CONFIG_PATA_OPTI=y CONFIG_PATA_PCMCIA=y CONFIG_PATA_PLATFORM=y CONFIG_PATA_OF_PLATFORM=y CONFIG_PATA_QDI=y CONFIG_PATA_RZ1000=y CONFIG_PATA_WINBOND_VLB=y # # Generic fallback / legacy drivers # CONFIG_PATA_ACPI=y CONFIG_ATA_GENERIC=y CONFIG_PATA_LEGACY=y CONFIG_MD=y CONFIG_BLK_DEV_MD=y CONFIG_MD_AUTODETECT=y CONFIG_MD_LINEAR=y CONFIG_MD_RAID0=y CONFIG_MD_RAID1=y CONFIG_MD_RAID10=y CONFIG_MD_RAID456=y CONFIG_MD_MULTIPATH=y CONFIG_MD_FAULTY=y CONFIG_MD_CLUSTER=y CONFIG_BCACHE=y CONFIG_BCACHE_DEBUG=y CONFIG_BCACHE_CLOSURES_DEBUG=y CONFIG_BCACHE_ASYNC_REGISTRATION=y CONFIG_BLK_DEV_DM_BUILTIN=y CONFIG_BLK_DEV_DM=y CONFIG_DM_DEBUG=y CONFIG_DM_BUFIO=y CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING=y CONFIG_DM_DEBUG_BLOCK_STACK_TRACING=y CONFIG_DM_BIO_PRISON=y CONFIG_DM_PERSISTENT_DATA=y CONFIG_DM_UNSTRIPED=y CONFIG_DM_CRYPT=y CONFIG_DM_SNAPSHOT=y CONFIG_DM_THIN_PROVISIONING=y CONFIG_DM_CACHE=y CONFIG_DM_CACHE_SMQ=y CONFIG_DM_WRITECACHE=y CONFIG_DM_ERA=y CONFIG_DM_CLONE=y CONFIG_DM_MIRROR=y CONFIG_DM_LOG_USERSPACE=y CONFIG_DM_RAID=y CONFIG_DM_ZERO=y CONFIG_DM_MULTIPATH=y CONFIG_DM_MULTIPATH_QL=y CONFIG_DM_MULTIPATH_ST=y CONFIG_DM_MULTIPATH_HST=y CONFIG_DM_MULTIPATH_IOA=y CONFIG_DM_DELAY=y CONFIG_DM_DUST=y CONFIG_DM_INIT=y CONFIG_DM_UEVENT=y CONFIG_DM_FLAKEY=y CONFIG_DM_VERITY=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_FEC=y CONFIG_DM_SWITCH=y CONFIG_DM_LOG_WRITES=y CONFIG_DM_INTEGRITY=y CONFIG_DM_ZONED=y CONFIG_DM_AUDIT=y CONFIG_TARGET_CORE=y CONFIG_TCM_IBLOCK=y CONFIG_TCM_FILEIO=y CONFIG_TCM_PSCSI=y CONFIG_TCM_USER2=y CONFIG_LOOPBACK_TARGET=y CONFIG_TCM_FC=y CONFIG_ISCSI_TARGET=y CONFIG_ISCSI_TARGET_CXGB4=y CONFIG_SBP_TARGET=y CONFIG_FUSION=y CONFIG_FUSION_SPI=y CONFIG_FUSION_FC=y CONFIG_FUSION_SAS=y CONFIG_FUSION_MAX_SGE=128 CONFIG_FUSION_CTL=y CONFIG_FUSION_LAN=y CONFIG_FUSION_LOGGING=y # # IEEE 1394 (FireWire) support # CONFIG_FIREWIRE=y CONFIG_FIREWIRE_OHCI=y CONFIG_FIREWIRE_SBP2=y CONFIG_FIREWIRE_NET=y CONFIG_FIREWIRE_NOSY=y # end of IEEE 1394 (FireWire) support CONFIG_MACINTOSH_DRIVERS=y CONFIG_MAC_EMUMOUSEBTN=y CONFIG_NETDEVICES=y CONFIG_MII=y CONFIG_NET_CORE=y CONFIG_BONDING=y CONFIG_DUMMY=y CONFIG_WIREGUARD=y CONFIG_WIREGUARD_DEBUG=y CONFIG_EQUALIZER=y CONFIG_NET_FC=y CONFIG_IFB=y CONFIG_NET_TEAM=y CONFIG_NET_TEAM_MODE_BROADCAST=y CONFIG_NET_TEAM_MODE_ROUNDROBIN=y CONFIG_NET_TEAM_MODE_RANDOM=y CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=y CONFIG_NET_TEAM_MODE_LOADBALANCE=y CONFIG_MACVLAN=y CONFIG_MACVTAP=y CONFIG_IPVLAN_L3S=y CONFIG_IPVLAN=y CONFIG_IPVTAP=y CONFIG_VXLAN=y CONFIG_GENEVE=y CONFIG_BAREUDP=y CONFIG_GTP=y CONFIG_AMT=y CONFIG_MACSEC=y CONFIG_NETCONSOLE=y CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_NETPOLL=y CONFIG_NET_POLL_CONTROLLER=y CONFIG_NTB_NETDEV=y CONFIG_RIONET=y CONFIG_RIONET_TX_SIZE=128 CONFIG_RIONET_RX_SIZE=128 CONFIG_TUN=y CONFIG_TAP=y CONFIG_TUN_VNET_CROSS_LE=y CONFIG_VETH=y CONFIG_VIRTIO_NET=y CONFIG_NLMON=y CONFIG_NET_VRF=y CONFIG_VSOCKMON=y CONFIG_MHI_NET=y CONFIG_SUNGEM_PHY=y CONFIG_ARCNET=y CONFIG_ARCNET_1201=y CONFIG_ARCNET_1051=y CONFIG_ARCNET_RAW=y CONFIG_ARCNET_CAP=y CONFIG_ARCNET_COM90xx=y CONFIG_ARCNET_COM90xxIO=y CONFIG_ARCNET_RIM_I=y CONFIG_ARCNET_COM20020=y CONFIG_ARCNET_COM20020_ISA=y CONFIG_ARCNET_COM20020_PCI=y CONFIG_ARCNET_COM20020_CS=y CONFIG_ATM_DRIVERS=y CONFIG_ATM_DUMMY=y CONFIG_ATM_TCP=y CONFIG_ATM_LANAI=y CONFIG_ATM_ENI=y CONFIG_ATM_ENI_DEBUG=y CONFIG_ATM_ENI_TUNE_BURST=y CONFIG_ATM_ENI_BURST_TX_16W=y CONFIG_ATM_ENI_BURST_TX_8W=y CONFIG_ATM_ENI_BURST_TX_4W=y CONFIG_ATM_ENI_BURST_TX_2W=y CONFIG_ATM_ENI_BURST_RX_16W=y CONFIG_ATM_ENI_BURST_RX_8W=y CONFIG_ATM_ENI_BURST_RX_4W=y CONFIG_ATM_ENI_BURST_RX_2W=y CONFIG_ATM_NICSTAR=y CONFIG_ATM_NICSTAR_USE_SUNI=y CONFIG_ATM_NICSTAR_USE_IDT77105=y CONFIG_ATM_IDT77252=y CONFIG_ATM_IDT77252_DEBUG=y CONFIG_ATM_IDT77252_RCV_ALL=y CONFIG_ATM_IDT77252_USE_SUNI=y CONFIG_ATM_IA=y CONFIG_ATM_IA_DEBUG=y CONFIG_ATM_FORE200E=y CONFIG_ATM_FORE200E_USE_TASKLET=y CONFIG_ATM_FORE200E_TX_RETRY=16 CONFIG_ATM_FORE200E_DEBUG=0 CONFIG_ATM_HE=y CONFIG_ATM_HE_USE_SUNI=y CONFIG_ATM_SOLOS=y CONFIG_CAIF_DRIVERS=y CONFIG_CAIF_TTY=y CONFIG_CAIF_VIRTIO=y # # Distributed Switch Architecture drivers # CONFIG_B53=y CONFIG_B53_SPI_DRIVER=y CONFIG_B53_MDIO_DRIVER=y CONFIG_B53_MMAP_DRIVER=y CONFIG_B53_SRAB_DRIVER=y CONFIG_B53_SERDES=y CONFIG_NET_DSA_BCM_SF2=y CONFIG_NET_DSA_LOOP=y CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=y CONFIG_NET_DSA_LANTIQ_GSWIP=y CONFIG_NET_DSA_MT7530=y CONFIG_NET_DSA_MV88E6060=y CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=y CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=y CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=y CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=y CONFIG_NET_DSA_MV88E6XXX=y CONFIG_NET_DSA_MV88E6XXX_PTP=y CONFIG_NET_DSA_MSCC_SEVILLE=y CONFIG_NET_DSA_AR9331=y CONFIG_NET_DSA_QCA8K=y CONFIG_NET_DSA_SJA1105=y CONFIG_NET_DSA_SJA1105_PTP=y CONFIG_NET_DSA_SJA1105_TAS=y CONFIG_NET_DSA_SJA1105_VL=y CONFIG_NET_DSA_XRS700X=y CONFIG_NET_DSA_XRS700X_I2C=y CONFIG_NET_DSA_XRS700X_MDIO=y CONFIG_NET_DSA_REALTEK=y CONFIG_NET_DSA_REALTEK_MDIO=y CONFIG_NET_DSA_REALTEK_SMI=y CONFIG_NET_DSA_REALTEK_RTL8365MB=y CONFIG_NET_DSA_REALTEK_RTL8366RB=y CONFIG_NET_DSA_SMSC_LAN9303=y CONFIG_NET_DSA_SMSC_LAN9303_I2C=y CONFIG_NET_DSA_SMSC_LAN9303_MDIO=y CONFIG_NET_DSA_VITESSE_VSC73XX=y CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=y CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=y # end of Distributed Switch Architecture drivers CONFIG_ETHERNET=y CONFIG_MDIO=y CONFIG_NET_VENDOR_3COM=y CONFIG_EL3=y CONFIG_3C515=y CONFIG_PCMCIA_3C574=y CONFIG_PCMCIA_3C589=y CONFIG_VORTEX=y CONFIG_TYPHOON=y CONFIG_NET_VENDOR_ADAPTEC=y CONFIG_ADAPTEC_STARFIRE=y CONFIG_NET_VENDOR_AGERE=y CONFIG_ET131X=y CONFIG_NET_VENDOR_ALACRITECH=y CONFIG_SLICOSS=y CONFIG_NET_VENDOR_ALTEON=y CONFIG_ACENIC=y CONFIG_ACENIC_OMIT_TIGON_I=y CONFIG_ALTERA_TSE=y CONFIG_NET_VENDOR_AMAZON=y CONFIG_ENA_ETHERNET=y CONFIG_NET_VENDOR_AMD=y CONFIG_AMD8111_ETH=y CONFIG_LANCE=y CONFIG_PCNET32=y CONFIG_PCMCIA_NMCLAN=y CONFIG_AMD_XGBE=y CONFIG_AMD_XGBE_DCB=y CONFIG_AMD_XGBE_HAVE_ECC=y CONFIG_NET_VENDOR_AQUANTIA=y CONFIG_AQTION=y CONFIG_NET_VENDOR_ARC=y CONFIG_NET_VENDOR_ASIX=y CONFIG_SPI_AX88796C=y CONFIG_SPI_AX88796C_COMPRESSION=y CONFIG_NET_VENDOR_ATHEROS=y CONFIG_ATL2=y CONFIG_ATL1=y CONFIG_ATL1E=y CONFIG_ATL1C=y CONFIG_ALX=y CONFIG_CX_ECAT=y CONFIG_NET_VENDOR_BROADCOM=y CONFIG_B44=y CONFIG_B44_PCI_AUTOSELECT=y CONFIG_B44_PCICORE_AUTOSELECT=y CONFIG_B44_PCI=y CONFIG_BCMGENET=y CONFIG_BNX2=y CONFIG_CNIC=y CONFIG_TIGON3=y CONFIG_TIGON3_HWMON=y CONFIG_BNX2X=y CONFIG_BNX2X_SRIOV=y CONFIG_SYSTEMPORT=y CONFIG_BNXT=y CONFIG_BNXT_SRIOV=y CONFIG_BNXT_FLOWER_OFFLOAD=y CONFIG_BNXT_DCB=y CONFIG_BNXT_HWMON=y CONFIG_NET_VENDOR_CADENCE=y CONFIG_MACB=y CONFIG_MACB_USE_HWSTAMP=y CONFIG_MACB_PCI=y CONFIG_NET_VENDOR_CAVIUM=y CONFIG_NET_VENDOR_CHELSIO=y CONFIG_CHELSIO_T1=y CONFIG_CHELSIO_T1_1G=y CONFIG_CHELSIO_T3=y CONFIG_CHELSIO_T4=y CONFIG_CHELSIO_T4_DCB=y CONFIG_CHELSIO_T4_FCOE=y CONFIG_CHELSIO_T4VF=y CONFIG_CHELSIO_LIB=y CONFIG_CHELSIO_INLINE_CRYPTO=y CONFIG_CRYPTO_DEV_CHELSIO_TLS=y CONFIG_CHELSIO_IPSEC_INLINE=y CONFIG_CHELSIO_TLS_DEVICE=y CONFIG_NET_VENDOR_CIRRUS=y # CONFIG_CS89x0_ISA is not set CONFIG_NET_VENDOR_CISCO=y CONFIG_ENIC=y CONFIG_NET_VENDOR_CORTINA=y CONFIG_GEMINI_ETHERNET=y CONFIG_NET_VENDOR_DAVICOM=y CONFIG_DM9051=y CONFIG_DNET=y CONFIG_NET_VENDOR_DEC=y CONFIG_NET_TULIP=y CONFIG_DE2104X=y CONFIG_DE2104X_DSL=0 CONFIG_TULIP=y CONFIG_TULIP_MWI=y CONFIG_TULIP_MMIO=y CONFIG_TULIP_NAPI=y CONFIG_TULIP_NAPI_HW_MITIGATION=y CONFIG_WINBOND_840=y CONFIG_DM9102=y CONFIG_ULI526X=y CONFIG_PCMCIA_XIRCOM=y CONFIG_NET_VENDOR_DLINK=y CONFIG_DL2K=y CONFIG_SUNDANCE=y CONFIG_SUNDANCE_MMIO=y CONFIG_NET_VENDOR_EMULEX=y CONFIG_BE2NET=y CONFIG_BE2NET_HWMON=y CONFIG_BE2NET_BE2=y CONFIG_BE2NET_BE3=y CONFIG_BE2NET_LANCER=y CONFIG_BE2NET_SKYHAWK=y CONFIG_NET_VENDOR_ENGLEDER=y CONFIG_TSNEP=y CONFIG_TSNEP_SELFTESTS=y CONFIG_NET_VENDOR_EZCHIP=y CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=y CONFIG_NET_VENDOR_FUJITSU=y CONFIG_PCMCIA_FMVJ18X=y CONFIG_NET_VENDOR_FUNGIBLE=y CONFIG_FUN_CORE=y CONFIG_FUN_ETH=y CONFIG_NET_VENDOR_GOOGLE=y CONFIG_GVE=y CONFIG_NET_VENDOR_HUAWEI=y CONFIG_HINIC=y CONFIG_NET_VENDOR_I825XX=y CONFIG_NET_VENDOR_INTEL=y CONFIG_E100=y CONFIG_E1000=y CONFIG_E1000E=y CONFIG_E1000E_HWTS=y CONFIG_IGB=y CONFIG_IGB_HWMON=y CONFIG_IGBVF=y CONFIG_IXGB=y CONFIG_IXGBE=y CONFIG_IXGBE_HWMON=y CONFIG_IXGBE_DCB=y CONFIG_IXGBE_IPSEC=y CONFIG_IXGBEVF=y CONFIG_IXGBEVF_IPSEC=y CONFIG_I40E=y CONFIG_I40E_DCB=y CONFIG_IAVF=y CONFIG_I40EVF=y CONFIG_ICE=y CONFIG_ICE_SWITCHDEV=y CONFIG_ICE_HWTS=y CONFIG_FM10K=y CONFIG_IGC=y CONFIG_NET_VENDOR_WANGXUN=y CONFIG_NGBE=y CONFIG_TXGBE=y CONFIG_JME=y CONFIG_NET_VENDOR_ADI=y CONFIG_ADIN1110=y CONFIG_NET_VENDOR_LITEX=y CONFIG_LITEX_LITEETH=y CONFIG_NET_VENDOR_MARVELL=y CONFIG_MVMDIO=y CONFIG_SKGE=y CONFIG_SKGE_DEBUG=y CONFIG_SKGE_GENESIS=y CONFIG_SKY2=y CONFIG_SKY2_DEBUG=y CONFIG_PRESTERA=y CONFIG_PRESTERA_PCI=y CONFIG_NET_VENDOR_MELLANOX=y CONFIG_MLX4_EN=y CONFIG_MLX4_EN_DCB=y CONFIG_MLX4_CORE=y CONFIG_MLX4_DEBUG=y CONFIG_MLX4_CORE_GEN2=y CONFIG_MLX5_CORE=y CONFIG_MLX5_FPGA=y CONFIG_MLX5_CORE_EN=y CONFIG_MLX5_EN_ARFS=y CONFIG_MLX5_EN_RXNFC=y CONFIG_MLX5_MPFS=y CONFIG_MLX5_ESWITCH=y CONFIG_MLX5_BRIDGE=y CONFIG_MLX5_CLS_ACT=y CONFIG_MLX5_TC_CT=y CONFIG_MLX5_TC_SAMPLE=y CONFIG_MLX5_CORE_EN_DCB=y CONFIG_MLX5_CORE_IPOIB=y CONFIG_MLX5_EN_MACSEC=y CONFIG_MLX5_EN_IPSEC=y CONFIG_MLX5_EN_TLS=y CONFIG_MLX5_SW_STEERING=y CONFIG_MLX5_SF=y CONFIG_MLX5_SF_MANAGER=y CONFIG_MLXSW_CORE=y CONFIG_MLXSW_CORE_HWMON=y CONFIG_MLXSW_CORE_THERMAL=y CONFIG_MLXSW_PCI=y CONFIG_MLXSW_I2C=y CONFIG_MLXSW_SPECTRUM=y CONFIG_MLXSW_SPECTRUM_DCB=y CONFIG_MLXSW_MINIMAL=y CONFIG_MLXFW=y CONFIG_NET_VENDOR_MICREL=y CONFIG_KS8842=y CONFIG_KS8851=y CONFIG_KS8851_MLL=y CONFIG_KSZ884X_PCI=y CONFIG_NET_VENDOR_MICROCHIP=y CONFIG_ENC28J60=y CONFIG_ENC28J60_WRITEVERIFY=y CONFIG_ENCX24J600=y CONFIG_LAN743X=y CONFIG_LAN966X_SWITCH=y CONFIG_NET_VENDOR_MICROSEMI=y CONFIG_MSCC_OCELOT_SWITCH_LIB=y CONFIG_MSCC_OCELOT_SWITCH=y CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y CONFIG_MYRI10GE=y CONFIG_FEALNX=y CONFIG_NET_VENDOR_NI=y CONFIG_NI_XGE_MANAGEMENT_ENET=y CONFIG_NET_VENDOR_NATSEMI=y CONFIG_NATSEMI=y CONFIG_NS83820=y CONFIG_NET_VENDOR_NETERION=y CONFIG_S2IO=y CONFIG_NET_VENDOR_NETRONOME=y CONFIG_NFP=y CONFIG_NFP_APP_FLOWER=y CONFIG_NFP_APP_ABM_NIC=y CONFIG_NFP_DEBUG=y CONFIG_NET_VENDOR_8390=y CONFIG_PCMCIA_AXNET=y CONFIG_NE2000=y CONFIG_NE2K_PCI=y CONFIG_PCMCIA_PCNET=y CONFIG_ULTRA=y CONFIG_WD80x3=y CONFIG_NET_VENDOR_NVIDIA=y CONFIG_FORCEDETH=y CONFIG_NET_VENDOR_OKI=y CONFIG_PCH_GBE=y CONFIG_ETHOC=y CONFIG_NET_VENDOR_PACKET_ENGINES=y CONFIG_HAMACHI=y CONFIG_YELLOWFIN=y CONFIG_NET_VENDOR_PENSANDO=y CONFIG_NET_VENDOR_QLOGIC=y CONFIG_QLA3XXX=y CONFIG_QLCNIC=y CONFIG_QLCNIC_SRIOV=y CONFIG_QLCNIC_DCB=y CONFIG_QLCNIC_HWMON=y CONFIG_NETXEN_NIC=y CONFIG_QED=y CONFIG_QED_LL2=y CONFIG_QED_SRIOV=y CONFIG_QEDE=y CONFIG_QED_ISCSI=y CONFIG_QED_FCOE=y CONFIG_QED_OOO=y CONFIG_NET_VENDOR_BROCADE=y CONFIG_BNA=y CONFIG_NET_VENDOR_QUALCOMM=y CONFIG_QCA7000=y CONFIG_QCA7000_SPI=y CONFIG_QCA7000_UART=y CONFIG_QCOM_EMAC=y CONFIG_RMNET=y CONFIG_NET_VENDOR_RDC=y CONFIG_R6040=y CONFIG_NET_VENDOR_REALTEK=y CONFIG_ATP=y CONFIG_8139CP=y CONFIG_8139TOO=y CONFIG_8139TOO_PIO=y CONFIG_8139TOO_TUNE_TWISTER=y CONFIG_8139TOO_8129=y CONFIG_8139_OLD_RX_RESET=y CONFIG_R8169=y CONFIG_NET_VENDOR_RENESAS=y CONFIG_NET_VENDOR_ROCKER=y CONFIG_ROCKER=y CONFIG_NET_VENDOR_SAMSUNG=y CONFIG_SXGBE_ETH=y CONFIG_NET_VENDOR_SEEQ=y CONFIG_NET_VENDOR_SILAN=y CONFIG_SC92031=y CONFIG_NET_VENDOR_SIS=y CONFIG_SIS900=y CONFIG_SIS190=y CONFIG_NET_VENDOR_SOLARFLARE=y CONFIG_SFC=y CONFIG_SFC_MTD=y CONFIG_SFC_MCDI_MON=y CONFIG_SFC_SRIOV=y CONFIG_SFC_MCDI_LOGGING=y CONFIG_SFC_FALCON=y CONFIG_SFC_FALCON_MTD=y CONFIG_SFC_SIENA=y CONFIG_SFC_SIENA_MTD=y CONFIG_SFC_SIENA_MCDI_MON=y CONFIG_SFC_SIENA_SRIOV=y CONFIG_SFC_SIENA_MCDI_LOGGING=y CONFIG_NET_VENDOR_SMSC=y CONFIG_SMC9194=y CONFIG_PCMCIA_SMC91C92=y CONFIG_EPIC100=y CONFIG_SMSC911X=y CONFIG_SMSC9420=y CONFIG_NET_VENDOR_SOCIONEXT=y CONFIG_NET_VENDOR_STMICRO=y CONFIG_STMMAC_ETH=y CONFIG_STMMAC_SELFTESTS=y CONFIG_STMMAC_PLATFORM=y CONFIG_DWMAC_DWC_QOS_ETH=y CONFIG_DWMAC_GENERIC=y CONFIG_DWMAC_INTEL_PLAT=y CONFIG_DWMAC_INTEL=y CONFIG_DWMAC_LOONGSON=y CONFIG_STMMAC_PCI=y CONFIG_NET_VENDOR_SUN=y CONFIG_HAPPYMEAL=y CONFIG_SUNGEM=y CONFIG_CASSINI=y CONFIG_NIU=y CONFIG_NET_VENDOR_SYNOPSYS=y CONFIG_DWC_XLGMAC=y CONFIG_DWC_XLGMAC_PCI=y CONFIG_NET_VENDOR_TEHUTI=y CONFIG_TEHUTI=y CONFIG_NET_VENDOR_TI=y CONFIG_TI_CPSW_PHY_SEL=y CONFIG_TLAN=y CONFIG_NET_VENDOR_VERTEXCOM=y CONFIG_MSE102X=y CONFIG_NET_VENDOR_VIA=y CONFIG_VIA_RHINE=y CONFIG_VIA_RHINE_MMIO=y CONFIG_VIA_VELOCITY=y CONFIG_NET_VENDOR_WIZNET=y CONFIG_WIZNET_W5100=y CONFIG_WIZNET_W5300=y # CONFIG_WIZNET_BUS_DIRECT is not set # CONFIG_WIZNET_BUS_INDIRECT is not set CONFIG_WIZNET_BUS_ANY=y CONFIG_WIZNET_W5100_SPI=y CONFIG_NET_VENDOR_XILINX=y CONFIG_XILINX_EMACLITE=y CONFIG_XILINX_AXI_EMAC=y CONFIG_XILINX_LL_TEMAC=y CONFIG_NET_VENDOR_XIRCOM=y CONFIG_PCMCIA_XIRC2PS=y CONFIG_FDDI=y CONFIG_DEFXX=y CONFIG_SKFP=y CONFIG_HIPPI=y CONFIG_ROADRUNNER=y CONFIG_ROADRUNNER_LARGE_RINGS=y CONFIG_NET_SB1000=y CONFIG_PHYLINK=y CONFIG_PHYLIB=y CONFIG_SWPHY=y CONFIG_LED_TRIGGER_PHY=y CONFIG_FIXED_PHY=y CONFIG_SFP=y # # MII PHY device drivers # CONFIG_AMD_PHY=y CONFIG_ADIN_PHY=y CONFIG_ADIN1100_PHY=y CONFIG_AQUANTIA_PHY=y CONFIG_AX88796B_PHY=y CONFIG_BROADCOM_PHY=y CONFIG_BCM54140_PHY=y CONFIG_BCM7XXX_PHY=y CONFIG_BCM84881_PHY=y CONFIG_BCM87XX_PHY=y CONFIG_BCM_NET_PHYLIB=y CONFIG_BCM_NET_PHYPTP=y CONFIG_CICADA_PHY=y CONFIG_CORTINA_PHY=y CONFIG_DAVICOM_PHY=y CONFIG_ICPLUS_PHY=y CONFIG_LXT_PHY=y CONFIG_INTEL_XWAY_PHY=y CONFIG_LSI_ET1011C_PHY=y CONFIG_MARVELL_PHY=y CONFIG_MARVELL_10G_PHY=y CONFIG_MARVELL_88X2222_PHY=y CONFIG_MAXLINEAR_GPHY=y CONFIG_MEDIATEK_GE_PHY=y CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=y CONFIG_MICROCHIP_T1_PHY=y CONFIG_MICROSEMI_PHY=y CONFIG_MOTORCOMM_PHY=y CONFIG_NATIONAL_PHY=y CONFIG_NXP_C45_TJA11XX_PHY=y CONFIG_NXP_TJA11XX_PHY=y CONFIG_AT803X_PHY=y CONFIG_QSEMI_PHY=y CONFIG_REALTEK_PHY=y CONFIG_RENESAS_PHY=y CONFIG_ROCKCHIP_PHY=y CONFIG_SMSC_PHY=y CONFIG_STE10XP=y CONFIG_TERANETICS_PHY=y CONFIG_DP83822_PHY=y CONFIG_DP83TC811_PHY=y CONFIG_DP83848_PHY=y CONFIG_DP83867_PHY=y CONFIG_DP83869_PHY=y CONFIG_DP83TD510_PHY=y CONFIG_VITESSE_PHY=y CONFIG_XILINX_GMII2RGMII=y CONFIG_MICREL_KS8995MA=y CONFIG_PSE_CONTROLLER=y CONFIG_PSE_REGULATOR=y CONFIG_CAN_DEV=y CONFIG_CAN_VCAN=y CONFIG_CAN_VXCAN=y CONFIG_CAN_NETLINK=y CONFIG_CAN_CALC_BITTIMING=y CONFIG_CAN_RX_OFFLOAD=y CONFIG_CAN_CAN327=y CONFIG_CAN_FLEXCAN=y CONFIG_CAN_GRCAN=y CONFIG_CAN_JANZ_ICAN3=y CONFIG_CAN_KVASER_PCIEFD=y CONFIG_CAN_SLCAN=y CONFIG_PCH_CAN=y CONFIG_CAN_C_CAN=y CONFIG_CAN_C_CAN_PLATFORM=y CONFIG_CAN_C_CAN_PCI=y CONFIG_CAN_CC770=y CONFIG_CAN_CC770_ISA=y CONFIG_CAN_CC770_PLATFORM=y CONFIG_CAN_CTUCANFD=y CONFIG_CAN_CTUCANFD_PCI=y CONFIG_CAN_CTUCANFD_PLATFORM=y CONFIG_CAN_IFI_CANFD=y CONFIG_CAN_M_CAN=y CONFIG_CAN_M_CAN_PCI=y CONFIG_CAN_M_CAN_PLATFORM=y CONFIG_CAN_M_CAN_TCAN4X5X=y CONFIG_CAN_PEAK_PCIEFD=y CONFIG_CAN_SJA1000=y CONFIG_CAN_EMS_PCI=y CONFIG_CAN_EMS_PCMCIA=y CONFIG_CAN_F81601=y CONFIG_CAN_KVASER_PCI=y CONFIG_CAN_PEAK_PCI=y CONFIG_CAN_PEAK_PCIEC=y CONFIG_CAN_PEAK_PCMCIA=y CONFIG_CAN_PLX_PCI=y CONFIG_CAN_SJA1000_ISA=y CONFIG_CAN_SJA1000_PLATFORM=y CONFIG_CAN_TSCAN1=y CONFIG_CAN_SOFTING=y CONFIG_CAN_SOFTING_CS=y # # CAN SPI interfaces # CONFIG_CAN_HI311X=y CONFIG_CAN_MCP251X=y CONFIG_CAN_MCP251XFD=y CONFIG_CAN_MCP251XFD_SANITY=y # end of CAN SPI interfaces # # CAN USB interfaces # CONFIG_CAN_8DEV_USB=y CONFIG_CAN_EMS_USB=y CONFIG_CAN_ESD_USB=y CONFIG_CAN_ETAS_ES58X=y CONFIG_CAN_GS_USB=y CONFIG_CAN_KVASER_USB=y CONFIG_CAN_MCBA_USB=y CONFIG_CAN_PEAK_USB=y CONFIG_CAN_UCAN=y # end of CAN USB interfaces CONFIG_CAN_DEBUG_DEVICES=y # # MCTP Device Drivers # CONFIG_MCTP_SERIAL=y CONFIG_MCTP_TRANSPORT_I2C=y # end of MCTP Device Drivers CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y CONFIG_ACPI_MDIO=y CONFIG_MDIO_DEVRES=y CONFIG_MDIO_BITBANG=y CONFIG_MDIO_BCM_UNIMAC=y CONFIG_MDIO_GPIO=y CONFIG_MDIO_HISI_FEMAC=y CONFIG_MDIO_I2C=y CONFIG_MDIO_MVUSB=y CONFIG_MDIO_MSCC_MIIM=y CONFIG_MDIO_IPQ4019=y CONFIG_MDIO_IPQ8064=y # # MDIO Multiplexers # CONFIG_MDIO_BUS_MUX=y CONFIG_MDIO_BUS_MUX_GPIO=y CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y CONFIG_MDIO_BUS_MUX_MMIOREG=y # # PCS device drivers # CONFIG_PCS_XPCS=y CONFIG_PCS_LYNX=y CONFIG_PCS_ALTERA_TSE=y # end of PCS device drivers CONFIG_PLIP=y CONFIG_PPP=y CONFIG_PPP_BSDCOMP=y CONFIG_PPP_DEFLATE=y CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=y CONFIG_PPP_MULTILINK=y CONFIG_PPPOATM=y CONFIG_PPPOE=y CONFIG_PPTP=y CONFIG_PPPOL2TP=y CONFIG_PPP_ASYNC=y CONFIG_PPP_SYNC_TTY=y CONFIG_SLIP=y CONFIG_SLHC=y CONFIG_SLIP_COMPRESSED=y CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y CONFIG_USB_NET_DRIVERS=y CONFIG_USB_CATC=y CONFIG_USB_KAWETH=y CONFIG_USB_PEGASUS=y CONFIG_USB_RTL8150=y CONFIG_USB_RTL8152=y CONFIG_USB_LAN78XX=y CONFIG_USB_USBNET=y CONFIG_USB_NET_AX8817X=y CONFIG_USB_NET_AX88179_178A=y CONFIG_USB_NET_CDCETHER=y CONFIG_USB_NET_CDC_EEM=y CONFIG_USB_NET_CDC_NCM=y CONFIG_USB_NET_HUAWEI_CDC_NCM=y CONFIG_USB_NET_CDC_MBIM=y CONFIG_USB_NET_DM9601=y CONFIG_USB_NET_SR9700=y CONFIG_USB_NET_SR9800=y CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC95XX=y CONFIG_USB_NET_GL620A=y CONFIG_USB_NET_NET1080=y CONFIG_USB_NET_PLUSB=y CONFIG_USB_NET_MCS7830=y CONFIG_USB_NET_RNDIS_HOST=y CONFIG_USB_NET_CDC_SUBSET_ENABLE=y CONFIG_USB_NET_CDC_SUBSET=y CONFIG_USB_ALI_M5632=y CONFIG_USB_AN2720=y CONFIG_USB_BELKIN=y CONFIG_USB_ARMLINUX=y CONFIG_USB_EPSON2888=y CONFIG_USB_KC2190=y CONFIG_USB_NET_ZAURUS=y CONFIG_USB_NET_CX82310_ETH=y CONFIG_USB_NET_KALMIA=y CONFIG_USB_NET_QMI_WWAN=y CONFIG_USB_HSO=y CONFIG_USB_NET_INT51X1=y CONFIG_USB_CDC_PHONET=y CONFIG_USB_IPHETH=y CONFIG_USB_SIERRA_NET=y CONFIG_USB_VL600=y CONFIG_USB_NET_CH9200=y CONFIG_USB_NET_AQC111=y CONFIG_USB_RTL8153_ECM=y CONFIG_WLAN=y CONFIG_WLAN_VENDOR_ADMTEK=y CONFIG_ADM8211=y CONFIG_ATH_COMMON=y CONFIG_WLAN_VENDOR_ATH=y CONFIG_ATH_DEBUG=y CONFIG_ATH_TRACEPOINTS=y CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS=y CONFIG_ATH_REG_DYNAMIC_USER_CERT_TESTING=y CONFIG_ATH5K=y CONFIG_ATH5K_DEBUG=y CONFIG_ATH5K_TRACER=y CONFIG_ATH5K_PCI=y CONFIG_ATH5K_TEST_CHANNELS=y CONFIG_ATH9K_HW=y CONFIG_ATH9K_COMMON=y CONFIG_ATH9K_COMMON_DEBUG=y CONFIG_ATH9K_DFS_DEBUGFS=y CONFIG_ATH9K_BTCOEX_SUPPORT=y CONFIG_ATH9K=y CONFIG_ATH9K_PCI=y CONFIG_ATH9K_AHB=y CONFIG_ATH9K_DEBUGFS=y CONFIG_ATH9K_STATION_STATISTICS=y CONFIG_ATH9K_TX99=y CONFIG_ATH9K_DFS_CERTIFIED=y CONFIG_ATH9K_DYNACK=y CONFIG_ATH9K_WOW=y CONFIG_ATH9K_RFKILL=y CONFIG_ATH9K_CHANNEL_CONTEXT=y CONFIG_ATH9K_PCOEM=y CONFIG_ATH9K_PCI_NO_EEPROM=y CONFIG_ATH9K_HTC=y CONFIG_ATH9K_HTC_DEBUGFS=y CONFIG_ATH9K_HWRNG=y CONFIG_ATH9K_COMMON_SPECTRAL=y CONFIG_CARL9170=y CONFIG_CARL9170_LEDS=y CONFIG_CARL9170_DEBUGFS=y CONFIG_CARL9170_WPC=y CONFIG_CARL9170_HWRNG=y CONFIG_ATH6KL=y CONFIG_ATH6KL_SDIO=y CONFIG_ATH6KL_USB=y CONFIG_ATH6KL_DEBUG=y CONFIG_ATH6KL_TRACING=y CONFIG_ATH6KL_REGDOMAIN=y CONFIG_AR5523=y CONFIG_WIL6210=y CONFIG_WIL6210_ISR_COR=y CONFIG_WIL6210_TRACING=y CONFIG_WIL6210_DEBUGFS=y CONFIG_ATH10K=y CONFIG_ATH10K_CE=y CONFIG_ATH10K_PCI=y CONFIG_ATH10K_AHB=y CONFIG_ATH10K_SDIO=y CONFIG_ATH10K_USB=y CONFIG_ATH10K_DEBUG=y CONFIG_ATH10K_DEBUGFS=y CONFIG_ATH10K_SPECTRAL=y CONFIG_ATH10K_TRACING=y CONFIG_ATH10K_DFS_CERTIFIED=y CONFIG_WCN36XX=y CONFIG_WCN36XX_DEBUGFS=y CONFIG_ATH11K=y CONFIG_ATH11K_AHB=y CONFIG_ATH11K_PCI=y CONFIG_ATH11K_DEBUG=y CONFIG_ATH11K_DEBUGFS=y CONFIG_ATH11K_TRACING=y CONFIG_ATH11K_SPECTRAL=y CONFIG_WLAN_VENDOR_ATMEL=y CONFIG_ATMEL=y CONFIG_PCI_ATMEL=y CONFIG_PCMCIA_ATMEL=y CONFIG_AT76C50X_USB=y CONFIG_WLAN_VENDOR_BROADCOM=y CONFIG_B43=y CONFIG_B43_BCMA=y CONFIG_B43_SSB=y CONFIG_B43_BUSES_BCMA_AND_SSB=y # CONFIG_B43_BUSES_BCMA is not set # CONFIG_B43_BUSES_SSB is not set CONFIG_B43_PCI_AUTOSELECT=y CONFIG_B43_PCICORE_AUTOSELECT=y CONFIG_B43_SDIO=y CONFIG_B43_BCMA_PIO=y CONFIG_B43_PIO=y CONFIG_B43_PHY_G=y CONFIG_B43_PHY_N=y CONFIG_B43_PHY_LP=y CONFIG_B43_PHY_HT=y CONFIG_B43_LEDS=y CONFIG_B43_HWRNG=y CONFIG_B43_DEBUG=y CONFIG_B43LEGACY=y CONFIG_B43LEGACY_PCI_AUTOSELECT=y CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y CONFIG_B43LEGACY_LEDS=y CONFIG_B43LEGACY_HWRNG=y CONFIG_B43LEGACY_DEBUG=y CONFIG_B43LEGACY_DMA=y CONFIG_B43LEGACY_PIO=y CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y # CONFIG_B43LEGACY_DMA_MODE is not set # CONFIG_B43LEGACY_PIO_MODE is not set CONFIG_BRCMUTIL=y CONFIG_BRCMSMAC=y CONFIG_BRCMSMAC_LEDS=y CONFIG_BRCMFMAC=y CONFIG_BRCMFMAC_PROTO_BCDC=y CONFIG_BRCMFMAC_PROTO_MSGBUF=y CONFIG_BRCMFMAC_SDIO=y CONFIG_BRCMFMAC_USB=y CONFIG_BRCMFMAC_PCIE=y CONFIG_BRCM_TRACING=y CONFIG_BRCMDBG=y CONFIG_WLAN_VENDOR_CISCO=y CONFIG_AIRO=y CONFIG_AIRO_CS=y CONFIG_WLAN_VENDOR_INTEL=y CONFIG_IPW2100=y CONFIG_IPW2100_MONITOR=y CONFIG_IPW2100_DEBUG=y CONFIG_IPW2200=y CONFIG_IPW2200_MONITOR=y CONFIG_IPW2200_RADIOTAP=y CONFIG_IPW2200_PROMISCUOUS=y CONFIG_IPW2200_QOS=y CONFIG_IPW2200_DEBUG=y CONFIG_LIBIPW=y CONFIG_LIBIPW_DEBUG=y CONFIG_IWLEGACY=y CONFIG_IWL4965=y CONFIG_IWL3945=y # # iwl3945 / iwl4965 Debugging Options # CONFIG_IWLEGACY_DEBUG=y CONFIG_IWLEGACY_DEBUGFS=y # end of iwl3945 / iwl4965 Debugging Options CONFIG_IWLWIFI=y CONFIG_IWLWIFI_LEDS=y CONFIG_IWLDVM=y CONFIG_IWLMVM=y # # Debugging Options # CONFIG_IWLWIFI_DEBUG=y CONFIG_IWLWIFI_DEBUGFS=y CONFIG_IWLWIFI_DEVICE_TRACING=y # end of Debugging Options CONFIG_WLAN_VENDOR_INTERSIL=y CONFIG_HOSTAP=y CONFIG_HOSTAP_FIRMWARE=y CONFIG_HOSTAP_FIRMWARE_NVRAM=y CONFIG_HOSTAP_PLX=y CONFIG_HOSTAP_PCI=y CONFIG_HOSTAP_CS=y CONFIG_HERMES=y CONFIG_HERMES_PRISM=y CONFIG_HERMES_CACHE_FW_ON_INIT=y CONFIG_PLX_HERMES=y CONFIG_TMD_HERMES=y CONFIG_NORTEL_HERMES=y CONFIG_PCI_HERMES=y CONFIG_PCMCIA_HERMES=y CONFIG_PCMCIA_SPECTRUM=y CONFIG_ORINOCO_USB=y CONFIG_P54_COMMON=y CONFIG_P54_USB=y CONFIG_P54_PCI=y CONFIG_P54_SPI=y CONFIG_P54_SPI_DEFAULT_EEPROM=y CONFIG_P54_LEDS=y CONFIG_WLAN_VENDOR_MARVELL=y CONFIG_LIBERTAS=y CONFIG_LIBERTAS_USB=y CONFIG_LIBERTAS_CS=y CONFIG_LIBERTAS_SDIO=y CONFIG_LIBERTAS_SPI=y CONFIG_LIBERTAS_DEBUG=y CONFIG_LIBERTAS_MESH=y CONFIG_LIBERTAS_THINFIRM=y CONFIG_LIBERTAS_THINFIRM_DEBUG=y CONFIG_LIBERTAS_THINFIRM_USB=y CONFIG_MWIFIEX=y CONFIG_MWIFIEX_SDIO=y CONFIG_MWIFIEX_PCIE=y CONFIG_MWIFIEX_USB=y CONFIG_MWL8K=y CONFIG_WLAN_VENDOR_MEDIATEK=y CONFIG_MT7601U=y CONFIG_MT76_CORE=y CONFIG_MT76_LEDS=y CONFIG_MT76_USB=y CONFIG_MT76_SDIO=y CONFIG_MT76x02_LIB=y CONFIG_MT76x02_USB=y CONFIG_MT76_CONNAC_LIB=y CONFIG_MT76x0_COMMON=y CONFIG_MT76x0U=y CONFIG_MT76x0E=y CONFIG_MT76x2_COMMON=y CONFIG_MT76x2E=y CONFIG_MT76x2U=y CONFIG_MT7603E=y CONFIG_MT7615_COMMON=y CONFIG_MT7615E=y CONFIG_MT7663_USB_SDIO_COMMON=y CONFIG_MT7663U=y CONFIG_MT7663S=y CONFIG_MT7915E=y CONFIG_MT7921_COMMON=y CONFIG_MT7921E=y CONFIG_MT7921S=y CONFIG_MT7921U=y CONFIG_WLAN_VENDOR_MICROCHIP=y CONFIG_WILC1000=y CONFIG_WILC1000_SDIO=y CONFIG_WILC1000_SPI=y CONFIG_WILC1000_HW_OOB_INTR=y CONFIG_WLAN_VENDOR_PURELIFI=y CONFIG_PLFXLC=y CONFIG_WLAN_VENDOR_RALINK=y CONFIG_RT2X00=y CONFIG_RT2400PCI=y CONFIG_RT2500PCI=y CONFIG_RT61PCI=y CONFIG_RT2800PCI=y CONFIG_RT2800PCI_RT33XX=y CONFIG_RT2800PCI_RT35XX=y CONFIG_RT2800PCI_RT53XX=y CONFIG_RT2800PCI_RT3290=y CONFIG_RT2500USB=y CONFIG_RT73USB=y CONFIG_RT2800USB=y CONFIG_RT2800USB_RT33XX=y CONFIG_RT2800USB_RT35XX=y CONFIG_RT2800USB_RT3573=y CONFIG_RT2800USB_RT53XX=y CONFIG_RT2800USB_RT55XX=y CONFIG_RT2800USB_UNKNOWN=y CONFIG_RT2800_LIB=y CONFIG_RT2800_LIB_MMIO=y CONFIG_RT2X00_LIB_MMIO=y CONFIG_RT2X00_LIB_PCI=y CONFIG_RT2X00_LIB_USB=y CONFIG_RT2X00_LIB=y CONFIG_RT2X00_LIB_FIRMWARE=y CONFIG_RT2X00_LIB_CRYPTO=y CONFIG_RT2X00_LIB_LEDS=y CONFIG_RT2X00_LIB_DEBUGFS=y CONFIG_RT2X00_DEBUG=y CONFIG_WLAN_VENDOR_REALTEK=y CONFIG_RTL8180=y CONFIG_RTL8187=y CONFIG_RTL8187_LEDS=y CONFIG_RTL_CARDS=y CONFIG_RTL8192CE=y CONFIG_RTL8192SE=y CONFIG_RTL8192DE=y CONFIG_RTL8723AE=y CONFIG_RTL8723BE=y CONFIG_RTL8188EE=y CONFIG_RTL8192EE=y CONFIG_RTL8821AE=y CONFIG_RTL8192CU=y CONFIG_RTLWIFI=y CONFIG_RTLWIFI_PCI=y CONFIG_RTLWIFI_USB=y CONFIG_RTLWIFI_DEBUG=y CONFIG_RTL8192C_COMMON=y CONFIG_RTL8723_COMMON=y CONFIG_RTLBTCOEXIST=y CONFIG_RTL8XXXU=y CONFIG_RTL8XXXU_UNTESTED=y CONFIG_RTW88=y CONFIG_RTW88_CORE=y CONFIG_RTW88_PCI=y CONFIG_RTW88_8822B=y CONFIG_RTW88_8822C=y CONFIG_RTW88_8723D=y CONFIG_RTW88_8821C=y CONFIG_RTW88_8822BE=y CONFIG_RTW88_8822CE=y CONFIG_RTW88_8723DE=y CONFIG_RTW88_8821CE=y CONFIG_RTW88_DEBUG=y CONFIG_RTW88_DEBUGFS=y CONFIG_RTW89=y CONFIG_RTW89_CORE=y CONFIG_RTW89_PCI=y CONFIG_RTW89_8852A=y CONFIG_RTW89_8852C=y CONFIG_RTW89_8852AE=y CONFIG_RTW89_8852CE=y CONFIG_RTW89_DEBUG=y CONFIG_RTW89_DEBUGMSG=y CONFIG_RTW89_DEBUGFS=y CONFIG_WLAN_VENDOR_RSI=y CONFIG_RSI_91X=y CONFIG_RSI_DEBUGFS=y CONFIG_RSI_SDIO=y CONFIG_RSI_USB=y CONFIG_RSI_COEX=y CONFIG_WLAN_VENDOR_SILABS=y CONFIG_WFX=y CONFIG_WLAN_VENDOR_ST=y CONFIG_CW1200=y CONFIG_CW1200_WLAN_SDIO=y CONFIG_CW1200_WLAN_SPI=y CONFIG_WLAN_VENDOR_TI=y CONFIG_WL1251=y CONFIG_WL1251_SPI=y CONFIG_WL1251_SDIO=y CONFIG_WL12XX=y CONFIG_WL18XX=y CONFIG_WLCORE=y CONFIG_WLCORE_SPI=y CONFIG_WLCORE_SDIO=y CONFIG_WILINK_PLATFORM_DATA=y CONFIG_WLAN_VENDOR_ZYDAS=y CONFIG_USB_ZD1201=y CONFIG_ZD1211RW=y CONFIG_ZD1211RW_DEBUG=y CONFIG_WLAN_VENDOR_QUANTENNA=y CONFIG_QTNFMAC=y CONFIG_QTNFMAC_PCIE=y CONFIG_PCMCIA_RAYCS=y CONFIG_PCMCIA_WL3501=y CONFIG_MAC80211_HWSIM=y CONFIG_USB_NET_RNDIS_WLAN=y CONFIG_VIRT_WIFI=y CONFIG_WAN=y CONFIG_HDLC=y CONFIG_HDLC_RAW=y CONFIG_HDLC_RAW_ETH=y CONFIG_HDLC_CISCO=y CONFIG_HDLC_FR=y CONFIG_HDLC_PPP=y CONFIG_HDLC_X25=y CONFIG_PCI200SYN=y CONFIG_WANXL=y CONFIG_PC300TOO=y CONFIG_N2=y CONFIG_C101=y CONFIG_FARSYNC=y CONFIG_LAPBETHER=y CONFIG_IEEE802154_DRIVERS=y CONFIG_IEEE802154_FAKELB=y CONFIG_IEEE802154_AT86RF230=y CONFIG_IEEE802154_MRF24J40=y CONFIG_IEEE802154_CC2520=y CONFIG_IEEE802154_ATUSB=y CONFIG_IEEE802154_ADF7242=y CONFIG_IEEE802154_CA8210=y CONFIG_IEEE802154_CA8210_DEBUGFS=y CONFIG_IEEE802154_MCR20A=y CONFIG_IEEE802154_HWSIM=y # # Wireless WAN # CONFIG_WWAN=y CONFIG_WWAN_DEBUGFS=y CONFIG_WWAN_HWSIM=y CONFIG_MHI_WWAN_CTRL=y CONFIG_MHI_WWAN_MBIM=y CONFIG_RPMSG_WWAN_CTRL=y CONFIG_IOSM=y CONFIG_MTK_T7XX=y # end of Wireless WAN CONFIG_VMXNET3=y CONFIG_FUJITSU_ES=y CONFIG_USB4_NET=y CONFIG_HYPERV_NET=y CONFIG_NETDEVSIM=y CONFIG_NET_FAILOVER=y CONFIG_NETDEV_LEGACY_INIT=y CONFIG_ISDN=y CONFIG_ISDN_CAPI=y CONFIG_CAPI_TRACE=y CONFIG_ISDN_CAPI_MIDDLEWARE=y CONFIG_MISDN=y CONFIG_MISDN_DSP=y CONFIG_MISDN_L1OIP=y # # mISDN hardware drivers # CONFIG_MISDN_HFCPCI=y CONFIG_MISDN_HFCMULTI=y CONFIG_MISDN_HFCUSB=y CONFIG_MISDN_AVMFRITZ=y CONFIG_MISDN_SPEEDFAX=y CONFIG_MISDN_INFINEON=y CONFIG_MISDN_W6692=y CONFIG_MISDN_NETJET=y CONFIG_MISDN_HDLC=y CONFIG_MISDN_IPAC=y CONFIG_MISDN_ISAR=y # # Input device support # CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y CONFIG_INPUT_SPARSEKMAP=y CONFIG_INPUT_MATRIXKMAP=y CONFIG_INPUT_VIVALDIFMAP=y # # Userland interfaces # CONFIG_INPUT_MOUSEDEV=y CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 CONFIG_INPUT_JOYDEV=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=y # # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y CONFIG_KEYBOARD_ADC=y CONFIG_KEYBOARD_ADP5520=y CONFIG_KEYBOARD_ADP5588=y CONFIG_KEYBOARD_ADP5589=y CONFIG_KEYBOARD_APPLESPI=y CONFIG_KEYBOARD_ATKBD=y CONFIG_KEYBOARD_QT1050=y CONFIG_KEYBOARD_QT1070=y CONFIG_KEYBOARD_QT2160=y CONFIG_KEYBOARD_DLINK_DIR685=y CONFIG_KEYBOARD_LKKBD=y CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_GPIO_POLLED=y CONFIG_KEYBOARD_TCA6416=y CONFIG_KEYBOARD_TCA8418=y CONFIG_KEYBOARD_MATRIX=y CONFIG_KEYBOARD_LM8323=y CONFIG_KEYBOARD_LM8333=y CONFIG_KEYBOARD_MAX7359=y CONFIG_KEYBOARD_MCS=y CONFIG_KEYBOARD_MPR121=y CONFIG_KEYBOARD_NEWTON=y CONFIG_KEYBOARD_OPENCORES=y CONFIG_KEYBOARD_PINEPHONE=y CONFIG_KEYBOARD_SAMSUNG=y CONFIG_KEYBOARD_GOLDFISH_EVENTS=y CONFIG_KEYBOARD_STOWAWAY=y CONFIG_KEYBOARD_SUNKBD=y CONFIG_KEYBOARD_STMPE=y CONFIG_KEYBOARD_IQS62X=y CONFIG_KEYBOARD_OMAP4=y CONFIG_KEYBOARD_TC3589X=y CONFIG_KEYBOARD_TM2_TOUCHKEY=y CONFIG_KEYBOARD_TWL4030=y CONFIG_KEYBOARD_XTKBD=y CONFIG_KEYBOARD_CROS_EC=y CONFIG_KEYBOARD_CAP11XX=y CONFIG_KEYBOARD_BCM=y CONFIG_KEYBOARD_MTK_PMIC=y CONFIG_KEYBOARD_CYPRESS_SF=y CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2_ALPS=y CONFIG_MOUSE_PS2_BYD=y CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y CONFIG_MOUSE_PS2_CYPRESS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y CONFIG_MOUSE_PS2_ELANTECH=y CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y CONFIG_MOUSE_PS2_SENTELIC=y CONFIG_MOUSE_PS2_TOUCHKIT=y CONFIG_MOUSE_PS2_OLPC=y CONFIG_MOUSE_PS2_FOCALTECH=y CONFIG_MOUSE_PS2_VMMOUSE=y CONFIG_MOUSE_PS2_SMBUS=y CONFIG_MOUSE_SERIAL=y CONFIG_MOUSE_APPLETOUCH=y CONFIG_MOUSE_BCM5974=y CONFIG_MOUSE_CYAPA=y CONFIG_MOUSE_ELAN_I2C=y CONFIG_MOUSE_ELAN_I2C_I2C=y CONFIG_MOUSE_ELAN_I2C_SMBUS=y CONFIG_MOUSE_INPORT=y CONFIG_MOUSE_ATIXL=y CONFIG_MOUSE_LOGIBM=y CONFIG_MOUSE_PC110PAD=y CONFIG_MOUSE_VSXXXAA=y CONFIG_MOUSE_GPIO=y CONFIG_MOUSE_SYNAPTICS_I2C=y CONFIG_MOUSE_SYNAPTICS_USB=y CONFIG_INPUT_JOYSTICK=y CONFIG_JOYSTICK_ANALOG=y CONFIG_JOYSTICK_A3D=y CONFIG_JOYSTICK_ADC=y CONFIG_JOYSTICK_ADI=y CONFIG_JOYSTICK_COBRA=y CONFIG_JOYSTICK_GF2K=y CONFIG_JOYSTICK_GRIP=y CONFIG_JOYSTICK_GRIP_MP=y CONFIG_JOYSTICK_GUILLEMOT=y CONFIG_JOYSTICK_INTERACT=y CONFIG_JOYSTICK_SIDEWINDER=y CONFIG_JOYSTICK_TMDC=y CONFIG_JOYSTICK_IFORCE=y CONFIG_JOYSTICK_IFORCE_USB=y CONFIG_JOYSTICK_IFORCE_232=y CONFIG_JOYSTICK_WARRIOR=y CONFIG_JOYSTICK_MAGELLAN=y CONFIG_JOYSTICK_SPACEORB=y CONFIG_JOYSTICK_SPACEBALL=y CONFIG_JOYSTICK_STINGER=y CONFIG_JOYSTICK_TWIDJOY=y CONFIG_JOYSTICK_ZHENHUA=y CONFIG_JOYSTICK_DB9=y CONFIG_JOYSTICK_GAMECON=y CONFIG_JOYSTICK_TURBOGRAFX=y CONFIG_JOYSTICK_AS5011=y CONFIG_JOYSTICK_JOYDUMP=y CONFIG_JOYSTICK_XPAD=y CONFIG_JOYSTICK_XPAD_FF=y CONFIG_JOYSTICK_XPAD_LEDS=y CONFIG_JOYSTICK_WALKERA0701=y CONFIG_JOYSTICK_PSXPAD_SPI=y CONFIG_JOYSTICK_PSXPAD_SPI_FF=y CONFIG_JOYSTICK_PXRC=y CONFIG_JOYSTICK_QWIIC=y CONFIG_JOYSTICK_FSIA6B=y CONFIG_JOYSTICK_SENSEHAT=y CONFIG_INPUT_TABLET=y CONFIG_TABLET_USB_ACECAD=y CONFIG_TABLET_USB_AIPTEK=y CONFIG_TABLET_USB_HANWANG=y CONFIG_TABLET_USB_KBTAB=y CONFIG_TABLET_USB_PEGASUS=y CONFIG_TABLET_SERIAL_WACOM4=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_88PM860X=y CONFIG_TOUCHSCREEN_ADS7846=y CONFIG_TOUCHSCREEN_AD7877=y CONFIG_TOUCHSCREEN_AD7879=y CONFIG_TOUCHSCREEN_AD7879_I2C=y CONFIG_TOUCHSCREEN_AD7879_SPI=y CONFIG_TOUCHSCREEN_ADC=y CONFIG_TOUCHSCREEN_AR1021_I2C=y CONFIG_TOUCHSCREEN_ATMEL_MXT=y CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y CONFIG_TOUCHSCREEN_AUO_PIXCIR=y CONFIG_TOUCHSCREEN_BU21013=y CONFIG_TOUCHSCREEN_BU21029=y CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=y CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=y CONFIG_TOUCHSCREEN_CY8CTMA140=y CONFIG_TOUCHSCREEN_CY8CTMG110=y CONFIG_TOUCHSCREEN_CYTTSP_CORE=y CONFIG_TOUCHSCREEN_CYTTSP_I2C=y CONFIG_TOUCHSCREEN_CYTTSP_SPI=y CONFIG_TOUCHSCREEN_CYTTSP4_CORE=y CONFIG_TOUCHSCREEN_CYTTSP4_I2C=y CONFIG_TOUCHSCREEN_CYTTSP4_SPI=y CONFIG_TOUCHSCREEN_DA9034=y CONFIG_TOUCHSCREEN_DA9052=y CONFIG_TOUCHSCREEN_DYNAPRO=y CONFIG_TOUCHSCREEN_HAMPSHIRE=y CONFIG_TOUCHSCREEN_EETI=y CONFIG_TOUCHSCREEN_EGALAX=y CONFIG_TOUCHSCREEN_EGALAX_SERIAL=y CONFIG_TOUCHSCREEN_EXC3000=y CONFIG_TOUCHSCREEN_FUJITSU=y CONFIG_TOUCHSCREEN_GOODIX=y CONFIG_TOUCHSCREEN_HIDEEP=y CONFIG_TOUCHSCREEN_HYCON_HY46XX=y CONFIG_TOUCHSCREEN_ILI210X=y CONFIG_TOUCHSCREEN_ILITEK=y CONFIG_TOUCHSCREEN_S6SY761=y CONFIG_TOUCHSCREEN_GUNZE=y CONFIG_TOUCHSCREEN_EKTF2127=y CONFIG_TOUCHSCREEN_ELAN=y CONFIG_TOUCHSCREEN_ELO=y CONFIG_TOUCHSCREEN_WACOM_W8001=y CONFIG_TOUCHSCREEN_WACOM_I2C=y CONFIG_TOUCHSCREEN_MAX11801=y CONFIG_TOUCHSCREEN_MCS5000=y CONFIG_TOUCHSCREEN_MMS114=y CONFIG_TOUCHSCREEN_MELFAS_MIP4=y CONFIG_TOUCHSCREEN_MSG2638=y CONFIG_TOUCHSCREEN_MTOUCH=y CONFIG_TOUCHSCREEN_IMAGIS=y CONFIG_TOUCHSCREEN_IMX6UL_TSC=y CONFIG_TOUCHSCREEN_INEXIO=y CONFIG_TOUCHSCREEN_MK712=y CONFIG_TOUCHSCREEN_HTCPEN=y CONFIG_TOUCHSCREEN_PENMOUNT=y CONFIG_TOUCHSCREEN_EDT_FT5X06=y CONFIG_TOUCHSCREEN_TOUCHRIGHT=y CONFIG_TOUCHSCREEN_TOUCHWIN=y CONFIG_TOUCHSCREEN_TI_AM335X_TSC=y CONFIG_TOUCHSCREEN_UCB1400=y CONFIG_TOUCHSCREEN_PIXCIR=y CONFIG_TOUCHSCREEN_WDT87XX_I2C=y CONFIG_TOUCHSCREEN_WM831X=y CONFIG_TOUCHSCREEN_WM97XX=y CONFIG_TOUCHSCREEN_WM9705=y CONFIG_TOUCHSCREEN_WM9712=y CONFIG_TOUCHSCREEN_WM9713=y CONFIG_TOUCHSCREEN_USB_COMPOSITE=y CONFIG_TOUCHSCREEN_MC13783=y CONFIG_TOUCHSCREEN_USB_EGALAX=y CONFIG_TOUCHSCREEN_USB_PANJIT=y CONFIG_TOUCHSCREEN_USB_3M=y CONFIG_TOUCHSCREEN_USB_ITM=y CONFIG_TOUCHSCREEN_USB_ETURBO=y CONFIG_TOUCHSCREEN_USB_GUNZE=y CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y CONFIG_TOUCHSCREEN_USB_IRTOUCH=y CONFIG_TOUCHSCREEN_USB_IDEALTEK=y CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y CONFIG_TOUCHSCREEN_USB_GOTOP=y CONFIG_TOUCHSCREEN_USB_JASTEC=y CONFIG_TOUCHSCREEN_USB_ELO=y CONFIG_TOUCHSCREEN_USB_E2I=y CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y CONFIG_TOUCHSCREEN_USB_NEXIO=y CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y CONFIG_TOUCHSCREEN_TOUCHIT213=y CONFIG_TOUCHSCREEN_TSC_SERIO=y CONFIG_TOUCHSCREEN_TSC200X_CORE=y CONFIG_TOUCHSCREEN_TSC2004=y CONFIG_TOUCHSCREEN_TSC2005=y CONFIG_TOUCHSCREEN_TSC2007=y CONFIG_TOUCHSCREEN_TSC2007_IIO=y CONFIG_TOUCHSCREEN_PCAP=y CONFIG_TOUCHSCREEN_RM_TS=y CONFIG_TOUCHSCREEN_SILEAD=y CONFIG_TOUCHSCREEN_SIS_I2C=y CONFIG_TOUCHSCREEN_ST1232=y CONFIG_TOUCHSCREEN_STMFTS=y CONFIG_TOUCHSCREEN_STMPE=y CONFIG_TOUCHSCREEN_SUR40=y CONFIG_TOUCHSCREEN_SURFACE3_SPI=y CONFIG_TOUCHSCREEN_SX8654=y CONFIG_TOUCHSCREEN_TPS6507X=y CONFIG_TOUCHSCREEN_ZET6223=y CONFIG_TOUCHSCREEN_ZFORCE=y CONFIG_TOUCHSCREEN_COLIBRI_VF50=y CONFIG_TOUCHSCREEN_ROHM_BU21023=y CONFIG_TOUCHSCREEN_IQS5XX=y CONFIG_TOUCHSCREEN_ZINITIX=y CONFIG_INPUT_MISC=y CONFIG_INPUT_88PM860X_ONKEY=y CONFIG_INPUT_88PM80X_ONKEY=y CONFIG_INPUT_AD714X=y CONFIG_INPUT_AD714X_I2C=y CONFIG_INPUT_AD714X_SPI=y CONFIG_INPUT_ARIZONA_HAPTICS=y CONFIG_INPUT_ATC260X_ONKEY=y CONFIG_INPUT_ATMEL_CAPTOUCH=y CONFIG_INPUT_BMA150=y CONFIG_INPUT_E3X0_BUTTON=y CONFIG_INPUT_PCSPKR=y CONFIG_INPUT_MAX77650_ONKEY=y CONFIG_INPUT_MAX77693_HAPTIC=y CONFIG_INPUT_MAX8925_ONKEY=y CONFIG_INPUT_MAX8997_HAPTIC=y CONFIG_INPUT_MC13783_PWRBUTTON=y CONFIG_INPUT_MMA8450=y CONFIG_INPUT_APANEL=y CONFIG_INPUT_GPIO_BEEPER=y CONFIG_INPUT_GPIO_DECODER=y CONFIG_INPUT_GPIO_VIBRA=y CONFIG_INPUT_CPCAP_PWRBUTTON=y CONFIG_INPUT_WISTRON_BTNS=y CONFIG_INPUT_ATLAS_BTNS=y CONFIG_INPUT_ATI_REMOTE2=y CONFIG_INPUT_KEYSPAN_REMOTE=y CONFIG_INPUT_KXTJ9=y CONFIG_INPUT_POWERMATE=y CONFIG_INPUT_YEALINK=y CONFIG_INPUT_CM109=y CONFIG_INPUT_REGULATOR_HAPTIC=y CONFIG_INPUT_RETU_PWRBUTTON=y CONFIG_INPUT_TPS65218_PWRBUTTON=y CONFIG_INPUT_AXP20X_PEK=y CONFIG_INPUT_TWL4030_PWRBUTTON=y CONFIG_INPUT_TWL4030_VIBRA=y CONFIG_INPUT_TWL6040_VIBRA=y CONFIG_INPUT_UINPUT=y CONFIG_INPUT_PALMAS_PWRBUTTON=y CONFIG_INPUT_PCF50633_PMU=y CONFIG_INPUT_PCF8574=y CONFIG_INPUT_PWM_BEEPER=y CONFIG_INPUT_PWM_VIBRA=y CONFIG_INPUT_RK805_PWRKEY=y CONFIG_INPUT_GPIO_ROTARY_ENCODER=y CONFIG_INPUT_DA7280_HAPTICS=y CONFIG_INPUT_DA9052_ONKEY=y CONFIG_INPUT_DA9055_ONKEY=y CONFIG_INPUT_DA9063_ONKEY=y CONFIG_INPUT_WM831X_ON=y CONFIG_INPUT_PCAP=y CONFIG_INPUT_ADXL34X=y CONFIG_INPUT_ADXL34X_I2C=y CONFIG_INPUT_ADXL34X_SPI=y CONFIG_INPUT_IBM_PANEL=y CONFIG_INPUT_IMS_PCU=y CONFIG_INPUT_IQS269A=y CONFIG_INPUT_IQS626A=y CONFIG_INPUT_IQS7222=y CONFIG_INPUT_CMA3000=y CONFIG_INPUT_CMA3000_I2C=y CONFIG_INPUT_IDEAPAD_SLIDEBAR=y CONFIG_INPUT_SOC_BUTTON_ARRAY=y CONFIG_INPUT_DRV260X_HAPTICS=y CONFIG_INPUT_DRV2665_HAPTICS=y CONFIG_INPUT_DRV2667_HAPTICS=y CONFIG_INPUT_RAVE_SP_PWRBUTTON=y CONFIG_INPUT_RT5120_PWRKEY=y CONFIG_INPUT_STPMIC1_ONKEY=y CONFIG_RMI4_CORE=y CONFIG_RMI4_I2C=y CONFIG_RMI4_SPI=y CONFIG_RMI4_SMB=y CONFIG_RMI4_F03=y CONFIG_RMI4_F03_SERIO=y CONFIG_RMI4_2D_SENSOR=y CONFIG_RMI4_F11=y CONFIG_RMI4_F12=y CONFIG_RMI4_F30=y CONFIG_RMI4_F34=y CONFIG_RMI4_F3A=y CONFIG_RMI4_F54=y CONFIG_RMI4_F55=y # # Hardware I/O ports # CONFIG_SERIO=y CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y CONFIG_SERIO_I8042=y CONFIG_SERIO_SERPORT=y CONFIG_SERIO_CT82C710=y CONFIG_SERIO_PARKBD=y CONFIG_SERIO_PCIPS2=y CONFIG_SERIO_LIBPS2=y CONFIG_SERIO_RAW=y CONFIG_SERIO_ALTERA_PS2=y CONFIG_SERIO_PS2MULT=y CONFIG_SERIO_ARC_PS2=y CONFIG_SERIO_APBPS2=y CONFIG_HYPERV_KEYBOARD=y CONFIG_SERIO_GPIO_PS2=y CONFIG_USERIO=y CONFIG_GAMEPORT=y CONFIG_GAMEPORT_NS558=y CONFIG_GAMEPORT_L4=y CONFIG_GAMEPORT_EMU10K1=y CONFIG_GAMEPORT_FM801=y # end of Hardware I/O ports # end of Input device support # # Character devices # CONFIG_TTY=y CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_VT_CONSOLE_SLEEP=y CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 CONFIG_LDISC_AUTOLOAD=y # # Serial drivers # CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_PNP=y CONFIG_SERIAL_8250_16550A_VARIANTS=y CONFIG_SERIAL_8250_FINTEK=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DMA=y CONFIG_SERIAL_8250_PCI=y CONFIG_SERIAL_8250_EXAR=y CONFIG_SERIAL_8250_CS=y CONFIG_SERIAL_8250_MEN_MCB=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_FOURPORT=y CONFIG_SERIAL_8250_ACCENT=y CONFIG_SERIAL_8250_BOCA=y CONFIG_SERIAL_8250_EXAR_ST16C554=y CONFIG_SERIAL_8250_HUB6=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_8250_RT288X=y CONFIG_SERIAL_8250_LPSS=y CONFIG_SERIAL_8250_MID=y CONFIG_SERIAL_8250_PERICOM=y CONFIG_SERIAL_OF_PLATFORM=y # # Non-8250 serial port support # CONFIG_SERIAL_KGDB_NMI=y CONFIG_SERIAL_MAX3100=y CONFIG_SERIAL_MAX310X=y CONFIG_SERIAL_UARTLITE=y CONFIG_SERIAL_UARTLITE_CONSOLE=y CONFIG_SERIAL_UARTLITE_NR_UARTS=1 CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_CONSOLE_POLL=y CONFIG_SERIAL_JSM=y CONFIG_SERIAL_SIFIVE=y CONFIG_SERIAL_SIFIVE_CONSOLE=y CONFIG_SERIAL_LANTIQ=y CONFIG_SERIAL_LANTIQ_CONSOLE=y CONFIG_SERIAL_SCCNXP=y CONFIG_SERIAL_SCCNXP_CONSOLE=y CONFIG_SERIAL_SC16IS7XX_CORE=y CONFIG_SERIAL_SC16IS7XX=y CONFIG_SERIAL_SC16IS7XX_I2C=y CONFIG_SERIAL_SC16IS7XX_SPI=y CONFIG_SERIAL_TIMBERDALE=y CONFIG_SERIAL_ALTERA_JTAGUART=y CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE=y CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE_BYPASS=y CONFIG_SERIAL_ALTERA_UART=y CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4 CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200 CONFIG_SERIAL_ALTERA_UART_CONSOLE=y CONFIG_SERIAL_PCH_UART=y CONFIG_SERIAL_PCH_UART_CONSOLE=y CONFIG_SERIAL_XILINX_PS_UART=y CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y CONFIG_SERIAL_ARC=y CONFIG_SERIAL_ARC_CONSOLE=y CONFIG_SERIAL_ARC_NR_PORTS=1 CONFIG_SERIAL_RP2=y CONFIG_SERIAL_RP2_NR_UARTS=32 CONFIG_SERIAL_FSL_LPUART=y CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_FSL_LINFLEXUART=y CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y CONFIG_SERIAL_CONEXANT_DIGICOLOR=y CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y CONFIG_SERIAL_MEN_Z135=y CONFIG_SERIAL_SPRD=y CONFIG_SERIAL_SPRD_CONSOLE=y CONFIG_SERIAL_LITEUART=y CONFIG_SERIAL_LITEUART_MAX_PORTS=1 CONFIG_SERIAL_LITEUART_CONSOLE=y # end of Serial drivers CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_NONSTANDARD=y CONFIG_MOXA_INTELLIO=y CONFIG_MOXA_SMARTIO=y CONFIG_SYNCLINK_GT=y CONFIG_N_HDLC=y CONFIG_GOLDFISH_TTY=y CONFIG_GOLDFISH_TTY_EARLY_CONSOLE=y CONFIG_N_GSM=y CONFIG_NOZOMI=y CONFIG_NULL_TTY=y CONFIG_HVC_DRIVER=y CONFIG_RPMSG_TTY=y CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y CONFIG_TTY_PRINTK=y CONFIG_TTY_PRINTK_LEVEL=6 CONFIG_PRINTER=y CONFIG_LP_CONSOLE=y CONFIG_PPDEV=y CONFIG_VIRTIO_CONSOLE=y CONFIG_IPMI_HANDLER=y CONFIG_IPMI_DMI_DECODE=y CONFIG_IPMI_PLAT_DATA=y CONFIG_IPMI_PANIC_EVENT=y CONFIG_IPMI_PANIC_STRING=y CONFIG_IPMI_DEVICE_INTERFACE=y CONFIG_IPMI_SI=y CONFIG_IPMI_SSIF=y CONFIG_IPMI_IPMB=y CONFIG_IPMI_WATCHDOG=y CONFIG_IPMI_POWEROFF=y CONFIG_IPMB_DEVICE_INTERFACE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_TIMERIOMEM=y CONFIG_HW_RANDOM_INTEL=y CONFIG_HW_RANDOM_AMD=y CONFIG_HW_RANDOM_BA431=y CONFIG_HW_RANDOM_GEODE=y CONFIG_HW_RANDOM_VIA=y CONFIG_HW_RANDOM_VIRTIO=y CONFIG_HW_RANDOM_CCTRNG=y CONFIG_HW_RANDOM_XIPHERA=y CONFIG_DTLK=y CONFIG_APPLICOM=y CONFIG_SONYPI=y # # PCMCIA character devices # CONFIG_SYNCLINK_CS=y CONFIG_CARDMAN_4000=y CONFIG_CARDMAN_4040=y CONFIG_SCR24X=y CONFIG_IPWIRELESS=y # end of PCMCIA character devices CONFIG_MWAVE=y CONFIG_SCx200_GPIO=y CONFIG_PC8736x_GPIO=y CONFIG_NSC_GPIO=y CONFIG_DEVMEM=y CONFIG_NVRAM=y CONFIG_DEVPORT=y CONFIG_HPET=y CONFIG_HPET_MMAP=y CONFIG_HPET_MMAP_DEFAULT=y CONFIG_HANGCHECK_TIMER=y CONFIG_TCG_TPM=y CONFIG_HW_RANDOM_TPM=y CONFIG_TCG_TIS_CORE=y CONFIG_TCG_TIS=y CONFIG_TCG_TIS_SPI=y CONFIG_TCG_TIS_SPI_CR50=y CONFIG_TCG_TIS_I2C=y CONFIG_TCG_TIS_I2C_CR50=y CONFIG_TCG_TIS_I2C_ATMEL=y CONFIG_TCG_TIS_I2C_INFINEON=y CONFIG_TCG_TIS_I2C_NUVOTON=y CONFIG_TCG_NSC=y CONFIG_TCG_ATMEL=y CONFIG_TCG_INFINEON=y CONFIG_TCG_CRB=y CONFIG_TCG_VTPM_PROXY=y CONFIG_TCG_TIS_ST33ZP24=y CONFIG_TCG_TIS_ST33ZP24_I2C=y CONFIG_TCG_TIS_ST33ZP24_SPI=y CONFIG_TELCLOCK=y CONFIG_XILLYBUS_CLASS=y CONFIG_XILLYBUS=y CONFIG_XILLYBUS_PCIE=y CONFIG_XILLYBUS_OF=y CONFIG_XILLYUSB=y CONFIG_RANDOM_TRUST_CPU=y CONFIG_RANDOM_TRUST_BOOTLOADER=y # end of Character devices # # I2C support # CONFIG_I2C=y CONFIG_ACPI_I2C_OPREGION=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y # # Multiplexer I2C Chip support # CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_I2C_MUX_GPIO=y CONFIG_I2C_MUX_GPMUX=y CONFIG_I2C_MUX_LTC4306=y CONFIG_I2C_MUX_PCA9541=y CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_MUX_PINCTRL=y CONFIG_I2C_MUX_REG=y CONFIG_I2C_DEMUX_PINCTRL=y CONFIG_I2C_MUX_MLXCPLD=y # end of Multiplexer I2C Chip support CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_SMBUS=y CONFIG_I2C_ALGOBIT=y CONFIG_I2C_ALGOPCA=y # # I2C Hardware Bus support # # # PC SMBus host controller drivers # CONFIG_I2C_CCGX_UCSI=y CONFIG_I2C_ALI1535=y CONFIG_I2C_ALI1563=y CONFIG_I2C_ALI15X3=y CONFIG_I2C_AMD756=y CONFIG_I2C_AMD756_S4882=y CONFIG_I2C_AMD8111=y CONFIG_I2C_AMD_MP2=y CONFIG_I2C_I801=y CONFIG_I2C_ISCH=y CONFIG_I2C_ISMT=y CONFIG_I2C_PIIX4=y CONFIG_I2C_CHT_WC=y CONFIG_I2C_NFORCE2=y CONFIG_I2C_NFORCE2_S4985=y CONFIG_I2C_NVIDIA_GPU=y CONFIG_I2C_SIS5595=y CONFIG_I2C_SIS630=y CONFIG_I2C_SIS96X=y CONFIG_I2C_VIA=y CONFIG_I2C_VIAPRO=y # # ACPI drivers # CONFIG_I2C_SCMI=y # # I2C system bus drivers (mostly embedded / system-on-chip) # CONFIG_I2C_CBUS_GPIO=y CONFIG_I2C_DESIGNWARE_CORE=y CONFIG_I2C_DESIGNWARE_SLAVE=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_DESIGNWARE_AMDPSP=y CONFIG_I2C_DESIGNWARE_BAYTRAIL=y CONFIG_I2C_DESIGNWARE_PCI=y CONFIG_I2C_EG20T=y CONFIG_I2C_EMEV2=y CONFIG_I2C_GPIO=y CONFIG_I2C_GPIO_FAULT_INJECTOR=y CONFIG_I2C_KEMPLD=y CONFIG_I2C_OCORES=y CONFIG_I2C_PCA_PLATFORM=y CONFIG_I2C_PXA=y CONFIG_I2C_PXA_PCI=y CONFIG_I2C_RK3X=y CONFIG_I2C_SIMTEC=y CONFIG_I2C_XILINX=y # # External I2C/SMBus adapter drivers # CONFIG_I2C_DIOLAN_U2C=y CONFIG_I2C_DLN2=y CONFIG_I2C_CP2615=y CONFIG_I2C_PARPORT=y CONFIG_I2C_PCI1XXXX=y CONFIG_I2C_ROBOTFUZZ_OSIF=y CONFIG_I2C_TAOS_EVM=y CONFIG_I2C_TINY_USB=y CONFIG_I2C_VIPERBOARD=y # # Other I2C/SMBus bus drivers # CONFIG_I2C_PCA_ISA=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SCx200_ACB=y CONFIG_I2C_FSI=y CONFIG_I2C_VIRTIO=y # end of I2C Hardware Bus support CONFIG_I2C_STUB=m CONFIG_I2C_SLAVE=y CONFIG_I2C_SLAVE_EEPROM=y CONFIG_I2C_SLAVE_TESTUNIT=y CONFIG_I2C_DEBUG_CORE=y CONFIG_I2C_DEBUG_ALGO=y CONFIG_I2C_DEBUG_BUS=y # end of I2C support CONFIG_I3C=y CONFIG_CDNS_I3C_MASTER=y CONFIG_DW_I3C_MASTER=y CONFIG_SVC_I3C_MASTER=y CONFIG_MIPI_I3C_HCI=y CONFIG_SPI=y CONFIG_SPI_DEBUG=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y # # SPI Master Controller Drivers # CONFIG_SPI_ALTERA=y CONFIG_SPI_ALTERA_CORE=y CONFIG_SPI_ALTERA_DFL=y CONFIG_SPI_AXI_SPI_ENGINE=y CONFIG_SPI_BITBANG=y CONFIG_SPI_BUTTERFLY=y CONFIG_SPI_CADENCE=y CONFIG_SPI_CADENCE_QUADSPI=y CONFIG_SPI_CADENCE_XSPI=y CONFIG_SPI_DESIGNWARE=y CONFIG_SPI_DW_DMA=y CONFIG_SPI_DW_PCI=y CONFIG_SPI_DW_MMIO=y CONFIG_SPI_DLN2=y CONFIG_SPI_FSI=y CONFIG_SPI_NXP_FLEXSPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_INTEL=y CONFIG_SPI_INTEL_PCI=y CONFIG_SPI_INTEL_PLATFORM=y CONFIG_SPI_LM70_LLP=y CONFIG_SPI_FSL_LIB=y CONFIG_SPI_FSL_SPI=y CONFIG_SPI_MICROCHIP_CORE=y CONFIG_SPI_MICROCHIP_CORE_QSPI=y CONFIG_SPI_LANTIQ_SSC=y CONFIG_SPI_OC_TINY=y CONFIG_SPI_PXA2XX=y CONFIG_SPI_PXA2XX_PCI=y CONFIG_SPI_ROCKCHIP=y CONFIG_SPI_SC18IS602=y CONFIG_SPI_SIFIVE=y CONFIG_SPI_MXIC=y CONFIG_SPI_TOPCLIFF_PCH=y CONFIG_SPI_XCOMM=y CONFIG_SPI_XILINX=y CONFIG_SPI_ZYNQMP_GQSPI=y CONFIG_SPI_AMD=y # # SPI Multiplexer support # CONFIG_SPI_MUX=y # # SPI Protocol Masters # CONFIG_SPI_SPIDEV=y CONFIG_SPI_LOOPBACK_TEST=m CONFIG_SPI_TLE62X0=y CONFIG_SPI_SLAVE=y CONFIG_SPI_SLAVE_TIME=y CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y CONFIG_SPI_DYNAMIC=y CONFIG_SPMI=y CONFIG_SPMI_HISI3670=y CONFIG_HSI=y CONFIG_HSI_BOARDINFO=y # # HSI controllers # # # HSI clients # CONFIG_HSI_CHAR=y CONFIG_PPS=y CONFIG_PPS_DEBUG=y # # PPS clients support # CONFIG_PPS_CLIENT_KTIMER=y CONFIG_PPS_CLIENT_LDISC=y CONFIG_PPS_CLIENT_PARPORT=y CONFIG_PPS_CLIENT_GPIO=y # # PPS generators support # # # PTP clock support # CONFIG_PTP_1588_CLOCK=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_DP83640_PHY=y CONFIG_PTP_1588_CLOCK_INES=y CONFIG_PTP_1588_CLOCK_PCH=y CONFIG_PTP_1588_CLOCK_KVM=y CONFIG_PTP_1588_CLOCK_IDT82P33=y CONFIG_PTP_1588_CLOCK_IDTCM=y CONFIG_PTP_1588_CLOCK_VMW=y CONFIG_PTP_1588_CLOCK_OCP=y # end of PTP clock support CONFIG_PINCTRL=y CONFIG_GENERIC_PINCTRL_GROUPS=y CONFIG_PINMUX=y CONFIG_GENERIC_PINMUX_FUNCTIONS=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y CONFIG_DEBUG_PINCTRL=y CONFIG_PINCTRL_AMD=y CONFIG_PINCTRL_AS3722=y CONFIG_PINCTRL_AXP209=y CONFIG_PINCTRL_CY8C95X0=y CONFIG_PINCTRL_DA9062=y CONFIG_PINCTRL_EQUILIBRIUM=y CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_MCP23S08_I2C=y CONFIG_PINCTRL_MCP23S08_SPI=y CONFIG_PINCTRL_MCP23S08=y CONFIG_PINCTRL_MICROCHIP_SGPIO=y CONFIG_PINCTRL_OCELOT=y CONFIG_PINCTRL_PALMAS=y CONFIG_PINCTRL_RK805=y CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_STMFX=y CONFIG_PINCTRL_SX150X=y CONFIG_PINCTRL_LOCHNAGAR=y CONFIG_PINCTRL_MADERA=y CONFIG_PINCTRL_CS47L15=y CONFIG_PINCTRL_CS47L35=y CONFIG_PINCTRL_CS47L85=y CONFIG_PINCTRL_CS47L90=y CONFIG_PINCTRL_CS47L92=y CONFIG_PINCTRL_CS48L32=y # # Intel pinctrl drivers # CONFIG_PINCTRL_BAYTRAIL=y CONFIG_PINCTRL_CHERRYVIEW=y CONFIG_PINCTRL_LYNXPOINT=y CONFIG_PINCTRL_MERRIFIELD=y CONFIG_PINCTRL_INTEL=y CONFIG_PINCTRL_ALDERLAKE=y CONFIG_PINCTRL_BROXTON=y CONFIG_PINCTRL_CANNONLAKE=y CONFIG_PINCTRL_CEDARFORK=y CONFIG_PINCTRL_DENVERTON=y CONFIG_PINCTRL_ELKHARTLAKE=y CONFIG_PINCTRL_EMMITSBURG=y CONFIG_PINCTRL_GEMINILAKE=y CONFIG_PINCTRL_ICELAKE=y CONFIG_PINCTRL_JASPERLAKE=y CONFIG_PINCTRL_LAKEFIELD=y CONFIG_PINCTRL_LEWISBURG=y CONFIG_PINCTRL_METEORLAKE=y CONFIG_PINCTRL_SUNRISEPOINT=y CONFIG_PINCTRL_TIGERLAKE=y # end of Intel pinctrl drivers # # Renesas pinctrl drivers # # end of Renesas pinctrl drivers CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIO_ACPI=y CONFIG_GPIOLIB_IRQCHIP=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y CONFIG_GPIO_MAX730X=y # # Memory mapped GPIO drivers # CONFIG_GPIO_74XX_MMIO=y CONFIG_GPIO_ALTERA=y CONFIG_GPIO_AMDPT=y CONFIG_GPIO_CADENCE=y CONFIG_GPIO_DWAPB=y CONFIG_GPIO_EXAR=y CONFIG_GPIO_FTGPIO010=y CONFIG_GPIO_GENERIC_PLATFORM=y CONFIG_GPIO_GRGPIO=y CONFIG_GPIO_HLWD=y CONFIG_GPIO_ICH=y CONFIG_GPIO_LOGICVC=y CONFIG_GPIO_MB86S7X=y CONFIG_GPIO_MENZ127=y CONFIG_GPIO_SIFIVE=y CONFIG_GPIO_SIOX=y # CONFIG_GPIO_STA2X11 is not set CONFIG_GPIO_SYSCON=y CONFIG_GPIO_VX855=y CONFIG_GPIO_WCD934X=y CONFIG_GPIO_XILINX=y CONFIG_GPIO_AMD_FCH=y # end of Memory mapped GPIO drivers # # Port-mapped I/O GPIO drivers # CONFIG_GPIO_I8255=y CONFIG_GPIO_104_DIO_48E=y CONFIG_GPIO_104_IDIO_16=y CONFIG_GPIO_104_IDI_48=y CONFIG_GPIO_F7188X=y CONFIG_GPIO_GPIO_MM=y CONFIG_GPIO_IT87=y CONFIG_GPIO_SCH=y CONFIG_GPIO_SCH311X=y CONFIG_GPIO_WINBOND=y CONFIG_GPIO_WS16C48=y # end of Port-mapped I/O GPIO drivers # # I2C GPIO expanders # CONFIG_GPIO_ADNP=y CONFIG_GPIO_GW_PLD=y CONFIG_GPIO_MAX7300=y CONFIG_GPIO_MAX732X=y CONFIG_GPIO_MAX732X_IRQ=y CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_PCA9570=y CONFIG_GPIO_PCF857X=y CONFIG_GPIO_TPIC2810=y # end of I2C GPIO expanders # # MFD GPIO expanders # CONFIG_GPIO_ADP5520=y CONFIG_GPIO_ARIZONA=y CONFIG_GPIO_BD71815=y CONFIG_GPIO_BD71828=y CONFIG_GPIO_BD9571MWV=y CONFIG_GPIO_CRYSTAL_COVE=y CONFIG_GPIO_CS5535=y CONFIG_GPIO_DA9052=y CONFIG_GPIO_DA9055=y CONFIG_GPIO_DLN2=y CONFIG_GPIO_JANZ_TTL=y CONFIG_GPIO_KEMPLD=y CONFIG_GPIO_LP3943=y CONFIG_GPIO_LP873X=y CONFIG_GPIO_LP87565=y CONFIG_GPIO_MADERA=y CONFIG_GPIO_MAX77620=y CONFIG_GPIO_MAX77650=y CONFIG_GPIO_PALMAS=y CONFIG_GPIO_RC5T583=y CONFIG_GPIO_STMPE=y CONFIG_GPIO_TC3589X=y CONFIG_GPIO_TIMBERDALE=y CONFIG_GPIO_TPS65086=y CONFIG_GPIO_TPS65218=y CONFIG_GPIO_TPS6586X=y CONFIG_GPIO_TPS65910=y CONFIG_GPIO_TPS65912=y CONFIG_GPIO_TPS68470=y CONFIG_GPIO_TQMX86=y CONFIG_GPIO_TWL4030=y CONFIG_GPIO_TWL6040=y CONFIG_GPIO_UCB1400=y CONFIG_GPIO_WHISKEY_COVE=y CONFIG_GPIO_WM831X=y CONFIG_GPIO_WM8350=y CONFIG_GPIO_WM8994=y # end of MFD GPIO expanders # # PCI GPIO expanders # CONFIG_GPIO_AMD8111=y CONFIG_GPIO_MERRIFIELD=y CONFIG_GPIO_ML_IOH=y CONFIG_GPIO_PCH=y CONFIG_GPIO_PCI_IDIO_16=y CONFIG_GPIO_PCIE_IDIO_24=y CONFIG_GPIO_RDC321X=y CONFIG_GPIO_SODAVILLE=y # end of PCI GPIO expanders # # SPI GPIO expanders # CONFIG_GPIO_74X164=y CONFIG_GPIO_MAX3191X=y CONFIG_GPIO_MAX7301=y CONFIG_GPIO_MC33880=y CONFIG_GPIO_PISOSR=y CONFIG_GPIO_XRA1403=y CONFIG_GPIO_MOXTET=y # end of SPI GPIO expanders # # USB GPIO expanders # CONFIG_GPIO_VIPERBOARD=y # end of USB GPIO expanders # # Virtual GPIO drivers # CONFIG_GPIO_AGGREGATOR=y CONFIG_GPIO_MOCKUP=y CONFIG_GPIO_VIRTIO=y CONFIG_GPIO_SIM=y # end of Virtual GPIO drivers CONFIG_W1=y CONFIG_W1_CON=y # # 1-wire Bus Masters # CONFIG_W1_MASTER_MATROX=y CONFIG_W1_MASTER_DS2490=y CONFIG_W1_MASTER_DS2482=y CONFIG_W1_MASTER_DS1WM=y CONFIG_W1_MASTER_GPIO=y CONFIG_W1_MASTER_SGI=y # end of 1-wire Bus Masters # # 1-wire Slaves # CONFIG_W1_SLAVE_THERM=y CONFIG_W1_SLAVE_SMEM=y CONFIG_W1_SLAVE_DS2405=y CONFIG_W1_SLAVE_DS2408=y CONFIG_W1_SLAVE_DS2408_READBACK=y CONFIG_W1_SLAVE_DS2413=y CONFIG_W1_SLAVE_DS2406=y CONFIG_W1_SLAVE_DS2423=y CONFIG_W1_SLAVE_DS2805=y CONFIG_W1_SLAVE_DS2430=y CONFIG_W1_SLAVE_DS2431=y CONFIG_W1_SLAVE_DS2433=y CONFIG_W1_SLAVE_DS2433_CRC=y CONFIG_W1_SLAVE_DS2438=y CONFIG_W1_SLAVE_DS250X=y CONFIG_W1_SLAVE_DS2780=y CONFIG_W1_SLAVE_DS2781=y CONFIG_W1_SLAVE_DS28E04=y CONFIG_W1_SLAVE_DS28E17=y # end of 1-wire Slaves CONFIG_POWER_RESET=y CONFIG_POWER_RESET_AS3722=y CONFIG_POWER_RESET_ATC260X=y CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_POWER_RESET_LTC2952=y CONFIG_POWER_RESET_MT6323=y CONFIG_POWER_RESET_REGULATOR=y CONFIG_POWER_RESET_RESTART=y CONFIG_POWER_RESET_TPS65086=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_REBOOT_MODE=y CONFIG_SYSCON_REBOOT_MODE=y CONFIG_NVMEM_REBOOT_MODE=y CONFIG_POWER_SUPPLY=y CONFIG_POWER_SUPPLY_DEBUG=y CONFIG_POWER_SUPPLY_HWMON=y CONFIG_PDA_POWER=y CONFIG_GENERIC_ADC_BATTERY=y CONFIG_IP5XXX_POWER=y CONFIG_MAX8925_POWER=y CONFIG_WM831X_BACKUP=y CONFIG_WM831X_POWER=y CONFIG_WM8350_POWER=y CONFIG_TEST_POWER=y CONFIG_BATTERY_88PM860X=y CONFIG_CHARGER_ADP5061=y CONFIG_BATTERY_ACT8945A=y CONFIG_BATTERY_CPCAP=y CONFIG_BATTERY_CW2015=y CONFIG_BATTERY_DS2760=y CONFIG_BATTERY_DS2780=y CONFIG_BATTERY_DS2781=y CONFIG_BATTERY_DS2782=y CONFIG_BATTERY_OLPC=y CONFIG_BATTERY_SAMSUNG_SDI=y CONFIG_BATTERY_WM97XX=y CONFIG_BATTERY_SBS=y CONFIG_CHARGER_SBS=y CONFIG_MANAGER_SBS=y CONFIG_BATTERY_BQ27XXX=y CONFIG_BATTERY_BQ27XXX_I2C=y CONFIG_BATTERY_BQ27XXX_HDQ=y CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM=y CONFIG_BATTERY_DA9030=y CONFIG_BATTERY_DA9052=y CONFIG_CHARGER_DA9150=y CONFIG_BATTERY_DA9150=y CONFIG_CHARGER_AXP20X=y CONFIG_BATTERY_AXP20X=y CONFIG_AXP20X_POWER=y CONFIG_AXP288_CHARGER=y CONFIG_AXP288_FUEL_GAUGE=y CONFIG_BATTERY_MAX17040=y CONFIG_BATTERY_MAX17042=y CONFIG_BATTERY_MAX1721X=y CONFIG_BATTERY_TWL4030_MADC=y CONFIG_CHARGER_88PM860X=y CONFIG_CHARGER_PCF50633=y CONFIG_BATTERY_RX51=y CONFIG_CHARGER_ISP1704=y CONFIG_CHARGER_MAX8903=y CONFIG_CHARGER_TWL4030=y CONFIG_CHARGER_LP8727=y CONFIG_CHARGER_LP8788=y CONFIG_CHARGER_GPIO=y CONFIG_CHARGER_MANAGER=y CONFIG_CHARGER_LT3651=y CONFIG_CHARGER_LTC4162L=y CONFIG_CHARGER_MAX14577=y CONFIG_CHARGER_DETECTOR_MAX14656=y CONFIG_CHARGER_MAX77650=y CONFIG_CHARGER_MAX77693=y CONFIG_CHARGER_MAX77976=y CONFIG_CHARGER_MAX8997=y CONFIG_CHARGER_MAX8998=y CONFIG_CHARGER_MP2629=y CONFIG_CHARGER_MT6360=y CONFIG_CHARGER_MT6370=y CONFIG_CHARGER_BQ2415X=y CONFIG_CHARGER_BQ24190=y CONFIG_CHARGER_BQ24257=y CONFIG_CHARGER_BQ24735=y CONFIG_CHARGER_BQ2515X=y CONFIG_CHARGER_BQ25890=y CONFIG_CHARGER_BQ25980=y CONFIG_CHARGER_BQ256XX=y CONFIG_CHARGER_RK817=y CONFIG_CHARGER_SMB347=y CONFIG_CHARGER_TPS65090=y CONFIG_CHARGER_TPS65217=y CONFIG_BATTERY_GAUGE_LTC2941=y CONFIG_BATTERY_GOLDFISH=y CONFIG_BATTERY_RT5033=y CONFIG_CHARGER_RT9455=y CONFIG_CHARGER_CROS_USBPD=y CONFIG_CHARGER_CROS_PCHG=y CONFIG_CHARGER_UCS1002=y CONFIG_CHARGER_BD99954=y CONFIG_CHARGER_WILCO=y CONFIG_RN5T618_POWER=y CONFIG_BATTERY_SURFACE=y CONFIG_CHARGER_SURFACE=y CONFIG_BATTERY_UG3105=y CONFIG_HWMON=y CONFIG_HWMON_VID=y CONFIG_HWMON_DEBUG_CHIP=y # # Native drivers # CONFIG_SENSORS_ABITUGURU=y CONFIG_SENSORS_ABITUGURU3=y CONFIG_SENSORS_AD7314=y CONFIG_SENSORS_AD7414=y CONFIG_SENSORS_AD7418=y CONFIG_SENSORS_ADM1025=y CONFIG_SENSORS_ADM1026=y CONFIG_SENSORS_ADM1029=y CONFIG_SENSORS_ADM1031=y CONFIG_SENSORS_ADM1177=y CONFIG_SENSORS_ADM9240=y CONFIG_SENSORS_ADT7X10=y CONFIG_SENSORS_ADT7310=y CONFIG_SENSORS_ADT7410=y CONFIG_SENSORS_ADT7411=y CONFIG_SENSORS_ADT7462=y CONFIG_SENSORS_ADT7470=y CONFIG_SENSORS_ADT7475=y CONFIG_SENSORS_AHT10=y CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=y CONFIG_SENSORS_AS370=y CONFIG_SENSORS_ASC7621=y CONFIG_SENSORS_AXI_FAN_CONTROL=y CONFIG_SENSORS_K8TEMP=y CONFIG_SENSORS_K10TEMP=y CONFIG_SENSORS_FAM15H_POWER=y CONFIG_SENSORS_APPLESMC=y CONFIG_SENSORS_ASB100=y CONFIG_SENSORS_ATXP1=y CONFIG_SENSORS_CORSAIR_CPRO=y CONFIG_SENSORS_CORSAIR_PSU=y CONFIG_SENSORS_DRIVETEMP=y CONFIG_SENSORS_DS620=y CONFIG_SENSORS_DS1621=y CONFIG_SENSORS_DELL_SMM=y CONFIG_I8K=y CONFIG_SENSORS_DA9052_ADC=y CONFIG_SENSORS_DA9055=y CONFIG_SENSORS_I5K_AMB=y CONFIG_SENSORS_F71805F=y CONFIG_SENSORS_F71882FG=y CONFIG_SENSORS_F75375S=y CONFIG_SENSORS_GSC=y CONFIG_SENSORS_MC13783_ADC=y CONFIG_SENSORS_FSCHMD=y CONFIG_SENSORS_FTSTEUTATES=y CONFIG_SENSORS_GL518SM=y CONFIG_SENSORS_GL520SM=y CONFIG_SENSORS_G760A=y CONFIG_SENSORS_G762=y CONFIG_SENSORS_GPIO_FAN=y CONFIG_SENSORS_HIH6130=y CONFIG_SENSORS_IBMAEM=y CONFIG_SENSORS_IBMPEX=y CONFIG_SENSORS_IIO_HWMON=y CONFIG_SENSORS_I5500=y CONFIG_SENSORS_CORETEMP=y CONFIG_SENSORS_IT87=y CONFIG_SENSORS_JC42=y CONFIG_SENSORS_POWR1220=y CONFIG_SENSORS_LINEAGE=y CONFIG_SENSORS_LOCHNAGAR=y CONFIG_SENSORS_LTC2945=y CONFIG_SENSORS_LTC2947=y CONFIG_SENSORS_LTC2947_I2C=y CONFIG_SENSORS_LTC2947_SPI=y CONFIG_SENSORS_LTC2990=y CONFIG_SENSORS_LTC2992=y CONFIG_SENSORS_LTC4151=y CONFIG_SENSORS_LTC4215=y CONFIG_SENSORS_LTC4222=y CONFIG_SENSORS_LTC4245=y CONFIG_SENSORS_LTC4260=y CONFIG_SENSORS_LTC4261=y CONFIG_SENSORS_MAX1111=y CONFIG_SENSORS_MAX127=y CONFIG_SENSORS_MAX16065=y CONFIG_SENSORS_MAX1619=y CONFIG_SENSORS_MAX1668=y CONFIG_SENSORS_MAX197=y CONFIG_SENSORS_MAX31722=y CONFIG_SENSORS_MAX31730=y CONFIG_SENSORS_MAX31760=y CONFIG_SENSORS_MAX6620=y CONFIG_SENSORS_MAX6621=y CONFIG_SENSORS_MAX6639=y CONFIG_SENSORS_MAX6650=y CONFIG_SENSORS_MAX6697=y CONFIG_SENSORS_MAX31790=y CONFIG_SENSORS_MCP3021=y CONFIG_SENSORS_MLXREG_FAN=y CONFIG_SENSORS_TC654=y CONFIG_SENSORS_TPS23861=y CONFIG_SENSORS_MENF21BMC_HWMON=y CONFIG_SENSORS_MR75203=y CONFIG_SENSORS_ADCXX=y CONFIG_SENSORS_LM63=y CONFIG_SENSORS_LM70=y CONFIG_SENSORS_LM73=y CONFIG_SENSORS_LM75=y CONFIG_SENSORS_LM77=y CONFIG_SENSORS_LM78=y CONFIG_SENSORS_LM80=y CONFIG_SENSORS_LM83=y CONFIG_SENSORS_LM85=y CONFIG_SENSORS_LM87=y CONFIG_SENSORS_LM90=y CONFIG_SENSORS_LM92=y CONFIG_SENSORS_LM93=y CONFIG_SENSORS_LM95234=y CONFIG_SENSORS_LM95241=y CONFIG_SENSORS_LM95245=y CONFIG_SENSORS_PC87360=y CONFIG_SENSORS_PC87427=y CONFIG_SENSORS_NTC_THERMISTOR=y CONFIG_SENSORS_NCT6683=y CONFIG_SENSORS_NCT6775_CORE=y CONFIG_SENSORS_NCT6775=y CONFIG_SENSORS_NCT6775_I2C=y CONFIG_SENSORS_NCT7802=y CONFIG_SENSORS_NCT7904=y CONFIG_SENSORS_NPCM7XX=y CONFIG_SENSORS_NZXT_KRAKEN2=y CONFIG_SENSORS_NZXT_SMART2=y CONFIG_SENSORS_PCF8591=y CONFIG_SENSORS_PECI_CPUTEMP=y CONFIG_SENSORS_PECI_DIMMTEMP=y CONFIG_SENSORS_PECI=y CONFIG_PMBUS=y CONFIG_SENSORS_PMBUS=y CONFIG_SENSORS_ADM1266=y CONFIG_SENSORS_ADM1275=y CONFIG_SENSORS_BEL_PFE=y CONFIG_SENSORS_BPA_RS600=y CONFIG_SENSORS_DELTA_AHE50DC_FAN=y CONFIG_SENSORS_FSP_3Y=y CONFIG_SENSORS_IBM_CFFPS=y CONFIG_SENSORS_DPS920AB=y CONFIG_SENSORS_INSPUR_IPSPS=y CONFIG_SENSORS_IR35221=y CONFIG_SENSORS_IR36021=y CONFIG_SENSORS_IR38064=y CONFIG_SENSORS_IR38064_REGULATOR=y CONFIG_SENSORS_IRPS5401=y CONFIG_SENSORS_ISL68137=y CONFIG_SENSORS_LM25066=y CONFIG_SENSORS_LM25066_REGULATOR=y CONFIG_SENSORS_LT7182S=y CONFIG_SENSORS_LTC2978=y CONFIG_SENSORS_LTC2978_REGULATOR=y CONFIG_SENSORS_LTC3815=y CONFIG_SENSORS_MAX15301=y CONFIG_SENSORS_MAX16064=y CONFIG_SENSORS_MAX16601=y CONFIG_SENSORS_MAX20730=y CONFIG_SENSORS_MAX20751=y CONFIG_SENSORS_MAX31785=y CONFIG_SENSORS_MAX34440=y CONFIG_SENSORS_MAX8688=y CONFIG_SENSORS_MP2888=y CONFIG_SENSORS_MP2975=y CONFIG_SENSORS_MP5023=y CONFIG_SENSORS_PIM4328=y CONFIG_SENSORS_PLI1209BC=y CONFIG_SENSORS_PLI1209BC_REGULATOR=y CONFIG_SENSORS_PM6764TR=y CONFIG_SENSORS_PXE1610=y CONFIG_SENSORS_Q54SJ108A2=y CONFIG_SENSORS_STPDDC60=y CONFIG_SENSORS_TPS40422=y CONFIG_SENSORS_TPS53679=y CONFIG_SENSORS_TPS546D24=y CONFIG_SENSORS_UCD9000=y CONFIG_SENSORS_UCD9200=y CONFIG_SENSORS_XDPE152=y CONFIG_SENSORS_XDPE122=y CONFIG_SENSORS_XDPE122_REGULATOR=y CONFIG_SENSORS_ZL6100=y CONFIG_SENSORS_PWM_FAN=y CONFIG_SENSORS_SBTSI=y CONFIG_SENSORS_SBRMI=y CONFIG_SENSORS_SHT15=y CONFIG_SENSORS_SHT21=y CONFIG_SENSORS_SHT3x=y CONFIG_SENSORS_SHT4x=y CONFIG_SENSORS_SHTC1=y CONFIG_SENSORS_SIS5595=y CONFIG_SENSORS_SY7636A=y CONFIG_SENSORS_DME1737=y CONFIG_SENSORS_EMC1403=y CONFIG_SENSORS_EMC2103=y CONFIG_SENSORS_EMC2305=y CONFIG_SENSORS_EMC6W201=y CONFIG_SENSORS_SMSC47M1=y CONFIG_SENSORS_SMSC47M192=y CONFIG_SENSORS_SMSC47B397=y CONFIG_SENSORS_SCH56XX_COMMON=y CONFIG_SENSORS_SCH5627=y CONFIG_SENSORS_SCH5636=y CONFIG_SENSORS_STTS751=y CONFIG_SENSORS_SMM665=y CONFIG_SENSORS_ADC128D818=y CONFIG_SENSORS_ADS7828=y CONFIG_SENSORS_ADS7871=y CONFIG_SENSORS_AMC6821=y CONFIG_SENSORS_INA209=y CONFIG_SENSORS_INA2XX=y CONFIG_SENSORS_INA238=y CONFIG_SENSORS_INA3221=y CONFIG_SENSORS_TC74=y CONFIG_SENSORS_THMC50=y CONFIG_SENSORS_TMP102=y CONFIG_SENSORS_TMP103=y CONFIG_SENSORS_TMP108=y CONFIG_SENSORS_TMP401=y CONFIG_SENSORS_TMP421=y CONFIG_SENSORS_TMP464=y CONFIG_SENSORS_TMP513=y CONFIG_SENSORS_VIA_CPUTEMP=y CONFIG_SENSORS_VIA686A=y CONFIG_SENSORS_VT1211=y CONFIG_SENSORS_VT8231=y CONFIG_SENSORS_W83773G=y CONFIG_SENSORS_W83781D=y CONFIG_SENSORS_W83791D=y CONFIG_SENSORS_W83792D=y CONFIG_SENSORS_W83793=y CONFIG_SENSORS_W83795=y CONFIG_SENSORS_W83795_FANCTRL=y CONFIG_SENSORS_W83L785TS=y CONFIG_SENSORS_W83L786NG=y CONFIG_SENSORS_W83627HF=y CONFIG_SENSORS_W83627EHF=y CONFIG_SENSORS_WM831X=y CONFIG_SENSORS_WM8350=y CONFIG_SENSORS_XGENE=y CONFIG_SENSORS_INTEL_M10_BMC_HWMON=y # # ACPI drivers # CONFIG_SENSORS_ACPI_POWER=y CONFIG_SENSORS_ATK0110=y CONFIG_SENSORS_ASUS_WMI=y CONFIG_SENSORS_ASUS_EC=y CONFIG_THERMAL=y CONFIG_THERMAL_NETLINK=y CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set # CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set CONFIG_THERMAL_GOV_FAIR_SHARE=y CONFIG_THERMAL_GOV_STEP_WISE=y CONFIG_THERMAL_GOV_BANG_BANG=y CONFIG_THERMAL_GOV_USER_SPACE=y CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y CONFIG_CPU_FREQ_THERMAL=y CONFIG_CPU_IDLE_THERMAL=y CONFIG_DEVFREQ_THERMAL=y CONFIG_THERMAL_EMULATION=y CONFIG_THERMAL_MMIO=y CONFIG_MAX77620_THERMAL=y CONFIG_DA9062_THERMAL=y # # Intel thermal drivers # CONFIG_INTEL_POWERCLAMP=y CONFIG_X86_THERMAL_VECTOR=y CONFIG_X86_PKG_TEMP_THERMAL=y CONFIG_INTEL_SOC_DTS_IOSF_CORE=y CONFIG_INTEL_SOC_DTS_THERMAL=y CONFIG_INTEL_QUARK_DTS_THERMAL=y # # ACPI INT340X thermal drivers # # end of ACPI INT340X thermal drivers CONFIG_INTEL_BXT_PMIC_THERMAL=y CONFIG_INTEL_PCH_THERMAL=y CONFIG_INTEL_TCC_COOLING=y CONFIG_INTEL_MENLOW=y CONFIG_INTEL_HFI_THERMAL=y # end of Intel thermal drivers # CONFIG_TI_SOC_THERMAL is not set CONFIG_GENERIC_ADC_THERMAL=y CONFIG_WATCHDOG=y CONFIG_WATCHDOG_CORE=y CONFIG_WATCHDOG_NOWAYOUT=y CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 CONFIG_WATCHDOG_SYSFS=y CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT=y # # Watchdog Pretimeout Governors # CONFIG_WATCHDOG_PRETIMEOUT_GOV=y CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=y CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y # CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y # # Watchdog Device Drivers # CONFIG_SOFT_WATCHDOG=y CONFIG_SOFT_WATCHDOG_PRETIMEOUT=y CONFIG_BD957XMUF_WATCHDOG=y CONFIG_DA9052_WATCHDOG=y CONFIG_DA9055_WATCHDOG=y CONFIG_DA9063_WATCHDOG=y CONFIG_DA9062_WATCHDOG=y CONFIG_GPIO_WATCHDOG=y CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y CONFIG_MENF21BMC_WATCHDOG=y CONFIG_MENZ069_WATCHDOG=y CONFIG_WDAT_WDT=y CONFIG_WM831X_WATCHDOG=y CONFIG_WM8350_WATCHDOG=y CONFIG_XILINX_WATCHDOG=y CONFIG_ZIIRAVE_WATCHDOG=y CONFIG_RAVE_SP_WATCHDOG=y CONFIG_MLX_WDT=y CONFIG_CADENCE_WATCHDOG=y CONFIG_DW_WATCHDOG=y CONFIG_RN5T618_WATCHDOG=y CONFIG_TWL4030_WATCHDOG=y CONFIG_MAX63XX_WATCHDOG=y CONFIG_MAX77620_WATCHDOG=y CONFIG_RETU_WATCHDOG=y CONFIG_STPMIC1_WATCHDOG=y CONFIG_ACQUIRE_WDT=y CONFIG_ADVANTECH_WDT=y CONFIG_ALIM1535_WDT=y CONFIG_ALIM7101_WDT=y CONFIG_EBC_C384_WDT=y CONFIG_EXAR_WDT=y CONFIG_F71808E_WDT=y CONFIG_SP5100_TCO=y CONFIG_GEODE_WDT=y CONFIG_SBC_FITPC2_WATCHDOG=y CONFIG_EUROTECH_WDT=y CONFIG_IB700_WDT=y CONFIG_IBMASR=y CONFIG_WAFER_WDT=y CONFIG_I6300ESB_WDT=y CONFIG_IE6XX_WDT=y CONFIG_INTEL_MID_WATCHDOG=y CONFIG_ITCO_WDT=y CONFIG_ITCO_VENDOR_SUPPORT=y CONFIG_IT8712F_WDT=y CONFIG_IT87_WDT=y CONFIG_HP_WATCHDOG=y CONFIG_HPWDT_NMI_DECODING=y CONFIG_KEMPLD_WDT=y CONFIG_SC1200_WDT=y CONFIG_SCx200_WDT=y CONFIG_PC87413_WDT=y CONFIG_NV_TCO=y CONFIG_RDC321X_WDT=y CONFIG_60XX_WDT=y CONFIG_SBC8360_WDT=y CONFIG_SBC7240_WDT=y CONFIG_CPU5_WDT=y CONFIG_SMSC_SCH311X_WDT=y CONFIG_SMSC37B787_WDT=y CONFIG_TQMX86_WDT=y CONFIG_VIA_WDT=y CONFIG_W83627HF_WDT=y CONFIG_W83877F_WDT=y CONFIG_W83977F_WDT=y CONFIG_MACHZ_WDT=y CONFIG_SBC_EPX_C3_WATCHDOG=y CONFIG_INTEL_MEI_WDT=y CONFIG_NI903X_WDT=y CONFIG_NIC7018_WDT=y CONFIG_SIEMENS_SIMATIC_IPC_WDT=y CONFIG_MEN_A21_WDT=y # # ISA-based Watchdog Cards # CONFIG_PCWATCHDOG=y CONFIG_MIXCOMWD=y CONFIG_WDT=y # # PCI-based Watchdog Cards # CONFIG_PCIPCWATCHDOG=y CONFIG_WDTPCI=y # # USB-based Watchdog Cards # CONFIG_USBPCWATCHDOG=y CONFIG_SSB_POSSIBLE=y CONFIG_SSB=y CONFIG_SSB_SPROM=y CONFIG_SSB_BLOCKIO=y CONFIG_SSB_PCIHOST_POSSIBLE=y CONFIG_SSB_PCIHOST=y CONFIG_SSB_B43_PCI_BRIDGE=y CONFIG_SSB_PCMCIAHOST_POSSIBLE=y CONFIG_SSB_PCMCIAHOST=y CONFIG_SSB_SDIOHOST_POSSIBLE=y CONFIG_SSB_SDIOHOST=y CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y CONFIG_SSB_DRIVER_PCICORE=y CONFIG_SSB_DRIVER_GPIO=y CONFIG_BCMA_POSSIBLE=y CONFIG_BCMA=y CONFIG_BCMA_BLOCKIO=y CONFIG_BCMA_HOST_PCI_POSSIBLE=y CONFIG_BCMA_HOST_PCI=y CONFIG_BCMA_HOST_SOC=y CONFIG_BCMA_DRIVER_PCI=y CONFIG_BCMA_SFLASH=y CONFIG_BCMA_DRIVER_GMAC_CMN=y CONFIG_BCMA_DRIVER_GPIO=y CONFIG_BCMA_DEBUG=y # # Multifunction device drivers # CONFIG_MFD_CORE=y CONFIG_MFD_CS5535=y CONFIG_MFD_ACT8945A=y CONFIG_MFD_AS3711=y CONFIG_MFD_AS3722=y CONFIG_PMIC_ADP5520=y CONFIG_MFD_AAT2870_CORE=y CONFIG_MFD_ATMEL_FLEXCOM=y CONFIG_MFD_ATMEL_HLCDC=y CONFIG_MFD_BCM590XX=y CONFIG_MFD_BD9571MWV=y CONFIG_MFD_AXP20X=y CONFIG_MFD_AXP20X_I2C=y CONFIG_MFD_CROS_EC_DEV=y CONFIG_MFD_MADERA=y CONFIG_MFD_MADERA_I2C=y CONFIG_MFD_MADERA_SPI=y CONFIG_MFD_CS47L15=y CONFIG_MFD_CS47L35=y CONFIG_MFD_CS47L85=y CONFIG_MFD_CS47L90=y CONFIG_MFD_CS47L92=y CONFIG_MFD_CS48L32=y CONFIG_PMIC_DA903X=y CONFIG_PMIC_DA9052=y CONFIG_MFD_DA9052_SPI=y CONFIG_MFD_DA9052_I2C=y CONFIG_MFD_DA9055=y CONFIG_MFD_DA9062=y CONFIG_MFD_DA9063=y CONFIG_MFD_DA9150=y CONFIG_MFD_DLN2=y CONFIG_MFD_GATEWORKS_GSC=y CONFIG_MFD_MC13XXX=y CONFIG_MFD_MC13XXX_SPI=y CONFIG_MFD_MC13XXX_I2C=y CONFIG_MFD_MP2629=y CONFIG_MFD_HI6421_PMIC=y CONFIG_MFD_HI6421_SPMI=y CONFIG_HTC_PASIC3=y # CONFIG_HTC_I2CPLD is not set CONFIG_MFD_INTEL_QUARK_I2C_GPIO=y CONFIG_LPC_ICH=y CONFIG_LPC_SCH=y CONFIG_INTEL_SOC_PMIC=y CONFIG_INTEL_SOC_PMIC_BXTWC=y CONFIG_INTEL_SOC_PMIC_CHTWC=y CONFIG_INTEL_SOC_PMIC_CHTDC_TI=y CONFIG_INTEL_SOC_PMIC_MRFLD=y CONFIG_MFD_INTEL_LPSS=y CONFIG_MFD_INTEL_LPSS_ACPI=y CONFIG_MFD_INTEL_LPSS_PCI=y CONFIG_MFD_INTEL_PMC_BXT=y CONFIG_MFD_IQS62X=y CONFIG_MFD_JANZ_CMODIO=y CONFIG_MFD_KEMPLD=y CONFIG_MFD_88PM800=y CONFIG_MFD_88PM805=y CONFIG_MFD_88PM860X=y CONFIG_MFD_MAX14577=y CONFIG_MFD_MAX77620=y CONFIG_MFD_MAX77650=y CONFIG_MFD_MAX77686=y CONFIG_MFD_MAX77693=y CONFIG_MFD_MAX77714=y CONFIG_MFD_MAX77843=y CONFIG_MFD_MAX8907=y CONFIG_MFD_MAX8925=y CONFIG_MFD_MAX8997=y CONFIG_MFD_MAX8998=y CONFIG_MFD_MT6360=y CONFIG_MFD_MT6370=y CONFIG_MFD_MT6397=y CONFIG_MFD_MENF21BMC=y CONFIG_MFD_OCELOT=y CONFIG_EZX_PCAP=y CONFIG_MFD_CPCAP=y CONFIG_MFD_VIPERBOARD=y CONFIG_MFD_NTXEC=y CONFIG_MFD_RETU=y CONFIG_MFD_PCF50633=y CONFIG_PCF50633_ADC=y CONFIG_PCF50633_GPIO=y CONFIG_UCB1400_CORE=y CONFIG_MFD_SY7636A=y CONFIG_MFD_RDC321X=y CONFIG_MFD_RT4831=y CONFIG_MFD_RT5033=y CONFIG_MFD_RT5120=y CONFIG_MFD_RC5T583=y CONFIG_MFD_RK808=y CONFIG_MFD_RN5T618=y CONFIG_MFD_SEC_CORE=y CONFIG_MFD_SI476X_CORE=y CONFIG_MFD_SIMPLE_MFD_I2C=y CONFIG_MFD_SM501=y CONFIG_MFD_SM501_GPIO=y CONFIG_MFD_SKY81452=y CONFIG_MFD_STMPE=y # # STMicroelectronics STMPE Interface Drivers # CONFIG_STMPE_I2C=y CONFIG_STMPE_SPI=y # end of STMicroelectronics STMPE Interface Drivers CONFIG_MFD_STA2X11=y CONFIG_MFD_SYSCON=y CONFIG_MFD_TI_AM335X_TSCADC=y CONFIG_MFD_LP3943=y CONFIG_MFD_LP8788=y CONFIG_MFD_TI_LMU=y CONFIG_MFD_PALMAS=y CONFIG_TPS6105X=y CONFIG_TPS65010=y CONFIG_TPS6507X=y CONFIG_MFD_TPS65086=y CONFIG_MFD_TPS65090=y CONFIG_MFD_TPS65217=y CONFIG_MFD_TI_LP873X=y CONFIG_MFD_TI_LP87565=y CONFIG_MFD_TPS65218=y CONFIG_MFD_TPS6586X=y CONFIG_MFD_TPS65910=y CONFIG_MFD_TPS65912=y CONFIG_MFD_TPS65912_I2C=y CONFIG_MFD_TPS65912_SPI=y CONFIG_TWL4030_CORE=y CONFIG_MFD_TWL4030_AUDIO=y CONFIG_TWL6040_CORE=y CONFIG_MFD_WL1273_CORE=y CONFIG_MFD_LM3533=y CONFIG_MFD_TIMBERDALE=y CONFIG_MFD_TC3589X=y CONFIG_MFD_TQMX86=y CONFIG_MFD_VX855=y CONFIG_MFD_LOCHNAGAR=y CONFIG_MFD_ARIZONA=y CONFIG_MFD_ARIZONA_I2C=y CONFIG_MFD_ARIZONA_SPI=y CONFIG_MFD_CS47L24=y CONFIG_MFD_WM5102=y CONFIG_MFD_WM5110=y CONFIG_MFD_WM8997=y CONFIG_MFD_WM8998=y CONFIG_MFD_WM8400=y CONFIG_MFD_WM831X=y CONFIG_MFD_WM831X_I2C=y CONFIG_MFD_WM831X_SPI=y CONFIG_MFD_WM8350=y CONFIG_MFD_WM8350_I2C=y CONFIG_MFD_WM8994=y CONFIG_MFD_ROHM_BD718XX=y CONFIG_MFD_ROHM_BD71828=y CONFIG_MFD_ROHM_BD957XMUF=y CONFIG_MFD_STPMIC1=y CONFIG_MFD_STMFX=y CONFIG_MFD_WCD934X=y CONFIG_MFD_ATC260X=y CONFIG_MFD_ATC260X_I2C=y CONFIG_MFD_QCOM_PM8008=y CONFIG_RAVE_SP_CORE=y CONFIG_MFD_INTEL_M10_BMC=y CONFIG_MFD_RSMU_I2C=y CONFIG_MFD_RSMU_SPI=y # end of Multifunction device drivers CONFIG_REGULATOR=y CONFIG_REGULATOR_DEBUG=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_VIRTUAL_CONSUMER=y CONFIG_REGULATOR_USERSPACE_CONSUMER=y CONFIG_REGULATOR_88PG86X=y CONFIG_REGULATOR_88PM800=y CONFIG_REGULATOR_88PM8607=y CONFIG_REGULATOR_ACT8865=y CONFIG_REGULATOR_ACT8945A=y CONFIG_REGULATOR_AD5398=y CONFIG_REGULATOR_AAT2870=y CONFIG_REGULATOR_ARIZONA_LDO1=y CONFIG_REGULATOR_ARIZONA_MICSUPP=y CONFIG_REGULATOR_AS3711=y CONFIG_REGULATOR_AS3722=y CONFIG_REGULATOR_ATC260X=y CONFIG_REGULATOR_AXP20X=y CONFIG_REGULATOR_BCM590XX=y CONFIG_REGULATOR_BD71815=y CONFIG_REGULATOR_BD71828=y CONFIG_REGULATOR_BD718XX=y CONFIG_REGULATOR_BD9571MWV=y CONFIG_REGULATOR_BD957XMUF=y CONFIG_REGULATOR_CPCAP=y CONFIG_REGULATOR_CROS_EC=y CONFIG_REGULATOR_DA903X=y CONFIG_REGULATOR_DA9052=y CONFIG_REGULATOR_DA9055=y CONFIG_REGULATOR_DA9062=y CONFIG_REGULATOR_DA9063=y CONFIG_REGULATOR_DA9121=y CONFIG_REGULATOR_DA9210=y CONFIG_REGULATOR_DA9211=y CONFIG_REGULATOR_FAN53555=y CONFIG_REGULATOR_FAN53880=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_HI6421=y CONFIG_REGULATOR_HI6421V530=y CONFIG_REGULATOR_HI6421V600=y CONFIG_REGULATOR_ISL9305=y CONFIG_REGULATOR_ISL6271A=y CONFIG_REGULATOR_LM363X=y CONFIG_REGULATOR_LOCHNAGAR=y CONFIG_REGULATOR_LP3971=y CONFIG_REGULATOR_LP3972=y CONFIG_REGULATOR_LP872X=y CONFIG_REGULATOR_LP873X=y CONFIG_REGULATOR_LP8755=y CONFIG_REGULATOR_LP87565=y CONFIG_REGULATOR_LP8788=y CONFIG_REGULATOR_LTC3589=y CONFIG_REGULATOR_LTC3676=y CONFIG_REGULATOR_MAX14577=y CONFIG_REGULATOR_MAX1586=y CONFIG_REGULATOR_MAX77620=y CONFIG_REGULATOR_MAX77650=y CONFIG_REGULATOR_MAX8649=y CONFIG_REGULATOR_MAX8660=y CONFIG_REGULATOR_MAX8893=y CONFIG_REGULATOR_MAX8907=y CONFIG_REGULATOR_MAX8925=y CONFIG_REGULATOR_MAX8952=y CONFIG_REGULATOR_MAX8973=y CONFIG_REGULATOR_MAX8997=y CONFIG_REGULATOR_MAX8998=y CONFIG_REGULATOR_MAX20086=y CONFIG_REGULATOR_MAX77686=y CONFIG_REGULATOR_MAX77693=y CONFIG_REGULATOR_MAX77802=y CONFIG_REGULATOR_MAX77826=y CONFIG_REGULATOR_MC13XXX_CORE=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y CONFIG_REGULATOR_MCP16502=y CONFIG_REGULATOR_MP5416=y CONFIG_REGULATOR_MP8859=y CONFIG_REGULATOR_MP886X=y CONFIG_REGULATOR_MPQ7920=y CONFIG_REGULATOR_MT6311=y CONFIG_REGULATOR_MT6315=y CONFIG_REGULATOR_MT6323=y CONFIG_REGULATOR_MT6331=y CONFIG_REGULATOR_MT6332=y CONFIG_REGULATOR_MT6358=y CONFIG_REGULATOR_MT6359=y CONFIG_REGULATOR_MT6360=y CONFIG_REGULATOR_MT6370=y CONFIG_REGULATOR_MT6397=y CONFIG_REGULATOR_PALMAS=y CONFIG_REGULATOR_PCA9450=y CONFIG_REGULATOR_PCAP=y CONFIG_REGULATOR_PCF50633=y CONFIG_REGULATOR_PF8X00=y CONFIG_REGULATOR_PFUZE100=y CONFIG_REGULATOR_PV88060=y CONFIG_REGULATOR_PV88080=y CONFIG_REGULATOR_PV88090=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_REGULATOR_QCOM_USB_VBUS=y CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=y CONFIG_REGULATOR_RC5T583=y CONFIG_REGULATOR_RK808=y CONFIG_REGULATOR_RN5T618=y CONFIG_REGULATOR_ROHM=y CONFIG_REGULATOR_RT4801=y CONFIG_REGULATOR_RT4831=y CONFIG_REGULATOR_RT5033=y CONFIG_REGULATOR_RT5120=y CONFIG_REGULATOR_RT5190A=y CONFIG_REGULATOR_RT5759=y CONFIG_REGULATOR_RT6160=y CONFIG_REGULATOR_RT6245=y CONFIG_REGULATOR_RTQ2134=y CONFIG_REGULATOR_RTMV20=y CONFIG_REGULATOR_RTQ6752=y CONFIG_REGULATOR_S2MPA01=y CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_SKY81452=y CONFIG_REGULATOR_SLG51000=y CONFIG_REGULATOR_STPMIC1=y CONFIG_REGULATOR_SY7636A=y CONFIG_REGULATOR_SY8106A=y CONFIG_REGULATOR_SY8824X=y CONFIG_REGULATOR_SY8827N=y CONFIG_REGULATOR_TPS51632=y CONFIG_REGULATOR_TPS6105X=y CONFIG_REGULATOR_TPS62360=y CONFIG_REGULATOR_TPS6286X=y CONFIG_REGULATOR_TPS65023=y CONFIG_REGULATOR_TPS6507X=y CONFIG_REGULATOR_TPS65086=y CONFIG_REGULATOR_TPS65090=y CONFIG_REGULATOR_TPS65132=y CONFIG_REGULATOR_TPS65217=y CONFIG_REGULATOR_TPS65218=y CONFIG_REGULATOR_TPS6524X=y CONFIG_REGULATOR_TPS6586X=y CONFIG_REGULATOR_TPS65910=y CONFIG_REGULATOR_TPS65912=y CONFIG_REGULATOR_TPS68470=y CONFIG_REGULATOR_TWL4030=y CONFIG_REGULATOR_VCTRL=y CONFIG_REGULATOR_WM831X=y CONFIG_REGULATOR_WM8350=y CONFIG_REGULATOR_WM8400=y CONFIG_REGULATOR_WM8994=y CONFIG_REGULATOR_QCOM_LABIBB=y CONFIG_RC_CORE=y CONFIG_BPF_LIRC_MODE2=y CONFIG_LIRC=y CONFIG_RC_MAP=y CONFIG_RC_DECODERS=y CONFIG_IR_IMON_DECODER=y CONFIG_IR_JVC_DECODER=y CONFIG_IR_MCE_KBD_DECODER=y CONFIG_IR_NEC_DECODER=y CONFIG_IR_RC5_DECODER=y CONFIG_IR_RC6_DECODER=y CONFIG_IR_RCMM_DECODER=y CONFIG_IR_SANYO_DECODER=y CONFIG_IR_SHARP_DECODER=y CONFIG_IR_SONY_DECODER=y CONFIG_IR_XMP_DECODER=y CONFIG_RC_DEVICES=y CONFIG_IR_ENE=y CONFIG_IR_FINTEK=y CONFIG_IR_GPIO_CIR=y CONFIG_IR_GPIO_TX=y CONFIG_IR_HIX5HD2=y CONFIG_IR_IGORPLUGUSB=y CONFIG_IR_IGUANA=y CONFIG_IR_IMON=y CONFIG_IR_IMON_RAW=y CONFIG_IR_ITE_CIR=y CONFIG_IR_MCEUSB=y CONFIG_IR_NUVOTON=y CONFIG_IR_PWM_TX=y CONFIG_IR_REDRAT3=y CONFIG_IR_SERIAL=y CONFIG_IR_SERIAL_TRANSMITTER=y CONFIG_IR_SPI=y CONFIG_IR_STREAMZAP=y CONFIG_IR_TOY=y CONFIG_IR_TTUSBIR=y CONFIG_IR_WINBOND_CIR=y CONFIG_RC_ATI_REMOTE=y CONFIG_RC_LOOPBACK=y CONFIG_RC_XBOX_DVD=y CONFIG_CEC_CORE=y CONFIG_CEC_NOTIFIER=y CONFIG_CEC_PIN=y # # CEC support # CONFIG_MEDIA_CEC_RC=y CONFIG_CEC_PIN_ERROR_INJ=y CONFIG_MEDIA_CEC_SUPPORT=y CONFIG_CEC_CH7322=y CONFIG_CEC_CROS_EC=y CONFIG_CEC_GPIO=y CONFIG_CEC_SECO=y CONFIG_CEC_SECO_RC=y CONFIG_USB_PULSE8_CEC=y CONFIG_USB_RAINSHADOW_CEC=y # end of CEC support CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_SUPPORT_FILTER=y CONFIG_MEDIA_SUBDRV_AUTOSELECT=y # # Media device types # CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_ANALOG_TV_SUPPORT=y CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y CONFIG_MEDIA_RADIO_SUPPORT=y CONFIG_MEDIA_SDR_SUPPORT=y CONFIG_MEDIA_PLATFORM_SUPPORT=y CONFIG_MEDIA_TEST_SUPPORT=y # end of Media device types CONFIG_VIDEO_DEV=y CONFIG_MEDIA_CONTROLLER=y CONFIG_DVB_CORE=y # # Video4Linux options # CONFIG_VIDEO_V4L2_I2C=y CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_ADV_DEBUG=y CONFIG_VIDEO_FIXED_MINOR_RANGES=y CONFIG_VIDEO_TUNER=y CONFIG_V4L2_MEM2MEM_DEV=y CONFIG_V4L2_FLASH_LED_CLASS=y CONFIG_V4L2_FWNODE=y CONFIG_V4L2_ASYNC=y CONFIG_VIDEOBUF_GEN=y CONFIG_VIDEOBUF_DMA_SG=y CONFIG_VIDEOBUF_VMALLOC=y # end of Video4Linux options # # Media controller options # CONFIG_MEDIA_CONTROLLER_DVB=y CONFIG_MEDIA_CONTROLLER_REQUEST_API=y # end of Media controller options # # Digital TV options # CONFIG_DVB_MMAP=y CONFIG_DVB_NET=y CONFIG_DVB_MAX_ADAPTERS=16 CONFIG_DVB_DYNAMIC_MINORS=y CONFIG_DVB_DEMUX_SECTION_LOSS_LOG=y CONFIG_DVB_ULE_DEBUG=y # end of Digital TV options # # Media drivers # # # Drivers filtered as selected at 'Filter media drivers' # # # Media drivers # CONFIG_MEDIA_USB_SUPPORT=y # # Webcam devices # CONFIG_USB_GSPCA=y CONFIG_USB_GSPCA_BENQ=y CONFIG_USB_GSPCA_CONEX=y CONFIG_USB_GSPCA_CPIA1=y CONFIG_USB_GSPCA_DTCS033=y CONFIG_USB_GSPCA_ETOMS=y CONFIG_USB_GSPCA_FINEPIX=y CONFIG_USB_GSPCA_JEILINJ=y CONFIG_USB_GSPCA_JL2005BCD=y CONFIG_USB_GSPCA_KINECT=y CONFIG_USB_GSPCA_KONICA=y CONFIG_USB_GSPCA_MARS=y CONFIG_USB_GSPCA_MR97310A=y CONFIG_USB_GSPCA_NW80X=y CONFIG_USB_GSPCA_OV519=y CONFIG_USB_GSPCA_OV534=y CONFIG_USB_GSPCA_OV534_9=y CONFIG_USB_GSPCA_PAC207=y CONFIG_USB_GSPCA_PAC7302=y CONFIG_USB_GSPCA_PAC7311=y CONFIG_USB_GSPCA_SE401=y CONFIG_USB_GSPCA_SN9C2028=y CONFIG_USB_GSPCA_SN9C20X=y CONFIG_USB_GSPCA_SONIXB=y CONFIG_USB_GSPCA_SONIXJ=y CONFIG_USB_GSPCA_SPCA1528=y CONFIG_USB_GSPCA_SPCA500=y CONFIG_USB_GSPCA_SPCA501=y CONFIG_USB_GSPCA_SPCA505=y CONFIG_USB_GSPCA_SPCA506=y CONFIG_USB_GSPCA_SPCA508=y CONFIG_USB_GSPCA_SPCA561=y CONFIG_USB_GSPCA_SQ905=y CONFIG_USB_GSPCA_SQ905C=y CONFIG_USB_GSPCA_SQ930X=y CONFIG_USB_GSPCA_STK014=y CONFIG_USB_GSPCA_STK1135=y CONFIG_USB_GSPCA_STV0680=y CONFIG_USB_GSPCA_SUNPLUS=y CONFIG_USB_GSPCA_T613=y CONFIG_USB_GSPCA_TOPRO=y CONFIG_USB_GSPCA_TOUPTEK=y CONFIG_USB_GSPCA_TV8532=y CONFIG_USB_GSPCA_VC032X=y CONFIG_USB_GSPCA_VICAM=y CONFIG_USB_GSPCA_XIRLINK_CIT=y CONFIG_USB_GSPCA_ZC3XX=y CONFIG_USB_GL860=y CONFIG_USB_M5602=y CONFIG_USB_STV06XX=y CONFIG_USB_PWC=y CONFIG_USB_PWC_DEBUG=y CONFIG_USB_PWC_INPUT_EVDEV=y CONFIG_USB_S2255=y CONFIG_VIDEO_USBTV=y CONFIG_USB_VIDEO_CLASS=y CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y # # Analog TV USB devices # CONFIG_VIDEO_GO7007=y CONFIG_VIDEO_GO7007_USB=y CONFIG_VIDEO_GO7007_LOADER=y CONFIG_VIDEO_GO7007_USB_S2250_BOARD=y CONFIG_VIDEO_HDPVR=y CONFIG_VIDEO_PVRUSB2=y CONFIG_VIDEO_PVRUSB2_SYSFS=y CONFIG_VIDEO_PVRUSB2_DVB=y CONFIG_VIDEO_PVRUSB2_DEBUGIFC=y CONFIG_VIDEO_STK1160_COMMON=y CONFIG_VIDEO_STK1160=y # # Analog/digital TV USB devices # CONFIG_VIDEO_AU0828=y CONFIG_VIDEO_AU0828_V4L2=y CONFIG_VIDEO_AU0828_RC=y CONFIG_VIDEO_CX231XX=y CONFIG_VIDEO_CX231XX_RC=y CONFIG_VIDEO_CX231XX_ALSA=y CONFIG_VIDEO_CX231XX_DVB=y # # Digital TV USB devices # CONFIG_DVB_AS102=y CONFIG_DVB_B2C2_FLEXCOP_USB=y CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG=y CONFIG_DVB_USB_V2=y CONFIG_DVB_USB_AF9015=y CONFIG_DVB_USB_AF9035=y CONFIG_DVB_USB_ANYSEE=y CONFIG_DVB_USB_AU6610=y CONFIG_DVB_USB_AZ6007=y CONFIG_DVB_USB_CE6230=y CONFIG_DVB_USB_DVBSKY=y CONFIG_DVB_USB_EC168=y CONFIG_DVB_USB_GL861=y CONFIG_DVB_USB_LME2510=y CONFIG_DVB_USB_MXL111SF=y CONFIG_DVB_USB_RTL28XXU=y CONFIG_DVB_USB_ZD1301=y CONFIG_DVB_USB=y CONFIG_DVB_USB_DEBUG=y CONFIG_DVB_USB_A800=y CONFIG_DVB_USB_AF9005=y CONFIG_DVB_USB_AF9005_REMOTE=y CONFIG_DVB_USB_AZ6027=y CONFIG_DVB_USB_CINERGY_T2=y CONFIG_DVB_USB_CXUSB=y CONFIG_DVB_USB_CXUSB_ANALOG=y CONFIG_DVB_USB_DIB0700=y CONFIG_DVB_USB_DIB3000MC=y CONFIG_DVB_USB_DIBUSB_MB=y CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y CONFIG_DVB_USB_DIBUSB_MC=y CONFIG_DVB_USB_DIGITV=y CONFIG_DVB_USB_DTT200U=y CONFIG_DVB_USB_DTV5100=y CONFIG_DVB_USB_DW2102=y CONFIG_DVB_USB_GP8PSK=y CONFIG_DVB_USB_M920X=y CONFIG_DVB_USB_NOVA_T_USB2=y CONFIG_DVB_USB_OPERA1=y CONFIG_DVB_USB_PCTV452E=y CONFIG_DVB_USB_TECHNISAT_USB2=y CONFIG_DVB_USB_TTUSB2=y CONFIG_DVB_USB_UMT_010=y CONFIG_DVB_USB_VP702X=y CONFIG_DVB_USB_VP7045=y CONFIG_SMS_USB_DRV=y CONFIG_DVB_TTUSB_BUDGET=y CONFIG_DVB_TTUSB_DEC=y # # Webcam, TV (analog/digital) USB devices # CONFIG_VIDEO_EM28XX=y CONFIG_VIDEO_EM28XX_V4L2=y CONFIG_VIDEO_EM28XX_ALSA=y CONFIG_VIDEO_EM28XX_DVB=y CONFIG_VIDEO_EM28XX_RC=y # # Software defined radio USB devices # CONFIG_USB_AIRSPY=y CONFIG_USB_HACKRF=y CONFIG_USB_MSI2500=y CONFIG_MEDIA_PCI_SUPPORT=y # # Media capture support # CONFIG_VIDEO_SOLO6X10=y CONFIG_STA2X11_VIP=y CONFIG_VIDEO_TW5864=y CONFIG_VIDEO_TW68=y CONFIG_VIDEO_TW686X=y CONFIG_VIDEO_ZORAN=y CONFIG_VIDEO_ZORAN_DC30=y CONFIG_VIDEO_ZORAN_ZR36060=y CONFIG_VIDEO_ZORAN_BUZ=y CONFIG_VIDEO_ZORAN_DC10=y CONFIG_VIDEO_ZORAN_LML33=y CONFIG_VIDEO_ZORAN_LML33R10=y CONFIG_VIDEO_ZORAN_AVS6EYES=y # # Media capture/analog TV support # CONFIG_VIDEO_DT3155=y CONFIG_VIDEO_IVTV=y CONFIG_VIDEO_IVTV_ALSA=y CONFIG_VIDEO_FB_IVTV=y CONFIG_VIDEO_FB_IVTV_FORCE_PAT=y # # Media capture/analog/hybrid TV support # CONFIG_VIDEO_BT848=y CONFIG_DVB_BT8XX=y CONFIG_VIDEO_CX18=y CONFIG_VIDEO_CX18_ALSA=y CONFIG_VIDEO_CX23885=y CONFIG_MEDIA_ALTERA_CI=y CONFIG_VIDEO_CX25821=y CONFIG_VIDEO_CX25821_ALSA=y CONFIG_VIDEO_CX88=y CONFIG_VIDEO_CX88_ALSA=y CONFIG_VIDEO_CX88_BLACKBIRD=y CONFIG_VIDEO_CX88_DVB=y CONFIG_VIDEO_CX88_ENABLE_VP3054=y CONFIG_VIDEO_CX88_VP3054=y CONFIG_VIDEO_CX88_MPEG=y CONFIG_VIDEO_SAA7134=y CONFIG_VIDEO_SAA7134_ALSA=y CONFIG_VIDEO_SAA7134_RC=y CONFIG_VIDEO_SAA7134_DVB=y CONFIG_VIDEO_SAA7134_GO7007=y CONFIG_VIDEO_SAA7164=y # # Media digital TV PCI Adapters # CONFIG_DVB_B2C2_FLEXCOP_PCI=y CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG=y CONFIG_DVB_DDBRIDGE=y CONFIG_DVB_DDBRIDGE_MSIENABLE=y CONFIG_DVB_DM1105=y CONFIG_MANTIS_CORE=y CONFIG_DVB_MANTIS=y CONFIG_DVB_HOPPER=y CONFIG_DVB_NETUP_UNIDVB=y CONFIG_DVB_NGENE=y CONFIG_DVB_PLUTO2=y CONFIG_DVB_PT1=y CONFIG_DVB_PT3=y CONFIG_DVB_SMIPCIE=y CONFIG_VIDEO_PCI_SKELETON=y CONFIG_VIDEO_IPU3_CIO2=y CONFIG_CIO2_BRIDGE=y CONFIG_RADIO_ADAPTERS=y CONFIG_RADIO_MAXIRADIO=y CONFIG_RADIO_SAA7706H=y CONFIG_RADIO_SHARK=y CONFIG_RADIO_SHARK2=y CONFIG_RADIO_SI4713=y CONFIG_RADIO_SI476X=y CONFIG_RADIO_TEA575X=y CONFIG_RADIO_TEA5764=y CONFIG_RADIO_TEA5764_XTAL=y CONFIG_RADIO_TEF6862=y CONFIG_RADIO_TIMBERDALE=y CONFIG_RADIO_WL1273=y CONFIG_USB_DSBR=y CONFIG_USB_KEENE=y CONFIG_USB_MA901=y CONFIG_USB_MR800=y CONFIG_USB_RAREMONO=y CONFIG_RADIO_SI470X=y CONFIG_USB_SI470X=y CONFIG_I2C_SI470X=y CONFIG_USB_SI4713=y CONFIG_PLATFORM_SI4713=y CONFIG_I2C_SI4713=y CONFIG_RADIO_WL128X=y CONFIG_V4L_RADIO_ISA_DRIVERS=y CONFIG_RADIO_AZTECH=y CONFIG_RADIO_AZTECH_PORT=350 CONFIG_RADIO_CADET=y CONFIG_RADIO_GEMTEK=y CONFIG_RADIO_GEMTEK_PORT=34c CONFIG_RADIO_GEMTEK_PROBE=y CONFIG_RADIO_ISA=y CONFIG_RADIO_MIROPCM20=y CONFIG_RADIO_RTRACK=y CONFIG_RADIO_RTRACK2=y CONFIG_RADIO_RTRACK2_PORT=30c CONFIG_RADIO_RTRACK_PORT=30f CONFIG_RADIO_SF16FMI=y CONFIG_RADIO_SF16FMR2=y CONFIG_RADIO_TERRATEC=y CONFIG_RADIO_TRUST=y CONFIG_RADIO_TRUST_PORT=350 CONFIG_RADIO_TYPHOON=y CONFIG_RADIO_TYPHOON_MUTEFREQ=87500 CONFIG_RADIO_TYPHOON_PORT=316 CONFIG_RADIO_ZOLTRIX=y CONFIG_RADIO_ZOLTRIX_PORT=20c CONFIG_MEDIA_PLATFORM_DRIVERS=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_SDR_PLATFORM_DRIVERS=y CONFIG_DVB_PLATFORM_DRIVERS=y CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y CONFIG_VIDEO_MUX=y # # Allegro DVT media platform drivers # # # Amlogic media platform drivers # # # Amphion drivers # # # Aspeed media platform drivers # CONFIG_VIDEO_ASPEED=y # # Atmel media platform drivers # # # Cadence media platform drivers # CONFIG_VIDEO_CADENCE_CSI2RX=y CONFIG_VIDEO_CADENCE_CSI2TX=y # # Chips&Media media platform drivers # # # Intel media platform drivers # # # Marvell media platform drivers # CONFIG_VIDEO_CAFE_CCIC=y # # Mediatek media platform drivers # # # NVidia media platform drivers # # # NXP media platform drivers # # # Qualcomm media platform drivers # # # Renesas media platform drivers # # # Rockchip media platform drivers # # # Samsung media platform drivers # # # STMicroelectronics media platform drivers # # # Sunxi media platform drivers # # # Texas Instruments drivers # # # Verisilicon media platform drivers # # # VIA media platform drivers # CONFIG_VIDEO_VIA_CAMERA=y # # Xilinx media platform drivers # CONFIG_VIDEO_XILINX=y CONFIG_VIDEO_XILINX_CSI2RXSS=y CONFIG_VIDEO_XILINX_TPG=y CONFIG_VIDEO_XILINX_VTC=y # # MMC/SDIO DVB adapters # CONFIG_SMS_SDIO_DRV=y CONFIG_V4L_TEST_DRIVERS=y CONFIG_VIDEO_VIM2M=y CONFIG_VIDEO_VICODEC=y CONFIG_VIDEO_VIMC=y CONFIG_VIDEO_VIVID=y CONFIG_VIDEO_VIVID_CEC=y CONFIG_VIDEO_VIVID_MAX_DEVS=64 CONFIG_DVB_TEST_DRIVERS=y CONFIG_DVB_VIDTV=y # # FireWire (IEEE 1394) Adapters # CONFIG_DVB_FIREDTV=y CONFIG_DVB_FIREDTV_INPUT=y CONFIG_MEDIA_COMMON_OPTIONS=y # # common driver options # CONFIG_CYPRESS_FIRMWARE=y CONFIG_TTPCI_EEPROM=y CONFIG_VIDEO_CX2341X=y CONFIG_VIDEO_TVEEPROM=y CONFIG_DVB_B2C2_FLEXCOP=y CONFIG_DVB_B2C2_FLEXCOP_DEBUG=y CONFIG_SMS_SIANO_MDTV=y CONFIG_SMS_SIANO_RC=y CONFIG_SMS_SIANO_DEBUGFS=y CONFIG_VIDEO_V4L2_TPG=y CONFIG_VIDEOBUF2_CORE=y CONFIG_VIDEOBUF2_V4L2=y CONFIG_VIDEOBUF2_MEMOPS=y CONFIG_VIDEOBUF2_DMA_CONTIG=y CONFIG_VIDEOBUF2_VMALLOC=y CONFIG_VIDEOBUF2_DMA_SG=y CONFIG_VIDEOBUF2_DVB=y # end of Media drivers # # Media ancillary drivers # CONFIG_MEDIA_ATTACH=y # # IR I2C driver auto-selected by 'Autoselect ancillary drivers' # CONFIG_VIDEO_IR_I2C=y # # Camera sensor devices # CONFIG_VIDEO_APTINA_PLL=y CONFIG_VIDEO_CCS_PLL=y CONFIG_VIDEO_AR0521=y CONFIG_VIDEO_HI556=y CONFIG_VIDEO_HI846=y CONFIG_VIDEO_HI847=y CONFIG_VIDEO_IMX208=y CONFIG_VIDEO_IMX214=y CONFIG_VIDEO_IMX219=y CONFIG_VIDEO_IMX258=y CONFIG_VIDEO_IMX274=y CONFIG_VIDEO_IMX290=y CONFIG_VIDEO_IMX319=y CONFIG_VIDEO_IMX334=y CONFIG_VIDEO_IMX335=y CONFIG_VIDEO_IMX355=y CONFIG_VIDEO_IMX412=y CONFIG_VIDEO_MAX9271_LIB=y CONFIG_VIDEO_MT9M001=y CONFIG_VIDEO_MT9M032=y CONFIG_VIDEO_MT9M111=y CONFIG_VIDEO_MT9P031=y CONFIG_VIDEO_MT9T001=y CONFIG_VIDEO_MT9T112=y CONFIG_VIDEO_MT9V011=y CONFIG_VIDEO_MT9V032=y CONFIG_VIDEO_MT9V111=y CONFIG_VIDEO_NOON010PC30=y CONFIG_VIDEO_OG01A1B=y CONFIG_VIDEO_OV02A10=y CONFIG_VIDEO_OV08D10=y CONFIG_VIDEO_OV13858=y CONFIG_VIDEO_OV13B10=y CONFIG_VIDEO_OV2640=y CONFIG_VIDEO_OV2659=y CONFIG_VIDEO_OV2680=y CONFIG_VIDEO_OV2685=y CONFIG_VIDEO_OV2740=y CONFIG_VIDEO_OV5640=y CONFIG_VIDEO_OV5645=y CONFIG_VIDEO_OV5647=y CONFIG_VIDEO_OV5648=y CONFIG_VIDEO_OV5670=y CONFIG_VIDEO_OV5675=y CONFIG_VIDEO_OV5693=y CONFIG_VIDEO_OV5695=y CONFIG_VIDEO_OV6650=y CONFIG_VIDEO_OV7251=y CONFIG_VIDEO_OV7640=y CONFIG_VIDEO_OV7670=y CONFIG_VIDEO_OV772X=y CONFIG_VIDEO_OV7740=y CONFIG_VIDEO_OV8856=y CONFIG_VIDEO_OV8865=y CONFIG_VIDEO_OV9282=y CONFIG_VIDEO_OV9640=y CONFIG_VIDEO_OV9650=y CONFIG_VIDEO_OV9734=y CONFIG_VIDEO_RDACM20=y CONFIG_VIDEO_RDACM21=y CONFIG_VIDEO_RJ54N1=y CONFIG_VIDEO_S5C73M3=y CONFIG_VIDEO_S5K4ECGX=y CONFIG_VIDEO_S5K5BAF=y CONFIG_VIDEO_S5K6A3=y CONFIG_VIDEO_S5K6AA=y CONFIG_VIDEO_SR030PC30=y CONFIG_VIDEO_VS6624=y CONFIG_VIDEO_CCS=y CONFIG_VIDEO_ET8EK8=y CONFIG_VIDEO_M5MOLS=y # end of Camera sensor devices # # Lens drivers # CONFIG_VIDEO_AD5820=y CONFIG_VIDEO_AK7375=y CONFIG_VIDEO_DW9714=y CONFIG_VIDEO_DW9768=y CONFIG_VIDEO_DW9807_VCM=y # end of Lens drivers # # Flash devices # CONFIG_VIDEO_ADP1653=y CONFIG_VIDEO_LM3560=y CONFIG_VIDEO_LM3646=y # end of Flash devices # # Audio decoders, processors and mixers # CONFIG_VIDEO_CS3308=y CONFIG_VIDEO_CS5345=y CONFIG_VIDEO_CS53L32A=y CONFIG_VIDEO_MSP3400=y CONFIG_VIDEO_SONY_BTF_MPX=y CONFIG_VIDEO_TDA1997X=y CONFIG_VIDEO_TDA7432=y CONFIG_VIDEO_TDA9840=y CONFIG_VIDEO_TEA6415C=y CONFIG_VIDEO_TEA6420=y CONFIG_VIDEO_TLV320AIC23B=y CONFIG_VIDEO_TVAUDIO=y CONFIG_VIDEO_UDA1342=y CONFIG_VIDEO_VP27SMPX=y CONFIG_VIDEO_WM8739=y CONFIG_VIDEO_WM8775=y # end of Audio decoders, processors and mixers # # RDS decoders # CONFIG_VIDEO_SAA6588=y # end of RDS decoders # # Video decoders # CONFIG_VIDEO_ADV7180=y CONFIG_VIDEO_ADV7183=y CONFIG_VIDEO_ADV748X=y CONFIG_VIDEO_ADV7604=y CONFIG_VIDEO_ADV7604_CEC=y CONFIG_VIDEO_ADV7842=y CONFIG_VIDEO_ADV7842_CEC=y CONFIG_VIDEO_BT819=y CONFIG_VIDEO_BT856=y CONFIG_VIDEO_BT866=y CONFIG_VIDEO_ISL7998X=y CONFIG_VIDEO_KS0127=y CONFIG_VIDEO_MAX9286=y CONFIG_VIDEO_ML86V7667=y CONFIG_VIDEO_SAA7110=y CONFIG_VIDEO_SAA711X=y CONFIG_VIDEO_TC358743=y CONFIG_VIDEO_TC358743_CEC=y CONFIG_VIDEO_TVP514X=y CONFIG_VIDEO_TVP5150=y CONFIG_VIDEO_TVP7002=y CONFIG_VIDEO_TW2804=y CONFIG_VIDEO_TW9903=y CONFIG_VIDEO_TW9906=y CONFIG_VIDEO_TW9910=y CONFIG_VIDEO_VPX3220=y # # Video and audio decoders # CONFIG_VIDEO_SAA717X=y CONFIG_VIDEO_CX25840=y # end of Video decoders # # Video encoders # CONFIG_VIDEO_AD9389B=y CONFIG_VIDEO_ADV7170=y CONFIG_VIDEO_ADV7175=y CONFIG_VIDEO_ADV7343=y CONFIG_VIDEO_ADV7393=y CONFIG_VIDEO_AK881X=y CONFIG_VIDEO_SAA7127=y CONFIG_VIDEO_SAA7185=y CONFIG_VIDEO_THS8200=y # end of Video encoders # # Video improvement chips # CONFIG_VIDEO_UPD64031A=y CONFIG_VIDEO_UPD64083=y # end of Video improvement chips # # Audio/Video compression chips # CONFIG_VIDEO_SAA6752HS=y # end of Audio/Video compression chips # # SDR tuner chips # CONFIG_SDR_MAX2175=y # end of SDR tuner chips # # Miscellaneous helper chips # CONFIG_VIDEO_I2C=y CONFIG_VIDEO_M52790=y CONFIG_VIDEO_ST_MIPID02=y CONFIG_VIDEO_THS7303=y # end of Miscellaneous helper chips # # Media SPI Adapters # CONFIG_CXD2880_SPI_DRV=y CONFIG_VIDEO_GS1662=y # end of Media SPI Adapters CONFIG_MEDIA_TUNER=y # # Customize TV tuners # CONFIG_MEDIA_TUNER_E4000=y CONFIG_MEDIA_TUNER_FC0011=y CONFIG_MEDIA_TUNER_FC0012=y CONFIG_MEDIA_TUNER_FC0013=y CONFIG_MEDIA_TUNER_FC2580=y CONFIG_MEDIA_TUNER_IT913X=y CONFIG_MEDIA_TUNER_M88RS6000T=y CONFIG_MEDIA_TUNER_MAX2165=y CONFIG_MEDIA_TUNER_MC44S803=y CONFIG_MEDIA_TUNER_MSI001=y CONFIG_MEDIA_TUNER_MT2060=y CONFIG_MEDIA_TUNER_MT2063=y CONFIG_MEDIA_TUNER_MT20XX=y CONFIG_MEDIA_TUNER_MT2131=y CONFIG_MEDIA_TUNER_MT2266=y CONFIG_MEDIA_TUNER_MXL301RF=y CONFIG_MEDIA_TUNER_MXL5005S=y CONFIG_MEDIA_TUNER_MXL5007T=y CONFIG_MEDIA_TUNER_QM1D1B0004=y CONFIG_MEDIA_TUNER_QM1D1C0042=y CONFIG_MEDIA_TUNER_QT1010=y CONFIG_MEDIA_TUNER_R820T=y CONFIG_MEDIA_TUNER_SI2157=y CONFIG_MEDIA_TUNER_SIMPLE=y CONFIG_MEDIA_TUNER_TDA18212=y CONFIG_MEDIA_TUNER_TDA18218=y CONFIG_MEDIA_TUNER_TDA18250=y CONFIG_MEDIA_TUNER_TDA18271=y CONFIG_MEDIA_TUNER_TDA827X=y CONFIG_MEDIA_TUNER_TDA8290=y CONFIG_MEDIA_TUNER_TDA9887=y CONFIG_MEDIA_TUNER_TEA5761=y CONFIG_MEDIA_TUNER_TEA5767=y CONFIG_MEDIA_TUNER_TUA9001=y CONFIG_MEDIA_TUNER_XC2028=y CONFIG_MEDIA_TUNER_XC4000=y CONFIG_MEDIA_TUNER_XC5000=y # end of Customize TV tuners # # Customise DVB Frontends # # # Multistandard (satellite) frontends # CONFIG_DVB_M88DS3103=y CONFIG_DVB_MXL5XX=y CONFIG_DVB_STB0899=y CONFIG_DVB_STB6100=y CONFIG_DVB_STV090x=y CONFIG_DVB_STV0910=y CONFIG_DVB_STV6110x=y CONFIG_DVB_STV6111=y # # Multistandard (cable + terrestrial) frontends # CONFIG_DVB_DRXK=y CONFIG_DVB_MN88472=y CONFIG_DVB_MN88473=y CONFIG_DVB_SI2165=y CONFIG_DVB_TDA18271C2DD=y # # DVB-S (satellite) frontends # CONFIG_DVB_CX24110=y CONFIG_DVB_CX24116=y CONFIG_DVB_CX24117=y CONFIG_DVB_CX24120=y CONFIG_DVB_CX24123=y CONFIG_DVB_DS3000=y CONFIG_DVB_MB86A16=y CONFIG_DVB_MT312=y CONFIG_DVB_S5H1420=y CONFIG_DVB_SI21XX=y CONFIG_DVB_STB6000=y CONFIG_DVB_STV0288=y CONFIG_DVB_STV0299=y CONFIG_DVB_STV0900=y CONFIG_DVB_STV6110=y CONFIG_DVB_TDA10071=y CONFIG_DVB_TDA10086=y CONFIG_DVB_TDA8083=y CONFIG_DVB_TDA8261=y CONFIG_DVB_TDA826X=y CONFIG_DVB_TS2020=y CONFIG_DVB_TUA6100=y CONFIG_DVB_TUNER_CX24113=y CONFIG_DVB_TUNER_ITD1000=y CONFIG_DVB_VES1X93=y CONFIG_DVB_ZL10036=y CONFIG_DVB_ZL10039=y # # DVB-T (terrestrial) frontends # CONFIG_DVB_AF9013=y CONFIG_DVB_AS102_FE=y CONFIG_DVB_CX22700=y CONFIG_DVB_CX22702=y CONFIG_DVB_CXD2820R=y CONFIG_DVB_CXD2841ER=y CONFIG_DVB_DIB3000MB=y CONFIG_DVB_DIB3000MC=y CONFIG_DVB_DIB7000M=y CONFIG_DVB_DIB7000P=y CONFIG_DVB_DIB9000=y CONFIG_DVB_DRXD=y CONFIG_DVB_EC100=y CONFIG_DVB_GP8PSK_FE=y CONFIG_DVB_L64781=y CONFIG_DVB_MT352=y CONFIG_DVB_NXT6000=y CONFIG_DVB_RTL2830=y CONFIG_DVB_RTL2832=y CONFIG_DVB_RTL2832_SDR=y CONFIG_DVB_S5H1432=y CONFIG_DVB_SI2168=y CONFIG_DVB_SP887X=y CONFIG_DVB_STV0367=y CONFIG_DVB_TDA10048=y CONFIG_DVB_TDA1004X=y CONFIG_DVB_ZD1301_DEMOD=y CONFIG_DVB_ZL10353=y CONFIG_DVB_CXD2880=y # # DVB-C (cable) frontends # CONFIG_DVB_STV0297=y CONFIG_DVB_TDA10021=y CONFIG_DVB_TDA10023=y CONFIG_DVB_VES1820=y # # ATSC (North American/Korean Terrestrial/Cable DTV) frontends # CONFIG_DVB_AU8522=y CONFIG_DVB_AU8522_DTV=y CONFIG_DVB_AU8522_V4L=y CONFIG_DVB_BCM3510=y CONFIG_DVB_LG2160=y CONFIG_DVB_LGDT3305=y CONFIG_DVB_LGDT3306A=y CONFIG_DVB_LGDT330X=y CONFIG_DVB_MXL692=y CONFIG_DVB_NXT200X=y CONFIG_DVB_OR51132=y CONFIG_DVB_OR51211=y CONFIG_DVB_S5H1409=y CONFIG_DVB_S5H1411=y # # ISDB-T (terrestrial) frontends # CONFIG_DVB_DIB8000=y CONFIG_DVB_MB86A20S=y CONFIG_DVB_S921=y # # ISDB-S (satellite) & ISDB-T (terrestrial) frontends # CONFIG_DVB_MN88443X=y CONFIG_DVB_TC90522=y # # Digital terrestrial only tuners/PLL # CONFIG_DVB_PLL=y CONFIG_DVB_TUNER_DIB0070=y CONFIG_DVB_TUNER_DIB0090=y # # SEC control devices for DVB-S # CONFIG_DVB_A8293=y CONFIG_DVB_AF9033=y CONFIG_DVB_ASCOT2E=y CONFIG_DVB_ATBM8830=y CONFIG_DVB_HELENE=y CONFIG_DVB_HORUS3A=y CONFIG_DVB_ISL6405=y CONFIG_DVB_ISL6421=y CONFIG_DVB_ISL6423=y CONFIG_DVB_IX2505V=y CONFIG_DVB_LGS8GL5=y CONFIG_DVB_LGS8GXX=y CONFIG_DVB_LNBH25=y CONFIG_DVB_LNBH29=y CONFIG_DVB_LNBP21=y CONFIG_DVB_LNBP22=y CONFIG_DVB_M88RS2000=y CONFIG_DVB_TDA665x=y CONFIG_DVB_DRX39XYJ=y # # Common Interface (EN50221) controller drivers # CONFIG_DVB_CXD2099=y CONFIG_DVB_SP2=y # end of Customise DVB Frontends # # Tools to develop new frontends # CONFIG_DVB_DUMMY_FE=y # end of Media ancillary drivers # # Graphics support # CONFIG_APERTURE_HELPERS=y CONFIG_AGP=y CONFIG_AGP_ALI=y CONFIG_AGP_ATI=y CONFIG_AGP_AMD=y CONFIG_AGP_AMD64=y CONFIG_AGP_INTEL=y CONFIG_AGP_NVIDIA=y CONFIG_AGP_SIS=y CONFIG_AGP_SWORKS=y CONFIG_AGP_VIA=y CONFIG_AGP_EFFICEON=y CONFIG_INTEL_GTT=y CONFIG_VGA_SWITCHEROO=y CONFIG_DRM=y CONFIG_DRM_MIPI_DBI=y CONFIG_DRM_MIPI_DSI=y CONFIG_DRM_DEBUG_MM=y CONFIG_DRM_USE_DYNAMIC_DEBUG=y CONFIG_DRM_KUNIT_TEST=y CONFIG_DRM_KMS_HELPER=y CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS=y CONFIG_DRM_DEBUG_MODESET_LOCK=y CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM=y CONFIG_DRM_LOAD_EDID_FIRMWARE=y CONFIG_DRM_DP_AUX_BUS=y CONFIG_DRM_DISPLAY_HELPER=y CONFIG_DRM_DISPLAY_DP_HELPER=y CONFIG_DRM_DISPLAY_HDCP_HELPER=y CONFIG_DRM_DISPLAY_HDMI_HELPER=y CONFIG_DRM_DP_AUX_CHARDEV=y CONFIG_DRM_DP_CEC=y CONFIG_DRM_TTM=y CONFIG_DRM_BUDDY=y CONFIG_DRM_VRAM_HELPER=y CONFIG_DRM_TTM_HELPER=y CONFIG_DRM_GEM_DMA_HELPER=y CONFIG_DRM_GEM_SHMEM_HELPER=y CONFIG_DRM_SCHED=y # # I2C encoder or helper chips # CONFIG_DRM_I2C_CH7006=y CONFIG_DRM_I2C_SIL164=y CONFIG_DRM_I2C_NXP_TDA998X=y CONFIG_DRM_I2C_NXP_TDA9950=y # end of I2C encoder or helper chips # # ARM devices # CONFIG_DRM_KOMEDA=y # end of ARM devices CONFIG_DRM_RADEON=y CONFIG_DRM_RADEON_USERPTR=y CONFIG_DRM_AMDGPU=y CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_CIK=y CONFIG_DRM_AMDGPU_USERPTR=y # # ACP (Audio CoProcessor) Configuration # CONFIG_DRM_AMD_ACP=y # end of ACP (Audio CoProcessor) Configuration # # Display Engine Configuration # CONFIG_DRM_AMD_DC=y CONFIG_DRM_AMD_DC_DCN=y CONFIG_DRM_AMD_DC_HDCP=y CONFIG_DRM_AMD_DC_SI=y CONFIG_DEBUG_KERNEL_DC=y CONFIG_DRM_AMD_SECURE_DISPLAY=y # end of Display Engine Configuration CONFIG_DRM_NOUVEAU=y CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT=y CONFIG_NOUVEAU_DEBUG=5 CONFIG_NOUVEAU_DEBUG_DEFAULT=3 CONFIG_NOUVEAU_DEBUG_MMU=y CONFIG_NOUVEAU_DEBUG_PUSH=y CONFIG_DRM_NOUVEAU_BACKLIGHT=y CONFIG_DRM_I915=y CONFIG_DRM_I915_FORCE_PROBE="" CONFIG_DRM_I915_CAPTURE_ERROR=y CONFIG_DRM_I915_COMPRESS_ERROR=y CONFIG_DRM_I915_USERPTR=y CONFIG_DRM_I915_PXP=y # # drm/i915 Debugging # CONFIG_DRM_I915_WERROR=y # CONFIG_DRM_I915_DEBUG is not set CONFIG_DRM_I915_DEBUG_MMIO=y # CONFIG_DRM_I915_DEBUG_GEM is not set CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS=y CONFIG_DRM_I915_SW_FENCE_CHECK_DAG=y CONFIG_DRM_I915_DEBUG_GUC=y CONFIG_DRM_I915_SELFTEST=y CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS=y CONFIG_DRM_I915_DEBUG_VBLANK_EVADE=y CONFIG_DRM_I915_DEBUG_RUNTIME_PM=y # end of drm/i915 Debugging # # drm/i915 Profile Guided Optimisation # CONFIG_DRM_I915_REQUEST_TIMEOUT=20000 CONFIG_DRM_I915_FENCE_TIMEOUT=10000 CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250 CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500 CONFIG_DRM_I915_PREEMPT_TIMEOUT=640 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 CONFIG_DRM_I915_STOP_TIMEOUT=100 CONFIG_DRM_I915_TIMESLICE_DURATION=1 # end of drm/i915 Profile Guided Optimisation CONFIG_DRM_VGEM=y CONFIG_DRM_VKMS=y CONFIG_DRM_VMWGFX=y # CONFIG_DRM_VMWGFX_FBCON is not set CONFIG_DRM_VMWGFX_MKSSTATS=y CONFIG_DRM_GMA500=y CONFIG_DRM_UDL=y CONFIG_DRM_AST=y CONFIG_DRM_MGAG200=y CONFIG_DRM_RCAR_DW_HDMI=y CONFIG_DRM_RCAR_USE_LVDS=y CONFIG_DRM_RCAR_MIPI_DSI=y CONFIG_DRM_QXL=y CONFIG_DRM_VIRTIO_GPU=y CONFIG_DRM_PANEL=y # # Display Panels # CONFIG_DRM_PANEL_ABT_Y030XX067A=y CONFIG_DRM_PANEL_ARM_VERSATILE=y CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=y CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=y CONFIG_DRM_PANEL_BOE_HIMAX8279D=y CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=y CONFIG_DRM_PANEL_DSI_CM=y CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y CONFIG_DRM_PANEL_EBBG_FT8719=y CONFIG_DRM_PANEL_ELIDA_KD35T133=y CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=y CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=y CONFIG_DRM_PANEL_ILITEK_IL9322=y CONFIG_DRM_PANEL_ILITEK_ILI9341=y CONFIG_DRM_PANEL_ILITEK_ILI9881C=y CONFIG_DRM_PANEL_INNOLUX_EJ030NA=y CONFIG_DRM_PANEL_INNOLUX_P079ZCA=y CONFIG_DRM_PANEL_JDI_LT070ME05000=y CONFIG_DRM_PANEL_JDI_R63452=y CONFIG_DRM_PANEL_KHADAS_TS050=y CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=y CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=y CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=y CONFIG_DRM_PANEL_SAMSUNG_LD9040=y CONFIG_DRM_PANEL_LG_LB035Q02=y CONFIG_DRM_PANEL_LG_LG4573=y CONFIG_DRM_PANEL_NEC_NL8048HL11=y CONFIG_DRM_PANEL_NEWVISION_NV3052C=y CONFIG_DRM_PANEL_NOVATEK_NT35510=y CONFIG_DRM_PANEL_NOVATEK_NT35560=y CONFIG_DRM_PANEL_NOVATEK_NT35950=y CONFIG_DRM_PANEL_NOVATEK_NT36672A=y CONFIG_DRM_PANEL_NOVATEK_NT39016=y CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=y CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=y CONFIG_DRM_PANEL_ORISETECH_OTM8009A=y CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=y CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=y CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y CONFIG_DRM_PANEL_RAYDIUM_RM67191=y CONFIG_DRM_PANEL_RAYDIUM_RM68200=y CONFIG_DRM_PANEL_RONBO_RB070D30=y CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=y CONFIG_DRM_PANEL_SAMSUNG_DB7430=y CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=y CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=y CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=y CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=y CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=y CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=y CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=y CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=y CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=y CONFIG_DRM_PANEL_SEIKO_43WVF1G=y CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=y CONFIG_DRM_PANEL_SHARP_LS037V7DW01=y CONFIG_DRM_PANEL_SHARP_LS043T1LE01=y CONFIG_DRM_PANEL_SHARP_LS060T1SX01=y CONFIG_DRM_PANEL_SITRONIX_ST7701=y CONFIG_DRM_PANEL_SITRONIX_ST7703=y CONFIG_DRM_PANEL_SITRONIX_ST7789V=y CONFIG_DRM_PANEL_SONY_ACX565AKM=y CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=y CONFIG_DRM_PANEL_TDO_TL070WSH30=y CONFIG_DRM_PANEL_TPO_TD028TTEC1=y CONFIG_DRM_PANEL_TPO_TD043MTEA1=y CONFIG_DRM_PANEL_TPO_TPG110=y CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=y CONFIG_DRM_PANEL_VISIONOX_RM69299=y CONFIG_DRM_PANEL_WIDECHIPS_WS2401=y CONFIG_DRM_PANEL_XINPENG_XPP055C272=y # end of Display Panels CONFIG_DRM_BRIDGE=y CONFIG_DRM_PANEL_BRIDGE=y # # Display Interface Bridges # CONFIG_DRM_CDNS_DSI=y CONFIG_DRM_CHIPONE_ICN6211=y CONFIG_DRM_CHRONTEL_CH7033=y CONFIG_DRM_CROS_EC_ANX7688=y CONFIG_DRM_DISPLAY_CONNECTOR=y CONFIG_DRM_ITE_IT6505=y CONFIG_DRM_LONTIUM_LT8912B=y CONFIG_DRM_LONTIUM_LT9211=y CONFIG_DRM_LONTIUM_LT9611=y CONFIG_DRM_LONTIUM_LT9611UXC=y CONFIG_DRM_ITE_IT66121=y CONFIG_DRM_LVDS_CODEC=y CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=y CONFIG_DRM_NWL_MIPI_DSI=y CONFIG_DRM_NXP_PTN3460=y CONFIG_DRM_PARADE_PS8622=y CONFIG_DRM_PARADE_PS8640=y CONFIG_DRM_SIL_SII8620=y CONFIG_DRM_SII902X=y CONFIG_DRM_SII9234=y CONFIG_DRM_SIMPLE_BRIDGE=y CONFIG_DRM_THINE_THC63LVD1024=y CONFIG_DRM_TOSHIBA_TC358762=y CONFIG_DRM_TOSHIBA_TC358764=y CONFIG_DRM_TOSHIBA_TC358767=y CONFIG_DRM_TOSHIBA_TC358768=y CONFIG_DRM_TOSHIBA_TC358775=y CONFIG_DRM_TI_DLPC3433=y CONFIG_DRM_TI_TFP410=y CONFIG_DRM_TI_SN65DSI83=y CONFIG_DRM_TI_SN65DSI86=y CONFIG_DRM_TI_TPD12S015=y CONFIG_DRM_ANALOGIX_ANX6345=y CONFIG_DRM_ANALOGIX_ANX78XX=y CONFIG_DRM_ANALOGIX_DP=y CONFIG_DRM_ANALOGIX_ANX7625=y CONFIG_DRM_I2C_ADV7511=y CONFIG_DRM_I2C_ADV7511_AUDIO=y CONFIG_DRM_I2C_ADV7511_CEC=y CONFIG_DRM_CDNS_MHDP8546=y CONFIG_DRM_DW_HDMI=y CONFIG_DRM_DW_HDMI_AHB_AUDIO=y CONFIG_DRM_DW_HDMI_I2S_AUDIO=y CONFIG_DRM_DW_HDMI_GP_AUDIO=y CONFIG_DRM_DW_HDMI_CEC=y # end of Display Interface Bridges CONFIG_DRM_ETNAVIV=y CONFIG_DRM_ETNAVIV_THERMAL=y CONFIG_DRM_LOGICVC=y CONFIG_DRM_MXS=y CONFIG_DRM_MXSFB=y CONFIG_DRM_IMX_LCDIF=y CONFIG_DRM_ARCPGU=y CONFIG_DRM_BOCHS=y CONFIG_DRM_CIRRUS_QEMU=y CONFIG_DRM_GM12U320=y CONFIG_DRM_PANEL_MIPI_DBI=y CONFIG_DRM_SIMPLEDRM=y CONFIG_TINYDRM_HX8357D=y CONFIG_TINYDRM_ILI9163=y CONFIG_TINYDRM_ILI9225=y CONFIG_TINYDRM_ILI9341=y CONFIG_TINYDRM_ILI9486=y CONFIG_TINYDRM_MI0283QT=y CONFIG_TINYDRM_REPAPER=y CONFIG_TINYDRM_ST7586=y CONFIG_TINYDRM_ST7735R=y CONFIG_DRM_VBOXVIDEO=y CONFIG_DRM_GUD=y CONFIG_DRM_SSD130X=y CONFIG_DRM_SSD130X_I2C=y CONFIG_DRM_SSD130X_SPI=y CONFIG_DRM_HYPERV=y CONFIG_DRM_LEGACY=y CONFIG_DRM_TDFX=y CONFIG_DRM_R128=y CONFIG_DRM_MGA=y CONFIG_DRM_SIS=y CONFIG_DRM_VIA=y CONFIG_DRM_SAVAGE=y CONFIG_DRM_EXPORT_FOR_TESTS=y CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y CONFIG_DRM_NOMODESET=y CONFIG_DRM_LIB_RANDOM=y CONFIG_DRM_PRIVACY_SCREEN=y # # Frame buffer Devices # CONFIG_FB_CMDLINE=y CONFIG_FB_NOTIFY=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_DDC=y CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y CONFIG_FB_SYS_FILLRECT=y CONFIG_FB_SYS_COPYAREA=y CONFIG_FB_SYS_IMAGEBLIT=y CONFIG_FB_FOREIGN_ENDIAN=y CONFIG_FB_BOTH_ENDIAN=y # CONFIG_FB_BIG_ENDIAN is not set # CONFIG_FB_LITTLE_ENDIAN is not set CONFIG_FB_SYS_FOPS=y CONFIG_FB_DEFERRED_IO=y CONFIG_FB_HECUBA=y CONFIG_FB_SVGALIB=y CONFIG_FB_BACKLIGHT=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y # # Frame buffer hardware drivers # CONFIG_FB_CIRRUS=y CONFIG_FB_PM2=y CONFIG_FB_PM2_FIFO_DISCONNECT=y CONFIG_FB_CYBER2000=y CONFIG_FB_CYBER2000_DDC=y CONFIG_FB_ARC=y CONFIG_FB_ASILIANT=y CONFIG_FB_IMSTT=y CONFIG_FB_VGA16=y CONFIG_FB_UVESA=y CONFIG_FB_VESA=y CONFIG_FB_EFI=y CONFIG_FB_N411=y CONFIG_FB_HGA=y CONFIG_FB_OPENCORES=y CONFIG_FB_S1D13XXX=y CONFIG_FB_NVIDIA=y CONFIG_FB_NVIDIA_I2C=y CONFIG_FB_NVIDIA_DEBUG=y CONFIG_FB_NVIDIA_BACKLIGHT=y CONFIG_FB_RIVA=y CONFIG_FB_RIVA_I2C=y CONFIG_FB_RIVA_DEBUG=y CONFIG_FB_RIVA_BACKLIGHT=y CONFIG_FB_I740=y CONFIG_FB_I810=y CONFIG_FB_I810_GTF=y CONFIG_FB_I810_I2C=y CONFIG_FB_LE80578=y CONFIG_FB_CARILLO_RANCH=y CONFIG_FB_MATROX=y CONFIG_FB_MATROX_MILLENIUM=y CONFIG_FB_MATROX_MYSTIQUE=y CONFIG_FB_MATROX_G=y CONFIG_FB_MATROX_I2C=y CONFIG_FB_MATROX_MAVEN=y CONFIG_FB_RADEON=y CONFIG_FB_RADEON_I2C=y CONFIG_FB_RADEON_BACKLIGHT=y CONFIG_FB_RADEON_DEBUG=y CONFIG_FB_ATY128=y CONFIG_FB_ATY128_BACKLIGHT=y CONFIG_FB_ATY=y CONFIG_FB_ATY_CT=y CONFIG_FB_ATY_GENERIC_LCD=y CONFIG_FB_ATY_GX=y CONFIG_FB_ATY_BACKLIGHT=y CONFIG_FB_S3=y CONFIG_FB_S3_DDC=y CONFIG_FB_SAVAGE=y CONFIG_FB_SAVAGE_I2C=y CONFIG_FB_SAVAGE_ACCEL=y CONFIG_FB_SIS=y CONFIG_FB_SIS_300=y CONFIG_FB_SIS_315=y CONFIG_FB_VIA=y CONFIG_FB_VIA_DIRECT_PROCFS=y CONFIG_FB_VIA_X_COMPATIBILITY=y CONFIG_FB_NEOMAGIC=y CONFIG_FB_KYRO=y CONFIG_FB_3DFX=y CONFIG_FB_3DFX_ACCEL=y CONFIG_FB_3DFX_I2C=y CONFIG_FB_VOODOO1=y CONFIG_FB_VT8623=y CONFIG_FB_TRIDENT=y CONFIG_FB_ARK=y CONFIG_FB_PM3=y CONFIG_FB_CARMINE=y CONFIG_FB_CARMINE_DRAM_EVAL=y # CONFIG_CARMINE_DRAM_CUSTOM is not set CONFIG_FB_GEODE=y CONFIG_FB_GEODE_LX=y CONFIG_FB_GEODE_GX=y CONFIG_FB_GEODE_GX1=y CONFIG_FB_SM501=y CONFIG_FB_SMSCUFX=y CONFIG_FB_UDL=y CONFIG_FB_IBM_GXT4500=y CONFIG_FB_GOLDFISH=y CONFIG_FB_VIRTUAL=y CONFIG_FB_METRONOME=y CONFIG_FB_MB862XX=y CONFIG_FB_MB862XX_PCI_GDC=y CONFIG_FB_MB862XX_I2C=y CONFIG_FB_HYPERV=y CONFIG_FB_SSD1307=y CONFIG_FB_SM712=y # end of Frame buffer Devices # # Backlight & LCD device support # CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_LMS283GF05=y CONFIG_LCD_LTV350QV=y CONFIG_LCD_ILI922X=y CONFIG_LCD_ILI9320=y CONFIG_LCD_TDO24M=y CONFIG_LCD_VGG2432A4=y CONFIG_LCD_PLATFORM=y CONFIG_LCD_AMS369FG06=y CONFIG_LCD_LMS501KF03=y CONFIG_LCD_HX8357=y CONFIG_LCD_OTM3225A=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_KTD253=y CONFIG_BACKLIGHT_LM3533=y CONFIG_BACKLIGHT_CARILLO_RANCH=y CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_DA903X=y CONFIG_BACKLIGHT_DA9052=y CONFIG_BACKLIGHT_MAX8925=y CONFIG_BACKLIGHT_MT6370=y CONFIG_BACKLIGHT_APPLE=y CONFIG_BACKLIGHT_QCOM_WLED=y CONFIG_BACKLIGHT_RT4831=y CONFIG_BACKLIGHT_SAHARA=y CONFIG_BACKLIGHT_WM831X=y CONFIG_BACKLIGHT_ADP5520=y CONFIG_BACKLIGHT_ADP8860=y CONFIG_BACKLIGHT_ADP8870=y CONFIG_BACKLIGHT_88PM860X=y CONFIG_BACKLIGHT_PCF50633=y CONFIG_BACKLIGHT_AAT2870=y CONFIG_BACKLIGHT_LM3630A=y CONFIG_BACKLIGHT_LM3639=y CONFIG_BACKLIGHT_LP855X=y CONFIG_BACKLIGHT_LP8788=y CONFIG_BACKLIGHT_PANDORA=y CONFIG_BACKLIGHT_SKY81452=y CONFIG_BACKLIGHT_TPS65217=y CONFIG_BACKLIGHT_AS3711=y CONFIG_BACKLIGHT_GPIO=y CONFIG_BACKLIGHT_LV5207LP=y CONFIG_BACKLIGHT_BD6107=y CONFIG_BACKLIGHT_ARCXCNN=y CONFIG_BACKLIGHT_RAVE_SP=y CONFIG_BACKLIGHT_LED=y # end of Backlight & LCD device support CONFIG_VGASTATE=y CONFIG_VIDEOMODE_HELPERS=y CONFIG_HDMI=y # # Console display driver support # CONFIG_VGA_CONSOLE=y CONFIG_MDA_CONSOLE=y CONFIG_DUMMY_CONSOLE=y CONFIG_DUMMY_CONSOLE_COLUMNS=80 CONFIG_DUMMY_CONSOLE_ROWS=25 CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y # end of Console display driver support CONFIG_LOGO=y CONFIG_LOGO_LINUX_MONO=y CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y # end of Graphics support CONFIG_SOUND=y CONFIG_SOUND_OSS_CORE=y CONFIG_SOUND_OSS_CORE_PRECLAIM=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y CONFIG_SND_PCM_ELD=y CONFIG_SND_PCM_IEC958=y CONFIG_SND_DMAENGINE_PCM=y CONFIG_SND_HWDEP=y CONFIG_SND_SEQ_DEVICE=y CONFIG_SND_RAWMIDI=y CONFIG_SND_COMPRESS_OFFLOAD=y CONFIG_SND_JACK=y CONFIG_SND_JACK_INPUT_DEV=y CONFIG_SND_OSSEMUL=y CONFIG_SND_MIXER_OSS=y CONFIG_SND_PCM_OSS=y CONFIG_SND_PCM_OSS_PLUGINS=y CONFIG_SND_PCM_TIMER=y CONFIG_SND_HRTIMER=y CONFIG_SND_DYNAMIC_MINORS=y CONFIG_SND_MAX_CARDS=32 CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y CONFIG_SND_VERBOSE_PRINTK=y CONFIG_SND_CTL_FAST_LOOKUP=y CONFIG_SND_DEBUG=y CONFIG_SND_DEBUG_VERBOSE=y CONFIG_SND_PCM_XRUN_DEBUG=y CONFIG_SND_CTL_INPUT_VALIDATION=y CONFIG_SND_CTL_DEBUG=y CONFIG_SND_JACK_INJECTION_DEBUG=y CONFIG_SND_VMASTER=y CONFIG_SND_DMA_SGBUF=y CONFIG_SND_CTL_LED=y CONFIG_SND_SEQUENCER=y CONFIG_SND_SEQ_DUMMY=y CONFIG_SND_SEQUENCER_OSS=y CONFIG_SND_SEQ_HRTIMER_DEFAULT=y CONFIG_SND_SEQ_MIDI_EVENT=y CONFIG_SND_SEQ_MIDI=y CONFIG_SND_SEQ_MIDI_EMUL=y CONFIG_SND_SEQ_VIRMIDI=y CONFIG_SND_MPU401_UART=y CONFIG_SND_OPL3_LIB=y CONFIG_SND_OPL4_LIB=y CONFIG_SND_OPL3_LIB_SEQ=y CONFIG_SND_OPL4_LIB_SEQ=y CONFIG_SND_VX_LIB=y CONFIG_SND_AC97_CODEC=y CONFIG_SND_DRIVERS=y CONFIG_SND_PCSP=y CONFIG_SND_DUMMY=y CONFIG_SND_ALOOP=y CONFIG_SND_VIRMIDI=y CONFIG_SND_MTPAV=y CONFIG_SND_MTS64=y CONFIG_SND_SERIAL_U16550=y CONFIG_SND_SERIAL_GENERIC=y CONFIG_SND_MPU401=y CONFIG_SND_PORTMAN2X4=y CONFIG_SND_AC97_POWER_SAVE=y CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 CONFIG_SND_WSS_LIB=y CONFIG_SND_SB_COMMON=y CONFIG_SND_SB8_DSP=y CONFIG_SND_SB16_DSP=y CONFIG_SND_ISA=y CONFIG_SND_ADLIB=y CONFIG_SND_AD1816A=y CONFIG_SND_AD1848=y CONFIG_SND_ALS100=y CONFIG_SND_AZT1605=y CONFIG_SND_AZT2316=y CONFIG_SND_AZT2320=y CONFIG_SND_CMI8328=y CONFIG_SND_CMI8330=y CONFIG_SND_CS4231=y CONFIG_SND_CS4236=y CONFIG_SND_ES1688=y CONFIG_SND_ES18XX=y CONFIG_SND_SC6000=y CONFIG_SND_GUSCLASSIC=y CONFIG_SND_GUSEXTREME=y CONFIG_SND_GUSMAX=y CONFIG_SND_INTERWAVE=y CONFIG_SND_INTERWAVE_STB=y CONFIG_SND_JAZZ16=y CONFIG_SND_OPL3SA2=y CONFIG_SND_OPTI92X_AD1848=y CONFIG_SND_OPTI92X_CS4231=y CONFIG_SND_OPTI93X=y CONFIG_SND_MIRO=y CONFIG_SND_SB8=y CONFIG_SND_SB16=y CONFIG_SND_SBAWE=y CONFIG_SND_SBAWE_SEQ=y CONFIG_SND_SB16_CSP=y CONFIG_SND_SSCAPE=y CONFIG_SND_WAVEFRONT=y CONFIG_SND_MSND_PINNACLE=y CONFIG_SND_MSND_CLASSIC=y CONFIG_SND_PCI=y CONFIG_SND_AD1889=y CONFIG_SND_ALS300=y CONFIG_SND_ALS4000=y CONFIG_SND_ALI5451=y CONFIG_SND_ASIHPI=y CONFIG_SND_ATIIXP=y CONFIG_SND_ATIIXP_MODEM=y CONFIG_SND_AU8810=y CONFIG_SND_AU8820=y CONFIG_SND_AU8830=y CONFIG_SND_AW2=y CONFIG_SND_AZT3328=y CONFIG_SND_BT87X=y CONFIG_SND_BT87X_OVERCLOCK=y CONFIG_SND_CA0106=y CONFIG_SND_CMIPCI=y CONFIG_SND_OXYGEN_LIB=y CONFIG_SND_OXYGEN=y CONFIG_SND_CS4281=y CONFIG_SND_CS46XX=y CONFIG_SND_CS46XX_NEW_DSP=y CONFIG_SND_CS5530=y CONFIG_SND_CS5535AUDIO=y CONFIG_SND_CTXFI=y CONFIG_SND_DARLA20=y CONFIG_SND_GINA20=y CONFIG_SND_LAYLA20=y CONFIG_SND_DARLA24=y CONFIG_SND_GINA24=y CONFIG_SND_LAYLA24=y CONFIG_SND_MONA=y CONFIG_SND_MIA=y CONFIG_SND_ECHO3G=y CONFIG_SND_INDIGO=y CONFIG_SND_INDIGOIO=y CONFIG_SND_INDIGODJ=y CONFIG_SND_INDIGOIOX=y CONFIG_SND_INDIGODJX=y CONFIG_SND_EMU10K1=y CONFIG_SND_EMU10K1_SEQ=y CONFIG_SND_EMU10K1X=y CONFIG_SND_ENS1370=y CONFIG_SND_ENS1371=y CONFIG_SND_ES1938=y CONFIG_SND_ES1968=y CONFIG_SND_ES1968_INPUT=y CONFIG_SND_ES1968_RADIO=y CONFIG_SND_FM801=y CONFIG_SND_FM801_TEA575X_BOOL=y CONFIG_SND_HDSP=y # # Don't forget to add built-in firmwares for HDSP driver # CONFIG_SND_HDSPM=y CONFIG_SND_ICE1712=y CONFIG_SND_ICE1724=y CONFIG_SND_INTEL8X0=y CONFIG_SND_INTEL8X0M=y CONFIG_SND_KORG1212=y CONFIG_SND_LOLA=y CONFIG_SND_LX6464ES=y CONFIG_SND_MAESTRO3=y CONFIG_SND_MAESTRO3_INPUT=y CONFIG_SND_MIXART=y CONFIG_SND_NM256=y CONFIG_SND_PCXHR=y CONFIG_SND_RIPTIDE=y CONFIG_SND_RME32=y CONFIG_SND_RME96=y CONFIG_SND_RME9652=y CONFIG_SND_SIS7019=y CONFIG_SND_SONICVIBES=y CONFIG_SND_TRIDENT=y CONFIG_SND_VIA82XX=y CONFIG_SND_VIA82XX_MODEM=y CONFIG_SND_VIRTUOSO=y CONFIG_SND_VX222=y CONFIG_SND_YMFPCI=y # # HD-Audio # CONFIG_SND_HDA=y CONFIG_SND_HDA_GENERIC_LEDS=y CONFIG_SND_HDA_INTEL=y CONFIG_SND_HDA_HWDEP=y CONFIG_SND_HDA_RECONFIG=y CONFIG_SND_HDA_INPUT_BEEP=y CONFIG_SND_HDA_INPUT_BEEP_MODE=1 CONFIG_SND_HDA_PATCH_LOADER=y CONFIG_SND_HDA_SCODEC_CS35L41=y CONFIG_SND_HDA_CS_DSP_CONTROLS=y CONFIG_SND_HDA_SCODEC_CS35L41_I2C=y CONFIG_SND_HDA_SCODEC_CS35L41_SPI=y CONFIG_SND_HDA_CODEC_REALTEK=y CONFIG_SND_HDA_CODEC_ANALOG=y CONFIG_SND_HDA_CODEC_SIGMATEL=y CONFIG_SND_HDA_CODEC_VIA=y CONFIG_SND_HDA_CODEC_HDMI=y CONFIG_SND_HDA_CODEC_CIRRUS=y CONFIG_SND_HDA_CODEC_CS8409=y CONFIG_SND_HDA_CODEC_CONEXANT=y CONFIG_SND_HDA_CODEC_CA0110=y CONFIG_SND_HDA_CODEC_CA0132=y CONFIG_SND_HDA_CODEC_CA0132_DSP=y CONFIG_SND_HDA_CODEC_CMEDIA=y CONFIG_SND_HDA_CODEC_SI3054=y CONFIG_SND_HDA_GENERIC=y CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y # end of HD-Audio CONFIG_SND_HDA_CORE=y CONFIG_SND_HDA_DSP_LOADER=y CONFIG_SND_HDA_COMPONENT=y CONFIG_SND_HDA_I915=y CONFIG_SND_HDA_EXT_CORE=y CONFIG_SND_HDA_PREALLOC_SIZE=0 CONFIG_SND_INTEL_NHLT=y CONFIG_SND_INTEL_DSP_CONFIG=y CONFIG_SND_INTEL_SOUNDWIRE_ACPI=y CONFIG_SND_INTEL_BYT_PREFER_SOF=y CONFIG_SND_SPI=y CONFIG_SND_USB=y CONFIG_SND_USB_AUDIO=y CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y CONFIG_SND_USB_UA101=y CONFIG_SND_USB_USX2Y=y CONFIG_SND_USB_CAIAQ=y CONFIG_SND_USB_CAIAQ_INPUT=y CONFIG_SND_USB_US122L=y CONFIG_SND_USB_6FIRE=y CONFIG_SND_USB_HIFACE=y CONFIG_SND_BCD2000=y CONFIG_SND_USB_LINE6=y CONFIG_SND_USB_POD=y CONFIG_SND_USB_PODHD=y CONFIG_SND_USB_TONEPORT=y CONFIG_SND_USB_VARIAX=y CONFIG_SND_FIREWIRE=y CONFIG_SND_FIREWIRE_LIB=y CONFIG_SND_DICE=y CONFIG_SND_OXFW=y CONFIG_SND_ISIGHT=y CONFIG_SND_FIREWORKS=y CONFIG_SND_BEBOB=y CONFIG_SND_FIREWIRE_DIGI00X=y CONFIG_SND_FIREWIRE_TASCAM=y CONFIG_SND_FIREWIRE_MOTU=y CONFIG_SND_FIREFACE=y CONFIG_SND_PCMCIA=y CONFIG_SND_VXPOCKET=y CONFIG_SND_PDAUDIOCF=y CONFIG_SND_SOC=y CONFIG_SND_SOC_AC97_BUS=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y CONFIG_SND_SOC_COMPRESS=y CONFIG_SND_SOC_TOPOLOGY=y CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=y CONFIG_SND_SOC_UTILS_KUNIT_TEST=y CONFIG_SND_SOC_ACPI=y CONFIG_SND_SOC_ADI=y CONFIG_SND_SOC_ADI_AXI_I2S=y CONFIG_SND_SOC_ADI_AXI_SPDIF=y CONFIG_SND_SOC_AMD_ACP=y CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=y CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=y CONFIG_SND_SOC_AMD_ST_ES8336_MACH=y CONFIG_SND_SOC_AMD_ACP3x=y CONFIG_SND_SOC_AMD_RV_RT5682_MACH=y CONFIG_SND_SOC_AMD_RENOIR=y CONFIG_SND_SOC_AMD_RENOIR_MACH=y CONFIG_SND_SOC_AMD_ACP5x=y CONFIG_SND_SOC_AMD_VANGOGH_MACH=y CONFIG_SND_SOC_AMD_ACP6x=y CONFIG_SND_SOC_AMD_YC_MACH=y CONFIG_SND_AMD_ACP_CONFIG=y CONFIG_SND_SOC_AMD_ACP_COMMON=y CONFIG_SND_SOC_AMD_ACP_PDM=y CONFIG_SND_SOC_AMD_ACP_I2S=y CONFIG_SND_SOC_AMD_ACP_PCM=y CONFIG_SND_SOC_AMD_ACP_PCI=y CONFIG_SND_AMD_ASOC_RENOIR=y CONFIG_SND_AMD_ASOC_REMBRANDT=y CONFIG_SND_SOC_AMD_MACH_COMMON=y CONFIG_SND_SOC_AMD_LEGACY_MACH=y CONFIG_SND_SOC_AMD_SOF_MACH=y CONFIG_SND_SOC_AMD_RPL_ACP6x=y CONFIG_SND_SOC_AMD_PS=y CONFIG_SND_SOC_AMD_PS_MACH=y CONFIG_SND_ATMEL_SOC=y CONFIG_SND_SOC_MIKROE_PROTO=y CONFIG_SND_BCM63XX_I2S_WHISTLER=y CONFIG_SND_DESIGNWARE_I2S=y CONFIG_SND_DESIGNWARE_PCM=y # # SoC Audio for Freescale CPUs # # # Common SoC Audio options for Freescale CPUs: # CONFIG_SND_SOC_FSL_ASRC=y CONFIG_SND_SOC_FSL_SAI=y CONFIG_SND_SOC_FSL_MQS=y CONFIG_SND_SOC_FSL_AUDMIX=y CONFIG_SND_SOC_FSL_SSI=y CONFIG_SND_SOC_FSL_SPDIF=y CONFIG_SND_SOC_FSL_ESAI=y CONFIG_SND_SOC_FSL_MICFIL=y CONFIG_SND_SOC_FSL_EASRC=y CONFIG_SND_SOC_FSL_XCVR=y CONFIG_SND_SOC_FSL_UTILS=y CONFIG_SND_SOC_FSL_RPMSG=y CONFIG_SND_SOC_IMX_AUDMUX=y # end of SoC Audio for Freescale CPUs CONFIG_SND_I2S_HI6210_I2S=y CONFIG_SND_SOC_IMG=y CONFIG_SND_SOC_IMG_I2S_IN=y CONFIG_SND_SOC_IMG_I2S_OUT=y CONFIG_SND_SOC_IMG_PARALLEL_OUT=y CONFIG_SND_SOC_IMG_SPDIF_IN=y CONFIG_SND_SOC_IMG_SPDIF_OUT=y CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=y CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y CONFIG_SND_SOC_INTEL_SST=y CONFIG_SND_SOC_INTEL_CATPT=y CONFIG_SND_SST_ATOM_HIFI2_PLATFORM=y CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI=y CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI=y CONFIG_SND_SOC_INTEL_SKYLAKE=y CONFIG_SND_SOC_INTEL_SKL=y CONFIG_SND_SOC_INTEL_APL=y CONFIG_SND_SOC_INTEL_KBL=y CONFIG_SND_SOC_INTEL_GLK=y CONFIG_SND_SOC_INTEL_CNL=y CONFIG_SND_SOC_INTEL_CFL=y CONFIG_SND_SOC_INTEL_CML_H=y CONFIG_SND_SOC_INTEL_CML_LP=y CONFIG_SND_SOC_INTEL_SKYLAKE_FAMILY=y CONFIG_SND_SOC_INTEL_SKYLAKE_SSP_CLK=y CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC=y CONFIG_SND_SOC_INTEL_SKYLAKE_COMMON=y CONFIG_SND_SOC_ACPI_INTEL_MATCH=y CONFIG_SND_SOC_INTEL_AVS=y # # Intel AVS Machine drivers # # # Available DSP configurations # CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=y CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC=y CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO=y CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST=y CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98927=y CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A=y CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373=y CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825=y CONFIG_SND_SOC_INTEL_AVS_MACH_RT274=y CONFIG_SND_SOC_INTEL_AVS_MACH_RT286=y CONFIG_SND_SOC_INTEL_AVS_MACH_RT298=y CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682=y CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567=y # end of Intel AVS Machine drivers CONFIG_SND_SOC_INTEL_MACH=y CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES=y CONFIG_SND_SOC_INTEL_HDA_DSP_COMMON=y CONFIG_SND_SOC_INTEL_SOF_MAXIM_COMMON=y CONFIG_SND_SOC_INTEL_SOF_REALTEK_COMMON=y CONFIG_SND_SOC_INTEL_HASWELL_MACH=y CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH=y CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH=y CONFIG_SND_SOC_INTEL_BROADWELL_MACH=y CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH=y CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH=y CONFIG_SND_SOC_INTEL_BYTCR_WM5102_MACH=y CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH=y CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH=y CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH=y CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH=y CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH=y CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH=y CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH=y CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH=y CONFIG_SND_SOC_INTEL_SKL_RT286_MACH=y CONFIG_SND_SOC_INTEL_SKL_NAU88L25_SSM4567_MACH=y CONFIG_SND_SOC_INTEL_SKL_NAU88L25_MAX98357A_MACH=y CONFIG_SND_SOC_INTEL_DA7219_MAX98357A_GENERIC=y CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_COMMON=y CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_MACH=y CONFIG_SND_SOC_INTEL_BXT_RT298_MACH=y CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH=y CONFIG_SND_SOC_INTEL_KBL_RT5663_MAX98927_MACH=y CONFIG_SND_SOC_INTEL_KBL_RT5663_RT5514_MAX98927_MACH=y CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98357A_MACH=y CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98927_MACH=y CONFIG_SND_SOC_INTEL_KBL_RT5660_MACH=y CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH=y CONFIG_SND_SOC_INTEL_SOF_RT5682_MACH=y CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH=y CONFIG_SND_SOC_INTEL_SOUNDWIRE_SOF_MACH=y CONFIG_SND_SOC_MTK_BTCVSD=y CONFIG_SND_SOC_SOF_TOPLEVEL=y CONFIG_SND_SOC_SOF_PCI_DEV=y CONFIG_SND_SOC_SOF_PCI=y CONFIG_SND_SOC_SOF_ACPI=y CONFIG_SND_SOC_SOF_ACPI_DEV=y CONFIG_SND_SOC_SOF_OF=y CONFIG_SND_SOC_SOF_DEBUG_PROBES=y CONFIG_SND_SOC_SOF_CLIENT=y CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT=y CONFIG_SND_SOC_SOF_FORCE_PROBE_WORKQUEUE=y CONFIG_SND_SOC_SOF_NOCODEC=y CONFIG_SND_SOC_SOF_NOCODEC_SUPPORT=y CONFIG_SND_SOC_SOF_STRICT_ABI_CHECKS=y CONFIG_SND_SOC_SOF_DEBUG=y CONFIG_SND_SOC_SOF_FORCE_NOCODEC_MODE=y CONFIG_SND_SOC_SOF_DEBUG_XRUN_STOP=y CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC=y CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION=y CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE=y CONFIG_SND_SOC_SOF_DEBUG_ENABLE_FIRMWARE_TRACE=y CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST=y CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST_NUM=2 CONFIG_SND_SOC_SOF_DEBUG_IPC_MSG_INJECTOR=y CONFIG_SND_SOC_SOF_DEBUG_RETAIN_DSP_CONTEXT=y CONFIG_SND_SOC_SOF=y CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE=y CONFIG_SND_SOC_SOF_IPC3=y CONFIG_SND_SOC_SOF_INTEL_IPC4=y CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=y CONFIG_SND_SOC_SOF_AMD_COMMON=y CONFIG_SND_SOC_SOF_AMD_RENOIR=y CONFIG_SND_SOC_SOF_AMD_REMBRANDT=y CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL=y CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC=y CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP=y CONFIG_SND_SOC_SOF_INTEL_COMMON=y CONFIG_SND_SOC_SOF_BAYTRAIL=y CONFIG_SND_SOC_SOF_BROADWELL=y CONFIG_SND_SOC_SOF_MERRIFIELD=y CONFIG_SND_SOC_SOF_INTEL_SKL=y CONFIG_SND_SOC_SOF_SKYLAKE=y CONFIG_SND_SOC_SOF_KABYLAKE=y CONFIG_SND_SOC_SOF_INTEL_APL=y CONFIG_SND_SOC_SOF_APOLLOLAKE=y CONFIG_SND_SOC_SOF_GEMINILAKE=y CONFIG_SND_SOC_SOF_INTEL_CNL=y CONFIG_SND_SOC_SOF_CANNONLAKE=y CONFIG_SND_SOC_SOF_COFFEELAKE=y CONFIG_SND_SOC_SOF_COMETLAKE=y CONFIG_SND_SOC_SOF_INTEL_ICL=y CONFIG_SND_SOC_SOF_ICELAKE=y CONFIG_SND_SOC_SOF_JASPERLAKE=y CONFIG_SND_SOC_SOF_INTEL_TGL=y CONFIG_SND_SOC_SOF_TIGERLAKE=y CONFIG_SND_SOC_SOF_ELKHARTLAKE=y CONFIG_SND_SOC_SOF_ALDERLAKE=y CONFIG_SND_SOC_SOF_INTEL_MTL=y CONFIG_SND_SOC_SOF_METEORLAKE=y CONFIG_SND_SOC_SOF_HDA_COMMON=y CONFIG_SND_SOC_SOF_HDA_LINK_BASELINE=y CONFIG_SND_SOC_SOF_HDA_PROBES=y CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE=y CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE=y CONFIG_SND_SOC_SOF_XTENSA=y # # STMicroelectronics STM32 SOC audio support # # end of STMicroelectronics STM32 SOC audio support CONFIG_SND_SOC_XILINX_I2S=y CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=y CONFIG_SND_SOC_XILINX_SPDIF=y CONFIG_SND_SOC_XTFPGA_I2S=y CONFIG_SND_SOC_I2C_AND_SPI=y # # CODEC drivers # CONFIG_SND_SOC_ARIZONA=y CONFIG_SND_SOC_WM_ADSP=y CONFIG_SND_SOC_AC97_CODEC=y CONFIG_SND_SOC_ADAU_UTILS=y CONFIG_SND_SOC_ADAU1372=y CONFIG_SND_SOC_ADAU1372_I2C=y CONFIG_SND_SOC_ADAU1372_SPI=y CONFIG_SND_SOC_ADAU1701=y CONFIG_SND_SOC_ADAU17X1=y CONFIG_SND_SOC_ADAU1761=y CONFIG_SND_SOC_ADAU1761_I2C=y CONFIG_SND_SOC_ADAU1761_SPI=y CONFIG_SND_SOC_ADAU7002=y CONFIG_SND_SOC_ADAU7118=y CONFIG_SND_SOC_ADAU7118_HW=y CONFIG_SND_SOC_ADAU7118_I2C=y CONFIG_SND_SOC_AK4104=y CONFIG_SND_SOC_AK4118=y CONFIG_SND_SOC_AK4375=y CONFIG_SND_SOC_AK4458=y CONFIG_SND_SOC_AK4554=y CONFIG_SND_SOC_AK4613=y CONFIG_SND_SOC_AK4642=y CONFIG_SND_SOC_AK5386=y CONFIG_SND_SOC_AK5558=y CONFIG_SND_SOC_ALC5623=y CONFIG_SND_SOC_AW8738=y CONFIG_SND_SOC_BD28623=y CONFIG_SND_SOC_BT_SCO=y CONFIG_SND_SOC_CPCAP=y CONFIG_SND_SOC_CROS_EC_CODEC=y CONFIG_SND_SOC_CS35L32=y CONFIG_SND_SOC_CS35L33=y CONFIG_SND_SOC_CS35L34=y CONFIG_SND_SOC_CS35L35=y CONFIG_SND_SOC_CS35L36=y CONFIG_SND_SOC_CS35L41_LIB=y CONFIG_SND_SOC_CS35L41=y CONFIG_SND_SOC_CS35L41_SPI=y CONFIG_SND_SOC_CS35L41_I2C=y CONFIG_SND_SOC_CS35L45_TABLES=y CONFIG_SND_SOC_CS35L45=y CONFIG_SND_SOC_CS35L45_SPI=y CONFIG_SND_SOC_CS35L45_I2C=y CONFIG_SND_SOC_CS42L42_CORE=y CONFIG_SND_SOC_CS42L42=y CONFIG_SND_SOC_CS42L51=y CONFIG_SND_SOC_CS42L51_I2C=y CONFIG_SND_SOC_CS42L52=y CONFIG_SND_SOC_CS42L56=y CONFIG_SND_SOC_CS42L73=y CONFIG_SND_SOC_CS42L83=y CONFIG_SND_SOC_CS4234=y CONFIG_SND_SOC_CS4265=y CONFIG_SND_SOC_CS4270=y CONFIG_SND_SOC_CS4271=y CONFIG_SND_SOC_CS4271_I2C=y CONFIG_SND_SOC_CS4271_SPI=y CONFIG_SND_SOC_CS42XX8=y CONFIG_SND_SOC_CS42XX8_I2C=y CONFIG_SND_SOC_CS43130=y CONFIG_SND_SOC_CS4341=y CONFIG_SND_SOC_CS4349=y CONFIG_SND_SOC_CS48L32=y CONFIG_SND_SOC_CS53L30=y CONFIG_SND_SOC_CX2072X=y CONFIG_SND_SOC_DA7213=y CONFIG_SND_SOC_DA7219=y CONFIG_SND_SOC_DMIC=y CONFIG_SND_SOC_HDMI_CODEC=y CONFIG_SND_SOC_ES7134=y CONFIG_SND_SOC_ES7241=y CONFIG_SND_SOC_ES8316=y CONFIG_SND_SOC_ES8326=y CONFIG_SND_SOC_ES8328=y CONFIG_SND_SOC_ES8328_I2C=y CONFIG_SND_SOC_ES8328_SPI=y CONFIG_SND_SOC_GTM601=y CONFIG_SND_SOC_HDAC_HDMI=y CONFIG_SND_SOC_HDAC_HDA=y CONFIG_SND_SOC_HDA=y CONFIG_SND_SOC_ICS43432=y CONFIG_SND_SOC_INNO_RK3036=y CONFIG_SND_SOC_LOCHNAGAR_SC=y CONFIG_SND_SOC_MAX98088=y CONFIG_SND_SOC_MAX98090=y CONFIG_SND_SOC_MAX98357A=y CONFIG_SND_SOC_MAX98504=y CONFIG_SND_SOC_MAX9867=y CONFIG_SND_SOC_MAX98927=y CONFIG_SND_SOC_MAX98520=y CONFIG_SND_SOC_MAX98373=y CONFIG_SND_SOC_MAX98373_I2C=y CONFIG_SND_SOC_MAX98373_SDW=y CONFIG_SND_SOC_MAX98390=y CONFIG_SND_SOC_MAX98396=y CONFIG_SND_SOC_MAX9860=y CONFIG_SND_SOC_MSM8916_WCD_ANALOG=y CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y CONFIG_SND_SOC_PCM1681=y CONFIG_SND_SOC_PCM1789=y CONFIG_SND_SOC_PCM1789_I2C=y CONFIG_SND_SOC_PCM179X=y CONFIG_SND_SOC_PCM179X_I2C=y CONFIG_SND_SOC_PCM179X_SPI=y CONFIG_SND_SOC_PCM186X=y CONFIG_SND_SOC_PCM186X_I2C=y CONFIG_SND_SOC_PCM186X_SPI=y CONFIG_SND_SOC_PCM3060=y CONFIG_SND_SOC_PCM3060_I2C=y CONFIG_SND_SOC_PCM3060_SPI=y CONFIG_SND_SOC_PCM3168A=y CONFIG_SND_SOC_PCM3168A_I2C=y CONFIG_SND_SOC_PCM3168A_SPI=y CONFIG_SND_SOC_PCM5102A=y CONFIG_SND_SOC_PCM512x=y CONFIG_SND_SOC_PCM512x_I2C=y CONFIG_SND_SOC_PCM512x_SPI=y CONFIG_SND_SOC_RK3328=y CONFIG_SND_SOC_RK817=y CONFIG_SND_SOC_RL6231=y CONFIG_SND_SOC_RL6347A=y CONFIG_SND_SOC_RT274=y CONFIG_SND_SOC_RT286=y CONFIG_SND_SOC_RT298=y CONFIG_SND_SOC_RT1011=y CONFIG_SND_SOC_RT1015=y CONFIG_SND_SOC_RT1015P=y CONFIG_SND_SOC_RT1019=y CONFIG_SND_SOC_RT1308=y CONFIG_SND_SOC_RT1308_SDW=y CONFIG_SND_SOC_RT1316_SDW=y CONFIG_SND_SOC_RT5514=y CONFIG_SND_SOC_RT5514_SPI=y CONFIG_SND_SOC_RT5616=y CONFIG_SND_SOC_RT5631=y CONFIG_SND_SOC_RT5640=y CONFIG_SND_SOC_RT5645=y CONFIG_SND_SOC_RT5651=y CONFIG_SND_SOC_RT5659=y CONFIG_SND_SOC_RT5660=y CONFIG_SND_SOC_RT5663=y CONFIG_SND_SOC_RT5670=y CONFIG_SND_SOC_RT5677=y CONFIG_SND_SOC_RT5677_SPI=y CONFIG_SND_SOC_RT5682=y CONFIG_SND_SOC_RT5682_I2C=y CONFIG_SND_SOC_RT5682_SDW=y CONFIG_SND_SOC_RT5682S=y CONFIG_SND_SOC_RT700=y CONFIG_SND_SOC_RT700_SDW=y CONFIG_SND_SOC_RT711=y CONFIG_SND_SOC_RT711_SDW=y CONFIG_SND_SOC_RT711_SDCA_SDW=y CONFIG_SND_SOC_RT715=y CONFIG_SND_SOC_RT715_SDW=y CONFIG_SND_SOC_RT715_SDCA_SDW=y CONFIG_SND_SOC_RT9120=y CONFIG_SND_SOC_SDW_MOCKUP=y CONFIG_SND_SOC_SGTL5000=y CONFIG_SND_SOC_SI476X=y CONFIG_SND_SOC_SIGMADSP=y CONFIG_SND_SOC_SIGMADSP_I2C=y CONFIG_SND_SOC_SIGMADSP_REGMAP=y CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y CONFIG_SND_SOC_SIMPLE_MUX=y CONFIG_SND_SOC_SPDIF=y CONFIG_SND_SOC_SRC4XXX_I2C=y CONFIG_SND_SOC_SRC4XXX=y CONFIG_SND_SOC_SSM2305=y CONFIG_SND_SOC_SSM2518=y CONFIG_SND_SOC_SSM2602=y CONFIG_SND_SOC_SSM2602_SPI=y CONFIG_SND_SOC_SSM2602_I2C=y CONFIG_SND_SOC_SSM4567=y CONFIG_SND_SOC_STA32X=y CONFIG_SND_SOC_STA350=y CONFIG_SND_SOC_STI_SAS=y CONFIG_SND_SOC_TAS2552=y CONFIG_SND_SOC_TAS2562=y CONFIG_SND_SOC_TAS2764=y CONFIG_SND_SOC_TAS2770=y CONFIG_SND_SOC_TAS2780=y CONFIG_SND_SOC_TAS5086=y CONFIG_SND_SOC_TAS571X=y CONFIG_SND_SOC_TAS5720=y CONFIG_SND_SOC_TAS5805M=y CONFIG_SND_SOC_TAS6424=y CONFIG_SND_SOC_TDA7419=y CONFIG_SND_SOC_TFA9879=y CONFIG_SND_SOC_TFA989X=y CONFIG_SND_SOC_TLV320ADC3XXX=y CONFIG_SND_SOC_TLV320AIC23=y CONFIG_SND_SOC_TLV320AIC23_I2C=y CONFIG_SND_SOC_TLV320AIC23_SPI=y CONFIG_SND_SOC_TLV320AIC31XX=y CONFIG_SND_SOC_TLV320AIC32X4=y CONFIG_SND_SOC_TLV320AIC32X4_I2C=y CONFIG_SND_SOC_TLV320AIC32X4_SPI=y CONFIG_SND_SOC_TLV320AIC3X=y CONFIG_SND_SOC_TLV320AIC3X_I2C=y CONFIG_SND_SOC_TLV320AIC3X_SPI=y CONFIG_SND_SOC_TLV320ADCX140=y CONFIG_SND_SOC_TS3A227E=y CONFIG_SND_SOC_TSCS42XX=y CONFIG_SND_SOC_TSCS454=y CONFIG_SND_SOC_UDA1334=y CONFIG_SND_SOC_WCD9335=y CONFIG_SND_SOC_WCD_MBHC=y CONFIG_SND_SOC_WCD934X=y CONFIG_SND_SOC_WCD938X=y CONFIG_SND_SOC_WCD938X_SDW=y CONFIG_SND_SOC_WM5102=y CONFIG_SND_SOC_WM8510=y CONFIG_SND_SOC_WM8523=y CONFIG_SND_SOC_WM8524=y CONFIG_SND_SOC_WM8580=y CONFIG_SND_SOC_WM8711=y CONFIG_SND_SOC_WM8728=y CONFIG_SND_SOC_WM8731=y CONFIG_SND_SOC_WM8731_I2C=y CONFIG_SND_SOC_WM8731_SPI=y CONFIG_SND_SOC_WM8737=y CONFIG_SND_SOC_WM8741=y CONFIG_SND_SOC_WM8750=y CONFIG_SND_SOC_WM8753=y CONFIG_SND_SOC_WM8770=y CONFIG_SND_SOC_WM8776=y CONFIG_SND_SOC_WM8782=y CONFIG_SND_SOC_WM8804=y CONFIG_SND_SOC_WM8804_I2C=y CONFIG_SND_SOC_WM8804_SPI=y CONFIG_SND_SOC_WM8903=y CONFIG_SND_SOC_WM8904=y CONFIG_SND_SOC_WM8940=y CONFIG_SND_SOC_WM8960=y CONFIG_SND_SOC_WM8961=y CONFIG_SND_SOC_WM8962=y CONFIG_SND_SOC_WM8974=y CONFIG_SND_SOC_WM8978=y CONFIG_SND_SOC_WM8985=y CONFIG_SND_SOC_WSA881X=y CONFIG_SND_SOC_WSA883X=y CONFIG_SND_SOC_ZL38060=y CONFIG_SND_SOC_MAX9759=y CONFIG_SND_SOC_MT6351=y CONFIG_SND_SOC_MT6358=y CONFIG_SND_SOC_MT6660=y CONFIG_SND_SOC_NAU8315=y CONFIG_SND_SOC_NAU8540=y CONFIG_SND_SOC_NAU8810=y CONFIG_SND_SOC_NAU8821=y CONFIG_SND_SOC_NAU8822=y CONFIG_SND_SOC_NAU8824=y CONFIG_SND_SOC_NAU8825=y CONFIG_SND_SOC_TPA6130A2=y CONFIG_SND_SOC_LPASS_MACRO_COMMON=y CONFIG_SND_SOC_LPASS_WSA_MACRO=y CONFIG_SND_SOC_LPASS_VA_MACRO=y CONFIG_SND_SOC_LPASS_RX_MACRO=y CONFIG_SND_SOC_LPASS_TX_MACRO=y # end of CODEC drivers CONFIG_SND_SIMPLE_CARD_UTILS=y CONFIG_SND_SIMPLE_CARD=y CONFIG_SND_AUDIO_GRAPH_CARD=y CONFIG_SND_AUDIO_GRAPH_CARD2=y CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=y CONFIG_SND_TEST_COMPONENT=y CONFIG_SND_X86=y CONFIG_HDMI_LPE_AUDIO=y CONFIG_SND_SYNTH_EMUX=y CONFIG_SND_VIRTIO=y CONFIG_AC97_BUS=y # # HID support # CONFIG_HID=y CONFIG_HID_BATTERY_STRENGTH=y CONFIG_HIDRAW=y CONFIG_UHID=y CONFIG_HID_GENERIC=y # # Special HID drivers # CONFIG_HID_A4TECH=y CONFIG_HID_ACCUTOUCH=y CONFIG_HID_ACRUX=y CONFIG_HID_ACRUX_FF=y CONFIG_HID_APPLE=y CONFIG_HID_APPLEIR=y CONFIG_HID_ASUS=y CONFIG_HID_AUREAL=y CONFIG_HID_BELKIN=y CONFIG_HID_BETOP_FF=y CONFIG_HID_BIGBEN_FF=y CONFIG_HID_CHERRY=y CONFIG_HID_CHICONY=y CONFIG_HID_CORSAIR=y CONFIG_HID_COUGAR=y CONFIG_HID_MACALLY=y CONFIG_HID_PRODIKEYS=y CONFIG_HID_CMEDIA=y CONFIG_HID_CP2112=y CONFIG_HID_CREATIVE_SB0540=y CONFIG_HID_CYPRESS=y CONFIG_HID_DRAGONRISE=y CONFIG_DRAGONRISE_FF=y CONFIG_HID_EMS_FF=y CONFIG_HID_ELAN=y CONFIG_HID_ELECOM=y CONFIG_HID_ELO=y CONFIG_HID_EZKEY=y CONFIG_HID_FT260=y CONFIG_HID_GEMBIRD=y CONFIG_HID_GFRM=y CONFIG_HID_GLORIOUS=y CONFIG_HID_HOLTEK=y CONFIG_HOLTEK_FF=y CONFIG_HID_VIVALDI_COMMON=y CONFIG_HID_GOOGLE_HAMMER=y CONFIG_HID_VIVALDI=y CONFIG_HID_GT683R=y CONFIG_HID_KEYTOUCH=y CONFIG_HID_KYE=y CONFIG_HID_UCLOGIC=y CONFIG_HID_WALTOP=y CONFIG_HID_VIEWSONIC=y CONFIG_HID_VRC2=y CONFIG_HID_XIAOMI=y CONFIG_HID_GYRATION=y CONFIG_HID_ICADE=y CONFIG_HID_ITE=y CONFIG_HID_JABRA=y CONFIG_HID_TWINHAN=y CONFIG_HID_KENSINGTON=y CONFIG_HID_LCPOWER=y CONFIG_HID_LED=y CONFIG_HID_LENOVO=y CONFIG_HID_LETSKETCH=y CONFIG_HID_LOGITECH=y CONFIG_HID_LOGITECH_DJ=y CONFIG_HID_LOGITECH_HIDPP=y CONFIG_LOGITECH_FF=y CONFIG_LOGIRUMBLEPAD2_FF=y CONFIG_LOGIG940_FF=y CONFIG_LOGIWHEELS_FF=y CONFIG_HID_MAGICMOUSE=y CONFIG_HID_MALTRON=y CONFIG_HID_MAYFLASH=y CONFIG_HID_MEGAWORLD_FF=y CONFIG_HID_REDRAGON=y CONFIG_HID_MICROSOFT=y CONFIG_HID_MONTEREY=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_NINTENDO=y CONFIG_NINTENDO_FF=y CONFIG_HID_NTI=y CONFIG_HID_NTRIG=y CONFIG_HID_ORTEK=y CONFIG_HID_PANTHERLORD=y CONFIG_PANTHERLORD_FF=y CONFIG_HID_PENMOUNT=y CONFIG_HID_PETALYNX=y CONFIG_HID_PICOLCD=y CONFIG_HID_PICOLCD_FB=y CONFIG_HID_PICOLCD_BACKLIGHT=y CONFIG_HID_PICOLCD_LCD=y CONFIG_HID_PICOLCD_LEDS=y CONFIG_HID_PICOLCD_CIR=y CONFIG_HID_PLANTRONICS=y CONFIG_HID_PLAYSTATION=y CONFIG_PLAYSTATION_FF=y CONFIG_HID_PXRC=y CONFIG_HID_RAZER=y CONFIG_HID_PRIMAX=y CONFIG_HID_RETRODE=y CONFIG_HID_ROCCAT=y CONFIG_HID_SAITEK=y CONFIG_HID_SAMSUNG=y CONFIG_HID_SEMITEK=y CONFIG_HID_SIGMAMICRO=y CONFIG_HID_SONY=y CONFIG_SONY_FF=y CONFIG_HID_SPEEDLINK=y CONFIG_HID_STEAM=y CONFIG_HID_STEELSERIES=y CONFIG_HID_SUNPLUS=y CONFIG_HID_RMI=y CONFIG_HID_GREENASIA=y CONFIG_GREENASIA_FF=y CONFIG_HID_HYPERV_MOUSE=y CONFIG_HID_SMARTJOYPLUS=y CONFIG_SMARTJOYPLUS_FF=y CONFIG_HID_TIVO=y CONFIG_HID_TOPSEED=y CONFIG_HID_TOPRE=y CONFIG_HID_THINGM=y CONFIG_HID_THRUSTMASTER=y CONFIG_THRUSTMASTER_FF=y CONFIG_HID_UDRAW_PS3=y CONFIG_HID_U2FZERO=y CONFIG_HID_WACOM=y CONFIG_HID_WIIMOTE=y CONFIG_HID_XINMO=y CONFIG_HID_ZEROPLUS=y CONFIG_ZEROPLUS_FF=y CONFIG_HID_ZYDACRON=y CONFIG_HID_SENSOR_HUB=y CONFIG_HID_SENSOR_CUSTOM_SENSOR=y CONFIG_HID_ALPS=y CONFIG_HID_MCP2221=y CONFIG_HID_KUNIT_TEST=y # end of Special HID drivers # # USB HID support # CONFIG_USB_HID=y CONFIG_HID_PID=y CONFIG_USB_HIDDEV=y # end of USB HID support # # I2C HID support # CONFIG_I2C_HID_ACPI=y CONFIG_I2C_HID_OF=y CONFIG_I2C_HID_OF_ELAN=y CONFIG_I2C_HID_OF_GOODIX=y # end of I2C HID support CONFIG_I2C_HID_CORE=y # # Surface System Aggregator Module HID support # CONFIG_SURFACE_HID=y CONFIG_SURFACE_KBD=y # end of Surface System Aggregator Module HID support CONFIG_SURFACE_HID_CORE=y # end of HID support CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=y CONFIG_USB_LED_TRIG=y CONFIG_USB_ULPI_BUS=y CONFIG_USB_CONN_GPIO=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y CONFIG_USB_PCI=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y # # Miscellaneous USB options # CONFIG_USB_DEFAULT_PERSIST=y CONFIG_USB_FEW_INIT_RETRIES=y CONFIG_USB_DYNAMIC_MINORS=y CONFIG_USB_OTG=y CONFIG_USB_OTG_PRODUCTLIST=y CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB=y CONFIG_USB_OTG_FSM=y CONFIG_USB_LEDS_TRIGGER_USBPORT=y CONFIG_USB_AUTOSUSPEND_DELAY=2 CONFIG_USB_MON=y # # USB Host Controller Drivers # CONFIG_USB_C67X00_HCD=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DBGCAP=y CONFIG_USB_XHCI_PCI=y CONFIG_USB_XHCI_PCI_RENESAS=y CONFIG_USB_XHCI_PLATFORM=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_EHCI_FSL=y CONFIG_USB_EHCI_HCD_PLATFORM=y CONFIG_USB_OXU210HP_HCD=y CONFIG_USB_ISP116X_HCD=y CONFIG_USB_FOTG210_HCD=y CONFIG_USB_MAX3421_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PCI=y CONFIG_USB_OHCI_HCD_SSB=y CONFIG_USB_OHCI_HCD_PLATFORM=y CONFIG_USB_UHCI_HCD=y CONFIG_USB_U132_HCD=y CONFIG_USB_SL811_HCD=y CONFIG_USB_SL811_HCD_ISO=y CONFIG_USB_SL811_CS=y CONFIG_USB_R8A66597_HCD=y CONFIG_USB_HCD_BCMA=y CONFIG_USB_HCD_SSB=y CONFIG_USB_HCD_TEST_MODE=y # # USB Device Class drivers # CONFIG_USB_ACM=y CONFIG_USB_PRINTER=y CONFIG_USB_WDM=y CONFIG_USB_TMC=y # # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # # also be needed; see USB_STORAGE Help for more info # CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE_DEBUG=y CONFIG_USB_STORAGE_REALTEK=y CONFIG_REALTEK_AUTOPM=y CONFIG_USB_STORAGE_DATAFAB=y CONFIG_USB_STORAGE_FREECOM=y CONFIG_USB_STORAGE_ISD200=y CONFIG_USB_STORAGE_USBAT=y CONFIG_USB_STORAGE_SDDR09=y CONFIG_USB_STORAGE_SDDR55=y CONFIG_USB_STORAGE_JUMPSHOT=y CONFIG_USB_STORAGE_ALAUDA=y CONFIG_USB_STORAGE_ONETOUCH=y CONFIG_USB_STORAGE_KARMA=y CONFIG_USB_STORAGE_CYPRESS_ATACB=y CONFIG_USB_STORAGE_ENE_UB6250=y CONFIG_USB_UAS=y # # USB Imaging devices # CONFIG_USB_MDC800=y CONFIG_USB_MICROTEK=y CONFIG_USBIP_CORE=y CONFIG_USBIP_VHCI_HCD=y CONFIG_USBIP_VHCI_HC_PORTS=8 CONFIG_USBIP_VHCI_NR_HCS=1 CONFIG_USBIP_HOST=y CONFIG_USBIP_VUDC=y CONFIG_USBIP_DEBUG=y CONFIG_USB_CDNS_SUPPORT=y CONFIG_USB_CDNS_HOST=y CONFIG_USB_CDNS3=y CONFIG_USB_CDNS3_GADGET=y CONFIG_USB_CDNS3_HOST=y CONFIG_USB_CDNS3_PCI_WRAP=y CONFIG_USB_CDNSP_PCI=y CONFIG_USB_CDNSP_GADGET=y CONFIG_USB_CDNSP_HOST=y CONFIG_USB_MUSB_HDRC=y # CONFIG_USB_MUSB_HOST is not set # CONFIG_USB_MUSB_GADGET is not set CONFIG_USB_MUSB_DUAL_ROLE=y # # Platform Glue Layer # # # MUSB DMA mode # CONFIG_MUSB_PIO_ONLY=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_ULPI=y # CONFIG_USB_DWC3_HOST is not set # CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_DWC3_DUAL_ROLE=y # # Platform Glue Driver Support # CONFIG_USB_DWC3_PCI=y CONFIG_USB_DWC3_HAPS=y CONFIG_USB_DWC3_OF_SIMPLE=y CONFIG_USB_DWC2=y # CONFIG_USB_DWC2_HOST is not set # # Gadget/Dual-role mode requires USB Gadget support to be enabled # # CONFIG_USB_DWC2_PERIPHERAL is not set CONFIG_USB_DWC2_DUAL_ROLE=y CONFIG_USB_DWC2_PCI=y CONFIG_USB_DWC2_DEBUG=y CONFIG_USB_DWC2_VERBOSE=y CONFIG_USB_DWC2_TRACK_MISSED_SOFS=y CONFIG_USB_DWC2_DEBUG_PERIODIC=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y CONFIG_USB_CHIPIDEA_PCI=y CONFIG_USB_CHIPIDEA_MSM=y CONFIG_USB_CHIPIDEA_IMX=y CONFIG_USB_CHIPIDEA_GENERIC=y CONFIG_USB_CHIPIDEA_TEGRA=y CONFIG_USB_ISP1760=y CONFIG_USB_ISP1760_HCD=y CONFIG_USB_ISP1761_UDC=y # CONFIG_USB_ISP1760_HOST_ROLE is not set # CONFIG_USB_ISP1760_GADGET_ROLE is not set CONFIG_USB_ISP1760_DUAL_ROLE=y # # USB port drivers # CONFIG_USB_USS720=y CONFIG_USB_SERIAL=y CONFIG_USB_SERIAL_CONSOLE=y CONFIG_USB_SERIAL_GENERIC=y CONFIG_USB_SERIAL_SIMPLE=y CONFIG_USB_SERIAL_AIRCABLE=y CONFIG_USB_SERIAL_ARK3116=y CONFIG_USB_SERIAL_BELKIN=y CONFIG_USB_SERIAL_CH341=y CONFIG_USB_SERIAL_WHITEHEAT=y CONFIG_USB_SERIAL_DIGI_ACCELEPORT=y CONFIG_USB_SERIAL_CP210X=y CONFIG_USB_SERIAL_CYPRESS_M8=y CONFIG_USB_SERIAL_EMPEG=y CONFIG_USB_SERIAL_FTDI_SIO=y CONFIG_USB_SERIAL_VISOR=y CONFIG_USB_SERIAL_IPAQ=y CONFIG_USB_SERIAL_IR=y CONFIG_USB_SERIAL_EDGEPORT=y CONFIG_USB_SERIAL_EDGEPORT_TI=y CONFIG_USB_SERIAL_F81232=y CONFIG_USB_SERIAL_F8153X=y CONFIG_USB_SERIAL_GARMIN=y CONFIG_USB_SERIAL_IPW=y CONFIG_USB_SERIAL_IUU=y CONFIG_USB_SERIAL_KEYSPAN_PDA=y CONFIG_USB_SERIAL_KEYSPAN=y CONFIG_USB_SERIAL_KLSI=y CONFIG_USB_SERIAL_KOBIL_SCT=y CONFIG_USB_SERIAL_MCT_U232=y CONFIG_USB_SERIAL_METRO=y CONFIG_USB_SERIAL_MOS7720=y CONFIG_USB_SERIAL_MOS7715_PARPORT=y CONFIG_USB_SERIAL_MOS7840=y CONFIG_USB_SERIAL_MXUPORT=y CONFIG_USB_SERIAL_NAVMAN=y CONFIG_USB_SERIAL_PL2303=y CONFIG_USB_SERIAL_OTI6858=y CONFIG_USB_SERIAL_QCAUX=y CONFIG_USB_SERIAL_QUALCOMM=y CONFIG_USB_SERIAL_SPCP8X5=y CONFIG_USB_SERIAL_SAFE=y CONFIG_USB_SERIAL_SAFE_PADDED=y CONFIG_USB_SERIAL_SIERRAWIRELESS=y CONFIG_USB_SERIAL_SYMBOL=y CONFIG_USB_SERIAL_TI=y CONFIG_USB_SERIAL_CYBERJACK=y CONFIG_USB_SERIAL_WWAN=y CONFIG_USB_SERIAL_OPTION=y CONFIG_USB_SERIAL_OMNINET=y CONFIG_USB_SERIAL_OPTICON=y CONFIG_USB_SERIAL_XSENS_MT=y CONFIG_USB_SERIAL_WISHBONE=y CONFIG_USB_SERIAL_SSU100=y CONFIG_USB_SERIAL_QT2=y CONFIG_USB_SERIAL_UPD78F0730=y CONFIG_USB_SERIAL_XR=y CONFIG_USB_SERIAL_DEBUG=y # # USB Miscellaneous drivers # CONFIG_USB_EMI62=y CONFIG_USB_EMI26=y CONFIG_USB_ADUTUX=y CONFIG_USB_SEVSEG=y CONFIG_USB_LEGOTOWER=y CONFIG_USB_LCD=y CONFIG_USB_CYPRESS_CY7C63=y CONFIG_USB_CYTHERM=y CONFIG_USB_IDMOUSE=y CONFIG_USB_FTDI_ELAN=y CONFIG_USB_APPLEDISPLAY=y CONFIG_APPLE_MFI_FASTCHARGE=y CONFIG_USB_SISUSBVGA=y CONFIG_USB_LD=y CONFIG_USB_TRANCEVIBRATOR=y CONFIG_USB_IOWARRIOR=y CONFIG_USB_TEST=y CONFIG_USB_EHSET_TEST_FIXTURE=y CONFIG_USB_ISIGHTFW=y CONFIG_USB_YUREX=y CONFIG_USB_EZUSB_FX2=y CONFIG_USB_HUB_USB251XB=y CONFIG_USB_HSIC_USB3503=y CONFIG_USB_HSIC_USB4604=y CONFIG_USB_LINK_LAYER_TEST=y CONFIG_USB_CHAOSKEY=y CONFIG_USB_ONBOARD_HUB=y CONFIG_USB_ATM=y CONFIG_USB_SPEEDTOUCH=y CONFIG_USB_CXACRU=y CONFIG_USB_UEAGLEATM=y CONFIG_USB_XUSBATM=y # # USB Physical Layer drivers # CONFIG_USB_PHY=y CONFIG_NOP_USB_XCEIV=y # CONFIG_USB_GPIO_VBUS is not set CONFIG_TAHVO_USB=y CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y CONFIG_USB_ISP1301=y # end of USB Physical Layer drivers CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DEBUG=y CONFIG_USB_GADGET_VERBOSE=y CONFIG_USB_GADGET_DEBUG_FILES=y CONFIG_USB_GADGET_DEBUG_FS=y CONFIG_USB_GADGET_VBUS_DRAW=2 CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 CONFIG_U_SERIAL_CONSOLE=y # # USB Peripheral Controller # CONFIG_USB_FUSB300=y CONFIG_USB_FOTG210_UDC=y CONFIG_USB_GR_UDC=y CONFIG_USB_R8A66597=y CONFIG_USB_PXA27X=y CONFIG_USB_MV_UDC=y CONFIG_USB_MV_U3D=y CONFIG_USB_SNP_CORE=y CONFIG_USB_SNP_UDC_PLAT=y CONFIG_USB_M66592=y CONFIG_USB_BDC_UDC=y CONFIG_USB_AMD5536UDC=y CONFIG_USB_NET2272=y CONFIG_USB_NET2272_DMA=y CONFIG_USB_NET2280=y CONFIG_USB_GOKU=y CONFIG_USB_EG20T=y CONFIG_USB_GADGET_XILINX=y CONFIG_USB_MAX3420_UDC=y CONFIG_USB_DUMMY_HCD=y # end of USB Peripheral Controller CONFIG_USB_LIBCOMPOSITE=y CONFIG_USB_F_ACM=y CONFIG_USB_F_SS_LB=y CONFIG_USB_U_SERIAL=y CONFIG_USB_U_ETHER=y CONFIG_USB_U_AUDIO=y CONFIG_USB_F_SERIAL=y CONFIG_USB_F_OBEX=y CONFIG_USB_F_NCM=y CONFIG_USB_F_ECM=y CONFIG_USB_F_PHONET=y CONFIG_USB_F_EEM=y CONFIG_USB_F_SUBSET=y CONFIG_USB_F_RNDIS=y CONFIG_USB_F_MASS_STORAGE=y CONFIG_USB_F_FS=y CONFIG_USB_F_UAC1=y CONFIG_USB_F_UAC1_LEGACY=y CONFIG_USB_F_UAC2=y CONFIG_USB_F_UVC=y CONFIG_USB_F_MIDI=y CONFIG_USB_F_HID=y CONFIG_USB_F_PRINTER=y CONFIG_USB_F_TCM=y CONFIG_USB_CONFIGFS=y CONFIG_USB_CONFIGFS_SERIAL=y CONFIG_USB_CONFIGFS_ACM=y CONFIG_USB_CONFIGFS_OBEX=y CONFIG_USB_CONFIGFS_NCM=y CONFIG_USB_CONFIGFS_ECM=y CONFIG_USB_CONFIGFS_ECM_SUBSET=y CONFIG_USB_CONFIGFS_RNDIS=y CONFIG_USB_CONFIGFS_EEM=y CONFIG_USB_CONFIGFS_PHONET=y CONFIG_USB_CONFIGFS_MASS_STORAGE=y CONFIG_USB_CONFIGFS_F_LB_SS=y CONFIG_USB_CONFIGFS_F_FS=y CONFIG_USB_CONFIGFS_F_UAC1=y CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y CONFIG_USB_CONFIGFS_F_UAC2=y CONFIG_USB_CONFIGFS_F_MIDI=y CONFIG_USB_CONFIGFS_F_HID=y CONFIG_USB_CONFIGFS_F_UVC=y CONFIG_USB_CONFIGFS_F_PRINTER=y CONFIG_USB_CONFIGFS_F_TCM=y # # USB Gadget precomposed configurations # CONFIG_USB_ZERO=y CONFIG_USB_ZERO_HNPTEST=y CONFIG_USB_AUDIO=y CONFIG_GADGET_UAC1=y CONFIG_GADGET_UAC1_LEGACY=y CONFIG_USB_ETH=y CONFIG_USB_ETH_RNDIS=y CONFIG_USB_ETH_EEM=y CONFIG_USB_G_NCM=y CONFIG_USB_GADGETFS=y CONFIG_USB_FUNCTIONFS=y CONFIG_USB_FUNCTIONFS_ETH=y CONFIG_USB_FUNCTIONFS_RNDIS=y CONFIG_USB_FUNCTIONFS_GENERIC=y CONFIG_USB_MASS_STORAGE=y CONFIG_USB_GADGET_TARGET=y CONFIG_USB_G_SERIAL=y CONFIG_USB_MIDI_GADGET=y CONFIG_USB_G_PRINTER=y CONFIG_USB_CDC_COMPOSITE=y CONFIG_USB_G_NOKIA=y CONFIG_USB_G_ACM_MS=y CONFIG_USB_G_MULTI=y CONFIG_USB_G_MULTI_RNDIS=y CONFIG_USB_G_MULTI_CDC=y CONFIG_USB_G_HID=y CONFIG_USB_G_DBGP=y # CONFIG_USB_G_DBGP_PRINTK is not set CONFIG_USB_G_DBGP_SERIAL=y CONFIG_USB_G_WEBCAM=y CONFIG_USB_RAW_GADGET=y # end of USB Gadget precomposed configurations CONFIG_TYPEC=y CONFIG_TYPEC_TCPM=y CONFIG_TYPEC_TCPCI=y CONFIG_TYPEC_RT1711H=y CONFIG_TYPEC_MT6360=y CONFIG_TYPEC_TCPCI_MT6370=y CONFIG_TYPEC_TCPCI_MAXIM=y CONFIG_TYPEC_FUSB302=y CONFIG_TYPEC_WCOVE=y CONFIG_TYPEC_UCSI=y CONFIG_UCSI_CCG=y CONFIG_UCSI_ACPI=y CONFIG_UCSI_STM32G0=y CONFIG_TYPEC_TPS6598X=y CONFIG_TYPEC_ANX7411=y CONFIG_TYPEC_RT1719=y CONFIG_TYPEC_HD3SS3220=y CONFIG_TYPEC_STUSB160X=y CONFIG_TYPEC_WUSB3801=y # # USB Type-C Multiplexer/DeMultiplexer Switch support # CONFIG_TYPEC_MUX_FSA4480=y CONFIG_TYPEC_MUX_PI3USB30532=y CONFIG_TYPEC_MUX_INTEL_PMC=y # end of USB Type-C Multiplexer/DeMultiplexer Switch support # # USB Type-C Alternate Mode drivers # CONFIG_TYPEC_DP_ALTMODE=y CONFIG_TYPEC_NVIDIA_ALTMODE=y # end of USB Type-C Alternate Mode drivers CONFIG_USB_ROLE_SWITCH=y CONFIG_USB_ROLES_INTEL_XHCI=y CONFIG_MMC=y CONFIG_PWRSEQ_EMMC=y CONFIG_PWRSEQ_SD8787=y CONFIG_PWRSEQ_SIMPLE=y CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_MINORS=8 CONFIG_SDIO_UART=y CONFIG_MMC_TEST=y CONFIG_MMC_CRYPTO=y # # MMC/SD/SDIO Host Controller Drivers # CONFIG_MMC_DEBUG=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_IO_ACCESSORS=y CONFIG_MMC_SDHCI_PCI=y CONFIG_MMC_RICOH_MMC=y CONFIG_MMC_SDHCI_ACPI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_OF_ARASAN=y CONFIG_MMC_SDHCI_OF_AT91=y CONFIG_MMC_SDHCI_OF_DWCMSHC=y CONFIG_MMC_SDHCI_CADENCE=y CONFIG_MMC_SDHCI_F_SDH30=y CONFIG_MMC_SDHCI_MILBEAUT=y CONFIG_MMC_WBSD=y CONFIG_MMC_ALCOR=y CONFIG_MMC_TIFM_SD=y CONFIG_MMC_SPI=y CONFIG_MMC_SDRICOH_CS=y CONFIG_MMC_CB710=y CONFIG_MMC_VIA_SDMMC=y CONFIG_MMC_VUB300=y CONFIG_MMC_USHC=y CONFIG_MMC_USDHI6ROL0=y CONFIG_MMC_REALTEK_PCI=y CONFIG_MMC_REALTEK_USB=y CONFIG_MMC_CQHCI=y CONFIG_MMC_HSQ=y CONFIG_MMC_TOSHIBA_PCI=y CONFIG_MMC_MTK=y CONFIG_MMC_SDHCI_XENON=y CONFIG_MMC_SDHCI_OMAP=y CONFIG_MMC_SDHCI_AM654=y CONFIG_MMC_SDHCI_EXTERNAL_DMA=y CONFIG_MMC_LITEX=y CONFIG_SCSI_UFSHCD=y CONFIG_SCSI_UFS_BSG=y CONFIG_SCSI_UFS_CRYPTO=y CONFIG_SCSI_UFS_HPB=y CONFIG_SCSI_UFS_FAULT_INJECTION=y CONFIG_SCSI_UFS_HWMON=y CONFIG_SCSI_UFSHCD_PCI=y CONFIG_SCSI_UFS_DWC_TC_PCI=y CONFIG_SCSI_UFSHCD_PLATFORM=y CONFIG_SCSI_UFS_CDNS_PLATFORM=y CONFIG_SCSI_UFS_DWC_TC_PLATFORM=y CONFIG_MEMSTICK=y CONFIG_MEMSTICK_DEBUG=y # # MemoryStick drivers # CONFIG_MEMSTICK_UNSAFE_RESUME=y CONFIG_MSPRO_BLOCK=y CONFIG_MS_BLOCK=y # # MemoryStick Host Controller Drivers # CONFIG_MEMSTICK_TIFM_MS=y CONFIG_MEMSTICK_JMICRON_38X=y CONFIG_MEMSTICK_R592=y CONFIG_MEMSTICK_REALTEK_PCI=y CONFIG_MEMSTICK_REALTEK_USB=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLASS_FLASH=y CONFIG_LEDS_CLASS_MULTICOLOR=y CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y # # LED drivers # CONFIG_LEDS_88PM860X=y CONFIG_LEDS_AN30259A=y CONFIG_LEDS_APU=y CONFIG_LEDS_AW2013=y CONFIG_LEDS_BCM6328=y CONFIG_LEDS_BCM6358=y CONFIG_LEDS_CPCAP=y CONFIG_LEDS_CR0014114=y CONFIG_LEDS_EL15203000=y CONFIG_LEDS_LM3530=y CONFIG_LEDS_LM3532=y CONFIG_LEDS_LM3533=y CONFIG_LEDS_LM3642=y CONFIG_LEDS_LM3692X=y CONFIG_LEDS_MT6323=y CONFIG_LEDS_NET48XX=y CONFIG_LEDS_WRAP=y CONFIG_LEDS_PCA9532=y CONFIG_LEDS_PCA9532_GPIO=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_LP3944=y CONFIG_LEDS_LP3952=y CONFIG_LEDS_LP50XX=y CONFIG_LEDS_LP55XX_COMMON=y CONFIG_LEDS_LP5521=y CONFIG_LEDS_LP5523=y CONFIG_LEDS_LP5562=y CONFIG_LEDS_LP8501=y CONFIG_LEDS_LP8788=y CONFIG_LEDS_LP8860=y CONFIG_LEDS_PCA955X=y CONFIG_LEDS_PCA955X_GPIO=y CONFIG_LEDS_PCA963X=y CONFIG_LEDS_WM831X_STATUS=y CONFIG_LEDS_WM8350=y CONFIG_LEDS_DA903X=y CONFIG_LEDS_DA9052=y CONFIG_LEDS_DAC124S085=y CONFIG_LEDS_PWM=y CONFIG_LEDS_REGULATOR=y CONFIG_LEDS_BD2802=y CONFIG_LEDS_INTEL_SS4200=y CONFIG_LEDS_LT3593=y CONFIG_LEDS_ADP5520=y CONFIG_LEDS_MC13783=y CONFIG_LEDS_TCA6507=y CONFIG_LEDS_TLC591XX=y CONFIG_LEDS_MAX77650=y CONFIG_LEDS_MAX8997=y CONFIG_LEDS_LM355x=y CONFIG_LEDS_OT200=y CONFIG_LEDS_MENF21BMC=y CONFIG_LEDS_IS31FL319X=y CONFIG_LEDS_IS31FL32XX=y # # LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) # CONFIG_LEDS_BLINKM=y CONFIG_LEDS_SYSCON=y CONFIG_LEDS_MLXCPLD=y CONFIG_LEDS_MLXREG=y CONFIG_LEDS_USER=y CONFIG_LEDS_NIC78BX=y CONFIG_LEDS_SPI_BYTE=y CONFIG_LEDS_TI_LMU_COMMON=y CONFIG_LEDS_LM3697=y CONFIG_LEDS_LM36274=y CONFIG_LEDS_TPS6105X=y CONFIG_LEDS_LGM=y # # Flash and Torch LED drivers # CONFIG_LEDS_AAT1290=y CONFIG_LEDS_AS3645A=y CONFIG_LEDS_KTD2692=y CONFIG_LEDS_LM3601X=y CONFIG_LEDS_MAX77693=y CONFIG_LEDS_MT6360=y CONFIG_LEDS_RT4505=y CONFIG_LEDS_RT8515=y CONFIG_LEDS_SGM3140=y # # RGB LED drivers # CONFIG_LEDS_PWM_MULTICOLOR=y CONFIG_LEDS_QCOM_LPG=y # # LED Triggers # CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_ONESHOT=y CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_MTD=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_ACTIVITY=y CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y # # iptables trigger is under Netfilter config (LED target) # CONFIG_LEDS_TRIGGER_TRANSIENT=y CONFIG_LEDS_TRIGGER_CAMERA=y CONFIG_LEDS_TRIGGER_PANIC=y CONFIG_LEDS_TRIGGER_NETDEV=y CONFIG_LEDS_TRIGGER_PATTERN=y CONFIG_LEDS_TRIGGER_AUDIO=y CONFIG_LEDS_TRIGGER_TTY=y # # Simple LED drivers # CONFIG_LEDS_SIEMENS_SIMATIC_IPC=y CONFIG_ACCESSIBILITY=y CONFIG_A11Y_BRAILLE_CONSOLE=y # # Speakup console speech # CONFIG_SPEAKUP=y CONFIG_SPEAKUP_SERIALIO=y CONFIG_SPEAKUP_SYNTH_ACNTSA=y CONFIG_SPEAKUP_SYNTH_ACNTPC=y CONFIG_SPEAKUP_SYNTH_APOLLO=y CONFIG_SPEAKUP_SYNTH_AUDPTR=y CONFIG_SPEAKUP_SYNTH_BNS=y CONFIG_SPEAKUP_SYNTH_DECTLK=y CONFIG_SPEAKUP_SYNTH_DECEXT=y CONFIG_SPEAKUP_SYNTH_DECPC=m CONFIG_SPEAKUP_SYNTH_DTLK=y CONFIG_SPEAKUP_SYNTH_KEYPC=y CONFIG_SPEAKUP_SYNTH_LTLK=y CONFIG_SPEAKUP_SYNTH_SOFT=y CONFIG_SPEAKUP_SYNTH_SPKOUT=y CONFIG_SPEAKUP_SYNTH_TXPRT=y CONFIG_SPEAKUP_SYNTH_DUMMY=y # end of Speakup console speech CONFIG_INFINIBAND=y CONFIG_INFINIBAND_USER_MAD=y CONFIG_INFINIBAND_USER_ACCESS=y CONFIG_INFINIBAND_USER_MEM=y CONFIG_INFINIBAND_ON_DEMAND_PAGING=y CONFIG_INFINIBAND_ADDR_TRANS=y CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y CONFIG_INFINIBAND_CXGB4=y CONFIG_INFINIBAND_IRDMA=y CONFIG_MLX4_INFINIBAND=y CONFIG_MLX5_INFINIBAND=y CONFIG_INFINIBAND_MTHCA=y CONFIG_INFINIBAND_MTHCA_DEBUG=y CONFIG_INFINIBAND_OCRDMA=y CONFIG_INFINIBAND_USNIC=y CONFIG_INFINIBAND_VMWARE_PVRDMA=y CONFIG_INFINIBAND_IPOIB=y CONFIG_INFINIBAND_IPOIB_CM=y CONFIG_INFINIBAND_IPOIB_DEBUG=y CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y CONFIG_INFINIBAND_SRP=y CONFIG_INFINIBAND_SRPT=y CONFIG_INFINIBAND_ISER=y CONFIG_INFINIBAND_ISERT=y CONFIG_INFINIBAND_RTRS=y CONFIG_INFINIBAND_RTRS_CLIENT=y CONFIG_INFINIBAND_RTRS_SERVER=y CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y CONFIG_EDAC=y CONFIG_EDAC_LEGACY_SYSFS=y CONFIG_EDAC_DEBUG=y CONFIG_EDAC_DECODE_MCE=y CONFIG_EDAC_GHES=y CONFIG_EDAC_AMD64=y CONFIG_EDAC_AMD76X=y CONFIG_EDAC_E7XXX=y CONFIG_EDAC_E752X=y CONFIG_EDAC_I82875P=y CONFIG_EDAC_I82975X=y CONFIG_EDAC_I3000=y CONFIG_EDAC_I3200=y CONFIG_EDAC_IE31200=y CONFIG_EDAC_X38=y CONFIG_EDAC_I5400=y CONFIG_EDAC_I7CORE=y CONFIG_EDAC_I82860=y CONFIG_EDAC_R82600=y # CONFIG_EDAC_I5000 is not set CONFIG_EDAC_I5100=y CONFIG_EDAC_I7300=y CONFIG_RTC_LIB=y CONFIG_RTC_MC146818_LIB=y CONFIG_RTC_CLASS=y CONFIG_RTC_HCTOSYS=y CONFIG_RTC_HCTOSYS_DEVICE="rtc0" CONFIG_RTC_SYSTOHC=y CONFIG_RTC_SYSTOHC_DEVICE="rtc0" CONFIG_RTC_DEBUG=y CONFIG_RTC_LIB_KUNIT_TEST=y CONFIG_RTC_NVMEM=y # # RTC interfaces # CONFIG_RTC_INTF_SYSFS=y CONFIG_RTC_INTF_PROC=y CONFIG_RTC_INTF_DEV=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_DRV_TEST=y # # I2C RTC drivers # CONFIG_RTC_DRV_88PM860X=y CONFIG_RTC_DRV_88PM80X=y CONFIG_RTC_DRV_ABB5ZES3=y CONFIG_RTC_DRV_ABEOZ9=y CONFIG_RTC_DRV_ABX80X=y CONFIG_RTC_DRV_AS3722=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_DS1307_CENTURY=y CONFIG_RTC_DRV_DS1374=y CONFIG_RTC_DRV_DS1374_WDT=y CONFIG_RTC_DRV_DS1672=y CONFIG_RTC_DRV_HYM8563=y CONFIG_RTC_DRV_LP8788=y CONFIG_RTC_DRV_MAX6900=y CONFIG_RTC_DRV_MAX8907=y CONFIG_RTC_DRV_MAX8925=y CONFIG_RTC_DRV_MAX8998=y CONFIG_RTC_DRV_MAX8997=y CONFIG_RTC_DRV_MAX77686=y CONFIG_RTC_DRV_NCT3018Y=y CONFIG_RTC_DRV_RK808=y CONFIG_RTC_DRV_RS5C372=y CONFIG_RTC_DRV_ISL1208=y CONFIG_RTC_DRV_ISL12022=y CONFIG_RTC_DRV_ISL12026=y CONFIG_RTC_DRV_X1205=y CONFIG_RTC_DRV_PCF8523=y CONFIG_RTC_DRV_PCF85063=y CONFIG_RTC_DRV_PCF85363=y CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_PCF8583=y CONFIG_RTC_DRV_M41T80=y CONFIG_RTC_DRV_M41T80_WDT=y CONFIG_RTC_DRV_BD70528=y CONFIG_RTC_DRV_BQ32K=y CONFIG_RTC_DRV_TWL4030=y CONFIG_RTC_DRV_PALMAS=y CONFIG_RTC_DRV_TPS6586X=y CONFIG_RTC_DRV_TPS65910=y CONFIG_RTC_DRV_RC5T583=y CONFIG_RTC_DRV_RC5T619=y CONFIG_RTC_DRV_S35390A=y CONFIG_RTC_DRV_FM3130=y CONFIG_RTC_DRV_RX8010=y CONFIG_RTC_DRV_RX8581=y CONFIG_RTC_DRV_RX8025=y CONFIG_RTC_DRV_EM3027=y CONFIG_RTC_DRV_RV3028=y CONFIG_RTC_DRV_RV3032=y CONFIG_RTC_DRV_RV8803=y CONFIG_RTC_DRV_S5M=y CONFIG_RTC_DRV_SD3078=y # # SPI RTC drivers # CONFIG_RTC_DRV_M41T93=y CONFIG_RTC_DRV_M41T94=y CONFIG_RTC_DRV_DS1302=y CONFIG_RTC_DRV_DS1305=y CONFIG_RTC_DRV_DS1343=y CONFIG_RTC_DRV_DS1347=y CONFIG_RTC_DRV_DS1390=y CONFIG_RTC_DRV_MAX6916=y CONFIG_RTC_DRV_R9701=y CONFIG_RTC_DRV_RX4581=y CONFIG_RTC_DRV_RS5C348=y CONFIG_RTC_DRV_MAX6902=y CONFIG_RTC_DRV_PCF2123=y CONFIG_RTC_DRV_MCP795=y CONFIG_RTC_I2C_AND_SPI=y # # SPI and I2C RTC drivers # CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_DS3232_HWMON=y CONFIG_RTC_DRV_PCF2127=y CONFIG_RTC_DRV_RV3029C2=y CONFIG_RTC_DRV_RV3029_HWMON=y CONFIG_RTC_DRV_RX6110=y # # Platform RTC drivers # CONFIG_RTC_DRV_CMOS=y CONFIG_RTC_DRV_DS1286=y CONFIG_RTC_DRV_DS1511=y CONFIG_RTC_DRV_DS1553=y CONFIG_RTC_DRV_DS1685_FAMILY=y CONFIG_RTC_DRV_DS1685=y # CONFIG_RTC_DRV_DS1689 is not set # CONFIG_RTC_DRV_DS17285 is not set # CONFIG_RTC_DRV_DS17485 is not set # CONFIG_RTC_DRV_DS17885 is not set CONFIG_RTC_DRV_DS1742=y CONFIG_RTC_DRV_DS2404=y CONFIG_RTC_DRV_DA9052=y CONFIG_RTC_DRV_DA9055=y CONFIG_RTC_DRV_DA9063=y CONFIG_RTC_DRV_STK17TA8=y CONFIG_RTC_DRV_M48T86=y CONFIG_RTC_DRV_M48T35=y CONFIG_RTC_DRV_M48T59=y CONFIG_RTC_DRV_MSM6242=y CONFIG_RTC_DRV_BQ4802=y CONFIG_RTC_DRV_RP5C01=y CONFIG_RTC_DRV_V3020=y CONFIG_RTC_DRV_WM831X=y CONFIG_RTC_DRV_WM8350=y CONFIG_RTC_DRV_PCF50633=y CONFIG_RTC_DRV_ZYNQMP=y CONFIG_RTC_DRV_CROS_EC=y CONFIG_RTC_DRV_NTXEC=y # # on-CPU RTC drivers # CONFIG_RTC_DRV_CADENCE=y CONFIG_RTC_DRV_FTRTC010=y CONFIG_RTC_DRV_PCAP=y CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MT6397=y CONFIG_RTC_DRV_R7301=y CONFIG_RTC_DRV_CPCAP=y # # HID Sensor RTC drivers # CONFIG_RTC_DRV_HID_SENSOR_TIME=y CONFIG_RTC_DRV_GOLDFISH=y CONFIG_RTC_DRV_WILCO_EC=y CONFIG_DMADEVICES=y CONFIG_DMADEVICES_DEBUG=y CONFIG_DMADEVICES_VDEBUG=y # # DMA Devices # CONFIG_DMA_ENGINE=y CONFIG_DMA_VIRTUAL_CHANNELS=y CONFIG_DMA_ACPI=y CONFIG_DMA_OF=y CONFIG_ALTERA_MSGDMA=y CONFIG_DW_AXI_DMAC=y CONFIG_FSL_EDMA=y CONFIG_INTEL_IDMA64=y CONFIG_PCH_DMA=y CONFIG_PLX_DMA=y CONFIG_TIMB_DMA=y CONFIG_XILINX_ZYNQMP_DPDMA=y CONFIG_QCOM_HIDMA_MGMT=y CONFIG_QCOM_HIDMA=y CONFIG_DW_DMAC_CORE=y CONFIG_DW_DMAC=y CONFIG_DW_DMAC_PCI=y CONFIG_DW_EDMA=y CONFIG_DW_EDMA_PCIE=y CONFIG_HSU_DMA=y CONFIG_HSU_DMA_PCI=y CONFIG_SF_PDMA=y CONFIG_INTEL_LDMA=y # # DMA Clients # CONFIG_ASYNC_TX_DMA=y CONFIG_DMATEST=y CONFIG_DMA_ENGINE_RAID=y # # DMABUF options # CONFIG_SYNC_FILE=y CONFIG_SW_SYNC=y CONFIG_UDMABUF=y CONFIG_DMABUF_MOVE_NOTIFY=y CONFIG_DMABUF_DEBUG=y CONFIG_DMABUF_SELFTESTS=y CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_SYSFS_STATS=y CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_DMABUF_HEAPS_CMA=y # end of DMABUF options CONFIG_AUXDISPLAY=y CONFIG_CHARLCD=y CONFIG_LINEDISP=y CONFIG_HD44780_COMMON=y CONFIG_HD44780=y CONFIG_KS0108=y CONFIG_KS0108_PORT=0x378 CONFIG_KS0108_DELAY=2 CONFIG_CFAG12864B=y CONFIG_CFAG12864B_RATE=20 CONFIG_IMG_ASCII_LCD=y CONFIG_HT16K33=y CONFIG_LCD2S=y CONFIG_PARPORT_PANEL=y CONFIG_PANEL_PARPORT=0 CONFIG_PANEL_PROFILE=5 CONFIG_PANEL_CHANGE_MESSAGE=y CONFIG_PANEL_BOOT_MESSAGE="" # CONFIG_CHARLCD_BL_OFF is not set # CONFIG_CHARLCD_BL_ON is not set CONFIG_CHARLCD_BL_FLASH=y CONFIG_PANEL=y CONFIG_UIO=y CONFIG_UIO_CIF=y CONFIG_UIO_PDRV_GENIRQ=y CONFIG_UIO_DMEM_GENIRQ=y CONFIG_UIO_AEC=y CONFIG_UIO_SERCOS3=y CONFIG_UIO_PCI_GENERIC=y CONFIG_UIO_NETX=y CONFIG_UIO_PRUSS=y CONFIG_UIO_MF624=y CONFIG_UIO_HV_GENERIC=y CONFIG_UIO_DFL=y CONFIG_VFIO=y CONFIG_VFIO_IOMMU_TYPE1=y CONFIG_VFIO_VIRQFD=y CONFIG_VFIO_NOIOMMU=y CONFIG_VFIO_PCI_CORE=y CONFIG_VFIO_PCI_MMAP=y CONFIG_VFIO_PCI_INTX=y CONFIG_VFIO_PCI=y CONFIG_VFIO_PCI_VGA=y CONFIG_VFIO_PCI_IGD=y CONFIG_MLX5_VFIO_PCI=y CONFIG_VFIO_MDEV=y CONFIG_IRQ_BYPASS_MANAGER=y CONFIG_VIRT_DRIVERS=y CONFIG_VMGENID=y CONFIG_VBOXGUEST=y CONFIG_NITRO_ENCLAVES=y CONFIG_NITRO_ENCLAVES_MISC_DEV_TEST=y CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO=y CONFIG_VIRTIO_PCI_LIB=y CONFIG_VIRTIO_PCI_LIB_LEGACY=y CONFIG_VIRTIO_MENU=y CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_PCI_LEGACY=y CONFIG_VIRTIO_VDPA=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_INPUT=y CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y CONFIG_VIRTIO_DMA_SHARED_BUFFER=y CONFIG_VDPA=y CONFIG_VDPA_SIM=y CONFIG_VDPA_SIM_NET=y CONFIG_VDPA_SIM_BLOCK=y CONFIG_VDPA_USER=y CONFIG_IFCVF=y CONFIG_MLX5_VDPA=y CONFIG_MLX5_VDPA_NET=y CONFIG_VP_VDPA=y CONFIG_ALIBABA_ENI_VDPA=y CONFIG_VHOST_IOTLB=y CONFIG_VHOST_RING=y CONFIG_VHOST=y CONFIG_VHOST_MENU=y CONFIG_VHOST_NET=y CONFIG_VHOST_SCSI=y CONFIG_VHOST_VSOCK=y CONFIG_VHOST_VDPA=y CONFIG_VHOST_CROSS_ENDIAN_LEGACY=y # # Microsoft Hyper-V guest support # CONFIG_HYPERV=y CONFIG_HYPERV_TIMER=y CONFIG_HYPERV_UTILS=y CONFIG_HYPERV_BALLOON=y # end of Microsoft Hyper-V guest support CONFIG_GREYBUS=y CONFIG_GREYBUS_ES2=y CONFIG_COMEDI=y CONFIG_COMEDI_DEBUG=y CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048 CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480 CONFIG_COMEDI_MISC_DRIVERS=y CONFIG_COMEDI_BOND=y CONFIG_COMEDI_TEST=y CONFIG_COMEDI_PARPORT=y CONFIG_COMEDI_SSV_DNP=y CONFIG_COMEDI_ISA_DRIVERS=y CONFIG_COMEDI_PCL711=y CONFIG_COMEDI_PCL724=y CONFIG_COMEDI_PCL726=y CONFIG_COMEDI_PCL730=y CONFIG_COMEDI_PCL812=y CONFIG_COMEDI_PCL816=y CONFIG_COMEDI_PCL818=y CONFIG_COMEDI_PCM3724=y CONFIG_COMEDI_AMPLC_DIO200_ISA=y CONFIG_COMEDI_AMPLC_PC236_ISA=y CONFIG_COMEDI_AMPLC_PC263_ISA=y CONFIG_COMEDI_RTI800=y CONFIG_COMEDI_RTI802=y CONFIG_COMEDI_DAC02=y CONFIG_COMEDI_DAS16M1=y CONFIG_COMEDI_DAS08_ISA=y CONFIG_COMEDI_DAS16=y CONFIG_COMEDI_DAS800=y CONFIG_COMEDI_DAS1800=y CONFIG_COMEDI_DAS6402=y CONFIG_COMEDI_DT2801=y CONFIG_COMEDI_DT2811=y CONFIG_COMEDI_DT2814=y CONFIG_COMEDI_DT2815=y CONFIG_COMEDI_DT2817=y CONFIG_COMEDI_DT282X=y CONFIG_COMEDI_DMM32AT=y CONFIG_COMEDI_FL512=y CONFIG_COMEDI_AIO_AIO12_8=y CONFIG_COMEDI_AIO_IIRO_16=y CONFIG_COMEDI_II_PCI20KC=y CONFIG_COMEDI_C6XDIGIO=y CONFIG_COMEDI_MPC624=y CONFIG_COMEDI_ADQ12B=y CONFIG_COMEDI_NI_AT_A2150=y CONFIG_COMEDI_NI_AT_AO=y CONFIG_COMEDI_NI_ATMIO=y CONFIG_COMEDI_NI_ATMIO16D=y CONFIG_COMEDI_NI_LABPC_ISA=y CONFIG_COMEDI_PCMAD=y CONFIG_COMEDI_PCMDA12=y CONFIG_COMEDI_PCMMIO=y CONFIG_COMEDI_PCMUIO=y CONFIG_COMEDI_MULTIQ3=y CONFIG_COMEDI_S526=y CONFIG_COMEDI_PCI_DRIVERS=y CONFIG_COMEDI_8255_PCI=y CONFIG_COMEDI_ADDI_WATCHDOG=y CONFIG_COMEDI_ADDI_APCI_1032=y CONFIG_COMEDI_ADDI_APCI_1500=y CONFIG_COMEDI_ADDI_APCI_1516=y CONFIG_COMEDI_ADDI_APCI_1564=y CONFIG_COMEDI_ADDI_APCI_16XX=y CONFIG_COMEDI_ADDI_APCI_2032=y CONFIG_COMEDI_ADDI_APCI_2200=y CONFIG_COMEDI_ADDI_APCI_3120=y CONFIG_COMEDI_ADDI_APCI_3501=y CONFIG_COMEDI_ADDI_APCI_3XXX=y CONFIG_COMEDI_ADL_PCI6208=y CONFIG_COMEDI_ADL_PCI7X3X=y CONFIG_COMEDI_ADL_PCI8164=y CONFIG_COMEDI_ADL_PCI9111=y CONFIG_COMEDI_ADL_PCI9118=y CONFIG_COMEDI_ADV_PCI1710=y CONFIG_COMEDI_ADV_PCI1720=y CONFIG_COMEDI_ADV_PCI1723=y CONFIG_COMEDI_ADV_PCI1724=y CONFIG_COMEDI_ADV_PCI1760=y CONFIG_COMEDI_ADV_PCI_DIO=y CONFIG_COMEDI_AMPLC_DIO200_PCI=y CONFIG_COMEDI_AMPLC_PC236_PCI=y CONFIG_COMEDI_AMPLC_PC263_PCI=y CONFIG_COMEDI_AMPLC_PCI224=y CONFIG_COMEDI_AMPLC_PCI230=y CONFIG_COMEDI_CONTEC_PCI_DIO=y CONFIG_COMEDI_DAS08_PCI=y CONFIG_COMEDI_DT3000=y CONFIG_COMEDI_DYNA_PCI10XX=y CONFIG_COMEDI_GSC_HPDI=y CONFIG_COMEDI_MF6X4=y CONFIG_COMEDI_ICP_MULTI=y CONFIG_COMEDI_DAQBOARD2000=y CONFIG_COMEDI_JR3_PCI=y CONFIG_COMEDI_KE_COUNTER=y CONFIG_COMEDI_CB_PCIDAS64=y CONFIG_COMEDI_CB_PCIDAS=y CONFIG_COMEDI_CB_PCIDDA=y CONFIG_COMEDI_CB_PCIMDAS=y CONFIG_COMEDI_CB_PCIMDDA=y CONFIG_COMEDI_ME4000=y CONFIG_COMEDI_ME_DAQ=y CONFIG_COMEDI_NI_6527=y CONFIG_COMEDI_NI_65XX=y CONFIG_COMEDI_NI_660X=y CONFIG_COMEDI_NI_670X=y CONFIG_COMEDI_NI_LABPC_PCI=y CONFIG_COMEDI_NI_PCIDIO=y CONFIG_COMEDI_NI_PCIMIO=y CONFIG_COMEDI_RTD520=y CONFIG_COMEDI_S626=y CONFIG_COMEDI_MITE=y CONFIG_COMEDI_NI_TIOCMD=y CONFIG_COMEDI_PCMCIA_DRIVERS=y CONFIG_COMEDI_CB_DAS16_CS=y CONFIG_COMEDI_DAS08_CS=y CONFIG_COMEDI_NI_DAQ_700_CS=y CONFIG_COMEDI_NI_DAQ_DIO24_CS=y CONFIG_COMEDI_NI_LABPC_CS=y CONFIG_COMEDI_NI_MIO_CS=y CONFIG_COMEDI_QUATECH_DAQP_CS=y CONFIG_COMEDI_USB_DRIVERS=y CONFIG_COMEDI_DT9812=y CONFIG_COMEDI_NI_USB6501=y CONFIG_COMEDI_USBDUX=y CONFIG_COMEDI_USBDUXFAST=y CONFIG_COMEDI_USBDUXSIGMA=y CONFIG_COMEDI_VMK80XX=y CONFIG_COMEDI_8254=y CONFIG_COMEDI_8255=y CONFIG_COMEDI_8255_SA=y CONFIG_COMEDI_KCOMEDILIB=y CONFIG_COMEDI_AMPLC_DIO200=y CONFIG_COMEDI_AMPLC_PC236=y CONFIG_COMEDI_DAS08=y CONFIG_COMEDI_ISADMA=y CONFIG_COMEDI_NI_LABPC=y CONFIG_COMEDI_NI_LABPC_ISADMA=y CONFIG_COMEDI_NI_TIO=y CONFIG_COMEDI_NI_ROUTING=y CONFIG_COMEDI_TESTS=y CONFIG_COMEDI_TESTS_EXAMPLE=y CONFIG_COMEDI_TESTS_NI_ROUTES=y CONFIG_STAGING=y CONFIG_PRISM2_USB=y CONFIG_RTL8192U=m CONFIG_RTLLIB=m CONFIG_RTLLIB_CRYPTO_CCMP=m CONFIG_RTLLIB_CRYPTO_TKIP=m CONFIG_RTLLIB_CRYPTO_WEP=m CONFIG_RTL8192E=m CONFIG_RTL8723BS=m CONFIG_R8712U=y CONFIG_R8188EU=m CONFIG_RTS5208=y CONFIG_VT6655=m CONFIG_VT6656=m # # IIO staging drivers # # # Accelerometers # CONFIG_ADIS16203=y CONFIG_ADIS16240=y # end of Accelerometers # # Analog to digital converters # CONFIG_AD7816=y # end of Analog to digital converters # # Analog digital bi-direction converters # CONFIG_ADT7316=y CONFIG_ADT7316_SPI=y CONFIG_ADT7316_I2C=y # end of Analog digital bi-direction converters # # Direct Digital Synthesis # CONFIG_AD9832=y CONFIG_AD9834=y # end of Direct Digital Synthesis # # Network Analyzer, Impedance Converters # CONFIG_AD5933=y # end of Network Analyzer, Impedance Converters # # Active energy metering IC # CONFIG_ADE7854=y CONFIG_ADE7854_I2C=y CONFIG_ADE7854_SPI=y # end of Active energy metering IC # # Resolver to digital converters # CONFIG_AD2S1210=y # end of Resolver to digital converters # end of IIO staging drivers CONFIG_FB_SM750=y CONFIG_STAGING_MEDIA=y CONFIG_INTEL_ATOMISP=y CONFIG_VIDEO_ATOMISP=y CONFIG_VIDEO_ATOMISP_ISP2401=y CONFIG_VIDEO_ATOMISP_OV2722=y CONFIG_VIDEO_ATOMISP_GC2235=y CONFIG_VIDEO_ATOMISP_MSRLIST_HELPER=y CONFIG_VIDEO_ATOMISP_MT9M114=y CONFIG_VIDEO_ATOMISP_GC0310=y CONFIG_VIDEO_ATOMISP_OV2680=y CONFIG_VIDEO_ATOMISP_OV5693=y CONFIG_VIDEO_ATOMISP_LM3554=y CONFIG_VIDEO_IPU3_IMGU=y CONFIG_VIDEO_MAX96712=y CONFIG_STAGING_MEDIA_DEPRECATED=y CONFIG_VIDEO_CPIA2=y CONFIG_VIDEO_MEYE=y CONFIG_VIDEO_SAA7146=y CONFIG_VIDEO_SAA7146_VV=y CONFIG_DVB_AV7110_IR=y CONFIG_DVB_AV7110=y CONFIG_DVB_AV7110_OSD=y CONFIG_DVB_BUDGET_PATCH=y CONFIG_DVB_SP8870=y CONFIG_VIDEO_HEXIUM_GEMINI=y CONFIG_VIDEO_HEXIUM_ORION=y CONFIG_VIDEO_MXB=y CONFIG_DVB_BUDGET_CORE=y CONFIG_DVB_BUDGET=y CONFIG_DVB_BUDGET_CI=y CONFIG_DVB_BUDGET_AV=y CONFIG_VIDEO_STKWEBCAM=y CONFIG_VIDEO_TM6000=y CONFIG_VIDEO_TM6000_ALSA=y CONFIG_VIDEO_TM6000_DVB=y CONFIG_USB_ZR364XX=y CONFIG_STAGING_BOARD=y CONFIG_LTE_GDM724X=m CONFIG_FB_TFT=y CONFIG_FB_TFT_AGM1264K_FL=y CONFIG_FB_TFT_BD663474=y CONFIG_FB_TFT_HX8340BN=y CONFIG_FB_TFT_HX8347D=y CONFIG_FB_TFT_HX8353D=y CONFIG_FB_TFT_HX8357D=y CONFIG_FB_TFT_ILI9163=y CONFIG_FB_TFT_ILI9320=y CONFIG_FB_TFT_ILI9325=y CONFIG_FB_TFT_ILI9340=y CONFIG_FB_TFT_ILI9341=y CONFIG_FB_TFT_ILI9481=y CONFIG_FB_TFT_ILI9486=y CONFIG_FB_TFT_PCD8544=y CONFIG_FB_TFT_RA8875=y CONFIG_FB_TFT_S6D02A1=y CONFIG_FB_TFT_S6D1121=y CONFIG_FB_TFT_SEPS525=y CONFIG_FB_TFT_SH1106=y CONFIG_FB_TFT_SSD1289=y CONFIG_FB_TFT_SSD1305=y CONFIG_FB_TFT_SSD1306=y CONFIG_FB_TFT_SSD1331=y CONFIG_FB_TFT_SSD1351=y CONFIG_FB_TFT_ST7735R=y CONFIG_FB_TFT_ST7789V=y CONFIG_FB_TFT_TINYLCD=y CONFIG_FB_TFT_TLS8204=y CONFIG_FB_TFT_UC1611=y CONFIG_FB_TFT_UC1701=y CONFIG_FB_TFT_UPD161704=y CONFIG_MOST_COMPONENTS=y CONFIG_MOST_NET=y CONFIG_MOST_VIDEO=y CONFIG_MOST_DIM2=y CONFIG_MOST_I2C=y CONFIG_KS7010=y CONFIG_GREYBUS_AUDIO=y CONFIG_GREYBUS_AUDIO_APB_CODEC=y CONFIG_GREYBUS_BOOTROM=y CONFIG_GREYBUS_FIRMWARE=y CONFIG_GREYBUS_HID=y CONFIG_GREYBUS_LIGHT=y CONFIG_GREYBUS_LOG=y CONFIG_GREYBUS_LOOPBACK=y CONFIG_GREYBUS_POWER=y CONFIG_GREYBUS_RAW=y CONFIG_GREYBUS_VIBRATOR=y CONFIG_GREYBUS_BRIDGED_PHY=y CONFIG_GREYBUS_GPIO=y CONFIG_GREYBUS_I2C=y CONFIG_GREYBUS_PWM=y CONFIG_GREYBUS_SDIO=y CONFIG_GREYBUS_SPI=y CONFIG_GREYBUS_UART=y CONFIG_GREYBUS_USB=y CONFIG_PI433=y CONFIG_XIL_AXIS_FIFO=y CONFIG_FIELDBUS_DEV=y CONFIG_HMS_ANYBUSS_BUS=y CONFIG_ARCX_ANYBUS_CONTROLLER=y CONFIG_HMS_PROFINET=y CONFIG_QLGE=y CONFIG_VME_BUS=y # # VME Bridge Drivers # CONFIG_VME_TSI148=y CONFIG_VME_FAKE=y # # VME Device Drivers # CONFIG_VME_USER=y CONFIG_GOLDFISH_PIPE=y CONFIG_CHROME_PLATFORMS=y CONFIG_CHROMEOS_ACPI=y CONFIG_CHROMEOS_LAPTOP=y CONFIG_CHROMEOS_PSTORE=y CONFIG_CHROMEOS_TBMC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_RPMSG=y CONFIG_CROS_EC_SPI=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_PROTO=y CONFIG_CROS_KBD_LED_BACKLIGHT=y CONFIG_CROS_EC_CHARDEV=y CONFIG_CROS_EC_LIGHTBAR=y CONFIG_CROS_EC_VBC=y CONFIG_CROS_EC_DEBUGFS=y CONFIG_CROS_EC_SENSORHUB=y CONFIG_CROS_EC_SYSFS=y CONFIG_CROS_EC_TYPEC=y CONFIG_CROS_USBPD_LOGGER=y CONFIG_CROS_USBPD_NOTIFY=y CONFIG_CHROMEOS_PRIVACY_SCREEN=y CONFIG_CROS_TYPEC_SWITCH=y CONFIG_WILCO_EC=y CONFIG_WILCO_EC_DEBUGFS=y CONFIG_WILCO_EC_EVENTS=y CONFIG_WILCO_EC_TELEMETRY=y CONFIG_CROS_KUNIT=y CONFIG_MELLANOX_PLATFORM=y CONFIG_MLXREG_HOTPLUG=y CONFIG_MLXREG_IO=y CONFIG_MLXREG_LC=y CONFIG_NVSW_SN2201=y CONFIG_OLPC_EC=y CONFIG_SURFACE_PLATFORMS=y CONFIG_SURFACE3_WMI=y CONFIG_SURFACE_3_POWER_OPREGION=y CONFIG_SURFACE_ACPI_NOTIFY=y CONFIG_SURFACE_AGGREGATOR_CDEV=y CONFIG_SURFACE_AGGREGATOR_HUB=y CONFIG_SURFACE_AGGREGATOR_REGISTRY=y CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=y CONFIG_SURFACE_DTX=y CONFIG_SURFACE_GPE=y CONFIG_SURFACE_HOTPLUG=y CONFIG_SURFACE_PLATFORM_PROFILE=y CONFIG_SURFACE_PRO3_BUTTON=y CONFIG_SURFACE_AGGREGATOR=y CONFIG_SURFACE_AGGREGATOR_BUS=y CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION=y CONFIG_X86_PLATFORM_DEVICES=y CONFIG_ACPI_WMI=y CONFIG_WMI_BMOF=y CONFIG_HUAWEI_WMI=y CONFIG_MXM_WMI=y CONFIG_PEAQ_WMI=y CONFIG_NVIDIA_WMI_EC_BACKLIGHT=y CONFIG_XIAOMI_WMI=y CONFIG_GIGABYTE_WMI=y CONFIG_YOGABOOK_WMI=y CONFIG_ACERHDF=y CONFIG_ACER_WIRELESS=y CONFIG_ACER_WMI=y CONFIG_AMD_PMF=y CONFIG_AMD_PMC=y CONFIG_ADV_SWBUTTON=y CONFIG_APPLE_GMUX=y CONFIG_ASUS_LAPTOP=y CONFIG_ASUS_WIRELESS=y CONFIG_ASUS_WMI=y CONFIG_ASUS_NB_WMI=y CONFIG_ASUS_TF103C_DOCK=y CONFIG_MERAKI_MX100=y CONFIG_EEEPC_LAPTOP=y CONFIG_EEEPC_WMI=y CONFIG_X86_PLATFORM_DRIVERS_DELL=y CONFIG_ALIENWARE_WMI=y CONFIG_DCDBAS=y CONFIG_DELL_LAPTOP=y CONFIG_DELL_RBU=y CONFIG_DELL_RBTN=y CONFIG_DELL_SMBIOS=y CONFIG_DELL_SMBIOS_WMI=y CONFIG_DELL_SMBIOS_SMM=y CONFIG_DELL_SMO8800=y CONFIG_DELL_WMI=y CONFIG_DELL_WMI_PRIVACY=y CONFIG_DELL_WMI_AIO=y CONFIG_DELL_WMI_DESCRIPTOR=y CONFIG_DELL_WMI_LED=y CONFIG_DELL_WMI_SYSMAN=y CONFIG_AMILO_RFKILL=y CONFIG_FUJITSU_LAPTOP=y CONFIG_FUJITSU_TABLET=y CONFIG_GPD_POCKET_FAN=y CONFIG_HP_ACCEL=y CONFIG_WIRELESS_HOTKEY=y CONFIG_HP_WMI=y CONFIG_TC1100_WMI=y CONFIG_IBM_RTL=y CONFIG_IDEAPAD_LAPTOP=y CONFIG_SENSORS_HDAPS=y CONFIG_THINKPAD_ACPI=y CONFIG_THINKPAD_ACPI_ALSA_SUPPORT=y CONFIG_THINKPAD_ACPI_DEBUGFACILITIES=y CONFIG_THINKPAD_ACPI_DEBUG=y CONFIG_THINKPAD_ACPI_UNSAFE_LEDS=y CONFIG_THINKPAD_ACPI_VIDEO=y CONFIG_THINKPAD_ACPI_HOTKEY_POLL=y CONFIG_THINKPAD_LMI=y CONFIG_INTEL_ATOMISP2_PDX86=y CONFIG_INTEL_ATOMISP2_LED=y CONFIG_INTEL_SAR_INT1092=y CONFIG_INTEL_SKL_INT3472=y CONFIG_INTEL_PMC_CORE=y CONFIG_INTEL_PMT_CLASS=y CONFIG_INTEL_PMT_TELEMETRY=y CONFIG_INTEL_PMT_CRASHLOG=y CONFIG_INTEL_WMI=y CONFIG_INTEL_WMI_SBL_FW_UPDATE=y CONFIG_INTEL_WMI_THUNDERBOLT=y CONFIG_INTEL_HID_EVENT=y CONFIG_INTEL_VBTN=y CONFIG_INTEL_INT0002_VGPIO=y CONFIG_INTEL_OAKTRAIL=y CONFIG_INTEL_BXTWC_PMIC_TMU=y CONFIG_INTEL_CHTDC_TI_PWRBTN=y CONFIG_INTEL_CHTWC_INT33FE=y CONFIG_INTEL_MRFLD_PWRBTN=y CONFIG_INTEL_PUNIT_IPC=y CONFIG_INTEL_RST=y CONFIG_INTEL_SMARTCONNECT=y CONFIG_INTEL_VSEC=y CONFIG_MSI_LAPTOP=y CONFIG_MSI_WMI=y CONFIG_XO15_EBOOK=y CONFIG_XO1_RFKILL=y CONFIG_PCENGINES_APU2=y CONFIG_BARCO_P50_GPIO=y CONFIG_SAMSUNG_LAPTOP=y CONFIG_SAMSUNG_Q10=y CONFIG_ACPI_TOSHIBA=y CONFIG_TOSHIBA_BT_RFKILL=y CONFIG_TOSHIBA_HAPS=y CONFIG_TOSHIBA_WMI=y CONFIG_ACPI_CMPC=y CONFIG_COMPAL_LAPTOP=y CONFIG_LG_LAPTOP=y CONFIG_PANASONIC_LAPTOP=y CONFIG_SONY_LAPTOP=y CONFIG_SONYPI_COMPAT=y CONFIG_SYSTEM76_ACPI=y CONFIG_TOPSTAR_LAPTOP=y CONFIG_SERIAL_MULTI_INSTANTIATE=y CONFIG_MLX_PLATFORM=y CONFIG_TOUCHSCREEN_DMI=y CONFIG_X86_ANDROID_TABLETS=y CONFIG_FW_ATTR_CLASS=y CONFIG_INTEL_IMR=y CONFIG_INTEL_IPS=y CONFIG_INTEL_SCU_IPC=y CONFIG_INTEL_SCU=y CONFIG_INTEL_SCU_PCI=y CONFIG_INTEL_SCU_PLATFORM=y CONFIG_INTEL_SCU_WDT=y CONFIG_INTEL_SCU_IPC_UTIL=y CONFIG_SIEMENS_SIMATIC_IPC=y CONFIG_WINMATE_FM07_KEYS=y CONFIG_P2SB=y CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_WM831X=y CONFIG_LMK04832=y CONFIG_COMMON_CLK_MAX77686=y CONFIG_COMMON_CLK_MAX9485=y CONFIG_COMMON_CLK_RK808=y CONFIG_COMMON_CLK_SI5341=y CONFIG_COMMON_CLK_SI5351=y CONFIG_COMMON_CLK_SI514=y CONFIG_COMMON_CLK_SI544=y CONFIG_COMMON_CLK_SI570=y CONFIG_COMMON_CLK_CDCE706=y CONFIG_COMMON_CLK_TPS68470=y CONFIG_COMMON_CLK_CDCE925=y CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_S2MPS11=y CONFIG_CLK_TWL6040=y CONFIG_COMMON_CLK_AXI_CLKGEN=y CONFIG_COMMON_CLK_LOCHNAGAR=y CONFIG_COMMON_CLK_PALMAS=y CONFIG_COMMON_CLK_PWM=y CONFIG_COMMON_CLK_RS9_PCIE=y CONFIG_COMMON_CLK_VC5=y CONFIG_COMMON_CLK_VC7=y CONFIG_COMMON_CLK_BD718XX=y CONFIG_COMMON_CLK_FIXED_MMIO=y CONFIG_CLK_LGM_CGU=y CONFIG_XILINX_VCU=y CONFIG_COMMON_CLK_XLNX_CLKWZRD=y CONFIG_CLK_KUNIT_TEST=y CONFIG_CLK_GATE_KUNIT_TEST=y CONFIG_HWSPINLOCK=y # # Clock Source drivers # CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y CONFIG_CLKSRC_I8253=y CONFIG_CLKEVT_I8253=y CONFIG_I8253_LOCK=y CONFIG_CLKBLD_I8253=y CONFIG_DW_APB_TIMER=y CONFIG_MICROCHIP_PIT64B=y # end of Clock Source drivers CONFIG_MAILBOX=y CONFIG_PLATFORM_MHU=y CONFIG_PCC=y CONFIG_ALTERA_MBOX=y CONFIG_MAILBOX_TEST=y CONFIG_IOMMU_IOVA=y CONFIG_IOASID=y CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y # # Generic IOMMU Pagetable Support # # end of Generic IOMMU Pagetable Support CONFIG_IOMMU_DEBUGFS=y # CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set CONFIG_IOMMU_DEFAULT_DMA_LAZY=y # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_IOMMU_DMA=y CONFIG_DMAR_TABLE=y CONFIG_DMAR_PERF=y CONFIG_DMAR_DEBUG=y CONFIG_INTEL_IOMMU=y CONFIG_INTEL_IOMMU_DEBUGFS=y CONFIG_INTEL_IOMMU_DEFAULT_ON=y CONFIG_INTEL_IOMMU_FLOPPY_WA=y CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON=y CONFIG_HYPERV_IOMMU=y CONFIG_VIRTIO_IOMMU=y # # Remoteproc drivers # CONFIG_REMOTEPROC=y CONFIG_REMOTEPROC_CDEV=y # end of Remoteproc drivers # # Rpmsg drivers # CONFIG_RPMSG=y CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_CTRL=y CONFIG_RPMSG_NS=y CONFIG_RPMSG_QCOM_GLINK=y CONFIG_RPMSG_QCOM_GLINK_RPM=y CONFIG_RPMSG_VIRTIO=y # end of Rpmsg drivers CONFIG_SOUNDWIRE=y # # SoundWire Devices # CONFIG_SOUNDWIRE_CADENCE=y CONFIG_SOUNDWIRE_INTEL=y CONFIG_SOUNDWIRE_QCOM=y CONFIG_SOUNDWIRE_GENERIC_ALLOCATION=y # # SOC (System On Chip) specific Drivers # # # Amlogic SoC drivers # # end of Amlogic SoC drivers # # Broadcom SoC drivers # # end of Broadcom SoC drivers # # NXP/Freescale QorIQ SoC drivers # # end of NXP/Freescale QorIQ SoC drivers # # fujitsu SoC drivers # # end of fujitsu SoC drivers # # i.MX SoC drivers # # end of i.MX SoC drivers # # Enable LiteX SoC Builder specific drivers # CONFIG_LITEX=y CONFIG_LITEX_SOC_CONTROLLER=y # end of Enable LiteX SoC Builder specific drivers # # Qualcomm SoC drivers # CONFIG_QCOM_QMI_HELPERS=y # end of Qualcomm SoC drivers CONFIG_SOC_TI=y # # Xilinx SoC drivers # # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers CONFIG_PM_DEVFREQ=y # # DEVFREQ Governors # CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_DEVFREQ_GOV_PASSIVE=y # # DEVFREQ Drivers # CONFIG_PM_DEVFREQ_EVENT=y CONFIG_EXTCON=y # # Extcon Device Drivers # CONFIG_EXTCON_ADC_JACK=y CONFIG_EXTCON_AXP288=y CONFIG_EXTCON_FSA9480=y CONFIG_EXTCON_GPIO=y CONFIG_EXTCON_INTEL_INT3496=y CONFIG_EXTCON_INTEL_CHT_WC=y CONFIG_EXTCON_INTEL_MRFLD=y CONFIG_EXTCON_MAX14577=y CONFIG_EXTCON_MAX3355=y CONFIG_EXTCON_MAX77693=y CONFIG_EXTCON_MAX77843=y CONFIG_EXTCON_MAX8997=y CONFIG_EXTCON_PALMAS=y CONFIG_EXTCON_PTN5150=y CONFIG_EXTCON_RT8973A=y CONFIG_EXTCON_SM5502=y CONFIG_EXTCON_USB_GPIO=y CONFIG_EXTCON_USBC_CROS_EC=y CONFIG_EXTCON_USBC_TUSB320=y CONFIG_MEMORY=y CONFIG_FPGA_DFL_EMIF=y CONFIG_IIO=y CONFIG_IIO_BUFFER=y CONFIG_IIO_BUFFER_CB=y CONFIG_IIO_BUFFER_DMA=y CONFIG_IIO_BUFFER_DMAENGINE=y CONFIG_IIO_BUFFER_HW_CONSUMER=y CONFIG_IIO_KFIFO_BUF=y CONFIG_IIO_TRIGGERED_BUFFER=y CONFIG_IIO_CONFIGFS=y CONFIG_IIO_TRIGGER=y CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 CONFIG_IIO_SW_DEVICE=y CONFIG_IIO_SW_TRIGGER=y CONFIG_IIO_TRIGGERED_EVENT=y # # Accelerometers # CONFIG_ADIS16201=y CONFIG_ADIS16209=y CONFIG_ADXL313=y CONFIG_ADXL313_I2C=y CONFIG_ADXL313_SPI=y CONFIG_ADXL355=y CONFIG_ADXL355_I2C=y CONFIG_ADXL355_SPI=y CONFIG_ADXL367=y CONFIG_ADXL367_SPI=y CONFIG_ADXL367_I2C=y CONFIG_ADXL372=y CONFIG_ADXL372_SPI=y CONFIG_ADXL372_I2C=y CONFIG_BMA220=y CONFIG_BMA400=y CONFIG_BMA400_I2C=y CONFIG_BMA400_SPI=y CONFIG_BMC150_ACCEL=y CONFIG_BMC150_ACCEL_I2C=y CONFIG_BMC150_ACCEL_SPI=y CONFIG_BMI088_ACCEL=y CONFIG_BMI088_ACCEL_SPI=y CONFIG_DA280=y CONFIG_DA311=y CONFIG_DMARD06=y CONFIG_DMARD09=y CONFIG_DMARD10=y CONFIG_FXLS8962AF=y CONFIG_FXLS8962AF_I2C=y CONFIG_FXLS8962AF_SPI=y CONFIG_HID_SENSOR_ACCEL_3D=y CONFIG_IIO_CROS_EC_ACCEL_LEGACY=y CONFIG_KXSD9=y CONFIG_KXSD9_SPI=y CONFIG_KXSD9_I2C=y CONFIG_KXCJK1013=y CONFIG_MC3230=y CONFIG_MMA7455=y CONFIG_MMA7455_I2C=y CONFIG_MMA7455_SPI=y CONFIG_MMA7660=y CONFIG_MMA8452=y CONFIG_MMA9551_CORE=y CONFIG_MMA9551=y CONFIG_MMA9553=y CONFIG_MSA311=y CONFIG_MXC4005=y CONFIG_MXC6255=y CONFIG_SCA3000=y CONFIG_SCA3300=y CONFIG_STK8312=y CONFIG_STK8BA50=y # end of Accelerometers # # Analog to digital converters # CONFIG_AD_SIGMA_DELTA=y CONFIG_AD7091R5=y CONFIG_AD7124=y CONFIG_AD7192=y CONFIG_AD7266=y CONFIG_AD7280=y CONFIG_AD7291=y CONFIG_AD7292=y CONFIG_AD7298=y CONFIG_AD7476=y CONFIG_AD7606=y CONFIG_AD7606_IFACE_PARALLEL=y CONFIG_AD7606_IFACE_SPI=y CONFIG_AD7766=y CONFIG_AD7768_1=y CONFIG_AD7780=y CONFIG_AD7791=y CONFIG_AD7793=y CONFIG_AD7887=y CONFIG_AD7923=y CONFIG_AD7949=y CONFIG_AD799X=y CONFIG_AD9467=y CONFIG_ADI_AXI_ADC=y CONFIG_AXP20X_ADC=y CONFIG_AXP288_ADC=y CONFIG_CC10001_ADC=y CONFIG_CPCAP_ADC=y CONFIG_DA9150_GPADC=y CONFIG_DLN2_ADC=y CONFIG_ENVELOPE_DETECTOR=y CONFIG_HI8435=y CONFIG_HX711=y CONFIG_INTEL_MRFLD_ADC=y CONFIG_LP8788_ADC=y CONFIG_LTC2471=y CONFIG_LTC2485=y CONFIG_LTC2496=y CONFIG_LTC2497=y CONFIG_MAX1027=y CONFIG_MAX11100=y CONFIG_MAX1118=y CONFIG_MAX11205=y CONFIG_MAX1241=y CONFIG_MAX1363=y CONFIG_MAX9611=y CONFIG_MCP320X=y CONFIG_MCP3422=y CONFIG_MCP3911=y CONFIG_MEDIATEK_MT6360_ADC=y CONFIG_MEN_Z188_ADC=y CONFIG_MP2629_ADC=y CONFIG_NAU7802=y CONFIG_PALMAS_GPADC=y CONFIG_QCOM_VADC_COMMON=y CONFIG_QCOM_SPMI_IADC=y CONFIG_QCOM_SPMI_VADC=y CONFIG_QCOM_SPMI_ADC5=y CONFIG_RN5T618_ADC=y CONFIG_RICHTEK_RTQ6056=y CONFIG_SD_ADC_MODULATOR=y CONFIG_STMPE_ADC=y CONFIG_TI_ADC081C=y CONFIG_TI_ADC0832=y CONFIG_TI_ADC084S021=y CONFIG_TI_ADC12138=y CONFIG_TI_ADC108S102=y CONFIG_TI_ADC128S052=y CONFIG_TI_ADC161S626=y CONFIG_TI_ADS1015=y CONFIG_TI_ADS7950=y CONFIG_TI_ADS8344=y CONFIG_TI_ADS8688=y CONFIG_TI_ADS124S08=y CONFIG_TI_ADS131E08=y CONFIG_TI_AM335X_ADC=y CONFIG_TI_TLC4541=y CONFIG_TI_TSC2046=y CONFIG_TWL4030_MADC=y CONFIG_TWL6030_GPADC=y CONFIG_VF610_ADC=y CONFIG_VIPERBOARD_ADC=y CONFIG_XILINX_XADC=y # end of Analog to digital converters # # Analog to digital and digital to analog converters # CONFIG_AD74413R=y CONFIG_STX104=y # end of Analog to digital and digital to analog converters # # Analog Front Ends # CONFIG_IIO_RESCALE=y # end of Analog Front Ends # # Amplifiers # CONFIG_AD8366=y CONFIG_ADA4250=y CONFIG_HMC425=y # end of Amplifiers # # Capacitance to digital converters # CONFIG_AD7150=y CONFIG_AD7746=y # end of Capacitance to digital converters # # Chemical Sensors # CONFIG_ATLAS_PH_SENSOR=y CONFIG_ATLAS_EZO_SENSOR=y CONFIG_BME680=y CONFIG_BME680_I2C=y CONFIG_BME680_SPI=y CONFIG_CCS811=y CONFIG_IAQCORE=y CONFIG_PMS7003=y CONFIG_SCD30_CORE=y CONFIG_SCD30_I2C=y CONFIG_SCD30_SERIAL=y CONFIG_SCD4X=y CONFIG_SENSIRION_SGP30=y CONFIG_SENSIRION_SGP40=y CONFIG_SPS30=y CONFIG_SPS30_I2C=y CONFIG_SPS30_SERIAL=y CONFIG_SENSEAIR_SUNRISE_CO2=y CONFIG_VZ89X=y # end of Chemical Sensors CONFIG_IIO_CROS_EC_SENSORS_CORE=y CONFIG_IIO_CROS_EC_SENSORS=y CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=y # # Hid Sensor IIO Common # CONFIG_HID_SENSOR_IIO_COMMON=y CONFIG_HID_SENSOR_IIO_TRIGGER=y # end of Hid Sensor IIO Common CONFIG_IIO_MS_SENSORS_I2C=y # # IIO SCMI Sensors # # end of IIO SCMI Sensors # # SSP Sensor Common # CONFIG_IIO_SSP_SENSORS_COMMONS=y CONFIG_IIO_SSP_SENSORHUB=y # end of SSP Sensor Common CONFIG_IIO_ST_SENSORS_I2C=y CONFIG_IIO_ST_SENSORS_SPI=y CONFIG_IIO_ST_SENSORS_CORE=y # # Digital to analog converters # CONFIG_AD3552R=y CONFIG_AD5064=y CONFIG_AD5360=y CONFIG_AD5380=y CONFIG_AD5421=y CONFIG_AD5446=y CONFIG_AD5449=y CONFIG_AD5592R_BASE=y CONFIG_AD5592R=y CONFIG_AD5593R=y CONFIG_AD5504=y CONFIG_AD5624R_SPI=y CONFIG_LTC2688=y CONFIG_AD5686=y CONFIG_AD5686_SPI=y CONFIG_AD5696_I2C=y CONFIG_AD5755=y CONFIG_AD5758=y CONFIG_AD5761=y CONFIG_AD5764=y CONFIG_AD5766=y CONFIG_AD5770R=y CONFIG_AD5791=y CONFIG_AD7293=y CONFIG_AD7303=y CONFIG_AD8801=y CONFIG_CIO_DAC=y CONFIG_DPOT_DAC=y CONFIG_DS4424=y CONFIG_LTC1660=y CONFIG_LTC2632=y CONFIG_M62332=y CONFIG_MAX517=y CONFIG_MAX5821=y CONFIG_MCP4725=y CONFIG_MCP4922=y CONFIG_TI_DAC082S085=y CONFIG_TI_DAC5571=y CONFIG_TI_DAC7311=y CONFIG_TI_DAC7612=y CONFIG_VF610_DAC=y # end of Digital to analog converters # # IIO dummy driver # CONFIG_IIO_DUMMY_EVGEN=y CONFIG_IIO_SIMPLE_DUMMY=y CONFIG_IIO_SIMPLE_DUMMY_EVENTS=y CONFIG_IIO_SIMPLE_DUMMY_BUFFER=y # end of IIO dummy driver # # Filters # # end of Filters # # Frequency Synthesizers DDS/PLL # # # Clock Generator/Distribution # CONFIG_AD9523=y # end of Clock Generator/Distribution # # Phase-Locked Loop (PLL) frequency synthesizers # CONFIG_ADF4350=y CONFIG_ADF4371=y CONFIG_ADMV1013=y CONFIG_ADMV4420=y CONFIG_ADRF6780=y # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL # # Digital gyroscope sensors # CONFIG_ADIS16080=y CONFIG_ADIS16130=y CONFIG_ADIS16136=y CONFIG_ADIS16260=y CONFIG_ADXRS290=y CONFIG_ADXRS450=y CONFIG_BMG160=y CONFIG_BMG160_I2C=y CONFIG_BMG160_SPI=y CONFIG_FXAS21002C=y CONFIG_FXAS21002C_I2C=y CONFIG_FXAS21002C_SPI=y CONFIG_HID_SENSOR_GYRO_3D=y CONFIG_MPU3050=y CONFIG_MPU3050_I2C=y CONFIG_IIO_ST_GYRO_3AXIS=y CONFIG_IIO_ST_GYRO_I2C_3AXIS=y CONFIG_IIO_ST_GYRO_SPI_3AXIS=y CONFIG_ITG3200=y # end of Digital gyroscope sensors # # Health Sensors # # # Heart Rate Monitors # CONFIG_AFE4403=y CONFIG_AFE4404=y CONFIG_MAX30100=y CONFIG_MAX30102=y # end of Heart Rate Monitors # end of Health Sensors # # Humidity sensors # CONFIG_AM2315=y CONFIG_DHT11=y CONFIG_HDC100X=y CONFIG_HDC2010=y CONFIG_HID_SENSOR_HUMIDITY=y CONFIG_HTS221=y CONFIG_HTS221_I2C=y CONFIG_HTS221_SPI=y CONFIG_HTU21=y CONFIG_SI7005=y CONFIG_SI7020=y # end of Humidity sensors # # Inertial measurement units # CONFIG_ADIS16400=y CONFIG_ADIS16460=y CONFIG_ADIS16475=y CONFIG_ADIS16480=y CONFIG_BMI160=y CONFIG_BMI160_I2C=y CONFIG_BMI160_SPI=y CONFIG_BOSCH_BNO055=y CONFIG_BOSCH_BNO055_SERIAL=y CONFIG_BOSCH_BNO055_I2C=y CONFIG_FXOS8700=y CONFIG_FXOS8700_I2C=y CONFIG_FXOS8700_SPI=y CONFIG_KMX61=y CONFIG_INV_ICM42600=y CONFIG_INV_ICM42600_I2C=y CONFIG_INV_ICM42600_SPI=y CONFIG_INV_MPU6050_IIO=y CONFIG_INV_MPU6050_I2C=y CONFIG_INV_MPU6050_SPI=y CONFIG_IIO_ST_LSM6DSX=y CONFIG_IIO_ST_LSM6DSX_I2C=y CONFIG_IIO_ST_LSM6DSX_SPI=y CONFIG_IIO_ST_LSM6DSX_I3C=y # end of Inertial measurement units CONFIG_IIO_ADIS_LIB=y CONFIG_IIO_ADIS_LIB_BUFFER=y # # Light sensors # CONFIG_ACPI_ALS=y CONFIG_ADJD_S311=y CONFIG_ADUX1020=y CONFIG_AL3010=y CONFIG_AL3320A=y CONFIG_APDS9300=y CONFIG_APDS9960=y CONFIG_AS73211=y CONFIG_BH1750=y CONFIG_BH1780=y CONFIG_CM32181=y CONFIG_CM3232=y CONFIG_CM3323=y CONFIG_CM3605=y CONFIG_CM36651=y CONFIG_IIO_CROS_EC_LIGHT_PROX=y CONFIG_GP2AP002=y CONFIG_GP2AP020A00F=y CONFIG_IQS621_ALS=y CONFIG_SENSORS_ISL29018=y CONFIG_SENSORS_ISL29028=y CONFIG_ISL29125=y CONFIG_HID_SENSOR_ALS=y CONFIG_HID_SENSOR_PROX=y CONFIG_JSA1212=y CONFIG_RPR0521=y CONFIG_SENSORS_LM3533=y CONFIG_LTR501=y CONFIG_LTRF216A=y CONFIG_LV0104CS=y CONFIG_MAX44000=y CONFIG_MAX44009=y CONFIG_NOA1305=y CONFIG_OPT3001=y CONFIG_PA12203001=y CONFIG_SI1133=y CONFIG_SI1145=y CONFIG_STK3310=y CONFIG_ST_UVIS25=y CONFIG_ST_UVIS25_I2C=y CONFIG_ST_UVIS25_SPI=y CONFIG_TCS3414=y CONFIG_TCS3472=y CONFIG_SENSORS_TSL2563=y CONFIG_TSL2583=y CONFIG_TSL2591=y CONFIG_TSL2772=y CONFIG_TSL4531=y CONFIG_US5182D=y CONFIG_VCNL4000=y CONFIG_VCNL4035=y CONFIG_VEML6030=y CONFIG_VEML6070=y CONFIG_VL6180=y CONFIG_ZOPT2201=y # end of Light sensors # # Magnetometer sensors # CONFIG_AK8974=y CONFIG_AK8975=y CONFIG_AK09911=y CONFIG_BMC150_MAGN=y CONFIG_BMC150_MAGN_I2C=y CONFIG_BMC150_MAGN_SPI=y CONFIG_MAG3110=y CONFIG_HID_SENSOR_MAGNETOMETER_3D=y CONFIG_MMC35240=y CONFIG_IIO_ST_MAGN_3AXIS=y CONFIG_IIO_ST_MAGN_I2C_3AXIS=y CONFIG_IIO_ST_MAGN_SPI_3AXIS=y CONFIG_SENSORS_HMC5843=y CONFIG_SENSORS_HMC5843_I2C=y CONFIG_SENSORS_HMC5843_SPI=y CONFIG_SENSORS_RM3100=y CONFIG_SENSORS_RM3100_I2C=y CONFIG_SENSORS_RM3100_SPI=y CONFIG_YAMAHA_YAS530=y # end of Magnetometer sensors # # Multiplexers # CONFIG_IIO_MUX=y # end of Multiplexers # # Inclinometer sensors # CONFIG_HID_SENSOR_INCLINOMETER_3D=y CONFIG_HID_SENSOR_DEVICE_ROTATION=y # end of Inclinometer sensors CONFIG_IIO_RESCALE_KUNIT_TEST=y CONFIG_IIO_FORMAT_KUNIT_TEST=y # # Triggers - standalone # CONFIG_IIO_HRTIMER_TRIGGER=y CONFIG_IIO_INTERRUPT_TRIGGER=y CONFIG_IIO_TIGHTLOOP_TRIGGER=y CONFIG_IIO_SYSFS_TRIGGER=y # end of Triggers - standalone # # Linear and angular position sensors # CONFIG_IQS624_POS=y CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=y # end of Linear and angular position sensors # # Digital potentiometers # CONFIG_AD5110=y CONFIG_AD5272=y CONFIG_DS1803=y CONFIG_MAX5432=y CONFIG_MAX5481=y CONFIG_MAX5487=y CONFIG_MCP4018=y CONFIG_MCP4131=y CONFIG_MCP4531=y CONFIG_MCP41010=y CONFIG_TPL0102=y # end of Digital potentiometers # # Digital potentiostats # CONFIG_LMP91000=y # end of Digital potentiostats # # Pressure sensors # CONFIG_ABP060MG=y CONFIG_BMP280=y CONFIG_BMP280_I2C=y CONFIG_BMP280_SPI=y CONFIG_IIO_CROS_EC_BARO=y CONFIG_DLHL60D=y CONFIG_DPS310=y CONFIG_HID_SENSOR_PRESS=y CONFIG_HP03=y CONFIG_ICP10100=y CONFIG_MPL115=y CONFIG_MPL115_I2C=y CONFIG_MPL115_SPI=y CONFIG_MPL3115=y CONFIG_MS5611=y CONFIG_MS5611_I2C=y CONFIG_MS5611_SPI=y CONFIG_MS5637=y CONFIG_IIO_ST_PRESS=y CONFIG_IIO_ST_PRESS_I2C=y CONFIG_IIO_ST_PRESS_SPI=y CONFIG_T5403=y CONFIG_HP206C=y CONFIG_ZPA2326=y CONFIG_ZPA2326_I2C=y CONFIG_ZPA2326_SPI=y # end of Pressure sensors # # Lightning sensors # CONFIG_AS3935=y # end of Lightning sensors # # Proximity and distance sensors # CONFIG_CROS_EC_MKBP_PROXIMITY=y CONFIG_ISL29501=y CONFIG_LIDAR_LITE_V2=y CONFIG_MB1232=y CONFIG_PING=y CONFIG_RFD77402=y CONFIG_SRF04=y CONFIG_SX_COMMON=y CONFIG_SX9310=y CONFIG_SX9324=y CONFIG_SX9360=y CONFIG_SX9500=y CONFIG_SRF08=y CONFIG_VCNL3020=y CONFIG_VL53L0X_I2C=y # end of Proximity and distance sensors # # Resolver to digital converters # CONFIG_AD2S90=y CONFIG_AD2S1200=y # end of Resolver to digital converters # # Temperature sensors # CONFIG_IQS620AT_TEMP=y CONFIG_LTC2983=y CONFIG_MAXIM_THERMOCOUPLE=y CONFIG_HID_SENSOR_TEMP=y CONFIG_MLX90614=y CONFIG_MLX90632=y CONFIG_TMP006=y CONFIG_TMP007=y CONFIG_TMP117=y CONFIG_TSYS01=y CONFIG_TSYS02D=y CONFIG_MAX31856=y CONFIG_MAX31865=y # end of Temperature sensors CONFIG_NTB=y CONFIG_NTB_MSI=y CONFIG_NTB_IDT=y CONFIG_NTB_EPF=m CONFIG_NTB_SWITCHTEC=y CONFIG_NTB_PINGPONG=y CONFIG_NTB_TOOL=y CONFIG_NTB_PERF=y CONFIG_NTB_MSI_TEST=y CONFIG_NTB_TRANSPORT=y CONFIG_PWM=y CONFIG_PWM_SYSFS=y CONFIG_PWM_DEBUG=y CONFIG_PWM_ATMEL_HLCDC_PWM=y CONFIG_PWM_ATMEL_TCB=y CONFIG_PWM_CLK=y CONFIG_PWM_CRC=y CONFIG_PWM_CROS_EC=y CONFIG_PWM_DWC=y CONFIG_PWM_FSL_FTM=y CONFIG_PWM_INTEL_LGM=y CONFIG_PWM_IQS620A=y CONFIG_PWM_LP3943=y CONFIG_PWM_LPSS=y CONFIG_PWM_LPSS_PCI=y CONFIG_PWM_LPSS_PLATFORM=y CONFIG_PWM_NTXEC=y CONFIG_PWM_PCA9685=y CONFIG_PWM_STMPE=y CONFIG_PWM_TWL=y CONFIG_PWM_TWL_LED=y CONFIG_PWM_XILINX=y # # IRQ chip support # CONFIG_IRQCHIP=y CONFIG_AL_FIC=y CONFIG_CIRRUS_CS48L32_IRQ=y CONFIG_MADERA_IRQ=y CONFIG_XILINX_INTC=y # end of IRQ chip support CONFIG_IPACK_BUS=y CONFIG_BOARD_TPCI200=y CONFIG_SERIAL_IPOCTAL=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_INTEL_GW=y CONFIG_RESET_SIMPLE=y CONFIG_RESET_TI_SYSCON=y CONFIG_RESET_TI_TPS380X=y # # PHY Subsystem # CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PHY_MIPI_DPHY=y CONFIG_USB_LGM_PHY=y CONFIG_PHY_CAN_TRANSCEIVER=y # # PHY drivers for Broadcom platforms # CONFIG_BCM_KONA_USB2_PHY=y # end of PHY drivers for Broadcom platforms CONFIG_PHY_CADENCE_TORRENT=y CONFIG_PHY_CADENCE_DPHY=y CONFIG_PHY_CADENCE_DPHY_RX=y CONFIG_PHY_CADENCE_SIERRA=y CONFIG_PHY_CADENCE_SALVO=y CONFIG_PHY_PXA_28NM_HSIC=y CONFIG_PHY_PXA_28NM_USB2=y CONFIG_PHY_LAN966X_SERDES=y CONFIG_PHY_CPCAP_USB=y CONFIG_PHY_MAPPHONE_MDM6600=y CONFIG_PHY_OCELOT_SERDES=y CONFIG_PHY_QCOM_USB_HS=y CONFIG_PHY_QCOM_USB_HSIC=y CONFIG_PHY_SAMSUNG_USB2=y CONFIG_PHY_TUSB1210=y CONFIG_PHY_INTEL_LGM_COMBO=y CONFIG_PHY_INTEL_LGM_EMMC=y # end of PHY Subsystem CONFIG_POWERCAP=y CONFIG_INTEL_RAPL_CORE=y CONFIG_INTEL_RAPL=y CONFIG_IDLE_INJECT=y CONFIG_DTPM=y CONFIG_DTPM_CPU=y CONFIG_DTPM_DEVFREQ=y CONFIG_MCB=y CONFIG_MCB_PCI=y CONFIG_MCB_LPC=y # # Performance monitor support # # end of Performance monitor support CONFIG_RAS=y CONFIG_RAS_CEC=y CONFIG_RAS_CEC_DEBUG=y CONFIG_USB4=y CONFIG_USB4_DEBUGFS_WRITE=y CONFIG_USB4_DEBUGFS_MARGINING=y CONFIG_USB4_KUNIT_TEST=y CONFIG_USB4_DMA_TEST=y # # Android # CONFIG_ANDROID_BINDER_IPC=y CONFIG_ANDROID_BINDERFS=y CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder" CONFIG_ANDROID_BINDER_IPC_SELFTEST=y # end of Android CONFIG_DAX=y CONFIG_DEV_DAX=y CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y CONFIG_NVMEM_RAVE_SP_EEPROM=y CONFIG_NVMEM_RMEM=y CONFIG_NVMEM_SPMI_SDAM=y CONFIG_NVMEM_U_BOOT_ENV=y # # HW tracing support # CONFIG_STM=y CONFIG_STM_PROTO_BASIC=y CONFIG_STM_PROTO_SYS_T=y CONFIG_STM_DUMMY=y CONFIG_STM_SOURCE_CONSOLE=y CONFIG_STM_SOURCE_HEARTBEAT=y CONFIG_STM_SOURCE_FTRACE=y CONFIG_INTEL_TH=y CONFIG_INTEL_TH_PCI=y CONFIG_INTEL_TH_ACPI=y CONFIG_INTEL_TH_GTH=y CONFIG_INTEL_TH_STH=y CONFIG_INTEL_TH_MSU=y CONFIG_INTEL_TH_PTI=y CONFIG_INTEL_TH_DEBUG=y # end of HW tracing support CONFIG_FPGA=y CONFIG_ALTERA_PR_IP_CORE=y CONFIG_ALTERA_PR_IP_CORE_PLAT=y CONFIG_FPGA_MGR_ALTERA_PS_SPI=y CONFIG_FPGA_MGR_ALTERA_CVP=y CONFIG_FPGA_MGR_XILINX_SPI=y CONFIG_FPGA_MGR_ICE40_SPI=y CONFIG_FPGA_MGR_MACHXO2_SPI=y CONFIG_FPGA_BRIDGE=y CONFIG_ALTERA_FREEZE_BRIDGE=y CONFIG_XILINX_PR_DECOUPLER=y CONFIG_FPGA_REGION=y CONFIG_OF_FPGA_REGION=y CONFIG_FPGA_DFL=y CONFIG_FPGA_DFL_FME=y CONFIG_FPGA_DFL_FME_MGR=y CONFIG_FPGA_DFL_FME_BRIDGE=y CONFIG_FPGA_DFL_FME_REGION=y CONFIG_FPGA_DFL_AFU=y CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=y CONFIG_FPGA_DFL_PCI=y CONFIG_FPGA_M10_BMC_SEC_UPDATE=y CONFIG_FPGA_MGR_MICROCHIP_SPI=y CONFIG_FSI=y CONFIG_FSI_NEW_DEV_NODE=y CONFIG_FSI_MASTER_GPIO=y CONFIG_FSI_MASTER_HUB=y CONFIG_FSI_MASTER_ASPEED=y CONFIG_FSI_SCOM=y CONFIG_FSI_SBEFIFO=y CONFIG_FSI_OCC=y CONFIG_TEE=y CONFIG_MULTIPLEXER=y # # Multiplexer drivers # CONFIG_MUX_ADG792A=y CONFIG_MUX_ADGS1408=y CONFIG_MUX_GPIO=y CONFIG_MUX_MMIO=y # end of Multiplexer drivers CONFIG_PM_OPP=y CONFIG_SIOX=y CONFIG_SIOX_BUS_GPIO=y CONFIG_SLIMBUS=y CONFIG_SLIM_QCOM_CTRL=y CONFIG_INTERCONNECT=y CONFIG_COUNTER=y CONFIG_104_QUAD_8=y CONFIG_INTERRUPT_CNT=y CONFIG_FTM_QUADDEC=y CONFIG_MICROCHIP_TCB_CAPTURE=y CONFIG_INTEL_QEP=y CONFIG_MOST=y CONFIG_MOST_USB_HDM=y CONFIG_MOST_CDEV=y CONFIG_MOST_SND=y CONFIG_PECI=y CONFIG_PECI_CPU=y CONFIG_HTE=y # end of Device Drivers # # File systems # CONFIG_DCACHE_WORD_ACCESS=y CONFIG_VALIDATE_FS_PARSER=y CONFIG_FS_IOMAP=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y CONFIG_EXT4_DEBUG=y CONFIG_EXT4_KUNIT_TESTS=y CONFIG_JBD2=y CONFIG_JBD2_DEBUG=y CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=y CONFIG_REISERFS_CHECK=y CONFIG_REISERFS_PROC_INFO=y CONFIG_REISERFS_FS_XATTR=y CONFIG_REISERFS_FS_POSIX_ACL=y CONFIG_REISERFS_FS_SECURITY=y CONFIG_JFS_FS=y CONFIG_JFS_POSIX_ACL=y CONFIG_JFS_SECURITY=y CONFIG_JFS_DEBUG=y CONFIG_JFS_STATISTICS=y CONFIG_XFS_FS=y CONFIG_XFS_SUPPORT_V4=y CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y CONFIG_XFS_RT=y CONFIG_XFS_ONLINE_SCRUB=y CONFIG_XFS_ONLINE_REPAIR=y CONFIG_XFS_DEBUG=y CONFIG_XFS_ASSERT_FATAL=y CONFIG_GFS2_FS=y CONFIG_GFS2_FS_LOCKING_DLM=y CONFIG_OCFS2_FS=y CONFIG_OCFS2_FS_O2CB=y CONFIG_OCFS2_FS_USERSPACE_CLUSTER=y CONFIG_OCFS2_FS_STATS=y CONFIG_OCFS2_DEBUG_MASKLOG=y CONFIG_OCFS2_DEBUG_FS=y CONFIG_BTRFS_FS=y CONFIG_BTRFS_FS_POSIX_ACL=y CONFIG_BTRFS_FS_CHECK_INTEGRITY=y CONFIG_BTRFS_FS_RUN_SANITY_TESTS=y CONFIG_BTRFS_DEBUG=y CONFIG_BTRFS_ASSERT=y CONFIG_BTRFS_FS_REF_VERIFY=y CONFIG_NILFS2_FS=y CONFIG_F2FS_FS=y CONFIG_F2FS_STAT_FS=y CONFIG_F2FS_FS_XATTR=y CONFIG_F2FS_FS_POSIX_ACL=y CONFIG_F2FS_FS_SECURITY=y CONFIG_F2FS_CHECK_FS=y CONFIG_F2FS_FAULT_INJECTION=y CONFIG_F2FS_FS_COMPRESSION=y CONFIG_F2FS_FS_LZO=y CONFIG_F2FS_FS_LZORLE=y CONFIG_F2FS_FS_LZ4=y CONFIG_F2FS_FS_LZ4HC=y CONFIG_F2FS_FS_ZSTD=y CONFIG_F2FS_IOSTAT=y CONFIG_F2FS_UNFAIR_RWSEM=y CONFIG_ZONEFS_FS=y CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y CONFIG_EXPORTFS_BLOCK_OPS=y CONFIG_FILE_LOCKING=y CONFIG_FS_ENCRYPTION=y CONFIG_FS_ENCRYPTION_ALGS=y CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y CONFIG_FS_VERITY=y CONFIG_FS_VERITY_DEBUG=y CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y CONFIG_FANOTIFY=y CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_PRINT_QUOTA_WARNING=y CONFIG_QUOTA_DEBUG=y CONFIG_QUOTA_TREE=y CONFIG_QFMT_V1=y CONFIG_QFMT_V2=y CONFIG_QUOTACTL=y CONFIG_AUTOFS4_FS=y CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=y CONFIG_CUSE=y CONFIG_VIRTIO_FS=y CONFIG_OVERLAY_FS=y CONFIG_OVERLAY_FS_REDIRECT_DIR=y CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y CONFIG_OVERLAY_FS_INDEX=y CONFIG_OVERLAY_FS_METACOPY=y # # Caches # CONFIG_NETFS_SUPPORT=y CONFIG_NETFS_STATS=y CONFIG_FSCACHE=y CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE_DEBUG=y CONFIG_CACHEFILES=y CONFIG_CACHEFILES_DEBUG=y CONFIG_CACHEFILES_ERROR_INJECTION=y CONFIG_CACHEFILES_ONDEMAND=y # end of Caches # # CD-ROM/DVD Filesystems # CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=y # end of CD-ROM/DVD Filesystems # # DOS/FAT/EXFAT/NT Filesystems # CONFIG_FAT_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_FAT_DEFAULT_UTF8=y CONFIG_FAT_KUNIT_TEST=y CONFIG_EXFAT_FS=y CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" CONFIG_NTFS_FS=y CONFIG_NTFS_DEBUG=y CONFIG_NTFS_RW=y CONFIG_NTFS3_FS=y CONFIG_NTFS3_LZX_XPRESS=y CONFIG_NTFS3_FS_POSIX_ACL=y # end of DOS/FAT/EXFAT/NT Filesystems # # Pseudo filesystems # CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_VMCORE=y CONFIG_PROC_VMCORE_DEVICE_DUMP=y CONFIG_PROC_SYSCTL=y CONFIG_PROC_PAGE_MONITOR=y CONFIG_PROC_CHILDREN=y CONFIG_PROC_PID_ARCH_STATUS=y CONFIG_PROC_CPU_RESCTRL=y CONFIG_KERNFS=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y CONFIG_MEMFD_CREATE=y CONFIG_CONFIGFS_FS=y CONFIG_EFIVAR_FS=y # end of Pseudo filesystems CONFIG_MISC_FILESYSTEMS=y CONFIG_ORANGEFS_FS=y CONFIG_ADFS_FS=y CONFIG_ADFS_FS_RW=y CONFIG_AFFS_FS=y CONFIG_ECRYPT_FS=y CONFIG_ECRYPT_FS_MESSAGING=y CONFIG_HFS_FS=y CONFIG_HFSPLUS_FS=y CONFIG_BEFS_FS=y CONFIG_BEFS_DEBUG=y CONFIG_BFS_FS=y CONFIG_EFS_FS=y CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y CONFIG_JFFS2_FS_WBUF_VERIFY=y CONFIG_JFFS2_SUMMARY=y CONFIG_JFFS2_FS_XATTR=y CONFIG_JFFS2_FS_POSIX_ACL=y CONFIG_JFFS2_FS_SECURITY=y CONFIG_JFFS2_COMPRESSION_OPTIONS=y CONFIG_JFFS2_ZLIB=y CONFIG_JFFS2_LZO=y CONFIG_JFFS2_RTIME=y CONFIG_JFFS2_RUBIN=y # CONFIG_JFFS2_CMODE_NONE is not set CONFIG_JFFS2_CMODE_PRIORITY=y # CONFIG_JFFS2_CMODE_SIZE is not set # CONFIG_JFFS2_CMODE_FAVOURLZO is not set CONFIG_UBIFS_FS=y CONFIG_UBIFS_FS_ADVANCED_COMPR=y CONFIG_UBIFS_FS_LZO=y CONFIG_UBIFS_FS_ZLIB=y CONFIG_UBIFS_FS_ZSTD=y CONFIG_UBIFS_ATIME_SUPPORT=y CONFIG_UBIFS_FS_XATTR=y CONFIG_UBIFS_FS_SECURITY=y CONFIG_UBIFS_FS_AUTHENTICATION=y CONFIG_CRAMFS=y CONFIG_CRAMFS_BLOCKDEV=y CONFIG_CRAMFS_MTD=y CONFIG_SQUASHFS=y CONFIG_SQUASHFS_FILE_CACHE=y # CONFIG_SQUASHFS_FILE_DIRECT is not set CONFIG_SQUASHFS_DECOMP_SINGLE=y # CONFIG_SQUASHFS_DECOMP_MULTI is not set # CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set CONFIG_SQUASHFS_XATTR=y CONFIG_SQUASHFS_ZLIB=y CONFIG_SQUASHFS_LZ4=y CONFIG_SQUASHFS_LZO=y CONFIG_SQUASHFS_XZ=y CONFIG_SQUASHFS_ZSTD=y CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y CONFIG_SQUASHFS_EMBEDDED=y CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 CONFIG_VXFS_FS=y CONFIG_MINIX_FS=y CONFIG_OMFS_FS=y CONFIG_HPFS_FS=y CONFIG_QNX4FS_FS=y CONFIG_QNX6FS_FS=y CONFIG_QNX6FS_DEBUG=y CONFIG_ROMFS_FS=y CONFIG_ROMFS_BACKED_BY_BLOCK=y # CONFIG_ROMFS_BACKED_BY_MTD is not set # CONFIG_ROMFS_BACKED_BY_BOTH is not set CONFIG_ROMFS_ON_BLOCK=y CONFIG_PSTORE=y CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 CONFIG_PSTORE_DEFLATE_COMPRESS=y CONFIG_PSTORE_LZO_COMPRESS=y CONFIG_PSTORE_LZ4_COMPRESS=y CONFIG_PSTORE_LZ4HC_COMPRESS=y CONFIG_PSTORE_842_COMPRESS=y CONFIG_PSTORE_ZSTD_COMPRESS=y CONFIG_PSTORE_COMPRESS=y CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y # CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set # CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set # CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set # CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set # CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT is not set CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" CONFIG_PSTORE_CONSOLE=y CONFIG_PSTORE_PMSG=y CONFIG_PSTORE_FTRACE=y CONFIG_PSTORE_RAM=y CONFIG_PSTORE_ZONE=y CONFIG_PSTORE_BLK=y CONFIG_PSTORE_BLK_BLKDEV="" CONFIG_PSTORE_BLK_KMSG_SIZE=64 CONFIG_PSTORE_BLK_MAX_REASON=2 CONFIG_PSTORE_BLK_PMSG_SIZE=64 CONFIG_PSTORE_BLK_CONSOLE_SIZE=64 CONFIG_PSTORE_BLK_FTRACE_SIZE=64 CONFIG_SYSV_FS=y CONFIG_UFS_FS=y CONFIG_UFS_FS_WRITE=y CONFIG_UFS_DEBUG=y CONFIG_EROFS_FS=y CONFIG_EROFS_FS_DEBUG=y CONFIG_EROFS_FS_XATTR=y CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_ZIP=y CONFIG_EROFS_FS_ZIP_LZMA=y CONFIG_EROFS_FS_ONDEMAND=y CONFIG_VBOXSF_FS=y CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V2=y CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_NFS_SWAP=y CONFIG_NFS_V4_1=y CONFIG_NFS_V4_2=y CONFIG_PNFS_FILE_LAYOUT=y CONFIG_PNFS_BLOCK=y CONFIG_PNFS_FLEXFILE_LAYOUT=y CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" CONFIG_NFS_V4_1_MIGRATION=y CONFIG_NFS_V4_SECURITY_LABEL=y CONFIG_ROOT_NFS=y CONFIG_NFS_FSCACHE=y CONFIG_NFS_USE_LEGACY_DNS=y CONFIG_NFS_DEBUG=y CONFIG_NFS_DISABLE_UDP_SUPPORT=y CONFIG_NFS_V4_2_READ_PLUS=y CONFIG_NFSD=y CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_NFSD_PNFS=y CONFIG_NFSD_BLOCKLAYOUT=y CONFIG_NFSD_SCSILAYOUT=y CONFIG_NFSD_FLEXFILELAYOUT=y CONFIG_NFSD_V4_2_INTER_SSC=y CONFIG_NFSD_V4_SECURITY_LABEL=y CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y CONFIG_NFS_V4_2_SSC_HELPER=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_SUNRPC_BACKCHANNEL=y CONFIG_SUNRPC_SWAP=y CONFIG_RPCSEC_GSS_KRB5=y CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES=y CONFIG_SUNRPC_DEBUG=y CONFIG_SUNRPC_XPRT_RDMA=y CONFIG_CEPH_FS=y CONFIG_CEPH_FSCACHE=y CONFIG_CEPH_FS_POSIX_ACL=y CONFIG_CEPH_FS_SECURITY_LABEL=y CONFIG_CIFS=y CONFIG_CIFS_STATS2=y CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y CONFIG_CIFS_UPCALL=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_CIFS_DEBUG=y CONFIG_CIFS_DEBUG2=y CONFIG_CIFS_DEBUG_DUMP_KEYS=y CONFIG_CIFS_DFS_UPCALL=y CONFIG_CIFS_SWN_UPCALL=y CONFIG_CIFS_SMB_DIRECT=y CONFIG_CIFS_FSCACHE=y CONFIG_CIFS_ROOT=y CONFIG_SMB_SERVER=y CONFIG_SMB_SERVER_SMBDIRECT=y CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y CONFIG_SMB_SERVER_KERBEROS5=y CONFIG_SMBFS_COMMON=y CONFIG_CODA_FS=y CONFIG_AFS_FS=y CONFIG_AFS_DEBUG=y CONFIG_AFS_FSCACHE=y CONFIG_AFS_DEBUG_CURSOR=y CONFIG_9P_FS=y CONFIG_9P_FSCACHE=y CONFIG_9P_FS_POSIX_ACL=y CONFIG_9P_FS_SECURITY=y CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=y CONFIG_NLS_CODEPAGE_775=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_CODEPAGE_852=y CONFIG_NLS_CODEPAGE_855=y CONFIG_NLS_CODEPAGE_857=y CONFIG_NLS_CODEPAGE_860=y CONFIG_NLS_CODEPAGE_861=y CONFIG_NLS_CODEPAGE_862=y CONFIG_NLS_CODEPAGE_863=y CONFIG_NLS_CODEPAGE_864=y CONFIG_NLS_CODEPAGE_865=y CONFIG_NLS_CODEPAGE_866=y CONFIG_NLS_CODEPAGE_869=y CONFIG_NLS_CODEPAGE_936=y CONFIG_NLS_CODEPAGE_950=y CONFIG_NLS_CODEPAGE_932=y CONFIG_NLS_CODEPAGE_949=y CONFIG_NLS_CODEPAGE_874=y CONFIG_NLS_ISO8859_8=y CONFIG_NLS_CODEPAGE_1250=y CONFIG_NLS_CODEPAGE_1251=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_2=y CONFIG_NLS_ISO8859_3=y CONFIG_NLS_ISO8859_4=y CONFIG_NLS_ISO8859_5=y CONFIG_NLS_ISO8859_6=y CONFIG_NLS_ISO8859_7=y CONFIG_NLS_ISO8859_9=y CONFIG_NLS_ISO8859_13=y CONFIG_NLS_ISO8859_14=y CONFIG_NLS_ISO8859_15=y CONFIG_NLS_KOI8_R=y CONFIG_NLS_KOI8_U=y CONFIG_NLS_MAC_ROMAN=y CONFIG_NLS_MAC_CELTIC=y CONFIG_NLS_MAC_CENTEURO=y CONFIG_NLS_MAC_CROATIAN=y CONFIG_NLS_MAC_CYRILLIC=y CONFIG_NLS_MAC_GAELIC=y CONFIG_NLS_MAC_GREEK=y CONFIG_NLS_MAC_ICELAND=y CONFIG_NLS_MAC_INUIT=y CONFIG_NLS_MAC_ROMANIAN=y CONFIG_NLS_MAC_TURKISH=y CONFIG_NLS_UTF8=y CONFIG_DLM=y CONFIG_DLM_DEPRECATED_API=y CONFIG_DLM_DEBUG=y CONFIG_UNICODE=y CONFIG_UNICODE_NORMALIZATION_SELFTEST=y CONFIG_IO_WQ=y # end of File systems # # Security options # CONFIG_KEYS=y CONFIG_KEYS_REQUEST_CACHE=y CONFIG_PERSISTENT_KEYRINGS=y CONFIG_BIG_KEYS=y CONFIG_TRUSTED_KEYS=y CONFIG_TRUSTED_KEYS_TPM=y CONFIG_TRUSTED_KEYS_TEE=y CONFIG_ENCRYPTED_KEYS=y CONFIG_USER_DECRYPTED_DATA=y CONFIG_KEY_DH_OPERATIONS=y CONFIG_KEY_NOTIFICATIONS=y CONFIG_SECURITY_DMESG_RESTRICT=y CONFIG_SECURITY=y CONFIG_SECURITY_WRITABLE_HOOKS=y CONFIG_SECURITYFS=y CONFIG_SECURITY_NETWORK=y CONFIG_SECURITY_INFINIBAND=y CONFIG_SECURITY_NETWORK_XFRM=y CONFIG_SECURITY_PATH=y CONFIG_INTEL_TXT=y CONFIG_LSM_MMAP_MIN_ADDR=65536 CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y CONFIG_HARDENED_USERCOPY=y CONFIG_FORTIFY_SOURCE=y CONFIG_STATIC_USERMODEHELPER=y CONFIG_STATIC_USERMODEHELPER_PATH="/sbin/usermode-helper" CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SELINUX_BOOTPARAM=y CONFIG_SECURITY_SELINUX_DISABLE=y CONFIG_SECURITY_SELINUX_DEVELOP=y CONFIG_SECURITY_SELINUX_AVC_STATS=y CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0 CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 CONFIG_SECURITY_SMACK=y CONFIG_SECURITY_SMACK_BRINGUP=y CONFIG_SECURITY_SMACK_NETFILTER=y CONFIG_SECURITY_SMACK_APPEND_SIGNALS=y CONFIG_SECURITY_TOMOYO=y CONFIG_SECURITY_TOMOYO_MAX_ACCEPT_ENTRY=2048 CONFIG_SECURITY_TOMOYO_MAX_AUDIT_LOG=1024 CONFIG_SECURITY_TOMOYO_OMIT_USERSPACE_LOADER=y CONFIG_SECURITY_TOMOYO_INSECURE_BUILTIN_SETTING=y CONFIG_SECURITY_APPARMOR=y CONFIG_SECURITY_APPARMOR_DEBUG=y CONFIG_SECURITY_APPARMOR_DEBUG_ASSERTS=y CONFIG_SECURITY_APPARMOR_DEBUG_MESSAGES=y CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y CONFIG_SECURITY_APPARMOR_HASH=y CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y CONFIG_SECURITY_APPARMOR_KUNIT_TEST=y CONFIG_SECURITY_LOADPIN=y CONFIG_SECURITY_LOADPIN_ENFORCE=y CONFIG_SECURITY_LOADPIN_VERITY=y CONFIG_SECURITY_YAMA=y CONFIG_SECURITY_SAFESETID=y CONFIG_SECURITY_LOCKDOWN_LSM=y CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y # CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY is not set # CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY is not set CONFIG_SECURITY_LANDLOCK=y CONFIG_INTEGRITY=y CONFIG_INTEGRITY_SIGNATURE=y CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y CONFIG_INTEGRITY_TRUSTED_KEYRING=y CONFIG_INTEGRITY_PLATFORM_KEYRING=y CONFIG_LOAD_UEFI_KEYS=y CONFIG_INTEGRITY_AUDIT=y CONFIG_IMA=y CONFIG_IMA_MEASURE_PCR_IDX=10 CONFIG_IMA_LSM_RULES=y CONFIG_IMA_NG_TEMPLATE=y # CONFIG_IMA_SIG_TEMPLATE is not set CONFIG_IMA_DEFAULT_TEMPLATE="ima-ng" CONFIG_IMA_DEFAULT_HASH_SHA1=y # CONFIG_IMA_DEFAULT_HASH_SHA256 is not set # CONFIG_IMA_DEFAULT_HASH_SHA512 is not set # CONFIG_IMA_DEFAULT_HASH_WP512 is not set # CONFIG_IMA_DEFAULT_HASH_SM3 is not set CONFIG_IMA_DEFAULT_HASH="sha1" CONFIG_IMA_WRITE_POLICY=y CONFIG_IMA_READ_POLICY=y CONFIG_IMA_APPRAISE=y CONFIG_IMA_ARCH_POLICY=y CONFIG_IMA_APPRAISE_BUILD_POLICY=y CONFIG_IMA_APPRAISE_REQUIRE_FIRMWARE_SIGS=y CONFIG_IMA_APPRAISE_REQUIRE_KEXEC_SIGS=y CONFIG_IMA_APPRAISE_REQUIRE_MODULE_SIGS=y CONFIG_IMA_APPRAISE_REQUIRE_POLICY_SIGS=y CONFIG_IMA_APPRAISE_BOOTPARAM=y CONFIG_IMA_APPRAISE_MODSIG=y CONFIG_IMA_TRUSTED_KEYRING=y CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY=y CONFIG_IMA_BLACKLIST_KEYRING=y CONFIG_IMA_LOAD_X509=y CONFIG_IMA_X509_PATH="/etc/keys/x509_ima.der" CONFIG_IMA_APPRAISE_SIGNED_INIT=y CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT=y CONFIG_IMA_DISABLE_HTABLE=y CONFIG_EVM=y CONFIG_EVM_ATTR_FSUUID=y CONFIG_EVM_EXTRA_SMACK_XATTRS=y CONFIG_EVM_ADD_XATTRS=y CONFIG_EVM_LOAD_X509=y CONFIG_EVM_X509_PATH="/etc/keys/x509_evm.der" CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SECURITY_SMACK is not set # CONFIG_DEFAULT_SECURITY_TOMOYO is not set # CONFIG_DEFAULT_SECURITY_APPARMOR is not set # CONFIG_DEFAULT_SECURITY_DAC is not set CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor,bpf" # # Kernel hardening options # CONFIG_GCC_PLUGIN_STRUCTLEAK=y # # Memory initialization # # CONFIG_INIT_STACK_NONE is not set # CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set # CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL=y # CONFIG_GCC_PLUGIN_STRUCTLEAK_VERBOSE is not set CONFIG_GCC_PLUGIN_STACKLEAK=y # CONFIG_GCC_PLUGIN_STACKLEAK_VERBOSE is not set CONFIG_STACKLEAK_TRACK_MIN_SIZE=100 CONFIG_STACKLEAK_METRICS=y CONFIG_STACKLEAK_RUNTIME_DISABLE=y CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y CONFIG_INIT_ON_FREE_DEFAULT_ON=y CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y CONFIG_ZERO_CALL_USED_REGS=y # end of Memory initialization # CONFIG_RANDSTRUCT_NONE is not set CONFIG_RANDSTRUCT_FULL=y # CONFIG_RANDSTRUCT_PERFORMANCE is not set CONFIG_RANDSTRUCT=y CONFIG_GCC_PLUGIN_RANDSTRUCT=y # end of Kernel hardening options # end of Security options CONFIG_XOR_BLOCKS=y CONFIG_ASYNC_CORE=y CONFIG_ASYNC_MEMCPY=y CONFIG_ASYNC_XOR=y CONFIG_ASYNC_PQ=y CONFIG_ASYNC_RAID6_RECOV=y CONFIG_CRYPTO=y # # Crypto core or helper # CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_AKCIPHER2=y CONFIG_CRYPTO_AKCIPHER=y CONFIG_CRYPTO_KPP2=y CONFIG_CRYPTO_KPP=y CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y CONFIG_CRYPTO_USER=y CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_PCRYPT=y CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_AUTHENC=y CONFIG_CRYPTO_TEST=y CONFIG_CRYPTO_SIMD=y CONFIG_CRYPTO_ENGINE=y # end of Crypto core or helper # # Public-key cryptography # CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_ECC=y CONFIG_CRYPTO_ECDH=y CONFIG_CRYPTO_ECDSA=y CONFIG_CRYPTO_ECRDSA=y CONFIG_CRYPTO_SM2=y CONFIG_CRYPTO_CURVE25519=y # end of Public-key cryptography # # Block ciphers # CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_AES_TI=y CONFIG_CRYPTO_ANUBIS=y CONFIG_CRYPTO_ARIA=y CONFIG_CRYPTO_BLOWFISH=y CONFIG_CRYPTO_BLOWFISH_COMMON=y CONFIG_CRYPTO_CAMELLIA=y CONFIG_CRYPTO_CAST_COMMON=y CONFIG_CRYPTO_CAST5=y CONFIG_CRYPTO_CAST6=y CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_FCRYPT=y CONFIG_CRYPTO_KHAZAD=y CONFIG_CRYPTO_SEED=y CONFIG_CRYPTO_SERPENT=y CONFIG_CRYPTO_SM4=y CONFIG_CRYPTO_SM4_GENERIC=y CONFIG_CRYPTO_TEA=y CONFIG_CRYPTO_TWOFISH=y CONFIG_CRYPTO_TWOFISH_COMMON=y # end of Block ciphers # # Length-preserving ciphers and modes # CONFIG_CRYPTO_ADIANTUM=y CONFIG_CRYPTO_ARC4=y CONFIG_CRYPTO_CHACHA20=y CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CFB=y CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_CTS=y CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_HCTR2=y CONFIG_CRYPTO_KEYWRAP=y CONFIG_CRYPTO_LRW=y CONFIG_CRYPTO_OFB=y CONFIG_CRYPTO_PCBC=y CONFIG_CRYPTO_XCTR=y CONFIG_CRYPTO_XTS=y CONFIG_CRYPTO_NHPOLY1305=y # end of Length-preserving ciphers and modes # # AEAD (authenticated encryption with associated data) ciphers # CONFIG_CRYPTO_AEGIS128=y CONFIG_CRYPTO_CHACHA20POLY1305=y CONFIG_CRYPTO_CCM=y CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_ECHAINIV=y CONFIG_CRYPTO_ESSIV=y # end of AEAD (authenticated encryption with associated data) ciphers # # Hashes, digests, and MACs # CONFIG_CRYPTO_BLAKE2B=y CONFIG_CRYPTO_CMAC=y CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=y CONFIG_CRYPTO_POLYVAL=y CONFIG_CRYPTO_POLY1305=y CONFIG_CRYPTO_RMD160=y CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA3=y CONFIG_CRYPTO_SM3=y CONFIG_CRYPTO_SM3_GENERIC=y CONFIG_CRYPTO_STREEBOG=y CONFIG_CRYPTO_VMAC=y CONFIG_CRYPTO_WP512=y CONFIG_CRYPTO_XCBC=y CONFIG_CRYPTO_XXHASH=y # end of Hashes, digests, and MACs # # CRCs (cyclic redundancy checks) # CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_CRC64_ROCKSOFT=y # end of CRCs (cyclic redundancy checks) # # Compression # CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_842=y CONFIG_CRYPTO_LZ4=y CONFIG_CRYPTO_LZ4HC=y CONFIG_CRYPTO_ZSTD=y # end of Compression # # Random number generation # CONFIG_CRYPTO_ANSI_CPRNG=y CONFIG_CRYPTO_DRBG_MENU=y CONFIG_CRYPTO_DRBG_HMAC=y CONFIG_CRYPTO_DRBG_HASH=y CONFIG_CRYPTO_DRBG_CTR=y CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_KDF800108_CTR=y # end of Random number generation # # Userspace interface # CONFIG_CRYPTO_USER_API=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_SKCIPHER=y CONFIG_CRYPTO_USER_API_RNG=y CONFIG_CRYPTO_USER_API_RNG_CAVP=y CONFIG_CRYPTO_USER_API_AEAD=y CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y CONFIG_CRYPTO_STATS=y # end of Userspace interface CONFIG_CRYPTO_HASH_INFO=y # # Accelerated Cryptographic Algorithms for CPU (x86) # CONFIG_CRYPTO_AES_NI_INTEL=y CONFIG_CRYPTO_SERPENT_SSE2_586=y CONFIG_CRYPTO_TWOFISH_586=y CONFIG_CRYPTO_CRC32C_INTEL=y CONFIG_CRYPTO_CRC32_PCLMUL=y # end of Accelerated Cryptographic Algorithms for CPU (x86) CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_DEV_PADLOCK=y CONFIG_CRYPTO_DEV_PADLOCK_AES=y CONFIG_CRYPTO_DEV_PADLOCK_SHA=y CONFIG_CRYPTO_DEV_GEODE=y CONFIG_CRYPTO_DEV_HIFN_795X=y CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y CONFIG_CRYPTO_DEV_ATMEL_I2C=y CONFIG_CRYPTO_DEV_ATMEL_ECC=y CONFIG_CRYPTO_DEV_ATMEL_SHA204A=y CONFIG_CRYPTO_DEV_CCP=y CONFIG_CRYPTO_DEV_CCP_DD=y CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_CCP_CRYPTO=y CONFIG_CRYPTO_DEV_CCP_DEBUGFS=y CONFIG_CRYPTO_DEV_QAT=y CONFIG_CRYPTO_DEV_QAT_DH895xCC=y CONFIG_CRYPTO_DEV_QAT_C3XXX=y CONFIG_CRYPTO_DEV_QAT_C62X=y CONFIG_CRYPTO_DEV_QAT_4XXX=y CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=y CONFIG_CRYPTO_DEV_QAT_C3XXXVF=y CONFIG_CRYPTO_DEV_QAT_C62XVF=y CONFIG_CRYPTO_DEV_CHELSIO=y CONFIG_CRYPTO_DEV_VIRTIO=y CONFIG_CRYPTO_DEV_SAFEXCEL=y CONFIG_CRYPTO_DEV_CCREE=y CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG=y CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y CONFIG_PKCS8_PRIVATE_KEY_PARSER=y CONFIG_PKCS7_MESSAGE_PARSER=y CONFIG_PKCS7_TEST_KEY=y CONFIG_SIGNED_PE_FILE_VERIFICATION=y CONFIG_FIPS_SIGNATURE_SELFTEST=y # # Certificates for signature checking # CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" CONFIG_MODULE_SIG_KEY_TYPE_RSA=y # CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set CONFIG_SYSTEM_TRUSTED_KEYRING=y CONFIG_SYSTEM_TRUSTED_KEYS="" CONFIG_SYSTEM_EXTRA_CERTIFICATE=y CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096 CONFIG_SECONDARY_TRUSTED_KEYRING=y CONFIG_SYSTEM_BLACKLIST_KEYRING=y CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" CONFIG_SYSTEM_REVOCATION_LIST=y CONFIG_SYSTEM_REVOCATION_KEYS="" CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y # end of Certificates for signature checking CONFIG_BINARY_PRINTF=y # # Library routines # CONFIG_RAID6_PQ=y CONFIG_RAID6_PQ_BENCHMARK=y CONFIG_LINEAR_RANGES=y CONFIG_PACKING=y CONFIG_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y CONFIG_CORDIC=y CONFIG_PRIME_NUMBERS=y CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_IOMAP=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y # # Crypto library routines # CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y CONFIG_CRYPTO_LIB_CHACHA=y CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y CONFIG_CRYPTO_LIB_CURVE25519=y CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305=y CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC_T10DIF=y CONFIG_CRC64_ROCKSOFT=y CONFIG_CRC_ITU_T=y CONFIG_CRC32=y CONFIG_CRC32_SELFTEST=y CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_SLICEBY4 is not set # CONFIG_CRC32_SARWATE is not set # CONFIG_CRC32_BIT is not set CONFIG_CRC64=y CONFIG_CRC4=y CONFIG_CRC7=y CONFIG_LIBCRC32C=y CONFIG_CRC8=y CONFIG_XXHASH=y CONFIG_AUDIT_GENERIC=y CONFIG_RANDOM32_SELFTEST=y CONFIG_842_COMPRESS=y CONFIG_842_DECOMPRESS=y CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4_COMPRESS=y CONFIG_LZ4HC_COMPRESS=y CONFIG_LZ4_DECOMPRESS=y CONFIG_ZSTD_COMMON=y CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_IA64=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_SPARC=y CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_BCJ=y CONFIG_XZ_DEC_TEST=y CONFIG_DECOMPRESS_GZIP=y CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_LZMA=y CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_DECOMPRESS_LZ4=y CONFIG_DECOMPRESS_ZSTD=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_REED_SOLOMON=y CONFIG_REED_SOLOMON_ENC8=y CONFIG_REED_SOLOMON_DEC8=y CONFIG_REED_SOLOMON_ENC16=y CONFIG_REED_SOLOMON_DEC16=y CONFIG_BCH=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=y CONFIG_TEXTSEARCH_BM=y CONFIG_TEXTSEARCH_FSM=y CONFIG_BTREE=y CONFIG_INTERVAL_TREE=y CONFIG_XARRAY_MULTI=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y CONFIG_DMA_OPS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_SWIOTLB=y CONFIG_DMA_RESTRICTED_POOL=y CONFIG_DMA_CMA=y CONFIG_DMA_PERNUMA_CMA=y # # Default contiguous memory area size: # CONFIG_CMA_SIZE_MBYTES=0 CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set # CONFIG_CMA_SIZE_SEL_MIN is not set # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 CONFIG_DMA_API_DEBUG=y CONFIG_DMA_API_DEBUG_SG=y CONFIG_DMA_MAP_BENCHMARK=y CONFIG_SGL_ALLOC=y CONFIG_CHECK_SIGNATURE=y CONFIG_CPUMASK_OFFSTACK=y CONFIG_FORCE_NR_CPUS=y CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_GLOB=y CONFIG_GLOB_SELFTEST=y CONFIG_NLATTR=y CONFIG_LRU_CACHE=y CONFIG_CLZ_TAB=y CONFIG_IRQ_POLL=y CONFIG_MPILIB=y CONFIG_SIGNATURE=y CONFIG_DIMLIB=y CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_UCS2_STRING=y CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_VDSO_32=y CONFIG_GENERIC_VDSO_TIME_NS=y CONFIG_FONT_SUPPORT=y CONFIG_FONTS=y CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_FONT_6x11=y CONFIG_FONT_7x14=y CONFIG_FONT_PEARL_8x8=y CONFIG_FONT_ACORN_8x8=y CONFIG_FONT_MINI_4x6=y CONFIG_FONT_6x10=y CONFIG_FONT_10x18=y CONFIG_FONT_SUN8x16=y CONFIG_FONT_SUN12x22=y CONFIG_FONT_TER16x32=y CONFIG_FONT_6x8=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y CONFIG_STACKDEPOT_ALWAYS_INIT=y CONFIG_REF_TRACKER=y CONFIG_SBITMAP=y CONFIG_PARMAN=y CONFIG_OBJAGG=y # end of Library routines CONFIG_PLDMFW=y CONFIG_ASN1_ENCODER=y CONFIG_POLYNOMIAL=y # # Kernel hacking # # # printk and dmesg options # CONFIG_PRINTK_TIME=y CONFIG_PRINTK_CALLER=y CONFIG_STACKTRACE_BUILD_ID=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 CONFIG_BOOT_PRINTK_DELAY=y CONFIG_DYNAMIC_DEBUG=y CONFIG_DYNAMIC_DEBUG_CORE=y CONFIG_SYMBOLIC_ERRNAME=y CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y # # Compile-time checks and compiler options # CONFIG_AS_HAS_NON_CONST_LEB128=y CONFIG_DEBUG_INFO_NONE=y # CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set # CONFIG_DEBUG_INFO_DWARF4 is not set # CONFIG_DEBUG_INFO_DWARF5 is not set CONFIG_FRAME_WARN=2048 CONFIG_STRIP_ASM_SYMS=y CONFIG_READABLE_ASM=y CONFIG_HEADERS_INSTALL=y CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_SECTION_MISMATCH_WARN_ONLY=y CONFIG_FRAME_POINTER=y CONFIG_VMLINUX_MAP=y CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y # end of Compile-time checks and compiler options # # Generic Kernel Debugging Instruments # CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 CONFIG_MAGIC_SYSRQ_SERIAL=y CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y CONFIG_KGDB=y CONFIG_KGDB_HONOUR_BLOCKLIST=y CONFIG_KGDB_SERIAL_CONSOLE=y CONFIG_KGDB_TESTS=y CONFIG_KGDB_TESTS_ON_BOOT=y CONFIG_KGDB_TESTS_BOOT_STRING="V1F100" CONFIG_KGDB_LOW_LEVEL_TRAP=y CONFIG_KGDB_KDB=y CONFIG_KDB_DEFAULT_ENABLE=0x1 CONFIG_KDB_KEYBOARD=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_ARCH_HAS_EARLY_DEBUG=y CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y CONFIG_UBSAN=y # CONFIG_UBSAN_TRAP is not set CONFIG_CC_HAS_UBSAN_BOUNDS=y CONFIG_UBSAN_BOUNDS=y CONFIG_UBSAN_ONLY_BOUNDS=y CONFIG_UBSAN_SHIFT=y CONFIG_UBSAN_DIV_ZERO=y CONFIG_UBSAN_UNREACHABLE=y CONFIG_UBSAN_BOOL=y CONFIG_UBSAN_ENUM=y # CONFIG_UBSAN_ALIGNMENT is not set CONFIG_UBSAN_SANITIZE_ALL=y CONFIG_TEST_UBSAN=m CONFIG_HAVE_KCSAN_COMPILER=y # end of Generic Kernel Debugging Instruments # # Networking Debugging # CONFIG_NET_DEV_REFCNT_TRACKER=y CONFIG_NET_NS_REFCNT_TRACKER=y CONFIG_DEBUG_NET=y # end of Networking Debugging # # Memory Debugging # CONFIG_PAGE_EXTENSION=y CONFIG_DEBUG_PAGEALLOC=y CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y CONFIG_SLUB_DEBUG=y CONFIG_SLUB_DEBUG_ON=y CONFIG_PAGE_OWNER=y CONFIG_PAGE_POISONING=y CONFIG_DEBUG_PAGE_REF=y CONFIG_DEBUG_RODATA_TEST=y CONFIG_ARCH_HAS_DEBUG_WX=y CONFIG_DEBUG_WX=y CONFIG_GENERIC_PTDUMP=y CONFIG_PTDUMP_CORE=y CONFIG_PTDUMP_DEBUGFS=y CONFIG_DEBUG_OBJECTS=y CONFIG_DEBUG_OBJECTS_SELFTEST=y CONFIG_DEBUG_OBJECTS_FREE=y CONFIG_DEBUG_OBJECTS_TIMERS=y CONFIG_DEBUG_OBJECTS_WORK=y CONFIG_DEBUG_OBJECTS_RCU_HEAD=y CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 CONFIG_SHRINKER_DEBUG=y CONFIG_HAVE_DEBUG_KMEMLEAK=y CONFIG_DEBUG_KMEMLEAK=y CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000 CONFIG_DEBUG_KMEMLEAK_TEST=m CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y CONFIG_DEBUG_STACK_USAGE=y CONFIG_SCHED_STACK_END_CHECK=y CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y CONFIG_DEBUG_VM_IRQSOFF=y CONFIG_DEBUG_VM=y CONFIG_DEBUG_VM_MAPLE_TREE=y CONFIG_DEBUG_VM_RB=y CONFIG_DEBUG_VM_PGFLAGS=y CONFIG_DEBUG_VM_PGTABLE=y CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y CONFIG_DEBUG_VIRTUAL=y CONFIG_DEBUG_MEMORY_INIT=y CONFIG_DEBUG_PER_CPU_MAPS=y CONFIG_DEBUG_KMAP_LOCAL=y CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP=y CONFIG_DEBUG_HIGHMEM=y CONFIG_HAVE_DEBUG_STACKOVERFLOW=y CONFIG_DEBUG_STACKOVERFLOW=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y CONFIG_HAVE_ARCH_KFENCE=y CONFIG_KFENCE=y CONFIG_KFENCE_SAMPLE_INTERVAL=100 CONFIG_KFENCE_NUM_OBJECTS=255 CONFIG_KFENCE_DEFERRABLE=y CONFIG_KFENCE_STATIC_KEYS=y CONFIG_KFENCE_STRESS_TEST_FAULTS=0 CONFIG_KFENCE_KUNIT_TEST=y # end of Memory Debugging CONFIG_DEBUG_SHIRQ=y # # Debug Oops, Lockups and Hangs # CONFIG_PANIC_ON_OOPS=y CONFIG_PANIC_ON_OOPS_VALUE=1 CONFIG_PANIC_TIMEOUT=0 CONFIG_LOCKUP_DETECTOR=y CONFIG_SOFTLOCKUP_DETECTOR=y CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y CONFIG_HARDLOCKUP_DETECTOR_PERF=y CONFIG_HARDLOCKUP_DETECTOR=y CONFIG_BOOTPARAM_HARDLOCKUP_PANIC=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y CONFIG_WQ_WATCHDOG=y CONFIG_TEST_LOCKUP=m # end of Debug Oops, Lockups and Hangs # # Scheduler Debugging # CONFIG_SCHED_DEBUG=y CONFIG_SCHED_INFO=y CONFIG_SCHEDSTATS=y # end of Scheduler Debugging CONFIG_DEBUG_TIMEKEEPING=y CONFIG_DEBUG_PREEMPT=y # # Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_PROVE_LOCKING=y CONFIG_PROVE_RAW_LOCK_NESTING=y CONFIG_LOCK_STAT=y CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y CONFIG_DEBUG_RWSEMS=y CONFIG_DEBUG_LOCK_ALLOC=y CONFIG_LOCKDEP=y CONFIG_LOCKDEP_BITS=15 CONFIG_LOCKDEP_CHAINS_BITS=16 CONFIG_LOCKDEP_STACK_TRACE_BITS=19 CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 CONFIG_DEBUG_LOCKDEP=y CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_DEBUG_LOCKING_API_SELFTESTS=y CONFIG_LOCK_TORTURE_TEST=y CONFIG_WW_MUTEX_SELFTEST=y CONFIG_SCF_TORTURE_TEST=y # end of Lock Debugging (spinlocks, mutexes, etc...) CONFIG_TRACE_IRQFLAGS=y CONFIG_TRACE_IRQFLAGS_NMI=y CONFIG_DEBUG_IRQFLAGS=y CONFIG_STACKTRACE=y CONFIG_WARN_ALL_UNSEEDED_RANDOM=y CONFIG_DEBUG_KOBJECT=y CONFIG_DEBUG_KOBJECT_RELEASE=y # # Debug kernel data structures # CONFIG_DEBUG_LIST=y CONFIG_DEBUG_PLIST=y CONFIG_DEBUG_SG=y CONFIG_DEBUG_NOTIFIERS=y CONFIG_BUG_ON_DATA_CORRUPTION=y CONFIG_DEBUG_MAPLE_TREE=y # end of Debug kernel data structures CONFIG_DEBUG_CREDENTIALS=y # # RCU Debugging # CONFIG_PROVE_RCU=y CONFIG_PROVE_RCU_LIST=y CONFIG_TORTURE_TEST=y CONFIG_RCU_SCALE_TEST=y CONFIG_RCU_TORTURE_TEST=y CONFIG_RCU_REF_SCALE_TEST=y CONFIG_RCU_CPU_STALL_TIMEOUT=21 CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 CONFIG_RCU_TRACE=y CONFIG_RCU_EQS_DEBUG=y # end of RCU Debugging CONFIG_DEBUG_WQ_FORCE_RR_CPU=y CONFIG_CPU_HOTPLUG_STATE_CONTROL=y CONFIG_LATENCYTOP=y CONFIG_USER_STACKTRACE_SUPPORT=y CONFIG_NOP_TRACER=y CONFIG_HAVE_RETHOOK=y CONFIG_RETHOOK=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y CONFIG_HAVE_DYNAMIC_FTRACE_NO_PATCHABLE=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_FENTRY=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y CONFIG_BUILDTIME_MCOUNT_SORT=y CONFIG_TRACER_MAX_TRACE=y CONFIG_TRACE_CLOCK=y CONFIG_RING_BUFFER=y CONFIG_EVENT_TRACING=y CONFIG_CONTEXT_SWITCH_TRACER=y CONFIG_RING_BUFFER_ALLOW_SWAP=y CONFIG_PREEMPTIRQ_TRACEPOINTS=y CONFIG_TRACING=y CONFIG_GENERIC_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y CONFIG_BOOTTIME_TRACING=y CONFIG_FUNCTION_TRACER=y CONFIG_FUNCTION_GRAPH_TRACER=y CONFIG_DYNAMIC_FTRACE=y CONFIG_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y CONFIG_FPROBE=y CONFIG_FUNCTION_PROFILER=y CONFIG_STACK_TRACER=y CONFIG_TRACE_PREEMPT_TOGGLE=y CONFIG_IRQSOFF_TRACER=y CONFIG_PREEMPT_TRACER=y CONFIG_SCHED_TRACER=y CONFIG_HWLAT_TRACER=y CONFIG_OSNOISE_TRACER=y CONFIG_TIMERLAT_TRACER=y CONFIG_MMIOTRACE=y CONFIG_FTRACE_SYSCALLS=y CONFIG_TRACER_SNAPSHOT=y CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set CONFIG_BLK_DEV_IO_TRACE=y CONFIG_KPROBE_EVENTS=y CONFIG_KPROBE_EVENTS_ON_NOTRACE=y CONFIG_UPROBE_EVENTS=y CONFIG_BPF_EVENTS=y CONFIG_DYNAMIC_EVENTS=y CONFIG_PROBE_EVENTS=y CONFIG_BPF_KPROBE_OVERRIDE=y CONFIG_FTRACE_MCOUNT_RECORD=y CONFIG_FTRACE_MCOUNT_USE_CC=y CONFIG_TRACING_MAP=y CONFIG_SYNTH_EVENTS=y CONFIG_HIST_TRIGGERS=y CONFIG_TRACE_EVENT_INJECT=y CONFIG_TRACEPOINT_BENCHMARK=y CONFIG_RING_BUFFER_BENCHMARK=y CONFIG_TRACE_EVAL_MAP_FILE=y CONFIG_FTRACE_RECORD_RECURSION=y CONFIG_FTRACE_RECORD_RECURSION_SIZE=128 CONFIG_RING_BUFFER_RECORD_RECURSION=y CONFIG_GCOV_PROFILE_FTRACE=y CONFIG_FTRACE_SELFTEST=y CONFIG_FTRACE_STARTUP_TEST=y CONFIG_EVENT_TRACE_STARTUP_TEST=y CONFIG_EVENT_TRACE_TEST_SYSCALLS=y CONFIG_FTRACE_SORT_STARTUP_TEST=y CONFIG_RING_BUFFER_STARTUP_TEST=y CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS=y CONFIG_MMIOTRACE_TEST=m CONFIG_PREEMPTIRQ_DELAY_TEST=m CONFIG_SYNTH_EVENT_GEN_TEST=y CONFIG_KPROBE_EVENT_GEN_TEST=y CONFIG_HIST_TRIGGERS_DEBUG=y CONFIG_DA_MON_EVENTS=y CONFIG_DA_MON_EVENTS_IMPLICIT=y CONFIG_DA_MON_EVENTS_ID=y CONFIG_RV=y CONFIG_RV_MON_WIP=y CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PRINTK=y CONFIG_RV_REACT_PANIC=y CONFIG_PROVIDE_OHCI1394_DMA_INIT=y CONFIG_SAMPLES=y CONFIG_SAMPLE_AUXDISPLAY=y CONFIG_SAMPLE_TRACE_EVENTS=m CONFIG_SAMPLE_TRACE_CUSTOM_EVENTS=m CONFIG_SAMPLE_TRACE_PRINTK=m CONFIG_SAMPLE_TRACE_ARRAY=m CONFIG_SAMPLE_KOBJECT=y CONFIG_SAMPLE_KPROBES=m CONFIG_SAMPLE_KRETPROBES=m CONFIG_SAMPLE_HW_BREAKPOINT=m CONFIG_SAMPLE_FPROBE=m CONFIG_SAMPLE_KFIFO=m CONFIG_SAMPLE_KDB=m CONFIG_SAMPLE_RPMSG_CLIENT=m CONFIG_SAMPLE_CONFIGFS=m CONFIG_SAMPLE_CONNECTOR=m CONFIG_SAMPLE_FANOTIFY_ERROR=y CONFIG_SAMPLE_HIDRAW=y CONFIG_SAMPLE_LANDLOCK=y CONFIG_SAMPLE_PIDFD=y CONFIG_SAMPLE_SECCOMP=y CONFIG_SAMPLE_TIMER=y CONFIG_SAMPLE_UHID=y CONFIG_SAMPLE_VFIO_MDEV_MTTY=m CONFIG_SAMPLE_VFIO_MDEV_MDPY=m CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB=m CONFIG_SAMPLE_VFIO_MDEV_MBOCHS=m CONFIG_SAMPLE_ANDROID_BINDERFS=y CONFIG_SAMPLE_VFS=y CONFIG_SAMPLE_INTEL_MEI=y CONFIG_SAMPLE_WATCHDOG=y CONFIG_SAMPLE_WATCH_QUEUE=y CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y CONFIG_STRICT_DEVMEM=y CONFIG_IO_STRICT_DEVMEM=y # # x86 Debugging # CONFIG_EARLY_PRINTK_USB=y CONFIG_X86_VERBOSE_BOOTUP=y CONFIG_EARLY_PRINTK=y CONFIG_EARLY_PRINTK_DBGP=y CONFIG_EARLY_PRINTK_USB_XDBC=y CONFIG_EFI_PGT_DUMP=y CONFIG_DEBUG_TLBFLUSH=y CONFIG_HAVE_MMIOTRACE_SUPPORT=y # CONFIG_X86_DECODER_SELFTEST is not set CONFIG_IO_DELAY_0X80=y # CONFIG_IO_DELAY_0XED is not set # CONFIG_IO_DELAY_UDELAY is not set # CONFIG_IO_DELAY_NONE is not set CONFIG_DEBUG_BOOT_PARAMS=y CONFIG_CPA_DEBUG=y CONFIG_DEBUG_ENTRY=y CONFIG_DEBUG_NMI_SELFTEST=y CONFIG_DEBUG_IMR_SELFTEST=y CONFIG_X86_DEBUG_FPU=y CONFIG_PUNIT_ATOM_DEBUG=y CONFIG_UNWINDER_FRAME_POINTER=y # end of x86 Debugging # # Kernel Testing and Coverage # CONFIG_KUNIT=y CONFIG_KUNIT_DEBUGFS=y CONFIG_KUNIT_TEST=y CONFIG_KUNIT_EXAMPLE_TEST=y CONFIG_KUNIT_ALL_TESTS=y CONFIG_KUNIT_DEFAULT_ENABLED=y CONFIG_NOTIFIER_ERROR_INJECTION=y CONFIG_PM_NOTIFIER_ERROR_INJECT=y CONFIG_OF_RECONFIG_NOTIFIER_ERROR_INJECT=y CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=y CONFIG_FUNCTION_ERROR_INJECTION=y CONFIG_FAULT_INJECTION=y CONFIG_FAILSLAB=y CONFIG_FAIL_PAGE_ALLOC=y CONFIG_FAULT_INJECTION_USERCOPY=y CONFIG_FAIL_MAKE_REQUEST=y CONFIG_FAIL_IO_TIMEOUT=y CONFIG_FAIL_FUTEX=y CONFIG_FAULT_INJECTION_DEBUG_FS=y CONFIG_FAIL_FUNCTION=y CONFIG_FAIL_MMC_REQUEST=y CONFIG_FAIL_SUNRPC=y CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_RUNTIME_TESTING_MENU=y CONFIG_LKDTM=y CONFIG_CPUMASK_KUNIT_TEST=y CONFIG_TEST_LIST_SORT=y CONFIG_TEST_MIN_HEAP=y CONFIG_TEST_SORT=y CONFIG_TEST_DIV64=y CONFIG_KPROBES_SANITY_TEST=y CONFIG_FPROBE_SANITY_TEST=y CONFIG_BACKTRACE_SELF_TEST=y CONFIG_TEST_REF_TRACKER=y CONFIG_RBTREE_TEST=y CONFIG_REED_SOLOMON_TEST=y CONFIG_INTERVAL_TREE_TEST=y CONFIG_PERCPU_TEST=m CONFIG_ATOMIC64_SELFTEST=y CONFIG_ASYNC_RAID6_TEST=y CONFIG_TEST_HEXDUMP=y CONFIG_STRING_SELFTEST=y CONFIG_TEST_STRING_HELPERS=y # CONFIG_TEST_STRSCPY is not set CONFIG_TEST_KSTRTOX=y CONFIG_TEST_PRINTF=y CONFIG_TEST_SCANF=y CONFIG_TEST_BITMAP=y CONFIG_TEST_UUID=y CONFIG_TEST_XARRAY=y CONFIG_TEST_RHASHTABLE=y # CONFIG_TEST_SIPHASH is not set CONFIG_TEST_IDA=y CONFIG_TEST_PARMAN=y CONFIG_TEST_LKM=m CONFIG_TEST_BITOPS=m CONFIG_TEST_VMALLOC=m CONFIG_TEST_USER_COPY=m CONFIG_TEST_BPF=m CONFIG_TEST_BLACKHOLE_DEV=m CONFIG_FIND_BIT_BENCHMARK=y CONFIG_TEST_FIRMWARE=y CONFIG_TEST_SYSCTL=y CONFIG_BITFIELD_KUNIT=y CONFIG_HASH_KUNIT_TEST=y CONFIG_RESOURCE_KUNIT_TEST=y CONFIG_SYSCTL_KUNIT_TEST=y CONFIG_LIST_KUNIT_TEST=y CONFIG_LINEAR_RANGES_TEST=y CONFIG_CMDLINE_KUNIT_TEST=y CONFIG_BITS_TEST=y CONFIG_SLUB_KUNIT_TEST=y CONFIG_RATIONAL_KUNIT_TEST=y CONFIG_MEMCPY_KUNIT_TEST=y CONFIG_IS_SIGNED_TYPE_KUNIT_TEST=y CONFIG_OVERFLOW_KUNIT_TEST=y CONFIG_STACKINIT_KUNIT_TEST=y CONFIG_FORTIFY_KUNIT_TEST=y CONFIG_HW_BREAKPOINT_KUNIT_TEST=y CONFIG_TEST_UDELAY=y CONFIG_TEST_STATIC_KEYS=m CONFIG_TEST_DYNAMIC_DEBUG=y CONFIG_TEST_KMOD=m CONFIG_TEST_DEBUG_VIRTUAL=y CONFIG_TEST_MEMCAT_P=y CONFIG_TEST_OBJAGG=y CONFIG_TEST_MEMINIT=y CONFIG_TEST_FREE_PAGES=y CONFIG_TEST_FPU=y CONFIG_TEST_CLOCKSOURCE_WATCHDOG=y CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y CONFIG_HYPERV_TESTING=y # end of Kernel Testing and Coverage # # Rust hacking # # end of Rust hacking # end of Kernel hacking ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 12/12] ASoC: cs48l32: Add codec driver for Cirrus Logic CS48L31/32/33 @ 2022-11-10 20:20 ` kernel test robot 0 siblings, 0 replies; 98+ messages in thread From: kernel test robot @ 2022-11-10 20:20 UTC (permalink / raw) To: Richard Fitzgerald, lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, broonie, tglx, maz Cc: devicetree, alsa-devel, patches, linux-kernel, linux-gpio, Richard Fitzgerald, oe-kbuild-all [-- Attachment #1: Type: text/plain, Size: 2418 bytes --] Hi Richard, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on broonie-sound/for-next] [also build test WARNING on lee-mfd/for-mfd-next linusw-pinctrl/devel linusw-pinctrl/for-next broonie-regulator/for-next linus/master] [cannot apply to lee-mfd/for-mfd-fixes] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Richard-Fitzgerald/Add-support-for-the-Cirrus-Logic-CS48L32-audio-codecs/20221110-005630 base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next patch link: https://lore.kernel.org/r/20221109165331.29332-13-rf%40opensource.cirrus.com patch subject: [PATCH 12/12] ASoC: cs48l32: Add codec driver for Cirrus Logic CS48L31/32/33 config: i386-allyesconfig compiler: gcc-11 (Debian 11.3.0-8) 11.3.0 reproduce (this is a W=1 build): # https://github.com/intel-lab-lkp/linux/commit/66bc34007a7eabb0b819d76e13de3c33562b4525 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Richard-Fitzgerald/Add-support-for-the-Cirrus-Logic-CS48L32-audio-codecs/20221110-005630 git checkout 66bc34007a7eabb0b819d76e13de3c33562b4525 # save the config file mkdir build_dir && cp config build_dir/.config make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/pci/controller/cadence/ sound/soc/codecs/ sound/soc/intel/boards/ If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot <lkp@intel.com> All warnings (new ones prefixed by >>): >> sound/soc/codecs/cs48l32-core.c:2257:8: warning: type qualifiers ignored on function return type [-Wignored-qualifiers] 2257 | static const char * const cs48l32_dai_clk_str(int clk_id) | ^~~~~ vim +2257 sound/soc/codecs/cs48l32-core.c 2256 > 2257 static const char * const cs48l32_dai_clk_str(int clk_id) 2258 { 2259 switch (clk_id) { 2260 case CS48L32_CLK_SYSCLK_1: 2261 case CS48L32_CLK_SYSCLK_2: 2262 case CS48L32_CLK_SYSCLK_3: 2263 case CS48L32_CLK_SYSCLK_4: 2264 return "SYSCLK"; 2265 default: 2266 return "Unknown clock"; 2267 } 2268 } 2269 -- 0-DAY CI Kernel Test Service https://01.org/lkp [-- Attachment #2: config --] [-- Type: text/plain, Size: 288302 bytes --] # # Automatically generated file; DO NOT EDIT. # Linux/i386 6.1.0-rc1 Kernel Configuration # CONFIG_CC_VERSION_TEXT="gcc-11 (Debian 11.3.0-8) 11.3.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=110300 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y CONFIG_AS_VERSION=23900 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23900 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=123 CONFIG_CONSTRUCTORS=y CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y # # General setup # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set # CONFIG_WERROR is not set CONFIG_UAPI_HEADER_TEST=y CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_BZIP2=y CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_XZ=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_HAVE_KERNEL_LZ4=y CONFIG_HAVE_KERNEL_ZSTD=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_BZIP2 is not set # CONFIG_KERNEL_LZMA is not set # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set # CONFIG_KERNEL_ZSTD is not set CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_WATCH_QUEUE=y CONFIG_CROSS_MEMORY_ATTACH=y CONFIG_USELIB=y CONFIG_AUDIT=y CONFIG_HAVE_ARCH_AUDITSYSCALL=y CONFIG_AUDITSYSCALL=y # # IRQ subsystem # CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_PENDING_IRQ=y CONFIG_GENERIC_IRQ_MIGRATION=y CONFIG_GENERIC_IRQ_INJECTION=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_CHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_SIM=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_IRQ_MSI_IOMMU=y CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y CONFIG_GENERIC_IRQ_RESERVATION_MODE=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y CONFIG_GENERIC_IRQ_DEBUGFS=y # end of IRQ subsystem CONFIG_CLOCKSOURCE_WATCHDOG=y CONFIG_ARCH_CLOCKSOURCE_INIT=y CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_TIME_KUNIT_TEST=y CONFIG_CONTEXT_TRACKING=y CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem # CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ_COMMON=y # CONFIG_HZ_PERIODIC is not set CONFIG_NO_HZ_IDLE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 # end of Timers subsystem CONFIG_BPF=y CONFIG_HAVE_EBPF_JIT=y # # BPF subsystem # CONFIG_BPF_SYSCALL=y CONFIG_BPF_JIT=y CONFIG_BPF_JIT_ALWAYS_ON=y CONFIG_BPF_JIT_DEFAULT_ON=y CONFIG_BPF_UNPRIV_DEFAULT_OFF=y CONFIG_USERMODE_DRIVER=y # CONFIG_BPF_PRELOAD is not set CONFIG_BPF_LSM=y # end of BPF subsystem CONFIG_PREEMPT_BUILD=y CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_PREEMPT_COUNT=y CONFIG_PREEMPTION=y CONFIG_PREEMPT_DYNAMIC=y CONFIG_SCHED_CORE=y # # CPU/Task time and stats accounting # CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_SCHED_AVG_IRQ=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y CONFIG_PSI=y CONFIG_PSI_DEFAULT_DISABLED=y # end of CPU/Task time and stats accounting CONFIG_CPU_ISOLATION=y # # RCU Subsystem # CONFIG_TREE_RCU=y CONFIG_PREEMPT_RCU=y CONFIG_RCU_EXPERT=y CONFIG_SRCU=y CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU_GENERIC=y CONFIG_FORCE_TASKS_RCU=y CONFIG_TASKS_RCU=y CONFIG_FORCE_TASKS_RUDE_RCU=y CONFIG_TASKS_RUDE_RCU=y CONFIG_FORCE_TASKS_TRACE_RCU=y CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y CONFIG_RCU_FANOUT=32 CONFIG_RCU_FANOUT_LEAF=16 CONFIG_RCU_BOOST=y CONFIG_RCU_BOOST_DELAY=500 CONFIG_RCU_EXP_KTHREAD=y CONFIG_RCU_NOCB_CPU=y CONFIG_RCU_NOCB_CPU_DEFAULT_ALL=y CONFIG_RCU_NOCB_CPU_CB_BOOST=y CONFIG_TASKS_TRACE_RCU_READ_MB=y # end of RCU Subsystem CONFIG_BUILD_BIN2C=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_IKHEADERS=y CONFIG_LOG_BUF_SHIFT=17 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 CONFIG_PRINTK_INDEX=y CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y # # Scheduler features # CONFIG_UCLAMP_TASK=y CONFIG_UCLAMP_BUCKETS_COUNT=5 # end of Scheduler features CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y CONFIG_CGROUP_FAVOR_DYNMODS=y CONFIG_MEMCG=y CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y CONFIG_RT_GROUP_SCHED=y CONFIG_UCLAMP_TASK_GROUP=y CONFIG_CGROUP_PIDS=y CONFIG_CGROUP_RDMA=y CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_HUGETLB=y CONFIG_CPUSETS=y CONFIG_PROC_PID_CPUSET=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y CONFIG_CGROUP_MISC=y CONFIG_CGROUP_DEBUG=y CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y CONFIG_UTS_NS=y CONFIG_TIME_NS=y CONFIG_IPC_NS=y CONFIG_USER_NS=y CONFIG_PID_NS=y CONFIG_NET_NS=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_SCHED_AUTOGROUP=y CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y CONFIG_RD_XZ=y CONFIG_RD_LZO=y CONFIG_RD_LZ4=y CONFIG_RD_ZSTD=y CONFIG_BOOT_CONFIG=y CONFIG_BOOT_CONFIG_EMBED=y CONFIG_BOOT_CONFIG_EMBED_FILE="" CONFIG_INITRAMFS_PRESERVE_MTIME=y CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_HAVE_PCSPKR_PLATFORM=y CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_MULTIUSER=y CONFIG_SGETMASK_SYSCALL=y CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_PCSPKR_PLATFORM=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y CONFIG_RSEQ=y CONFIG_DEBUG_RSEQ=y CONFIG_EMBEDDED=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_GUEST_PERF_EVENTS=y CONFIG_PERF_USE_VMALLOC=y CONFIG_PC104=y # # Kernel Performance Events And Counters # CONFIG_PERF_EVENTS=y CONFIG_DEBUG_PERF_USE_VMALLOC=y # end of Kernel Performance Events And Counters CONFIG_SYSTEM_DATA_VERIFICATION=y CONFIG_PROFILING=y CONFIG_TRACEPOINTS=y # end of General setup CONFIG_X86_32=y CONFIG_FORCE_DYNAMIC_FTRACE=y CONFIG_X86=y CONFIG_INSTRUCTION_DECODER=y CONFIG_OUTPUT_FORMAT="elf32-i386" CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_MMU=y CONFIG_ARCH_MMAP_RND_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=16 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 CONFIG_GENERIC_ISA_DMA=y CONFIG_GENERIC_BUG=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_HAS_CPU_RELAX=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_NR_GPIO=512 CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_HAVE_INTEL_TXT=y CONFIG_X86_32_SMP=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_PGTABLE_LEVELS=2 CONFIG_CC_HAS_SANE_STACKPROTECTOR=y # # Processor type and features # CONFIG_SMP=y CONFIG_X86_FEATURE_NAMES=y CONFIG_X86_MPPARSE=y CONFIG_GOLDFISH=y CONFIG_X86_CPU_RESCTRL=y CONFIG_X86_BIGSMP=y CONFIG_X86_EXTENDED_PLATFORM=y CONFIG_X86_GOLDFISH=y CONFIG_X86_INTEL_MID=y CONFIG_X86_INTEL_QUARK=y CONFIG_X86_INTEL_LPSS=y CONFIG_X86_AMD_PLATFORM_DEVICE=y CONFIG_IOSF_MBI=y CONFIG_IOSF_MBI_DEBUG=y CONFIG_X86_RDC321X=y CONFIG_X86_32_NON_STANDARD=y CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y CONFIG_STA2X11=y CONFIG_X86_32_IRIS=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_HYPERVISOR_GUEST=y CONFIG_PARAVIRT=y CONFIG_PARAVIRT_DEBUG=y CONFIG_PARAVIRT_SPINLOCKS=y CONFIG_X86_HV_CALLBACK_VECTOR=y CONFIG_KVM_GUEST=y CONFIG_ARCH_CPUIDLE_HALTPOLL=y CONFIG_PVH=y CONFIG_PARAVIRT_TIME_ACCOUNTING=y CONFIG_PARAVIRT_CLOCK=y # CONFIG_M486SX is not set # CONFIG_M486 is not set # CONFIG_M586 is not set # CONFIG_M586TSC is not set # CONFIG_M586MMX is not set CONFIG_M686=y # CONFIG_MPENTIUMII is not set # CONFIG_MPENTIUMIII is not set # CONFIG_MPENTIUMM is not set # CONFIG_MPENTIUM4 is not set # CONFIG_MK6 is not set # CONFIG_MK7 is not set # CONFIG_MK8 is not set # CONFIG_MCRUSOE is not set # CONFIG_MEFFICEON is not set # CONFIG_MWINCHIPC6 is not set # CONFIG_MWINCHIP3D is not set # CONFIG_MELAN is not set # CONFIG_MGEODEGX1 is not set # CONFIG_MGEODE_LX is not set # CONFIG_MCYRIXIII is not set # CONFIG_MVIAC3_2 is not set # CONFIG_MVIAC7 is not set # CONFIG_MCORE2 is not set # CONFIG_MATOM is not set CONFIG_X86_GENERIC=y CONFIG_X86_INTERNODE_CACHE_SHIFT=6 CONFIG_X86_L1_CACHE_SHIFT=6 CONFIG_X86_INTEL_USERCOPY=y CONFIG_X86_USE_PPRO_CHECKSUM=y CONFIG_X86_TSC=y CONFIG_X86_CMPXCHG64=y CONFIG_X86_CMOV=y CONFIG_X86_MINIMUM_CPU_FAMILY=6 CONFIG_X86_DEBUGCTLMSR=y CONFIG_IA32_FEAT_CTL=y CONFIG_X86_VMX_FEATURE_NAMES=y CONFIG_PROCESSOR_SELECT=y CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_CYRIX_32=y CONFIG_CPU_SUP_AMD=y CONFIG_CPU_SUP_HYGON=y CONFIG_CPU_SUP_CENTAUR=y CONFIG_CPU_SUP_TRANSMETA_32=y CONFIG_CPU_SUP_UMC_32=y CONFIG_CPU_SUP_ZHAOXIN=y CONFIG_CPU_SUP_VORTEX_32=y CONFIG_HPET_TIMER=y CONFIG_HPET_EMULATE_RTC=y CONFIG_DMI=y CONFIG_BOOT_VESA_SUPPORT=y CONFIG_NR_CPUS_RANGE_BEGIN=2 CONFIG_NR_CPUS_RANGE_END=64 CONFIG_NR_CPUS_DEFAULT=32 CONFIG_NR_CPUS=32 CONFIG_SCHED_CLUSTER=y CONFIG_SCHED_SMT=y CONFIG_SCHED_MC=y CONFIG_SCHED_MC_PRIO=y CONFIG_X86_LOCAL_APIC=y CONFIG_X86_IO_APIC=y CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y CONFIG_X86_MCE=y CONFIG_X86_MCELOG_LEGACY=y CONFIG_X86_MCE_INTEL=y CONFIG_X86_MCE_AMD=y CONFIG_X86_ANCIENT_MCE=y CONFIG_X86_MCE_THRESHOLD=y CONFIG_X86_MCE_INJECT=y # # Performance monitoring # CONFIG_PERF_EVENTS_INTEL_UNCORE=y CONFIG_PERF_EVENTS_INTEL_RAPL=y CONFIG_PERF_EVENTS_INTEL_CSTATE=y CONFIG_PERF_EVENTS_AMD_POWER=y CONFIG_PERF_EVENTS_AMD_UNCORE=y CONFIG_PERF_EVENTS_AMD_BRS=y # end of Performance monitoring CONFIG_X86_LEGACY_VM86=y CONFIG_VM86=y CONFIG_X86_16BIT=y CONFIG_X86_ESPFIX32=y CONFIG_X86_IOPL_IOPERM=y CONFIG_TOSHIBA=y CONFIG_X86_REBOOTFIXUPS=y CONFIG_MICROCODE=y CONFIG_MICROCODE_INTEL=y CONFIG_MICROCODE_AMD=y CONFIG_MICROCODE_LATE_LOADING=y CONFIG_X86_MSR=y CONFIG_X86_CPUID=y # CONFIG_NOHIGHMEM is not set CONFIG_HIGHMEM4G=y # CONFIG_HIGHMEM64G is not set CONFIG_VMSPLIT_3G=y # CONFIG_VMSPLIT_3G_OPT is not set # CONFIG_VMSPLIT_2G is not set # CONFIG_VMSPLIT_2G_OPT is not set # CONFIG_VMSPLIT_1G is not set CONFIG_PAGE_OFFSET=0xC0000000 CONFIG_HIGHMEM=y CONFIG_X86_CPA_STATISTICS=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ILLEGAL_POINTER_VALUE=0 CONFIG_HIGHPTE=y CONFIG_X86_CHECK_BIOS_CORRUPTION=y CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y CONFIG_MTRR=y CONFIG_MTRR_SANITIZER=y CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0 CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 CONFIG_X86_PAT=y CONFIG_ARCH_USES_PG_UNCACHED=y CONFIG_X86_UMIP=y CONFIG_CC_HAS_IBT=y CONFIG_X86_INTEL_TSX_MODE_OFF=y # CONFIG_X86_INTEL_TSX_MODE_ON is not set # CONFIG_X86_INTEL_TSX_MODE_AUTO is not set CONFIG_EFI=y CONFIG_EFI_STUB=y # CONFIG_HZ_100 is not set CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 CONFIG_SCHED_HRTICK=y CONFIG_KEXEC=y CONFIG_CRASH_DUMP=y CONFIG_KEXEC_JUMP=y CONFIG_PHYSICAL_START=0x1000000 CONFIG_RELOCATABLE=y # CONFIG_RANDOMIZE_BASE is not set CONFIG_X86_NEED_RELOCS=y CONFIG_PHYSICAL_ALIGN=0x200000 CONFIG_HOTPLUG_CPU=y CONFIG_BOOTPARAM_HOTPLUG_CPU0=y CONFIG_DEBUG_HOTPLUG_CPU0=y CONFIG_COMPAT_VDSO=y CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="" CONFIG_MODIFY_LDT_SYSCALL=y CONFIG_STRICT_SIGALTSTACK_SIZE=y # end of Processor type and features CONFIG_CC_HAS_SLS=y CONFIG_CC_HAS_RETURN_THUNK=y CONFIG_SPECULATION_MITIGATIONS=y CONFIG_RETPOLINE=y CONFIG_RETHUNK=y CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y # # Power management and ACPI options # CONFIG_ARCH_HIBERNATION_HEADER=y CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y CONFIG_SUSPEND_SKIP_SYNC=y CONFIG_HIBERNATE_CALLBACKS=y CONFIG_HIBERNATION=y CONFIG_HIBERNATION_SNAPSHOT_DEV=y CONFIG_PM_STD_PARTITION="" CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y CONFIG_PM_AUTOSLEEP=y CONFIG_PM_USERSPACE_AUTOSLEEP=y CONFIG_PM_WAKELOCKS=y CONFIG_PM_WAKELOCKS_LIMIT=100 CONFIG_PM_WAKELOCKS_GC=y CONFIG_PM=y CONFIG_PM_DEBUG=y CONFIG_PM_ADVANCED_DEBUG=y CONFIG_PM_TEST_SUSPEND=y CONFIG_PM_SLEEP_DEBUG=y CONFIG_DPM_WATCHDOG=y CONFIG_DPM_WATCHDOG_TIMEOUT=120 CONFIG_PM_TRACE=y CONFIG_PM_TRACE_RTC=y CONFIG_PM_CLK=y CONFIG_PM_GENERIC_DOMAINS=y CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y CONFIG_PM_GENERIC_DOMAINS_SLEEP=y CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_ENERGY_MODEL=y CONFIG_ARCH_SUPPORTS_ACPI=y CONFIG_ACPI=y CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y CONFIG_ACPI_TABLE_LIB=y CONFIG_ACPI_DEBUGGER=y CONFIG_ACPI_DEBUGGER_USER=y CONFIG_ACPI_SPCR_TABLE=y CONFIG_ACPI_SLEEP=y CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y CONFIG_ACPI_EC_DEBUGFS=y CONFIG_ACPI_AC=y CONFIG_ACPI_BATTERY=y CONFIG_ACPI_BUTTON=y CONFIG_ACPI_VIDEO=y CONFIG_ACPI_FAN=y CONFIG_ACPI_TAD=y CONFIG_ACPI_DOCK=y CONFIG_ACPI_CPU_FREQ_PSS=y CONFIG_ACPI_PROCESSOR_CSTATE=y CONFIG_ACPI_PROCESSOR_IDLE=y CONFIG_ACPI_PROCESSOR=y CONFIG_ACPI_IPMI=y CONFIG_ACPI_HOTPLUG_CPU=y CONFIG_ACPI_PROCESSOR_AGGREGATOR=y CONFIG_ACPI_THERMAL=y CONFIG_ACPI_PLATFORM_PROFILE=y CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y CONFIG_ACPI_TABLE_UPGRADE=y CONFIG_ACPI_DEBUG=y CONFIG_ACPI_PCI_SLOT=y CONFIG_ACPI_CONTAINER=y CONFIG_ACPI_HOTPLUG_IOAPIC=y CONFIG_ACPI_SBS=y CONFIG_ACPI_HED=y CONFIG_ACPI_CUSTOM_METHOD=y CONFIG_ACPI_BGRT=y CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y CONFIG_HAVE_ACPI_APEI=y CONFIG_HAVE_ACPI_APEI_NMI=y CONFIG_ACPI_APEI=y CONFIG_ACPI_APEI_GHES=y CONFIG_ACPI_APEI_PCIEAER=y CONFIG_ACPI_APEI_MEMORY_FAILURE=y CONFIG_ACPI_APEI_EINJ=y CONFIG_ACPI_APEI_ERST_DEBUG=y CONFIG_ACPI_DPTF=y CONFIG_DPTF_POWER=y CONFIG_DPTF_PCH_FIVR=y CONFIG_ACPI_WATCHDOG=y CONFIG_ACPI_EXTLOG=y CONFIG_ACPI_CONFIGFS=y CONFIG_ACPI_PCC=y CONFIG_PMIC_OPREGION=y CONFIG_BYTCRC_PMIC_OPREGION=y CONFIG_CHTCRC_PMIC_OPREGION=y CONFIG_XPOWER_PMIC_OPREGION=y CONFIG_BXT_WC_PMIC_OPREGION=y CONFIG_CHT_WC_PMIC_OPREGION=y CONFIG_CHT_DC_TI_PMIC_OPREGION=y CONFIG_TPS68470_PMIC_OPREGION=y CONFIG_ACPI_VIOT=y CONFIG_X86_PM_TIMER=y CONFIG_X86_APM_BOOT=y CONFIG_APM=y CONFIG_APM_IGNORE_USER_SUSPEND=y CONFIG_APM_DO_ENABLE=y CONFIG_APM_CPU_IDLE=y CONFIG_APM_DISPLAY_BLANK=y CONFIG_APM_ALLOW_INTS=y # # CPU Frequency scaling # CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_GOV_ATTR_SET=y CONFIG_CPU_FREQ_GOV_COMMON=y CONFIG_CPU_FREQ_STAT=y # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y CONFIG_CPU_FREQ_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # # CPU frequency scaling drivers # CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y CONFIG_X86_INTEL_PSTATE=y CONFIG_X86_PCC_CPUFREQ=y CONFIG_X86_AMD_PSTATE=y CONFIG_X86_AMD_PSTATE_UT=y CONFIG_X86_ACPI_CPUFREQ=y CONFIG_X86_ACPI_CPUFREQ_CPB=y CONFIG_X86_POWERNOW_K6=y CONFIG_X86_POWERNOW_K7=y CONFIG_X86_POWERNOW_K7_ACPI=y CONFIG_X86_POWERNOW_K8=y CONFIG_X86_AMD_FREQ_SENSITIVITY=y CONFIG_X86_GX_SUSPMOD=y CONFIG_X86_SPEEDSTEP_CENTRINO=y CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE=y CONFIG_X86_SPEEDSTEP_ICH=y CONFIG_X86_SPEEDSTEP_SMI=y CONFIG_X86_P4_CLOCKMOD=y CONFIG_X86_CPUFREQ_NFORCE2=y CONFIG_X86_LONGRUN=y CONFIG_X86_LONGHAUL=y CONFIG_X86_E_POWERSAVER=y # # shared options # CONFIG_X86_SPEEDSTEP_LIB=y CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK=y # end of CPU Frequency scaling # # CPU Idle # CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_GOV_TEO=y CONFIG_CPU_IDLE_GOV_HALTPOLL=y CONFIG_HALTPOLL_CPUIDLE=y # end of CPU Idle CONFIG_INTEL_IDLE=y # end of Power management and ACPI options # # Bus options (PCI etc.) # # CONFIG_PCI_GOBIOS is not set # CONFIG_PCI_GOMMCONFIG is not set # CONFIG_PCI_GODIRECT is not set # CONFIG_PCI_GOOLPC is not set CONFIG_PCI_GOANY=y CONFIG_PCI_BIOS=y CONFIG_PCI_DIRECT=y CONFIG_PCI_MMCONFIG=y CONFIG_PCI_OLPC=y CONFIG_PCI_CNB20LE_QUIRK=y CONFIG_ISA_BUS=y CONFIG_ISA_DMA_API=y CONFIG_ISA=y CONFIG_SCx200=y CONFIG_SCx200HR_TIMER=y CONFIG_OLPC=y CONFIG_OLPC_XO1_PM=y CONFIG_OLPC_XO1_RTC=y CONFIG_OLPC_XO1_SCI=y CONFIG_OLPC_XO15_SCI=y CONFIG_ALIX=y CONFIG_NET5501=y CONFIG_GEOS=y CONFIG_AMD_NB=y # end of Bus options (PCI etc.) # # Binary Emulations # CONFIG_COMPAT_32=y # end of Binary Emulations CONFIG_HAVE_ATOMIC_IOMAP=y CONFIG_HAVE_KVM=y CONFIG_HAVE_KVM_PFNCACHE=y CONFIG_HAVE_KVM_IRQCHIP=y CONFIG_HAVE_KVM_IRQFD=y CONFIG_HAVE_KVM_IRQ_ROUTING=y CONFIG_HAVE_KVM_DIRTY_RING=y CONFIG_HAVE_KVM_DIRTY_RING_TSO=y CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y CONFIG_HAVE_KVM_EVENTFD=y CONFIG_KVM_MMIO=y CONFIG_KVM_ASYNC_PF=y CONFIG_HAVE_KVM_MSI=y CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y CONFIG_KVM_VFIO=y CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y CONFIG_HAVE_KVM_IRQ_BYPASS=y CONFIG_HAVE_KVM_NO_POLL=y CONFIG_KVM_XFER_TO_GUEST_WORK=y CONFIG_HAVE_KVM_PM_NOTIFIER=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=y # CONFIG_KVM_WERROR is not set CONFIG_KVM_INTEL=y CONFIG_KVM_AMD=y CONFIG_KVM_XEN=y CONFIG_AS_AVX512=y CONFIG_AS_SHA1_NI=y CONFIG_AS_SHA256_NI=y CONFIG_AS_TPAUSE=y # # General architecture-dependent options # CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y CONFIG_HOTPLUG_SMT=y CONFIG_GENERIC_ENTRY=y CONFIG_KPROBES=y CONFIG_JUMP_LABEL=y CONFIG_STATIC_KEYS_SELFTEST=y CONFIG_STATIC_CALL_SELFTEST=y CONFIG_OPTPROBES=y CONFIG_KPROBES_ON_FTRACE=y CONFIG_UPROBES=y CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_KRETPROBES=y CONFIG_KRETPROBE_ON_RETHOOK=y CONFIG_USER_RETURN_NOTIFIER=y CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_OPTPROBES=y CONFIG_HAVE_KPROBES_ON_FTRACE=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y CONFIG_HAVE_NMI=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_ARCH_HAS_FORTIFY_SOURCE=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_ARCH_32BIT_OFF_T=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y CONFIG_HAVE_USER_RETURN_NOTIFIER=y CONFIG_HAVE_PERF_EVENTS_NMI=y CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y CONFIG_MMU_GATHER_TABLE_FREE=y CONFIG_MMU_GATHER_RCU_TABLE_FREE=y CONFIG_MMU_GATHER_MERGE_VMAS=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y CONFIG_HAVE_CMPXCHG_LOCAL=y CONFIG_HAVE_CMPXCHG_DOUBLE=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y CONFIG_SECCOMP_CACHE_DEBUG=y CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_ARCH_SUPPORTS_LTO_CLANG=y CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y CONFIG_LTO_NONE=y CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOVE_PUD=y CONFIG_HAVE_MOVE_PMD=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_ISA_BUS_API=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y CONFIG_ARCH_USE_MEMREMAP_PROT=y CONFIG_LOCK_EVENT_COUNTS=y CONFIG_ARCH_HAS_MEM_ENCRYPT=y CONFIG_HAVE_STATIC_CALL=y CONFIG_HAVE_PREEMPT_DYNAMIC=y CONFIG_HAVE_PREEMPT_DYNAMIC_CALL=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SPLIT_ARG64=y CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y CONFIG_DYNAMIC_SIGFRAME=y # # GCOV-based kernel profiling # CONFIG_GCOV_KERNEL=y CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # CONFIG_GCOV_PROFILE_ALL is not set # end of GCOV-based kernel profiling CONFIG_HAVE_GCC_PLUGINS=y CONFIG_GCC_PLUGINS=y CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y # end of General architecture-dependent options CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULE_SIG_FORMAT=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODULE_UNLOAD_TAINT_TRACKING=y CONFIG_MODVERSIONS=y CONFIG_ASM_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_MODULE_SIG=y CONFIG_MODULE_SIG_FORCE=y CONFIG_MODULE_SIG_ALL=y CONFIG_MODULE_SIG_SHA1=y # CONFIG_MODULE_SIG_SHA224 is not set # CONFIG_MODULE_SIG_SHA256 is not set # CONFIG_MODULE_SIG_SHA384 is not set # CONFIG_MODULE_SIG_SHA512 is not set CONFIG_MODULE_SIG_HASH="sha1" CONFIG_MODULE_COMPRESS_NONE=y # CONFIG_MODULE_COMPRESS_GZIP is not set # CONFIG_MODULE_COMPRESS_XZ is not set # CONFIG_MODULE_COMPRESS_ZSTD is not set CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLOCK_LEGACY_AUTOLOAD=y CONFIG_BLK_RQ_ALLOC_TIME=y CONFIG_BLK_CGROUP_RWSTAT=y CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_ICQ=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y CONFIG_BLK_DEV_INTEGRITY_T10=y CONFIG_BLK_DEV_ZONED=y CONFIG_BLK_DEV_THROTTLING=y CONFIG_BLK_DEV_THROTTLING_LOW=y CONFIG_BLK_WBT=y CONFIG_BLK_WBT_MQ=y CONFIG_BLK_CGROUP_IOLATENCY=y CONFIG_BLK_CGROUP_FC_APPID=y CONFIG_BLK_CGROUP_IOCOST=y CONFIG_BLK_CGROUP_IOPRIO=y CONFIG_BLK_DEBUG_FS=y CONFIG_BLK_DEBUG_FS_ZONED=y CONFIG_BLK_SED_OPAL=y CONFIG_BLK_INLINE_ENCRYPTION=y CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y # # Partition Types # CONFIG_PARTITION_ADVANCED=y CONFIG_ACORN_PARTITION=y CONFIG_ACORN_PARTITION_CUMANA=y CONFIG_ACORN_PARTITION_EESOX=y CONFIG_ACORN_PARTITION_ICS=y CONFIG_ACORN_PARTITION_ADFS=y CONFIG_ACORN_PARTITION_POWERTEC=y CONFIG_ACORN_PARTITION_RISCIX=y CONFIG_AIX_PARTITION=y CONFIG_OSF_PARTITION=y CONFIG_AMIGA_PARTITION=y CONFIG_ATARI_PARTITION=y CONFIG_MAC_PARTITION=y CONFIG_MSDOS_PARTITION=y CONFIG_BSD_DISKLABEL=y CONFIG_MINIX_SUBPARTITION=y CONFIG_SOLARIS_X86_PARTITION=y CONFIG_UNIXWARE_DISKLABEL=y CONFIG_LDM_PARTITION=y CONFIG_LDM_DEBUG=y CONFIG_SGI_PARTITION=y CONFIG_ULTRIX_PARTITION=y CONFIG_SUN_PARTITION=y CONFIG_KARMA_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_SYSV68_PARTITION=y CONFIG_CMDLINE_PARTITION=y # end of Partition Types CONFIG_BLK_MQ_PCI=y CONFIG_BLK_MQ_VIRTIO=y CONFIG_BLK_MQ_RDMA=y CONFIG_BLK_PM=y CONFIG_BLOCK_HOLDER_DEPRECATED=y CONFIG_BLK_MQ_STACKING=y # # IO Schedulers # CONFIG_MQ_IOSCHED_DEADLINE=y CONFIG_MQ_IOSCHED_KYBER=y CONFIG_IOSCHED_BFQ=y CONFIG_BFQ_GROUP_IOSCHED=y CONFIG_BFQ_CGROUP_DEBUG=y # end of IO Schedulers CONFIG_PREEMPT_NOTIFIERS=y CONFIG_PADATA=y CONFIG_ASN1=y CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_RWSEM_SPIN_ON_OWNER=y CONFIG_LOCK_SPIN_ON_OWNER=y CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y CONFIG_QUEUED_SPINLOCKS=y CONFIG_ARCH_USE_QUEUED_RWLOCKS=y CONFIG_QUEUED_RWLOCKS=y CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y CONFIG_FREEZER=y # # Executable file formats # CONFIG_BINFMT_ELF=y CONFIG_BINFMT_ELF_KUNIT_TEST=y CONFIG_ELFCORE=y CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y CONFIG_BINFMT_SCRIPT=y CONFIG_BINFMT_MISC=y CONFIG_COREDUMP=y # end of Executable file formats # # Memory Management options # CONFIG_ZPOOL=y CONFIG_SWAP=y CONFIG_ZSWAP=y CONFIG_ZSWAP_DEFAULT_ON=y # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y # CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set # CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud" CONFIG_ZBUD=y CONFIG_Z3FOLD=y CONFIG_ZSMALLOC=y CONFIG_ZSMALLOC_STAT=y # # SLAB allocator options # # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set CONFIG_SLAB_MERGE_DEFAULT=y CONFIG_SLAB_FREELIST_RANDOM=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLUB_STATS=y CONFIG_SLUB_CPU_PARTIAL=y # end of SLAB allocator options CONFIG_SHUFFLE_PAGE_ALLOCATOR=y CONFIG_COMPAT_BRK=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_SPARSEMEM_STATIC=y CONFIG_HAVE_FAST_GUP=y CONFIG_MEMORY_ISOLATION=y CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MEMORY_BALLOON=y CONFIG_BALLOON_COMPACTION=y CONFIG_COMPACTION=y CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 CONFIG_PAGE_REPORTING=y CONFIG_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_BOUNCE=y CONFIG_MMU_NOTIFIER=y CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_MEMORY_FAILURE=y CONFIG_HWPOISON_INJECT=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set CONFIG_READ_ONLY_THP_FOR_FS=y CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_FRONTSWAP=y CONFIG_CMA=y CONFIG_CMA_DEBUG=y CONFIG_CMA_DEBUGFS=y CONFIG_CMA_SYSFS=y CONFIG_CMA_AREAS=7 CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_PAGE_IDLE_FLAG=y CONFIG_IDLE_PAGE_TRACKING=y CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y CONFIG_ARCH_HAS_ZONE_DMA_SET=y CONFIG_ZONE_DMA=y CONFIG_HMM_MIRROR=y CONFIG_VMAP_PFN=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_PERCPU_STATS=y CONFIG_GUP_TEST=y CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_MAPPING_DIRTY_HELPERS=y CONFIG_KMAP_LOCAL=y CONFIG_ANON_VMA_NAME=y CONFIG_USERFAULTFD=y CONFIG_LRU_GEN=y CONFIG_LRU_GEN_ENABLED=y CONFIG_LRU_GEN_STATS=y # # Data Access Monitoring # CONFIG_DAMON=y CONFIG_DAMON_KUNIT_TEST=y CONFIG_DAMON_VADDR=y CONFIG_DAMON_PADDR=y CONFIG_DAMON_VADDR_KUNIT_TEST=y CONFIG_DAMON_SYSFS=y CONFIG_DAMON_DBGFS=y CONFIG_DAMON_DBGFS_KUNIT_TEST=y CONFIG_DAMON_RECLAIM=y CONFIG_DAMON_LRU_SORT=y # end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y CONFIG_NET_INGRESS=y CONFIG_NET_EGRESS=y CONFIG_NET_REDIRECT=y CONFIG_SKB_EXTENSIONS=y # # Networking options # CONFIG_PACKET=y CONFIG_PACKET_DIAG=y CONFIG_UNIX=y CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y CONFIG_UNIX_DIAG=y CONFIG_TLS=y CONFIG_TLS_DEVICE=y CONFIG_TLS_TOE=y CONFIG_XFRM=y CONFIG_XFRM_OFFLOAD=y CONFIG_XFRM_ALGO=y CONFIG_XFRM_USER=y CONFIG_XFRM_INTERFACE=y CONFIG_XFRM_SUB_POLICY=y CONFIG_XFRM_MIGRATE=y CONFIG_XFRM_STATISTICS=y CONFIG_XFRM_AH=y CONFIG_XFRM_ESP=y CONFIG_XFRM_IPCOMP=y CONFIG_NET_KEY=y CONFIG_NET_KEY_MIGRATE=y CONFIG_XFRM_ESPINTCP=y CONFIG_SMC=y CONFIG_SMC_DIAG=y CONFIG_XDP_SOCKETS=y CONFIG_XDP_SOCKETS_DIAG=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y CONFIG_IP_FIB_TRIE_STATS=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_ROUTE_CLASSID=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=y CONFIG_NET_IPGRE_DEMUX=y CONFIG_NET_IP_TUNNEL=y CONFIG_NET_IPGRE=y CONFIG_NET_IPGRE_BROADCAST=y CONFIG_IP_MROUTE_COMMON=y CONFIG_IP_MROUTE=y CONFIG_IP_MROUTE_MULTIPLE_TABLES=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_SYN_COOKIES=y CONFIG_NET_IPVTI=y CONFIG_NET_UDP_TUNNEL=y CONFIG_NET_FOU=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_INET_AH=y CONFIG_INET_ESP=y CONFIG_INET_ESP_OFFLOAD=y CONFIG_INET_ESPINTCP=y CONFIG_INET_IPCOMP=y CONFIG_INET_XFRM_TUNNEL=y CONFIG_INET_TUNNEL=y CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y CONFIG_INET_UDP_DIAG=y CONFIG_INET_RAW_DIAG=y CONFIG_INET_DIAG_DESTROY=y CONFIG_TCP_CONG_ADVANCED=y CONFIG_TCP_CONG_BIC=y CONFIG_TCP_CONG_CUBIC=y CONFIG_TCP_CONG_WESTWOOD=y CONFIG_TCP_CONG_HTCP=y CONFIG_TCP_CONG_HSTCP=y CONFIG_TCP_CONG_HYBLA=y CONFIG_TCP_CONG_VEGAS=y CONFIG_TCP_CONG_NV=y CONFIG_TCP_CONG_SCALABLE=y CONFIG_TCP_CONG_LP=y CONFIG_TCP_CONG_VENO=y CONFIG_TCP_CONG_YEAH=y CONFIG_TCP_CONG_ILLINOIS=y CONFIG_TCP_CONG_DCTCP=y CONFIG_TCP_CONG_CDG=y CONFIG_TCP_CONG_BBR=y # CONFIG_DEFAULT_BIC is not set CONFIG_DEFAULT_CUBIC=y # CONFIG_DEFAULT_HTCP is not set # CONFIG_DEFAULT_HYBLA is not set # CONFIG_DEFAULT_VEGAS is not set # CONFIG_DEFAULT_VENO is not set # CONFIG_DEFAULT_WESTWOOD is not set # CONFIG_DEFAULT_DCTCP is not set # CONFIG_DEFAULT_CDG is not set # CONFIG_DEFAULT_BBR is not set # CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_TCP_MD5SIG=y CONFIG_IPV6=y CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTE_INFO=y CONFIG_IPV6_OPTIMISTIC_DAD=y CONFIG_INET6_AH=y CONFIG_INET6_ESP=y CONFIG_INET6_ESP_OFFLOAD=y CONFIG_INET6_ESPINTCP=y CONFIG_INET6_IPCOMP=y CONFIG_IPV6_MIP6=y CONFIG_IPV6_ILA=y CONFIG_INET6_XFRM_TUNNEL=y CONFIG_INET6_TUNNEL=y CONFIG_IPV6_VTI=y CONFIG_IPV6_SIT=y CONFIG_IPV6_SIT_6RD=y CONFIG_IPV6_NDISC_NODETYPE=y CONFIG_IPV6_TUNNEL=y CONFIG_IPV6_GRE=y CONFIG_IPV6_FOU=y CONFIG_IPV6_FOU_TUNNEL=y CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y CONFIG_IPV6_MROUTE=y CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y CONFIG_IPV6_PIMSM_V2=y CONFIG_IPV6_SEG6_LWTUNNEL=y CONFIG_IPV6_SEG6_HMAC=y CONFIG_IPV6_SEG6_BPF=y CONFIG_IPV6_RPL_LWTUNNEL=y CONFIG_IPV6_IOAM6_LWTUNNEL=y CONFIG_NETLABEL=y CONFIG_MPTCP=y CONFIG_INET_MPTCP_DIAG=y CONFIG_MPTCP_IPV6=y CONFIG_MPTCP_KUNIT_TEST=y CONFIG_NETWORK_SECMARK=y CONFIG_NET_PTP_CLASSIFY=y CONFIG_NETWORK_PHY_TIMESTAMPING=y CONFIG_NETFILTER=y CONFIG_NETFILTER_ADVANCED=y CONFIG_BRIDGE_NETFILTER=y # # Core Netfilter Configuration # CONFIG_NETFILTER_INGRESS=y CONFIG_NETFILTER_EGRESS=y CONFIG_NETFILTER_SKIP_EGRESS=y CONFIG_NETFILTER_NETLINK=y CONFIG_NETFILTER_FAMILY_BRIDGE=y CONFIG_NETFILTER_FAMILY_ARP=y CONFIG_NETFILTER_NETLINK_HOOK=y CONFIG_NETFILTER_NETLINK_ACCT=y CONFIG_NETFILTER_NETLINK_QUEUE=y CONFIG_NETFILTER_NETLINK_LOG=y CONFIG_NETFILTER_NETLINK_OSF=y CONFIG_NF_CONNTRACK=y CONFIG_NF_LOG_SYSLOG=y CONFIG_NETFILTER_CONNCOUNT=y CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_ZONES=y CONFIG_NF_CONNTRACK_PROCFS=y CONFIG_NF_CONNTRACK_EVENTS=y CONFIG_NF_CONNTRACK_TIMEOUT=y CONFIG_NF_CONNTRACK_TIMESTAMP=y CONFIG_NF_CONNTRACK_LABELS=y CONFIG_NF_CT_PROTO_DCCP=y CONFIG_NF_CT_PROTO_GRE=y CONFIG_NF_CT_PROTO_SCTP=y CONFIG_NF_CT_PROTO_UDPLITE=y CONFIG_NF_CONNTRACK_AMANDA=y CONFIG_NF_CONNTRACK_FTP=y CONFIG_NF_CONNTRACK_H323=y CONFIG_NF_CONNTRACK_IRC=y CONFIG_NF_CONNTRACK_BROADCAST=y CONFIG_NF_CONNTRACK_NETBIOS_NS=y CONFIG_NF_CONNTRACK_SNMP=y CONFIG_NF_CONNTRACK_PPTP=y CONFIG_NF_CONNTRACK_SANE=y CONFIG_NF_CONNTRACK_SIP=y CONFIG_NF_CONNTRACK_TFTP=y CONFIG_NF_CT_NETLINK=y CONFIG_NF_CT_NETLINK_TIMEOUT=y CONFIG_NF_CT_NETLINK_HELPER=y CONFIG_NETFILTER_NETLINK_GLUE_CT=y CONFIG_NF_NAT=y CONFIG_NF_NAT_AMANDA=y CONFIG_NF_NAT_FTP=y CONFIG_NF_NAT_IRC=y CONFIG_NF_NAT_SIP=y CONFIG_NF_NAT_TFTP=y CONFIG_NF_NAT_REDIRECT=y CONFIG_NF_NAT_MASQUERADE=y CONFIG_NETFILTER_SYNPROXY=y CONFIG_NF_TABLES=y CONFIG_NF_TABLES_INET=y CONFIG_NF_TABLES_NETDEV=y CONFIG_NFT_NUMGEN=y CONFIG_NFT_CT=y CONFIG_NFT_FLOW_OFFLOAD=y CONFIG_NFT_CONNLIMIT=y CONFIG_NFT_LOG=y CONFIG_NFT_LIMIT=y CONFIG_NFT_MASQ=y CONFIG_NFT_REDIR=y CONFIG_NFT_NAT=y CONFIG_NFT_TUNNEL=y # CONFIG_NFT_OBJREF is not set CONFIG_NFT_QUEUE=y CONFIG_NFT_QUOTA=y CONFIG_NFT_REJECT=y CONFIG_NFT_REJECT_INET=y CONFIG_NFT_COMPAT=y CONFIG_NFT_HASH=y CONFIG_NFT_FIB=y CONFIG_NFT_FIB_INET=y CONFIG_NFT_XFRM=y CONFIG_NFT_SOCKET=y CONFIG_NFT_OSF=y CONFIG_NFT_TPROXY=y CONFIG_NFT_SYNPROXY=y CONFIG_NF_DUP_NETDEV=y CONFIG_NFT_DUP_NETDEV=y CONFIG_NFT_FWD_NETDEV=y CONFIG_NFT_FIB_NETDEV=y CONFIG_NFT_REJECT_NETDEV=y CONFIG_NF_FLOW_TABLE_INET=y CONFIG_NF_FLOW_TABLE=y CONFIG_NF_FLOW_TABLE_PROCFS=y CONFIG_NETFILTER_XTABLES=y # # Xtables combined modules # CONFIG_NETFILTER_XT_MARK=y CONFIG_NETFILTER_XT_CONNMARK=y CONFIG_NETFILTER_XT_SET=y # # Xtables targets # CONFIG_NETFILTER_XT_TARGET_AUDIT=y CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y CONFIG_NETFILTER_XT_TARGET_CONNMARK=y CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y CONFIG_NETFILTER_XT_TARGET_CT=y CONFIG_NETFILTER_XT_TARGET_DSCP=y CONFIG_NETFILTER_XT_TARGET_HL=y CONFIG_NETFILTER_XT_TARGET_HMARK=y CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y CONFIG_NETFILTER_XT_TARGET_LED=y CONFIG_NETFILTER_XT_TARGET_LOG=y CONFIG_NETFILTER_XT_TARGET_MARK=y CONFIG_NETFILTER_XT_NAT=y CONFIG_NETFILTER_XT_TARGET_NETMAP=y CONFIG_NETFILTER_XT_TARGET_NFLOG=y CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y CONFIG_NETFILTER_XT_TARGET_NOTRACK=y CONFIG_NETFILTER_XT_TARGET_RATEEST=y CONFIG_NETFILTER_XT_TARGET_REDIRECT=y CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y CONFIG_NETFILTER_XT_TARGET_TEE=y CONFIG_NETFILTER_XT_TARGET_TPROXY=y CONFIG_NETFILTER_XT_TARGET_TRACE=y CONFIG_NETFILTER_XT_TARGET_SECMARK=y CONFIG_NETFILTER_XT_TARGET_TCPMSS=y CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y # # Xtables matches # CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y CONFIG_NETFILTER_XT_MATCH_BPF=y CONFIG_NETFILTER_XT_MATCH_CGROUP=y CONFIG_NETFILTER_XT_MATCH_CLUSTER=y CONFIG_NETFILTER_XT_MATCH_COMMENT=y CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y CONFIG_NETFILTER_XT_MATCH_CONNLABEL=y CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y CONFIG_NETFILTER_XT_MATCH_CONNMARK=y CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y CONFIG_NETFILTER_XT_MATCH_CPU=y CONFIG_NETFILTER_XT_MATCH_DCCP=y CONFIG_NETFILTER_XT_MATCH_DEVGROUP=y CONFIG_NETFILTER_XT_MATCH_DSCP=y CONFIG_NETFILTER_XT_MATCH_ECN=y CONFIG_NETFILTER_XT_MATCH_ESP=y CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y CONFIG_NETFILTER_XT_MATCH_HELPER=y CONFIG_NETFILTER_XT_MATCH_HL=y CONFIG_NETFILTER_XT_MATCH_IPCOMP=y CONFIG_NETFILTER_XT_MATCH_IPRANGE=y CONFIG_NETFILTER_XT_MATCH_IPVS=y CONFIG_NETFILTER_XT_MATCH_L2TP=y CONFIG_NETFILTER_XT_MATCH_LENGTH=y CONFIG_NETFILTER_XT_MATCH_LIMIT=y CONFIG_NETFILTER_XT_MATCH_MAC=y CONFIG_NETFILTER_XT_MATCH_MARK=y CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y CONFIG_NETFILTER_XT_MATCH_NFACCT=y CONFIG_NETFILTER_XT_MATCH_OSF=y CONFIG_NETFILTER_XT_MATCH_OWNER=y CONFIG_NETFILTER_XT_MATCH_POLICY=y CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y CONFIG_NETFILTER_XT_MATCH_QUOTA=y CONFIG_NETFILTER_XT_MATCH_RATEEST=y CONFIG_NETFILTER_XT_MATCH_REALM=y CONFIG_NETFILTER_XT_MATCH_RECENT=y CONFIG_NETFILTER_XT_MATCH_SCTP=y CONFIG_NETFILTER_XT_MATCH_SOCKET=y CONFIG_NETFILTER_XT_MATCH_STATE=y CONFIG_NETFILTER_XT_MATCH_STATISTIC=y CONFIG_NETFILTER_XT_MATCH_STRING=y CONFIG_NETFILTER_XT_MATCH_TCPMSS=y CONFIG_NETFILTER_XT_MATCH_TIME=y CONFIG_NETFILTER_XT_MATCH_U32=y # end of Core Netfilter Configuration CONFIG_IP_SET=y CONFIG_IP_SET_MAX=256 CONFIG_IP_SET_BITMAP_IP=y CONFIG_IP_SET_BITMAP_IPMAC=y CONFIG_IP_SET_BITMAP_PORT=y CONFIG_IP_SET_HASH_IP=y CONFIG_IP_SET_HASH_IPMARK=y CONFIG_IP_SET_HASH_IPPORT=y CONFIG_IP_SET_HASH_IPPORTIP=y CONFIG_IP_SET_HASH_IPPORTNET=y CONFIG_IP_SET_HASH_IPMAC=y CONFIG_IP_SET_HASH_MAC=y CONFIG_IP_SET_HASH_NETPORTNET=y CONFIG_IP_SET_HASH_NET=y CONFIG_IP_SET_HASH_NETNET=y CONFIG_IP_SET_HASH_NETPORT=y CONFIG_IP_SET_HASH_NETIFACE=y CONFIG_IP_SET_LIST_SET=y CONFIG_IP_VS=y CONFIG_IP_VS_IPV6=y CONFIG_IP_VS_DEBUG=y CONFIG_IP_VS_TAB_BITS=12 # # IPVS transport protocol load balancing support # CONFIG_IP_VS_PROTO_TCP=y CONFIG_IP_VS_PROTO_UDP=y CONFIG_IP_VS_PROTO_AH_ESP=y CONFIG_IP_VS_PROTO_ESP=y CONFIG_IP_VS_PROTO_AH=y CONFIG_IP_VS_PROTO_SCTP=y # # IPVS scheduler # CONFIG_IP_VS_RR=y CONFIG_IP_VS_WRR=y CONFIG_IP_VS_LC=y CONFIG_IP_VS_WLC=y CONFIG_IP_VS_FO=y CONFIG_IP_VS_OVF=y CONFIG_IP_VS_LBLC=y CONFIG_IP_VS_LBLCR=y CONFIG_IP_VS_DH=y CONFIG_IP_VS_SH=y CONFIG_IP_VS_MH=y CONFIG_IP_VS_SED=y CONFIG_IP_VS_NQ=y CONFIG_IP_VS_TWOS=y # # IPVS SH scheduler # CONFIG_IP_VS_SH_TAB_BITS=8 # # IPVS MH scheduler # CONFIG_IP_VS_MH_TAB_INDEX=12 # # IPVS application helper # CONFIG_IP_VS_FTP=y CONFIG_IP_VS_NFCT=y CONFIG_IP_VS_PE_SIP=y # # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=y CONFIG_NF_SOCKET_IPV4=y CONFIG_NF_TPROXY_IPV4=y CONFIG_NF_TABLES_IPV4=y CONFIG_NFT_REJECT_IPV4=y CONFIG_NFT_DUP_IPV4=y CONFIG_NFT_FIB_IPV4=y CONFIG_NF_TABLES_ARP=y CONFIG_NF_DUP_IPV4=y CONFIG_NF_LOG_ARP=y CONFIG_NF_LOG_IPV4=y CONFIG_NF_REJECT_IPV4=y CONFIG_NF_NAT_SNMP_BASIC=y CONFIG_NF_NAT_PPTP=y CONFIG_NF_NAT_H323=y CONFIG_IP_NF_IPTABLES=y CONFIG_IP_NF_MATCH_AH=y CONFIG_IP_NF_MATCH_ECN=y CONFIG_IP_NF_MATCH_RPFILTER=y CONFIG_IP_NF_MATCH_TTL=y CONFIG_IP_NF_FILTER=y CONFIG_IP_NF_TARGET_REJECT=y CONFIG_IP_NF_TARGET_SYNPROXY=y CONFIG_IP_NF_NAT=y CONFIG_IP_NF_TARGET_MASQUERADE=y CONFIG_IP_NF_TARGET_NETMAP=y CONFIG_IP_NF_TARGET_REDIRECT=y CONFIG_IP_NF_MANGLE=y CONFIG_IP_NF_TARGET_CLUSTERIP=y CONFIG_IP_NF_TARGET_ECN=y CONFIG_IP_NF_TARGET_TTL=y CONFIG_IP_NF_RAW=y CONFIG_IP_NF_SECURITY=y CONFIG_IP_NF_ARPTABLES=y CONFIG_IP_NF_ARPFILTER=y CONFIG_IP_NF_ARP_MANGLE=y # end of IP: Netfilter Configuration # # IPv6: Netfilter Configuration # CONFIG_NF_SOCKET_IPV6=y CONFIG_NF_TPROXY_IPV6=y CONFIG_NF_TABLES_IPV6=y CONFIG_NFT_REJECT_IPV6=y CONFIG_NFT_DUP_IPV6=y CONFIG_NFT_FIB_IPV6=y CONFIG_NF_DUP_IPV6=y CONFIG_NF_REJECT_IPV6=y CONFIG_NF_LOG_IPV6=y CONFIG_IP6_NF_IPTABLES=y CONFIG_IP6_NF_MATCH_AH=y CONFIG_IP6_NF_MATCH_EUI64=y CONFIG_IP6_NF_MATCH_FRAG=y CONFIG_IP6_NF_MATCH_OPTS=y CONFIG_IP6_NF_MATCH_HL=y CONFIG_IP6_NF_MATCH_IPV6HEADER=y CONFIG_IP6_NF_MATCH_MH=y CONFIG_IP6_NF_MATCH_RPFILTER=y CONFIG_IP6_NF_MATCH_RT=y CONFIG_IP6_NF_MATCH_SRH=y CONFIG_IP6_NF_TARGET_HL=y CONFIG_IP6_NF_FILTER=y CONFIG_IP6_NF_TARGET_REJECT=y CONFIG_IP6_NF_TARGET_SYNPROXY=y CONFIG_IP6_NF_MANGLE=y CONFIG_IP6_NF_RAW=y CONFIG_IP6_NF_SECURITY=y CONFIG_IP6_NF_NAT=y CONFIG_IP6_NF_TARGET_MASQUERADE=y CONFIG_IP6_NF_TARGET_NPT=y # end of IPv6: Netfilter Configuration CONFIG_NF_DEFRAG_IPV6=y CONFIG_NF_TABLES_BRIDGE=y CONFIG_NFT_BRIDGE_META=y CONFIG_NFT_BRIDGE_REJECT=y CONFIG_NF_CONNTRACK_BRIDGE=y CONFIG_BRIDGE_NF_EBTABLES=y CONFIG_BRIDGE_EBT_BROUTE=y CONFIG_BRIDGE_EBT_T_FILTER=y CONFIG_BRIDGE_EBT_T_NAT=y CONFIG_BRIDGE_EBT_802_3=y CONFIG_BRIDGE_EBT_AMONG=y CONFIG_BRIDGE_EBT_ARP=y CONFIG_BRIDGE_EBT_IP=y CONFIG_BRIDGE_EBT_IP6=y CONFIG_BRIDGE_EBT_LIMIT=y CONFIG_BRIDGE_EBT_MARK=y CONFIG_BRIDGE_EBT_PKTTYPE=y CONFIG_BRIDGE_EBT_STP=y CONFIG_BRIDGE_EBT_VLAN=y CONFIG_BRIDGE_EBT_ARPREPLY=y CONFIG_BRIDGE_EBT_DNAT=y CONFIG_BRIDGE_EBT_MARK_T=y CONFIG_BRIDGE_EBT_REDIRECT=y CONFIG_BRIDGE_EBT_SNAT=y CONFIG_BRIDGE_EBT_LOG=y CONFIG_BRIDGE_EBT_NFLOG=y CONFIG_BPFILTER=y CONFIG_BPFILTER_UMH=y CONFIG_IP_DCCP=y CONFIG_INET_DCCP_DIAG=y # # DCCP CCIDs Configuration # CONFIG_IP_DCCP_CCID2_DEBUG=y CONFIG_IP_DCCP_CCID3=y CONFIG_IP_DCCP_CCID3_DEBUG=y CONFIG_IP_DCCP_TFRC_LIB=y CONFIG_IP_DCCP_TFRC_DEBUG=y # end of DCCP CCIDs Configuration # # DCCP Kernel Hacking # CONFIG_IP_DCCP_DEBUG=y # end of DCCP Kernel Hacking CONFIG_IP_SCTP=y CONFIG_SCTP_DBG_OBJCNT=y CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set CONFIG_SCTP_COOKIE_HMAC_MD5=y CONFIG_SCTP_COOKIE_HMAC_SHA1=y CONFIG_INET_SCTP_DIAG=y CONFIG_RDS=y CONFIG_RDS_RDMA=y CONFIG_RDS_TCP=y CONFIG_RDS_DEBUG=y CONFIG_TIPC=y CONFIG_TIPC_MEDIA_IB=y CONFIG_TIPC_MEDIA_UDP=y CONFIG_TIPC_CRYPTO=y CONFIG_TIPC_DIAG=y CONFIG_ATM=y CONFIG_ATM_CLIP=y CONFIG_ATM_CLIP_NO_ICMP=y CONFIG_ATM_LANE=y CONFIG_ATM_MPOA=y CONFIG_ATM_BR2684=y CONFIG_ATM_BR2684_IPFILTER=y CONFIG_L2TP=y CONFIG_L2TP_DEBUGFS=y CONFIG_L2TP_V3=y CONFIG_L2TP_IP=y CONFIG_L2TP_ETH=y CONFIG_STP=y CONFIG_GARP=y CONFIG_MRP=y CONFIG_BRIDGE=y CONFIG_BRIDGE_IGMP_SNOOPING=y CONFIG_BRIDGE_VLAN_FILTERING=y CONFIG_BRIDGE_MRP=y CONFIG_BRIDGE_CFM=y CONFIG_NET_DSA=y CONFIG_NET_DSA_TAG_AR9331=y CONFIG_NET_DSA_TAG_BRCM_COMMON=y CONFIG_NET_DSA_TAG_BRCM=y CONFIG_NET_DSA_TAG_BRCM_LEGACY=y CONFIG_NET_DSA_TAG_BRCM_PREPEND=y CONFIG_NET_DSA_TAG_HELLCREEK=y CONFIG_NET_DSA_TAG_GSWIP=y CONFIG_NET_DSA_TAG_DSA_COMMON=y CONFIG_NET_DSA_TAG_DSA=y CONFIG_NET_DSA_TAG_EDSA=y CONFIG_NET_DSA_TAG_MTK=y CONFIG_NET_DSA_TAG_KSZ=y CONFIG_NET_DSA_TAG_OCELOT=y CONFIG_NET_DSA_TAG_OCELOT_8021Q=y CONFIG_NET_DSA_TAG_QCA=y CONFIG_NET_DSA_TAG_RTL4_A=y CONFIG_NET_DSA_TAG_RTL8_4=y CONFIG_NET_DSA_TAG_RZN1_A5PSW=y CONFIG_NET_DSA_TAG_LAN9303=y CONFIG_NET_DSA_TAG_SJA1105=y CONFIG_NET_DSA_TAG_TRAILER=y CONFIG_NET_DSA_TAG_XRS700X=y CONFIG_VLAN_8021Q=y CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y CONFIG_LLC=y CONFIG_LLC2=y CONFIG_ATALK=y CONFIG_DEV_APPLETALK=y CONFIG_COPS=y CONFIG_COPS_DAYNA=y CONFIG_COPS_TANGENT=y CONFIG_IPDDP=y CONFIG_IPDDP_ENCAP=y CONFIG_X25=y CONFIG_LAPB=y CONFIG_PHONET=y CONFIG_6LOWPAN=y CONFIG_6LOWPAN_DEBUGFS=y CONFIG_6LOWPAN_NHC=y CONFIG_6LOWPAN_NHC_DEST=y CONFIG_6LOWPAN_NHC_FRAGMENT=y CONFIG_6LOWPAN_NHC_HOP=y CONFIG_6LOWPAN_NHC_IPV6=y CONFIG_6LOWPAN_NHC_MOBILITY=y CONFIG_6LOWPAN_NHC_ROUTING=y CONFIG_6LOWPAN_NHC_UDP=y CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=y CONFIG_6LOWPAN_GHC_UDP=y CONFIG_6LOWPAN_GHC_ICMPV6=y CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=y CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=y CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=y CONFIG_IEEE802154=y CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y CONFIG_IEEE802154_SOCKET=y CONFIG_IEEE802154_6LOWPAN=y CONFIG_MAC802154=y CONFIG_NET_SCHED=y # # Queueing/Scheduling # CONFIG_NET_SCH_CBQ=y CONFIG_NET_SCH_HTB=y CONFIG_NET_SCH_HFSC=y CONFIG_NET_SCH_ATM=y CONFIG_NET_SCH_PRIO=y CONFIG_NET_SCH_MULTIQ=y CONFIG_NET_SCH_RED=y CONFIG_NET_SCH_SFB=y CONFIG_NET_SCH_SFQ=y CONFIG_NET_SCH_TEQL=y CONFIG_NET_SCH_TBF=y CONFIG_NET_SCH_CBS=y CONFIG_NET_SCH_ETF=y CONFIG_NET_SCH_TAPRIO=y CONFIG_NET_SCH_GRED=y CONFIG_NET_SCH_DSMARK=y CONFIG_NET_SCH_NETEM=y CONFIG_NET_SCH_DRR=y CONFIG_NET_SCH_MQPRIO=y CONFIG_NET_SCH_SKBPRIO=y CONFIG_NET_SCH_CHOKE=y CONFIG_NET_SCH_QFQ=y CONFIG_NET_SCH_CODEL=y CONFIG_NET_SCH_FQ_CODEL=y CONFIG_NET_SCH_CAKE=y CONFIG_NET_SCH_FQ=y CONFIG_NET_SCH_HHF=y CONFIG_NET_SCH_PIE=y CONFIG_NET_SCH_FQ_PIE=y CONFIG_NET_SCH_INGRESS=y CONFIG_NET_SCH_PLUG=y CONFIG_NET_SCH_ETS=y CONFIG_NET_SCH_DEFAULT=y # CONFIG_DEFAULT_FQ is not set # CONFIG_DEFAULT_CODEL is not set # CONFIG_DEFAULT_FQ_CODEL is not set # CONFIG_DEFAULT_FQ_PIE is not set # CONFIG_DEFAULT_SFQ is not set CONFIG_DEFAULT_PFIFO_FAST=y CONFIG_DEFAULT_NET_SCH="pfifo_fast" # # Classification # CONFIG_NET_CLS=y CONFIG_NET_CLS_BASIC=y CONFIG_NET_CLS_TCINDEX=y CONFIG_NET_CLS_ROUTE4=y CONFIG_NET_CLS_FW=y CONFIG_NET_CLS_U32=y CONFIG_CLS_U32_PERF=y CONFIG_CLS_U32_MARK=y CONFIG_NET_CLS_RSVP=y CONFIG_NET_CLS_RSVP6=y CONFIG_NET_CLS_FLOW=y CONFIG_NET_CLS_CGROUP=y CONFIG_NET_CLS_BPF=y CONFIG_NET_CLS_FLOWER=y CONFIG_NET_CLS_MATCHALL=y CONFIG_NET_EMATCH=y CONFIG_NET_EMATCH_STACK=32 CONFIG_NET_EMATCH_CMP=y CONFIG_NET_EMATCH_NBYTE=y CONFIG_NET_EMATCH_U32=y CONFIG_NET_EMATCH_META=y CONFIG_NET_EMATCH_TEXT=y CONFIG_NET_EMATCH_CANID=y CONFIG_NET_EMATCH_IPSET=y CONFIG_NET_EMATCH_IPT=y CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=y CONFIG_NET_ACT_GACT=y CONFIG_GACT_PROB=y CONFIG_NET_ACT_MIRRED=y CONFIG_NET_ACT_SAMPLE=y CONFIG_NET_ACT_IPT=y CONFIG_NET_ACT_NAT=y CONFIG_NET_ACT_PEDIT=y CONFIG_NET_ACT_SIMP=y CONFIG_NET_ACT_SKBEDIT=y CONFIG_NET_ACT_CSUM=y CONFIG_NET_ACT_MPLS=y CONFIG_NET_ACT_VLAN=y CONFIG_NET_ACT_BPF=y CONFIG_NET_ACT_CONNMARK=y CONFIG_NET_ACT_CTINFO=y CONFIG_NET_ACT_SKBMOD=y CONFIG_NET_ACT_IFE=y CONFIG_NET_ACT_TUNNEL_KEY=y CONFIG_NET_ACT_CT=y CONFIG_NET_ACT_GATE=y CONFIG_NET_IFE_SKBMARK=y CONFIG_NET_IFE_SKBPRIO=y CONFIG_NET_IFE_SKBTCINDEX=y CONFIG_NET_TC_SKB_EXT=y CONFIG_NET_SCH_FIFO=y CONFIG_DCB=y CONFIG_DNS_RESOLVER=y CONFIG_BATMAN_ADV=y CONFIG_BATMAN_ADV_BATMAN_V=y CONFIG_BATMAN_ADV_BLA=y CONFIG_BATMAN_ADV_DAT=y CONFIG_BATMAN_ADV_NC=y CONFIG_BATMAN_ADV_MCAST=y CONFIG_BATMAN_ADV_DEBUG=y CONFIG_BATMAN_ADV_TRACING=y CONFIG_OPENVSWITCH=y CONFIG_OPENVSWITCH_GRE=y CONFIG_OPENVSWITCH_VXLAN=y CONFIG_OPENVSWITCH_GENEVE=y CONFIG_VSOCKETS=y CONFIG_VSOCKETS_DIAG=y CONFIG_VSOCKETS_LOOPBACK=y CONFIG_VMWARE_VMCI_VSOCKETS=y CONFIG_VIRTIO_VSOCKETS=y CONFIG_VIRTIO_VSOCKETS_COMMON=y CONFIG_HYPERV_VSOCKETS=y CONFIG_NETLINK_DIAG=y CONFIG_MPLS=y CONFIG_NET_MPLS_GSO=y CONFIG_MPLS_ROUTING=y CONFIG_MPLS_IPTUNNEL=y CONFIG_NET_NSH=y CONFIG_HSR=y CONFIG_NET_SWITCHDEV=y CONFIG_NET_L3_MASTER_DEV=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y CONFIG_QRTR_TUN=y CONFIG_QRTR_MHI=y CONFIG_NET_NCSI=y CONFIG_NCSI_OEM_CMD_GET_MAC=y CONFIG_NCSI_OEM_CMD_KEEP_PHY=y CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y CONFIG_CGROUP_NET_PRIO=y CONFIG_CGROUP_NET_CLASSID=y CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y CONFIG_BPF_STREAM_PARSER=y CONFIG_NET_FLOW_LIMIT=y # # Network testing # CONFIG_NET_PKTGEN=y CONFIG_NET_DROP_MONITOR=y # end of Network testing # end of Networking options CONFIG_HAMRADIO=y # # Packet Radio protocols # CONFIG_AX25=y CONFIG_AX25_DAMA_SLAVE=y CONFIG_NETROM=y CONFIG_ROSE=y # # AX.25 network device drivers # CONFIG_MKISS=y CONFIG_6PACK=y CONFIG_BPQETHER=y CONFIG_SCC=y CONFIG_SCC_DELAY=y CONFIG_SCC_TRXECHO=y CONFIG_BAYCOM_SER_FDX=y CONFIG_BAYCOM_SER_HDX=y CONFIG_BAYCOM_PAR=y CONFIG_BAYCOM_EPP=y CONFIG_YAM=y # end of AX.25 network device drivers CONFIG_CAN=y CONFIG_CAN_RAW=y CONFIG_CAN_BCM=y CONFIG_CAN_GW=y CONFIG_CAN_J1939=y CONFIG_CAN_ISOTP=y CONFIG_BT=y CONFIG_BT_BREDR=y CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=y CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_CMTP=y CONFIG_BT_HIDP=y CONFIG_BT_HS=y CONFIG_BT_LE=y CONFIG_BT_6LOWPAN=y CONFIG_BT_LEDS=y CONFIG_BT_MSFTEXT=y CONFIG_BT_AOSPEXT=y CONFIG_BT_DEBUGFS=y CONFIG_BT_SELFTEST=y CONFIG_BT_SELFTEST_ECDH=y CONFIG_BT_SELFTEST_SMP=y # # Bluetooth device drivers # CONFIG_BT_INTEL=y CONFIG_BT_BCM=y CONFIG_BT_RTL=y CONFIG_BT_QCA=y CONFIG_BT_MTK=y CONFIG_BT_HCIBTUSB=y CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y CONFIG_BT_HCIBTUSB_BCM=y CONFIG_BT_HCIBTUSB_MTK=y CONFIG_BT_HCIBTUSB_RTL=y CONFIG_BT_HCIBTSDIO=y CONFIG_BT_HCIUART=y CONFIG_BT_HCIUART_SERDEV=y CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_NOKIA=y CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_ATH3K=y CONFIG_BT_HCIUART_LL=y CONFIG_BT_HCIUART_3WIRE=y CONFIG_BT_HCIUART_INTEL=y CONFIG_BT_HCIUART_BCM=y CONFIG_BT_HCIUART_RTL=y CONFIG_BT_HCIUART_QCA=y CONFIG_BT_HCIUART_AG6XX=y CONFIG_BT_HCIUART_MRVL=y CONFIG_BT_HCIBCM203X=y CONFIG_BT_HCIBPA10X=y CONFIG_BT_HCIBFUSB=y CONFIG_BT_HCIDTL1=y CONFIG_BT_HCIBT3C=y CONFIG_BT_HCIBLUECARD=y CONFIG_BT_HCIVHCI=y CONFIG_BT_MRVL=y CONFIG_BT_MRVL_SDIO=y CONFIG_BT_ATH3K=y CONFIG_BT_MTKSDIO=y CONFIG_BT_MTKUART=y CONFIG_BT_HCIRSI=y CONFIG_BT_VIRTIO=y # end of Bluetooth device drivers CONFIG_AF_RXRPC=y CONFIG_AF_RXRPC_IPV6=y CONFIG_AF_RXRPC_INJECT_LOSS=y CONFIG_AF_RXRPC_DEBUG=y CONFIG_RXKAD=y CONFIG_AF_KCM=y CONFIG_STREAM_PARSER=y CONFIG_MCTP=y CONFIG_MCTP_TEST=y CONFIG_MCTP_FLOWS=y CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y CONFIG_WEXT_CORE=y CONFIG_WEXT_PROC=y CONFIG_WEXT_SPY=y CONFIG_WEXT_PRIV=y CONFIG_CFG80211=y CONFIG_NL80211_TESTMODE=y CONFIG_CFG80211_DEVELOPER_WARNINGS=y CONFIG_CFG80211_CERTIFICATION_ONUS=y CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y CONFIG_CFG80211_EXTRA_REGDB_KEYDIR="" CONFIG_CFG80211_REG_CELLULAR_HINTS=y CONFIG_CFG80211_REG_RELAX_NO_IR=y CONFIG_CFG80211_DEFAULT_PS=y CONFIG_CFG80211_DEBUGFS=y CONFIG_CFG80211_CRDA_SUPPORT=y CONFIG_CFG80211_WEXT=y CONFIG_CFG80211_WEXT_EXPORT=y CONFIG_LIB80211=y CONFIG_LIB80211_CRYPT_WEP=y CONFIG_LIB80211_CRYPT_CCMP=y CONFIG_LIB80211_CRYPT_TKIP=y CONFIG_LIB80211_DEBUG=y CONFIG_MAC80211=y CONFIG_MAC80211_HAS_RC=y CONFIG_MAC80211_RC_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" CONFIG_MAC80211_MESH=y CONFIG_MAC80211_LEDS=y CONFIG_MAC80211_DEBUGFS=y CONFIG_MAC80211_MESSAGE_TRACING=y CONFIG_MAC80211_DEBUG_MENU=y CONFIG_MAC80211_NOINLINE=y CONFIG_MAC80211_VERBOSE_DEBUG=y CONFIG_MAC80211_MLME_DEBUG=y CONFIG_MAC80211_STA_DEBUG=y CONFIG_MAC80211_HT_DEBUG=y CONFIG_MAC80211_OCB_DEBUG=y CONFIG_MAC80211_IBSS_DEBUG=y CONFIG_MAC80211_PS_DEBUG=y CONFIG_MAC80211_MPL_DEBUG=y CONFIG_MAC80211_MPATH_DEBUG=y CONFIG_MAC80211_MHWMP_DEBUG=y CONFIG_MAC80211_MESH_SYNC_DEBUG=y CONFIG_MAC80211_MESH_CSA_DEBUG=y CONFIG_MAC80211_MESH_PS_DEBUG=y CONFIG_MAC80211_TDLS_DEBUG=y CONFIG_MAC80211_DEBUG_COUNTERS=y CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 CONFIG_RFKILL=y CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y CONFIG_RFKILL_GPIO=y CONFIG_NET_9P=y CONFIG_NET_9P_FD=y CONFIG_NET_9P_VIRTIO=y CONFIG_NET_9P_RDMA=y CONFIG_NET_9P_DEBUG=y CONFIG_CAIF=y CONFIG_CAIF_DEBUG=y CONFIG_CAIF_NETDEV=y CONFIG_CAIF_USB=y CONFIG_CEPH_LIB=y CONFIG_CEPH_LIB_PRETTYDEBUG=y CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y CONFIG_NFC=y CONFIG_NFC_DIGITAL=y CONFIG_NFC_NCI=y CONFIG_NFC_NCI_SPI=y CONFIG_NFC_NCI_UART=y CONFIG_NFC_HCI=y CONFIG_NFC_SHDLC=y # # Near Field Communication (NFC) devices # CONFIG_NFC_TRF7970A=y CONFIG_NFC_MEI_PHY=y CONFIG_NFC_SIM=y CONFIG_NFC_PORT100=y CONFIG_NFC_VIRTUAL_NCI=y CONFIG_NFC_FDP=y CONFIG_NFC_FDP_I2C=y CONFIG_NFC_PN544=y CONFIG_NFC_PN544_I2C=y CONFIG_NFC_PN544_MEI=y CONFIG_NFC_PN533=y CONFIG_NFC_PN533_USB=y CONFIG_NFC_PN533_I2C=y CONFIG_NFC_PN532_UART=y CONFIG_NFC_MICROREAD=y CONFIG_NFC_MICROREAD_I2C=y CONFIG_NFC_MICROREAD_MEI=y CONFIG_NFC_MRVL=y CONFIG_NFC_MRVL_USB=y CONFIG_NFC_MRVL_UART=y CONFIG_NFC_MRVL_I2C=y CONFIG_NFC_MRVL_SPI=y CONFIG_NFC_ST21NFCA=y CONFIG_NFC_ST21NFCA_I2C=y CONFIG_NFC_ST_NCI=y CONFIG_NFC_ST_NCI_I2C=y CONFIG_NFC_ST_NCI_SPI=y CONFIG_NFC_NXP_NCI=y CONFIG_NFC_NXP_NCI_I2C=y CONFIG_NFC_S3FWRN5=y CONFIG_NFC_S3FWRN5_I2C=y CONFIG_NFC_S3FWRN82_UART=y CONFIG_NFC_ST95HF=y # end of Near Field Communication (NFC) devices CONFIG_PSAMPLE=y CONFIG_NET_IFE=y CONFIG_LWTUNNEL=y CONFIG_LWTUNNEL_BPF=y CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y CONFIG_SOCK_VALIDATE_XMIT=y CONFIG_NET_SELFTESTS=y CONFIG_NET_SOCK_MSG=y CONFIG_NET_DEVLINK=y CONFIG_PAGE_POOL=y CONFIG_PAGE_POOL_STATS=y CONFIG_FAILOVER=y CONFIG_ETHTOOL_NETLINK=y CONFIG_NETDEV_ADDR_LIST_TEST=y # # Device Drivers # CONFIG_HAVE_EISA=y CONFIG_EISA=y CONFIG_EISA_VLB_PRIMING=y CONFIG_EISA_PCI_EISA=y CONFIG_EISA_VIRTUAL_ROOT=y CONFIG_EISA_NAMES=y CONFIG_HAVE_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCIEPORTBUS=y CONFIG_HOTPLUG_PCI_PCIE=y CONFIG_PCIEAER=y CONFIG_PCIEAER_INJECT=y CONFIG_PCIE_ECRC=y CONFIG_PCIEASPM=y CONFIG_PCIEASPM_DEFAULT=y # CONFIG_PCIEASPM_POWERSAVE is not set # CONFIG_PCIEASPM_POWER_SUPERSAVE is not set # CONFIG_PCIEASPM_PERFORMANCE is not set CONFIG_PCIE_PME=y CONFIG_PCIE_DPC=y CONFIG_PCIE_PTM=y CONFIG_PCIE_EDR=y CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCI_QUIRKS=y CONFIG_PCI_DEBUG=y CONFIG_PCI_REALLOC_ENABLE_AUTO=y CONFIG_PCI_STUB=y CONFIG_PCI_PF_STUB=y CONFIG_PCI_ATS=y CONFIG_PCI_DOE=y CONFIG_PCI_ECAM=y CONFIG_PCI_LOCKLESS_CONFIG=y CONFIG_PCI_IOV=y CONFIG_PCI_PRI=y CONFIG_PCI_PASID=y CONFIG_PCI_LABEL=y # CONFIG_PCIE_BUS_TUNE_OFF is not set CONFIG_PCIE_BUS_DEFAULT=y # CONFIG_PCIE_BUS_SAFE is not set # CONFIG_PCIE_BUS_PERFORMANCE is not set # CONFIG_PCIE_BUS_PEER2PEER is not set CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 CONFIG_HOTPLUG_PCI=y CONFIG_HOTPLUG_PCI_COMPAQ=y CONFIG_HOTPLUG_PCI_COMPAQ_NVRAM=y CONFIG_HOTPLUG_PCI_IBM=y CONFIG_HOTPLUG_PCI_ACPI=y CONFIG_HOTPLUG_PCI_ACPI_IBM=y CONFIG_HOTPLUG_PCI_CPCI=y CONFIG_HOTPLUG_PCI_CPCI_ZT5550=y CONFIG_HOTPLUG_PCI_CPCI_GENERIC=y CONFIG_HOTPLUG_PCI_SHPC=y # # PCI controller drivers # CONFIG_PCI_FTPCI100=y CONFIG_PCI_HOST_COMMON=y CONFIG_PCI_HOST_GENERIC=y CONFIG_PCIE_XILINX=y CONFIG_PCIE_MICROCHIP_HOST=y # # DesignWare PCI Core Support # CONFIG_PCIE_DW=y CONFIG_PCIE_DW_HOST=y CONFIG_PCIE_DW_EP=y CONFIG_PCIE_DW_PLAT=y CONFIG_PCIE_DW_PLAT_HOST=y CONFIG_PCIE_DW_PLAT_EP=y CONFIG_PCIE_INTEL_GW=y CONFIG_PCI_MESON=y # end of DesignWare PCI Core Support # # Mobiveil PCIe Core Support # # end of Mobiveil PCIe Core Support # # Cadence PCIe controllers support # CONFIG_PCIE_CADENCE=y CONFIG_PCIE_CADENCE_HOST=y CONFIG_PCIE_CADENCE_EP=y CONFIG_PCIE_CADENCE_PLAT=y CONFIG_PCIE_CADENCE_PLAT_HOST=y CONFIG_PCIE_CADENCE_PLAT_EP=y CONFIG_PCI_J721E=y CONFIG_PCI_J721E_HOST=y CONFIG_PCI_J721E_EP=y # end of Cadence PCIe controllers support # end of PCI controller drivers # # PCI Endpoint # CONFIG_PCI_ENDPOINT=y CONFIG_PCI_ENDPOINT_CONFIGFS=y CONFIG_PCI_EPF_TEST=y CONFIG_PCI_EPF_NTB=y CONFIG_PCI_EPF_VNTB=y # end of PCI Endpoint # # PCI switch controller drivers # CONFIG_PCI_SW_SWITCHTEC=y # end of PCI switch controller drivers CONFIG_CXL_BUS=y CONFIG_CXL_PCI=y CONFIG_CXL_MEM_RAW_COMMANDS=y CONFIG_CXL_ACPI=y CONFIG_CXL_MEM=y CONFIG_CXL_PORT=y CONFIG_CXL_SUSPEND=y CONFIG_PCCARD=y CONFIG_PCMCIA=y CONFIG_PCMCIA_LOAD_CIS=y CONFIG_CARDBUS=y # # PC-card bridges # CONFIG_YENTA=y CONFIG_YENTA_O2=y CONFIG_YENTA_RICOH=y CONFIG_YENTA_TI=y CONFIG_YENTA_ENE_TUNE=y CONFIG_YENTA_TOSHIBA=y CONFIG_PD6729=y CONFIG_I82092=y CONFIG_I82365=y CONFIG_TCIC=y CONFIG_PCMCIA_PROBE=y CONFIG_PCCARD_NONSTATIC=y CONFIG_RAPIDIO=y CONFIG_RAPIDIO_TSI721=y CONFIG_RAPIDIO_DISC_TIMEOUT=30 CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y CONFIG_RAPIDIO_DMA_ENGINE=y CONFIG_RAPIDIO_DEBUG=y CONFIG_RAPIDIO_ENUM_BASIC=y CONFIG_RAPIDIO_CHMAN=y CONFIG_RAPIDIO_MPORT_CDEV=y # # RapidIO Switch drivers # CONFIG_RAPIDIO_CPS_XX=y CONFIG_RAPIDIO_CPS_GEN2=y CONFIG_RAPIDIO_RXS_GEN3=y # end of RapidIO Switch drivers # # Generic Driver Options # CONFIG_AUXILIARY_BUS=y CONFIG_UEVENT_HELPER=y CONFIG_UEVENT_HELPER_PATH="" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # # Firmware loader # CONFIG_FW_LOADER=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_FW_LOADER_SYSFS=y CONFIG_EXTRA_FIRMWARE="" CONFIG_FW_LOADER_USER_HELPER=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_FW_LOADER_COMPRESS=y CONFIG_FW_LOADER_COMPRESS_XZ=y CONFIG_FW_LOADER_COMPRESS_ZSTD=y CONFIG_FW_CACHE=y CONFIG_FW_UPLOAD=y # end of Firmware loader CONFIG_WANT_DEV_COREDUMP=y CONFIG_ALLOW_DEV_COREDUMP=y CONFIG_DEV_COREDUMP=y CONFIG_DEBUG_DRIVER=y CONFIG_DEBUG_DEVRES=y CONFIG_DEBUG_TEST_DRIVER_REMOVE=y CONFIG_PM_QOS_KUNIT_TEST=y CONFIG_TEST_ASYNC_DRIVER_PROBE=m CONFIG_DRIVER_PE_KUNIT_TEST=y CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y CONFIG_REGMAP_SLIMBUS=y CONFIG_REGMAP_SPI=y CONFIG_REGMAP_SPMI=y CONFIG_REGMAP_W1=y CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_IRQ=y CONFIG_REGMAP_SOUNDWIRE=y CONFIG_REGMAP_SOUNDWIRE_MBQ=y CONFIG_REGMAP_SCCB=y CONFIG_REGMAP_I3C=y CONFIG_REGMAP_SPI_AVMM=y CONFIG_DMA_SHARED_BUFFER=y CONFIG_DMA_FENCE_TRACE=y # end of Generic Driver Options # # Bus devices # CONFIG_MOXTET=y CONFIG_MHI_BUS=y CONFIG_MHI_BUS_DEBUG=y CONFIG_MHI_BUS_PCI_GENERIC=y CONFIG_MHI_BUS_EP=y # end of Bus devices CONFIG_CONNECTOR=y CONFIG_PROC_EVENTS=y # # Firmware Drivers # # # ARM System Control and Management Interface Protocol # # end of ARM System Control and Management Interface Protocol CONFIG_EDD=y CONFIG_EDD_OFF=y CONFIG_FIRMWARE_MEMMAP=y CONFIG_DMIID=y CONFIG_DMI_SYSFS=y CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y CONFIG_ISCSI_IBFT_FIND=y CONFIG_ISCSI_IBFT=y CONFIG_FW_CFG_SYSFS=y CONFIG_FW_CFG_SYSFS_CMDLINE=y CONFIG_SYSFB=y CONFIG_SYSFB_SIMPLEFB=y CONFIG_CS_DSP=y CONFIG_GOOGLE_FIRMWARE=y CONFIG_GOOGLE_SMI=y CONFIG_GOOGLE_COREBOOT_TABLE=y CONFIG_GOOGLE_MEMCONSOLE=y CONFIG_GOOGLE_MEMCONSOLE_X86_LEGACY=y CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=y CONFIG_GOOGLE_VPD=y # # EFI (Extensible Firmware Interface) Support # CONFIG_EFI_ESRT=y CONFIG_EFI_VARS_PSTORE=y CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y CONFIG_EFI_RUNTIME_MAP=y CONFIG_EFI_FAKE_MEMMAP=y CONFIG_EFI_MAX_FAKE_MEM=8 CONFIG_EFI_DXE_MEM_ATTRIBUTES=y CONFIG_EFI_RUNTIME_WRAPPERS=y CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y CONFIG_EFI_BOOTLOADER_CONTROL=y CONFIG_EFI_CAPSULE_LOADER=y CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH=y CONFIG_EFI_TEST=y CONFIG_EFI_DEV_PATH_PARSER=y CONFIG_APPLE_PROPERTIES=y CONFIG_RESET_ATTACK_MITIGATION=y CONFIG_EFI_RCI2_TABLE=y CONFIG_EFI_DISABLE_PCI_DMA=y CONFIG_EFI_EARLYCON=y CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y CONFIG_EFI_DISABLE_RUNTIME=y CONFIG_EFI_COCO_SECRET=y CONFIG_EFI_EMBEDDED_FIRMWARE=y # end of EFI (Extensible Firmware Interface) Support CONFIG_UEFI_CPER=y CONFIG_UEFI_CPER_X86=y # # Tegra firmware driver # # end of Tegra firmware driver # end of Firmware Drivers CONFIG_GNSS=y CONFIG_GNSS_SERIAL=y CONFIG_GNSS_MTK_SERIAL=y CONFIG_GNSS_SIRF_SERIAL=y CONFIG_GNSS_UBX_SERIAL=y CONFIG_GNSS_USB=y CONFIG_MTD=y CONFIG_MTD_TESTS=m # # Partition parsers # CONFIG_MTD_AR7_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_OF_PARTS=y CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y CONFIG_MTD_REDBOOT_PARTS_READONLY=y # end of Partition parsers # # User Modules And Translation Layers # CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y # # Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. # CONFIG_FTL=y CONFIG_NFTL=y CONFIG_NFTL_RW=y CONFIG_INFTL=y CONFIG_RFD_FTL=y CONFIG_SSFDC=y CONFIG_SM_FTL=y CONFIG_MTD_OOPS=y CONFIG_MTD_PSTORE=y CONFIG_MTD_SWAP=y CONFIG_MTD_PARTITIONED_MASTER=y # # RAM/ROM/Flash chip drivers # CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y CONFIG_MTD_GEN_PROBE=y CONFIG_MTD_CFI_ADV_OPTIONS=y CONFIG_MTD_CFI_NOSWAP=y # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set CONFIG_MTD_CFI_GEOMETRY=y CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y CONFIG_MTD_MAP_BANK_WIDTH_8=y CONFIG_MTD_MAP_BANK_WIDTH_16=y CONFIG_MTD_MAP_BANK_WIDTH_32=y CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_I4=y CONFIG_MTD_CFI_I8=y CONFIG_MTD_OTP=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_STAA=y CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y CONFIG_MTD_ROM=y CONFIG_MTD_ABSENT=y # end of RAM/ROM/Flash chip drivers # # Mapping drivers for chip access # CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP_COMPAT=y CONFIG_MTD_PHYSMAP_START=0x8000000 CONFIG_MTD_PHYSMAP_LEN=0 CONFIG_MTD_PHYSMAP_BANKWIDTH=2 CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_VERSATILE=y CONFIG_MTD_PHYSMAP_GEMINI=y CONFIG_MTD_PHYSMAP_GPIO_ADDR=y CONFIG_MTD_SBC_GXX=y CONFIG_MTD_SCx200_DOCFLASH=y CONFIG_MTD_AMD76XROM=y CONFIG_MTD_ICHXROM=y CONFIG_MTD_ESB2ROM=y CONFIG_MTD_CK804XROM=y CONFIG_MTD_SCB2_FLASH=y CONFIG_MTD_NETtel=y CONFIG_MTD_L440GX=y CONFIG_MTD_PCI=y CONFIG_MTD_PCMCIA=y CONFIG_MTD_PCMCIA_ANONYMOUS=y CONFIG_MTD_INTEL_VR_NOR=y CONFIG_MTD_PLATRAM=y # end of Mapping drivers for chip access # # Self-contained MTD device drivers # CONFIG_MTD_PMC551=y CONFIG_MTD_PMC551_BUGFIX=y CONFIG_MTD_PMC551_DEBUG=y CONFIG_MTD_DATAFLASH=y CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y CONFIG_MTD_DATAFLASH_OTP=y CONFIG_MTD_MCHP23K256=y CONFIG_MTD_MCHP48L640=y CONFIG_MTD_SST25L=y CONFIG_MTD_SLRAM=y CONFIG_MTD_PHRAM=y CONFIG_MTD_MTDRAM=y CONFIG_MTDRAM_TOTAL_SIZE=4096 CONFIG_MTDRAM_ERASE_SIZE=128 CONFIG_MTD_BLOCK2MTD=y # # Disk-On-Chip Device Drivers # CONFIG_MTD_DOCG3=y CONFIG_BCH_CONST_M=14 CONFIG_BCH_CONST_T=4 # end of Self-contained MTD device drivers # # NAND # CONFIG_MTD_NAND_CORE=y CONFIG_MTD_ONENAND=y CONFIG_MTD_ONENAND_VERIFY_WRITE=y CONFIG_MTD_ONENAND_GENERIC=y CONFIG_MTD_ONENAND_OTP=y CONFIG_MTD_ONENAND_2X_PROGRAM=y CONFIG_MTD_RAW_NAND=y # # Raw/parallel NAND flash controllers # CONFIG_MTD_NAND_DENALI=y CONFIG_MTD_NAND_DENALI_PCI=y CONFIG_MTD_NAND_DENALI_DT=y CONFIG_MTD_NAND_CAFE=y CONFIG_MTD_NAND_CS553X=y CONFIG_MTD_NAND_MXIC=y CONFIG_MTD_NAND_GPIO=y CONFIG_MTD_NAND_PLATFORM=y CONFIG_MTD_NAND_CADENCE=y CONFIG_MTD_NAND_ARASAN=y CONFIG_MTD_NAND_INTEL_LGM=y # # Misc # CONFIG_MTD_SM_COMMON=y CONFIG_MTD_NAND_NANDSIM=y CONFIG_MTD_NAND_RICOH=y CONFIG_MTD_NAND_DISKONCHIP=y CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y CONFIG_MTD_SPI_NAND=y # # ECC engine support # CONFIG_MTD_NAND_ECC=y CONFIG_MTD_NAND_ECC_SW_HAMMING=y CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y CONFIG_MTD_NAND_ECC_SW_BCH=y CONFIG_MTD_NAND_ECC_MXIC=y # end of ECC engine support # end of NAND # # LPDDR & LPDDR2 PCM memory drivers # CONFIG_MTD_LPDDR=y CONFIG_MTD_QINFO_PROBE=y # end of LPDDR & LPDDR2 PCM memory drivers CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y # CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y # CONFIG_MTD_SPI_NOR_SWP_KEEP is not set CONFIG_MTD_UBI=y CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_GLUEBI=y CONFIG_MTD_UBI_BLOCK=y CONFIG_MTD_HYPERBUS=y CONFIG_DTC=y CONFIG_OF=y CONFIG_OF_UNITTEST=y CONFIG_OF_FLATTREE=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_PROMTREE=y CONFIG_OF_KOBJ=y CONFIG_OF_DYNAMIC=y CONFIG_OF_ADDRESS=y CONFIG_OF_IRQ=y CONFIG_OF_RESERVED_MEM=y CONFIG_OF_RESOLVE=y CONFIG_OF_OVERLAY=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_PARPORT=y CONFIG_PARPORT_PC=y CONFIG_PARPORT_SERIAL=y CONFIG_PARPORT_PC_FIFO=y CONFIG_PARPORT_PC_SUPERIO=y CONFIG_PARPORT_PC_PCMCIA=y CONFIG_PARPORT_AX88796=y CONFIG_PARPORT_1284=y CONFIG_PARPORT_NOT_PC=y CONFIG_PNP=y CONFIG_PNP_DEBUG_MESSAGES=y # # Protocols # CONFIG_ISAPNP=y CONFIG_PNPBIOS=y CONFIG_PNPBIOS_PROC_FS=y CONFIG_PNPACPI=y CONFIG_BLK_DEV=y CONFIG_BLK_DEV_NULL_BLK=y CONFIG_BLK_DEV_NULL_BLK_FAULT_INJECTION=y CONFIG_BLK_DEV_FD=y CONFIG_BLK_DEV_FD_RAWCMD=y CONFIG_CDROM=y CONFIG_PARIDE=y # # Parallel IDE high-level drivers # CONFIG_PARIDE_PD=y CONFIG_PARIDE_PCD=y CONFIG_PARIDE_PF=y CONFIG_PARIDE_PT=y CONFIG_PARIDE_PG=y # # Parallel IDE protocol modules # CONFIG_PARIDE_ATEN=y CONFIG_PARIDE_BPCK=y CONFIG_PARIDE_BPCK6=y CONFIG_PARIDE_COMM=y CONFIG_PARIDE_DSTR=y CONFIG_PARIDE_FIT2=y CONFIG_PARIDE_FIT3=y CONFIG_PARIDE_EPAT=y CONFIG_PARIDE_EPATC8=y CONFIG_PARIDE_EPIA=y CONFIG_PARIDE_FRIQ=y CONFIG_PARIDE_FRPW=y CONFIG_PARIDE_KBIC=y CONFIG_PARIDE_KTTI=y CONFIG_PARIDE_ON20=y CONFIG_PARIDE_ON26=y CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y CONFIG_ZRAM=y CONFIG_ZRAM_DEF_COMP_LZORLE=y # CONFIG_ZRAM_DEF_COMP_ZSTD is not set # CONFIG_ZRAM_DEF_COMP_LZ4 is not set # CONFIG_ZRAM_DEF_COMP_LZO is not set # CONFIG_ZRAM_DEF_COMP_LZ4HC is not set # CONFIG_ZRAM_DEF_COMP_842 is not set CONFIG_ZRAM_DEF_COMP="lzo-rle" CONFIG_ZRAM_WRITEBACK=y CONFIG_ZRAM_MEMORY_TRACKING=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 CONFIG_BLK_DEV_DRBD=y CONFIG_DRBD_FAULT_INJECTION=y CONFIG_BLK_DEV_NBD=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 CONFIG_CDROM_PKTCDVD=y CONFIG_CDROM_PKTCDVD_BUFFERS=8 CONFIG_CDROM_PKTCDVD_WCACHE=y CONFIG_ATA_OVER_ETH=y CONFIG_VIRTIO_BLK=y CONFIG_BLK_DEV_RBD=y CONFIG_BLK_DEV_UBLK=y CONFIG_BLK_DEV_RNBD=y CONFIG_BLK_DEV_RNBD_CLIENT=y CONFIG_BLK_DEV_RNBD_SERVER=y # # NVME Support # CONFIG_NVME_COMMON=y CONFIG_NVME_CORE=y CONFIG_BLK_DEV_NVME=y CONFIG_NVME_MULTIPATH=y CONFIG_NVME_VERBOSE_ERRORS=y CONFIG_NVME_HWMON=y CONFIG_NVME_FABRICS=y CONFIG_NVME_RDMA=y CONFIG_NVME_FC=y CONFIG_NVME_TCP=y CONFIG_NVME_AUTH=y CONFIG_NVME_TARGET=y CONFIG_NVME_TARGET_PASSTHRU=y CONFIG_NVME_TARGET_LOOP=y CONFIG_NVME_TARGET_RDMA=y CONFIG_NVME_TARGET_FC=y CONFIG_NVME_TARGET_FCLOOP=y CONFIG_NVME_TARGET_TCP=y CONFIG_NVME_TARGET_AUTH=y # end of NVME Support # # Misc devices # CONFIG_SENSORS_LIS3LV02D=y CONFIG_AD525X_DPOT=y CONFIG_AD525X_DPOT_I2C=y CONFIG_AD525X_DPOT_SPI=y CONFIG_DUMMY_IRQ=y CONFIG_IBM_ASM=y CONFIG_PHANTOM=y CONFIG_TIFM_CORE=y CONFIG_TIFM_7XX1=y CONFIG_ICS932S401=y CONFIG_ENCLOSURE_SERVICES=y CONFIG_CS5535_MFGPT=y CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7 CONFIG_CS5535_CLOCK_EVENT_SRC=y CONFIG_HI6421V600_IRQ=y CONFIG_HP_ILO=y CONFIG_APDS9802ALS=y CONFIG_ISL29003=y CONFIG_ISL29020=y CONFIG_SENSORS_TSL2550=y CONFIG_SENSORS_BH1770=y CONFIG_SENSORS_APDS990X=y CONFIG_HMC6352=y CONFIG_DS1682=y CONFIG_VMWARE_BALLOON=y CONFIG_PCH_PHUB=y CONFIG_LATTICE_ECP3_CONFIG=y CONFIG_SRAM=y CONFIG_DW_XDATA_PCIE=y CONFIG_PCI_ENDPOINT_TEST=y CONFIG_XILINX_SDFEC=y CONFIG_MISC_RTSX=y CONFIG_HISI_HIKEY_USB=y CONFIG_OPEN_DICE=y CONFIG_VCPU_STALL_DETECTOR=y CONFIG_C2PORT=y CONFIG_C2PORT_DURAMAR_2150=y # # EEPROM support # CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT25=y CONFIG_EEPROM_LEGACY=y CONFIG_EEPROM_MAX6875=y CONFIG_EEPROM_93CX6=y CONFIG_EEPROM_93XX46=y CONFIG_EEPROM_IDT_89HPESX=y CONFIG_EEPROM_EE1004=y # end of EEPROM support CONFIG_CB710_CORE=y CONFIG_CB710_DEBUG=y CONFIG_CB710_DEBUG_ASSUMPTIONS=y # # Texas Instruments shared transport line discipline # CONFIG_TI_ST=y # end of Texas Instruments shared transport line discipline CONFIG_SENSORS_LIS3_I2C=y CONFIG_ALTERA_STAPL=y CONFIG_INTEL_MEI=y CONFIG_INTEL_MEI_ME=y CONFIG_INTEL_MEI_TXE=y CONFIG_INTEL_MEI_GSC=y CONFIG_INTEL_MEI_HDCP=y CONFIG_INTEL_MEI_PXP=y CONFIG_VMWARE_VMCI=y CONFIG_ECHO=y CONFIG_BCM_VK=y CONFIG_BCM_VK_TTY=y CONFIG_MISC_ALCOR_PCI=y CONFIG_MISC_RTSX_PCI=y CONFIG_MISC_RTSX_USB=y CONFIG_HABANA_AI=y CONFIG_UACCE=y CONFIG_PVPANIC=y CONFIG_PVPANIC_MMIO=y CONFIG_PVPANIC_PCI=y CONFIG_GP_PCI1XXXX=y # end of Misc devices # # SCSI device support # CONFIG_SCSI_MOD=y CONFIG_RAID_ATTRS=y CONFIG_SCSI_COMMON=y CONFIG_SCSI=y CONFIG_SCSI_DMA=y CONFIG_SCSI_NETLINK=y CONFIG_SCSI_PROC_FS=y # # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=y CONFIG_BLK_DEV_SR=y CONFIG_CHR_DEV_SG=y CONFIG_BLK_DEV_BSG=y CONFIG_CHR_DEV_SCH=y CONFIG_SCSI_ENCLOSURE=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y # # SCSI Transports # CONFIG_SCSI_SPI_ATTRS=y CONFIG_SCSI_FC_ATTRS=y CONFIG_SCSI_ISCSI_ATTRS=y CONFIG_SCSI_SAS_ATTRS=y CONFIG_SCSI_SAS_LIBSAS=y CONFIG_SCSI_SAS_ATA=y CONFIG_SCSI_SAS_HOST_SMP=y CONFIG_SCSI_SRP_ATTRS=y # end of SCSI Transports CONFIG_SCSI_LOWLEVEL=y CONFIG_ISCSI_TCP=y CONFIG_ISCSI_BOOT_SYSFS=y CONFIG_SCSI_CXGB3_ISCSI=y CONFIG_SCSI_CXGB4_ISCSI=y CONFIG_SCSI_BNX2_ISCSI=y CONFIG_SCSI_BNX2X_FCOE=y CONFIG_BE2ISCSI=y CONFIG_BLK_DEV_3W_XXXX_RAID=y CONFIG_SCSI_HPSA=y CONFIG_SCSI_3W_9XXX=y CONFIG_SCSI_3W_SAS=y CONFIG_SCSI_ACARD=y CONFIG_SCSI_AHA152X=y CONFIG_SCSI_AHA1542=y CONFIG_SCSI_AHA1740=y CONFIG_SCSI_AACRAID=y CONFIG_SCSI_AIC7XXX=y CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 CONFIG_AIC7XXX_RESET_DELAY_MS=5000 CONFIG_AIC7XXX_DEBUG_ENABLE=y CONFIG_AIC7XXX_DEBUG_MASK=0 CONFIG_AIC7XXX_REG_PRETTY_PRINT=y CONFIG_SCSI_AIC79XX=y CONFIG_AIC79XX_CMDS_PER_DEVICE=32 CONFIG_AIC79XX_RESET_DELAY_MS=5000 CONFIG_AIC79XX_DEBUG_ENABLE=y CONFIG_AIC79XX_DEBUG_MASK=0 CONFIG_AIC79XX_REG_PRETTY_PRINT=y CONFIG_SCSI_AIC94XX=y CONFIG_AIC94XX_DEBUG=y CONFIG_SCSI_MVSAS=y CONFIG_SCSI_MVSAS_DEBUG=y CONFIG_SCSI_MVSAS_TASKLET=y CONFIG_SCSI_MVUMI=y CONFIG_SCSI_ADVANSYS=y CONFIG_SCSI_ARCMSR=y CONFIG_SCSI_ESAS2R=y CONFIG_MEGARAID_NEWGEN=y CONFIG_MEGARAID_MM=y CONFIG_MEGARAID_MAILBOX=y CONFIG_MEGARAID_LEGACY=y CONFIG_MEGARAID_SAS=y CONFIG_SCSI_MPT3SAS=y CONFIG_SCSI_MPT2SAS_MAX_SGE=128 CONFIG_SCSI_MPT3SAS_MAX_SGE=128 CONFIG_SCSI_MPT2SAS=y CONFIG_SCSI_MPI3MR=y CONFIG_SCSI_SMARTPQI=y CONFIG_SCSI_HPTIOP=y CONFIG_SCSI_BUSLOGIC=y CONFIG_SCSI_FLASHPOINT=y CONFIG_SCSI_MYRB=y CONFIG_SCSI_MYRS=y CONFIG_VMWARE_PVSCSI=y CONFIG_HYPERV_STORAGE=y CONFIG_LIBFC=y CONFIG_LIBFCOE=y CONFIG_FCOE=y CONFIG_FCOE_FNIC=y CONFIG_SCSI_SNIC=y CONFIG_SCSI_SNIC_DEBUG_FS=y CONFIG_SCSI_DMX3191D=y CONFIG_SCSI_FDOMAIN=y CONFIG_SCSI_FDOMAIN_PCI=y CONFIG_SCSI_FDOMAIN_ISA=y CONFIG_SCSI_ISCI=y CONFIG_SCSI_GENERIC_NCR5380=y CONFIG_SCSI_IPS=y CONFIG_SCSI_INITIO=y CONFIG_SCSI_INIA100=y CONFIG_SCSI_PPA=y CONFIG_SCSI_IMM=y CONFIG_SCSI_IZIP_EPP16=y CONFIG_SCSI_IZIP_SLOW_CTR=y CONFIG_SCSI_STEX=y CONFIG_SCSI_SYM53C8XX_2=y CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 CONFIG_SCSI_SYM53C8XX_MMIO=y CONFIG_SCSI_IPR=y CONFIG_SCSI_IPR_TRACE=y CONFIG_SCSI_IPR_DUMP=y CONFIG_SCSI_QLOGIC_FAS=y CONFIG_SCSI_QLOGIC_1280=y CONFIG_SCSI_QLA_FC=y CONFIG_TCM_QLA2XXX=y CONFIG_TCM_QLA2XXX_DEBUG=y CONFIG_SCSI_QLA_ISCSI=y CONFIG_QEDI=y CONFIG_QEDF=y CONFIG_SCSI_LPFC=y CONFIG_SCSI_LPFC_DEBUG_FS=y CONFIG_SCSI_EFCT=y CONFIG_SCSI_SIM710=y CONFIG_SCSI_DC395x=y CONFIG_SCSI_AM53C974=y CONFIG_SCSI_NSP32=y CONFIG_SCSI_WD719X=y CONFIG_SCSI_DEBUG=y CONFIG_SCSI_PMCRAID=y CONFIG_SCSI_PM8001=y CONFIG_SCSI_BFA_FC=y CONFIG_SCSI_VIRTIO=y CONFIG_SCSI_CHELSIO_FCOE=y CONFIG_SCSI_LOWLEVEL_PCMCIA=y CONFIG_PCMCIA_AHA152X=m CONFIG_PCMCIA_FDOMAIN=m CONFIG_PCMCIA_NINJA_SCSI=m CONFIG_PCMCIA_QLOGIC=m CONFIG_PCMCIA_SYM53C500=m CONFIG_SCSI_DH=y CONFIG_SCSI_DH_RDAC=y CONFIG_SCSI_DH_HP_SW=y CONFIG_SCSI_DH_EMC=y CONFIG_SCSI_DH_ALUA=y # end of SCSI device support CONFIG_ATA=y CONFIG_SATA_HOST=y CONFIG_PATA_TIMINGS=y CONFIG_ATA_VERBOSE_ERROR=y CONFIG_ATA_FORCE=y CONFIG_ATA_ACPI=y CONFIG_SATA_ZPODD=y CONFIG_SATA_PMP=y # # Controllers with non-SFF native interface # CONFIG_SATA_AHCI=y CONFIG_SATA_MOBILE_LPM_POLICY=0 CONFIG_SATA_AHCI_PLATFORM=y CONFIG_AHCI_DWC=y CONFIG_AHCI_CEVA=y CONFIG_AHCI_QORIQ=y CONFIG_SATA_INIC162X=y CONFIG_SATA_ACARD_AHCI=y CONFIG_SATA_SIL24=y CONFIG_ATA_SFF=y # # SFF controllers with custom DMA interface # CONFIG_PDC_ADMA=y CONFIG_SATA_QSTOR=y CONFIG_SATA_SX4=y CONFIG_ATA_BMDMA=y # # SATA SFF controllers with BMDMA # CONFIG_ATA_PIIX=y CONFIG_SATA_DWC=y CONFIG_SATA_DWC_OLD_DMA=y CONFIG_SATA_MV=y CONFIG_SATA_NV=y CONFIG_SATA_PROMISE=y CONFIG_SATA_SIL=y CONFIG_SATA_SIS=y CONFIG_SATA_SVW=y CONFIG_SATA_ULI=y CONFIG_SATA_VIA=y CONFIG_SATA_VITESSE=y # # PATA SFF controllers with BMDMA # CONFIG_PATA_ALI=y CONFIG_PATA_AMD=y CONFIG_PATA_ARTOP=y CONFIG_PATA_ATIIXP=y CONFIG_PATA_ATP867X=y CONFIG_PATA_CMD64X=y CONFIG_PATA_CS5520=y CONFIG_PATA_CS5530=y CONFIG_PATA_CS5535=y CONFIG_PATA_CS5536=y CONFIG_PATA_CYPRESS=y CONFIG_PATA_EFAR=y CONFIG_PATA_HPT366=y CONFIG_PATA_HPT37X=y CONFIG_PATA_HPT3X2N=y CONFIG_PATA_HPT3X3=y CONFIG_PATA_HPT3X3_DMA=y CONFIG_PATA_IT8213=y CONFIG_PATA_IT821X=y CONFIG_PATA_JMICRON=y CONFIG_PATA_MARVELL=y CONFIG_PATA_NETCELL=y CONFIG_PATA_NINJA32=y CONFIG_PATA_NS87415=y CONFIG_PATA_OLDPIIX=y CONFIG_PATA_OPTIDMA=y CONFIG_PATA_PDC2027X=y CONFIG_PATA_PDC_OLD=y CONFIG_PATA_RADISYS=y CONFIG_PATA_RDC=y CONFIG_PATA_SC1200=y CONFIG_PATA_SCH=y CONFIG_PATA_SERVERWORKS=y CONFIG_PATA_SIL680=y CONFIG_PATA_SIS=y CONFIG_PATA_TOSHIBA=y CONFIG_PATA_TRIFLEX=y CONFIG_PATA_VIA=y CONFIG_PATA_WINBOND=y # # PIO-only SFF controllers # CONFIG_PATA_CMD640_PCI=y CONFIG_PATA_ISAPNP=y CONFIG_PATA_MPIIX=y CONFIG_PATA_NS87410=y CONFIG_PATA_OPTI=y CONFIG_PATA_PCMCIA=y CONFIG_PATA_PLATFORM=y CONFIG_PATA_OF_PLATFORM=y CONFIG_PATA_QDI=y CONFIG_PATA_RZ1000=y CONFIG_PATA_WINBOND_VLB=y # # Generic fallback / legacy drivers # CONFIG_PATA_ACPI=y CONFIG_ATA_GENERIC=y CONFIG_PATA_LEGACY=y CONFIG_MD=y CONFIG_BLK_DEV_MD=y CONFIG_MD_AUTODETECT=y CONFIG_MD_LINEAR=y CONFIG_MD_RAID0=y CONFIG_MD_RAID1=y CONFIG_MD_RAID10=y CONFIG_MD_RAID456=y CONFIG_MD_MULTIPATH=y CONFIG_MD_FAULTY=y CONFIG_MD_CLUSTER=y CONFIG_BCACHE=y CONFIG_BCACHE_DEBUG=y CONFIG_BCACHE_CLOSURES_DEBUG=y CONFIG_BCACHE_ASYNC_REGISTRATION=y CONFIG_BLK_DEV_DM_BUILTIN=y CONFIG_BLK_DEV_DM=y CONFIG_DM_DEBUG=y CONFIG_DM_BUFIO=y CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING=y CONFIG_DM_DEBUG_BLOCK_STACK_TRACING=y CONFIG_DM_BIO_PRISON=y CONFIG_DM_PERSISTENT_DATA=y CONFIG_DM_UNSTRIPED=y CONFIG_DM_CRYPT=y CONFIG_DM_SNAPSHOT=y CONFIG_DM_THIN_PROVISIONING=y CONFIG_DM_CACHE=y CONFIG_DM_CACHE_SMQ=y CONFIG_DM_WRITECACHE=y CONFIG_DM_ERA=y CONFIG_DM_CLONE=y CONFIG_DM_MIRROR=y CONFIG_DM_LOG_USERSPACE=y CONFIG_DM_RAID=y CONFIG_DM_ZERO=y CONFIG_DM_MULTIPATH=y CONFIG_DM_MULTIPATH_QL=y CONFIG_DM_MULTIPATH_ST=y CONFIG_DM_MULTIPATH_HST=y CONFIG_DM_MULTIPATH_IOA=y CONFIG_DM_DELAY=y CONFIG_DM_DUST=y CONFIG_DM_INIT=y CONFIG_DM_UEVENT=y CONFIG_DM_FLAKEY=y CONFIG_DM_VERITY=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_FEC=y CONFIG_DM_SWITCH=y CONFIG_DM_LOG_WRITES=y CONFIG_DM_INTEGRITY=y CONFIG_DM_ZONED=y CONFIG_DM_AUDIT=y CONFIG_TARGET_CORE=y CONFIG_TCM_IBLOCK=y CONFIG_TCM_FILEIO=y CONFIG_TCM_PSCSI=y CONFIG_TCM_USER2=y CONFIG_LOOPBACK_TARGET=y CONFIG_TCM_FC=y CONFIG_ISCSI_TARGET=y CONFIG_ISCSI_TARGET_CXGB4=y CONFIG_SBP_TARGET=y CONFIG_FUSION=y CONFIG_FUSION_SPI=y CONFIG_FUSION_FC=y CONFIG_FUSION_SAS=y CONFIG_FUSION_MAX_SGE=128 CONFIG_FUSION_CTL=y CONFIG_FUSION_LAN=y CONFIG_FUSION_LOGGING=y # # IEEE 1394 (FireWire) support # CONFIG_FIREWIRE=y CONFIG_FIREWIRE_OHCI=y CONFIG_FIREWIRE_SBP2=y CONFIG_FIREWIRE_NET=y CONFIG_FIREWIRE_NOSY=y # end of IEEE 1394 (FireWire) support CONFIG_MACINTOSH_DRIVERS=y CONFIG_MAC_EMUMOUSEBTN=y CONFIG_NETDEVICES=y CONFIG_MII=y CONFIG_NET_CORE=y CONFIG_BONDING=y CONFIG_DUMMY=y CONFIG_WIREGUARD=y CONFIG_WIREGUARD_DEBUG=y CONFIG_EQUALIZER=y CONFIG_NET_FC=y CONFIG_IFB=y CONFIG_NET_TEAM=y CONFIG_NET_TEAM_MODE_BROADCAST=y CONFIG_NET_TEAM_MODE_ROUNDROBIN=y CONFIG_NET_TEAM_MODE_RANDOM=y CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=y CONFIG_NET_TEAM_MODE_LOADBALANCE=y CONFIG_MACVLAN=y CONFIG_MACVTAP=y CONFIG_IPVLAN_L3S=y CONFIG_IPVLAN=y CONFIG_IPVTAP=y CONFIG_VXLAN=y CONFIG_GENEVE=y CONFIG_BAREUDP=y CONFIG_GTP=y CONFIG_AMT=y CONFIG_MACSEC=y CONFIG_NETCONSOLE=y CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_NETPOLL=y CONFIG_NET_POLL_CONTROLLER=y CONFIG_NTB_NETDEV=y CONFIG_RIONET=y CONFIG_RIONET_TX_SIZE=128 CONFIG_RIONET_RX_SIZE=128 CONFIG_TUN=y CONFIG_TAP=y CONFIG_TUN_VNET_CROSS_LE=y CONFIG_VETH=y CONFIG_VIRTIO_NET=y CONFIG_NLMON=y CONFIG_NET_VRF=y CONFIG_VSOCKMON=y CONFIG_MHI_NET=y CONFIG_SUNGEM_PHY=y CONFIG_ARCNET=y CONFIG_ARCNET_1201=y CONFIG_ARCNET_1051=y CONFIG_ARCNET_RAW=y CONFIG_ARCNET_CAP=y CONFIG_ARCNET_COM90xx=y CONFIG_ARCNET_COM90xxIO=y CONFIG_ARCNET_RIM_I=y CONFIG_ARCNET_COM20020=y CONFIG_ARCNET_COM20020_ISA=y CONFIG_ARCNET_COM20020_PCI=y CONFIG_ARCNET_COM20020_CS=y CONFIG_ATM_DRIVERS=y CONFIG_ATM_DUMMY=y CONFIG_ATM_TCP=y CONFIG_ATM_LANAI=y CONFIG_ATM_ENI=y CONFIG_ATM_ENI_DEBUG=y CONFIG_ATM_ENI_TUNE_BURST=y CONFIG_ATM_ENI_BURST_TX_16W=y CONFIG_ATM_ENI_BURST_TX_8W=y CONFIG_ATM_ENI_BURST_TX_4W=y CONFIG_ATM_ENI_BURST_TX_2W=y CONFIG_ATM_ENI_BURST_RX_16W=y CONFIG_ATM_ENI_BURST_RX_8W=y CONFIG_ATM_ENI_BURST_RX_4W=y CONFIG_ATM_ENI_BURST_RX_2W=y CONFIG_ATM_NICSTAR=y CONFIG_ATM_NICSTAR_USE_SUNI=y CONFIG_ATM_NICSTAR_USE_IDT77105=y CONFIG_ATM_IDT77252=y CONFIG_ATM_IDT77252_DEBUG=y CONFIG_ATM_IDT77252_RCV_ALL=y CONFIG_ATM_IDT77252_USE_SUNI=y CONFIG_ATM_IA=y CONFIG_ATM_IA_DEBUG=y CONFIG_ATM_FORE200E=y CONFIG_ATM_FORE200E_USE_TASKLET=y CONFIG_ATM_FORE200E_TX_RETRY=16 CONFIG_ATM_FORE200E_DEBUG=0 CONFIG_ATM_HE=y CONFIG_ATM_HE_USE_SUNI=y CONFIG_ATM_SOLOS=y CONFIG_CAIF_DRIVERS=y CONFIG_CAIF_TTY=y CONFIG_CAIF_VIRTIO=y # # Distributed Switch Architecture drivers # CONFIG_B53=y CONFIG_B53_SPI_DRIVER=y CONFIG_B53_MDIO_DRIVER=y CONFIG_B53_MMAP_DRIVER=y CONFIG_B53_SRAB_DRIVER=y CONFIG_B53_SERDES=y CONFIG_NET_DSA_BCM_SF2=y CONFIG_NET_DSA_LOOP=y CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=y CONFIG_NET_DSA_LANTIQ_GSWIP=y CONFIG_NET_DSA_MT7530=y CONFIG_NET_DSA_MV88E6060=y CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=y CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=y CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=y CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=y CONFIG_NET_DSA_MV88E6XXX=y CONFIG_NET_DSA_MV88E6XXX_PTP=y CONFIG_NET_DSA_MSCC_SEVILLE=y CONFIG_NET_DSA_AR9331=y CONFIG_NET_DSA_QCA8K=y CONFIG_NET_DSA_SJA1105=y CONFIG_NET_DSA_SJA1105_PTP=y CONFIG_NET_DSA_SJA1105_TAS=y CONFIG_NET_DSA_SJA1105_VL=y CONFIG_NET_DSA_XRS700X=y CONFIG_NET_DSA_XRS700X_I2C=y CONFIG_NET_DSA_XRS700X_MDIO=y CONFIG_NET_DSA_REALTEK=y CONFIG_NET_DSA_REALTEK_MDIO=y CONFIG_NET_DSA_REALTEK_SMI=y CONFIG_NET_DSA_REALTEK_RTL8365MB=y CONFIG_NET_DSA_REALTEK_RTL8366RB=y CONFIG_NET_DSA_SMSC_LAN9303=y CONFIG_NET_DSA_SMSC_LAN9303_I2C=y CONFIG_NET_DSA_SMSC_LAN9303_MDIO=y CONFIG_NET_DSA_VITESSE_VSC73XX=y CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=y CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=y # end of Distributed Switch Architecture drivers CONFIG_ETHERNET=y CONFIG_MDIO=y CONFIG_NET_VENDOR_3COM=y CONFIG_EL3=y CONFIG_3C515=y CONFIG_PCMCIA_3C574=y CONFIG_PCMCIA_3C589=y CONFIG_VORTEX=y CONFIG_TYPHOON=y CONFIG_NET_VENDOR_ADAPTEC=y CONFIG_ADAPTEC_STARFIRE=y CONFIG_NET_VENDOR_AGERE=y CONFIG_ET131X=y CONFIG_NET_VENDOR_ALACRITECH=y CONFIG_SLICOSS=y CONFIG_NET_VENDOR_ALTEON=y CONFIG_ACENIC=y CONFIG_ACENIC_OMIT_TIGON_I=y CONFIG_ALTERA_TSE=y CONFIG_NET_VENDOR_AMAZON=y CONFIG_ENA_ETHERNET=y CONFIG_NET_VENDOR_AMD=y CONFIG_AMD8111_ETH=y CONFIG_LANCE=y CONFIG_PCNET32=y CONFIG_PCMCIA_NMCLAN=y CONFIG_AMD_XGBE=y CONFIG_AMD_XGBE_DCB=y CONFIG_AMD_XGBE_HAVE_ECC=y CONFIG_NET_VENDOR_AQUANTIA=y CONFIG_AQTION=y CONFIG_NET_VENDOR_ARC=y CONFIG_NET_VENDOR_ASIX=y CONFIG_SPI_AX88796C=y CONFIG_SPI_AX88796C_COMPRESSION=y CONFIG_NET_VENDOR_ATHEROS=y CONFIG_ATL2=y CONFIG_ATL1=y CONFIG_ATL1E=y CONFIG_ATL1C=y CONFIG_ALX=y CONFIG_CX_ECAT=y CONFIG_NET_VENDOR_BROADCOM=y CONFIG_B44=y CONFIG_B44_PCI_AUTOSELECT=y CONFIG_B44_PCICORE_AUTOSELECT=y CONFIG_B44_PCI=y CONFIG_BCMGENET=y CONFIG_BNX2=y CONFIG_CNIC=y CONFIG_TIGON3=y CONFIG_TIGON3_HWMON=y CONFIG_BNX2X=y CONFIG_BNX2X_SRIOV=y CONFIG_SYSTEMPORT=y CONFIG_BNXT=y CONFIG_BNXT_SRIOV=y CONFIG_BNXT_FLOWER_OFFLOAD=y CONFIG_BNXT_DCB=y CONFIG_BNXT_HWMON=y CONFIG_NET_VENDOR_CADENCE=y CONFIG_MACB=y CONFIG_MACB_USE_HWSTAMP=y CONFIG_MACB_PCI=y CONFIG_NET_VENDOR_CAVIUM=y CONFIG_NET_VENDOR_CHELSIO=y CONFIG_CHELSIO_T1=y CONFIG_CHELSIO_T1_1G=y CONFIG_CHELSIO_T3=y CONFIG_CHELSIO_T4=y CONFIG_CHELSIO_T4_DCB=y CONFIG_CHELSIO_T4_FCOE=y CONFIG_CHELSIO_T4VF=y CONFIG_CHELSIO_LIB=y CONFIG_CHELSIO_INLINE_CRYPTO=y CONFIG_CRYPTO_DEV_CHELSIO_TLS=y CONFIG_CHELSIO_IPSEC_INLINE=y CONFIG_CHELSIO_TLS_DEVICE=y CONFIG_NET_VENDOR_CIRRUS=y # CONFIG_CS89x0_ISA is not set CONFIG_NET_VENDOR_CISCO=y CONFIG_ENIC=y CONFIG_NET_VENDOR_CORTINA=y CONFIG_GEMINI_ETHERNET=y CONFIG_NET_VENDOR_DAVICOM=y CONFIG_DM9051=y CONFIG_DNET=y CONFIG_NET_VENDOR_DEC=y CONFIG_NET_TULIP=y CONFIG_DE2104X=y CONFIG_DE2104X_DSL=0 CONFIG_TULIP=y CONFIG_TULIP_MWI=y CONFIG_TULIP_MMIO=y CONFIG_TULIP_NAPI=y CONFIG_TULIP_NAPI_HW_MITIGATION=y CONFIG_WINBOND_840=y CONFIG_DM9102=y CONFIG_ULI526X=y CONFIG_PCMCIA_XIRCOM=y CONFIG_NET_VENDOR_DLINK=y CONFIG_DL2K=y CONFIG_SUNDANCE=y CONFIG_SUNDANCE_MMIO=y CONFIG_NET_VENDOR_EMULEX=y CONFIG_BE2NET=y CONFIG_BE2NET_HWMON=y CONFIG_BE2NET_BE2=y CONFIG_BE2NET_BE3=y CONFIG_BE2NET_LANCER=y CONFIG_BE2NET_SKYHAWK=y CONFIG_NET_VENDOR_ENGLEDER=y CONFIG_TSNEP=y CONFIG_TSNEP_SELFTESTS=y CONFIG_NET_VENDOR_EZCHIP=y CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=y CONFIG_NET_VENDOR_FUJITSU=y CONFIG_PCMCIA_FMVJ18X=y CONFIG_NET_VENDOR_FUNGIBLE=y CONFIG_FUN_CORE=y CONFIG_FUN_ETH=y CONFIG_NET_VENDOR_GOOGLE=y CONFIG_GVE=y CONFIG_NET_VENDOR_HUAWEI=y CONFIG_HINIC=y CONFIG_NET_VENDOR_I825XX=y CONFIG_NET_VENDOR_INTEL=y CONFIG_E100=y CONFIG_E1000=y CONFIG_E1000E=y CONFIG_E1000E_HWTS=y CONFIG_IGB=y CONFIG_IGB_HWMON=y CONFIG_IGBVF=y CONFIG_IXGB=y CONFIG_IXGBE=y CONFIG_IXGBE_HWMON=y CONFIG_IXGBE_DCB=y CONFIG_IXGBE_IPSEC=y CONFIG_IXGBEVF=y CONFIG_IXGBEVF_IPSEC=y CONFIG_I40E=y CONFIG_I40E_DCB=y CONFIG_IAVF=y CONFIG_I40EVF=y CONFIG_ICE=y CONFIG_ICE_SWITCHDEV=y CONFIG_ICE_HWTS=y CONFIG_FM10K=y CONFIG_IGC=y CONFIG_NET_VENDOR_WANGXUN=y CONFIG_NGBE=y CONFIG_TXGBE=y CONFIG_JME=y CONFIG_NET_VENDOR_ADI=y CONFIG_ADIN1110=y CONFIG_NET_VENDOR_LITEX=y CONFIG_LITEX_LITEETH=y CONFIG_NET_VENDOR_MARVELL=y CONFIG_MVMDIO=y CONFIG_SKGE=y CONFIG_SKGE_DEBUG=y CONFIG_SKGE_GENESIS=y CONFIG_SKY2=y CONFIG_SKY2_DEBUG=y CONFIG_PRESTERA=y CONFIG_PRESTERA_PCI=y CONFIG_NET_VENDOR_MELLANOX=y CONFIG_MLX4_EN=y CONFIG_MLX4_EN_DCB=y CONFIG_MLX4_CORE=y CONFIG_MLX4_DEBUG=y CONFIG_MLX4_CORE_GEN2=y CONFIG_MLX5_CORE=y CONFIG_MLX5_FPGA=y CONFIG_MLX5_CORE_EN=y CONFIG_MLX5_EN_ARFS=y CONFIG_MLX5_EN_RXNFC=y CONFIG_MLX5_MPFS=y CONFIG_MLX5_ESWITCH=y CONFIG_MLX5_BRIDGE=y CONFIG_MLX5_CLS_ACT=y CONFIG_MLX5_TC_CT=y CONFIG_MLX5_TC_SAMPLE=y CONFIG_MLX5_CORE_EN_DCB=y CONFIG_MLX5_CORE_IPOIB=y CONFIG_MLX5_EN_MACSEC=y CONFIG_MLX5_EN_IPSEC=y CONFIG_MLX5_EN_TLS=y CONFIG_MLX5_SW_STEERING=y CONFIG_MLX5_SF=y CONFIG_MLX5_SF_MANAGER=y CONFIG_MLXSW_CORE=y CONFIG_MLXSW_CORE_HWMON=y CONFIG_MLXSW_CORE_THERMAL=y CONFIG_MLXSW_PCI=y CONFIG_MLXSW_I2C=y CONFIG_MLXSW_SPECTRUM=y CONFIG_MLXSW_SPECTRUM_DCB=y CONFIG_MLXSW_MINIMAL=y CONFIG_MLXFW=y CONFIG_NET_VENDOR_MICREL=y CONFIG_KS8842=y CONFIG_KS8851=y CONFIG_KS8851_MLL=y CONFIG_KSZ884X_PCI=y CONFIG_NET_VENDOR_MICROCHIP=y CONFIG_ENC28J60=y CONFIG_ENC28J60_WRITEVERIFY=y CONFIG_ENCX24J600=y CONFIG_LAN743X=y CONFIG_LAN966X_SWITCH=y CONFIG_NET_VENDOR_MICROSEMI=y CONFIG_MSCC_OCELOT_SWITCH_LIB=y CONFIG_MSCC_OCELOT_SWITCH=y CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y CONFIG_MYRI10GE=y CONFIG_FEALNX=y CONFIG_NET_VENDOR_NI=y CONFIG_NI_XGE_MANAGEMENT_ENET=y CONFIG_NET_VENDOR_NATSEMI=y CONFIG_NATSEMI=y CONFIG_NS83820=y CONFIG_NET_VENDOR_NETERION=y CONFIG_S2IO=y CONFIG_NET_VENDOR_NETRONOME=y CONFIG_NFP=y CONFIG_NFP_APP_FLOWER=y CONFIG_NFP_APP_ABM_NIC=y CONFIG_NFP_DEBUG=y CONFIG_NET_VENDOR_8390=y CONFIG_PCMCIA_AXNET=y CONFIG_NE2000=y CONFIG_NE2K_PCI=y CONFIG_PCMCIA_PCNET=y CONFIG_ULTRA=y CONFIG_WD80x3=y CONFIG_NET_VENDOR_NVIDIA=y CONFIG_FORCEDETH=y CONFIG_NET_VENDOR_OKI=y CONFIG_PCH_GBE=y CONFIG_ETHOC=y CONFIG_NET_VENDOR_PACKET_ENGINES=y CONFIG_HAMACHI=y CONFIG_YELLOWFIN=y CONFIG_NET_VENDOR_PENSANDO=y CONFIG_NET_VENDOR_QLOGIC=y CONFIG_QLA3XXX=y CONFIG_QLCNIC=y CONFIG_QLCNIC_SRIOV=y CONFIG_QLCNIC_DCB=y CONFIG_QLCNIC_HWMON=y CONFIG_NETXEN_NIC=y CONFIG_QED=y CONFIG_QED_LL2=y CONFIG_QED_SRIOV=y CONFIG_QEDE=y CONFIG_QED_ISCSI=y CONFIG_QED_FCOE=y CONFIG_QED_OOO=y CONFIG_NET_VENDOR_BROCADE=y CONFIG_BNA=y CONFIG_NET_VENDOR_QUALCOMM=y CONFIG_QCA7000=y CONFIG_QCA7000_SPI=y CONFIG_QCA7000_UART=y CONFIG_QCOM_EMAC=y CONFIG_RMNET=y CONFIG_NET_VENDOR_RDC=y CONFIG_R6040=y CONFIG_NET_VENDOR_REALTEK=y CONFIG_ATP=y CONFIG_8139CP=y CONFIG_8139TOO=y CONFIG_8139TOO_PIO=y CONFIG_8139TOO_TUNE_TWISTER=y CONFIG_8139TOO_8129=y CONFIG_8139_OLD_RX_RESET=y CONFIG_R8169=y CONFIG_NET_VENDOR_RENESAS=y CONFIG_NET_VENDOR_ROCKER=y CONFIG_ROCKER=y CONFIG_NET_VENDOR_SAMSUNG=y CONFIG_SXGBE_ETH=y CONFIG_NET_VENDOR_SEEQ=y CONFIG_NET_VENDOR_SILAN=y CONFIG_SC92031=y CONFIG_NET_VENDOR_SIS=y CONFIG_SIS900=y CONFIG_SIS190=y CONFIG_NET_VENDOR_SOLARFLARE=y CONFIG_SFC=y CONFIG_SFC_MTD=y CONFIG_SFC_MCDI_MON=y CONFIG_SFC_SRIOV=y CONFIG_SFC_MCDI_LOGGING=y CONFIG_SFC_FALCON=y CONFIG_SFC_FALCON_MTD=y CONFIG_SFC_SIENA=y CONFIG_SFC_SIENA_MTD=y CONFIG_SFC_SIENA_MCDI_MON=y CONFIG_SFC_SIENA_SRIOV=y CONFIG_SFC_SIENA_MCDI_LOGGING=y CONFIG_NET_VENDOR_SMSC=y CONFIG_SMC9194=y CONFIG_PCMCIA_SMC91C92=y CONFIG_EPIC100=y CONFIG_SMSC911X=y CONFIG_SMSC9420=y CONFIG_NET_VENDOR_SOCIONEXT=y CONFIG_NET_VENDOR_STMICRO=y CONFIG_STMMAC_ETH=y CONFIG_STMMAC_SELFTESTS=y CONFIG_STMMAC_PLATFORM=y CONFIG_DWMAC_DWC_QOS_ETH=y CONFIG_DWMAC_GENERIC=y CONFIG_DWMAC_INTEL_PLAT=y CONFIG_DWMAC_INTEL=y CONFIG_DWMAC_LOONGSON=y CONFIG_STMMAC_PCI=y CONFIG_NET_VENDOR_SUN=y CONFIG_HAPPYMEAL=y CONFIG_SUNGEM=y CONFIG_CASSINI=y CONFIG_NIU=y CONFIG_NET_VENDOR_SYNOPSYS=y CONFIG_DWC_XLGMAC=y CONFIG_DWC_XLGMAC_PCI=y CONFIG_NET_VENDOR_TEHUTI=y CONFIG_TEHUTI=y CONFIG_NET_VENDOR_TI=y CONFIG_TI_CPSW_PHY_SEL=y CONFIG_TLAN=y CONFIG_NET_VENDOR_VERTEXCOM=y CONFIG_MSE102X=y CONFIG_NET_VENDOR_VIA=y CONFIG_VIA_RHINE=y CONFIG_VIA_RHINE_MMIO=y CONFIG_VIA_VELOCITY=y CONFIG_NET_VENDOR_WIZNET=y CONFIG_WIZNET_W5100=y CONFIG_WIZNET_W5300=y # CONFIG_WIZNET_BUS_DIRECT is not set # CONFIG_WIZNET_BUS_INDIRECT is not set CONFIG_WIZNET_BUS_ANY=y CONFIG_WIZNET_W5100_SPI=y CONFIG_NET_VENDOR_XILINX=y CONFIG_XILINX_EMACLITE=y CONFIG_XILINX_AXI_EMAC=y CONFIG_XILINX_LL_TEMAC=y CONFIG_NET_VENDOR_XIRCOM=y CONFIG_PCMCIA_XIRC2PS=y CONFIG_FDDI=y CONFIG_DEFXX=y CONFIG_SKFP=y CONFIG_HIPPI=y CONFIG_ROADRUNNER=y CONFIG_ROADRUNNER_LARGE_RINGS=y CONFIG_NET_SB1000=y CONFIG_PHYLINK=y CONFIG_PHYLIB=y CONFIG_SWPHY=y CONFIG_LED_TRIGGER_PHY=y CONFIG_FIXED_PHY=y CONFIG_SFP=y # # MII PHY device drivers # CONFIG_AMD_PHY=y CONFIG_ADIN_PHY=y CONFIG_ADIN1100_PHY=y CONFIG_AQUANTIA_PHY=y CONFIG_AX88796B_PHY=y CONFIG_BROADCOM_PHY=y CONFIG_BCM54140_PHY=y CONFIG_BCM7XXX_PHY=y CONFIG_BCM84881_PHY=y CONFIG_BCM87XX_PHY=y CONFIG_BCM_NET_PHYLIB=y CONFIG_BCM_NET_PHYPTP=y CONFIG_CICADA_PHY=y CONFIG_CORTINA_PHY=y CONFIG_DAVICOM_PHY=y CONFIG_ICPLUS_PHY=y CONFIG_LXT_PHY=y CONFIG_INTEL_XWAY_PHY=y CONFIG_LSI_ET1011C_PHY=y CONFIG_MARVELL_PHY=y CONFIG_MARVELL_10G_PHY=y CONFIG_MARVELL_88X2222_PHY=y CONFIG_MAXLINEAR_GPHY=y CONFIG_MEDIATEK_GE_PHY=y CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=y CONFIG_MICROCHIP_T1_PHY=y CONFIG_MICROSEMI_PHY=y CONFIG_MOTORCOMM_PHY=y CONFIG_NATIONAL_PHY=y CONFIG_NXP_C45_TJA11XX_PHY=y CONFIG_NXP_TJA11XX_PHY=y CONFIG_AT803X_PHY=y CONFIG_QSEMI_PHY=y CONFIG_REALTEK_PHY=y CONFIG_RENESAS_PHY=y CONFIG_ROCKCHIP_PHY=y CONFIG_SMSC_PHY=y CONFIG_STE10XP=y CONFIG_TERANETICS_PHY=y CONFIG_DP83822_PHY=y CONFIG_DP83TC811_PHY=y CONFIG_DP83848_PHY=y CONFIG_DP83867_PHY=y CONFIG_DP83869_PHY=y CONFIG_DP83TD510_PHY=y CONFIG_VITESSE_PHY=y CONFIG_XILINX_GMII2RGMII=y CONFIG_MICREL_KS8995MA=y CONFIG_PSE_CONTROLLER=y CONFIG_PSE_REGULATOR=y CONFIG_CAN_DEV=y CONFIG_CAN_VCAN=y CONFIG_CAN_VXCAN=y CONFIG_CAN_NETLINK=y CONFIG_CAN_CALC_BITTIMING=y CONFIG_CAN_RX_OFFLOAD=y CONFIG_CAN_CAN327=y CONFIG_CAN_FLEXCAN=y CONFIG_CAN_GRCAN=y CONFIG_CAN_JANZ_ICAN3=y CONFIG_CAN_KVASER_PCIEFD=y CONFIG_CAN_SLCAN=y CONFIG_PCH_CAN=y CONFIG_CAN_C_CAN=y CONFIG_CAN_C_CAN_PLATFORM=y CONFIG_CAN_C_CAN_PCI=y CONFIG_CAN_CC770=y CONFIG_CAN_CC770_ISA=y CONFIG_CAN_CC770_PLATFORM=y CONFIG_CAN_CTUCANFD=y CONFIG_CAN_CTUCANFD_PCI=y CONFIG_CAN_CTUCANFD_PLATFORM=y CONFIG_CAN_IFI_CANFD=y CONFIG_CAN_M_CAN=y CONFIG_CAN_M_CAN_PCI=y CONFIG_CAN_M_CAN_PLATFORM=y CONFIG_CAN_M_CAN_TCAN4X5X=y CONFIG_CAN_PEAK_PCIEFD=y CONFIG_CAN_SJA1000=y CONFIG_CAN_EMS_PCI=y CONFIG_CAN_EMS_PCMCIA=y CONFIG_CAN_F81601=y CONFIG_CAN_KVASER_PCI=y CONFIG_CAN_PEAK_PCI=y CONFIG_CAN_PEAK_PCIEC=y CONFIG_CAN_PEAK_PCMCIA=y CONFIG_CAN_PLX_PCI=y CONFIG_CAN_SJA1000_ISA=y CONFIG_CAN_SJA1000_PLATFORM=y CONFIG_CAN_TSCAN1=y CONFIG_CAN_SOFTING=y CONFIG_CAN_SOFTING_CS=y # # CAN SPI interfaces # CONFIG_CAN_HI311X=y CONFIG_CAN_MCP251X=y CONFIG_CAN_MCP251XFD=y CONFIG_CAN_MCP251XFD_SANITY=y # end of CAN SPI interfaces # # CAN USB interfaces # CONFIG_CAN_8DEV_USB=y CONFIG_CAN_EMS_USB=y CONFIG_CAN_ESD_USB=y CONFIG_CAN_ETAS_ES58X=y CONFIG_CAN_GS_USB=y CONFIG_CAN_KVASER_USB=y CONFIG_CAN_MCBA_USB=y CONFIG_CAN_PEAK_USB=y CONFIG_CAN_UCAN=y # end of CAN USB interfaces CONFIG_CAN_DEBUG_DEVICES=y # # MCTP Device Drivers # CONFIG_MCTP_SERIAL=y CONFIG_MCTP_TRANSPORT_I2C=y # end of MCTP Device Drivers CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y CONFIG_ACPI_MDIO=y CONFIG_MDIO_DEVRES=y CONFIG_MDIO_BITBANG=y CONFIG_MDIO_BCM_UNIMAC=y CONFIG_MDIO_GPIO=y CONFIG_MDIO_HISI_FEMAC=y CONFIG_MDIO_I2C=y CONFIG_MDIO_MVUSB=y CONFIG_MDIO_MSCC_MIIM=y CONFIG_MDIO_IPQ4019=y CONFIG_MDIO_IPQ8064=y # # MDIO Multiplexers # CONFIG_MDIO_BUS_MUX=y CONFIG_MDIO_BUS_MUX_GPIO=y CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y CONFIG_MDIO_BUS_MUX_MMIOREG=y # # PCS device drivers # CONFIG_PCS_XPCS=y CONFIG_PCS_LYNX=y CONFIG_PCS_ALTERA_TSE=y # end of PCS device drivers CONFIG_PLIP=y CONFIG_PPP=y CONFIG_PPP_BSDCOMP=y CONFIG_PPP_DEFLATE=y CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=y CONFIG_PPP_MULTILINK=y CONFIG_PPPOATM=y CONFIG_PPPOE=y CONFIG_PPTP=y CONFIG_PPPOL2TP=y CONFIG_PPP_ASYNC=y CONFIG_PPP_SYNC_TTY=y CONFIG_SLIP=y CONFIG_SLHC=y CONFIG_SLIP_COMPRESSED=y CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y CONFIG_USB_NET_DRIVERS=y CONFIG_USB_CATC=y CONFIG_USB_KAWETH=y CONFIG_USB_PEGASUS=y CONFIG_USB_RTL8150=y CONFIG_USB_RTL8152=y CONFIG_USB_LAN78XX=y CONFIG_USB_USBNET=y CONFIG_USB_NET_AX8817X=y CONFIG_USB_NET_AX88179_178A=y CONFIG_USB_NET_CDCETHER=y CONFIG_USB_NET_CDC_EEM=y CONFIG_USB_NET_CDC_NCM=y CONFIG_USB_NET_HUAWEI_CDC_NCM=y CONFIG_USB_NET_CDC_MBIM=y CONFIG_USB_NET_DM9601=y CONFIG_USB_NET_SR9700=y CONFIG_USB_NET_SR9800=y CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC95XX=y CONFIG_USB_NET_GL620A=y CONFIG_USB_NET_NET1080=y CONFIG_USB_NET_PLUSB=y CONFIG_USB_NET_MCS7830=y CONFIG_USB_NET_RNDIS_HOST=y CONFIG_USB_NET_CDC_SUBSET_ENABLE=y CONFIG_USB_NET_CDC_SUBSET=y CONFIG_USB_ALI_M5632=y CONFIG_USB_AN2720=y CONFIG_USB_BELKIN=y CONFIG_USB_ARMLINUX=y CONFIG_USB_EPSON2888=y CONFIG_USB_KC2190=y CONFIG_USB_NET_ZAURUS=y CONFIG_USB_NET_CX82310_ETH=y CONFIG_USB_NET_KALMIA=y CONFIG_USB_NET_QMI_WWAN=y CONFIG_USB_HSO=y CONFIG_USB_NET_INT51X1=y CONFIG_USB_CDC_PHONET=y CONFIG_USB_IPHETH=y CONFIG_USB_SIERRA_NET=y CONFIG_USB_VL600=y CONFIG_USB_NET_CH9200=y CONFIG_USB_NET_AQC111=y CONFIG_USB_RTL8153_ECM=y CONFIG_WLAN=y CONFIG_WLAN_VENDOR_ADMTEK=y CONFIG_ADM8211=y CONFIG_ATH_COMMON=y CONFIG_WLAN_VENDOR_ATH=y CONFIG_ATH_DEBUG=y CONFIG_ATH_TRACEPOINTS=y CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS=y CONFIG_ATH_REG_DYNAMIC_USER_CERT_TESTING=y CONFIG_ATH5K=y CONFIG_ATH5K_DEBUG=y CONFIG_ATH5K_TRACER=y CONFIG_ATH5K_PCI=y CONFIG_ATH5K_TEST_CHANNELS=y CONFIG_ATH9K_HW=y CONFIG_ATH9K_COMMON=y CONFIG_ATH9K_COMMON_DEBUG=y CONFIG_ATH9K_DFS_DEBUGFS=y CONFIG_ATH9K_BTCOEX_SUPPORT=y CONFIG_ATH9K=y CONFIG_ATH9K_PCI=y CONFIG_ATH9K_AHB=y CONFIG_ATH9K_DEBUGFS=y CONFIG_ATH9K_STATION_STATISTICS=y CONFIG_ATH9K_TX99=y CONFIG_ATH9K_DFS_CERTIFIED=y CONFIG_ATH9K_DYNACK=y CONFIG_ATH9K_WOW=y CONFIG_ATH9K_RFKILL=y CONFIG_ATH9K_CHANNEL_CONTEXT=y CONFIG_ATH9K_PCOEM=y CONFIG_ATH9K_PCI_NO_EEPROM=y CONFIG_ATH9K_HTC=y CONFIG_ATH9K_HTC_DEBUGFS=y CONFIG_ATH9K_HWRNG=y CONFIG_ATH9K_COMMON_SPECTRAL=y CONFIG_CARL9170=y CONFIG_CARL9170_LEDS=y CONFIG_CARL9170_DEBUGFS=y CONFIG_CARL9170_WPC=y CONFIG_CARL9170_HWRNG=y CONFIG_ATH6KL=y CONFIG_ATH6KL_SDIO=y CONFIG_ATH6KL_USB=y CONFIG_ATH6KL_DEBUG=y CONFIG_ATH6KL_TRACING=y CONFIG_ATH6KL_REGDOMAIN=y CONFIG_AR5523=y CONFIG_WIL6210=y CONFIG_WIL6210_ISR_COR=y CONFIG_WIL6210_TRACING=y CONFIG_WIL6210_DEBUGFS=y CONFIG_ATH10K=y CONFIG_ATH10K_CE=y CONFIG_ATH10K_PCI=y CONFIG_ATH10K_AHB=y CONFIG_ATH10K_SDIO=y CONFIG_ATH10K_USB=y CONFIG_ATH10K_DEBUG=y CONFIG_ATH10K_DEBUGFS=y CONFIG_ATH10K_SPECTRAL=y CONFIG_ATH10K_TRACING=y CONFIG_ATH10K_DFS_CERTIFIED=y CONFIG_WCN36XX=y CONFIG_WCN36XX_DEBUGFS=y CONFIG_ATH11K=y CONFIG_ATH11K_AHB=y CONFIG_ATH11K_PCI=y CONFIG_ATH11K_DEBUG=y CONFIG_ATH11K_DEBUGFS=y CONFIG_ATH11K_TRACING=y CONFIG_ATH11K_SPECTRAL=y CONFIG_WLAN_VENDOR_ATMEL=y CONFIG_ATMEL=y CONFIG_PCI_ATMEL=y CONFIG_PCMCIA_ATMEL=y CONFIG_AT76C50X_USB=y CONFIG_WLAN_VENDOR_BROADCOM=y CONFIG_B43=y CONFIG_B43_BCMA=y CONFIG_B43_SSB=y CONFIG_B43_BUSES_BCMA_AND_SSB=y # CONFIG_B43_BUSES_BCMA is not set # CONFIG_B43_BUSES_SSB is not set CONFIG_B43_PCI_AUTOSELECT=y CONFIG_B43_PCICORE_AUTOSELECT=y CONFIG_B43_SDIO=y CONFIG_B43_BCMA_PIO=y CONFIG_B43_PIO=y CONFIG_B43_PHY_G=y CONFIG_B43_PHY_N=y CONFIG_B43_PHY_LP=y CONFIG_B43_PHY_HT=y CONFIG_B43_LEDS=y CONFIG_B43_HWRNG=y CONFIG_B43_DEBUG=y CONFIG_B43LEGACY=y CONFIG_B43LEGACY_PCI_AUTOSELECT=y CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y CONFIG_B43LEGACY_LEDS=y CONFIG_B43LEGACY_HWRNG=y CONFIG_B43LEGACY_DEBUG=y CONFIG_B43LEGACY_DMA=y CONFIG_B43LEGACY_PIO=y CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y # CONFIG_B43LEGACY_DMA_MODE is not set # CONFIG_B43LEGACY_PIO_MODE is not set CONFIG_BRCMUTIL=y CONFIG_BRCMSMAC=y CONFIG_BRCMSMAC_LEDS=y CONFIG_BRCMFMAC=y CONFIG_BRCMFMAC_PROTO_BCDC=y CONFIG_BRCMFMAC_PROTO_MSGBUF=y CONFIG_BRCMFMAC_SDIO=y CONFIG_BRCMFMAC_USB=y CONFIG_BRCMFMAC_PCIE=y CONFIG_BRCM_TRACING=y CONFIG_BRCMDBG=y CONFIG_WLAN_VENDOR_CISCO=y CONFIG_AIRO=y CONFIG_AIRO_CS=y CONFIG_WLAN_VENDOR_INTEL=y CONFIG_IPW2100=y CONFIG_IPW2100_MONITOR=y CONFIG_IPW2100_DEBUG=y CONFIG_IPW2200=y CONFIG_IPW2200_MONITOR=y CONFIG_IPW2200_RADIOTAP=y CONFIG_IPW2200_PROMISCUOUS=y CONFIG_IPW2200_QOS=y CONFIG_IPW2200_DEBUG=y CONFIG_LIBIPW=y CONFIG_LIBIPW_DEBUG=y CONFIG_IWLEGACY=y CONFIG_IWL4965=y CONFIG_IWL3945=y # # iwl3945 / iwl4965 Debugging Options # CONFIG_IWLEGACY_DEBUG=y CONFIG_IWLEGACY_DEBUGFS=y # end of iwl3945 / iwl4965 Debugging Options CONFIG_IWLWIFI=y CONFIG_IWLWIFI_LEDS=y CONFIG_IWLDVM=y CONFIG_IWLMVM=y # # Debugging Options # CONFIG_IWLWIFI_DEBUG=y CONFIG_IWLWIFI_DEBUGFS=y CONFIG_IWLWIFI_DEVICE_TRACING=y # end of Debugging Options CONFIG_WLAN_VENDOR_INTERSIL=y CONFIG_HOSTAP=y CONFIG_HOSTAP_FIRMWARE=y CONFIG_HOSTAP_FIRMWARE_NVRAM=y CONFIG_HOSTAP_PLX=y CONFIG_HOSTAP_PCI=y CONFIG_HOSTAP_CS=y CONFIG_HERMES=y CONFIG_HERMES_PRISM=y CONFIG_HERMES_CACHE_FW_ON_INIT=y CONFIG_PLX_HERMES=y CONFIG_TMD_HERMES=y CONFIG_NORTEL_HERMES=y CONFIG_PCI_HERMES=y CONFIG_PCMCIA_HERMES=y CONFIG_PCMCIA_SPECTRUM=y CONFIG_ORINOCO_USB=y CONFIG_P54_COMMON=y CONFIG_P54_USB=y CONFIG_P54_PCI=y CONFIG_P54_SPI=y CONFIG_P54_SPI_DEFAULT_EEPROM=y CONFIG_P54_LEDS=y CONFIG_WLAN_VENDOR_MARVELL=y CONFIG_LIBERTAS=y CONFIG_LIBERTAS_USB=y CONFIG_LIBERTAS_CS=y CONFIG_LIBERTAS_SDIO=y CONFIG_LIBERTAS_SPI=y CONFIG_LIBERTAS_DEBUG=y CONFIG_LIBERTAS_MESH=y CONFIG_LIBERTAS_THINFIRM=y CONFIG_LIBERTAS_THINFIRM_DEBUG=y CONFIG_LIBERTAS_THINFIRM_USB=y CONFIG_MWIFIEX=y CONFIG_MWIFIEX_SDIO=y CONFIG_MWIFIEX_PCIE=y CONFIG_MWIFIEX_USB=y CONFIG_MWL8K=y CONFIG_WLAN_VENDOR_MEDIATEK=y CONFIG_MT7601U=y CONFIG_MT76_CORE=y CONFIG_MT76_LEDS=y CONFIG_MT76_USB=y CONFIG_MT76_SDIO=y CONFIG_MT76x02_LIB=y CONFIG_MT76x02_USB=y CONFIG_MT76_CONNAC_LIB=y CONFIG_MT76x0_COMMON=y CONFIG_MT76x0U=y CONFIG_MT76x0E=y CONFIG_MT76x2_COMMON=y CONFIG_MT76x2E=y CONFIG_MT76x2U=y CONFIG_MT7603E=y CONFIG_MT7615_COMMON=y CONFIG_MT7615E=y CONFIG_MT7663_USB_SDIO_COMMON=y CONFIG_MT7663U=y CONFIG_MT7663S=y CONFIG_MT7915E=y CONFIG_MT7921_COMMON=y CONFIG_MT7921E=y CONFIG_MT7921S=y CONFIG_MT7921U=y CONFIG_WLAN_VENDOR_MICROCHIP=y CONFIG_WILC1000=y CONFIG_WILC1000_SDIO=y CONFIG_WILC1000_SPI=y CONFIG_WILC1000_HW_OOB_INTR=y CONFIG_WLAN_VENDOR_PURELIFI=y CONFIG_PLFXLC=y CONFIG_WLAN_VENDOR_RALINK=y CONFIG_RT2X00=y CONFIG_RT2400PCI=y CONFIG_RT2500PCI=y CONFIG_RT61PCI=y CONFIG_RT2800PCI=y CONFIG_RT2800PCI_RT33XX=y CONFIG_RT2800PCI_RT35XX=y CONFIG_RT2800PCI_RT53XX=y CONFIG_RT2800PCI_RT3290=y CONFIG_RT2500USB=y CONFIG_RT73USB=y CONFIG_RT2800USB=y CONFIG_RT2800USB_RT33XX=y CONFIG_RT2800USB_RT35XX=y CONFIG_RT2800USB_RT3573=y CONFIG_RT2800USB_RT53XX=y CONFIG_RT2800USB_RT55XX=y CONFIG_RT2800USB_UNKNOWN=y CONFIG_RT2800_LIB=y CONFIG_RT2800_LIB_MMIO=y CONFIG_RT2X00_LIB_MMIO=y CONFIG_RT2X00_LIB_PCI=y CONFIG_RT2X00_LIB_USB=y CONFIG_RT2X00_LIB=y CONFIG_RT2X00_LIB_FIRMWARE=y CONFIG_RT2X00_LIB_CRYPTO=y CONFIG_RT2X00_LIB_LEDS=y CONFIG_RT2X00_LIB_DEBUGFS=y CONFIG_RT2X00_DEBUG=y CONFIG_WLAN_VENDOR_REALTEK=y CONFIG_RTL8180=y CONFIG_RTL8187=y CONFIG_RTL8187_LEDS=y CONFIG_RTL_CARDS=y CONFIG_RTL8192CE=y CONFIG_RTL8192SE=y CONFIG_RTL8192DE=y CONFIG_RTL8723AE=y CONFIG_RTL8723BE=y CONFIG_RTL8188EE=y CONFIG_RTL8192EE=y CONFIG_RTL8821AE=y CONFIG_RTL8192CU=y CONFIG_RTLWIFI=y CONFIG_RTLWIFI_PCI=y CONFIG_RTLWIFI_USB=y CONFIG_RTLWIFI_DEBUG=y CONFIG_RTL8192C_COMMON=y CONFIG_RTL8723_COMMON=y CONFIG_RTLBTCOEXIST=y CONFIG_RTL8XXXU=y CONFIG_RTL8XXXU_UNTESTED=y CONFIG_RTW88=y CONFIG_RTW88_CORE=y CONFIG_RTW88_PCI=y CONFIG_RTW88_8822B=y CONFIG_RTW88_8822C=y CONFIG_RTW88_8723D=y CONFIG_RTW88_8821C=y CONFIG_RTW88_8822BE=y CONFIG_RTW88_8822CE=y CONFIG_RTW88_8723DE=y CONFIG_RTW88_8821CE=y CONFIG_RTW88_DEBUG=y CONFIG_RTW88_DEBUGFS=y CONFIG_RTW89=y CONFIG_RTW89_CORE=y CONFIG_RTW89_PCI=y CONFIG_RTW89_8852A=y CONFIG_RTW89_8852C=y CONFIG_RTW89_8852AE=y CONFIG_RTW89_8852CE=y CONFIG_RTW89_DEBUG=y CONFIG_RTW89_DEBUGMSG=y CONFIG_RTW89_DEBUGFS=y CONFIG_WLAN_VENDOR_RSI=y CONFIG_RSI_91X=y CONFIG_RSI_DEBUGFS=y CONFIG_RSI_SDIO=y CONFIG_RSI_USB=y CONFIG_RSI_COEX=y CONFIG_WLAN_VENDOR_SILABS=y CONFIG_WFX=y CONFIG_WLAN_VENDOR_ST=y CONFIG_CW1200=y CONFIG_CW1200_WLAN_SDIO=y CONFIG_CW1200_WLAN_SPI=y CONFIG_WLAN_VENDOR_TI=y CONFIG_WL1251=y CONFIG_WL1251_SPI=y CONFIG_WL1251_SDIO=y CONFIG_WL12XX=y CONFIG_WL18XX=y CONFIG_WLCORE=y CONFIG_WLCORE_SPI=y CONFIG_WLCORE_SDIO=y CONFIG_WILINK_PLATFORM_DATA=y CONFIG_WLAN_VENDOR_ZYDAS=y CONFIG_USB_ZD1201=y CONFIG_ZD1211RW=y CONFIG_ZD1211RW_DEBUG=y CONFIG_WLAN_VENDOR_QUANTENNA=y CONFIG_QTNFMAC=y CONFIG_QTNFMAC_PCIE=y CONFIG_PCMCIA_RAYCS=y CONFIG_PCMCIA_WL3501=y CONFIG_MAC80211_HWSIM=y CONFIG_USB_NET_RNDIS_WLAN=y CONFIG_VIRT_WIFI=y CONFIG_WAN=y CONFIG_HDLC=y CONFIG_HDLC_RAW=y CONFIG_HDLC_RAW_ETH=y CONFIG_HDLC_CISCO=y CONFIG_HDLC_FR=y CONFIG_HDLC_PPP=y CONFIG_HDLC_X25=y CONFIG_PCI200SYN=y CONFIG_WANXL=y CONFIG_PC300TOO=y CONFIG_N2=y CONFIG_C101=y CONFIG_FARSYNC=y CONFIG_LAPBETHER=y CONFIG_IEEE802154_DRIVERS=y CONFIG_IEEE802154_FAKELB=y CONFIG_IEEE802154_AT86RF230=y CONFIG_IEEE802154_MRF24J40=y CONFIG_IEEE802154_CC2520=y CONFIG_IEEE802154_ATUSB=y CONFIG_IEEE802154_ADF7242=y CONFIG_IEEE802154_CA8210=y CONFIG_IEEE802154_CA8210_DEBUGFS=y CONFIG_IEEE802154_MCR20A=y CONFIG_IEEE802154_HWSIM=y # # Wireless WAN # CONFIG_WWAN=y CONFIG_WWAN_DEBUGFS=y CONFIG_WWAN_HWSIM=y CONFIG_MHI_WWAN_CTRL=y CONFIG_MHI_WWAN_MBIM=y CONFIG_RPMSG_WWAN_CTRL=y CONFIG_IOSM=y CONFIG_MTK_T7XX=y # end of Wireless WAN CONFIG_VMXNET3=y CONFIG_FUJITSU_ES=y CONFIG_USB4_NET=y CONFIG_HYPERV_NET=y CONFIG_NETDEVSIM=y CONFIG_NET_FAILOVER=y CONFIG_NETDEV_LEGACY_INIT=y CONFIG_ISDN=y CONFIG_ISDN_CAPI=y CONFIG_CAPI_TRACE=y CONFIG_ISDN_CAPI_MIDDLEWARE=y CONFIG_MISDN=y CONFIG_MISDN_DSP=y CONFIG_MISDN_L1OIP=y # # mISDN hardware drivers # CONFIG_MISDN_HFCPCI=y CONFIG_MISDN_HFCMULTI=y CONFIG_MISDN_HFCUSB=y CONFIG_MISDN_AVMFRITZ=y CONFIG_MISDN_SPEEDFAX=y CONFIG_MISDN_INFINEON=y CONFIG_MISDN_W6692=y CONFIG_MISDN_NETJET=y CONFIG_MISDN_HDLC=y CONFIG_MISDN_IPAC=y CONFIG_MISDN_ISAR=y # # Input device support # CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y CONFIG_INPUT_SPARSEKMAP=y CONFIG_INPUT_MATRIXKMAP=y CONFIG_INPUT_VIVALDIFMAP=y # # Userland interfaces # CONFIG_INPUT_MOUSEDEV=y CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 CONFIG_INPUT_JOYDEV=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=y # # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y CONFIG_KEYBOARD_ADC=y CONFIG_KEYBOARD_ADP5520=y CONFIG_KEYBOARD_ADP5588=y CONFIG_KEYBOARD_ADP5589=y CONFIG_KEYBOARD_APPLESPI=y CONFIG_KEYBOARD_ATKBD=y CONFIG_KEYBOARD_QT1050=y CONFIG_KEYBOARD_QT1070=y CONFIG_KEYBOARD_QT2160=y CONFIG_KEYBOARD_DLINK_DIR685=y CONFIG_KEYBOARD_LKKBD=y CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_GPIO_POLLED=y CONFIG_KEYBOARD_TCA6416=y CONFIG_KEYBOARD_TCA8418=y CONFIG_KEYBOARD_MATRIX=y CONFIG_KEYBOARD_LM8323=y CONFIG_KEYBOARD_LM8333=y CONFIG_KEYBOARD_MAX7359=y CONFIG_KEYBOARD_MCS=y CONFIG_KEYBOARD_MPR121=y CONFIG_KEYBOARD_NEWTON=y CONFIG_KEYBOARD_OPENCORES=y CONFIG_KEYBOARD_PINEPHONE=y CONFIG_KEYBOARD_SAMSUNG=y CONFIG_KEYBOARD_GOLDFISH_EVENTS=y CONFIG_KEYBOARD_STOWAWAY=y CONFIG_KEYBOARD_SUNKBD=y CONFIG_KEYBOARD_STMPE=y CONFIG_KEYBOARD_IQS62X=y CONFIG_KEYBOARD_OMAP4=y CONFIG_KEYBOARD_TC3589X=y CONFIG_KEYBOARD_TM2_TOUCHKEY=y CONFIG_KEYBOARD_TWL4030=y CONFIG_KEYBOARD_XTKBD=y CONFIG_KEYBOARD_CROS_EC=y CONFIG_KEYBOARD_CAP11XX=y CONFIG_KEYBOARD_BCM=y CONFIG_KEYBOARD_MTK_PMIC=y CONFIG_KEYBOARD_CYPRESS_SF=y CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2_ALPS=y CONFIG_MOUSE_PS2_BYD=y CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y CONFIG_MOUSE_PS2_CYPRESS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y CONFIG_MOUSE_PS2_ELANTECH=y CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y CONFIG_MOUSE_PS2_SENTELIC=y CONFIG_MOUSE_PS2_TOUCHKIT=y CONFIG_MOUSE_PS2_OLPC=y CONFIG_MOUSE_PS2_FOCALTECH=y CONFIG_MOUSE_PS2_VMMOUSE=y CONFIG_MOUSE_PS2_SMBUS=y CONFIG_MOUSE_SERIAL=y CONFIG_MOUSE_APPLETOUCH=y CONFIG_MOUSE_BCM5974=y CONFIG_MOUSE_CYAPA=y CONFIG_MOUSE_ELAN_I2C=y CONFIG_MOUSE_ELAN_I2C_I2C=y CONFIG_MOUSE_ELAN_I2C_SMBUS=y CONFIG_MOUSE_INPORT=y CONFIG_MOUSE_ATIXL=y CONFIG_MOUSE_LOGIBM=y CONFIG_MOUSE_PC110PAD=y CONFIG_MOUSE_VSXXXAA=y CONFIG_MOUSE_GPIO=y CONFIG_MOUSE_SYNAPTICS_I2C=y CONFIG_MOUSE_SYNAPTICS_USB=y CONFIG_INPUT_JOYSTICK=y CONFIG_JOYSTICK_ANALOG=y CONFIG_JOYSTICK_A3D=y CONFIG_JOYSTICK_ADC=y CONFIG_JOYSTICK_ADI=y CONFIG_JOYSTICK_COBRA=y CONFIG_JOYSTICK_GF2K=y CONFIG_JOYSTICK_GRIP=y CONFIG_JOYSTICK_GRIP_MP=y CONFIG_JOYSTICK_GUILLEMOT=y CONFIG_JOYSTICK_INTERACT=y CONFIG_JOYSTICK_SIDEWINDER=y CONFIG_JOYSTICK_TMDC=y CONFIG_JOYSTICK_IFORCE=y CONFIG_JOYSTICK_IFORCE_USB=y CONFIG_JOYSTICK_IFORCE_232=y CONFIG_JOYSTICK_WARRIOR=y CONFIG_JOYSTICK_MAGELLAN=y CONFIG_JOYSTICK_SPACEORB=y CONFIG_JOYSTICK_SPACEBALL=y CONFIG_JOYSTICK_STINGER=y CONFIG_JOYSTICK_TWIDJOY=y CONFIG_JOYSTICK_ZHENHUA=y CONFIG_JOYSTICK_DB9=y CONFIG_JOYSTICK_GAMECON=y CONFIG_JOYSTICK_TURBOGRAFX=y CONFIG_JOYSTICK_AS5011=y CONFIG_JOYSTICK_JOYDUMP=y CONFIG_JOYSTICK_XPAD=y CONFIG_JOYSTICK_XPAD_FF=y CONFIG_JOYSTICK_XPAD_LEDS=y CONFIG_JOYSTICK_WALKERA0701=y CONFIG_JOYSTICK_PSXPAD_SPI=y CONFIG_JOYSTICK_PSXPAD_SPI_FF=y CONFIG_JOYSTICK_PXRC=y CONFIG_JOYSTICK_QWIIC=y CONFIG_JOYSTICK_FSIA6B=y CONFIG_JOYSTICK_SENSEHAT=y CONFIG_INPUT_TABLET=y CONFIG_TABLET_USB_ACECAD=y CONFIG_TABLET_USB_AIPTEK=y CONFIG_TABLET_USB_HANWANG=y CONFIG_TABLET_USB_KBTAB=y CONFIG_TABLET_USB_PEGASUS=y CONFIG_TABLET_SERIAL_WACOM4=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_88PM860X=y CONFIG_TOUCHSCREEN_ADS7846=y CONFIG_TOUCHSCREEN_AD7877=y CONFIG_TOUCHSCREEN_AD7879=y CONFIG_TOUCHSCREEN_AD7879_I2C=y CONFIG_TOUCHSCREEN_AD7879_SPI=y CONFIG_TOUCHSCREEN_ADC=y CONFIG_TOUCHSCREEN_AR1021_I2C=y CONFIG_TOUCHSCREEN_ATMEL_MXT=y CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y CONFIG_TOUCHSCREEN_AUO_PIXCIR=y CONFIG_TOUCHSCREEN_BU21013=y CONFIG_TOUCHSCREEN_BU21029=y CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=y CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=y CONFIG_TOUCHSCREEN_CY8CTMA140=y CONFIG_TOUCHSCREEN_CY8CTMG110=y CONFIG_TOUCHSCREEN_CYTTSP_CORE=y CONFIG_TOUCHSCREEN_CYTTSP_I2C=y CONFIG_TOUCHSCREEN_CYTTSP_SPI=y CONFIG_TOUCHSCREEN_CYTTSP4_CORE=y CONFIG_TOUCHSCREEN_CYTTSP4_I2C=y CONFIG_TOUCHSCREEN_CYTTSP4_SPI=y CONFIG_TOUCHSCREEN_DA9034=y CONFIG_TOUCHSCREEN_DA9052=y CONFIG_TOUCHSCREEN_DYNAPRO=y CONFIG_TOUCHSCREEN_HAMPSHIRE=y CONFIG_TOUCHSCREEN_EETI=y CONFIG_TOUCHSCREEN_EGALAX=y CONFIG_TOUCHSCREEN_EGALAX_SERIAL=y CONFIG_TOUCHSCREEN_EXC3000=y CONFIG_TOUCHSCREEN_FUJITSU=y CONFIG_TOUCHSCREEN_GOODIX=y CONFIG_TOUCHSCREEN_HIDEEP=y CONFIG_TOUCHSCREEN_HYCON_HY46XX=y CONFIG_TOUCHSCREEN_ILI210X=y CONFIG_TOUCHSCREEN_ILITEK=y CONFIG_TOUCHSCREEN_S6SY761=y CONFIG_TOUCHSCREEN_GUNZE=y CONFIG_TOUCHSCREEN_EKTF2127=y CONFIG_TOUCHSCREEN_ELAN=y CONFIG_TOUCHSCREEN_ELO=y CONFIG_TOUCHSCREEN_WACOM_W8001=y CONFIG_TOUCHSCREEN_WACOM_I2C=y CONFIG_TOUCHSCREEN_MAX11801=y CONFIG_TOUCHSCREEN_MCS5000=y CONFIG_TOUCHSCREEN_MMS114=y CONFIG_TOUCHSCREEN_MELFAS_MIP4=y CONFIG_TOUCHSCREEN_MSG2638=y CONFIG_TOUCHSCREEN_MTOUCH=y CONFIG_TOUCHSCREEN_IMAGIS=y CONFIG_TOUCHSCREEN_IMX6UL_TSC=y CONFIG_TOUCHSCREEN_INEXIO=y CONFIG_TOUCHSCREEN_MK712=y CONFIG_TOUCHSCREEN_HTCPEN=y CONFIG_TOUCHSCREEN_PENMOUNT=y CONFIG_TOUCHSCREEN_EDT_FT5X06=y CONFIG_TOUCHSCREEN_TOUCHRIGHT=y CONFIG_TOUCHSCREEN_TOUCHWIN=y CONFIG_TOUCHSCREEN_TI_AM335X_TSC=y CONFIG_TOUCHSCREEN_UCB1400=y CONFIG_TOUCHSCREEN_PIXCIR=y CONFIG_TOUCHSCREEN_WDT87XX_I2C=y CONFIG_TOUCHSCREEN_WM831X=y CONFIG_TOUCHSCREEN_WM97XX=y CONFIG_TOUCHSCREEN_WM9705=y CONFIG_TOUCHSCREEN_WM9712=y CONFIG_TOUCHSCREEN_WM9713=y CONFIG_TOUCHSCREEN_USB_COMPOSITE=y CONFIG_TOUCHSCREEN_MC13783=y CONFIG_TOUCHSCREEN_USB_EGALAX=y CONFIG_TOUCHSCREEN_USB_PANJIT=y CONFIG_TOUCHSCREEN_USB_3M=y CONFIG_TOUCHSCREEN_USB_ITM=y CONFIG_TOUCHSCREEN_USB_ETURBO=y CONFIG_TOUCHSCREEN_USB_GUNZE=y CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y CONFIG_TOUCHSCREEN_USB_IRTOUCH=y CONFIG_TOUCHSCREEN_USB_IDEALTEK=y CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y CONFIG_TOUCHSCREEN_USB_GOTOP=y CONFIG_TOUCHSCREEN_USB_JASTEC=y CONFIG_TOUCHSCREEN_USB_ELO=y CONFIG_TOUCHSCREEN_USB_E2I=y CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y CONFIG_TOUCHSCREEN_USB_NEXIO=y CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y CONFIG_TOUCHSCREEN_TOUCHIT213=y CONFIG_TOUCHSCREEN_TSC_SERIO=y CONFIG_TOUCHSCREEN_TSC200X_CORE=y CONFIG_TOUCHSCREEN_TSC2004=y CONFIG_TOUCHSCREEN_TSC2005=y CONFIG_TOUCHSCREEN_TSC2007=y CONFIG_TOUCHSCREEN_TSC2007_IIO=y CONFIG_TOUCHSCREEN_PCAP=y CONFIG_TOUCHSCREEN_RM_TS=y CONFIG_TOUCHSCREEN_SILEAD=y CONFIG_TOUCHSCREEN_SIS_I2C=y CONFIG_TOUCHSCREEN_ST1232=y CONFIG_TOUCHSCREEN_STMFTS=y CONFIG_TOUCHSCREEN_STMPE=y CONFIG_TOUCHSCREEN_SUR40=y CONFIG_TOUCHSCREEN_SURFACE3_SPI=y CONFIG_TOUCHSCREEN_SX8654=y CONFIG_TOUCHSCREEN_TPS6507X=y CONFIG_TOUCHSCREEN_ZET6223=y CONFIG_TOUCHSCREEN_ZFORCE=y CONFIG_TOUCHSCREEN_COLIBRI_VF50=y CONFIG_TOUCHSCREEN_ROHM_BU21023=y CONFIG_TOUCHSCREEN_IQS5XX=y CONFIG_TOUCHSCREEN_ZINITIX=y CONFIG_INPUT_MISC=y CONFIG_INPUT_88PM860X_ONKEY=y CONFIG_INPUT_88PM80X_ONKEY=y CONFIG_INPUT_AD714X=y CONFIG_INPUT_AD714X_I2C=y CONFIG_INPUT_AD714X_SPI=y CONFIG_INPUT_ARIZONA_HAPTICS=y CONFIG_INPUT_ATC260X_ONKEY=y CONFIG_INPUT_ATMEL_CAPTOUCH=y CONFIG_INPUT_BMA150=y CONFIG_INPUT_E3X0_BUTTON=y CONFIG_INPUT_PCSPKR=y CONFIG_INPUT_MAX77650_ONKEY=y CONFIG_INPUT_MAX77693_HAPTIC=y CONFIG_INPUT_MAX8925_ONKEY=y CONFIG_INPUT_MAX8997_HAPTIC=y CONFIG_INPUT_MC13783_PWRBUTTON=y CONFIG_INPUT_MMA8450=y CONFIG_INPUT_APANEL=y CONFIG_INPUT_GPIO_BEEPER=y CONFIG_INPUT_GPIO_DECODER=y CONFIG_INPUT_GPIO_VIBRA=y CONFIG_INPUT_CPCAP_PWRBUTTON=y CONFIG_INPUT_WISTRON_BTNS=y CONFIG_INPUT_ATLAS_BTNS=y CONFIG_INPUT_ATI_REMOTE2=y CONFIG_INPUT_KEYSPAN_REMOTE=y CONFIG_INPUT_KXTJ9=y CONFIG_INPUT_POWERMATE=y CONFIG_INPUT_YEALINK=y CONFIG_INPUT_CM109=y CONFIG_INPUT_REGULATOR_HAPTIC=y CONFIG_INPUT_RETU_PWRBUTTON=y CONFIG_INPUT_TPS65218_PWRBUTTON=y CONFIG_INPUT_AXP20X_PEK=y CONFIG_INPUT_TWL4030_PWRBUTTON=y CONFIG_INPUT_TWL4030_VIBRA=y CONFIG_INPUT_TWL6040_VIBRA=y CONFIG_INPUT_UINPUT=y CONFIG_INPUT_PALMAS_PWRBUTTON=y CONFIG_INPUT_PCF50633_PMU=y CONFIG_INPUT_PCF8574=y CONFIG_INPUT_PWM_BEEPER=y CONFIG_INPUT_PWM_VIBRA=y CONFIG_INPUT_RK805_PWRKEY=y CONFIG_INPUT_GPIO_ROTARY_ENCODER=y CONFIG_INPUT_DA7280_HAPTICS=y CONFIG_INPUT_DA9052_ONKEY=y CONFIG_INPUT_DA9055_ONKEY=y CONFIG_INPUT_DA9063_ONKEY=y CONFIG_INPUT_WM831X_ON=y CONFIG_INPUT_PCAP=y CONFIG_INPUT_ADXL34X=y CONFIG_INPUT_ADXL34X_I2C=y CONFIG_INPUT_ADXL34X_SPI=y CONFIG_INPUT_IBM_PANEL=y CONFIG_INPUT_IMS_PCU=y CONFIG_INPUT_IQS269A=y CONFIG_INPUT_IQS626A=y CONFIG_INPUT_IQS7222=y CONFIG_INPUT_CMA3000=y CONFIG_INPUT_CMA3000_I2C=y CONFIG_INPUT_IDEAPAD_SLIDEBAR=y CONFIG_INPUT_SOC_BUTTON_ARRAY=y CONFIG_INPUT_DRV260X_HAPTICS=y CONFIG_INPUT_DRV2665_HAPTICS=y CONFIG_INPUT_DRV2667_HAPTICS=y CONFIG_INPUT_RAVE_SP_PWRBUTTON=y CONFIG_INPUT_RT5120_PWRKEY=y CONFIG_INPUT_STPMIC1_ONKEY=y CONFIG_RMI4_CORE=y CONFIG_RMI4_I2C=y CONFIG_RMI4_SPI=y CONFIG_RMI4_SMB=y CONFIG_RMI4_F03=y CONFIG_RMI4_F03_SERIO=y CONFIG_RMI4_2D_SENSOR=y CONFIG_RMI4_F11=y CONFIG_RMI4_F12=y CONFIG_RMI4_F30=y CONFIG_RMI4_F34=y CONFIG_RMI4_F3A=y CONFIG_RMI4_F54=y CONFIG_RMI4_F55=y # # Hardware I/O ports # CONFIG_SERIO=y CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y CONFIG_SERIO_I8042=y CONFIG_SERIO_SERPORT=y CONFIG_SERIO_CT82C710=y CONFIG_SERIO_PARKBD=y CONFIG_SERIO_PCIPS2=y CONFIG_SERIO_LIBPS2=y CONFIG_SERIO_RAW=y CONFIG_SERIO_ALTERA_PS2=y CONFIG_SERIO_PS2MULT=y CONFIG_SERIO_ARC_PS2=y CONFIG_SERIO_APBPS2=y CONFIG_HYPERV_KEYBOARD=y CONFIG_SERIO_GPIO_PS2=y CONFIG_USERIO=y CONFIG_GAMEPORT=y CONFIG_GAMEPORT_NS558=y CONFIG_GAMEPORT_L4=y CONFIG_GAMEPORT_EMU10K1=y CONFIG_GAMEPORT_FM801=y # end of Hardware I/O ports # end of Input device support # # Character devices # CONFIG_TTY=y CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_VT_CONSOLE_SLEEP=y CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 CONFIG_LDISC_AUTOLOAD=y # # Serial drivers # CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_PNP=y CONFIG_SERIAL_8250_16550A_VARIANTS=y CONFIG_SERIAL_8250_FINTEK=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DMA=y CONFIG_SERIAL_8250_PCI=y CONFIG_SERIAL_8250_EXAR=y CONFIG_SERIAL_8250_CS=y CONFIG_SERIAL_8250_MEN_MCB=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_FOURPORT=y CONFIG_SERIAL_8250_ACCENT=y CONFIG_SERIAL_8250_BOCA=y CONFIG_SERIAL_8250_EXAR_ST16C554=y CONFIG_SERIAL_8250_HUB6=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_8250_RT288X=y CONFIG_SERIAL_8250_LPSS=y CONFIG_SERIAL_8250_MID=y CONFIG_SERIAL_8250_PERICOM=y CONFIG_SERIAL_OF_PLATFORM=y # # Non-8250 serial port support # CONFIG_SERIAL_KGDB_NMI=y CONFIG_SERIAL_MAX3100=y CONFIG_SERIAL_MAX310X=y CONFIG_SERIAL_UARTLITE=y CONFIG_SERIAL_UARTLITE_CONSOLE=y CONFIG_SERIAL_UARTLITE_NR_UARTS=1 CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_CONSOLE_POLL=y CONFIG_SERIAL_JSM=y CONFIG_SERIAL_SIFIVE=y CONFIG_SERIAL_SIFIVE_CONSOLE=y CONFIG_SERIAL_LANTIQ=y CONFIG_SERIAL_LANTIQ_CONSOLE=y CONFIG_SERIAL_SCCNXP=y CONFIG_SERIAL_SCCNXP_CONSOLE=y CONFIG_SERIAL_SC16IS7XX_CORE=y CONFIG_SERIAL_SC16IS7XX=y CONFIG_SERIAL_SC16IS7XX_I2C=y CONFIG_SERIAL_SC16IS7XX_SPI=y CONFIG_SERIAL_TIMBERDALE=y CONFIG_SERIAL_ALTERA_JTAGUART=y CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE=y CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE_BYPASS=y CONFIG_SERIAL_ALTERA_UART=y CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4 CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200 CONFIG_SERIAL_ALTERA_UART_CONSOLE=y CONFIG_SERIAL_PCH_UART=y CONFIG_SERIAL_PCH_UART_CONSOLE=y CONFIG_SERIAL_XILINX_PS_UART=y CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y CONFIG_SERIAL_ARC=y CONFIG_SERIAL_ARC_CONSOLE=y CONFIG_SERIAL_ARC_NR_PORTS=1 CONFIG_SERIAL_RP2=y CONFIG_SERIAL_RP2_NR_UARTS=32 CONFIG_SERIAL_FSL_LPUART=y CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_FSL_LINFLEXUART=y CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y CONFIG_SERIAL_CONEXANT_DIGICOLOR=y CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y CONFIG_SERIAL_MEN_Z135=y CONFIG_SERIAL_SPRD=y CONFIG_SERIAL_SPRD_CONSOLE=y CONFIG_SERIAL_LITEUART=y CONFIG_SERIAL_LITEUART_MAX_PORTS=1 CONFIG_SERIAL_LITEUART_CONSOLE=y # end of Serial drivers CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_NONSTANDARD=y CONFIG_MOXA_INTELLIO=y CONFIG_MOXA_SMARTIO=y CONFIG_SYNCLINK_GT=y CONFIG_N_HDLC=y CONFIG_GOLDFISH_TTY=y CONFIG_GOLDFISH_TTY_EARLY_CONSOLE=y CONFIG_N_GSM=y CONFIG_NOZOMI=y CONFIG_NULL_TTY=y CONFIG_HVC_DRIVER=y CONFIG_RPMSG_TTY=y CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y CONFIG_TTY_PRINTK=y CONFIG_TTY_PRINTK_LEVEL=6 CONFIG_PRINTER=y CONFIG_LP_CONSOLE=y CONFIG_PPDEV=y CONFIG_VIRTIO_CONSOLE=y CONFIG_IPMI_HANDLER=y CONFIG_IPMI_DMI_DECODE=y CONFIG_IPMI_PLAT_DATA=y CONFIG_IPMI_PANIC_EVENT=y CONFIG_IPMI_PANIC_STRING=y CONFIG_IPMI_DEVICE_INTERFACE=y CONFIG_IPMI_SI=y CONFIG_IPMI_SSIF=y CONFIG_IPMI_IPMB=y CONFIG_IPMI_WATCHDOG=y CONFIG_IPMI_POWEROFF=y CONFIG_IPMB_DEVICE_INTERFACE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_TIMERIOMEM=y CONFIG_HW_RANDOM_INTEL=y CONFIG_HW_RANDOM_AMD=y CONFIG_HW_RANDOM_BA431=y CONFIG_HW_RANDOM_GEODE=y CONFIG_HW_RANDOM_VIA=y CONFIG_HW_RANDOM_VIRTIO=y CONFIG_HW_RANDOM_CCTRNG=y CONFIG_HW_RANDOM_XIPHERA=y CONFIG_DTLK=y CONFIG_APPLICOM=y CONFIG_SONYPI=y # # PCMCIA character devices # CONFIG_SYNCLINK_CS=y CONFIG_CARDMAN_4000=y CONFIG_CARDMAN_4040=y CONFIG_SCR24X=y CONFIG_IPWIRELESS=y # end of PCMCIA character devices CONFIG_MWAVE=y CONFIG_SCx200_GPIO=y CONFIG_PC8736x_GPIO=y CONFIG_NSC_GPIO=y CONFIG_DEVMEM=y CONFIG_NVRAM=y CONFIG_DEVPORT=y CONFIG_HPET=y CONFIG_HPET_MMAP=y CONFIG_HPET_MMAP_DEFAULT=y CONFIG_HANGCHECK_TIMER=y CONFIG_TCG_TPM=y CONFIG_HW_RANDOM_TPM=y CONFIG_TCG_TIS_CORE=y CONFIG_TCG_TIS=y CONFIG_TCG_TIS_SPI=y CONFIG_TCG_TIS_SPI_CR50=y CONFIG_TCG_TIS_I2C=y CONFIG_TCG_TIS_I2C_CR50=y CONFIG_TCG_TIS_I2C_ATMEL=y CONFIG_TCG_TIS_I2C_INFINEON=y CONFIG_TCG_TIS_I2C_NUVOTON=y CONFIG_TCG_NSC=y CONFIG_TCG_ATMEL=y CONFIG_TCG_INFINEON=y CONFIG_TCG_CRB=y CONFIG_TCG_VTPM_PROXY=y CONFIG_TCG_TIS_ST33ZP24=y CONFIG_TCG_TIS_ST33ZP24_I2C=y CONFIG_TCG_TIS_ST33ZP24_SPI=y CONFIG_TELCLOCK=y CONFIG_XILLYBUS_CLASS=y CONFIG_XILLYBUS=y CONFIG_XILLYBUS_PCIE=y CONFIG_XILLYBUS_OF=y CONFIG_XILLYUSB=y CONFIG_RANDOM_TRUST_CPU=y CONFIG_RANDOM_TRUST_BOOTLOADER=y # end of Character devices # # I2C support # CONFIG_I2C=y CONFIG_ACPI_I2C_OPREGION=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y # # Multiplexer I2C Chip support # CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_I2C_MUX_GPIO=y CONFIG_I2C_MUX_GPMUX=y CONFIG_I2C_MUX_LTC4306=y CONFIG_I2C_MUX_PCA9541=y CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_MUX_PINCTRL=y CONFIG_I2C_MUX_REG=y CONFIG_I2C_DEMUX_PINCTRL=y CONFIG_I2C_MUX_MLXCPLD=y # end of Multiplexer I2C Chip support CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_SMBUS=y CONFIG_I2C_ALGOBIT=y CONFIG_I2C_ALGOPCA=y # # I2C Hardware Bus support # # # PC SMBus host controller drivers # CONFIG_I2C_CCGX_UCSI=y CONFIG_I2C_ALI1535=y CONFIG_I2C_ALI1563=y CONFIG_I2C_ALI15X3=y CONFIG_I2C_AMD756=y CONFIG_I2C_AMD756_S4882=y CONFIG_I2C_AMD8111=y CONFIG_I2C_AMD_MP2=y CONFIG_I2C_I801=y CONFIG_I2C_ISCH=y CONFIG_I2C_ISMT=y CONFIG_I2C_PIIX4=y CONFIG_I2C_CHT_WC=y CONFIG_I2C_NFORCE2=y CONFIG_I2C_NFORCE2_S4985=y CONFIG_I2C_NVIDIA_GPU=y CONFIG_I2C_SIS5595=y CONFIG_I2C_SIS630=y CONFIG_I2C_SIS96X=y CONFIG_I2C_VIA=y CONFIG_I2C_VIAPRO=y # # ACPI drivers # CONFIG_I2C_SCMI=y # # I2C system bus drivers (mostly embedded / system-on-chip) # CONFIG_I2C_CBUS_GPIO=y CONFIG_I2C_DESIGNWARE_CORE=y CONFIG_I2C_DESIGNWARE_SLAVE=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_DESIGNWARE_AMDPSP=y CONFIG_I2C_DESIGNWARE_BAYTRAIL=y CONFIG_I2C_DESIGNWARE_PCI=y CONFIG_I2C_EG20T=y CONFIG_I2C_EMEV2=y CONFIG_I2C_GPIO=y CONFIG_I2C_GPIO_FAULT_INJECTOR=y CONFIG_I2C_KEMPLD=y CONFIG_I2C_OCORES=y CONFIG_I2C_PCA_PLATFORM=y CONFIG_I2C_PXA=y CONFIG_I2C_PXA_PCI=y CONFIG_I2C_RK3X=y CONFIG_I2C_SIMTEC=y CONFIG_I2C_XILINX=y # # External I2C/SMBus adapter drivers # CONFIG_I2C_DIOLAN_U2C=y CONFIG_I2C_DLN2=y CONFIG_I2C_CP2615=y CONFIG_I2C_PARPORT=y CONFIG_I2C_PCI1XXXX=y CONFIG_I2C_ROBOTFUZZ_OSIF=y CONFIG_I2C_TAOS_EVM=y CONFIG_I2C_TINY_USB=y CONFIG_I2C_VIPERBOARD=y # # Other I2C/SMBus bus drivers # CONFIG_I2C_PCA_ISA=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SCx200_ACB=y CONFIG_I2C_FSI=y CONFIG_I2C_VIRTIO=y # end of I2C Hardware Bus support CONFIG_I2C_STUB=m CONFIG_I2C_SLAVE=y CONFIG_I2C_SLAVE_EEPROM=y CONFIG_I2C_SLAVE_TESTUNIT=y CONFIG_I2C_DEBUG_CORE=y CONFIG_I2C_DEBUG_ALGO=y CONFIG_I2C_DEBUG_BUS=y # end of I2C support CONFIG_I3C=y CONFIG_CDNS_I3C_MASTER=y CONFIG_DW_I3C_MASTER=y CONFIG_SVC_I3C_MASTER=y CONFIG_MIPI_I3C_HCI=y CONFIG_SPI=y CONFIG_SPI_DEBUG=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y # # SPI Master Controller Drivers # CONFIG_SPI_ALTERA=y CONFIG_SPI_ALTERA_CORE=y CONFIG_SPI_ALTERA_DFL=y CONFIG_SPI_AXI_SPI_ENGINE=y CONFIG_SPI_BITBANG=y CONFIG_SPI_BUTTERFLY=y CONFIG_SPI_CADENCE=y CONFIG_SPI_CADENCE_QUADSPI=y CONFIG_SPI_CADENCE_XSPI=y CONFIG_SPI_DESIGNWARE=y CONFIG_SPI_DW_DMA=y CONFIG_SPI_DW_PCI=y CONFIG_SPI_DW_MMIO=y CONFIG_SPI_DLN2=y CONFIG_SPI_FSI=y CONFIG_SPI_NXP_FLEXSPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_INTEL=y CONFIG_SPI_INTEL_PCI=y CONFIG_SPI_INTEL_PLATFORM=y CONFIG_SPI_LM70_LLP=y CONFIG_SPI_FSL_LIB=y CONFIG_SPI_FSL_SPI=y CONFIG_SPI_MICROCHIP_CORE=y CONFIG_SPI_MICROCHIP_CORE_QSPI=y CONFIG_SPI_LANTIQ_SSC=y CONFIG_SPI_OC_TINY=y CONFIG_SPI_PXA2XX=y CONFIG_SPI_PXA2XX_PCI=y CONFIG_SPI_ROCKCHIP=y CONFIG_SPI_SC18IS602=y CONFIG_SPI_SIFIVE=y CONFIG_SPI_MXIC=y CONFIG_SPI_TOPCLIFF_PCH=y CONFIG_SPI_XCOMM=y CONFIG_SPI_XILINX=y CONFIG_SPI_ZYNQMP_GQSPI=y CONFIG_SPI_AMD=y # # SPI Multiplexer support # CONFIG_SPI_MUX=y # # SPI Protocol Masters # CONFIG_SPI_SPIDEV=y CONFIG_SPI_LOOPBACK_TEST=m CONFIG_SPI_TLE62X0=y CONFIG_SPI_SLAVE=y CONFIG_SPI_SLAVE_TIME=y CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y CONFIG_SPI_DYNAMIC=y CONFIG_SPMI=y CONFIG_SPMI_HISI3670=y CONFIG_HSI=y CONFIG_HSI_BOARDINFO=y # # HSI controllers # # # HSI clients # CONFIG_HSI_CHAR=y CONFIG_PPS=y CONFIG_PPS_DEBUG=y # # PPS clients support # CONFIG_PPS_CLIENT_KTIMER=y CONFIG_PPS_CLIENT_LDISC=y CONFIG_PPS_CLIENT_PARPORT=y CONFIG_PPS_CLIENT_GPIO=y # # PPS generators support # # # PTP clock support # CONFIG_PTP_1588_CLOCK=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_DP83640_PHY=y CONFIG_PTP_1588_CLOCK_INES=y CONFIG_PTP_1588_CLOCK_PCH=y CONFIG_PTP_1588_CLOCK_KVM=y CONFIG_PTP_1588_CLOCK_IDT82P33=y CONFIG_PTP_1588_CLOCK_IDTCM=y CONFIG_PTP_1588_CLOCK_VMW=y CONFIG_PTP_1588_CLOCK_OCP=y # end of PTP clock support CONFIG_PINCTRL=y CONFIG_GENERIC_PINCTRL_GROUPS=y CONFIG_PINMUX=y CONFIG_GENERIC_PINMUX_FUNCTIONS=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y CONFIG_DEBUG_PINCTRL=y CONFIG_PINCTRL_AMD=y CONFIG_PINCTRL_AS3722=y CONFIG_PINCTRL_AXP209=y CONFIG_PINCTRL_CY8C95X0=y CONFIG_PINCTRL_DA9062=y CONFIG_PINCTRL_EQUILIBRIUM=y CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_MCP23S08_I2C=y CONFIG_PINCTRL_MCP23S08_SPI=y CONFIG_PINCTRL_MCP23S08=y CONFIG_PINCTRL_MICROCHIP_SGPIO=y CONFIG_PINCTRL_OCELOT=y CONFIG_PINCTRL_PALMAS=y CONFIG_PINCTRL_RK805=y CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_STMFX=y CONFIG_PINCTRL_SX150X=y CONFIG_PINCTRL_LOCHNAGAR=y CONFIG_PINCTRL_MADERA=y CONFIG_PINCTRL_CS47L15=y CONFIG_PINCTRL_CS47L35=y CONFIG_PINCTRL_CS47L85=y CONFIG_PINCTRL_CS47L90=y CONFIG_PINCTRL_CS47L92=y CONFIG_PINCTRL_CS48L32=y # # Intel pinctrl drivers # CONFIG_PINCTRL_BAYTRAIL=y CONFIG_PINCTRL_CHERRYVIEW=y CONFIG_PINCTRL_LYNXPOINT=y CONFIG_PINCTRL_MERRIFIELD=y CONFIG_PINCTRL_INTEL=y CONFIG_PINCTRL_ALDERLAKE=y CONFIG_PINCTRL_BROXTON=y CONFIG_PINCTRL_CANNONLAKE=y CONFIG_PINCTRL_CEDARFORK=y CONFIG_PINCTRL_DENVERTON=y CONFIG_PINCTRL_ELKHARTLAKE=y CONFIG_PINCTRL_EMMITSBURG=y CONFIG_PINCTRL_GEMINILAKE=y CONFIG_PINCTRL_ICELAKE=y CONFIG_PINCTRL_JASPERLAKE=y CONFIG_PINCTRL_LAKEFIELD=y CONFIG_PINCTRL_LEWISBURG=y CONFIG_PINCTRL_METEORLAKE=y CONFIG_PINCTRL_SUNRISEPOINT=y CONFIG_PINCTRL_TIGERLAKE=y # end of Intel pinctrl drivers # # Renesas pinctrl drivers # # end of Renesas pinctrl drivers CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIO_ACPI=y CONFIG_GPIOLIB_IRQCHIP=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y CONFIG_GPIO_MAX730X=y # # Memory mapped GPIO drivers # CONFIG_GPIO_74XX_MMIO=y CONFIG_GPIO_ALTERA=y CONFIG_GPIO_AMDPT=y CONFIG_GPIO_CADENCE=y CONFIG_GPIO_DWAPB=y CONFIG_GPIO_EXAR=y CONFIG_GPIO_FTGPIO010=y CONFIG_GPIO_GENERIC_PLATFORM=y CONFIG_GPIO_GRGPIO=y CONFIG_GPIO_HLWD=y CONFIG_GPIO_ICH=y CONFIG_GPIO_LOGICVC=y CONFIG_GPIO_MB86S7X=y CONFIG_GPIO_MENZ127=y CONFIG_GPIO_SIFIVE=y CONFIG_GPIO_SIOX=y # CONFIG_GPIO_STA2X11 is not set CONFIG_GPIO_SYSCON=y CONFIG_GPIO_VX855=y CONFIG_GPIO_WCD934X=y CONFIG_GPIO_XILINX=y CONFIG_GPIO_AMD_FCH=y # end of Memory mapped GPIO drivers # # Port-mapped I/O GPIO drivers # CONFIG_GPIO_I8255=y CONFIG_GPIO_104_DIO_48E=y CONFIG_GPIO_104_IDIO_16=y CONFIG_GPIO_104_IDI_48=y CONFIG_GPIO_F7188X=y CONFIG_GPIO_GPIO_MM=y CONFIG_GPIO_IT87=y CONFIG_GPIO_SCH=y CONFIG_GPIO_SCH311X=y CONFIG_GPIO_WINBOND=y CONFIG_GPIO_WS16C48=y # end of Port-mapped I/O GPIO drivers # # I2C GPIO expanders # CONFIG_GPIO_ADNP=y CONFIG_GPIO_GW_PLD=y CONFIG_GPIO_MAX7300=y CONFIG_GPIO_MAX732X=y CONFIG_GPIO_MAX732X_IRQ=y CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_PCA9570=y CONFIG_GPIO_PCF857X=y CONFIG_GPIO_TPIC2810=y # end of I2C GPIO expanders # # MFD GPIO expanders # CONFIG_GPIO_ADP5520=y CONFIG_GPIO_ARIZONA=y CONFIG_GPIO_BD71815=y CONFIG_GPIO_BD71828=y CONFIG_GPIO_BD9571MWV=y CONFIG_GPIO_CRYSTAL_COVE=y CONFIG_GPIO_CS5535=y CONFIG_GPIO_DA9052=y CONFIG_GPIO_DA9055=y CONFIG_GPIO_DLN2=y CONFIG_GPIO_JANZ_TTL=y CONFIG_GPIO_KEMPLD=y CONFIG_GPIO_LP3943=y CONFIG_GPIO_LP873X=y CONFIG_GPIO_LP87565=y CONFIG_GPIO_MADERA=y CONFIG_GPIO_MAX77620=y CONFIG_GPIO_MAX77650=y CONFIG_GPIO_PALMAS=y CONFIG_GPIO_RC5T583=y CONFIG_GPIO_STMPE=y CONFIG_GPIO_TC3589X=y CONFIG_GPIO_TIMBERDALE=y CONFIG_GPIO_TPS65086=y CONFIG_GPIO_TPS65218=y CONFIG_GPIO_TPS6586X=y CONFIG_GPIO_TPS65910=y CONFIG_GPIO_TPS65912=y CONFIG_GPIO_TPS68470=y CONFIG_GPIO_TQMX86=y CONFIG_GPIO_TWL4030=y CONFIG_GPIO_TWL6040=y CONFIG_GPIO_UCB1400=y CONFIG_GPIO_WHISKEY_COVE=y CONFIG_GPIO_WM831X=y CONFIG_GPIO_WM8350=y CONFIG_GPIO_WM8994=y # end of MFD GPIO expanders # # PCI GPIO expanders # CONFIG_GPIO_AMD8111=y CONFIG_GPIO_MERRIFIELD=y CONFIG_GPIO_ML_IOH=y CONFIG_GPIO_PCH=y CONFIG_GPIO_PCI_IDIO_16=y CONFIG_GPIO_PCIE_IDIO_24=y CONFIG_GPIO_RDC321X=y CONFIG_GPIO_SODAVILLE=y # end of PCI GPIO expanders # # SPI GPIO expanders # CONFIG_GPIO_74X164=y CONFIG_GPIO_MAX3191X=y CONFIG_GPIO_MAX7301=y CONFIG_GPIO_MC33880=y CONFIG_GPIO_PISOSR=y CONFIG_GPIO_XRA1403=y CONFIG_GPIO_MOXTET=y # end of SPI GPIO expanders # # USB GPIO expanders # CONFIG_GPIO_VIPERBOARD=y # end of USB GPIO expanders # # Virtual GPIO drivers # CONFIG_GPIO_AGGREGATOR=y CONFIG_GPIO_MOCKUP=y CONFIG_GPIO_VIRTIO=y CONFIG_GPIO_SIM=y # end of Virtual GPIO drivers CONFIG_W1=y CONFIG_W1_CON=y # # 1-wire Bus Masters # CONFIG_W1_MASTER_MATROX=y CONFIG_W1_MASTER_DS2490=y CONFIG_W1_MASTER_DS2482=y CONFIG_W1_MASTER_DS1WM=y CONFIG_W1_MASTER_GPIO=y CONFIG_W1_MASTER_SGI=y # end of 1-wire Bus Masters # # 1-wire Slaves # CONFIG_W1_SLAVE_THERM=y CONFIG_W1_SLAVE_SMEM=y CONFIG_W1_SLAVE_DS2405=y CONFIG_W1_SLAVE_DS2408=y CONFIG_W1_SLAVE_DS2408_READBACK=y CONFIG_W1_SLAVE_DS2413=y CONFIG_W1_SLAVE_DS2406=y CONFIG_W1_SLAVE_DS2423=y CONFIG_W1_SLAVE_DS2805=y CONFIG_W1_SLAVE_DS2430=y CONFIG_W1_SLAVE_DS2431=y CONFIG_W1_SLAVE_DS2433=y CONFIG_W1_SLAVE_DS2433_CRC=y CONFIG_W1_SLAVE_DS2438=y CONFIG_W1_SLAVE_DS250X=y CONFIG_W1_SLAVE_DS2780=y CONFIG_W1_SLAVE_DS2781=y CONFIG_W1_SLAVE_DS28E04=y CONFIG_W1_SLAVE_DS28E17=y # end of 1-wire Slaves CONFIG_POWER_RESET=y CONFIG_POWER_RESET_AS3722=y CONFIG_POWER_RESET_ATC260X=y CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_POWER_RESET_LTC2952=y CONFIG_POWER_RESET_MT6323=y CONFIG_POWER_RESET_REGULATOR=y CONFIG_POWER_RESET_RESTART=y CONFIG_POWER_RESET_TPS65086=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_REBOOT_MODE=y CONFIG_SYSCON_REBOOT_MODE=y CONFIG_NVMEM_REBOOT_MODE=y CONFIG_POWER_SUPPLY=y CONFIG_POWER_SUPPLY_DEBUG=y CONFIG_POWER_SUPPLY_HWMON=y CONFIG_PDA_POWER=y CONFIG_GENERIC_ADC_BATTERY=y CONFIG_IP5XXX_POWER=y CONFIG_MAX8925_POWER=y CONFIG_WM831X_BACKUP=y CONFIG_WM831X_POWER=y CONFIG_WM8350_POWER=y CONFIG_TEST_POWER=y CONFIG_BATTERY_88PM860X=y CONFIG_CHARGER_ADP5061=y CONFIG_BATTERY_ACT8945A=y CONFIG_BATTERY_CPCAP=y CONFIG_BATTERY_CW2015=y CONFIG_BATTERY_DS2760=y CONFIG_BATTERY_DS2780=y CONFIG_BATTERY_DS2781=y CONFIG_BATTERY_DS2782=y CONFIG_BATTERY_OLPC=y CONFIG_BATTERY_SAMSUNG_SDI=y CONFIG_BATTERY_WM97XX=y CONFIG_BATTERY_SBS=y CONFIG_CHARGER_SBS=y CONFIG_MANAGER_SBS=y CONFIG_BATTERY_BQ27XXX=y CONFIG_BATTERY_BQ27XXX_I2C=y CONFIG_BATTERY_BQ27XXX_HDQ=y CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM=y CONFIG_BATTERY_DA9030=y CONFIG_BATTERY_DA9052=y CONFIG_CHARGER_DA9150=y CONFIG_BATTERY_DA9150=y CONFIG_CHARGER_AXP20X=y CONFIG_BATTERY_AXP20X=y CONFIG_AXP20X_POWER=y CONFIG_AXP288_CHARGER=y CONFIG_AXP288_FUEL_GAUGE=y CONFIG_BATTERY_MAX17040=y CONFIG_BATTERY_MAX17042=y CONFIG_BATTERY_MAX1721X=y CONFIG_BATTERY_TWL4030_MADC=y CONFIG_CHARGER_88PM860X=y CONFIG_CHARGER_PCF50633=y CONFIG_BATTERY_RX51=y CONFIG_CHARGER_ISP1704=y CONFIG_CHARGER_MAX8903=y CONFIG_CHARGER_TWL4030=y CONFIG_CHARGER_LP8727=y CONFIG_CHARGER_LP8788=y CONFIG_CHARGER_GPIO=y CONFIG_CHARGER_MANAGER=y CONFIG_CHARGER_LT3651=y CONFIG_CHARGER_LTC4162L=y CONFIG_CHARGER_MAX14577=y CONFIG_CHARGER_DETECTOR_MAX14656=y CONFIG_CHARGER_MAX77650=y CONFIG_CHARGER_MAX77693=y CONFIG_CHARGER_MAX77976=y CONFIG_CHARGER_MAX8997=y CONFIG_CHARGER_MAX8998=y CONFIG_CHARGER_MP2629=y CONFIG_CHARGER_MT6360=y CONFIG_CHARGER_MT6370=y CONFIG_CHARGER_BQ2415X=y CONFIG_CHARGER_BQ24190=y CONFIG_CHARGER_BQ24257=y CONFIG_CHARGER_BQ24735=y CONFIG_CHARGER_BQ2515X=y CONFIG_CHARGER_BQ25890=y CONFIG_CHARGER_BQ25980=y CONFIG_CHARGER_BQ256XX=y CONFIG_CHARGER_RK817=y CONFIG_CHARGER_SMB347=y CONFIG_CHARGER_TPS65090=y CONFIG_CHARGER_TPS65217=y CONFIG_BATTERY_GAUGE_LTC2941=y CONFIG_BATTERY_GOLDFISH=y CONFIG_BATTERY_RT5033=y CONFIG_CHARGER_RT9455=y CONFIG_CHARGER_CROS_USBPD=y CONFIG_CHARGER_CROS_PCHG=y CONFIG_CHARGER_UCS1002=y CONFIG_CHARGER_BD99954=y CONFIG_CHARGER_WILCO=y CONFIG_RN5T618_POWER=y CONFIG_BATTERY_SURFACE=y CONFIG_CHARGER_SURFACE=y CONFIG_BATTERY_UG3105=y CONFIG_HWMON=y CONFIG_HWMON_VID=y CONFIG_HWMON_DEBUG_CHIP=y # # Native drivers # CONFIG_SENSORS_ABITUGURU=y CONFIG_SENSORS_ABITUGURU3=y CONFIG_SENSORS_AD7314=y CONFIG_SENSORS_AD7414=y CONFIG_SENSORS_AD7418=y CONFIG_SENSORS_ADM1025=y CONFIG_SENSORS_ADM1026=y CONFIG_SENSORS_ADM1029=y CONFIG_SENSORS_ADM1031=y CONFIG_SENSORS_ADM1177=y CONFIG_SENSORS_ADM9240=y CONFIG_SENSORS_ADT7X10=y CONFIG_SENSORS_ADT7310=y CONFIG_SENSORS_ADT7410=y CONFIG_SENSORS_ADT7411=y CONFIG_SENSORS_ADT7462=y CONFIG_SENSORS_ADT7470=y CONFIG_SENSORS_ADT7475=y CONFIG_SENSORS_AHT10=y CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=y CONFIG_SENSORS_AS370=y CONFIG_SENSORS_ASC7621=y CONFIG_SENSORS_AXI_FAN_CONTROL=y CONFIG_SENSORS_K8TEMP=y CONFIG_SENSORS_K10TEMP=y CONFIG_SENSORS_FAM15H_POWER=y CONFIG_SENSORS_APPLESMC=y CONFIG_SENSORS_ASB100=y CONFIG_SENSORS_ATXP1=y CONFIG_SENSORS_CORSAIR_CPRO=y CONFIG_SENSORS_CORSAIR_PSU=y CONFIG_SENSORS_DRIVETEMP=y CONFIG_SENSORS_DS620=y CONFIG_SENSORS_DS1621=y CONFIG_SENSORS_DELL_SMM=y CONFIG_I8K=y CONFIG_SENSORS_DA9052_ADC=y CONFIG_SENSORS_DA9055=y CONFIG_SENSORS_I5K_AMB=y CONFIG_SENSORS_F71805F=y CONFIG_SENSORS_F71882FG=y CONFIG_SENSORS_F75375S=y CONFIG_SENSORS_GSC=y CONFIG_SENSORS_MC13783_ADC=y CONFIG_SENSORS_FSCHMD=y CONFIG_SENSORS_FTSTEUTATES=y CONFIG_SENSORS_GL518SM=y CONFIG_SENSORS_GL520SM=y CONFIG_SENSORS_G760A=y CONFIG_SENSORS_G762=y CONFIG_SENSORS_GPIO_FAN=y CONFIG_SENSORS_HIH6130=y CONFIG_SENSORS_IBMAEM=y CONFIG_SENSORS_IBMPEX=y CONFIG_SENSORS_IIO_HWMON=y CONFIG_SENSORS_I5500=y CONFIG_SENSORS_CORETEMP=y CONFIG_SENSORS_IT87=y CONFIG_SENSORS_JC42=y CONFIG_SENSORS_POWR1220=y CONFIG_SENSORS_LINEAGE=y CONFIG_SENSORS_LOCHNAGAR=y CONFIG_SENSORS_LTC2945=y CONFIG_SENSORS_LTC2947=y CONFIG_SENSORS_LTC2947_I2C=y CONFIG_SENSORS_LTC2947_SPI=y CONFIG_SENSORS_LTC2990=y CONFIG_SENSORS_LTC2992=y CONFIG_SENSORS_LTC4151=y CONFIG_SENSORS_LTC4215=y CONFIG_SENSORS_LTC4222=y CONFIG_SENSORS_LTC4245=y CONFIG_SENSORS_LTC4260=y CONFIG_SENSORS_LTC4261=y CONFIG_SENSORS_MAX1111=y CONFIG_SENSORS_MAX127=y CONFIG_SENSORS_MAX16065=y CONFIG_SENSORS_MAX1619=y CONFIG_SENSORS_MAX1668=y CONFIG_SENSORS_MAX197=y CONFIG_SENSORS_MAX31722=y CONFIG_SENSORS_MAX31730=y CONFIG_SENSORS_MAX31760=y CONFIG_SENSORS_MAX6620=y CONFIG_SENSORS_MAX6621=y CONFIG_SENSORS_MAX6639=y CONFIG_SENSORS_MAX6650=y CONFIG_SENSORS_MAX6697=y CONFIG_SENSORS_MAX31790=y CONFIG_SENSORS_MCP3021=y CONFIG_SENSORS_MLXREG_FAN=y CONFIG_SENSORS_TC654=y CONFIG_SENSORS_TPS23861=y CONFIG_SENSORS_MENF21BMC_HWMON=y CONFIG_SENSORS_MR75203=y CONFIG_SENSORS_ADCXX=y CONFIG_SENSORS_LM63=y CONFIG_SENSORS_LM70=y CONFIG_SENSORS_LM73=y CONFIG_SENSORS_LM75=y CONFIG_SENSORS_LM77=y CONFIG_SENSORS_LM78=y CONFIG_SENSORS_LM80=y CONFIG_SENSORS_LM83=y CONFIG_SENSORS_LM85=y CONFIG_SENSORS_LM87=y CONFIG_SENSORS_LM90=y CONFIG_SENSORS_LM92=y CONFIG_SENSORS_LM93=y CONFIG_SENSORS_LM95234=y CONFIG_SENSORS_LM95241=y CONFIG_SENSORS_LM95245=y CONFIG_SENSORS_PC87360=y CONFIG_SENSORS_PC87427=y CONFIG_SENSORS_NTC_THERMISTOR=y CONFIG_SENSORS_NCT6683=y CONFIG_SENSORS_NCT6775_CORE=y CONFIG_SENSORS_NCT6775=y CONFIG_SENSORS_NCT6775_I2C=y CONFIG_SENSORS_NCT7802=y CONFIG_SENSORS_NCT7904=y CONFIG_SENSORS_NPCM7XX=y CONFIG_SENSORS_NZXT_KRAKEN2=y CONFIG_SENSORS_NZXT_SMART2=y CONFIG_SENSORS_PCF8591=y CONFIG_SENSORS_PECI_CPUTEMP=y CONFIG_SENSORS_PECI_DIMMTEMP=y CONFIG_SENSORS_PECI=y CONFIG_PMBUS=y CONFIG_SENSORS_PMBUS=y CONFIG_SENSORS_ADM1266=y CONFIG_SENSORS_ADM1275=y CONFIG_SENSORS_BEL_PFE=y CONFIG_SENSORS_BPA_RS600=y CONFIG_SENSORS_DELTA_AHE50DC_FAN=y CONFIG_SENSORS_FSP_3Y=y CONFIG_SENSORS_IBM_CFFPS=y CONFIG_SENSORS_DPS920AB=y CONFIG_SENSORS_INSPUR_IPSPS=y CONFIG_SENSORS_IR35221=y CONFIG_SENSORS_IR36021=y CONFIG_SENSORS_IR38064=y CONFIG_SENSORS_IR38064_REGULATOR=y CONFIG_SENSORS_IRPS5401=y CONFIG_SENSORS_ISL68137=y CONFIG_SENSORS_LM25066=y CONFIG_SENSORS_LM25066_REGULATOR=y CONFIG_SENSORS_LT7182S=y CONFIG_SENSORS_LTC2978=y CONFIG_SENSORS_LTC2978_REGULATOR=y CONFIG_SENSORS_LTC3815=y CONFIG_SENSORS_MAX15301=y CONFIG_SENSORS_MAX16064=y CONFIG_SENSORS_MAX16601=y CONFIG_SENSORS_MAX20730=y CONFIG_SENSORS_MAX20751=y CONFIG_SENSORS_MAX31785=y CONFIG_SENSORS_MAX34440=y CONFIG_SENSORS_MAX8688=y CONFIG_SENSORS_MP2888=y CONFIG_SENSORS_MP2975=y CONFIG_SENSORS_MP5023=y CONFIG_SENSORS_PIM4328=y CONFIG_SENSORS_PLI1209BC=y CONFIG_SENSORS_PLI1209BC_REGULATOR=y CONFIG_SENSORS_PM6764TR=y CONFIG_SENSORS_PXE1610=y CONFIG_SENSORS_Q54SJ108A2=y CONFIG_SENSORS_STPDDC60=y CONFIG_SENSORS_TPS40422=y CONFIG_SENSORS_TPS53679=y CONFIG_SENSORS_TPS546D24=y CONFIG_SENSORS_UCD9000=y CONFIG_SENSORS_UCD9200=y CONFIG_SENSORS_XDPE152=y CONFIG_SENSORS_XDPE122=y CONFIG_SENSORS_XDPE122_REGULATOR=y CONFIG_SENSORS_ZL6100=y CONFIG_SENSORS_PWM_FAN=y CONFIG_SENSORS_SBTSI=y CONFIG_SENSORS_SBRMI=y CONFIG_SENSORS_SHT15=y CONFIG_SENSORS_SHT21=y CONFIG_SENSORS_SHT3x=y CONFIG_SENSORS_SHT4x=y CONFIG_SENSORS_SHTC1=y CONFIG_SENSORS_SIS5595=y CONFIG_SENSORS_SY7636A=y CONFIG_SENSORS_DME1737=y CONFIG_SENSORS_EMC1403=y CONFIG_SENSORS_EMC2103=y CONFIG_SENSORS_EMC2305=y CONFIG_SENSORS_EMC6W201=y CONFIG_SENSORS_SMSC47M1=y CONFIG_SENSORS_SMSC47M192=y CONFIG_SENSORS_SMSC47B397=y CONFIG_SENSORS_SCH56XX_COMMON=y CONFIG_SENSORS_SCH5627=y CONFIG_SENSORS_SCH5636=y CONFIG_SENSORS_STTS751=y CONFIG_SENSORS_SMM665=y CONFIG_SENSORS_ADC128D818=y CONFIG_SENSORS_ADS7828=y CONFIG_SENSORS_ADS7871=y CONFIG_SENSORS_AMC6821=y CONFIG_SENSORS_INA209=y CONFIG_SENSORS_INA2XX=y CONFIG_SENSORS_INA238=y CONFIG_SENSORS_INA3221=y CONFIG_SENSORS_TC74=y CONFIG_SENSORS_THMC50=y CONFIG_SENSORS_TMP102=y CONFIG_SENSORS_TMP103=y CONFIG_SENSORS_TMP108=y CONFIG_SENSORS_TMP401=y CONFIG_SENSORS_TMP421=y CONFIG_SENSORS_TMP464=y CONFIG_SENSORS_TMP513=y CONFIG_SENSORS_VIA_CPUTEMP=y CONFIG_SENSORS_VIA686A=y CONFIG_SENSORS_VT1211=y CONFIG_SENSORS_VT8231=y CONFIG_SENSORS_W83773G=y CONFIG_SENSORS_W83781D=y CONFIG_SENSORS_W83791D=y CONFIG_SENSORS_W83792D=y CONFIG_SENSORS_W83793=y CONFIG_SENSORS_W83795=y CONFIG_SENSORS_W83795_FANCTRL=y CONFIG_SENSORS_W83L785TS=y CONFIG_SENSORS_W83L786NG=y CONFIG_SENSORS_W83627HF=y CONFIG_SENSORS_W83627EHF=y CONFIG_SENSORS_WM831X=y CONFIG_SENSORS_WM8350=y CONFIG_SENSORS_XGENE=y CONFIG_SENSORS_INTEL_M10_BMC_HWMON=y # # ACPI drivers # CONFIG_SENSORS_ACPI_POWER=y CONFIG_SENSORS_ATK0110=y CONFIG_SENSORS_ASUS_WMI=y CONFIG_SENSORS_ASUS_EC=y CONFIG_THERMAL=y CONFIG_THERMAL_NETLINK=y CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set # CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set CONFIG_THERMAL_GOV_FAIR_SHARE=y CONFIG_THERMAL_GOV_STEP_WISE=y CONFIG_THERMAL_GOV_BANG_BANG=y CONFIG_THERMAL_GOV_USER_SPACE=y CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y CONFIG_CPU_FREQ_THERMAL=y CONFIG_CPU_IDLE_THERMAL=y CONFIG_DEVFREQ_THERMAL=y CONFIG_THERMAL_EMULATION=y CONFIG_THERMAL_MMIO=y CONFIG_MAX77620_THERMAL=y CONFIG_DA9062_THERMAL=y # # Intel thermal drivers # CONFIG_INTEL_POWERCLAMP=y CONFIG_X86_THERMAL_VECTOR=y CONFIG_X86_PKG_TEMP_THERMAL=y CONFIG_INTEL_SOC_DTS_IOSF_CORE=y CONFIG_INTEL_SOC_DTS_THERMAL=y CONFIG_INTEL_QUARK_DTS_THERMAL=y # # ACPI INT340X thermal drivers # # end of ACPI INT340X thermal drivers CONFIG_INTEL_BXT_PMIC_THERMAL=y CONFIG_INTEL_PCH_THERMAL=y CONFIG_INTEL_TCC_COOLING=y CONFIG_INTEL_MENLOW=y CONFIG_INTEL_HFI_THERMAL=y # end of Intel thermal drivers # CONFIG_TI_SOC_THERMAL is not set CONFIG_GENERIC_ADC_THERMAL=y CONFIG_WATCHDOG=y CONFIG_WATCHDOG_CORE=y CONFIG_WATCHDOG_NOWAYOUT=y CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 CONFIG_WATCHDOG_SYSFS=y CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT=y # # Watchdog Pretimeout Governors # CONFIG_WATCHDOG_PRETIMEOUT_GOV=y CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=y CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y # CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y # # Watchdog Device Drivers # CONFIG_SOFT_WATCHDOG=y CONFIG_SOFT_WATCHDOG_PRETIMEOUT=y CONFIG_BD957XMUF_WATCHDOG=y CONFIG_DA9052_WATCHDOG=y CONFIG_DA9055_WATCHDOG=y CONFIG_DA9063_WATCHDOG=y CONFIG_DA9062_WATCHDOG=y CONFIG_GPIO_WATCHDOG=y CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y CONFIG_MENF21BMC_WATCHDOG=y CONFIG_MENZ069_WATCHDOG=y CONFIG_WDAT_WDT=y CONFIG_WM831X_WATCHDOG=y CONFIG_WM8350_WATCHDOG=y CONFIG_XILINX_WATCHDOG=y CONFIG_ZIIRAVE_WATCHDOG=y CONFIG_RAVE_SP_WATCHDOG=y CONFIG_MLX_WDT=y CONFIG_CADENCE_WATCHDOG=y CONFIG_DW_WATCHDOG=y CONFIG_RN5T618_WATCHDOG=y CONFIG_TWL4030_WATCHDOG=y CONFIG_MAX63XX_WATCHDOG=y CONFIG_MAX77620_WATCHDOG=y CONFIG_RETU_WATCHDOG=y CONFIG_STPMIC1_WATCHDOG=y CONFIG_ACQUIRE_WDT=y CONFIG_ADVANTECH_WDT=y CONFIG_ALIM1535_WDT=y CONFIG_ALIM7101_WDT=y CONFIG_EBC_C384_WDT=y CONFIG_EXAR_WDT=y CONFIG_F71808E_WDT=y CONFIG_SP5100_TCO=y CONFIG_GEODE_WDT=y CONFIG_SBC_FITPC2_WATCHDOG=y CONFIG_EUROTECH_WDT=y CONFIG_IB700_WDT=y CONFIG_IBMASR=y CONFIG_WAFER_WDT=y CONFIG_I6300ESB_WDT=y CONFIG_IE6XX_WDT=y CONFIG_INTEL_MID_WATCHDOG=y CONFIG_ITCO_WDT=y CONFIG_ITCO_VENDOR_SUPPORT=y CONFIG_IT8712F_WDT=y CONFIG_IT87_WDT=y CONFIG_HP_WATCHDOG=y CONFIG_HPWDT_NMI_DECODING=y CONFIG_KEMPLD_WDT=y CONFIG_SC1200_WDT=y CONFIG_SCx200_WDT=y CONFIG_PC87413_WDT=y CONFIG_NV_TCO=y CONFIG_RDC321X_WDT=y CONFIG_60XX_WDT=y CONFIG_SBC8360_WDT=y CONFIG_SBC7240_WDT=y CONFIG_CPU5_WDT=y CONFIG_SMSC_SCH311X_WDT=y CONFIG_SMSC37B787_WDT=y CONFIG_TQMX86_WDT=y CONFIG_VIA_WDT=y CONFIG_W83627HF_WDT=y CONFIG_W83877F_WDT=y CONFIG_W83977F_WDT=y CONFIG_MACHZ_WDT=y CONFIG_SBC_EPX_C3_WATCHDOG=y CONFIG_INTEL_MEI_WDT=y CONFIG_NI903X_WDT=y CONFIG_NIC7018_WDT=y CONFIG_SIEMENS_SIMATIC_IPC_WDT=y CONFIG_MEN_A21_WDT=y # # ISA-based Watchdog Cards # CONFIG_PCWATCHDOG=y CONFIG_MIXCOMWD=y CONFIG_WDT=y # # PCI-based Watchdog Cards # CONFIG_PCIPCWATCHDOG=y CONFIG_WDTPCI=y # # USB-based Watchdog Cards # CONFIG_USBPCWATCHDOG=y CONFIG_SSB_POSSIBLE=y CONFIG_SSB=y CONFIG_SSB_SPROM=y CONFIG_SSB_BLOCKIO=y CONFIG_SSB_PCIHOST_POSSIBLE=y CONFIG_SSB_PCIHOST=y CONFIG_SSB_B43_PCI_BRIDGE=y CONFIG_SSB_PCMCIAHOST_POSSIBLE=y CONFIG_SSB_PCMCIAHOST=y CONFIG_SSB_SDIOHOST_POSSIBLE=y CONFIG_SSB_SDIOHOST=y CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y CONFIG_SSB_DRIVER_PCICORE=y CONFIG_SSB_DRIVER_GPIO=y CONFIG_BCMA_POSSIBLE=y CONFIG_BCMA=y CONFIG_BCMA_BLOCKIO=y CONFIG_BCMA_HOST_PCI_POSSIBLE=y CONFIG_BCMA_HOST_PCI=y CONFIG_BCMA_HOST_SOC=y CONFIG_BCMA_DRIVER_PCI=y CONFIG_BCMA_SFLASH=y CONFIG_BCMA_DRIVER_GMAC_CMN=y CONFIG_BCMA_DRIVER_GPIO=y CONFIG_BCMA_DEBUG=y # # Multifunction device drivers # CONFIG_MFD_CORE=y CONFIG_MFD_CS5535=y CONFIG_MFD_ACT8945A=y CONFIG_MFD_AS3711=y CONFIG_MFD_AS3722=y CONFIG_PMIC_ADP5520=y CONFIG_MFD_AAT2870_CORE=y CONFIG_MFD_ATMEL_FLEXCOM=y CONFIG_MFD_ATMEL_HLCDC=y CONFIG_MFD_BCM590XX=y CONFIG_MFD_BD9571MWV=y CONFIG_MFD_AXP20X=y CONFIG_MFD_AXP20X_I2C=y CONFIG_MFD_CROS_EC_DEV=y CONFIG_MFD_MADERA=y CONFIG_MFD_MADERA_I2C=y CONFIG_MFD_MADERA_SPI=y CONFIG_MFD_CS47L15=y CONFIG_MFD_CS47L35=y CONFIG_MFD_CS47L85=y CONFIG_MFD_CS47L90=y CONFIG_MFD_CS47L92=y CONFIG_MFD_CS48L32=y CONFIG_PMIC_DA903X=y CONFIG_PMIC_DA9052=y CONFIG_MFD_DA9052_SPI=y CONFIG_MFD_DA9052_I2C=y CONFIG_MFD_DA9055=y CONFIG_MFD_DA9062=y CONFIG_MFD_DA9063=y CONFIG_MFD_DA9150=y CONFIG_MFD_DLN2=y CONFIG_MFD_GATEWORKS_GSC=y CONFIG_MFD_MC13XXX=y CONFIG_MFD_MC13XXX_SPI=y CONFIG_MFD_MC13XXX_I2C=y CONFIG_MFD_MP2629=y CONFIG_MFD_HI6421_PMIC=y CONFIG_MFD_HI6421_SPMI=y CONFIG_HTC_PASIC3=y # CONFIG_HTC_I2CPLD is not set CONFIG_MFD_INTEL_QUARK_I2C_GPIO=y CONFIG_LPC_ICH=y CONFIG_LPC_SCH=y CONFIG_INTEL_SOC_PMIC=y CONFIG_INTEL_SOC_PMIC_BXTWC=y CONFIG_INTEL_SOC_PMIC_CHTWC=y CONFIG_INTEL_SOC_PMIC_CHTDC_TI=y CONFIG_INTEL_SOC_PMIC_MRFLD=y CONFIG_MFD_INTEL_LPSS=y CONFIG_MFD_INTEL_LPSS_ACPI=y CONFIG_MFD_INTEL_LPSS_PCI=y CONFIG_MFD_INTEL_PMC_BXT=y CONFIG_MFD_IQS62X=y CONFIG_MFD_JANZ_CMODIO=y CONFIG_MFD_KEMPLD=y CONFIG_MFD_88PM800=y CONFIG_MFD_88PM805=y CONFIG_MFD_88PM860X=y CONFIG_MFD_MAX14577=y CONFIG_MFD_MAX77620=y CONFIG_MFD_MAX77650=y CONFIG_MFD_MAX77686=y CONFIG_MFD_MAX77693=y CONFIG_MFD_MAX77714=y CONFIG_MFD_MAX77843=y CONFIG_MFD_MAX8907=y CONFIG_MFD_MAX8925=y CONFIG_MFD_MAX8997=y CONFIG_MFD_MAX8998=y CONFIG_MFD_MT6360=y CONFIG_MFD_MT6370=y CONFIG_MFD_MT6397=y CONFIG_MFD_MENF21BMC=y CONFIG_MFD_OCELOT=y CONFIG_EZX_PCAP=y CONFIG_MFD_CPCAP=y CONFIG_MFD_VIPERBOARD=y CONFIG_MFD_NTXEC=y CONFIG_MFD_RETU=y CONFIG_MFD_PCF50633=y CONFIG_PCF50633_ADC=y CONFIG_PCF50633_GPIO=y CONFIG_UCB1400_CORE=y CONFIG_MFD_SY7636A=y CONFIG_MFD_RDC321X=y CONFIG_MFD_RT4831=y CONFIG_MFD_RT5033=y CONFIG_MFD_RT5120=y CONFIG_MFD_RC5T583=y CONFIG_MFD_RK808=y CONFIG_MFD_RN5T618=y CONFIG_MFD_SEC_CORE=y CONFIG_MFD_SI476X_CORE=y CONFIG_MFD_SIMPLE_MFD_I2C=y CONFIG_MFD_SM501=y CONFIG_MFD_SM501_GPIO=y CONFIG_MFD_SKY81452=y CONFIG_MFD_STMPE=y # # STMicroelectronics STMPE Interface Drivers # CONFIG_STMPE_I2C=y CONFIG_STMPE_SPI=y # end of STMicroelectronics STMPE Interface Drivers CONFIG_MFD_STA2X11=y CONFIG_MFD_SYSCON=y CONFIG_MFD_TI_AM335X_TSCADC=y CONFIG_MFD_LP3943=y CONFIG_MFD_LP8788=y CONFIG_MFD_TI_LMU=y CONFIG_MFD_PALMAS=y CONFIG_TPS6105X=y CONFIG_TPS65010=y CONFIG_TPS6507X=y CONFIG_MFD_TPS65086=y CONFIG_MFD_TPS65090=y CONFIG_MFD_TPS65217=y CONFIG_MFD_TI_LP873X=y CONFIG_MFD_TI_LP87565=y CONFIG_MFD_TPS65218=y CONFIG_MFD_TPS6586X=y CONFIG_MFD_TPS65910=y CONFIG_MFD_TPS65912=y CONFIG_MFD_TPS65912_I2C=y CONFIG_MFD_TPS65912_SPI=y CONFIG_TWL4030_CORE=y CONFIG_MFD_TWL4030_AUDIO=y CONFIG_TWL6040_CORE=y CONFIG_MFD_WL1273_CORE=y CONFIG_MFD_LM3533=y CONFIG_MFD_TIMBERDALE=y CONFIG_MFD_TC3589X=y CONFIG_MFD_TQMX86=y CONFIG_MFD_VX855=y CONFIG_MFD_LOCHNAGAR=y CONFIG_MFD_ARIZONA=y CONFIG_MFD_ARIZONA_I2C=y CONFIG_MFD_ARIZONA_SPI=y CONFIG_MFD_CS47L24=y CONFIG_MFD_WM5102=y CONFIG_MFD_WM5110=y CONFIG_MFD_WM8997=y CONFIG_MFD_WM8998=y CONFIG_MFD_WM8400=y CONFIG_MFD_WM831X=y CONFIG_MFD_WM831X_I2C=y CONFIG_MFD_WM831X_SPI=y CONFIG_MFD_WM8350=y CONFIG_MFD_WM8350_I2C=y CONFIG_MFD_WM8994=y CONFIG_MFD_ROHM_BD718XX=y CONFIG_MFD_ROHM_BD71828=y CONFIG_MFD_ROHM_BD957XMUF=y CONFIG_MFD_STPMIC1=y CONFIG_MFD_STMFX=y CONFIG_MFD_WCD934X=y CONFIG_MFD_ATC260X=y CONFIG_MFD_ATC260X_I2C=y CONFIG_MFD_QCOM_PM8008=y CONFIG_RAVE_SP_CORE=y CONFIG_MFD_INTEL_M10_BMC=y CONFIG_MFD_RSMU_I2C=y CONFIG_MFD_RSMU_SPI=y # end of Multifunction device drivers CONFIG_REGULATOR=y CONFIG_REGULATOR_DEBUG=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_VIRTUAL_CONSUMER=y CONFIG_REGULATOR_USERSPACE_CONSUMER=y CONFIG_REGULATOR_88PG86X=y CONFIG_REGULATOR_88PM800=y CONFIG_REGULATOR_88PM8607=y CONFIG_REGULATOR_ACT8865=y CONFIG_REGULATOR_ACT8945A=y CONFIG_REGULATOR_AD5398=y CONFIG_REGULATOR_AAT2870=y CONFIG_REGULATOR_ARIZONA_LDO1=y CONFIG_REGULATOR_ARIZONA_MICSUPP=y CONFIG_REGULATOR_AS3711=y CONFIG_REGULATOR_AS3722=y CONFIG_REGULATOR_ATC260X=y CONFIG_REGULATOR_AXP20X=y CONFIG_REGULATOR_BCM590XX=y CONFIG_REGULATOR_BD71815=y CONFIG_REGULATOR_BD71828=y CONFIG_REGULATOR_BD718XX=y CONFIG_REGULATOR_BD9571MWV=y CONFIG_REGULATOR_BD957XMUF=y CONFIG_REGULATOR_CPCAP=y CONFIG_REGULATOR_CROS_EC=y CONFIG_REGULATOR_DA903X=y CONFIG_REGULATOR_DA9052=y CONFIG_REGULATOR_DA9055=y CONFIG_REGULATOR_DA9062=y CONFIG_REGULATOR_DA9063=y CONFIG_REGULATOR_DA9121=y CONFIG_REGULATOR_DA9210=y CONFIG_REGULATOR_DA9211=y CONFIG_REGULATOR_FAN53555=y CONFIG_REGULATOR_FAN53880=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_HI6421=y CONFIG_REGULATOR_HI6421V530=y CONFIG_REGULATOR_HI6421V600=y CONFIG_REGULATOR_ISL9305=y CONFIG_REGULATOR_ISL6271A=y CONFIG_REGULATOR_LM363X=y CONFIG_REGULATOR_LOCHNAGAR=y CONFIG_REGULATOR_LP3971=y CONFIG_REGULATOR_LP3972=y CONFIG_REGULATOR_LP872X=y CONFIG_REGULATOR_LP873X=y CONFIG_REGULATOR_LP8755=y CONFIG_REGULATOR_LP87565=y CONFIG_REGULATOR_LP8788=y CONFIG_REGULATOR_LTC3589=y CONFIG_REGULATOR_LTC3676=y CONFIG_REGULATOR_MAX14577=y CONFIG_REGULATOR_MAX1586=y CONFIG_REGULATOR_MAX77620=y CONFIG_REGULATOR_MAX77650=y CONFIG_REGULATOR_MAX8649=y CONFIG_REGULATOR_MAX8660=y CONFIG_REGULATOR_MAX8893=y CONFIG_REGULATOR_MAX8907=y CONFIG_REGULATOR_MAX8925=y CONFIG_REGULATOR_MAX8952=y CONFIG_REGULATOR_MAX8973=y CONFIG_REGULATOR_MAX8997=y CONFIG_REGULATOR_MAX8998=y CONFIG_REGULATOR_MAX20086=y CONFIG_REGULATOR_MAX77686=y CONFIG_REGULATOR_MAX77693=y CONFIG_REGULATOR_MAX77802=y CONFIG_REGULATOR_MAX77826=y CONFIG_REGULATOR_MC13XXX_CORE=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y CONFIG_REGULATOR_MCP16502=y CONFIG_REGULATOR_MP5416=y CONFIG_REGULATOR_MP8859=y CONFIG_REGULATOR_MP886X=y CONFIG_REGULATOR_MPQ7920=y CONFIG_REGULATOR_MT6311=y CONFIG_REGULATOR_MT6315=y CONFIG_REGULATOR_MT6323=y CONFIG_REGULATOR_MT6331=y CONFIG_REGULATOR_MT6332=y CONFIG_REGULATOR_MT6358=y CONFIG_REGULATOR_MT6359=y CONFIG_REGULATOR_MT6360=y CONFIG_REGULATOR_MT6370=y CONFIG_REGULATOR_MT6397=y CONFIG_REGULATOR_PALMAS=y CONFIG_REGULATOR_PCA9450=y CONFIG_REGULATOR_PCAP=y CONFIG_REGULATOR_PCF50633=y CONFIG_REGULATOR_PF8X00=y CONFIG_REGULATOR_PFUZE100=y CONFIG_REGULATOR_PV88060=y CONFIG_REGULATOR_PV88080=y CONFIG_REGULATOR_PV88090=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_REGULATOR_QCOM_USB_VBUS=y CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=y CONFIG_REGULATOR_RC5T583=y CONFIG_REGULATOR_RK808=y CONFIG_REGULATOR_RN5T618=y CONFIG_REGULATOR_ROHM=y CONFIG_REGULATOR_RT4801=y CONFIG_REGULATOR_RT4831=y CONFIG_REGULATOR_RT5033=y CONFIG_REGULATOR_RT5120=y CONFIG_REGULATOR_RT5190A=y CONFIG_REGULATOR_RT5759=y CONFIG_REGULATOR_RT6160=y CONFIG_REGULATOR_RT6245=y CONFIG_REGULATOR_RTQ2134=y CONFIG_REGULATOR_RTMV20=y CONFIG_REGULATOR_RTQ6752=y CONFIG_REGULATOR_S2MPA01=y CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_SKY81452=y CONFIG_REGULATOR_SLG51000=y CONFIG_REGULATOR_STPMIC1=y CONFIG_REGULATOR_SY7636A=y CONFIG_REGULATOR_SY8106A=y CONFIG_REGULATOR_SY8824X=y CONFIG_REGULATOR_SY8827N=y CONFIG_REGULATOR_TPS51632=y CONFIG_REGULATOR_TPS6105X=y CONFIG_REGULATOR_TPS62360=y CONFIG_REGULATOR_TPS6286X=y CONFIG_REGULATOR_TPS65023=y CONFIG_REGULATOR_TPS6507X=y CONFIG_REGULATOR_TPS65086=y CONFIG_REGULATOR_TPS65090=y CONFIG_REGULATOR_TPS65132=y CONFIG_REGULATOR_TPS65217=y CONFIG_REGULATOR_TPS65218=y CONFIG_REGULATOR_TPS6524X=y CONFIG_REGULATOR_TPS6586X=y CONFIG_REGULATOR_TPS65910=y CONFIG_REGULATOR_TPS65912=y CONFIG_REGULATOR_TPS68470=y CONFIG_REGULATOR_TWL4030=y CONFIG_REGULATOR_VCTRL=y CONFIG_REGULATOR_WM831X=y CONFIG_REGULATOR_WM8350=y CONFIG_REGULATOR_WM8400=y CONFIG_REGULATOR_WM8994=y CONFIG_REGULATOR_QCOM_LABIBB=y CONFIG_RC_CORE=y CONFIG_BPF_LIRC_MODE2=y CONFIG_LIRC=y CONFIG_RC_MAP=y CONFIG_RC_DECODERS=y CONFIG_IR_IMON_DECODER=y CONFIG_IR_JVC_DECODER=y CONFIG_IR_MCE_KBD_DECODER=y CONFIG_IR_NEC_DECODER=y CONFIG_IR_RC5_DECODER=y CONFIG_IR_RC6_DECODER=y CONFIG_IR_RCMM_DECODER=y CONFIG_IR_SANYO_DECODER=y CONFIG_IR_SHARP_DECODER=y CONFIG_IR_SONY_DECODER=y CONFIG_IR_XMP_DECODER=y CONFIG_RC_DEVICES=y CONFIG_IR_ENE=y CONFIG_IR_FINTEK=y CONFIG_IR_GPIO_CIR=y CONFIG_IR_GPIO_TX=y CONFIG_IR_HIX5HD2=y CONFIG_IR_IGORPLUGUSB=y CONFIG_IR_IGUANA=y CONFIG_IR_IMON=y CONFIG_IR_IMON_RAW=y CONFIG_IR_ITE_CIR=y CONFIG_IR_MCEUSB=y CONFIG_IR_NUVOTON=y CONFIG_IR_PWM_TX=y CONFIG_IR_REDRAT3=y CONFIG_IR_SERIAL=y CONFIG_IR_SERIAL_TRANSMITTER=y CONFIG_IR_SPI=y CONFIG_IR_STREAMZAP=y CONFIG_IR_TOY=y CONFIG_IR_TTUSBIR=y CONFIG_IR_WINBOND_CIR=y CONFIG_RC_ATI_REMOTE=y CONFIG_RC_LOOPBACK=y CONFIG_RC_XBOX_DVD=y CONFIG_CEC_CORE=y CONFIG_CEC_NOTIFIER=y CONFIG_CEC_PIN=y # # CEC support # CONFIG_MEDIA_CEC_RC=y CONFIG_CEC_PIN_ERROR_INJ=y CONFIG_MEDIA_CEC_SUPPORT=y CONFIG_CEC_CH7322=y CONFIG_CEC_CROS_EC=y CONFIG_CEC_GPIO=y CONFIG_CEC_SECO=y CONFIG_CEC_SECO_RC=y CONFIG_USB_PULSE8_CEC=y CONFIG_USB_RAINSHADOW_CEC=y # end of CEC support CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_SUPPORT_FILTER=y CONFIG_MEDIA_SUBDRV_AUTOSELECT=y # # Media device types # CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_ANALOG_TV_SUPPORT=y CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y CONFIG_MEDIA_RADIO_SUPPORT=y CONFIG_MEDIA_SDR_SUPPORT=y CONFIG_MEDIA_PLATFORM_SUPPORT=y CONFIG_MEDIA_TEST_SUPPORT=y # end of Media device types CONFIG_VIDEO_DEV=y CONFIG_MEDIA_CONTROLLER=y CONFIG_DVB_CORE=y # # Video4Linux options # CONFIG_VIDEO_V4L2_I2C=y CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_ADV_DEBUG=y CONFIG_VIDEO_FIXED_MINOR_RANGES=y CONFIG_VIDEO_TUNER=y CONFIG_V4L2_MEM2MEM_DEV=y CONFIG_V4L2_FLASH_LED_CLASS=y CONFIG_V4L2_FWNODE=y CONFIG_V4L2_ASYNC=y CONFIG_VIDEOBUF_GEN=y CONFIG_VIDEOBUF_DMA_SG=y CONFIG_VIDEOBUF_VMALLOC=y # end of Video4Linux options # # Media controller options # CONFIG_MEDIA_CONTROLLER_DVB=y CONFIG_MEDIA_CONTROLLER_REQUEST_API=y # end of Media controller options # # Digital TV options # CONFIG_DVB_MMAP=y CONFIG_DVB_NET=y CONFIG_DVB_MAX_ADAPTERS=16 CONFIG_DVB_DYNAMIC_MINORS=y CONFIG_DVB_DEMUX_SECTION_LOSS_LOG=y CONFIG_DVB_ULE_DEBUG=y # end of Digital TV options # # Media drivers # # # Drivers filtered as selected at 'Filter media drivers' # # # Media drivers # CONFIG_MEDIA_USB_SUPPORT=y # # Webcam devices # CONFIG_USB_GSPCA=y CONFIG_USB_GSPCA_BENQ=y CONFIG_USB_GSPCA_CONEX=y CONFIG_USB_GSPCA_CPIA1=y CONFIG_USB_GSPCA_DTCS033=y CONFIG_USB_GSPCA_ETOMS=y CONFIG_USB_GSPCA_FINEPIX=y CONFIG_USB_GSPCA_JEILINJ=y CONFIG_USB_GSPCA_JL2005BCD=y CONFIG_USB_GSPCA_KINECT=y CONFIG_USB_GSPCA_KONICA=y CONFIG_USB_GSPCA_MARS=y CONFIG_USB_GSPCA_MR97310A=y CONFIG_USB_GSPCA_NW80X=y CONFIG_USB_GSPCA_OV519=y CONFIG_USB_GSPCA_OV534=y CONFIG_USB_GSPCA_OV534_9=y CONFIG_USB_GSPCA_PAC207=y CONFIG_USB_GSPCA_PAC7302=y CONFIG_USB_GSPCA_PAC7311=y CONFIG_USB_GSPCA_SE401=y CONFIG_USB_GSPCA_SN9C2028=y CONFIG_USB_GSPCA_SN9C20X=y CONFIG_USB_GSPCA_SONIXB=y CONFIG_USB_GSPCA_SONIXJ=y CONFIG_USB_GSPCA_SPCA1528=y CONFIG_USB_GSPCA_SPCA500=y CONFIG_USB_GSPCA_SPCA501=y CONFIG_USB_GSPCA_SPCA505=y CONFIG_USB_GSPCA_SPCA506=y CONFIG_USB_GSPCA_SPCA508=y CONFIG_USB_GSPCA_SPCA561=y CONFIG_USB_GSPCA_SQ905=y CONFIG_USB_GSPCA_SQ905C=y CONFIG_USB_GSPCA_SQ930X=y CONFIG_USB_GSPCA_STK014=y CONFIG_USB_GSPCA_STK1135=y CONFIG_USB_GSPCA_STV0680=y CONFIG_USB_GSPCA_SUNPLUS=y CONFIG_USB_GSPCA_T613=y CONFIG_USB_GSPCA_TOPRO=y CONFIG_USB_GSPCA_TOUPTEK=y CONFIG_USB_GSPCA_TV8532=y CONFIG_USB_GSPCA_VC032X=y CONFIG_USB_GSPCA_VICAM=y CONFIG_USB_GSPCA_XIRLINK_CIT=y CONFIG_USB_GSPCA_ZC3XX=y CONFIG_USB_GL860=y CONFIG_USB_M5602=y CONFIG_USB_STV06XX=y CONFIG_USB_PWC=y CONFIG_USB_PWC_DEBUG=y CONFIG_USB_PWC_INPUT_EVDEV=y CONFIG_USB_S2255=y CONFIG_VIDEO_USBTV=y CONFIG_USB_VIDEO_CLASS=y CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y # # Analog TV USB devices # CONFIG_VIDEO_GO7007=y CONFIG_VIDEO_GO7007_USB=y CONFIG_VIDEO_GO7007_LOADER=y CONFIG_VIDEO_GO7007_USB_S2250_BOARD=y CONFIG_VIDEO_HDPVR=y CONFIG_VIDEO_PVRUSB2=y CONFIG_VIDEO_PVRUSB2_SYSFS=y CONFIG_VIDEO_PVRUSB2_DVB=y CONFIG_VIDEO_PVRUSB2_DEBUGIFC=y CONFIG_VIDEO_STK1160_COMMON=y CONFIG_VIDEO_STK1160=y # # Analog/digital TV USB devices # CONFIG_VIDEO_AU0828=y CONFIG_VIDEO_AU0828_V4L2=y CONFIG_VIDEO_AU0828_RC=y CONFIG_VIDEO_CX231XX=y CONFIG_VIDEO_CX231XX_RC=y CONFIG_VIDEO_CX231XX_ALSA=y CONFIG_VIDEO_CX231XX_DVB=y # # Digital TV USB devices # CONFIG_DVB_AS102=y CONFIG_DVB_B2C2_FLEXCOP_USB=y CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG=y CONFIG_DVB_USB_V2=y CONFIG_DVB_USB_AF9015=y CONFIG_DVB_USB_AF9035=y CONFIG_DVB_USB_ANYSEE=y CONFIG_DVB_USB_AU6610=y CONFIG_DVB_USB_AZ6007=y CONFIG_DVB_USB_CE6230=y CONFIG_DVB_USB_DVBSKY=y CONFIG_DVB_USB_EC168=y CONFIG_DVB_USB_GL861=y CONFIG_DVB_USB_LME2510=y CONFIG_DVB_USB_MXL111SF=y CONFIG_DVB_USB_RTL28XXU=y CONFIG_DVB_USB_ZD1301=y CONFIG_DVB_USB=y CONFIG_DVB_USB_DEBUG=y CONFIG_DVB_USB_A800=y CONFIG_DVB_USB_AF9005=y CONFIG_DVB_USB_AF9005_REMOTE=y CONFIG_DVB_USB_AZ6027=y CONFIG_DVB_USB_CINERGY_T2=y CONFIG_DVB_USB_CXUSB=y CONFIG_DVB_USB_CXUSB_ANALOG=y CONFIG_DVB_USB_DIB0700=y CONFIG_DVB_USB_DIB3000MC=y CONFIG_DVB_USB_DIBUSB_MB=y CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y CONFIG_DVB_USB_DIBUSB_MC=y CONFIG_DVB_USB_DIGITV=y CONFIG_DVB_USB_DTT200U=y CONFIG_DVB_USB_DTV5100=y CONFIG_DVB_USB_DW2102=y CONFIG_DVB_USB_GP8PSK=y CONFIG_DVB_USB_M920X=y CONFIG_DVB_USB_NOVA_T_USB2=y CONFIG_DVB_USB_OPERA1=y CONFIG_DVB_USB_PCTV452E=y CONFIG_DVB_USB_TECHNISAT_USB2=y CONFIG_DVB_USB_TTUSB2=y CONFIG_DVB_USB_UMT_010=y CONFIG_DVB_USB_VP702X=y CONFIG_DVB_USB_VP7045=y CONFIG_SMS_USB_DRV=y CONFIG_DVB_TTUSB_BUDGET=y CONFIG_DVB_TTUSB_DEC=y # # Webcam, TV (analog/digital) USB devices # CONFIG_VIDEO_EM28XX=y CONFIG_VIDEO_EM28XX_V4L2=y CONFIG_VIDEO_EM28XX_ALSA=y CONFIG_VIDEO_EM28XX_DVB=y CONFIG_VIDEO_EM28XX_RC=y # # Software defined radio USB devices # CONFIG_USB_AIRSPY=y CONFIG_USB_HACKRF=y CONFIG_USB_MSI2500=y CONFIG_MEDIA_PCI_SUPPORT=y # # Media capture support # CONFIG_VIDEO_SOLO6X10=y CONFIG_STA2X11_VIP=y CONFIG_VIDEO_TW5864=y CONFIG_VIDEO_TW68=y CONFIG_VIDEO_TW686X=y CONFIG_VIDEO_ZORAN=y CONFIG_VIDEO_ZORAN_DC30=y CONFIG_VIDEO_ZORAN_ZR36060=y CONFIG_VIDEO_ZORAN_BUZ=y CONFIG_VIDEO_ZORAN_DC10=y CONFIG_VIDEO_ZORAN_LML33=y CONFIG_VIDEO_ZORAN_LML33R10=y CONFIG_VIDEO_ZORAN_AVS6EYES=y # # Media capture/analog TV support # CONFIG_VIDEO_DT3155=y CONFIG_VIDEO_IVTV=y CONFIG_VIDEO_IVTV_ALSA=y CONFIG_VIDEO_FB_IVTV=y CONFIG_VIDEO_FB_IVTV_FORCE_PAT=y # # Media capture/analog/hybrid TV support # CONFIG_VIDEO_BT848=y CONFIG_DVB_BT8XX=y CONFIG_VIDEO_CX18=y CONFIG_VIDEO_CX18_ALSA=y CONFIG_VIDEO_CX23885=y CONFIG_MEDIA_ALTERA_CI=y CONFIG_VIDEO_CX25821=y CONFIG_VIDEO_CX25821_ALSA=y CONFIG_VIDEO_CX88=y CONFIG_VIDEO_CX88_ALSA=y CONFIG_VIDEO_CX88_BLACKBIRD=y CONFIG_VIDEO_CX88_DVB=y CONFIG_VIDEO_CX88_ENABLE_VP3054=y CONFIG_VIDEO_CX88_VP3054=y CONFIG_VIDEO_CX88_MPEG=y CONFIG_VIDEO_SAA7134=y CONFIG_VIDEO_SAA7134_ALSA=y CONFIG_VIDEO_SAA7134_RC=y CONFIG_VIDEO_SAA7134_DVB=y CONFIG_VIDEO_SAA7134_GO7007=y CONFIG_VIDEO_SAA7164=y # # Media digital TV PCI Adapters # CONFIG_DVB_B2C2_FLEXCOP_PCI=y CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG=y CONFIG_DVB_DDBRIDGE=y CONFIG_DVB_DDBRIDGE_MSIENABLE=y CONFIG_DVB_DM1105=y CONFIG_MANTIS_CORE=y CONFIG_DVB_MANTIS=y CONFIG_DVB_HOPPER=y CONFIG_DVB_NETUP_UNIDVB=y CONFIG_DVB_NGENE=y CONFIG_DVB_PLUTO2=y CONFIG_DVB_PT1=y CONFIG_DVB_PT3=y CONFIG_DVB_SMIPCIE=y CONFIG_VIDEO_PCI_SKELETON=y CONFIG_VIDEO_IPU3_CIO2=y CONFIG_CIO2_BRIDGE=y CONFIG_RADIO_ADAPTERS=y CONFIG_RADIO_MAXIRADIO=y CONFIG_RADIO_SAA7706H=y CONFIG_RADIO_SHARK=y CONFIG_RADIO_SHARK2=y CONFIG_RADIO_SI4713=y CONFIG_RADIO_SI476X=y CONFIG_RADIO_TEA575X=y CONFIG_RADIO_TEA5764=y CONFIG_RADIO_TEA5764_XTAL=y CONFIG_RADIO_TEF6862=y CONFIG_RADIO_TIMBERDALE=y CONFIG_RADIO_WL1273=y CONFIG_USB_DSBR=y CONFIG_USB_KEENE=y CONFIG_USB_MA901=y CONFIG_USB_MR800=y CONFIG_USB_RAREMONO=y CONFIG_RADIO_SI470X=y CONFIG_USB_SI470X=y CONFIG_I2C_SI470X=y CONFIG_USB_SI4713=y CONFIG_PLATFORM_SI4713=y CONFIG_I2C_SI4713=y CONFIG_RADIO_WL128X=y CONFIG_V4L_RADIO_ISA_DRIVERS=y CONFIG_RADIO_AZTECH=y CONFIG_RADIO_AZTECH_PORT=350 CONFIG_RADIO_CADET=y CONFIG_RADIO_GEMTEK=y CONFIG_RADIO_GEMTEK_PORT=34c CONFIG_RADIO_GEMTEK_PROBE=y CONFIG_RADIO_ISA=y CONFIG_RADIO_MIROPCM20=y CONFIG_RADIO_RTRACK=y CONFIG_RADIO_RTRACK2=y CONFIG_RADIO_RTRACK2_PORT=30c CONFIG_RADIO_RTRACK_PORT=30f CONFIG_RADIO_SF16FMI=y CONFIG_RADIO_SF16FMR2=y CONFIG_RADIO_TERRATEC=y CONFIG_RADIO_TRUST=y CONFIG_RADIO_TRUST_PORT=350 CONFIG_RADIO_TYPHOON=y CONFIG_RADIO_TYPHOON_MUTEFREQ=87500 CONFIG_RADIO_TYPHOON_PORT=316 CONFIG_RADIO_ZOLTRIX=y CONFIG_RADIO_ZOLTRIX_PORT=20c CONFIG_MEDIA_PLATFORM_DRIVERS=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_SDR_PLATFORM_DRIVERS=y CONFIG_DVB_PLATFORM_DRIVERS=y CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y CONFIG_VIDEO_MUX=y # # Allegro DVT media platform drivers # # # Amlogic media platform drivers # # # Amphion drivers # # # Aspeed media platform drivers # CONFIG_VIDEO_ASPEED=y # # Atmel media platform drivers # # # Cadence media platform drivers # CONFIG_VIDEO_CADENCE_CSI2RX=y CONFIG_VIDEO_CADENCE_CSI2TX=y # # Chips&Media media platform drivers # # # Intel media platform drivers # # # Marvell media platform drivers # CONFIG_VIDEO_CAFE_CCIC=y # # Mediatek media platform drivers # # # NVidia media platform drivers # # # NXP media platform drivers # # # Qualcomm media platform drivers # # # Renesas media platform drivers # # # Rockchip media platform drivers # # # Samsung media platform drivers # # # STMicroelectronics media platform drivers # # # Sunxi media platform drivers # # # Texas Instruments drivers # # # Verisilicon media platform drivers # # # VIA media platform drivers # CONFIG_VIDEO_VIA_CAMERA=y # # Xilinx media platform drivers # CONFIG_VIDEO_XILINX=y CONFIG_VIDEO_XILINX_CSI2RXSS=y CONFIG_VIDEO_XILINX_TPG=y CONFIG_VIDEO_XILINX_VTC=y # # MMC/SDIO DVB adapters # CONFIG_SMS_SDIO_DRV=y CONFIG_V4L_TEST_DRIVERS=y CONFIG_VIDEO_VIM2M=y CONFIG_VIDEO_VICODEC=y CONFIG_VIDEO_VIMC=y CONFIG_VIDEO_VIVID=y CONFIG_VIDEO_VIVID_CEC=y CONFIG_VIDEO_VIVID_MAX_DEVS=64 CONFIG_DVB_TEST_DRIVERS=y CONFIG_DVB_VIDTV=y # # FireWire (IEEE 1394) Adapters # CONFIG_DVB_FIREDTV=y CONFIG_DVB_FIREDTV_INPUT=y CONFIG_MEDIA_COMMON_OPTIONS=y # # common driver options # CONFIG_CYPRESS_FIRMWARE=y CONFIG_TTPCI_EEPROM=y CONFIG_VIDEO_CX2341X=y CONFIG_VIDEO_TVEEPROM=y CONFIG_DVB_B2C2_FLEXCOP=y CONFIG_DVB_B2C2_FLEXCOP_DEBUG=y CONFIG_SMS_SIANO_MDTV=y CONFIG_SMS_SIANO_RC=y CONFIG_SMS_SIANO_DEBUGFS=y CONFIG_VIDEO_V4L2_TPG=y CONFIG_VIDEOBUF2_CORE=y CONFIG_VIDEOBUF2_V4L2=y CONFIG_VIDEOBUF2_MEMOPS=y CONFIG_VIDEOBUF2_DMA_CONTIG=y CONFIG_VIDEOBUF2_VMALLOC=y CONFIG_VIDEOBUF2_DMA_SG=y CONFIG_VIDEOBUF2_DVB=y # end of Media drivers # # Media ancillary drivers # CONFIG_MEDIA_ATTACH=y # # IR I2C driver auto-selected by 'Autoselect ancillary drivers' # CONFIG_VIDEO_IR_I2C=y # # Camera sensor devices # CONFIG_VIDEO_APTINA_PLL=y CONFIG_VIDEO_CCS_PLL=y CONFIG_VIDEO_AR0521=y CONFIG_VIDEO_HI556=y CONFIG_VIDEO_HI846=y CONFIG_VIDEO_HI847=y CONFIG_VIDEO_IMX208=y CONFIG_VIDEO_IMX214=y CONFIG_VIDEO_IMX219=y CONFIG_VIDEO_IMX258=y CONFIG_VIDEO_IMX274=y CONFIG_VIDEO_IMX290=y CONFIG_VIDEO_IMX319=y CONFIG_VIDEO_IMX334=y CONFIG_VIDEO_IMX335=y CONFIG_VIDEO_IMX355=y CONFIG_VIDEO_IMX412=y CONFIG_VIDEO_MAX9271_LIB=y CONFIG_VIDEO_MT9M001=y CONFIG_VIDEO_MT9M032=y CONFIG_VIDEO_MT9M111=y CONFIG_VIDEO_MT9P031=y CONFIG_VIDEO_MT9T001=y CONFIG_VIDEO_MT9T112=y CONFIG_VIDEO_MT9V011=y CONFIG_VIDEO_MT9V032=y CONFIG_VIDEO_MT9V111=y CONFIG_VIDEO_NOON010PC30=y CONFIG_VIDEO_OG01A1B=y CONFIG_VIDEO_OV02A10=y CONFIG_VIDEO_OV08D10=y CONFIG_VIDEO_OV13858=y CONFIG_VIDEO_OV13B10=y CONFIG_VIDEO_OV2640=y CONFIG_VIDEO_OV2659=y CONFIG_VIDEO_OV2680=y CONFIG_VIDEO_OV2685=y CONFIG_VIDEO_OV2740=y CONFIG_VIDEO_OV5640=y CONFIG_VIDEO_OV5645=y CONFIG_VIDEO_OV5647=y CONFIG_VIDEO_OV5648=y CONFIG_VIDEO_OV5670=y CONFIG_VIDEO_OV5675=y CONFIG_VIDEO_OV5693=y CONFIG_VIDEO_OV5695=y CONFIG_VIDEO_OV6650=y CONFIG_VIDEO_OV7251=y CONFIG_VIDEO_OV7640=y CONFIG_VIDEO_OV7670=y CONFIG_VIDEO_OV772X=y CONFIG_VIDEO_OV7740=y CONFIG_VIDEO_OV8856=y CONFIG_VIDEO_OV8865=y CONFIG_VIDEO_OV9282=y CONFIG_VIDEO_OV9640=y CONFIG_VIDEO_OV9650=y CONFIG_VIDEO_OV9734=y CONFIG_VIDEO_RDACM20=y CONFIG_VIDEO_RDACM21=y CONFIG_VIDEO_RJ54N1=y CONFIG_VIDEO_S5C73M3=y CONFIG_VIDEO_S5K4ECGX=y CONFIG_VIDEO_S5K5BAF=y CONFIG_VIDEO_S5K6A3=y CONFIG_VIDEO_S5K6AA=y CONFIG_VIDEO_SR030PC30=y CONFIG_VIDEO_VS6624=y CONFIG_VIDEO_CCS=y CONFIG_VIDEO_ET8EK8=y CONFIG_VIDEO_M5MOLS=y # end of Camera sensor devices # # Lens drivers # CONFIG_VIDEO_AD5820=y CONFIG_VIDEO_AK7375=y CONFIG_VIDEO_DW9714=y CONFIG_VIDEO_DW9768=y CONFIG_VIDEO_DW9807_VCM=y # end of Lens drivers # # Flash devices # CONFIG_VIDEO_ADP1653=y CONFIG_VIDEO_LM3560=y CONFIG_VIDEO_LM3646=y # end of Flash devices # # Audio decoders, processors and mixers # CONFIG_VIDEO_CS3308=y CONFIG_VIDEO_CS5345=y CONFIG_VIDEO_CS53L32A=y CONFIG_VIDEO_MSP3400=y CONFIG_VIDEO_SONY_BTF_MPX=y CONFIG_VIDEO_TDA1997X=y CONFIG_VIDEO_TDA7432=y CONFIG_VIDEO_TDA9840=y CONFIG_VIDEO_TEA6415C=y CONFIG_VIDEO_TEA6420=y CONFIG_VIDEO_TLV320AIC23B=y CONFIG_VIDEO_TVAUDIO=y CONFIG_VIDEO_UDA1342=y CONFIG_VIDEO_VP27SMPX=y CONFIG_VIDEO_WM8739=y CONFIG_VIDEO_WM8775=y # end of Audio decoders, processors and mixers # # RDS decoders # CONFIG_VIDEO_SAA6588=y # end of RDS decoders # # Video decoders # CONFIG_VIDEO_ADV7180=y CONFIG_VIDEO_ADV7183=y CONFIG_VIDEO_ADV748X=y CONFIG_VIDEO_ADV7604=y CONFIG_VIDEO_ADV7604_CEC=y CONFIG_VIDEO_ADV7842=y CONFIG_VIDEO_ADV7842_CEC=y CONFIG_VIDEO_BT819=y CONFIG_VIDEO_BT856=y CONFIG_VIDEO_BT866=y CONFIG_VIDEO_ISL7998X=y CONFIG_VIDEO_KS0127=y CONFIG_VIDEO_MAX9286=y CONFIG_VIDEO_ML86V7667=y CONFIG_VIDEO_SAA7110=y CONFIG_VIDEO_SAA711X=y CONFIG_VIDEO_TC358743=y CONFIG_VIDEO_TC358743_CEC=y CONFIG_VIDEO_TVP514X=y CONFIG_VIDEO_TVP5150=y CONFIG_VIDEO_TVP7002=y CONFIG_VIDEO_TW2804=y CONFIG_VIDEO_TW9903=y CONFIG_VIDEO_TW9906=y CONFIG_VIDEO_TW9910=y CONFIG_VIDEO_VPX3220=y # # Video and audio decoders # CONFIG_VIDEO_SAA717X=y CONFIG_VIDEO_CX25840=y # end of Video decoders # # Video encoders # CONFIG_VIDEO_AD9389B=y CONFIG_VIDEO_ADV7170=y CONFIG_VIDEO_ADV7175=y CONFIG_VIDEO_ADV7343=y CONFIG_VIDEO_ADV7393=y CONFIG_VIDEO_AK881X=y CONFIG_VIDEO_SAA7127=y CONFIG_VIDEO_SAA7185=y CONFIG_VIDEO_THS8200=y # end of Video encoders # # Video improvement chips # CONFIG_VIDEO_UPD64031A=y CONFIG_VIDEO_UPD64083=y # end of Video improvement chips # # Audio/Video compression chips # CONFIG_VIDEO_SAA6752HS=y # end of Audio/Video compression chips # # SDR tuner chips # CONFIG_SDR_MAX2175=y # end of SDR tuner chips # # Miscellaneous helper chips # CONFIG_VIDEO_I2C=y CONFIG_VIDEO_M52790=y CONFIG_VIDEO_ST_MIPID02=y CONFIG_VIDEO_THS7303=y # end of Miscellaneous helper chips # # Media SPI Adapters # CONFIG_CXD2880_SPI_DRV=y CONFIG_VIDEO_GS1662=y # end of Media SPI Adapters CONFIG_MEDIA_TUNER=y # # Customize TV tuners # CONFIG_MEDIA_TUNER_E4000=y CONFIG_MEDIA_TUNER_FC0011=y CONFIG_MEDIA_TUNER_FC0012=y CONFIG_MEDIA_TUNER_FC0013=y CONFIG_MEDIA_TUNER_FC2580=y CONFIG_MEDIA_TUNER_IT913X=y CONFIG_MEDIA_TUNER_M88RS6000T=y CONFIG_MEDIA_TUNER_MAX2165=y CONFIG_MEDIA_TUNER_MC44S803=y CONFIG_MEDIA_TUNER_MSI001=y CONFIG_MEDIA_TUNER_MT2060=y CONFIG_MEDIA_TUNER_MT2063=y CONFIG_MEDIA_TUNER_MT20XX=y CONFIG_MEDIA_TUNER_MT2131=y CONFIG_MEDIA_TUNER_MT2266=y CONFIG_MEDIA_TUNER_MXL301RF=y CONFIG_MEDIA_TUNER_MXL5005S=y CONFIG_MEDIA_TUNER_MXL5007T=y CONFIG_MEDIA_TUNER_QM1D1B0004=y CONFIG_MEDIA_TUNER_QM1D1C0042=y CONFIG_MEDIA_TUNER_QT1010=y CONFIG_MEDIA_TUNER_R820T=y CONFIG_MEDIA_TUNER_SI2157=y CONFIG_MEDIA_TUNER_SIMPLE=y CONFIG_MEDIA_TUNER_TDA18212=y CONFIG_MEDIA_TUNER_TDA18218=y CONFIG_MEDIA_TUNER_TDA18250=y CONFIG_MEDIA_TUNER_TDA18271=y CONFIG_MEDIA_TUNER_TDA827X=y CONFIG_MEDIA_TUNER_TDA8290=y CONFIG_MEDIA_TUNER_TDA9887=y CONFIG_MEDIA_TUNER_TEA5761=y CONFIG_MEDIA_TUNER_TEA5767=y CONFIG_MEDIA_TUNER_TUA9001=y CONFIG_MEDIA_TUNER_XC2028=y CONFIG_MEDIA_TUNER_XC4000=y CONFIG_MEDIA_TUNER_XC5000=y # end of Customize TV tuners # # Customise DVB Frontends # # # Multistandard (satellite) frontends # CONFIG_DVB_M88DS3103=y CONFIG_DVB_MXL5XX=y CONFIG_DVB_STB0899=y CONFIG_DVB_STB6100=y CONFIG_DVB_STV090x=y CONFIG_DVB_STV0910=y CONFIG_DVB_STV6110x=y CONFIG_DVB_STV6111=y # # Multistandard (cable + terrestrial) frontends # CONFIG_DVB_DRXK=y CONFIG_DVB_MN88472=y CONFIG_DVB_MN88473=y CONFIG_DVB_SI2165=y CONFIG_DVB_TDA18271C2DD=y # # DVB-S (satellite) frontends # CONFIG_DVB_CX24110=y CONFIG_DVB_CX24116=y CONFIG_DVB_CX24117=y CONFIG_DVB_CX24120=y CONFIG_DVB_CX24123=y CONFIG_DVB_DS3000=y CONFIG_DVB_MB86A16=y CONFIG_DVB_MT312=y CONFIG_DVB_S5H1420=y CONFIG_DVB_SI21XX=y CONFIG_DVB_STB6000=y CONFIG_DVB_STV0288=y CONFIG_DVB_STV0299=y CONFIG_DVB_STV0900=y CONFIG_DVB_STV6110=y CONFIG_DVB_TDA10071=y CONFIG_DVB_TDA10086=y CONFIG_DVB_TDA8083=y CONFIG_DVB_TDA8261=y CONFIG_DVB_TDA826X=y CONFIG_DVB_TS2020=y CONFIG_DVB_TUA6100=y CONFIG_DVB_TUNER_CX24113=y CONFIG_DVB_TUNER_ITD1000=y CONFIG_DVB_VES1X93=y CONFIG_DVB_ZL10036=y CONFIG_DVB_ZL10039=y # # DVB-T (terrestrial) frontends # CONFIG_DVB_AF9013=y CONFIG_DVB_AS102_FE=y CONFIG_DVB_CX22700=y CONFIG_DVB_CX22702=y CONFIG_DVB_CXD2820R=y CONFIG_DVB_CXD2841ER=y CONFIG_DVB_DIB3000MB=y CONFIG_DVB_DIB3000MC=y CONFIG_DVB_DIB7000M=y CONFIG_DVB_DIB7000P=y CONFIG_DVB_DIB9000=y CONFIG_DVB_DRXD=y CONFIG_DVB_EC100=y CONFIG_DVB_GP8PSK_FE=y CONFIG_DVB_L64781=y CONFIG_DVB_MT352=y CONFIG_DVB_NXT6000=y CONFIG_DVB_RTL2830=y CONFIG_DVB_RTL2832=y CONFIG_DVB_RTL2832_SDR=y CONFIG_DVB_S5H1432=y CONFIG_DVB_SI2168=y CONFIG_DVB_SP887X=y CONFIG_DVB_STV0367=y CONFIG_DVB_TDA10048=y CONFIG_DVB_TDA1004X=y CONFIG_DVB_ZD1301_DEMOD=y CONFIG_DVB_ZL10353=y CONFIG_DVB_CXD2880=y # # DVB-C (cable) frontends # CONFIG_DVB_STV0297=y CONFIG_DVB_TDA10021=y CONFIG_DVB_TDA10023=y CONFIG_DVB_VES1820=y # # ATSC (North American/Korean Terrestrial/Cable DTV) frontends # CONFIG_DVB_AU8522=y CONFIG_DVB_AU8522_DTV=y CONFIG_DVB_AU8522_V4L=y CONFIG_DVB_BCM3510=y CONFIG_DVB_LG2160=y CONFIG_DVB_LGDT3305=y CONFIG_DVB_LGDT3306A=y CONFIG_DVB_LGDT330X=y CONFIG_DVB_MXL692=y CONFIG_DVB_NXT200X=y CONFIG_DVB_OR51132=y CONFIG_DVB_OR51211=y CONFIG_DVB_S5H1409=y CONFIG_DVB_S5H1411=y # # ISDB-T (terrestrial) frontends # CONFIG_DVB_DIB8000=y CONFIG_DVB_MB86A20S=y CONFIG_DVB_S921=y # # ISDB-S (satellite) & ISDB-T (terrestrial) frontends # CONFIG_DVB_MN88443X=y CONFIG_DVB_TC90522=y # # Digital terrestrial only tuners/PLL # CONFIG_DVB_PLL=y CONFIG_DVB_TUNER_DIB0070=y CONFIG_DVB_TUNER_DIB0090=y # # SEC control devices for DVB-S # CONFIG_DVB_A8293=y CONFIG_DVB_AF9033=y CONFIG_DVB_ASCOT2E=y CONFIG_DVB_ATBM8830=y CONFIG_DVB_HELENE=y CONFIG_DVB_HORUS3A=y CONFIG_DVB_ISL6405=y CONFIG_DVB_ISL6421=y CONFIG_DVB_ISL6423=y CONFIG_DVB_IX2505V=y CONFIG_DVB_LGS8GL5=y CONFIG_DVB_LGS8GXX=y CONFIG_DVB_LNBH25=y CONFIG_DVB_LNBH29=y CONFIG_DVB_LNBP21=y CONFIG_DVB_LNBP22=y CONFIG_DVB_M88RS2000=y CONFIG_DVB_TDA665x=y CONFIG_DVB_DRX39XYJ=y # # Common Interface (EN50221) controller drivers # CONFIG_DVB_CXD2099=y CONFIG_DVB_SP2=y # end of Customise DVB Frontends # # Tools to develop new frontends # CONFIG_DVB_DUMMY_FE=y # end of Media ancillary drivers # # Graphics support # CONFIG_APERTURE_HELPERS=y CONFIG_AGP=y CONFIG_AGP_ALI=y CONFIG_AGP_ATI=y CONFIG_AGP_AMD=y CONFIG_AGP_AMD64=y CONFIG_AGP_INTEL=y CONFIG_AGP_NVIDIA=y CONFIG_AGP_SIS=y CONFIG_AGP_SWORKS=y CONFIG_AGP_VIA=y CONFIG_AGP_EFFICEON=y CONFIG_INTEL_GTT=y CONFIG_VGA_SWITCHEROO=y CONFIG_DRM=y CONFIG_DRM_MIPI_DBI=y CONFIG_DRM_MIPI_DSI=y CONFIG_DRM_DEBUG_MM=y CONFIG_DRM_USE_DYNAMIC_DEBUG=y CONFIG_DRM_KUNIT_TEST=y CONFIG_DRM_KMS_HELPER=y CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS=y CONFIG_DRM_DEBUG_MODESET_LOCK=y CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM=y CONFIG_DRM_LOAD_EDID_FIRMWARE=y CONFIG_DRM_DP_AUX_BUS=y CONFIG_DRM_DISPLAY_HELPER=y CONFIG_DRM_DISPLAY_DP_HELPER=y CONFIG_DRM_DISPLAY_HDCP_HELPER=y CONFIG_DRM_DISPLAY_HDMI_HELPER=y CONFIG_DRM_DP_AUX_CHARDEV=y CONFIG_DRM_DP_CEC=y CONFIG_DRM_TTM=y CONFIG_DRM_BUDDY=y CONFIG_DRM_VRAM_HELPER=y CONFIG_DRM_TTM_HELPER=y CONFIG_DRM_GEM_DMA_HELPER=y CONFIG_DRM_GEM_SHMEM_HELPER=y CONFIG_DRM_SCHED=y # # I2C encoder or helper chips # CONFIG_DRM_I2C_CH7006=y CONFIG_DRM_I2C_SIL164=y CONFIG_DRM_I2C_NXP_TDA998X=y CONFIG_DRM_I2C_NXP_TDA9950=y # end of I2C encoder or helper chips # # ARM devices # CONFIG_DRM_KOMEDA=y # end of ARM devices CONFIG_DRM_RADEON=y CONFIG_DRM_RADEON_USERPTR=y CONFIG_DRM_AMDGPU=y CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_CIK=y CONFIG_DRM_AMDGPU_USERPTR=y # # ACP (Audio CoProcessor) Configuration # CONFIG_DRM_AMD_ACP=y # end of ACP (Audio CoProcessor) Configuration # # Display Engine Configuration # CONFIG_DRM_AMD_DC=y CONFIG_DRM_AMD_DC_DCN=y CONFIG_DRM_AMD_DC_HDCP=y CONFIG_DRM_AMD_DC_SI=y CONFIG_DEBUG_KERNEL_DC=y CONFIG_DRM_AMD_SECURE_DISPLAY=y # end of Display Engine Configuration CONFIG_DRM_NOUVEAU=y CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT=y CONFIG_NOUVEAU_DEBUG=5 CONFIG_NOUVEAU_DEBUG_DEFAULT=3 CONFIG_NOUVEAU_DEBUG_MMU=y CONFIG_NOUVEAU_DEBUG_PUSH=y CONFIG_DRM_NOUVEAU_BACKLIGHT=y CONFIG_DRM_I915=y CONFIG_DRM_I915_FORCE_PROBE="" CONFIG_DRM_I915_CAPTURE_ERROR=y CONFIG_DRM_I915_COMPRESS_ERROR=y CONFIG_DRM_I915_USERPTR=y CONFIG_DRM_I915_PXP=y # # drm/i915 Debugging # CONFIG_DRM_I915_WERROR=y # CONFIG_DRM_I915_DEBUG is not set CONFIG_DRM_I915_DEBUG_MMIO=y # CONFIG_DRM_I915_DEBUG_GEM is not set CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS=y CONFIG_DRM_I915_SW_FENCE_CHECK_DAG=y CONFIG_DRM_I915_DEBUG_GUC=y CONFIG_DRM_I915_SELFTEST=y CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS=y CONFIG_DRM_I915_DEBUG_VBLANK_EVADE=y CONFIG_DRM_I915_DEBUG_RUNTIME_PM=y # end of drm/i915 Debugging # # drm/i915 Profile Guided Optimisation # CONFIG_DRM_I915_REQUEST_TIMEOUT=20000 CONFIG_DRM_I915_FENCE_TIMEOUT=10000 CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250 CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500 CONFIG_DRM_I915_PREEMPT_TIMEOUT=640 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 CONFIG_DRM_I915_STOP_TIMEOUT=100 CONFIG_DRM_I915_TIMESLICE_DURATION=1 # end of drm/i915 Profile Guided Optimisation CONFIG_DRM_VGEM=y CONFIG_DRM_VKMS=y CONFIG_DRM_VMWGFX=y # CONFIG_DRM_VMWGFX_FBCON is not set CONFIG_DRM_VMWGFX_MKSSTATS=y CONFIG_DRM_GMA500=y CONFIG_DRM_UDL=y CONFIG_DRM_AST=y CONFIG_DRM_MGAG200=y CONFIG_DRM_RCAR_DW_HDMI=y CONFIG_DRM_RCAR_USE_LVDS=y CONFIG_DRM_RCAR_MIPI_DSI=y CONFIG_DRM_QXL=y CONFIG_DRM_VIRTIO_GPU=y CONFIG_DRM_PANEL=y # # Display Panels # CONFIG_DRM_PANEL_ABT_Y030XX067A=y CONFIG_DRM_PANEL_ARM_VERSATILE=y CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=y CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=y CONFIG_DRM_PANEL_BOE_HIMAX8279D=y CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=y CONFIG_DRM_PANEL_DSI_CM=y CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y CONFIG_DRM_PANEL_EBBG_FT8719=y CONFIG_DRM_PANEL_ELIDA_KD35T133=y CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=y CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=y CONFIG_DRM_PANEL_ILITEK_IL9322=y CONFIG_DRM_PANEL_ILITEK_ILI9341=y CONFIG_DRM_PANEL_ILITEK_ILI9881C=y CONFIG_DRM_PANEL_INNOLUX_EJ030NA=y CONFIG_DRM_PANEL_INNOLUX_P079ZCA=y CONFIG_DRM_PANEL_JDI_LT070ME05000=y CONFIG_DRM_PANEL_JDI_R63452=y CONFIG_DRM_PANEL_KHADAS_TS050=y CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=y CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=y CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=y CONFIG_DRM_PANEL_SAMSUNG_LD9040=y CONFIG_DRM_PANEL_LG_LB035Q02=y CONFIG_DRM_PANEL_LG_LG4573=y CONFIG_DRM_PANEL_NEC_NL8048HL11=y CONFIG_DRM_PANEL_NEWVISION_NV3052C=y CONFIG_DRM_PANEL_NOVATEK_NT35510=y CONFIG_DRM_PANEL_NOVATEK_NT35560=y CONFIG_DRM_PANEL_NOVATEK_NT35950=y CONFIG_DRM_PANEL_NOVATEK_NT36672A=y CONFIG_DRM_PANEL_NOVATEK_NT39016=y CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=y CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=y CONFIG_DRM_PANEL_ORISETECH_OTM8009A=y CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=y CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=y CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y CONFIG_DRM_PANEL_RAYDIUM_RM67191=y CONFIG_DRM_PANEL_RAYDIUM_RM68200=y CONFIG_DRM_PANEL_RONBO_RB070D30=y CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=y CONFIG_DRM_PANEL_SAMSUNG_DB7430=y CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=y CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=y CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=y CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=y CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=y CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=y CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=y CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=y CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=y CONFIG_DRM_PANEL_SEIKO_43WVF1G=y CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=y CONFIG_DRM_PANEL_SHARP_LS037V7DW01=y CONFIG_DRM_PANEL_SHARP_LS043T1LE01=y CONFIG_DRM_PANEL_SHARP_LS060T1SX01=y CONFIG_DRM_PANEL_SITRONIX_ST7701=y CONFIG_DRM_PANEL_SITRONIX_ST7703=y CONFIG_DRM_PANEL_SITRONIX_ST7789V=y CONFIG_DRM_PANEL_SONY_ACX565AKM=y CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=y CONFIG_DRM_PANEL_TDO_TL070WSH30=y CONFIG_DRM_PANEL_TPO_TD028TTEC1=y CONFIG_DRM_PANEL_TPO_TD043MTEA1=y CONFIG_DRM_PANEL_TPO_TPG110=y CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=y CONFIG_DRM_PANEL_VISIONOX_RM69299=y CONFIG_DRM_PANEL_WIDECHIPS_WS2401=y CONFIG_DRM_PANEL_XINPENG_XPP055C272=y # end of Display Panels CONFIG_DRM_BRIDGE=y CONFIG_DRM_PANEL_BRIDGE=y # # Display Interface Bridges # CONFIG_DRM_CDNS_DSI=y CONFIG_DRM_CHIPONE_ICN6211=y CONFIG_DRM_CHRONTEL_CH7033=y CONFIG_DRM_CROS_EC_ANX7688=y CONFIG_DRM_DISPLAY_CONNECTOR=y CONFIG_DRM_ITE_IT6505=y CONFIG_DRM_LONTIUM_LT8912B=y CONFIG_DRM_LONTIUM_LT9211=y CONFIG_DRM_LONTIUM_LT9611=y CONFIG_DRM_LONTIUM_LT9611UXC=y CONFIG_DRM_ITE_IT66121=y CONFIG_DRM_LVDS_CODEC=y CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=y CONFIG_DRM_NWL_MIPI_DSI=y CONFIG_DRM_NXP_PTN3460=y CONFIG_DRM_PARADE_PS8622=y CONFIG_DRM_PARADE_PS8640=y CONFIG_DRM_SIL_SII8620=y CONFIG_DRM_SII902X=y CONFIG_DRM_SII9234=y CONFIG_DRM_SIMPLE_BRIDGE=y CONFIG_DRM_THINE_THC63LVD1024=y CONFIG_DRM_TOSHIBA_TC358762=y CONFIG_DRM_TOSHIBA_TC358764=y CONFIG_DRM_TOSHIBA_TC358767=y CONFIG_DRM_TOSHIBA_TC358768=y CONFIG_DRM_TOSHIBA_TC358775=y CONFIG_DRM_TI_DLPC3433=y CONFIG_DRM_TI_TFP410=y CONFIG_DRM_TI_SN65DSI83=y CONFIG_DRM_TI_SN65DSI86=y CONFIG_DRM_TI_TPD12S015=y CONFIG_DRM_ANALOGIX_ANX6345=y CONFIG_DRM_ANALOGIX_ANX78XX=y CONFIG_DRM_ANALOGIX_DP=y CONFIG_DRM_ANALOGIX_ANX7625=y CONFIG_DRM_I2C_ADV7511=y CONFIG_DRM_I2C_ADV7511_AUDIO=y CONFIG_DRM_I2C_ADV7511_CEC=y CONFIG_DRM_CDNS_MHDP8546=y CONFIG_DRM_DW_HDMI=y CONFIG_DRM_DW_HDMI_AHB_AUDIO=y CONFIG_DRM_DW_HDMI_I2S_AUDIO=y CONFIG_DRM_DW_HDMI_GP_AUDIO=y CONFIG_DRM_DW_HDMI_CEC=y # end of Display Interface Bridges CONFIG_DRM_ETNAVIV=y CONFIG_DRM_ETNAVIV_THERMAL=y CONFIG_DRM_LOGICVC=y CONFIG_DRM_MXS=y CONFIG_DRM_MXSFB=y CONFIG_DRM_IMX_LCDIF=y CONFIG_DRM_ARCPGU=y CONFIG_DRM_BOCHS=y CONFIG_DRM_CIRRUS_QEMU=y CONFIG_DRM_GM12U320=y CONFIG_DRM_PANEL_MIPI_DBI=y CONFIG_DRM_SIMPLEDRM=y CONFIG_TINYDRM_HX8357D=y CONFIG_TINYDRM_ILI9163=y CONFIG_TINYDRM_ILI9225=y CONFIG_TINYDRM_ILI9341=y CONFIG_TINYDRM_ILI9486=y CONFIG_TINYDRM_MI0283QT=y CONFIG_TINYDRM_REPAPER=y CONFIG_TINYDRM_ST7586=y CONFIG_TINYDRM_ST7735R=y CONFIG_DRM_VBOXVIDEO=y CONFIG_DRM_GUD=y CONFIG_DRM_SSD130X=y CONFIG_DRM_SSD130X_I2C=y CONFIG_DRM_SSD130X_SPI=y CONFIG_DRM_HYPERV=y CONFIG_DRM_LEGACY=y CONFIG_DRM_TDFX=y CONFIG_DRM_R128=y CONFIG_DRM_MGA=y CONFIG_DRM_SIS=y CONFIG_DRM_VIA=y CONFIG_DRM_SAVAGE=y CONFIG_DRM_EXPORT_FOR_TESTS=y CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y CONFIG_DRM_NOMODESET=y CONFIG_DRM_LIB_RANDOM=y CONFIG_DRM_PRIVACY_SCREEN=y # # Frame buffer Devices # CONFIG_FB_CMDLINE=y CONFIG_FB_NOTIFY=y CONFIG_FB=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_DDC=y CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y CONFIG_FB_SYS_FILLRECT=y CONFIG_FB_SYS_COPYAREA=y CONFIG_FB_SYS_IMAGEBLIT=y CONFIG_FB_FOREIGN_ENDIAN=y CONFIG_FB_BOTH_ENDIAN=y # CONFIG_FB_BIG_ENDIAN is not set # CONFIG_FB_LITTLE_ENDIAN is not set CONFIG_FB_SYS_FOPS=y CONFIG_FB_DEFERRED_IO=y CONFIG_FB_HECUBA=y CONFIG_FB_SVGALIB=y CONFIG_FB_BACKLIGHT=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y # # Frame buffer hardware drivers # CONFIG_FB_CIRRUS=y CONFIG_FB_PM2=y CONFIG_FB_PM2_FIFO_DISCONNECT=y CONFIG_FB_CYBER2000=y CONFIG_FB_CYBER2000_DDC=y CONFIG_FB_ARC=y CONFIG_FB_ASILIANT=y CONFIG_FB_IMSTT=y CONFIG_FB_VGA16=y CONFIG_FB_UVESA=y CONFIG_FB_VESA=y CONFIG_FB_EFI=y CONFIG_FB_N411=y CONFIG_FB_HGA=y CONFIG_FB_OPENCORES=y CONFIG_FB_S1D13XXX=y CONFIG_FB_NVIDIA=y CONFIG_FB_NVIDIA_I2C=y CONFIG_FB_NVIDIA_DEBUG=y CONFIG_FB_NVIDIA_BACKLIGHT=y CONFIG_FB_RIVA=y CONFIG_FB_RIVA_I2C=y CONFIG_FB_RIVA_DEBUG=y CONFIG_FB_RIVA_BACKLIGHT=y CONFIG_FB_I740=y CONFIG_FB_I810=y CONFIG_FB_I810_GTF=y CONFIG_FB_I810_I2C=y CONFIG_FB_LE80578=y CONFIG_FB_CARILLO_RANCH=y CONFIG_FB_MATROX=y CONFIG_FB_MATROX_MILLENIUM=y CONFIG_FB_MATROX_MYSTIQUE=y CONFIG_FB_MATROX_G=y CONFIG_FB_MATROX_I2C=y CONFIG_FB_MATROX_MAVEN=y CONFIG_FB_RADEON=y CONFIG_FB_RADEON_I2C=y CONFIG_FB_RADEON_BACKLIGHT=y CONFIG_FB_RADEON_DEBUG=y CONFIG_FB_ATY128=y CONFIG_FB_ATY128_BACKLIGHT=y CONFIG_FB_ATY=y CONFIG_FB_ATY_CT=y CONFIG_FB_ATY_GENERIC_LCD=y CONFIG_FB_ATY_GX=y CONFIG_FB_ATY_BACKLIGHT=y CONFIG_FB_S3=y CONFIG_FB_S3_DDC=y CONFIG_FB_SAVAGE=y CONFIG_FB_SAVAGE_I2C=y CONFIG_FB_SAVAGE_ACCEL=y CONFIG_FB_SIS=y CONFIG_FB_SIS_300=y CONFIG_FB_SIS_315=y CONFIG_FB_VIA=y CONFIG_FB_VIA_DIRECT_PROCFS=y CONFIG_FB_VIA_X_COMPATIBILITY=y CONFIG_FB_NEOMAGIC=y CONFIG_FB_KYRO=y CONFIG_FB_3DFX=y CONFIG_FB_3DFX_ACCEL=y CONFIG_FB_3DFX_I2C=y CONFIG_FB_VOODOO1=y CONFIG_FB_VT8623=y CONFIG_FB_TRIDENT=y CONFIG_FB_ARK=y CONFIG_FB_PM3=y CONFIG_FB_CARMINE=y CONFIG_FB_CARMINE_DRAM_EVAL=y # CONFIG_CARMINE_DRAM_CUSTOM is not set CONFIG_FB_GEODE=y CONFIG_FB_GEODE_LX=y CONFIG_FB_GEODE_GX=y CONFIG_FB_GEODE_GX1=y CONFIG_FB_SM501=y CONFIG_FB_SMSCUFX=y CONFIG_FB_UDL=y CONFIG_FB_IBM_GXT4500=y CONFIG_FB_GOLDFISH=y CONFIG_FB_VIRTUAL=y CONFIG_FB_METRONOME=y CONFIG_FB_MB862XX=y CONFIG_FB_MB862XX_PCI_GDC=y CONFIG_FB_MB862XX_I2C=y CONFIG_FB_HYPERV=y CONFIG_FB_SSD1307=y CONFIG_FB_SM712=y # end of Frame buffer Devices # # Backlight & LCD device support # CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y CONFIG_LCD_LMS283GF05=y CONFIG_LCD_LTV350QV=y CONFIG_LCD_ILI922X=y CONFIG_LCD_ILI9320=y CONFIG_LCD_TDO24M=y CONFIG_LCD_VGG2432A4=y CONFIG_LCD_PLATFORM=y CONFIG_LCD_AMS369FG06=y CONFIG_LCD_LMS501KF03=y CONFIG_LCD_HX8357=y CONFIG_LCD_OTM3225A=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_KTD253=y CONFIG_BACKLIGHT_LM3533=y CONFIG_BACKLIGHT_CARILLO_RANCH=y CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_DA903X=y CONFIG_BACKLIGHT_DA9052=y CONFIG_BACKLIGHT_MAX8925=y CONFIG_BACKLIGHT_MT6370=y CONFIG_BACKLIGHT_APPLE=y CONFIG_BACKLIGHT_QCOM_WLED=y CONFIG_BACKLIGHT_RT4831=y CONFIG_BACKLIGHT_SAHARA=y CONFIG_BACKLIGHT_WM831X=y CONFIG_BACKLIGHT_ADP5520=y CONFIG_BACKLIGHT_ADP8860=y CONFIG_BACKLIGHT_ADP8870=y CONFIG_BACKLIGHT_88PM860X=y CONFIG_BACKLIGHT_PCF50633=y CONFIG_BACKLIGHT_AAT2870=y CONFIG_BACKLIGHT_LM3630A=y CONFIG_BACKLIGHT_LM3639=y CONFIG_BACKLIGHT_LP855X=y CONFIG_BACKLIGHT_LP8788=y CONFIG_BACKLIGHT_PANDORA=y CONFIG_BACKLIGHT_SKY81452=y CONFIG_BACKLIGHT_TPS65217=y CONFIG_BACKLIGHT_AS3711=y CONFIG_BACKLIGHT_GPIO=y CONFIG_BACKLIGHT_LV5207LP=y CONFIG_BACKLIGHT_BD6107=y CONFIG_BACKLIGHT_ARCXCNN=y CONFIG_BACKLIGHT_RAVE_SP=y CONFIG_BACKLIGHT_LED=y # end of Backlight & LCD device support CONFIG_VGASTATE=y CONFIG_VIDEOMODE_HELPERS=y CONFIG_HDMI=y # # Console display driver support # CONFIG_VGA_CONSOLE=y CONFIG_MDA_CONSOLE=y CONFIG_DUMMY_CONSOLE=y CONFIG_DUMMY_CONSOLE_COLUMNS=80 CONFIG_DUMMY_CONSOLE_ROWS=25 CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y # end of Console display driver support CONFIG_LOGO=y CONFIG_LOGO_LINUX_MONO=y CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y # end of Graphics support CONFIG_SOUND=y CONFIG_SOUND_OSS_CORE=y CONFIG_SOUND_OSS_CORE_PRECLAIM=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y CONFIG_SND_PCM_ELD=y CONFIG_SND_PCM_IEC958=y CONFIG_SND_DMAENGINE_PCM=y CONFIG_SND_HWDEP=y CONFIG_SND_SEQ_DEVICE=y CONFIG_SND_RAWMIDI=y CONFIG_SND_COMPRESS_OFFLOAD=y CONFIG_SND_JACK=y CONFIG_SND_JACK_INPUT_DEV=y CONFIG_SND_OSSEMUL=y CONFIG_SND_MIXER_OSS=y CONFIG_SND_PCM_OSS=y CONFIG_SND_PCM_OSS_PLUGINS=y CONFIG_SND_PCM_TIMER=y CONFIG_SND_HRTIMER=y CONFIG_SND_DYNAMIC_MINORS=y CONFIG_SND_MAX_CARDS=32 CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y CONFIG_SND_VERBOSE_PRINTK=y CONFIG_SND_CTL_FAST_LOOKUP=y CONFIG_SND_DEBUG=y CONFIG_SND_DEBUG_VERBOSE=y CONFIG_SND_PCM_XRUN_DEBUG=y CONFIG_SND_CTL_INPUT_VALIDATION=y CONFIG_SND_CTL_DEBUG=y CONFIG_SND_JACK_INJECTION_DEBUG=y CONFIG_SND_VMASTER=y CONFIG_SND_DMA_SGBUF=y CONFIG_SND_CTL_LED=y CONFIG_SND_SEQUENCER=y CONFIG_SND_SEQ_DUMMY=y CONFIG_SND_SEQUENCER_OSS=y CONFIG_SND_SEQ_HRTIMER_DEFAULT=y CONFIG_SND_SEQ_MIDI_EVENT=y CONFIG_SND_SEQ_MIDI=y CONFIG_SND_SEQ_MIDI_EMUL=y CONFIG_SND_SEQ_VIRMIDI=y CONFIG_SND_MPU401_UART=y CONFIG_SND_OPL3_LIB=y CONFIG_SND_OPL4_LIB=y CONFIG_SND_OPL3_LIB_SEQ=y CONFIG_SND_OPL4_LIB_SEQ=y CONFIG_SND_VX_LIB=y CONFIG_SND_AC97_CODEC=y CONFIG_SND_DRIVERS=y CONFIG_SND_PCSP=y CONFIG_SND_DUMMY=y CONFIG_SND_ALOOP=y CONFIG_SND_VIRMIDI=y CONFIG_SND_MTPAV=y CONFIG_SND_MTS64=y CONFIG_SND_SERIAL_U16550=y CONFIG_SND_SERIAL_GENERIC=y CONFIG_SND_MPU401=y CONFIG_SND_PORTMAN2X4=y CONFIG_SND_AC97_POWER_SAVE=y CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 CONFIG_SND_WSS_LIB=y CONFIG_SND_SB_COMMON=y CONFIG_SND_SB8_DSP=y CONFIG_SND_SB16_DSP=y CONFIG_SND_ISA=y CONFIG_SND_ADLIB=y CONFIG_SND_AD1816A=y CONFIG_SND_AD1848=y CONFIG_SND_ALS100=y CONFIG_SND_AZT1605=y CONFIG_SND_AZT2316=y CONFIG_SND_AZT2320=y CONFIG_SND_CMI8328=y CONFIG_SND_CMI8330=y CONFIG_SND_CS4231=y CONFIG_SND_CS4236=y CONFIG_SND_ES1688=y CONFIG_SND_ES18XX=y CONFIG_SND_SC6000=y CONFIG_SND_GUSCLASSIC=y CONFIG_SND_GUSEXTREME=y CONFIG_SND_GUSMAX=y CONFIG_SND_INTERWAVE=y CONFIG_SND_INTERWAVE_STB=y CONFIG_SND_JAZZ16=y CONFIG_SND_OPL3SA2=y CONFIG_SND_OPTI92X_AD1848=y CONFIG_SND_OPTI92X_CS4231=y CONFIG_SND_OPTI93X=y CONFIG_SND_MIRO=y CONFIG_SND_SB8=y CONFIG_SND_SB16=y CONFIG_SND_SBAWE=y CONFIG_SND_SBAWE_SEQ=y CONFIG_SND_SB16_CSP=y CONFIG_SND_SSCAPE=y CONFIG_SND_WAVEFRONT=y CONFIG_SND_MSND_PINNACLE=y CONFIG_SND_MSND_CLASSIC=y CONFIG_SND_PCI=y CONFIG_SND_AD1889=y CONFIG_SND_ALS300=y CONFIG_SND_ALS4000=y CONFIG_SND_ALI5451=y CONFIG_SND_ASIHPI=y CONFIG_SND_ATIIXP=y CONFIG_SND_ATIIXP_MODEM=y CONFIG_SND_AU8810=y CONFIG_SND_AU8820=y CONFIG_SND_AU8830=y CONFIG_SND_AW2=y CONFIG_SND_AZT3328=y CONFIG_SND_BT87X=y CONFIG_SND_BT87X_OVERCLOCK=y CONFIG_SND_CA0106=y CONFIG_SND_CMIPCI=y CONFIG_SND_OXYGEN_LIB=y CONFIG_SND_OXYGEN=y CONFIG_SND_CS4281=y CONFIG_SND_CS46XX=y CONFIG_SND_CS46XX_NEW_DSP=y CONFIG_SND_CS5530=y CONFIG_SND_CS5535AUDIO=y CONFIG_SND_CTXFI=y CONFIG_SND_DARLA20=y CONFIG_SND_GINA20=y CONFIG_SND_LAYLA20=y CONFIG_SND_DARLA24=y CONFIG_SND_GINA24=y CONFIG_SND_LAYLA24=y CONFIG_SND_MONA=y CONFIG_SND_MIA=y CONFIG_SND_ECHO3G=y CONFIG_SND_INDIGO=y CONFIG_SND_INDIGOIO=y CONFIG_SND_INDIGODJ=y CONFIG_SND_INDIGOIOX=y CONFIG_SND_INDIGODJX=y CONFIG_SND_EMU10K1=y CONFIG_SND_EMU10K1_SEQ=y CONFIG_SND_EMU10K1X=y CONFIG_SND_ENS1370=y CONFIG_SND_ENS1371=y CONFIG_SND_ES1938=y CONFIG_SND_ES1968=y CONFIG_SND_ES1968_INPUT=y CONFIG_SND_ES1968_RADIO=y CONFIG_SND_FM801=y CONFIG_SND_FM801_TEA575X_BOOL=y CONFIG_SND_HDSP=y # # Don't forget to add built-in firmwares for HDSP driver # CONFIG_SND_HDSPM=y CONFIG_SND_ICE1712=y CONFIG_SND_ICE1724=y CONFIG_SND_INTEL8X0=y CONFIG_SND_INTEL8X0M=y CONFIG_SND_KORG1212=y CONFIG_SND_LOLA=y CONFIG_SND_LX6464ES=y CONFIG_SND_MAESTRO3=y CONFIG_SND_MAESTRO3_INPUT=y CONFIG_SND_MIXART=y CONFIG_SND_NM256=y CONFIG_SND_PCXHR=y CONFIG_SND_RIPTIDE=y CONFIG_SND_RME32=y CONFIG_SND_RME96=y CONFIG_SND_RME9652=y CONFIG_SND_SIS7019=y CONFIG_SND_SONICVIBES=y CONFIG_SND_TRIDENT=y CONFIG_SND_VIA82XX=y CONFIG_SND_VIA82XX_MODEM=y CONFIG_SND_VIRTUOSO=y CONFIG_SND_VX222=y CONFIG_SND_YMFPCI=y # # HD-Audio # CONFIG_SND_HDA=y CONFIG_SND_HDA_GENERIC_LEDS=y CONFIG_SND_HDA_INTEL=y CONFIG_SND_HDA_HWDEP=y CONFIG_SND_HDA_RECONFIG=y CONFIG_SND_HDA_INPUT_BEEP=y CONFIG_SND_HDA_INPUT_BEEP_MODE=1 CONFIG_SND_HDA_PATCH_LOADER=y CONFIG_SND_HDA_SCODEC_CS35L41=y CONFIG_SND_HDA_CS_DSP_CONTROLS=y CONFIG_SND_HDA_SCODEC_CS35L41_I2C=y CONFIG_SND_HDA_SCODEC_CS35L41_SPI=y CONFIG_SND_HDA_CODEC_REALTEK=y CONFIG_SND_HDA_CODEC_ANALOG=y CONFIG_SND_HDA_CODEC_SIGMATEL=y CONFIG_SND_HDA_CODEC_VIA=y CONFIG_SND_HDA_CODEC_HDMI=y CONFIG_SND_HDA_CODEC_CIRRUS=y CONFIG_SND_HDA_CODEC_CS8409=y CONFIG_SND_HDA_CODEC_CONEXANT=y CONFIG_SND_HDA_CODEC_CA0110=y CONFIG_SND_HDA_CODEC_CA0132=y CONFIG_SND_HDA_CODEC_CA0132_DSP=y CONFIG_SND_HDA_CODEC_CMEDIA=y CONFIG_SND_HDA_CODEC_SI3054=y CONFIG_SND_HDA_GENERIC=y CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y # end of HD-Audio CONFIG_SND_HDA_CORE=y CONFIG_SND_HDA_DSP_LOADER=y CONFIG_SND_HDA_COMPONENT=y CONFIG_SND_HDA_I915=y CONFIG_SND_HDA_EXT_CORE=y CONFIG_SND_HDA_PREALLOC_SIZE=0 CONFIG_SND_INTEL_NHLT=y CONFIG_SND_INTEL_DSP_CONFIG=y CONFIG_SND_INTEL_SOUNDWIRE_ACPI=y CONFIG_SND_INTEL_BYT_PREFER_SOF=y CONFIG_SND_SPI=y CONFIG_SND_USB=y CONFIG_SND_USB_AUDIO=y CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y CONFIG_SND_USB_UA101=y CONFIG_SND_USB_USX2Y=y CONFIG_SND_USB_CAIAQ=y CONFIG_SND_USB_CAIAQ_INPUT=y CONFIG_SND_USB_US122L=y CONFIG_SND_USB_6FIRE=y CONFIG_SND_USB_HIFACE=y CONFIG_SND_BCD2000=y CONFIG_SND_USB_LINE6=y CONFIG_SND_USB_POD=y CONFIG_SND_USB_PODHD=y CONFIG_SND_USB_TONEPORT=y CONFIG_SND_USB_VARIAX=y CONFIG_SND_FIREWIRE=y CONFIG_SND_FIREWIRE_LIB=y CONFIG_SND_DICE=y CONFIG_SND_OXFW=y CONFIG_SND_ISIGHT=y CONFIG_SND_FIREWORKS=y CONFIG_SND_BEBOB=y CONFIG_SND_FIREWIRE_DIGI00X=y CONFIG_SND_FIREWIRE_TASCAM=y CONFIG_SND_FIREWIRE_MOTU=y CONFIG_SND_FIREFACE=y CONFIG_SND_PCMCIA=y CONFIG_SND_VXPOCKET=y CONFIG_SND_PDAUDIOCF=y CONFIG_SND_SOC=y CONFIG_SND_SOC_AC97_BUS=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y CONFIG_SND_SOC_COMPRESS=y CONFIG_SND_SOC_TOPOLOGY=y CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=y CONFIG_SND_SOC_UTILS_KUNIT_TEST=y CONFIG_SND_SOC_ACPI=y CONFIG_SND_SOC_ADI=y CONFIG_SND_SOC_ADI_AXI_I2S=y CONFIG_SND_SOC_ADI_AXI_SPDIF=y CONFIG_SND_SOC_AMD_ACP=y CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=y CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=y CONFIG_SND_SOC_AMD_ST_ES8336_MACH=y CONFIG_SND_SOC_AMD_ACP3x=y CONFIG_SND_SOC_AMD_RV_RT5682_MACH=y CONFIG_SND_SOC_AMD_RENOIR=y CONFIG_SND_SOC_AMD_RENOIR_MACH=y CONFIG_SND_SOC_AMD_ACP5x=y CONFIG_SND_SOC_AMD_VANGOGH_MACH=y CONFIG_SND_SOC_AMD_ACP6x=y CONFIG_SND_SOC_AMD_YC_MACH=y CONFIG_SND_AMD_ACP_CONFIG=y CONFIG_SND_SOC_AMD_ACP_COMMON=y CONFIG_SND_SOC_AMD_ACP_PDM=y CONFIG_SND_SOC_AMD_ACP_I2S=y CONFIG_SND_SOC_AMD_ACP_PCM=y CONFIG_SND_SOC_AMD_ACP_PCI=y CONFIG_SND_AMD_ASOC_RENOIR=y CONFIG_SND_AMD_ASOC_REMBRANDT=y CONFIG_SND_SOC_AMD_MACH_COMMON=y CONFIG_SND_SOC_AMD_LEGACY_MACH=y CONFIG_SND_SOC_AMD_SOF_MACH=y CONFIG_SND_SOC_AMD_RPL_ACP6x=y CONFIG_SND_SOC_AMD_PS=y CONFIG_SND_SOC_AMD_PS_MACH=y CONFIG_SND_ATMEL_SOC=y CONFIG_SND_SOC_MIKROE_PROTO=y CONFIG_SND_BCM63XX_I2S_WHISTLER=y CONFIG_SND_DESIGNWARE_I2S=y CONFIG_SND_DESIGNWARE_PCM=y # # SoC Audio for Freescale CPUs # # # Common SoC Audio options for Freescale CPUs: # CONFIG_SND_SOC_FSL_ASRC=y CONFIG_SND_SOC_FSL_SAI=y CONFIG_SND_SOC_FSL_MQS=y CONFIG_SND_SOC_FSL_AUDMIX=y CONFIG_SND_SOC_FSL_SSI=y CONFIG_SND_SOC_FSL_SPDIF=y CONFIG_SND_SOC_FSL_ESAI=y CONFIG_SND_SOC_FSL_MICFIL=y CONFIG_SND_SOC_FSL_EASRC=y CONFIG_SND_SOC_FSL_XCVR=y CONFIG_SND_SOC_FSL_UTILS=y CONFIG_SND_SOC_FSL_RPMSG=y CONFIG_SND_SOC_IMX_AUDMUX=y # end of SoC Audio for Freescale CPUs CONFIG_SND_I2S_HI6210_I2S=y CONFIG_SND_SOC_IMG=y CONFIG_SND_SOC_IMG_I2S_IN=y CONFIG_SND_SOC_IMG_I2S_OUT=y CONFIG_SND_SOC_IMG_PARALLEL_OUT=y CONFIG_SND_SOC_IMG_SPDIF_IN=y CONFIG_SND_SOC_IMG_SPDIF_OUT=y CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=y CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y CONFIG_SND_SOC_INTEL_SST=y CONFIG_SND_SOC_INTEL_CATPT=y CONFIG_SND_SST_ATOM_HIFI2_PLATFORM=y CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI=y CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI=y CONFIG_SND_SOC_INTEL_SKYLAKE=y CONFIG_SND_SOC_INTEL_SKL=y CONFIG_SND_SOC_INTEL_APL=y CONFIG_SND_SOC_INTEL_KBL=y CONFIG_SND_SOC_INTEL_GLK=y CONFIG_SND_SOC_INTEL_CNL=y CONFIG_SND_SOC_INTEL_CFL=y CONFIG_SND_SOC_INTEL_CML_H=y CONFIG_SND_SOC_INTEL_CML_LP=y CONFIG_SND_SOC_INTEL_SKYLAKE_FAMILY=y CONFIG_SND_SOC_INTEL_SKYLAKE_SSP_CLK=y CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC=y CONFIG_SND_SOC_INTEL_SKYLAKE_COMMON=y CONFIG_SND_SOC_ACPI_INTEL_MATCH=y CONFIG_SND_SOC_INTEL_AVS=y # # Intel AVS Machine drivers # # # Available DSP configurations # CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=y CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC=y CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO=y CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST=y CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98927=y CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A=y CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373=y CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825=y CONFIG_SND_SOC_INTEL_AVS_MACH_RT274=y CONFIG_SND_SOC_INTEL_AVS_MACH_RT286=y CONFIG_SND_SOC_INTEL_AVS_MACH_RT298=y CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682=y CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567=y # end of Intel AVS Machine drivers CONFIG_SND_SOC_INTEL_MACH=y CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES=y CONFIG_SND_SOC_INTEL_HDA_DSP_COMMON=y CONFIG_SND_SOC_INTEL_SOF_MAXIM_COMMON=y CONFIG_SND_SOC_INTEL_SOF_REALTEK_COMMON=y CONFIG_SND_SOC_INTEL_HASWELL_MACH=y CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH=y CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH=y CONFIG_SND_SOC_INTEL_BROADWELL_MACH=y CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH=y CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH=y CONFIG_SND_SOC_INTEL_BYTCR_WM5102_MACH=y CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH=y CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH=y CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH=y CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH=y CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH=y CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH=y CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH=y CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH=y CONFIG_SND_SOC_INTEL_SKL_RT286_MACH=y CONFIG_SND_SOC_INTEL_SKL_NAU88L25_SSM4567_MACH=y CONFIG_SND_SOC_INTEL_SKL_NAU88L25_MAX98357A_MACH=y CONFIG_SND_SOC_INTEL_DA7219_MAX98357A_GENERIC=y CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_COMMON=y CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_MACH=y CONFIG_SND_SOC_INTEL_BXT_RT298_MACH=y CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH=y CONFIG_SND_SOC_INTEL_KBL_RT5663_MAX98927_MACH=y CONFIG_SND_SOC_INTEL_KBL_RT5663_RT5514_MAX98927_MACH=y CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98357A_MACH=y CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98927_MACH=y CONFIG_SND_SOC_INTEL_KBL_RT5660_MACH=y CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH=y CONFIG_SND_SOC_INTEL_SOF_RT5682_MACH=y CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH=y CONFIG_SND_SOC_INTEL_SOUNDWIRE_SOF_MACH=y CONFIG_SND_SOC_MTK_BTCVSD=y CONFIG_SND_SOC_SOF_TOPLEVEL=y CONFIG_SND_SOC_SOF_PCI_DEV=y CONFIG_SND_SOC_SOF_PCI=y CONFIG_SND_SOC_SOF_ACPI=y CONFIG_SND_SOC_SOF_ACPI_DEV=y CONFIG_SND_SOC_SOF_OF=y CONFIG_SND_SOC_SOF_DEBUG_PROBES=y CONFIG_SND_SOC_SOF_CLIENT=y CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT=y CONFIG_SND_SOC_SOF_FORCE_PROBE_WORKQUEUE=y CONFIG_SND_SOC_SOF_NOCODEC=y CONFIG_SND_SOC_SOF_NOCODEC_SUPPORT=y CONFIG_SND_SOC_SOF_STRICT_ABI_CHECKS=y CONFIG_SND_SOC_SOF_DEBUG=y CONFIG_SND_SOC_SOF_FORCE_NOCODEC_MODE=y CONFIG_SND_SOC_SOF_DEBUG_XRUN_STOP=y CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC=y CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION=y CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE=y CONFIG_SND_SOC_SOF_DEBUG_ENABLE_FIRMWARE_TRACE=y CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST=y CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST_NUM=2 CONFIG_SND_SOC_SOF_DEBUG_IPC_MSG_INJECTOR=y CONFIG_SND_SOC_SOF_DEBUG_RETAIN_DSP_CONTEXT=y CONFIG_SND_SOC_SOF=y CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE=y CONFIG_SND_SOC_SOF_IPC3=y CONFIG_SND_SOC_SOF_INTEL_IPC4=y CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=y CONFIG_SND_SOC_SOF_AMD_COMMON=y CONFIG_SND_SOC_SOF_AMD_RENOIR=y CONFIG_SND_SOC_SOF_AMD_REMBRANDT=y CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL=y CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC=y CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP=y CONFIG_SND_SOC_SOF_INTEL_COMMON=y CONFIG_SND_SOC_SOF_BAYTRAIL=y CONFIG_SND_SOC_SOF_BROADWELL=y CONFIG_SND_SOC_SOF_MERRIFIELD=y CONFIG_SND_SOC_SOF_INTEL_SKL=y CONFIG_SND_SOC_SOF_SKYLAKE=y CONFIG_SND_SOC_SOF_KABYLAKE=y CONFIG_SND_SOC_SOF_INTEL_APL=y CONFIG_SND_SOC_SOF_APOLLOLAKE=y CONFIG_SND_SOC_SOF_GEMINILAKE=y CONFIG_SND_SOC_SOF_INTEL_CNL=y CONFIG_SND_SOC_SOF_CANNONLAKE=y CONFIG_SND_SOC_SOF_COFFEELAKE=y CONFIG_SND_SOC_SOF_COMETLAKE=y CONFIG_SND_SOC_SOF_INTEL_ICL=y CONFIG_SND_SOC_SOF_ICELAKE=y CONFIG_SND_SOC_SOF_JASPERLAKE=y CONFIG_SND_SOC_SOF_INTEL_TGL=y CONFIG_SND_SOC_SOF_TIGERLAKE=y CONFIG_SND_SOC_SOF_ELKHARTLAKE=y CONFIG_SND_SOC_SOF_ALDERLAKE=y CONFIG_SND_SOC_SOF_INTEL_MTL=y CONFIG_SND_SOC_SOF_METEORLAKE=y CONFIG_SND_SOC_SOF_HDA_COMMON=y CONFIG_SND_SOC_SOF_HDA_LINK_BASELINE=y CONFIG_SND_SOC_SOF_HDA_PROBES=y CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE=y CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE=y CONFIG_SND_SOC_SOF_XTENSA=y # # STMicroelectronics STM32 SOC audio support # # end of STMicroelectronics STM32 SOC audio support CONFIG_SND_SOC_XILINX_I2S=y CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=y CONFIG_SND_SOC_XILINX_SPDIF=y CONFIG_SND_SOC_XTFPGA_I2S=y CONFIG_SND_SOC_I2C_AND_SPI=y # # CODEC drivers # CONFIG_SND_SOC_ARIZONA=y CONFIG_SND_SOC_WM_ADSP=y CONFIG_SND_SOC_AC97_CODEC=y CONFIG_SND_SOC_ADAU_UTILS=y CONFIG_SND_SOC_ADAU1372=y CONFIG_SND_SOC_ADAU1372_I2C=y CONFIG_SND_SOC_ADAU1372_SPI=y CONFIG_SND_SOC_ADAU1701=y CONFIG_SND_SOC_ADAU17X1=y CONFIG_SND_SOC_ADAU1761=y CONFIG_SND_SOC_ADAU1761_I2C=y CONFIG_SND_SOC_ADAU1761_SPI=y CONFIG_SND_SOC_ADAU7002=y CONFIG_SND_SOC_ADAU7118=y CONFIG_SND_SOC_ADAU7118_HW=y CONFIG_SND_SOC_ADAU7118_I2C=y CONFIG_SND_SOC_AK4104=y CONFIG_SND_SOC_AK4118=y CONFIG_SND_SOC_AK4375=y CONFIG_SND_SOC_AK4458=y CONFIG_SND_SOC_AK4554=y CONFIG_SND_SOC_AK4613=y CONFIG_SND_SOC_AK4642=y CONFIG_SND_SOC_AK5386=y CONFIG_SND_SOC_AK5558=y CONFIG_SND_SOC_ALC5623=y CONFIG_SND_SOC_AW8738=y CONFIG_SND_SOC_BD28623=y CONFIG_SND_SOC_BT_SCO=y CONFIG_SND_SOC_CPCAP=y CONFIG_SND_SOC_CROS_EC_CODEC=y CONFIG_SND_SOC_CS35L32=y CONFIG_SND_SOC_CS35L33=y CONFIG_SND_SOC_CS35L34=y CONFIG_SND_SOC_CS35L35=y CONFIG_SND_SOC_CS35L36=y CONFIG_SND_SOC_CS35L41_LIB=y CONFIG_SND_SOC_CS35L41=y CONFIG_SND_SOC_CS35L41_SPI=y CONFIG_SND_SOC_CS35L41_I2C=y CONFIG_SND_SOC_CS35L45_TABLES=y CONFIG_SND_SOC_CS35L45=y CONFIG_SND_SOC_CS35L45_SPI=y CONFIG_SND_SOC_CS35L45_I2C=y CONFIG_SND_SOC_CS42L42_CORE=y CONFIG_SND_SOC_CS42L42=y CONFIG_SND_SOC_CS42L51=y CONFIG_SND_SOC_CS42L51_I2C=y CONFIG_SND_SOC_CS42L52=y CONFIG_SND_SOC_CS42L56=y CONFIG_SND_SOC_CS42L73=y CONFIG_SND_SOC_CS42L83=y CONFIG_SND_SOC_CS4234=y CONFIG_SND_SOC_CS4265=y CONFIG_SND_SOC_CS4270=y CONFIG_SND_SOC_CS4271=y CONFIG_SND_SOC_CS4271_I2C=y CONFIG_SND_SOC_CS4271_SPI=y CONFIG_SND_SOC_CS42XX8=y CONFIG_SND_SOC_CS42XX8_I2C=y CONFIG_SND_SOC_CS43130=y CONFIG_SND_SOC_CS4341=y CONFIG_SND_SOC_CS4349=y CONFIG_SND_SOC_CS48L32=y CONFIG_SND_SOC_CS53L30=y CONFIG_SND_SOC_CX2072X=y CONFIG_SND_SOC_DA7213=y CONFIG_SND_SOC_DA7219=y CONFIG_SND_SOC_DMIC=y CONFIG_SND_SOC_HDMI_CODEC=y CONFIG_SND_SOC_ES7134=y CONFIG_SND_SOC_ES7241=y CONFIG_SND_SOC_ES8316=y CONFIG_SND_SOC_ES8326=y CONFIG_SND_SOC_ES8328=y CONFIG_SND_SOC_ES8328_I2C=y CONFIG_SND_SOC_ES8328_SPI=y CONFIG_SND_SOC_GTM601=y CONFIG_SND_SOC_HDAC_HDMI=y CONFIG_SND_SOC_HDAC_HDA=y CONFIG_SND_SOC_HDA=y CONFIG_SND_SOC_ICS43432=y CONFIG_SND_SOC_INNO_RK3036=y CONFIG_SND_SOC_LOCHNAGAR_SC=y CONFIG_SND_SOC_MAX98088=y CONFIG_SND_SOC_MAX98090=y CONFIG_SND_SOC_MAX98357A=y CONFIG_SND_SOC_MAX98504=y CONFIG_SND_SOC_MAX9867=y CONFIG_SND_SOC_MAX98927=y CONFIG_SND_SOC_MAX98520=y CONFIG_SND_SOC_MAX98373=y CONFIG_SND_SOC_MAX98373_I2C=y CONFIG_SND_SOC_MAX98373_SDW=y CONFIG_SND_SOC_MAX98390=y CONFIG_SND_SOC_MAX98396=y CONFIG_SND_SOC_MAX9860=y CONFIG_SND_SOC_MSM8916_WCD_ANALOG=y CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y CONFIG_SND_SOC_PCM1681=y CONFIG_SND_SOC_PCM1789=y CONFIG_SND_SOC_PCM1789_I2C=y CONFIG_SND_SOC_PCM179X=y CONFIG_SND_SOC_PCM179X_I2C=y CONFIG_SND_SOC_PCM179X_SPI=y CONFIG_SND_SOC_PCM186X=y CONFIG_SND_SOC_PCM186X_I2C=y CONFIG_SND_SOC_PCM186X_SPI=y CONFIG_SND_SOC_PCM3060=y CONFIG_SND_SOC_PCM3060_I2C=y CONFIG_SND_SOC_PCM3060_SPI=y CONFIG_SND_SOC_PCM3168A=y CONFIG_SND_SOC_PCM3168A_I2C=y CONFIG_SND_SOC_PCM3168A_SPI=y CONFIG_SND_SOC_PCM5102A=y CONFIG_SND_SOC_PCM512x=y CONFIG_SND_SOC_PCM512x_I2C=y CONFIG_SND_SOC_PCM512x_SPI=y CONFIG_SND_SOC_RK3328=y CONFIG_SND_SOC_RK817=y CONFIG_SND_SOC_RL6231=y CONFIG_SND_SOC_RL6347A=y CONFIG_SND_SOC_RT274=y CONFIG_SND_SOC_RT286=y CONFIG_SND_SOC_RT298=y CONFIG_SND_SOC_RT1011=y CONFIG_SND_SOC_RT1015=y CONFIG_SND_SOC_RT1015P=y CONFIG_SND_SOC_RT1019=y CONFIG_SND_SOC_RT1308=y CONFIG_SND_SOC_RT1308_SDW=y CONFIG_SND_SOC_RT1316_SDW=y CONFIG_SND_SOC_RT5514=y CONFIG_SND_SOC_RT5514_SPI=y CONFIG_SND_SOC_RT5616=y CONFIG_SND_SOC_RT5631=y CONFIG_SND_SOC_RT5640=y CONFIG_SND_SOC_RT5645=y CONFIG_SND_SOC_RT5651=y CONFIG_SND_SOC_RT5659=y CONFIG_SND_SOC_RT5660=y CONFIG_SND_SOC_RT5663=y CONFIG_SND_SOC_RT5670=y CONFIG_SND_SOC_RT5677=y CONFIG_SND_SOC_RT5677_SPI=y CONFIG_SND_SOC_RT5682=y CONFIG_SND_SOC_RT5682_I2C=y CONFIG_SND_SOC_RT5682_SDW=y CONFIG_SND_SOC_RT5682S=y CONFIG_SND_SOC_RT700=y CONFIG_SND_SOC_RT700_SDW=y CONFIG_SND_SOC_RT711=y CONFIG_SND_SOC_RT711_SDW=y CONFIG_SND_SOC_RT711_SDCA_SDW=y CONFIG_SND_SOC_RT715=y CONFIG_SND_SOC_RT715_SDW=y CONFIG_SND_SOC_RT715_SDCA_SDW=y CONFIG_SND_SOC_RT9120=y CONFIG_SND_SOC_SDW_MOCKUP=y CONFIG_SND_SOC_SGTL5000=y CONFIG_SND_SOC_SI476X=y CONFIG_SND_SOC_SIGMADSP=y CONFIG_SND_SOC_SIGMADSP_I2C=y CONFIG_SND_SOC_SIGMADSP_REGMAP=y CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y CONFIG_SND_SOC_SIMPLE_MUX=y CONFIG_SND_SOC_SPDIF=y CONFIG_SND_SOC_SRC4XXX_I2C=y CONFIG_SND_SOC_SRC4XXX=y CONFIG_SND_SOC_SSM2305=y CONFIG_SND_SOC_SSM2518=y CONFIG_SND_SOC_SSM2602=y CONFIG_SND_SOC_SSM2602_SPI=y CONFIG_SND_SOC_SSM2602_I2C=y CONFIG_SND_SOC_SSM4567=y CONFIG_SND_SOC_STA32X=y CONFIG_SND_SOC_STA350=y CONFIG_SND_SOC_STI_SAS=y CONFIG_SND_SOC_TAS2552=y CONFIG_SND_SOC_TAS2562=y CONFIG_SND_SOC_TAS2764=y CONFIG_SND_SOC_TAS2770=y CONFIG_SND_SOC_TAS2780=y CONFIG_SND_SOC_TAS5086=y CONFIG_SND_SOC_TAS571X=y CONFIG_SND_SOC_TAS5720=y CONFIG_SND_SOC_TAS5805M=y CONFIG_SND_SOC_TAS6424=y CONFIG_SND_SOC_TDA7419=y CONFIG_SND_SOC_TFA9879=y CONFIG_SND_SOC_TFA989X=y CONFIG_SND_SOC_TLV320ADC3XXX=y CONFIG_SND_SOC_TLV320AIC23=y CONFIG_SND_SOC_TLV320AIC23_I2C=y CONFIG_SND_SOC_TLV320AIC23_SPI=y CONFIG_SND_SOC_TLV320AIC31XX=y CONFIG_SND_SOC_TLV320AIC32X4=y CONFIG_SND_SOC_TLV320AIC32X4_I2C=y CONFIG_SND_SOC_TLV320AIC32X4_SPI=y CONFIG_SND_SOC_TLV320AIC3X=y CONFIG_SND_SOC_TLV320AIC3X_I2C=y CONFIG_SND_SOC_TLV320AIC3X_SPI=y CONFIG_SND_SOC_TLV320ADCX140=y CONFIG_SND_SOC_TS3A227E=y CONFIG_SND_SOC_TSCS42XX=y CONFIG_SND_SOC_TSCS454=y CONFIG_SND_SOC_UDA1334=y CONFIG_SND_SOC_WCD9335=y CONFIG_SND_SOC_WCD_MBHC=y CONFIG_SND_SOC_WCD934X=y CONFIG_SND_SOC_WCD938X=y CONFIG_SND_SOC_WCD938X_SDW=y CONFIG_SND_SOC_WM5102=y CONFIG_SND_SOC_WM8510=y CONFIG_SND_SOC_WM8523=y CONFIG_SND_SOC_WM8524=y CONFIG_SND_SOC_WM8580=y CONFIG_SND_SOC_WM8711=y CONFIG_SND_SOC_WM8728=y CONFIG_SND_SOC_WM8731=y CONFIG_SND_SOC_WM8731_I2C=y CONFIG_SND_SOC_WM8731_SPI=y CONFIG_SND_SOC_WM8737=y CONFIG_SND_SOC_WM8741=y CONFIG_SND_SOC_WM8750=y CONFIG_SND_SOC_WM8753=y CONFIG_SND_SOC_WM8770=y CONFIG_SND_SOC_WM8776=y CONFIG_SND_SOC_WM8782=y CONFIG_SND_SOC_WM8804=y CONFIG_SND_SOC_WM8804_I2C=y CONFIG_SND_SOC_WM8804_SPI=y CONFIG_SND_SOC_WM8903=y CONFIG_SND_SOC_WM8904=y CONFIG_SND_SOC_WM8940=y CONFIG_SND_SOC_WM8960=y CONFIG_SND_SOC_WM8961=y CONFIG_SND_SOC_WM8962=y CONFIG_SND_SOC_WM8974=y CONFIG_SND_SOC_WM8978=y CONFIG_SND_SOC_WM8985=y CONFIG_SND_SOC_WSA881X=y CONFIG_SND_SOC_WSA883X=y CONFIG_SND_SOC_ZL38060=y CONFIG_SND_SOC_MAX9759=y CONFIG_SND_SOC_MT6351=y CONFIG_SND_SOC_MT6358=y CONFIG_SND_SOC_MT6660=y CONFIG_SND_SOC_NAU8315=y CONFIG_SND_SOC_NAU8540=y CONFIG_SND_SOC_NAU8810=y CONFIG_SND_SOC_NAU8821=y CONFIG_SND_SOC_NAU8822=y CONFIG_SND_SOC_NAU8824=y CONFIG_SND_SOC_NAU8825=y CONFIG_SND_SOC_TPA6130A2=y CONFIG_SND_SOC_LPASS_MACRO_COMMON=y CONFIG_SND_SOC_LPASS_WSA_MACRO=y CONFIG_SND_SOC_LPASS_VA_MACRO=y CONFIG_SND_SOC_LPASS_RX_MACRO=y CONFIG_SND_SOC_LPASS_TX_MACRO=y # end of CODEC drivers CONFIG_SND_SIMPLE_CARD_UTILS=y CONFIG_SND_SIMPLE_CARD=y CONFIG_SND_AUDIO_GRAPH_CARD=y CONFIG_SND_AUDIO_GRAPH_CARD2=y CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=y CONFIG_SND_TEST_COMPONENT=y CONFIG_SND_X86=y CONFIG_HDMI_LPE_AUDIO=y CONFIG_SND_SYNTH_EMUX=y CONFIG_SND_VIRTIO=y CONFIG_AC97_BUS=y # # HID support # CONFIG_HID=y CONFIG_HID_BATTERY_STRENGTH=y CONFIG_HIDRAW=y CONFIG_UHID=y CONFIG_HID_GENERIC=y # # Special HID drivers # CONFIG_HID_A4TECH=y CONFIG_HID_ACCUTOUCH=y CONFIG_HID_ACRUX=y CONFIG_HID_ACRUX_FF=y CONFIG_HID_APPLE=y CONFIG_HID_APPLEIR=y CONFIG_HID_ASUS=y CONFIG_HID_AUREAL=y CONFIG_HID_BELKIN=y CONFIG_HID_BETOP_FF=y CONFIG_HID_BIGBEN_FF=y CONFIG_HID_CHERRY=y CONFIG_HID_CHICONY=y CONFIG_HID_CORSAIR=y CONFIG_HID_COUGAR=y CONFIG_HID_MACALLY=y CONFIG_HID_PRODIKEYS=y CONFIG_HID_CMEDIA=y CONFIG_HID_CP2112=y CONFIG_HID_CREATIVE_SB0540=y CONFIG_HID_CYPRESS=y CONFIG_HID_DRAGONRISE=y CONFIG_DRAGONRISE_FF=y CONFIG_HID_EMS_FF=y CONFIG_HID_ELAN=y CONFIG_HID_ELECOM=y CONFIG_HID_ELO=y CONFIG_HID_EZKEY=y CONFIG_HID_FT260=y CONFIG_HID_GEMBIRD=y CONFIG_HID_GFRM=y CONFIG_HID_GLORIOUS=y CONFIG_HID_HOLTEK=y CONFIG_HOLTEK_FF=y CONFIG_HID_VIVALDI_COMMON=y CONFIG_HID_GOOGLE_HAMMER=y CONFIG_HID_VIVALDI=y CONFIG_HID_GT683R=y CONFIG_HID_KEYTOUCH=y CONFIG_HID_KYE=y CONFIG_HID_UCLOGIC=y CONFIG_HID_WALTOP=y CONFIG_HID_VIEWSONIC=y CONFIG_HID_VRC2=y CONFIG_HID_XIAOMI=y CONFIG_HID_GYRATION=y CONFIG_HID_ICADE=y CONFIG_HID_ITE=y CONFIG_HID_JABRA=y CONFIG_HID_TWINHAN=y CONFIG_HID_KENSINGTON=y CONFIG_HID_LCPOWER=y CONFIG_HID_LED=y CONFIG_HID_LENOVO=y CONFIG_HID_LETSKETCH=y CONFIG_HID_LOGITECH=y CONFIG_HID_LOGITECH_DJ=y CONFIG_HID_LOGITECH_HIDPP=y CONFIG_LOGITECH_FF=y CONFIG_LOGIRUMBLEPAD2_FF=y CONFIG_LOGIG940_FF=y CONFIG_LOGIWHEELS_FF=y CONFIG_HID_MAGICMOUSE=y CONFIG_HID_MALTRON=y CONFIG_HID_MAYFLASH=y CONFIG_HID_MEGAWORLD_FF=y CONFIG_HID_REDRAGON=y CONFIG_HID_MICROSOFT=y CONFIG_HID_MONTEREY=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_NINTENDO=y CONFIG_NINTENDO_FF=y CONFIG_HID_NTI=y CONFIG_HID_NTRIG=y CONFIG_HID_ORTEK=y CONFIG_HID_PANTHERLORD=y CONFIG_PANTHERLORD_FF=y CONFIG_HID_PENMOUNT=y CONFIG_HID_PETALYNX=y CONFIG_HID_PICOLCD=y CONFIG_HID_PICOLCD_FB=y CONFIG_HID_PICOLCD_BACKLIGHT=y CONFIG_HID_PICOLCD_LCD=y CONFIG_HID_PICOLCD_LEDS=y CONFIG_HID_PICOLCD_CIR=y CONFIG_HID_PLANTRONICS=y CONFIG_HID_PLAYSTATION=y CONFIG_PLAYSTATION_FF=y CONFIG_HID_PXRC=y CONFIG_HID_RAZER=y CONFIG_HID_PRIMAX=y CONFIG_HID_RETRODE=y CONFIG_HID_ROCCAT=y CONFIG_HID_SAITEK=y CONFIG_HID_SAMSUNG=y CONFIG_HID_SEMITEK=y CONFIG_HID_SIGMAMICRO=y CONFIG_HID_SONY=y CONFIG_SONY_FF=y CONFIG_HID_SPEEDLINK=y CONFIG_HID_STEAM=y CONFIG_HID_STEELSERIES=y CONFIG_HID_SUNPLUS=y CONFIG_HID_RMI=y CONFIG_HID_GREENASIA=y CONFIG_GREENASIA_FF=y CONFIG_HID_HYPERV_MOUSE=y CONFIG_HID_SMARTJOYPLUS=y CONFIG_SMARTJOYPLUS_FF=y CONFIG_HID_TIVO=y CONFIG_HID_TOPSEED=y CONFIG_HID_TOPRE=y CONFIG_HID_THINGM=y CONFIG_HID_THRUSTMASTER=y CONFIG_THRUSTMASTER_FF=y CONFIG_HID_UDRAW_PS3=y CONFIG_HID_U2FZERO=y CONFIG_HID_WACOM=y CONFIG_HID_WIIMOTE=y CONFIG_HID_XINMO=y CONFIG_HID_ZEROPLUS=y CONFIG_ZEROPLUS_FF=y CONFIG_HID_ZYDACRON=y CONFIG_HID_SENSOR_HUB=y CONFIG_HID_SENSOR_CUSTOM_SENSOR=y CONFIG_HID_ALPS=y CONFIG_HID_MCP2221=y CONFIG_HID_KUNIT_TEST=y # end of Special HID drivers # # USB HID support # CONFIG_USB_HID=y CONFIG_HID_PID=y CONFIG_USB_HIDDEV=y # end of USB HID support # # I2C HID support # CONFIG_I2C_HID_ACPI=y CONFIG_I2C_HID_OF=y CONFIG_I2C_HID_OF_ELAN=y CONFIG_I2C_HID_OF_GOODIX=y # end of I2C HID support CONFIG_I2C_HID_CORE=y # # Surface System Aggregator Module HID support # CONFIG_SURFACE_HID=y CONFIG_SURFACE_KBD=y # end of Surface System Aggregator Module HID support CONFIG_SURFACE_HID_CORE=y # end of HID support CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=y CONFIG_USB_LED_TRIG=y CONFIG_USB_ULPI_BUS=y CONFIG_USB_CONN_GPIO=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y CONFIG_USB_PCI=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y # # Miscellaneous USB options # CONFIG_USB_DEFAULT_PERSIST=y CONFIG_USB_FEW_INIT_RETRIES=y CONFIG_USB_DYNAMIC_MINORS=y CONFIG_USB_OTG=y CONFIG_USB_OTG_PRODUCTLIST=y CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB=y CONFIG_USB_OTG_FSM=y CONFIG_USB_LEDS_TRIGGER_USBPORT=y CONFIG_USB_AUTOSUSPEND_DELAY=2 CONFIG_USB_MON=y # # USB Host Controller Drivers # CONFIG_USB_C67X00_HCD=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DBGCAP=y CONFIG_USB_XHCI_PCI=y CONFIG_USB_XHCI_PCI_RENESAS=y CONFIG_USB_XHCI_PLATFORM=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_EHCI_FSL=y CONFIG_USB_EHCI_HCD_PLATFORM=y CONFIG_USB_OXU210HP_HCD=y CONFIG_USB_ISP116X_HCD=y CONFIG_USB_FOTG210_HCD=y CONFIG_USB_MAX3421_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PCI=y CONFIG_USB_OHCI_HCD_SSB=y CONFIG_USB_OHCI_HCD_PLATFORM=y CONFIG_USB_UHCI_HCD=y CONFIG_USB_U132_HCD=y CONFIG_USB_SL811_HCD=y CONFIG_USB_SL811_HCD_ISO=y CONFIG_USB_SL811_CS=y CONFIG_USB_R8A66597_HCD=y CONFIG_USB_HCD_BCMA=y CONFIG_USB_HCD_SSB=y CONFIG_USB_HCD_TEST_MODE=y # # USB Device Class drivers # CONFIG_USB_ACM=y CONFIG_USB_PRINTER=y CONFIG_USB_WDM=y CONFIG_USB_TMC=y # # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # # also be needed; see USB_STORAGE Help for more info # CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE_DEBUG=y CONFIG_USB_STORAGE_REALTEK=y CONFIG_REALTEK_AUTOPM=y CONFIG_USB_STORAGE_DATAFAB=y CONFIG_USB_STORAGE_FREECOM=y CONFIG_USB_STORAGE_ISD200=y CONFIG_USB_STORAGE_USBAT=y CONFIG_USB_STORAGE_SDDR09=y CONFIG_USB_STORAGE_SDDR55=y CONFIG_USB_STORAGE_JUMPSHOT=y CONFIG_USB_STORAGE_ALAUDA=y CONFIG_USB_STORAGE_ONETOUCH=y CONFIG_USB_STORAGE_KARMA=y CONFIG_USB_STORAGE_CYPRESS_ATACB=y CONFIG_USB_STORAGE_ENE_UB6250=y CONFIG_USB_UAS=y # # USB Imaging devices # CONFIG_USB_MDC800=y CONFIG_USB_MICROTEK=y CONFIG_USBIP_CORE=y CONFIG_USBIP_VHCI_HCD=y CONFIG_USBIP_VHCI_HC_PORTS=8 CONFIG_USBIP_VHCI_NR_HCS=1 CONFIG_USBIP_HOST=y CONFIG_USBIP_VUDC=y CONFIG_USBIP_DEBUG=y CONFIG_USB_CDNS_SUPPORT=y CONFIG_USB_CDNS_HOST=y CONFIG_USB_CDNS3=y CONFIG_USB_CDNS3_GADGET=y CONFIG_USB_CDNS3_HOST=y CONFIG_USB_CDNS3_PCI_WRAP=y CONFIG_USB_CDNSP_PCI=y CONFIG_USB_CDNSP_GADGET=y CONFIG_USB_CDNSP_HOST=y CONFIG_USB_MUSB_HDRC=y # CONFIG_USB_MUSB_HOST is not set # CONFIG_USB_MUSB_GADGET is not set CONFIG_USB_MUSB_DUAL_ROLE=y # # Platform Glue Layer # # # MUSB DMA mode # CONFIG_MUSB_PIO_ONLY=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_ULPI=y # CONFIG_USB_DWC3_HOST is not set # CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_DWC3_DUAL_ROLE=y # # Platform Glue Driver Support # CONFIG_USB_DWC3_PCI=y CONFIG_USB_DWC3_HAPS=y CONFIG_USB_DWC3_OF_SIMPLE=y CONFIG_USB_DWC2=y # CONFIG_USB_DWC2_HOST is not set # # Gadget/Dual-role mode requires USB Gadget support to be enabled # # CONFIG_USB_DWC2_PERIPHERAL is not set CONFIG_USB_DWC2_DUAL_ROLE=y CONFIG_USB_DWC2_PCI=y CONFIG_USB_DWC2_DEBUG=y CONFIG_USB_DWC2_VERBOSE=y CONFIG_USB_DWC2_TRACK_MISSED_SOFS=y CONFIG_USB_DWC2_DEBUG_PERIODIC=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y CONFIG_USB_CHIPIDEA_PCI=y CONFIG_USB_CHIPIDEA_MSM=y CONFIG_USB_CHIPIDEA_IMX=y CONFIG_USB_CHIPIDEA_GENERIC=y CONFIG_USB_CHIPIDEA_TEGRA=y CONFIG_USB_ISP1760=y CONFIG_USB_ISP1760_HCD=y CONFIG_USB_ISP1761_UDC=y # CONFIG_USB_ISP1760_HOST_ROLE is not set # CONFIG_USB_ISP1760_GADGET_ROLE is not set CONFIG_USB_ISP1760_DUAL_ROLE=y # # USB port drivers # CONFIG_USB_USS720=y CONFIG_USB_SERIAL=y CONFIG_USB_SERIAL_CONSOLE=y CONFIG_USB_SERIAL_GENERIC=y CONFIG_USB_SERIAL_SIMPLE=y CONFIG_USB_SERIAL_AIRCABLE=y CONFIG_USB_SERIAL_ARK3116=y CONFIG_USB_SERIAL_BELKIN=y CONFIG_USB_SERIAL_CH341=y CONFIG_USB_SERIAL_WHITEHEAT=y CONFIG_USB_SERIAL_DIGI_ACCELEPORT=y CONFIG_USB_SERIAL_CP210X=y CONFIG_USB_SERIAL_CYPRESS_M8=y CONFIG_USB_SERIAL_EMPEG=y CONFIG_USB_SERIAL_FTDI_SIO=y CONFIG_USB_SERIAL_VISOR=y CONFIG_USB_SERIAL_IPAQ=y CONFIG_USB_SERIAL_IR=y CONFIG_USB_SERIAL_EDGEPORT=y CONFIG_USB_SERIAL_EDGEPORT_TI=y CONFIG_USB_SERIAL_F81232=y CONFIG_USB_SERIAL_F8153X=y CONFIG_USB_SERIAL_GARMIN=y CONFIG_USB_SERIAL_IPW=y CONFIG_USB_SERIAL_IUU=y CONFIG_USB_SERIAL_KEYSPAN_PDA=y CONFIG_USB_SERIAL_KEYSPAN=y CONFIG_USB_SERIAL_KLSI=y CONFIG_USB_SERIAL_KOBIL_SCT=y CONFIG_USB_SERIAL_MCT_U232=y CONFIG_USB_SERIAL_METRO=y CONFIG_USB_SERIAL_MOS7720=y CONFIG_USB_SERIAL_MOS7715_PARPORT=y CONFIG_USB_SERIAL_MOS7840=y CONFIG_USB_SERIAL_MXUPORT=y CONFIG_USB_SERIAL_NAVMAN=y CONFIG_USB_SERIAL_PL2303=y CONFIG_USB_SERIAL_OTI6858=y CONFIG_USB_SERIAL_QCAUX=y CONFIG_USB_SERIAL_QUALCOMM=y CONFIG_USB_SERIAL_SPCP8X5=y CONFIG_USB_SERIAL_SAFE=y CONFIG_USB_SERIAL_SAFE_PADDED=y CONFIG_USB_SERIAL_SIERRAWIRELESS=y CONFIG_USB_SERIAL_SYMBOL=y CONFIG_USB_SERIAL_TI=y CONFIG_USB_SERIAL_CYBERJACK=y CONFIG_USB_SERIAL_WWAN=y CONFIG_USB_SERIAL_OPTION=y CONFIG_USB_SERIAL_OMNINET=y CONFIG_USB_SERIAL_OPTICON=y CONFIG_USB_SERIAL_XSENS_MT=y CONFIG_USB_SERIAL_WISHBONE=y CONFIG_USB_SERIAL_SSU100=y CONFIG_USB_SERIAL_QT2=y CONFIG_USB_SERIAL_UPD78F0730=y CONFIG_USB_SERIAL_XR=y CONFIG_USB_SERIAL_DEBUG=y # # USB Miscellaneous drivers # CONFIG_USB_EMI62=y CONFIG_USB_EMI26=y CONFIG_USB_ADUTUX=y CONFIG_USB_SEVSEG=y CONFIG_USB_LEGOTOWER=y CONFIG_USB_LCD=y CONFIG_USB_CYPRESS_CY7C63=y CONFIG_USB_CYTHERM=y CONFIG_USB_IDMOUSE=y CONFIG_USB_FTDI_ELAN=y CONFIG_USB_APPLEDISPLAY=y CONFIG_APPLE_MFI_FASTCHARGE=y CONFIG_USB_SISUSBVGA=y CONFIG_USB_LD=y CONFIG_USB_TRANCEVIBRATOR=y CONFIG_USB_IOWARRIOR=y CONFIG_USB_TEST=y CONFIG_USB_EHSET_TEST_FIXTURE=y CONFIG_USB_ISIGHTFW=y CONFIG_USB_YUREX=y CONFIG_USB_EZUSB_FX2=y CONFIG_USB_HUB_USB251XB=y CONFIG_USB_HSIC_USB3503=y CONFIG_USB_HSIC_USB4604=y CONFIG_USB_LINK_LAYER_TEST=y CONFIG_USB_CHAOSKEY=y CONFIG_USB_ONBOARD_HUB=y CONFIG_USB_ATM=y CONFIG_USB_SPEEDTOUCH=y CONFIG_USB_CXACRU=y CONFIG_USB_UEAGLEATM=y CONFIG_USB_XUSBATM=y # # USB Physical Layer drivers # CONFIG_USB_PHY=y CONFIG_NOP_USB_XCEIV=y # CONFIG_USB_GPIO_VBUS is not set CONFIG_TAHVO_USB=y CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y CONFIG_USB_ISP1301=y # end of USB Physical Layer drivers CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DEBUG=y CONFIG_USB_GADGET_VERBOSE=y CONFIG_USB_GADGET_DEBUG_FILES=y CONFIG_USB_GADGET_DEBUG_FS=y CONFIG_USB_GADGET_VBUS_DRAW=2 CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 CONFIG_U_SERIAL_CONSOLE=y # # USB Peripheral Controller # CONFIG_USB_FUSB300=y CONFIG_USB_FOTG210_UDC=y CONFIG_USB_GR_UDC=y CONFIG_USB_R8A66597=y CONFIG_USB_PXA27X=y CONFIG_USB_MV_UDC=y CONFIG_USB_MV_U3D=y CONFIG_USB_SNP_CORE=y CONFIG_USB_SNP_UDC_PLAT=y CONFIG_USB_M66592=y CONFIG_USB_BDC_UDC=y CONFIG_USB_AMD5536UDC=y CONFIG_USB_NET2272=y CONFIG_USB_NET2272_DMA=y CONFIG_USB_NET2280=y CONFIG_USB_GOKU=y CONFIG_USB_EG20T=y CONFIG_USB_GADGET_XILINX=y CONFIG_USB_MAX3420_UDC=y CONFIG_USB_DUMMY_HCD=y # end of USB Peripheral Controller CONFIG_USB_LIBCOMPOSITE=y CONFIG_USB_F_ACM=y CONFIG_USB_F_SS_LB=y CONFIG_USB_U_SERIAL=y CONFIG_USB_U_ETHER=y CONFIG_USB_U_AUDIO=y CONFIG_USB_F_SERIAL=y CONFIG_USB_F_OBEX=y CONFIG_USB_F_NCM=y CONFIG_USB_F_ECM=y CONFIG_USB_F_PHONET=y CONFIG_USB_F_EEM=y CONFIG_USB_F_SUBSET=y CONFIG_USB_F_RNDIS=y CONFIG_USB_F_MASS_STORAGE=y CONFIG_USB_F_FS=y CONFIG_USB_F_UAC1=y CONFIG_USB_F_UAC1_LEGACY=y CONFIG_USB_F_UAC2=y CONFIG_USB_F_UVC=y CONFIG_USB_F_MIDI=y CONFIG_USB_F_HID=y CONFIG_USB_F_PRINTER=y CONFIG_USB_F_TCM=y CONFIG_USB_CONFIGFS=y CONFIG_USB_CONFIGFS_SERIAL=y CONFIG_USB_CONFIGFS_ACM=y CONFIG_USB_CONFIGFS_OBEX=y CONFIG_USB_CONFIGFS_NCM=y CONFIG_USB_CONFIGFS_ECM=y CONFIG_USB_CONFIGFS_ECM_SUBSET=y CONFIG_USB_CONFIGFS_RNDIS=y CONFIG_USB_CONFIGFS_EEM=y CONFIG_USB_CONFIGFS_PHONET=y CONFIG_USB_CONFIGFS_MASS_STORAGE=y CONFIG_USB_CONFIGFS_F_LB_SS=y CONFIG_USB_CONFIGFS_F_FS=y CONFIG_USB_CONFIGFS_F_UAC1=y CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y CONFIG_USB_CONFIGFS_F_UAC2=y CONFIG_USB_CONFIGFS_F_MIDI=y CONFIG_USB_CONFIGFS_F_HID=y CONFIG_USB_CONFIGFS_F_UVC=y CONFIG_USB_CONFIGFS_F_PRINTER=y CONFIG_USB_CONFIGFS_F_TCM=y # # USB Gadget precomposed configurations # CONFIG_USB_ZERO=y CONFIG_USB_ZERO_HNPTEST=y CONFIG_USB_AUDIO=y CONFIG_GADGET_UAC1=y CONFIG_GADGET_UAC1_LEGACY=y CONFIG_USB_ETH=y CONFIG_USB_ETH_RNDIS=y CONFIG_USB_ETH_EEM=y CONFIG_USB_G_NCM=y CONFIG_USB_GADGETFS=y CONFIG_USB_FUNCTIONFS=y CONFIG_USB_FUNCTIONFS_ETH=y CONFIG_USB_FUNCTIONFS_RNDIS=y CONFIG_USB_FUNCTIONFS_GENERIC=y CONFIG_USB_MASS_STORAGE=y CONFIG_USB_GADGET_TARGET=y CONFIG_USB_G_SERIAL=y CONFIG_USB_MIDI_GADGET=y CONFIG_USB_G_PRINTER=y CONFIG_USB_CDC_COMPOSITE=y CONFIG_USB_G_NOKIA=y CONFIG_USB_G_ACM_MS=y CONFIG_USB_G_MULTI=y CONFIG_USB_G_MULTI_RNDIS=y CONFIG_USB_G_MULTI_CDC=y CONFIG_USB_G_HID=y CONFIG_USB_G_DBGP=y # CONFIG_USB_G_DBGP_PRINTK is not set CONFIG_USB_G_DBGP_SERIAL=y CONFIG_USB_G_WEBCAM=y CONFIG_USB_RAW_GADGET=y # end of USB Gadget precomposed configurations CONFIG_TYPEC=y CONFIG_TYPEC_TCPM=y CONFIG_TYPEC_TCPCI=y CONFIG_TYPEC_RT1711H=y CONFIG_TYPEC_MT6360=y CONFIG_TYPEC_TCPCI_MT6370=y CONFIG_TYPEC_TCPCI_MAXIM=y CONFIG_TYPEC_FUSB302=y CONFIG_TYPEC_WCOVE=y CONFIG_TYPEC_UCSI=y CONFIG_UCSI_CCG=y CONFIG_UCSI_ACPI=y CONFIG_UCSI_STM32G0=y CONFIG_TYPEC_TPS6598X=y CONFIG_TYPEC_ANX7411=y CONFIG_TYPEC_RT1719=y CONFIG_TYPEC_HD3SS3220=y CONFIG_TYPEC_STUSB160X=y CONFIG_TYPEC_WUSB3801=y # # USB Type-C Multiplexer/DeMultiplexer Switch support # CONFIG_TYPEC_MUX_FSA4480=y CONFIG_TYPEC_MUX_PI3USB30532=y CONFIG_TYPEC_MUX_INTEL_PMC=y # end of USB Type-C Multiplexer/DeMultiplexer Switch support # # USB Type-C Alternate Mode drivers # CONFIG_TYPEC_DP_ALTMODE=y CONFIG_TYPEC_NVIDIA_ALTMODE=y # end of USB Type-C Alternate Mode drivers CONFIG_USB_ROLE_SWITCH=y CONFIG_USB_ROLES_INTEL_XHCI=y CONFIG_MMC=y CONFIG_PWRSEQ_EMMC=y CONFIG_PWRSEQ_SD8787=y CONFIG_PWRSEQ_SIMPLE=y CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_MINORS=8 CONFIG_SDIO_UART=y CONFIG_MMC_TEST=y CONFIG_MMC_CRYPTO=y # # MMC/SD/SDIO Host Controller Drivers # CONFIG_MMC_DEBUG=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_IO_ACCESSORS=y CONFIG_MMC_SDHCI_PCI=y CONFIG_MMC_RICOH_MMC=y CONFIG_MMC_SDHCI_ACPI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_OF_ARASAN=y CONFIG_MMC_SDHCI_OF_AT91=y CONFIG_MMC_SDHCI_OF_DWCMSHC=y CONFIG_MMC_SDHCI_CADENCE=y CONFIG_MMC_SDHCI_F_SDH30=y CONFIG_MMC_SDHCI_MILBEAUT=y CONFIG_MMC_WBSD=y CONFIG_MMC_ALCOR=y CONFIG_MMC_TIFM_SD=y CONFIG_MMC_SPI=y CONFIG_MMC_SDRICOH_CS=y CONFIG_MMC_CB710=y CONFIG_MMC_VIA_SDMMC=y CONFIG_MMC_VUB300=y CONFIG_MMC_USHC=y CONFIG_MMC_USDHI6ROL0=y CONFIG_MMC_REALTEK_PCI=y CONFIG_MMC_REALTEK_USB=y CONFIG_MMC_CQHCI=y CONFIG_MMC_HSQ=y CONFIG_MMC_TOSHIBA_PCI=y CONFIG_MMC_MTK=y CONFIG_MMC_SDHCI_XENON=y CONFIG_MMC_SDHCI_OMAP=y CONFIG_MMC_SDHCI_AM654=y CONFIG_MMC_SDHCI_EXTERNAL_DMA=y CONFIG_MMC_LITEX=y CONFIG_SCSI_UFSHCD=y CONFIG_SCSI_UFS_BSG=y CONFIG_SCSI_UFS_CRYPTO=y CONFIG_SCSI_UFS_HPB=y CONFIG_SCSI_UFS_FAULT_INJECTION=y CONFIG_SCSI_UFS_HWMON=y CONFIG_SCSI_UFSHCD_PCI=y CONFIG_SCSI_UFS_DWC_TC_PCI=y CONFIG_SCSI_UFSHCD_PLATFORM=y CONFIG_SCSI_UFS_CDNS_PLATFORM=y CONFIG_SCSI_UFS_DWC_TC_PLATFORM=y CONFIG_MEMSTICK=y CONFIG_MEMSTICK_DEBUG=y # # MemoryStick drivers # CONFIG_MEMSTICK_UNSAFE_RESUME=y CONFIG_MSPRO_BLOCK=y CONFIG_MS_BLOCK=y # # MemoryStick Host Controller Drivers # CONFIG_MEMSTICK_TIFM_MS=y CONFIG_MEMSTICK_JMICRON_38X=y CONFIG_MEMSTICK_R592=y CONFIG_MEMSTICK_REALTEK_PCI=y CONFIG_MEMSTICK_REALTEK_USB=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLASS_FLASH=y CONFIG_LEDS_CLASS_MULTICOLOR=y CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y # # LED drivers # CONFIG_LEDS_88PM860X=y CONFIG_LEDS_AN30259A=y CONFIG_LEDS_APU=y CONFIG_LEDS_AW2013=y CONFIG_LEDS_BCM6328=y CONFIG_LEDS_BCM6358=y CONFIG_LEDS_CPCAP=y CONFIG_LEDS_CR0014114=y CONFIG_LEDS_EL15203000=y CONFIG_LEDS_LM3530=y CONFIG_LEDS_LM3532=y CONFIG_LEDS_LM3533=y CONFIG_LEDS_LM3642=y CONFIG_LEDS_LM3692X=y CONFIG_LEDS_MT6323=y CONFIG_LEDS_NET48XX=y CONFIG_LEDS_WRAP=y CONFIG_LEDS_PCA9532=y CONFIG_LEDS_PCA9532_GPIO=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_LP3944=y CONFIG_LEDS_LP3952=y CONFIG_LEDS_LP50XX=y CONFIG_LEDS_LP55XX_COMMON=y CONFIG_LEDS_LP5521=y CONFIG_LEDS_LP5523=y CONFIG_LEDS_LP5562=y CONFIG_LEDS_LP8501=y CONFIG_LEDS_LP8788=y CONFIG_LEDS_LP8860=y CONFIG_LEDS_PCA955X=y CONFIG_LEDS_PCA955X_GPIO=y CONFIG_LEDS_PCA963X=y CONFIG_LEDS_WM831X_STATUS=y CONFIG_LEDS_WM8350=y CONFIG_LEDS_DA903X=y CONFIG_LEDS_DA9052=y CONFIG_LEDS_DAC124S085=y CONFIG_LEDS_PWM=y CONFIG_LEDS_REGULATOR=y CONFIG_LEDS_BD2802=y CONFIG_LEDS_INTEL_SS4200=y CONFIG_LEDS_LT3593=y CONFIG_LEDS_ADP5520=y CONFIG_LEDS_MC13783=y CONFIG_LEDS_TCA6507=y CONFIG_LEDS_TLC591XX=y CONFIG_LEDS_MAX77650=y CONFIG_LEDS_MAX8997=y CONFIG_LEDS_LM355x=y CONFIG_LEDS_OT200=y CONFIG_LEDS_MENF21BMC=y CONFIG_LEDS_IS31FL319X=y CONFIG_LEDS_IS31FL32XX=y # # LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) # CONFIG_LEDS_BLINKM=y CONFIG_LEDS_SYSCON=y CONFIG_LEDS_MLXCPLD=y CONFIG_LEDS_MLXREG=y CONFIG_LEDS_USER=y CONFIG_LEDS_NIC78BX=y CONFIG_LEDS_SPI_BYTE=y CONFIG_LEDS_TI_LMU_COMMON=y CONFIG_LEDS_LM3697=y CONFIG_LEDS_LM36274=y CONFIG_LEDS_TPS6105X=y CONFIG_LEDS_LGM=y # # Flash and Torch LED drivers # CONFIG_LEDS_AAT1290=y CONFIG_LEDS_AS3645A=y CONFIG_LEDS_KTD2692=y CONFIG_LEDS_LM3601X=y CONFIG_LEDS_MAX77693=y CONFIG_LEDS_MT6360=y CONFIG_LEDS_RT4505=y CONFIG_LEDS_RT8515=y CONFIG_LEDS_SGM3140=y # # RGB LED drivers # CONFIG_LEDS_PWM_MULTICOLOR=y CONFIG_LEDS_QCOM_LPG=y # # LED Triggers # CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_ONESHOT=y CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_MTD=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_ACTIVITY=y CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y # # iptables trigger is under Netfilter config (LED target) # CONFIG_LEDS_TRIGGER_TRANSIENT=y CONFIG_LEDS_TRIGGER_CAMERA=y CONFIG_LEDS_TRIGGER_PANIC=y CONFIG_LEDS_TRIGGER_NETDEV=y CONFIG_LEDS_TRIGGER_PATTERN=y CONFIG_LEDS_TRIGGER_AUDIO=y CONFIG_LEDS_TRIGGER_TTY=y # # Simple LED drivers # CONFIG_LEDS_SIEMENS_SIMATIC_IPC=y CONFIG_ACCESSIBILITY=y CONFIG_A11Y_BRAILLE_CONSOLE=y # # Speakup console speech # CONFIG_SPEAKUP=y CONFIG_SPEAKUP_SERIALIO=y CONFIG_SPEAKUP_SYNTH_ACNTSA=y CONFIG_SPEAKUP_SYNTH_ACNTPC=y CONFIG_SPEAKUP_SYNTH_APOLLO=y CONFIG_SPEAKUP_SYNTH_AUDPTR=y CONFIG_SPEAKUP_SYNTH_BNS=y CONFIG_SPEAKUP_SYNTH_DECTLK=y CONFIG_SPEAKUP_SYNTH_DECEXT=y CONFIG_SPEAKUP_SYNTH_DECPC=m CONFIG_SPEAKUP_SYNTH_DTLK=y CONFIG_SPEAKUP_SYNTH_KEYPC=y CONFIG_SPEAKUP_SYNTH_LTLK=y CONFIG_SPEAKUP_SYNTH_SOFT=y CONFIG_SPEAKUP_SYNTH_SPKOUT=y CONFIG_SPEAKUP_SYNTH_TXPRT=y CONFIG_SPEAKUP_SYNTH_DUMMY=y # end of Speakup console speech CONFIG_INFINIBAND=y CONFIG_INFINIBAND_USER_MAD=y CONFIG_INFINIBAND_USER_ACCESS=y CONFIG_INFINIBAND_USER_MEM=y CONFIG_INFINIBAND_ON_DEMAND_PAGING=y CONFIG_INFINIBAND_ADDR_TRANS=y CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y CONFIG_INFINIBAND_CXGB4=y CONFIG_INFINIBAND_IRDMA=y CONFIG_MLX4_INFINIBAND=y CONFIG_MLX5_INFINIBAND=y CONFIG_INFINIBAND_MTHCA=y CONFIG_INFINIBAND_MTHCA_DEBUG=y CONFIG_INFINIBAND_OCRDMA=y CONFIG_INFINIBAND_USNIC=y CONFIG_INFINIBAND_VMWARE_PVRDMA=y CONFIG_INFINIBAND_IPOIB=y CONFIG_INFINIBAND_IPOIB_CM=y CONFIG_INFINIBAND_IPOIB_DEBUG=y CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y CONFIG_INFINIBAND_SRP=y CONFIG_INFINIBAND_SRPT=y CONFIG_INFINIBAND_ISER=y CONFIG_INFINIBAND_ISERT=y CONFIG_INFINIBAND_RTRS=y CONFIG_INFINIBAND_RTRS_CLIENT=y CONFIG_INFINIBAND_RTRS_SERVER=y CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y CONFIG_EDAC=y CONFIG_EDAC_LEGACY_SYSFS=y CONFIG_EDAC_DEBUG=y CONFIG_EDAC_DECODE_MCE=y CONFIG_EDAC_GHES=y CONFIG_EDAC_AMD64=y CONFIG_EDAC_AMD76X=y CONFIG_EDAC_E7XXX=y CONFIG_EDAC_E752X=y CONFIG_EDAC_I82875P=y CONFIG_EDAC_I82975X=y CONFIG_EDAC_I3000=y CONFIG_EDAC_I3200=y CONFIG_EDAC_IE31200=y CONFIG_EDAC_X38=y CONFIG_EDAC_I5400=y CONFIG_EDAC_I7CORE=y CONFIG_EDAC_I82860=y CONFIG_EDAC_R82600=y # CONFIG_EDAC_I5000 is not set CONFIG_EDAC_I5100=y CONFIG_EDAC_I7300=y CONFIG_RTC_LIB=y CONFIG_RTC_MC146818_LIB=y CONFIG_RTC_CLASS=y CONFIG_RTC_HCTOSYS=y CONFIG_RTC_HCTOSYS_DEVICE="rtc0" CONFIG_RTC_SYSTOHC=y CONFIG_RTC_SYSTOHC_DEVICE="rtc0" CONFIG_RTC_DEBUG=y CONFIG_RTC_LIB_KUNIT_TEST=y CONFIG_RTC_NVMEM=y # # RTC interfaces # CONFIG_RTC_INTF_SYSFS=y CONFIG_RTC_INTF_PROC=y CONFIG_RTC_INTF_DEV=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_DRV_TEST=y # # I2C RTC drivers # CONFIG_RTC_DRV_88PM860X=y CONFIG_RTC_DRV_88PM80X=y CONFIG_RTC_DRV_ABB5ZES3=y CONFIG_RTC_DRV_ABEOZ9=y CONFIG_RTC_DRV_ABX80X=y CONFIG_RTC_DRV_AS3722=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_DS1307_CENTURY=y CONFIG_RTC_DRV_DS1374=y CONFIG_RTC_DRV_DS1374_WDT=y CONFIG_RTC_DRV_DS1672=y CONFIG_RTC_DRV_HYM8563=y CONFIG_RTC_DRV_LP8788=y CONFIG_RTC_DRV_MAX6900=y CONFIG_RTC_DRV_MAX8907=y CONFIG_RTC_DRV_MAX8925=y CONFIG_RTC_DRV_MAX8998=y CONFIG_RTC_DRV_MAX8997=y CONFIG_RTC_DRV_MAX77686=y CONFIG_RTC_DRV_NCT3018Y=y CONFIG_RTC_DRV_RK808=y CONFIG_RTC_DRV_RS5C372=y CONFIG_RTC_DRV_ISL1208=y CONFIG_RTC_DRV_ISL12022=y CONFIG_RTC_DRV_ISL12026=y CONFIG_RTC_DRV_X1205=y CONFIG_RTC_DRV_PCF8523=y CONFIG_RTC_DRV_PCF85063=y CONFIG_RTC_DRV_PCF85363=y CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_PCF8583=y CONFIG_RTC_DRV_M41T80=y CONFIG_RTC_DRV_M41T80_WDT=y CONFIG_RTC_DRV_BD70528=y CONFIG_RTC_DRV_BQ32K=y CONFIG_RTC_DRV_TWL4030=y CONFIG_RTC_DRV_PALMAS=y CONFIG_RTC_DRV_TPS6586X=y CONFIG_RTC_DRV_TPS65910=y CONFIG_RTC_DRV_RC5T583=y CONFIG_RTC_DRV_RC5T619=y CONFIG_RTC_DRV_S35390A=y CONFIG_RTC_DRV_FM3130=y CONFIG_RTC_DRV_RX8010=y CONFIG_RTC_DRV_RX8581=y CONFIG_RTC_DRV_RX8025=y CONFIG_RTC_DRV_EM3027=y CONFIG_RTC_DRV_RV3028=y CONFIG_RTC_DRV_RV3032=y CONFIG_RTC_DRV_RV8803=y CONFIG_RTC_DRV_S5M=y CONFIG_RTC_DRV_SD3078=y # # SPI RTC drivers # CONFIG_RTC_DRV_M41T93=y CONFIG_RTC_DRV_M41T94=y CONFIG_RTC_DRV_DS1302=y CONFIG_RTC_DRV_DS1305=y CONFIG_RTC_DRV_DS1343=y CONFIG_RTC_DRV_DS1347=y CONFIG_RTC_DRV_DS1390=y CONFIG_RTC_DRV_MAX6916=y CONFIG_RTC_DRV_R9701=y CONFIG_RTC_DRV_RX4581=y CONFIG_RTC_DRV_RS5C348=y CONFIG_RTC_DRV_MAX6902=y CONFIG_RTC_DRV_PCF2123=y CONFIG_RTC_DRV_MCP795=y CONFIG_RTC_I2C_AND_SPI=y # # SPI and I2C RTC drivers # CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_DS3232_HWMON=y CONFIG_RTC_DRV_PCF2127=y CONFIG_RTC_DRV_RV3029C2=y CONFIG_RTC_DRV_RV3029_HWMON=y CONFIG_RTC_DRV_RX6110=y # # Platform RTC drivers # CONFIG_RTC_DRV_CMOS=y CONFIG_RTC_DRV_DS1286=y CONFIG_RTC_DRV_DS1511=y CONFIG_RTC_DRV_DS1553=y CONFIG_RTC_DRV_DS1685_FAMILY=y CONFIG_RTC_DRV_DS1685=y # CONFIG_RTC_DRV_DS1689 is not set # CONFIG_RTC_DRV_DS17285 is not set # CONFIG_RTC_DRV_DS17485 is not set # CONFIG_RTC_DRV_DS17885 is not set CONFIG_RTC_DRV_DS1742=y CONFIG_RTC_DRV_DS2404=y CONFIG_RTC_DRV_DA9052=y CONFIG_RTC_DRV_DA9055=y CONFIG_RTC_DRV_DA9063=y CONFIG_RTC_DRV_STK17TA8=y CONFIG_RTC_DRV_M48T86=y CONFIG_RTC_DRV_M48T35=y CONFIG_RTC_DRV_M48T59=y CONFIG_RTC_DRV_MSM6242=y CONFIG_RTC_DRV_BQ4802=y CONFIG_RTC_DRV_RP5C01=y CONFIG_RTC_DRV_V3020=y CONFIG_RTC_DRV_WM831X=y CONFIG_RTC_DRV_WM8350=y CONFIG_RTC_DRV_PCF50633=y CONFIG_RTC_DRV_ZYNQMP=y CONFIG_RTC_DRV_CROS_EC=y CONFIG_RTC_DRV_NTXEC=y # # on-CPU RTC drivers # CONFIG_RTC_DRV_CADENCE=y CONFIG_RTC_DRV_FTRTC010=y CONFIG_RTC_DRV_PCAP=y CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MT6397=y CONFIG_RTC_DRV_R7301=y CONFIG_RTC_DRV_CPCAP=y # # HID Sensor RTC drivers # CONFIG_RTC_DRV_HID_SENSOR_TIME=y CONFIG_RTC_DRV_GOLDFISH=y CONFIG_RTC_DRV_WILCO_EC=y CONFIG_DMADEVICES=y CONFIG_DMADEVICES_DEBUG=y CONFIG_DMADEVICES_VDEBUG=y # # DMA Devices # CONFIG_DMA_ENGINE=y CONFIG_DMA_VIRTUAL_CHANNELS=y CONFIG_DMA_ACPI=y CONFIG_DMA_OF=y CONFIG_ALTERA_MSGDMA=y CONFIG_DW_AXI_DMAC=y CONFIG_FSL_EDMA=y CONFIG_INTEL_IDMA64=y CONFIG_PCH_DMA=y CONFIG_PLX_DMA=y CONFIG_TIMB_DMA=y CONFIG_XILINX_ZYNQMP_DPDMA=y CONFIG_QCOM_HIDMA_MGMT=y CONFIG_QCOM_HIDMA=y CONFIG_DW_DMAC_CORE=y CONFIG_DW_DMAC=y CONFIG_DW_DMAC_PCI=y CONFIG_DW_EDMA=y CONFIG_DW_EDMA_PCIE=y CONFIG_HSU_DMA=y CONFIG_HSU_DMA_PCI=y CONFIG_SF_PDMA=y CONFIG_INTEL_LDMA=y # # DMA Clients # CONFIG_ASYNC_TX_DMA=y CONFIG_DMATEST=y CONFIG_DMA_ENGINE_RAID=y # # DMABUF options # CONFIG_SYNC_FILE=y CONFIG_SW_SYNC=y CONFIG_UDMABUF=y CONFIG_DMABUF_MOVE_NOTIFY=y CONFIG_DMABUF_DEBUG=y CONFIG_DMABUF_SELFTESTS=y CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_SYSFS_STATS=y CONFIG_DMABUF_HEAPS_SYSTEM=y CONFIG_DMABUF_HEAPS_CMA=y # end of DMABUF options CONFIG_AUXDISPLAY=y CONFIG_CHARLCD=y CONFIG_LINEDISP=y CONFIG_HD44780_COMMON=y CONFIG_HD44780=y CONFIG_KS0108=y CONFIG_KS0108_PORT=0x378 CONFIG_KS0108_DELAY=2 CONFIG_CFAG12864B=y CONFIG_CFAG12864B_RATE=20 CONFIG_IMG_ASCII_LCD=y CONFIG_HT16K33=y CONFIG_LCD2S=y CONFIG_PARPORT_PANEL=y CONFIG_PANEL_PARPORT=0 CONFIG_PANEL_PROFILE=5 CONFIG_PANEL_CHANGE_MESSAGE=y CONFIG_PANEL_BOOT_MESSAGE="" # CONFIG_CHARLCD_BL_OFF is not set # CONFIG_CHARLCD_BL_ON is not set CONFIG_CHARLCD_BL_FLASH=y CONFIG_PANEL=y CONFIG_UIO=y CONFIG_UIO_CIF=y CONFIG_UIO_PDRV_GENIRQ=y CONFIG_UIO_DMEM_GENIRQ=y CONFIG_UIO_AEC=y CONFIG_UIO_SERCOS3=y CONFIG_UIO_PCI_GENERIC=y CONFIG_UIO_NETX=y CONFIG_UIO_PRUSS=y CONFIG_UIO_MF624=y CONFIG_UIO_HV_GENERIC=y CONFIG_UIO_DFL=y CONFIG_VFIO=y CONFIG_VFIO_IOMMU_TYPE1=y CONFIG_VFIO_VIRQFD=y CONFIG_VFIO_NOIOMMU=y CONFIG_VFIO_PCI_CORE=y CONFIG_VFIO_PCI_MMAP=y CONFIG_VFIO_PCI_INTX=y CONFIG_VFIO_PCI=y CONFIG_VFIO_PCI_VGA=y CONFIG_VFIO_PCI_IGD=y CONFIG_MLX5_VFIO_PCI=y CONFIG_VFIO_MDEV=y CONFIG_IRQ_BYPASS_MANAGER=y CONFIG_VIRT_DRIVERS=y CONFIG_VMGENID=y CONFIG_VBOXGUEST=y CONFIG_NITRO_ENCLAVES=y CONFIG_NITRO_ENCLAVES_MISC_DEV_TEST=y CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO=y CONFIG_VIRTIO_PCI_LIB=y CONFIG_VIRTIO_PCI_LIB_LEGACY=y CONFIG_VIRTIO_MENU=y CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_PCI_LEGACY=y CONFIG_VIRTIO_VDPA=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_INPUT=y CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y CONFIG_VIRTIO_DMA_SHARED_BUFFER=y CONFIG_VDPA=y CONFIG_VDPA_SIM=y CONFIG_VDPA_SIM_NET=y CONFIG_VDPA_SIM_BLOCK=y CONFIG_VDPA_USER=y CONFIG_IFCVF=y CONFIG_MLX5_VDPA=y CONFIG_MLX5_VDPA_NET=y CONFIG_VP_VDPA=y CONFIG_ALIBABA_ENI_VDPA=y CONFIG_VHOST_IOTLB=y CONFIG_VHOST_RING=y CONFIG_VHOST=y CONFIG_VHOST_MENU=y CONFIG_VHOST_NET=y CONFIG_VHOST_SCSI=y CONFIG_VHOST_VSOCK=y CONFIG_VHOST_VDPA=y CONFIG_VHOST_CROSS_ENDIAN_LEGACY=y # # Microsoft Hyper-V guest support # CONFIG_HYPERV=y CONFIG_HYPERV_TIMER=y CONFIG_HYPERV_UTILS=y CONFIG_HYPERV_BALLOON=y # end of Microsoft Hyper-V guest support CONFIG_GREYBUS=y CONFIG_GREYBUS_ES2=y CONFIG_COMEDI=y CONFIG_COMEDI_DEBUG=y CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048 CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480 CONFIG_COMEDI_MISC_DRIVERS=y CONFIG_COMEDI_BOND=y CONFIG_COMEDI_TEST=y CONFIG_COMEDI_PARPORT=y CONFIG_COMEDI_SSV_DNP=y CONFIG_COMEDI_ISA_DRIVERS=y CONFIG_COMEDI_PCL711=y CONFIG_COMEDI_PCL724=y CONFIG_COMEDI_PCL726=y CONFIG_COMEDI_PCL730=y CONFIG_COMEDI_PCL812=y CONFIG_COMEDI_PCL816=y CONFIG_COMEDI_PCL818=y CONFIG_COMEDI_PCM3724=y CONFIG_COMEDI_AMPLC_DIO200_ISA=y CONFIG_COMEDI_AMPLC_PC236_ISA=y CONFIG_COMEDI_AMPLC_PC263_ISA=y CONFIG_COMEDI_RTI800=y CONFIG_COMEDI_RTI802=y CONFIG_COMEDI_DAC02=y CONFIG_COMEDI_DAS16M1=y CONFIG_COMEDI_DAS08_ISA=y CONFIG_COMEDI_DAS16=y CONFIG_COMEDI_DAS800=y CONFIG_COMEDI_DAS1800=y CONFIG_COMEDI_DAS6402=y CONFIG_COMEDI_DT2801=y CONFIG_COMEDI_DT2811=y CONFIG_COMEDI_DT2814=y CONFIG_COMEDI_DT2815=y CONFIG_COMEDI_DT2817=y CONFIG_COMEDI_DT282X=y CONFIG_COMEDI_DMM32AT=y CONFIG_COMEDI_FL512=y CONFIG_COMEDI_AIO_AIO12_8=y CONFIG_COMEDI_AIO_IIRO_16=y CONFIG_COMEDI_II_PCI20KC=y CONFIG_COMEDI_C6XDIGIO=y CONFIG_COMEDI_MPC624=y CONFIG_COMEDI_ADQ12B=y CONFIG_COMEDI_NI_AT_A2150=y CONFIG_COMEDI_NI_AT_AO=y CONFIG_COMEDI_NI_ATMIO=y CONFIG_COMEDI_NI_ATMIO16D=y CONFIG_COMEDI_NI_LABPC_ISA=y CONFIG_COMEDI_PCMAD=y CONFIG_COMEDI_PCMDA12=y CONFIG_COMEDI_PCMMIO=y CONFIG_COMEDI_PCMUIO=y CONFIG_COMEDI_MULTIQ3=y CONFIG_COMEDI_S526=y CONFIG_COMEDI_PCI_DRIVERS=y CONFIG_COMEDI_8255_PCI=y CONFIG_COMEDI_ADDI_WATCHDOG=y CONFIG_COMEDI_ADDI_APCI_1032=y CONFIG_COMEDI_ADDI_APCI_1500=y CONFIG_COMEDI_ADDI_APCI_1516=y CONFIG_COMEDI_ADDI_APCI_1564=y CONFIG_COMEDI_ADDI_APCI_16XX=y CONFIG_COMEDI_ADDI_APCI_2032=y CONFIG_COMEDI_ADDI_APCI_2200=y CONFIG_COMEDI_ADDI_APCI_3120=y CONFIG_COMEDI_ADDI_APCI_3501=y CONFIG_COMEDI_ADDI_APCI_3XXX=y CONFIG_COMEDI_ADL_PCI6208=y CONFIG_COMEDI_ADL_PCI7X3X=y CONFIG_COMEDI_ADL_PCI8164=y CONFIG_COMEDI_ADL_PCI9111=y CONFIG_COMEDI_ADL_PCI9118=y CONFIG_COMEDI_ADV_PCI1710=y CONFIG_COMEDI_ADV_PCI1720=y CONFIG_COMEDI_ADV_PCI1723=y CONFIG_COMEDI_ADV_PCI1724=y CONFIG_COMEDI_ADV_PCI1760=y CONFIG_COMEDI_ADV_PCI_DIO=y CONFIG_COMEDI_AMPLC_DIO200_PCI=y CONFIG_COMEDI_AMPLC_PC236_PCI=y CONFIG_COMEDI_AMPLC_PC263_PCI=y CONFIG_COMEDI_AMPLC_PCI224=y CONFIG_COMEDI_AMPLC_PCI230=y CONFIG_COMEDI_CONTEC_PCI_DIO=y CONFIG_COMEDI_DAS08_PCI=y CONFIG_COMEDI_DT3000=y CONFIG_COMEDI_DYNA_PCI10XX=y CONFIG_COMEDI_GSC_HPDI=y CONFIG_COMEDI_MF6X4=y CONFIG_COMEDI_ICP_MULTI=y CONFIG_COMEDI_DAQBOARD2000=y CONFIG_COMEDI_JR3_PCI=y CONFIG_COMEDI_KE_COUNTER=y CONFIG_COMEDI_CB_PCIDAS64=y CONFIG_COMEDI_CB_PCIDAS=y CONFIG_COMEDI_CB_PCIDDA=y CONFIG_COMEDI_CB_PCIMDAS=y CONFIG_COMEDI_CB_PCIMDDA=y CONFIG_COMEDI_ME4000=y CONFIG_COMEDI_ME_DAQ=y CONFIG_COMEDI_NI_6527=y CONFIG_COMEDI_NI_65XX=y CONFIG_COMEDI_NI_660X=y CONFIG_COMEDI_NI_670X=y CONFIG_COMEDI_NI_LABPC_PCI=y CONFIG_COMEDI_NI_PCIDIO=y CONFIG_COMEDI_NI_PCIMIO=y CONFIG_COMEDI_RTD520=y CONFIG_COMEDI_S626=y CONFIG_COMEDI_MITE=y CONFIG_COMEDI_NI_TIOCMD=y CONFIG_COMEDI_PCMCIA_DRIVERS=y CONFIG_COMEDI_CB_DAS16_CS=y CONFIG_COMEDI_DAS08_CS=y CONFIG_COMEDI_NI_DAQ_700_CS=y CONFIG_COMEDI_NI_DAQ_DIO24_CS=y CONFIG_COMEDI_NI_LABPC_CS=y CONFIG_COMEDI_NI_MIO_CS=y CONFIG_COMEDI_QUATECH_DAQP_CS=y CONFIG_COMEDI_USB_DRIVERS=y CONFIG_COMEDI_DT9812=y CONFIG_COMEDI_NI_USB6501=y CONFIG_COMEDI_USBDUX=y CONFIG_COMEDI_USBDUXFAST=y CONFIG_COMEDI_USBDUXSIGMA=y CONFIG_COMEDI_VMK80XX=y CONFIG_COMEDI_8254=y CONFIG_COMEDI_8255=y CONFIG_COMEDI_8255_SA=y CONFIG_COMEDI_KCOMEDILIB=y CONFIG_COMEDI_AMPLC_DIO200=y CONFIG_COMEDI_AMPLC_PC236=y CONFIG_COMEDI_DAS08=y CONFIG_COMEDI_ISADMA=y CONFIG_COMEDI_NI_LABPC=y CONFIG_COMEDI_NI_LABPC_ISADMA=y CONFIG_COMEDI_NI_TIO=y CONFIG_COMEDI_NI_ROUTING=y CONFIG_COMEDI_TESTS=y CONFIG_COMEDI_TESTS_EXAMPLE=y CONFIG_COMEDI_TESTS_NI_ROUTES=y CONFIG_STAGING=y CONFIG_PRISM2_USB=y CONFIG_RTL8192U=m CONFIG_RTLLIB=m CONFIG_RTLLIB_CRYPTO_CCMP=m CONFIG_RTLLIB_CRYPTO_TKIP=m CONFIG_RTLLIB_CRYPTO_WEP=m CONFIG_RTL8192E=m CONFIG_RTL8723BS=m CONFIG_R8712U=y CONFIG_R8188EU=m CONFIG_RTS5208=y CONFIG_VT6655=m CONFIG_VT6656=m # # IIO staging drivers # # # Accelerometers # CONFIG_ADIS16203=y CONFIG_ADIS16240=y # end of Accelerometers # # Analog to digital converters # CONFIG_AD7816=y # end of Analog to digital converters # # Analog digital bi-direction converters # CONFIG_ADT7316=y CONFIG_ADT7316_SPI=y CONFIG_ADT7316_I2C=y # end of Analog digital bi-direction converters # # Direct Digital Synthesis # CONFIG_AD9832=y CONFIG_AD9834=y # end of Direct Digital Synthesis # # Network Analyzer, Impedance Converters # CONFIG_AD5933=y # end of Network Analyzer, Impedance Converters # # Active energy metering IC # CONFIG_ADE7854=y CONFIG_ADE7854_I2C=y CONFIG_ADE7854_SPI=y # end of Active energy metering IC # # Resolver to digital converters # CONFIG_AD2S1210=y # end of Resolver to digital converters # end of IIO staging drivers CONFIG_FB_SM750=y CONFIG_STAGING_MEDIA=y CONFIG_INTEL_ATOMISP=y CONFIG_VIDEO_ATOMISP=y CONFIG_VIDEO_ATOMISP_ISP2401=y CONFIG_VIDEO_ATOMISP_OV2722=y CONFIG_VIDEO_ATOMISP_GC2235=y CONFIG_VIDEO_ATOMISP_MSRLIST_HELPER=y CONFIG_VIDEO_ATOMISP_MT9M114=y CONFIG_VIDEO_ATOMISP_GC0310=y CONFIG_VIDEO_ATOMISP_OV2680=y CONFIG_VIDEO_ATOMISP_OV5693=y CONFIG_VIDEO_ATOMISP_LM3554=y CONFIG_VIDEO_IPU3_IMGU=y CONFIG_VIDEO_MAX96712=y CONFIG_STAGING_MEDIA_DEPRECATED=y CONFIG_VIDEO_CPIA2=y CONFIG_VIDEO_MEYE=y CONFIG_VIDEO_SAA7146=y CONFIG_VIDEO_SAA7146_VV=y CONFIG_DVB_AV7110_IR=y CONFIG_DVB_AV7110=y CONFIG_DVB_AV7110_OSD=y CONFIG_DVB_BUDGET_PATCH=y CONFIG_DVB_SP8870=y CONFIG_VIDEO_HEXIUM_GEMINI=y CONFIG_VIDEO_HEXIUM_ORION=y CONFIG_VIDEO_MXB=y CONFIG_DVB_BUDGET_CORE=y CONFIG_DVB_BUDGET=y CONFIG_DVB_BUDGET_CI=y CONFIG_DVB_BUDGET_AV=y CONFIG_VIDEO_STKWEBCAM=y CONFIG_VIDEO_TM6000=y CONFIG_VIDEO_TM6000_ALSA=y CONFIG_VIDEO_TM6000_DVB=y CONFIG_USB_ZR364XX=y CONFIG_STAGING_BOARD=y CONFIG_LTE_GDM724X=m CONFIG_FB_TFT=y CONFIG_FB_TFT_AGM1264K_FL=y CONFIG_FB_TFT_BD663474=y CONFIG_FB_TFT_HX8340BN=y CONFIG_FB_TFT_HX8347D=y CONFIG_FB_TFT_HX8353D=y CONFIG_FB_TFT_HX8357D=y CONFIG_FB_TFT_ILI9163=y CONFIG_FB_TFT_ILI9320=y CONFIG_FB_TFT_ILI9325=y CONFIG_FB_TFT_ILI9340=y CONFIG_FB_TFT_ILI9341=y CONFIG_FB_TFT_ILI9481=y CONFIG_FB_TFT_ILI9486=y CONFIG_FB_TFT_PCD8544=y CONFIG_FB_TFT_RA8875=y CONFIG_FB_TFT_S6D02A1=y CONFIG_FB_TFT_S6D1121=y CONFIG_FB_TFT_SEPS525=y CONFIG_FB_TFT_SH1106=y CONFIG_FB_TFT_SSD1289=y CONFIG_FB_TFT_SSD1305=y CONFIG_FB_TFT_SSD1306=y CONFIG_FB_TFT_SSD1331=y CONFIG_FB_TFT_SSD1351=y CONFIG_FB_TFT_ST7735R=y CONFIG_FB_TFT_ST7789V=y CONFIG_FB_TFT_TINYLCD=y CONFIG_FB_TFT_TLS8204=y CONFIG_FB_TFT_UC1611=y CONFIG_FB_TFT_UC1701=y CONFIG_FB_TFT_UPD161704=y CONFIG_MOST_COMPONENTS=y CONFIG_MOST_NET=y CONFIG_MOST_VIDEO=y CONFIG_MOST_DIM2=y CONFIG_MOST_I2C=y CONFIG_KS7010=y CONFIG_GREYBUS_AUDIO=y CONFIG_GREYBUS_AUDIO_APB_CODEC=y CONFIG_GREYBUS_BOOTROM=y CONFIG_GREYBUS_FIRMWARE=y CONFIG_GREYBUS_HID=y CONFIG_GREYBUS_LIGHT=y CONFIG_GREYBUS_LOG=y CONFIG_GREYBUS_LOOPBACK=y CONFIG_GREYBUS_POWER=y CONFIG_GREYBUS_RAW=y CONFIG_GREYBUS_VIBRATOR=y CONFIG_GREYBUS_BRIDGED_PHY=y CONFIG_GREYBUS_GPIO=y CONFIG_GREYBUS_I2C=y CONFIG_GREYBUS_PWM=y CONFIG_GREYBUS_SDIO=y CONFIG_GREYBUS_SPI=y CONFIG_GREYBUS_UART=y CONFIG_GREYBUS_USB=y CONFIG_PI433=y CONFIG_XIL_AXIS_FIFO=y CONFIG_FIELDBUS_DEV=y CONFIG_HMS_ANYBUSS_BUS=y CONFIG_ARCX_ANYBUS_CONTROLLER=y CONFIG_HMS_PROFINET=y CONFIG_QLGE=y CONFIG_VME_BUS=y # # VME Bridge Drivers # CONFIG_VME_TSI148=y CONFIG_VME_FAKE=y # # VME Device Drivers # CONFIG_VME_USER=y CONFIG_GOLDFISH_PIPE=y CONFIG_CHROME_PLATFORMS=y CONFIG_CHROMEOS_ACPI=y CONFIG_CHROMEOS_LAPTOP=y CONFIG_CHROMEOS_PSTORE=y CONFIG_CHROMEOS_TBMC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_RPMSG=y CONFIG_CROS_EC_SPI=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_PROTO=y CONFIG_CROS_KBD_LED_BACKLIGHT=y CONFIG_CROS_EC_CHARDEV=y CONFIG_CROS_EC_LIGHTBAR=y CONFIG_CROS_EC_VBC=y CONFIG_CROS_EC_DEBUGFS=y CONFIG_CROS_EC_SENSORHUB=y CONFIG_CROS_EC_SYSFS=y CONFIG_CROS_EC_TYPEC=y CONFIG_CROS_USBPD_LOGGER=y CONFIG_CROS_USBPD_NOTIFY=y CONFIG_CHROMEOS_PRIVACY_SCREEN=y CONFIG_CROS_TYPEC_SWITCH=y CONFIG_WILCO_EC=y CONFIG_WILCO_EC_DEBUGFS=y CONFIG_WILCO_EC_EVENTS=y CONFIG_WILCO_EC_TELEMETRY=y CONFIG_CROS_KUNIT=y CONFIG_MELLANOX_PLATFORM=y CONFIG_MLXREG_HOTPLUG=y CONFIG_MLXREG_IO=y CONFIG_MLXREG_LC=y CONFIG_NVSW_SN2201=y CONFIG_OLPC_EC=y CONFIG_SURFACE_PLATFORMS=y CONFIG_SURFACE3_WMI=y CONFIG_SURFACE_3_POWER_OPREGION=y CONFIG_SURFACE_ACPI_NOTIFY=y CONFIG_SURFACE_AGGREGATOR_CDEV=y CONFIG_SURFACE_AGGREGATOR_HUB=y CONFIG_SURFACE_AGGREGATOR_REGISTRY=y CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=y CONFIG_SURFACE_DTX=y CONFIG_SURFACE_GPE=y CONFIG_SURFACE_HOTPLUG=y CONFIG_SURFACE_PLATFORM_PROFILE=y CONFIG_SURFACE_PRO3_BUTTON=y CONFIG_SURFACE_AGGREGATOR=y CONFIG_SURFACE_AGGREGATOR_BUS=y CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION=y CONFIG_X86_PLATFORM_DEVICES=y CONFIG_ACPI_WMI=y CONFIG_WMI_BMOF=y CONFIG_HUAWEI_WMI=y CONFIG_MXM_WMI=y CONFIG_PEAQ_WMI=y CONFIG_NVIDIA_WMI_EC_BACKLIGHT=y CONFIG_XIAOMI_WMI=y CONFIG_GIGABYTE_WMI=y CONFIG_YOGABOOK_WMI=y CONFIG_ACERHDF=y CONFIG_ACER_WIRELESS=y CONFIG_ACER_WMI=y CONFIG_AMD_PMF=y CONFIG_AMD_PMC=y CONFIG_ADV_SWBUTTON=y CONFIG_APPLE_GMUX=y CONFIG_ASUS_LAPTOP=y CONFIG_ASUS_WIRELESS=y CONFIG_ASUS_WMI=y CONFIG_ASUS_NB_WMI=y CONFIG_ASUS_TF103C_DOCK=y CONFIG_MERAKI_MX100=y CONFIG_EEEPC_LAPTOP=y CONFIG_EEEPC_WMI=y CONFIG_X86_PLATFORM_DRIVERS_DELL=y CONFIG_ALIENWARE_WMI=y CONFIG_DCDBAS=y CONFIG_DELL_LAPTOP=y CONFIG_DELL_RBU=y CONFIG_DELL_RBTN=y CONFIG_DELL_SMBIOS=y CONFIG_DELL_SMBIOS_WMI=y CONFIG_DELL_SMBIOS_SMM=y CONFIG_DELL_SMO8800=y CONFIG_DELL_WMI=y CONFIG_DELL_WMI_PRIVACY=y CONFIG_DELL_WMI_AIO=y CONFIG_DELL_WMI_DESCRIPTOR=y CONFIG_DELL_WMI_LED=y CONFIG_DELL_WMI_SYSMAN=y CONFIG_AMILO_RFKILL=y CONFIG_FUJITSU_LAPTOP=y CONFIG_FUJITSU_TABLET=y CONFIG_GPD_POCKET_FAN=y CONFIG_HP_ACCEL=y CONFIG_WIRELESS_HOTKEY=y CONFIG_HP_WMI=y CONFIG_TC1100_WMI=y CONFIG_IBM_RTL=y CONFIG_IDEAPAD_LAPTOP=y CONFIG_SENSORS_HDAPS=y CONFIG_THINKPAD_ACPI=y CONFIG_THINKPAD_ACPI_ALSA_SUPPORT=y CONFIG_THINKPAD_ACPI_DEBUGFACILITIES=y CONFIG_THINKPAD_ACPI_DEBUG=y CONFIG_THINKPAD_ACPI_UNSAFE_LEDS=y CONFIG_THINKPAD_ACPI_VIDEO=y CONFIG_THINKPAD_ACPI_HOTKEY_POLL=y CONFIG_THINKPAD_LMI=y CONFIG_INTEL_ATOMISP2_PDX86=y CONFIG_INTEL_ATOMISP2_LED=y CONFIG_INTEL_SAR_INT1092=y CONFIG_INTEL_SKL_INT3472=y CONFIG_INTEL_PMC_CORE=y CONFIG_INTEL_PMT_CLASS=y CONFIG_INTEL_PMT_TELEMETRY=y CONFIG_INTEL_PMT_CRASHLOG=y CONFIG_INTEL_WMI=y CONFIG_INTEL_WMI_SBL_FW_UPDATE=y CONFIG_INTEL_WMI_THUNDERBOLT=y CONFIG_INTEL_HID_EVENT=y CONFIG_INTEL_VBTN=y CONFIG_INTEL_INT0002_VGPIO=y CONFIG_INTEL_OAKTRAIL=y CONFIG_INTEL_BXTWC_PMIC_TMU=y CONFIG_INTEL_CHTDC_TI_PWRBTN=y CONFIG_INTEL_CHTWC_INT33FE=y CONFIG_INTEL_MRFLD_PWRBTN=y CONFIG_INTEL_PUNIT_IPC=y CONFIG_INTEL_RST=y CONFIG_INTEL_SMARTCONNECT=y CONFIG_INTEL_VSEC=y CONFIG_MSI_LAPTOP=y CONFIG_MSI_WMI=y CONFIG_XO15_EBOOK=y CONFIG_XO1_RFKILL=y CONFIG_PCENGINES_APU2=y CONFIG_BARCO_P50_GPIO=y CONFIG_SAMSUNG_LAPTOP=y CONFIG_SAMSUNG_Q10=y CONFIG_ACPI_TOSHIBA=y CONFIG_TOSHIBA_BT_RFKILL=y CONFIG_TOSHIBA_HAPS=y CONFIG_TOSHIBA_WMI=y CONFIG_ACPI_CMPC=y CONFIG_COMPAL_LAPTOP=y CONFIG_LG_LAPTOP=y CONFIG_PANASONIC_LAPTOP=y CONFIG_SONY_LAPTOP=y CONFIG_SONYPI_COMPAT=y CONFIG_SYSTEM76_ACPI=y CONFIG_TOPSTAR_LAPTOP=y CONFIG_SERIAL_MULTI_INSTANTIATE=y CONFIG_MLX_PLATFORM=y CONFIG_TOUCHSCREEN_DMI=y CONFIG_X86_ANDROID_TABLETS=y CONFIG_FW_ATTR_CLASS=y CONFIG_INTEL_IMR=y CONFIG_INTEL_IPS=y CONFIG_INTEL_SCU_IPC=y CONFIG_INTEL_SCU=y CONFIG_INTEL_SCU_PCI=y CONFIG_INTEL_SCU_PLATFORM=y CONFIG_INTEL_SCU_WDT=y CONFIG_INTEL_SCU_IPC_UTIL=y CONFIG_SIEMENS_SIMATIC_IPC=y CONFIG_WINMATE_FM07_KEYS=y CONFIG_P2SB=y CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_WM831X=y CONFIG_LMK04832=y CONFIG_COMMON_CLK_MAX77686=y CONFIG_COMMON_CLK_MAX9485=y CONFIG_COMMON_CLK_RK808=y CONFIG_COMMON_CLK_SI5341=y CONFIG_COMMON_CLK_SI5351=y CONFIG_COMMON_CLK_SI514=y CONFIG_COMMON_CLK_SI544=y CONFIG_COMMON_CLK_SI570=y CONFIG_COMMON_CLK_CDCE706=y CONFIG_COMMON_CLK_TPS68470=y CONFIG_COMMON_CLK_CDCE925=y CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_S2MPS11=y CONFIG_CLK_TWL6040=y CONFIG_COMMON_CLK_AXI_CLKGEN=y CONFIG_COMMON_CLK_LOCHNAGAR=y CONFIG_COMMON_CLK_PALMAS=y CONFIG_COMMON_CLK_PWM=y CONFIG_COMMON_CLK_RS9_PCIE=y CONFIG_COMMON_CLK_VC5=y CONFIG_COMMON_CLK_VC7=y CONFIG_COMMON_CLK_BD718XX=y CONFIG_COMMON_CLK_FIXED_MMIO=y CONFIG_CLK_LGM_CGU=y CONFIG_XILINX_VCU=y CONFIG_COMMON_CLK_XLNX_CLKWZRD=y CONFIG_CLK_KUNIT_TEST=y CONFIG_CLK_GATE_KUNIT_TEST=y CONFIG_HWSPINLOCK=y # # Clock Source drivers # CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y CONFIG_CLKSRC_I8253=y CONFIG_CLKEVT_I8253=y CONFIG_I8253_LOCK=y CONFIG_CLKBLD_I8253=y CONFIG_DW_APB_TIMER=y CONFIG_MICROCHIP_PIT64B=y # end of Clock Source drivers CONFIG_MAILBOX=y CONFIG_PLATFORM_MHU=y CONFIG_PCC=y CONFIG_ALTERA_MBOX=y CONFIG_MAILBOX_TEST=y CONFIG_IOMMU_IOVA=y CONFIG_IOASID=y CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y # # Generic IOMMU Pagetable Support # # end of Generic IOMMU Pagetable Support CONFIG_IOMMU_DEBUGFS=y # CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set CONFIG_IOMMU_DEFAULT_DMA_LAZY=y # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_IOMMU_DMA=y CONFIG_DMAR_TABLE=y CONFIG_DMAR_PERF=y CONFIG_DMAR_DEBUG=y CONFIG_INTEL_IOMMU=y CONFIG_INTEL_IOMMU_DEBUGFS=y CONFIG_INTEL_IOMMU_DEFAULT_ON=y CONFIG_INTEL_IOMMU_FLOPPY_WA=y CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON=y CONFIG_HYPERV_IOMMU=y CONFIG_VIRTIO_IOMMU=y # # Remoteproc drivers # CONFIG_REMOTEPROC=y CONFIG_REMOTEPROC_CDEV=y # end of Remoteproc drivers # # Rpmsg drivers # CONFIG_RPMSG=y CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_CTRL=y CONFIG_RPMSG_NS=y CONFIG_RPMSG_QCOM_GLINK=y CONFIG_RPMSG_QCOM_GLINK_RPM=y CONFIG_RPMSG_VIRTIO=y # end of Rpmsg drivers CONFIG_SOUNDWIRE=y # # SoundWire Devices # CONFIG_SOUNDWIRE_CADENCE=y CONFIG_SOUNDWIRE_INTEL=y CONFIG_SOUNDWIRE_QCOM=y CONFIG_SOUNDWIRE_GENERIC_ALLOCATION=y # # SOC (System On Chip) specific Drivers # # # Amlogic SoC drivers # # end of Amlogic SoC drivers # # Broadcom SoC drivers # # end of Broadcom SoC drivers # # NXP/Freescale QorIQ SoC drivers # # end of NXP/Freescale QorIQ SoC drivers # # fujitsu SoC drivers # # end of fujitsu SoC drivers # # i.MX SoC drivers # # end of i.MX SoC drivers # # Enable LiteX SoC Builder specific drivers # CONFIG_LITEX=y CONFIG_LITEX_SOC_CONTROLLER=y # end of Enable LiteX SoC Builder specific drivers # # Qualcomm SoC drivers # CONFIG_QCOM_QMI_HELPERS=y # end of Qualcomm SoC drivers CONFIG_SOC_TI=y # # Xilinx SoC drivers # # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers CONFIG_PM_DEVFREQ=y # # DEVFREQ Governors # CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_DEVFREQ_GOV_PASSIVE=y # # DEVFREQ Drivers # CONFIG_PM_DEVFREQ_EVENT=y CONFIG_EXTCON=y # # Extcon Device Drivers # CONFIG_EXTCON_ADC_JACK=y CONFIG_EXTCON_AXP288=y CONFIG_EXTCON_FSA9480=y CONFIG_EXTCON_GPIO=y CONFIG_EXTCON_INTEL_INT3496=y CONFIG_EXTCON_INTEL_CHT_WC=y CONFIG_EXTCON_INTEL_MRFLD=y CONFIG_EXTCON_MAX14577=y CONFIG_EXTCON_MAX3355=y CONFIG_EXTCON_MAX77693=y CONFIG_EXTCON_MAX77843=y CONFIG_EXTCON_MAX8997=y CONFIG_EXTCON_PALMAS=y CONFIG_EXTCON_PTN5150=y CONFIG_EXTCON_RT8973A=y CONFIG_EXTCON_SM5502=y CONFIG_EXTCON_USB_GPIO=y CONFIG_EXTCON_USBC_CROS_EC=y CONFIG_EXTCON_USBC_TUSB320=y CONFIG_MEMORY=y CONFIG_FPGA_DFL_EMIF=y CONFIG_IIO=y CONFIG_IIO_BUFFER=y CONFIG_IIO_BUFFER_CB=y CONFIG_IIO_BUFFER_DMA=y CONFIG_IIO_BUFFER_DMAENGINE=y CONFIG_IIO_BUFFER_HW_CONSUMER=y CONFIG_IIO_KFIFO_BUF=y CONFIG_IIO_TRIGGERED_BUFFER=y CONFIG_IIO_CONFIGFS=y CONFIG_IIO_TRIGGER=y CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 CONFIG_IIO_SW_DEVICE=y CONFIG_IIO_SW_TRIGGER=y CONFIG_IIO_TRIGGERED_EVENT=y # # Accelerometers # CONFIG_ADIS16201=y CONFIG_ADIS16209=y CONFIG_ADXL313=y CONFIG_ADXL313_I2C=y CONFIG_ADXL313_SPI=y CONFIG_ADXL355=y CONFIG_ADXL355_I2C=y CONFIG_ADXL355_SPI=y CONFIG_ADXL367=y CONFIG_ADXL367_SPI=y CONFIG_ADXL367_I2C=y CONFIG_ADXL372=y CONFIG_ADXL372_SPI=y CONFIG_ADXL372_I2C=y CONFIG_BMA220=y CONFIG_BMA400=y CONFIG_BMA400_I2C=y CONFIG_BMA400_SPI=y CONFIG_BMC150_ACCEL=y CONFIG_BMC150_ACCEL_I2C=y CONFIG_BMC150_ACCEL_SPI=y CONFIG_BMI088_ACCEL=y CONFIG_BMI088_ACCEL_SPI=y CONFIG_DA280=y CONFIG_DA311=y CONFIG_DMARD06=y CONFIG_DMARD09=y CONFIG_DMARD10=y CONFIG_FXLS8962AF=y CONFIG_FXLS8962AF_I2C=y CONFIG_FXLS8962AF_SPI=y CONFIG_HID_SENSOR_ACCEL_3D=y CONFIG_IIO_CROS_EC_ACCEL_LEGACY=y CONFIG_KXSD9=y CONFIG_KXSD9_SPI=y CONFIG_KXSD9_I2C=y CONFIG_KXCJK1013=y CONFIG_MC3230=y CONFIG_MMA7455=y CONFIG_MMA7455_I2C=y CONFIG_MMA7455_SPI=y CONFIG_MMA7660=y CONFIG_MMA8452=y CONFIG_MMA9551_CORE=y CONFIG_MMA9551=y CONFIG_MMA9553=y CONFIG_MSA311=y CONFIG_MXC4005=y CONFIG_MXC6255=y CONFIG_SCA3000=y CONFIG_SCA3300=y CONFIG_STK8312=y CONFIG_STK8BA50=y # end of Accelerometers # # Analog to digital converters # CONFIG_AD_SIGMA_DELTA=y CONFIG_AD7091R5=y CONFIG_AD7124=y CONFIG_AD7192=y CONFIG_AD7266=y CONFIG_AD7280=y CONFIG_AD7291=y CONFIG_AD7292=y CONFIG_AD7298=y CONFIG_AD7476=y CONFIG_AD7606=y CONFIG_AD7606_IFACE_PARALLEL=y CONFIG_AD7606_IFACE_SPI=y CONFIG_AD7766=y CONFIG_AD7768_1=y CONFIG_AD7780=y CONFIG_AD7791=y CONFIG_AD7793=y CONFIG_AD7887=y CONFIG_AD7923=y CONFIG_AD7949=y CONFIG_AD799X=y CONFIG_AD9467=y CONFIG_ADI_AXI_ADC=y CONFIG_AXP20X_ADC=y CONFIG_AXP288_ADC=y CONFIG_CC10001_ADC=y CONFIG_CPCAP_ADC=y CONFIG_DA9150_GPADC=y CONFIG_DLN2_ADC=y CONFIG_ENVELOPE_DETECTOR=y CONFIG_HI8435=y CONFIG_HX711=y CONFIG_INTEL_MRFLD_ADC=y CONFIG_LP8788_ADC=y CONFIG_LTC2471=y CONFIG_LTC2485=y CONFIG_LTC2496=y CONFIG_LTC2497=y CONFIG_MAX1027=y CONFIG_MAX11100=y CONFIG_MAX1118=y CONFIG_MAX11205=y CONFIG_MAX1241=y CONFIG_MAX1363=y CONFIG_MAX9611=y CONFIG_MCP320X=y CONFIG_MCP3422=y CONFIG_MCP3911=y CONFIG_MEDIATEK_MT6360_ADC=y CONFIG_MEN_Z188_ADC=y CONFIG_MP2629_ADC=y CONFIG_NAU7802=y CONFIG_PALMAS_GPADC=y CONFIG_QCOM_VADC_COMMON=y CONFIG_QCOM_SPMI_IADC=y CONFIG_QCOM_SPMI_VADC=y CONFIG_QCOM_SPMI_ADC5=y CONFIG_RN5T618_ADC=y CONFIG_RICHTEK_RTQ6056=y CONFIG_SD_ADC_MODULATOR=y CONFIG_STMPE_ADC=y CONFIG_TI_ADC081C=y CONFIG_TI_ADC0832=y CONFIG_TI_ADC084S021=y CONFIG_TI_ADC12138=y CONFIG_TI_ADC108S102=y CONFIG_TI_ADC128S052=y CONFIG_TI_ADC161S626=y CONFIG_TI_ADS1015=y CONFIG_TI_ADS7950=y CONFIG_TI_ADS8344=y CONFIG_TI_ADS8688=y CONFIG_TI_ADS124S08=y CONFIG_TI_ADS131E08=y CONFIG_TI_AM335X_ADC=y CONFIG_TI_TLC4541=y CONFIG_TI_TSC2046=y CONFIG_TWL4030_MADC=y CONFIG_TWL6030_GPADC=y CONFIG_VF610_ADC=y CONFIG_VIPERBOARD_ADC=y CONFIG_XILINX_XADC=y # end of Analog to digital converters # # Analog to digital and digital to analog converters # CONFIG_AD74413R=y CONFIG_STX104=y # end of Analog to digital and digital to analog converters # # Analog Front Ends # CONFIG_IIO_RESCALE=y # end of Analog Front Ends # # Amplifiers # CONFIG_AD8366=y CONFIG_ADA4250=y CONFIG_HMC425=y # end of Amplifiers # # Capacitance to digital converters # CONFIG_AD7150=y CONFIG_AD7746=y # end of Capacitance to digital converters # # Chemical Sensors # CONFIG_ATLAS_PH_SENSOR=y CONFIG_ATLAS_EZO_SENSOR=y CONFIG_BME680=y CONFIG_BME680_I2C=y CONFIG_BME680_SPI=y CONFIG_CCS811=y CONFIG_IAQCORE=y CONFIG_PMS7003=y CONFIG_SCD30_CORE=y CONFIG_SCD30_I2C=y CONFIG_SCD30_SERIAL=y CONFIG_SCD4X=y CONFIG_SENSIRION_SGP30=y CONFIG_SENSIRION_SGP40=y CONFIG_SPS30=y CONFIG_SPS30_I2C=y CONFIG_SPS30_SERIAL=y CONFIG_SENSEAIR_SUNRISE_CO2=y CONFIG_VZ89X=y # end of Chemical Sensors CONFIG_IIO_CROS_EC_SENSORS_CORE=y CONFIG_IIO_CROS_EC_SENSORS=y CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=y # # Hid Sensor IIO Common # CONFIG_HID_SENSOR_IIO_COMMON=y CONFIG_HID_SENSOR_IIO_TRIGGER=y # end of Hid Sensor IIO Common CONFIG_IIO_MS_SENSORS_I2C=y # # IIO SCMI Sensors # # end of IIO SCMI Sensors # # SSP Sensor Common # CONFIG_IIO_SSP_SENSORS_COMMONS=y CONFIG_IIO_SSP_SENSORHUB=y # end of SSP Sensor Common CONFIG_IIO_ST_SENSORS_I2C=y CONFIG_IIO_ST_SENSORS_SPI=y CONFIG_IIO_ST_SENSORS_CORE=y # # Digital to analog converters # CONFIG_AD3552R=y CONFIG_AD5064=y CONFIG_AD5360=y CONFIG_AD5380=y CONFIG_AD5421=y CONFIG_AD5446=y CONFIG_AD5449=y CONFIG_AD5592R_BASE=y CONFIG_AD5592R=y CONFIG_AD5593R=y CONFIG_AD5504=y CONFIG_AD5624R_SPI=y CONFIG_LTC2688=y CONFIG_AD5686=y CONFIG_AD5686_SPI=y CONFIG_AD5696_I2C=y CONFIG_AD5755=y CONFIG_AD5758=y CONFIG_AD5761=y CONFIG_AD5764=y CONFIG_AD5766=y CONFIG_AD5770R=y CONFIG_AD5791=y CONFIG_AD7293=y CONFIG_AD7303=y CONFIG_AD8801=y CONFIG_CIO_DAC=y CONFIG_DPOT_DAC=y CONFIG_DS4424=y CONFIG_LTC1660=y CONFIG_LTC2632=y CONFIG_M62332=y CONFIG_MAX517=y CONFIG_MAX5821=y CONFIG_MCP4725=y CONFIG_MCP4922=y CONFIG_TI_DAC082S085=y CONFIG_TI_DAC5571=y CONFIG_TI_DAC7311=y CONFIG_TI_DAC7612=y CONFIG_VF610_DAC=y # end of Digital to analog converters # # IIO dummy driver # CONFIG_IIO_DUMMY_EVGEN=y CONFIG_IIO_SIMPLE_DUMMY=y CONFIG_IIO_SIMPLE_DUMMY_EVENTS=y CONFIG_IIO_SIMPLE_DUMMY_BUFFER=y # end of IIO dummy driver # # Filters # # end of Filters # # Frequency Synthesizers DDS/PLL # # # Clock Generator/Distribution # CONFIG_AD9523=y # end of Clock Generator/Distribution # # Phase-Locked Loop (PLL) frequency synthesizers # CONFIG_ADF4350=y CONFIG_ADF4371=y CONFIG_ADMV1013=y CONFIG_ADMV4420=y CONFIG_ADRF6780=y # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL # # Digital gyroscope sensors # CONFIG_ADIS16080=y CONFIG_ADIS16130=y CONFIG_ADIS16136=y CONFIG_ADIS16260=y CONFIG_ADXRS290=y CONFIG_ADXRS450=y CONFIG_BMG160=y CONFIG_BMG160_I2C=y CONFIG_BMG160_SPI=y CONFIG_FXAS21002C=y CONFIG_FXAS21002C_I2C=y CONFIG_FXAS21002C_SPI=y CONFIG_HID_SENSOR_GYRO_3D=y CONFIG_MPU3050=y CONFIG_MPU3050_I2C=y CONFIG_IIO_ST_GYRO_3AXIS=y CONFIG_IIO_ST_GYRO_I2C_3AXIS=y CONFIG_IIO_ST_GYRO_SPI_3AXIS=y CONFIG_ITG3200=y # end of Digital gyroscope sensors # # Health Sensors # # # Heart Rate Monitors # CONFIG_AFE4403=y CONFIG_AFE4404=y CONFIG_MAX30100=y CONFIG_MAX30102=y # end of Heart Rate Monitors # end of Health Sensors # # Humidity sensors # CONFIG_AM2315=y CONFIG_DHT11=y CONFIG_HDC100X=y CONFIG_HDC2010=y CONFIG_HID_SENSOR_HUMIDITY=y CONFIG_HTS221=y CONFIG_HTS221_I2C=y CONFIG_HTS221_SPI=y CONFIG_HTU21=y CONFIG_SI7005=y CONFIG_SI7020=y # end of Humidity sensors # # Inertial measurement units # CONFIG_ADIS16400=y CONFIG_ADIS16460=y CONFIG_ADIS16475=y CONFIG_ADIS16480=y CONFIG_BMI160=y CONFIG_BMI160_I2C=y CONFIG_BMI160_SPI=y CONFIG_BOSCH_BNO055=y CONFIG_BOSCH_BNO055_SERIAL=y CONFIG_BOSCH_BNO055_I2C=y CONFIG_FXOS8700=y CONFIG_FXOS8700_I2C=y CONFIG_FXOS8700_SPI=y CONFIG_KMX61=y CONFIG_INV_ICM42600=y CONFIG_INV_ICM42600_I2C=y CONFIG_INV_ICM42600_SPI=y CONFIG_INV_MPU6050_IIO=y CONFIG_INV_MPU6050_I2C=y CONFIG_INV_MPU6050_SPI=y CONFIG_IIO_ST_LSM6DSX=y CONFIG_IIO_ST_LSM6DSX_I2C=y CONFIG_IIO_ST_LSM6DSX_SPI=y CONFIG_IIO_ST_LSM6DSX_I3C=y # end of Inertial measurement units CONFIG_IIO_ADIS_LIB=y CONFIG_IIO_ADIS_LIB_BUFFER=y # # Light sensors # CONFIG_ACPI_ALS=y CONFIG_ADJD_S311=y CONFIG_ADUX1020=y CONFIG_AL3010=y CONFIG_AL3320A=y CONFIG_APDS9300=y CONFIG_APDS9960=y CONFIG_AS73211=y CONFIG_BH1750=y CONFIG_BH1780=y CONFIG_CM32181=y CONFIG_CM3232=y CONFIG_CM3323=y CONFIG_CM3605=y CONFIG_CM36651=y CONFIG_IIO_CROS_EC_LIGHT_PROX=y CONFIG_GP2AP002=y CONFIG_GP2AP020A00F=y CONFIG_IQS621_ALS=y CONFIG_SENSORS_ISL29018=y CONFIG_SENSORS_ISL29028=y CONFIG_ISL29125=y CONFIG_HID_SENSOR_ALS=y CONFIG_HID_SENSOR_PROX=y CONFIG_JSA1212=y CONFIG_RPR0521=y CONFIG_SENSORS_LM3533=y CONFIG_LTR501=y CONFIG_LTRF216A=y CONFIG_LV0104CS=y CONFIG_MAX44000=y CONFIG_MAX44009=y CONFIG_NOA1305=y CONFIG_OPT3001=y CONFIG_PA12203001=y CONFIG_SI1133=y CONFIG_SI1145=y CONFIG_STK3310=y CONFIG_ST_UVIS25=y CONFIG_ST_UVIS25_I2C=y CONFIG_ST_UVIS25_SPI=y CONFIG_TCS3414=y CONFIG_TCS3472=y CONFIG_SENSORS_TSL2563=y CONFIG_TSL2583=y CONFIG_TSL2591=y CONFIG_TSL2772=y CONFIG_TSL4531=y CONFIG_US5182D=y CONFIG_VCNL4000=y CONFIG_VCNL4035=y CONFIG_VEML6030=y CONFIG_VEML6070=y CONFIG_VL6180=y CONFIG_ZOPT2201=y # end of Light sensors # # Magnetometer sensors # CONFIG_AK8974=y CONFIG_AK8975=y CONFIG_AK09911=y CONFIG_BMC150_MAGN=y CONFIG_BMC150_MAGN_I2C=y CONFIG_BMC150_MAGN_SPI=y CONFIG_MAG3110=y CONFIG_HID_SENSOR_MAGNETOMETER_3D=y CONFIG_MMC35240=y CONFIG_IIO_ST_MAGN_3AXIS=y CONFIG_IIO_ST_MAGN_I2C_3AXIS=y CONFIG_IIO_ST_MAGN_SPI_3AXIS=y CONFIG_SENSORS_HMC5843=y CONFIG_SENSORS_HMC5843_I2C=y CONFIG_SENSORS_HMC5843_SPI=y CONFIG_SENSORS_RM3100=y CONFIG_SENSORS_RM3100_I2C=y CONFIG_SENSORS_RM3100_SPI=y CONFIG_YAMAHA_YAS530=y # end of Magnetometer sensors # # Multiplexers # CONFIG_IIO_MUX=y # end of Multiplexers # # Inclinometer sensors # CONFIG_HID_SENSOR_INCLINOMETER_3D=y CONFIG_HID_SENSOR_DEVICE_ROTATION=y # end of Inclinometer sensors CONFIG_IIO_RESCALE_KUNIT_TEST=y CONFIG_IIO_FORMAT_KUNIT_TEST=y # # Triggers - standalone # CONFIG_IIO_HRTIMER_TRIGGER=y CONFIG_IIO_INTERRUPT_TRIGGER=y CONFIG_IIO_TIGHTLOOP_TRIGGER=y CONFIG_IIO_SYSFS_TRIGGER=y # end of Triggers - standalone # # Linear and angular position sensors # CONFIG_IQS624_POS=y CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=y # end of Linear and angular position sensors # # Digital potentiometers # CONFIG_AD5110=y CONFIG_AD5272=y CONFIG_DS1803=y CONFIG_MAX5432=y CONFIG_MAX5481=y CONFIG_MAX5487=y CONFIG_MCP4018=y CONFIG_MCP4131=y CONFIG_MCP4531=y CONFIG_MCP41010=y CONFIG_TPL0102=y # end of Digital potentiometers # # Digital potentiostats # CONFIG_LMP91000=y # end of Digital potentiostats # # Pressure sensors # CONFIG_ABP060MG=y CONFIG_BMP280=y CONFIG_BMP280_I2C=y CONFIG_BMP280_SPI=y CONFIG_IIO_CROS_EC_BARO=y CONFIG_DLHL60D=y CONFIG_DPS310=y CONFIG_HID_SENSOR_PRESS=y CONFIG_HP03=y CONFIG_ICP10100=y CONFIG_MPL115=y CONFIG_MPL115_I2C=y CONFIG_MPL115_SPI=y CONFIG_MPL3115=y CONFIG_MS5611=y CONFIG_MS5611_I2C=y CONFIG_MS5611_SPI=y CONFIG_MS5637=y CONFIG_IIO_ST_PRESS=y CONFIG_IIO_ST_PRESS_I2C=y CONFIG_IIO_ST_PRESS_SPI=y CONFIG_T5403=y CONFIG_HP206C=y CONFIG_ZPA2326=y CONFIG_ZPA2326_I2C=y CONFIG_ZPA2326_SPI=y # end of Pressure sensors # # Lightning sensors # CONFIG_AS3935=y # end of Lightning sensors # # Proximity and distance sensors # CONFIG_CROS_EC_MKBP_PROXIMITY=y CONFIG_ISL29501=y CONFIG_LIDAR_LITE_V2=y CONFIG_MB1232=y CONFIG_PING=y CONFIG_RFD77402=y CONFIG_SRF04=y CONFIG_SX_COMMON=y CONFIG_SX9310=y CONFIG_SX9324=y CONFIG_SX9360=y CONFIG_SX9500=y CONFIG_SRF08=y CONFIG_VCNL3020=y CONFIG_VL53L0X_I2C=y # end of Proximity and distance sensors # # Resolver to digital converters # CONFIG_AD2S90=y CONFIG_AD2S1200=y # end of Resolver to digital converters # # Temperature sensors # CONFIG_IQS620AT_TEMP=y CONFIG_LTC2983=y CONFIG_MAXIM_THERMOCOUPLE=y CONFIG_HID_SENSOR_TEMP=y CONFIG_MLX90614=y CONFIG_MLX90632=y CONFIG_TMP006=y CONFIG_TMP007=y CONFIG_TMP117=y CONFIG_TSYS01=y CONFIG_TSYS02D=y CONFIG_MAX31856=y CONFIG_MAX31865=y # end of Temperature sensors CONFIG_NTB=y CONFIG_NTB_MSI=y CONFIG_NTB_IDT=y CONFIG_NTB_EPF=m CONFIG_NTB_SWITCHTEC=y CONFIG_NTB_PINGPONG=y CONFIG_NTB_TOOL=y CONFIG_NTB_PERF=y CONFIG_NTB_MSI_TEST=y CONFIG_NTB_TRANSPORT=y CONFIG_PWM=y CONFIG_PWM_SYSFS=y CONFIG_PWM_DEBUG=y CONFIG_PWM_ATMEL_HLCDC_PWM=y CONFIG_PWM_ATMEL_TCB=y CONFIG_PWM_CLK=y CONFIG_PWM_CRC=y CONFIG_PWM_CROS_EC=y CONFIG_PWM_DWC=y CONFIG_PWM_FSL_FTM=y CONFIG_PWM_INTEL_LGM=y CONFIG_PWM_IQS620A=y CONFIG_PWM_LP3943=y CONFIG_PWM_LPSS=y CONFIG_PWM_LPSS_PCI=y CONFIG_PWM_LPSS_PLATFORM=y CONFIG_PWM_NTXEC=y CONFIG_PWM_PCA9685=y CONFIG_PWM_STMPE=y CONFIG_PWM_TWL=y CONFIG_PWM_TWL_LED=y CONFIG_PWM_XILINX=y # # IRQ chip support # CONFIG_IRQCHIP=y CONFIG_AL_FIC=y CONFIG_CIRRUS_CS48L32_IRQ=y CONFIG_MADERA_IRQ=y CONFIG_XILINX_INTC=y # end of IRQ chip support CONFIG_IPACK_BUS=y CONFIG_BOARD_TPCI200=y CONFIG_SERIAL_IPOCTAL=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_INTEL_GW=y CONFIG_RESET_SIMPLE=y CONFIG_RESET_TI_SYSCON=y CONFIG_RESET_TI_TPS380X=y # # PHY Subsystem # CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PHY_MIPI_DPHY=y CONFIG_USB_LGM_PHY=y CONFIG_PHY_CAN_TRANSCEIVER=y # # PHY drivers for Broadcom platforms # CONFIG_BCM_KONA_USB2_PHY=y # end of PHY drivers for Broadcom platforms CONFIG_PHY_CADENCE_TORRENT=y CONFIG_PHY_CADENCE_DPHY=y CONFIG_PHY_CADENCE_DPHY_RX=y CONFIG_PHY_CADENCE_SIERRA=y CONFIG_PHY_CADENCE_SALVO=y CONFIG_PHY_PXA_28NM_HSIC=y CONFIG_PHY_PXA_28NM_USB2=y CONFIG_PHY_LAN966X_SERDES=y CONFIG_PHY_CPCAP_USB=y CONFIG_PHY_MAPPHONE_MDM6600=y CONFIG_PHY_OCELOT_SERDES=y CONFIG_PHY_QCOM_USB_HS=y CONFIG_PHY_QCOM_USB_HSIC=y CONFIG_PHY_SAMSUNG_USB2=y CONFIG_PHY_TUSB1210=y CONFIG_PHY_INTEL_LGM_COMBO=y CONFIG_PHY_INTEL_LGM_EMMC=y # end of PHY Subsystem CONFIG_POWERCAP=y CONFIG_INTEL_RAPL_CORE=y CONFIG_INTEL_RAPL=y CONFIG_IDLE_INJECT=y CONFIG_DTPM=y CONFIG_DTPM_CPU=y CONFIG_DTPM_DEVFREQ=y CONFIG_MCB=y CONFIG_MCB_PCI=y CONFIG_MCB_LPC=y # # Performance monitor support # # end of Performance monitor support CONFIG_RAS=y CONFIG_RAS_CEC=y CONFIG_RAS_CEC_DEBUG=y CONFIG_USB4=y CONFIG_USB4_DEBUGFS_WRITE=y CONFIG_USB4_DEBUGFS_MARGINING=y CONFIG_USB4_KUNIT_TEST=y CONFIG_USB4_DMA_TEST=y # # Android # CONFIG_ANDROID_BINDER_IPC=y CONFIG_ANDROID_BINDERFS=y CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder" CONFIG_ANDROID_BINDER_IPC_SELFTEST=y # end of Android CONFIG_DAX=y CONFIG_DEV_DAX=y CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y CONFIG_NVMEM_RAVE_SP_EEPROM=y CONFIG_NVMEM_RMEM=y CONFIG_NVMEM_SPMI_SDAM=y CONFIG_NVMEM_U_BOOT_ENV=y # # HW tracing support # CONFIG_STM=y CONFIG_STM_PROTO_BASIC=y CONFIG_STM_PROTO_SYS_T=y CONFIG_STM_DUMMY=y CONFIG_STM_SOURCE_CONSOLE=y CONFIG_STM_SOURCE_HEARTBEAT=y CONFIG_STM_SOURCE_FTRACE=y CONFIG_INTEL_TH=y CONFIG_INTEL_TH_PCI=y CONFIG_INTEL_TH_ACPI=y CONFIG_INTEL_TH_GTH=y CONFIG_INTEL_TH_STH=y CONFIG_INTEL_TH_MSU=y CONFIG_INTEL_TH_PTI=y CONFIG_INTEL_TH_DEBUG=y # end of HW tracing support CONFIG_FPGA=y CONFIG_ALTERA_PR_IP_CORE=y CONFIG_ALTERA_PR_IP_CORE_PLAT=y CONFIG_FPGA_MGR_ALTERA_PS_SPI=y CONFIG_FPGA_MGR_ALTERA_CVP=y CONFIG_FPGA_MGR_XILINX_SPI=y CONFIG_FPGA_MGR_ICE40_SPI=y CONFIG_FPGA_MGR_MACHXO2_SPI=y CONFIG_FPGA_BRIDGE=y CONFIG_ALTERA_FREEZE_BRIDGE=y CONFIG_XILINX_PR_DECOUPLER=y CONFIG_FPGA_REGION=y CONFIG_OF_FPGA_REGION=y CONFIG_FPGA_DFL=y CONFIG_FPGA_DFL_FME=y CONFIG_FPGA_DFL_FME_MGR=y CONFIG_FPGA_DFL_FME_BRIDGE=y CONFIG_FPGA_DFL_FME_REGION=y CONFIG_FPGA_DFL_AFU=y CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=y CONFIG_FPGA_DFL_PCI=y CONFIG_FPGA_M10_BMC_SEC_UPDATE=y CONFIG_FPGA_MGR_MICROCHIP_SPI=y CONFIG_FSI=y CONFIG_FSI_NEW_DEV_NODE=y CONFIG_FSI_MASTER_GPIO=y CONFIG_FSI_MASTER_HUB=y CONFIG_FSI_MASTER_ASPEED=y CONFIG_FSI_SCOM=y CONFIG_FSI_SBEFIFO=y CONFIG_FSI_OCC=y CONFIG_TEE=y CONFIG_MULTIPLEXER=y # # Multiplexer drivers # CONFIG_MUX_ADG792A=y CONFIG_MUX_ADGS1408=y CONFIG_MUX_GPIO=y CONFIG_MUX_MMIO=y # end of Multiplexer drivers CONFIG_PM_OPP=y CONFIG_SIOX=y CONFIG_SIOX_BUS_GPIO=y CONFIG_SLIMBUS=y CONFIG_SLIM_QCOM_CTRL=y CONFIG_INTERCONNECT=y CONFIG_COUNTER=y CONFIG_104_QUAD_8=y CONFIG_INTERRUPT_CNT=y CONFIG_FTM_QUADDEC=y CONFIG_MICROCHIP_TCB_CAPTURE=y CONFIG_INTEL_QEP=y CONFIG_MOST=y CONFIG_MOST_USB_HDM=y CONFIG_MOST_CDEV=y CONFIG_MOST_SND=y CONFIG_PECI=y CONFIG_PECI_CPU=y CONFIG_HTE=y # end of Device Drivers # # File systems # CONFIG_DCACHE_WORD_ACCESS=y CONFIG_VALIDATE_FS_PARSER=y CONFIG_FS_IOMAP=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y CONFIG_EXT4_DEBUG=y CONFIG_EXT4_KUNIT_TESTS=y CONFIG_JBD2=y CONFIG_JBD2_DEBUG=y CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=y CONFIG_REISERFS_CHECK=y CONFIG_REISERFS_PROC_INFO=y CONFIG_REISERFS_FS_XATTR=y CONFIG_REISERFS_FS_POSIX_ACL=y CONFIG_REISERFS_FS_SECURITY=y CONFIG_JFS_FS=y CONFIG_JFS_POSIX_ACL=y CONFIG_JFS_SECURITY=y CONFIG_JFS_DEBUG=y CONFIG_JFS_STATISTICS=y CONFIG_XFS_FS=y CONFIG_XFS_SUPPORT_V4=y CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y CONFIG_XFS_RT=y CONFIG_XFS_ONLINE_SCRUB=y CONFIG_XFS_ONLINE_REPAIR=y CONFIG_XFS_DEBUG=y CONFIG_XFS_ASSERT_FATAL=y CONFIG_GFS2_FS=y CONFIG_GFS2_FS_LOCKING_DLM=y CONFIG_OCFS2_FS=y CONFIG_OCFS2_FS_O2CB=y CONFIG_OCFS2_FS_USERSPACE_CLUSTER=y CONFIG_OCFS2_FS_STATS=y CONFIG_OCFS2_DEBUG_MASKLOG=y CONFIG_OCFS2_DEBUG_FS=y CONFIG_BTRFS_FS=y CONFIG_BTRFS_FS_POSIX_ACL=y CONFIG_BTRFS_FS_CHECK_INTEGRITY=y CONFIG_BTRFS_FS_RUN_SANITY_TESTS=y CONFIG_BTRFS_DEBUG=y CONFIG_BTRFS_ASSERT=y CONFIG_BTRFS_FS_REF_VERIFY=y CONFIG_NILFS2_FS=y CONFIG_F2FS_FS=y CONFIG_F2FS_STAT_FS=y CONFIG_F2FS_FS_XATTR=y CONFIG_F2FS_FS_POSIX_ACL=y CONFIG_F2FS_FS_SECURITY=y CONFIG_F2FS_CHECK_FS=y CONFIG_F2FS_FAULT_INJECTION=y CONFIG_F2FS_FS_COMPRESSION=y CONFIG_F2FS_FS_LZO=y CONFIG_F2FS_FS_LZORLE=y CONFIG_F2FS_FS_LZ4=y CONFIG_F2FS_FS_LZ4HC=y CONFIG_F2FS_FS_ZSTD=y CONFIG_F2FS_IOSTAT=y CONFIG_F2FS_UNFAIR_RWSEM=y CONFIG_ZONEFS_FS=y CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y CONFIG_EXPORTFS_BLOCK_OPS=y CONFIG_FILE_LOCKING=y CONFIG_FS_ENCRYPTION=y CONFIG_FS_ENCRYPTION_ALGS=y CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y CONFIG_FS_VERITY=y CONFIG_FS_VERITY_DEBUG=y CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y CONFIG_FANOTIFY=y CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_PRINT_QUOTA_WARNING=y CONFIG_QUOTA_DEBUG=y CONFIG_QUOTA_TREE=y CONFIG_QFMT_V1=y CONFIG_QFMT_V2=y CONFIG_QUOTACTL=y CONFIG_AUTOFS4_FS=y CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=y CONFIG_CUSE=y CONFIG_VIRTIO_FS=y CONFIG_OVERLAY_FS=y CONFIG_OVERLAY_FS_REDIRECT_DIR=y CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y CONFIG_OVERLAY_FS_INDEX=y CONFIG_OVERLAY_FS_METACOPY=y # # Caches # CONFIG_NETFS_SUPPORT=y CONFIG_NETFS_STATS=y CONFIG_FSCACHE=y CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE_DEBUG=y CONFIG_CACHEFILES=y CONFIG_CACHEFILES_DEBUG=y CONFIG_CACHEFILES_ERROR_INJECTION=y CONFIG_CACHEFILES_ONDEMAND=y # end of Caches # # CD-ROM/DVD Filesystems # CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=y # end of CD-ROM/DVD Filesystems # # DOS/FAT/EXFAT/NT Filesystems # CONFIG_FAT_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_FAT_DEFAULT_UTF8=y CONFIG_FAT_KUNIT_TEST=y CONFIG_EXFAT_FS=y CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" CONFIG_NTFS_FS=y CONFIG_NTFS_DEBUG=y CONFIG_NTFS_RW=y CONFIG_NTFS3_FS=y CONFIG_NTFS3_LZX_XPRESS=y CONFIG_NTFS3_FS_POSIX_ACL=y # end of DOS/FAT/EXFAT/NT Filesystems # # Pseudo filesystems # CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_VMCORE=y CONFIG_PROC_VMCORE_DEVICE_DUMP=y CONFIG_PROC_SYSCTL=y CONFIG_PROC_PAGE_MONITOR=y CONFIG_PROC_CHILDREN=y CONFIG_PROC_PID_ARCH_STATUS=y CONFIG_PROC_CPU_RESCTRL=y CONFIG_KERNFS=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y CONFIG_MEMFD_CREATE=y CONFIG_CONFIGFS_FS=y CONFIG_EFIVAR_FS=y # end of Pseudo filesystems CONFIG_MISC_FILESYSTEMS=y CONFIG_ORANGEFS_FS=y CONFIG_ADFS_FS=y CONFIG_ADFS_FS_RW=y CONFIG_AFFS_FS=y CONFIG_ECRYPT_FS=y CONFIG_ECRYPT_FS_MESSAGING=y CONFIG_HFS_FS=y CONFIG_HFSPLUS_FS=y CONFIG_BEFS_FS=y CONFIG_BEFS_DEBUG=y CONFIG_BFS_FS=y CONFIG_EFS_FS=y CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y CONFIG_JFFS2_FS_WBUF_VERIFY=y CONFIG_JFFS2_SUMMARY=y CONFIG_JFFS2_FS_XATTR=y CONFIG_JFFS2_FS_POSIX_ACL=y CONFIG_JFFS2_FS_SECURITY=y CONFIG_JFFS2_COMPRESSION_OPTIONS=y CONFIG_JFFS2_ZLIB=y CONFIG_JFFS2_LZO=y CONFIG_JFFS2_RTIME=y CONFIG_JFFS2_RUBIN=y # CONFIG_JFFS2_CMODE_NONE is not set CONFIG_JFFS2_CMODE_PRIORITY=y # CONFIG_JFFS2_CMODE_SIZE is not set # CONFIG_JFFS2_CMODE_FAVOURLZO is not set CONFIG_UBIFS_FS=y CONFIG_UBIFS_FS_ADVANCED_COMPR=y CONFIG_UBIFS_FS_LZO=y CONFIG_UBIFS_FS_ZLIB=y CONFIG_UBIFS_FS_ZSTD=y CONFIG_UBIFS_ATIME_SUPPORT=y CONFIG_UBIFS_FS_XATTR=y CONFIG_UBIFS_FS_SECURITY=y CONFIG_UBIFS_FS_AUTHENTICATION=y CONFIG_CRAMFS=y CONFIG_CRAMFS_BLOCKDEV=y CONFIG_CRAMFS_MTD=y CONFIG_SQUASHFS=y CONFIG_SQUASHFS_FILE_CACHE=y # CONFIG_SQUASHFS_FILE_DIRECT is not set CONFIG_SQUASHFS_DECOMP_SINGLE=y # CONFIG_SQUASHFS_DECOMP_MULTI is not set # CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set CONFIG_SQUASHFS_XATTR=y CONFIG_SQUASHFS_ZLIB=y CONFIG_SQUASHFS_LZ4=y CONFIG_SQUASHFS_LZO=y CONFIG_SQUASHFS_XZ=y CONFIG_SQUASHFS_ZSTD=y CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y CONFIG_SQUASHFS_EMBEDDED=y CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 CONFIG_VXFS_FS=y CONFIG_MINIX_FS=y CONFIG_OMFS_FS=y CONFIG_HPFS_FS=y CONFIG_QNX4FS_FS=y CONFIG_QNX6FS_FS=y CONFIG_QNX6FS_DEBUG=y CONFIG_ROMFS_FS=y CONFIG_ROMFS_BACKED_BY_BLOCK=y # CONFIG_ROMFS_BACKED_BY_MTD is not set # CONFIG_ROMFS_BACKED_BY_BOTH is not set CONFIG_ROMFS_ON_BLOCK=y CONFIG_PSTORE=y CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 CONFIG_PSTORE_DEFLATE_COMPRESS=y CONFIG_PSTORE_LZO_COMPRESS=y CONFIG_PSTORE_LZ4_COMPRESS=y CONFIG_PSTORE_LZ4HC_COMPRESS=y CONFIG_PSTORE_842_COMPRESS=y CONFIG_PSTORE_ZSTD_COMPRESS=y CONFIG_PSTORE_COMPRESS=y CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y # CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set # CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set # CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set # CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set # CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT is not set CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" CONFIG_PSTORE_CONSOLE=y CONFIG_PSTORE_PMSG=y CONFIG_PSTORE_FTRACE=y CONFIG_PSTORE_RAM=y CONFIG_PSTORE_ZONE=y CONFIG_PSTORE_BLK=y CONFIG_PSTORE_BLK_BLKDEV="" CONFIG_PSTORE_BLK_KMSG_SIZE=64 CONFIG_PSTORE_BLK_MAX_REASON=2 CONFIG_PSTORE_BLK_PMSG_SIZE=64 CONFIG_PSTORE_BLK_CONSOLE_SIZE=64 CONFIG_PSTORE_BLK_FTRACE_SIZE=64 CONFIG_SYSV_FS=y CONFIG_UFS_FS=y CONFIG_UFS_FS_WRITE=y CONFIG_UFS_DEBUG=y CONFIG_EROFS_FS=y CONFIG_EROFS_FS_DEBUG=y CONFIG_EROFS_FS_XATTR=y CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_ZIP=y CONFIG_EROFS_FS_ZIP_LZMA=y CONFIG_EROFS_FS_ONDEMAND=y CONFIG_VBOXSF_FS=y CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V2=y CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_NFS_SWAP=y CONFIG_NFS_V4_1=y CONFIG_NFS_V4_2=y CONFIG_PNFS_FILE_LAYOUT=y CONFIG_PNFS_BLOCK=y CONFIG_PNFS_FLEXFILE_LAYOUT=y CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" CONFIG_NFS_V4_1_MIGRATION=y CONFIG_NFS_V4_SECURITY_LABEL=y CONFIG_ROOT_NFS=y CONFIG_NFS_FSCACHE=y CONFIG_NFS_USE_LEGACY_DNS=y CONFIG_NFS_DEBUG=y CONFIG_NFS_DISABLE_UDP_SUPPORT=y CONFIG_NFS_V4_2_READ_PLUS=y CONFIG_NFSD=y CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_NFSD_PNFS=y CONFIG_NFSD_BLOCKLAYOUT=y CONFIG_NFSD_SCSILAYOUT=y CONFIG_NFSD_FLEXFILELAYOUT=y CONFIG_NFSD_V4_2_INTER_SSC=y CONFIG_NFSD_V4_SECURITY_LABEL=y CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y CONFIG_NFS_V4_2_SSC_HELPER=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_SUNRPC_BACKCHANNEL=y CONFIG_SUNRPC_SWAP=y CONFIG_RPCSEC_GSS_KRB5=y CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES=y CONFIG_SUNRPC_DEBUG=y CONFIG_SUNRPC_XPRT_RDMA=y CONFIG_CEPH_FS=y CONFIG_CEPH_FSCACHE=y CONFIG_CEPH_FS_POSIX_ACL=y CONFIG_CEPH_FS_SECURITY_LABEL=y CONFIG_CIFS=y CONFIG_CIFS_STATS2=y CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y CONFIG_CIFS_UPCALL=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_CIFS_DEBUG=y CONFIG_CIFS_DEBUG2=y CONFIG_CIFS_DEBUG_DUMP_KEYS=y CONFIG_CIFS_DFS_UPCALL=y CONFIG_CIFS_SWN_UPCALL=y CONFIG_CIFS_SMB_DIRECT=y CONFIG_CIFS_FSCACHE=y CONFIG_CIFS_ROOT=y CONFIG_SMB_SERVER=y CONFIG_SMB_SERVER_SMBDIRECT=y CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y CONFIG_SMB_SERVER_KERBEROS5=y CONFIG_SMBFS_COMMON=y CONFIG_CODA_FS=y CONFIG_AFS_FS=y CONFIG_AFS_DEBUG=y CONFIG_AFS_FSCACHE=y CONFIG_AFS_DEBUG_CURSOR=y CONFIG_9P_FS=y CONFIG_9P_FSCACHE=y CONFIG_9P_FS_POSIX_ACL=y CONFIG_9P_FS_SECURITY=y CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=y CONFIG_NLS_CODEPAGE_775=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_CODEPAGE_852=y CONFIG_NLS_CODEPAGE_855=y CONFIG_NLS_CODEPAGE_857=y CONFIG_NLS_CODEPAGE_860=y CONFIG_NLS_CODEPAGE_861=y CONFIG_NLS_CODEPAGE_862=y CONFIG_NLS_CODEPAGE_863=y CONFIG_NLS_CODEPAGE_864=y CONFIG_NLS_CODEPAGE_865=y CONFIG_NLS_CODEPAGE_866=y CONFIG_NLS_CODEPAGE_869=y CONFIG_NLS_CODEPAGE_936=y CONFIG_NLS_CODEPAGE_950=y CONFIG_NLS_CODEPAGE_932=y CONFIG_NLS_CODEPAGE_949=y CONFIG_NLS_CODEPAGE_874=y CONFIG_NLS_ISO8859_8=y CONFIG_NLS_CODEPAGE_1250=y CONFIG_NLS_CODEPAGE_1251=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_2=y CONFIG_NLS_ISO8859_3=y CONFIG_NLS_ISO8859_4=y CONFIG_NLS_ISO8859_5=y CONFIG_NLS_ISO8859_6=y CONFIG_NLS_ISO8859_7=y CONFIG_NLS_ISO8859_9=y CONFIG_NLS_ISO8859_13=y CONFIG_NLS_ISO8859_14=y CONFIG_NLS_ISO8859_15=y CONFIG_NLS_KOI8_R=y CONFIG_NLS_KOI8_U=y CONFIG_NLS_MAC_ROMAN=y CONFIG_NLS_MAC_CELTIC=y CONFIG_NLS_MAC_CENTEURO=y CONFIG_NLS_MAC_CROATIAN=y CONFIG_NLS_MAC_CYRILLIC=y CONFIG_NLS_MAC_GAELIC=y CONFIG_NLS_MAC_GREEK=y CONFIG_NLS_MAC_ICELAND=y CONFIG_NLS_MAC_INUIT=y CONFIG_NLS_MAC_ROMANIAN=y CONFIG_NLS_MAC_TURKISH=y CONFIG_NLS_UTF8=y CONFIG_DLM=y CONFIG_DLM_DEPRECATED_API=y CONFIG_DLM_DEBUG=y CONFIG_UNICODE=y CONFIG_UNICODE_NORMALIZATION_SELFTEST=y CONFIG_IO_WQ=y # end of File systems # # Security options # CONFIG_KEYS=y CONFIG_KEYS_REQUEST_CACHE=y CONFIG_PERSISTENT_KEYRINGS=y CONFIG_BIG_KEYS=y CONFIG_TRUSTED_KEYS=y CONFIG_TRUSTED_KEYS_TPM=y CONFIG_TRUSTED_KEYS_TEE=y CONFIG_ENCRYPTED_KEYS=y CONFIG_USER_DECRYPTED_DATA=y CONFIG_KEY_DH_OPERATIONS=y CONFIG_KEY_NOTIFICATIONS=y CONFIG_SECURITY_DMESG_RESTRICT=y CONFIG_SECURITY=y CONFIG_SECURITY_WRITABLE_HOOKS=y CONFIG_SECURITYFS=y CONFIG_SECURITY_NETWORK=y CONFIG_SECURITY_INFINIBAND=y CONFIG_SECURITY_NETWORK_XFRM=y CONFIG_SECURITY_PATH=y CONFIG_INTEL_TXT=y CONFIG_LSM_MMAP_MIN_ADDR=65536 CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y CONFIG_HARDENED_USERCOPY=y CONFIG_FORTIFY_SOURCE=y CONFIG_STATIC_USERMODEHELPER=y CONFIG_STATIC_USERMODEHELPER_PATH="/sbin/usermode-helper" CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SELINUX_BOOTPARAM=y CONFIG_SECURITY_SELINUX_DISABLE=y CONFIG_SECURITY_SELINUX_DEVELOP=y CONFIG_SECURITY_SELINUX_AVC_STATS=y CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0 CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 CONFIG_SECURITY_SMACK=y CONFIG_SECURITY_SMACK_BRINGUP=y CONFIG_SECURITY_SMACK_NETFILTER=y CONFIG_SECURITY_SMACK_APPEND_SIGNALS=y CONFIG_SECURITY_TOMOYO=y CONFIG_SECURITY_TOMOYO_MAX_ACCEPT_ENTRY=2048 CONFIG_SECURITY_TOMOYO_MAX_AUDIT_LOG=1024 CONFIG_SECURITY_TOMOYO_OMIT_USERSPACE_LOADER=y CONFIG_SECURITY_TOMOYO_INSECURE_BUILTIN_SETTING=y CONFIG_SECURITY_APPARMOR=y CONFIG_SECURITY_APPARMOR_DEBUG=y CONFIG_SECURITY_APPARMOR_DEBUG_ASSERTS=y CONFIG_SECURITY_APPARMOR_DEBUG_MESSAGES=y CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y CONFIG_SECURITY_APPARMOR_HASH=y CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y CONFIG_SECURITY_APPARMOR_KUNIT_TEST=y CONFIG_SECURITY_LOADPIN=y CONFIG_SECURITY_LOADPIN_ENFORCE=y CONFIG_SECURITY_LOADPIN_VERITY=y CONFIG_SECURITY_YAMA=y CONFIG_SECURITY_SAFESETID=y CONFIG_SECURITY_LOCKDOWN_LSM=y CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y # CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY is not set # CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY is not set CONFIG_SECURITY_LANDLOCK=y CONFIG_INTEGRITY=y CONFIG_INTEGRITY_SIGNATURE=y CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y CONFIG_INTEGRITY_TRUSTED_KEYRING=y CONFIG_INTEGRITY_PLATFORM_KEYRING=y CONFIG_LOAD_UEFI_KEYS=y CONFIG_INTEGRITY_AUDIT=y CONFIG_IMA=y CONFIG_IMA_MEASURE_PCR_IDX=10 CONFIG_IMA_LSM_RULES=y CONFIG_IMA_NG_TEMPLATE=y # CONFIG_IMA_SIG_TEMPLATE is not set CONFIG_IMA_DEFAULT_TEMPLATE="ima-ng" CONFIG_IMA_DEFAULT_HASH_SHA1=y # CONFIG_IMA_DEFAULT_HASH_SHA256 is not set # CONFIG_IMA_DEFAULT_HASH_SHA512 is not set # CONFIG_IMA_DEFAULT_HASH_WP512 is not set # CONFIG_IMA_DEFAULT_HASH_SM3 is not set CONFIG_IMA_DEFAULT_HASH="sha1" CONFIG_IMA_WRITE_POLICY=y CONFIG_IMA_READ_POLICY=y CONFIG_IMA_APPRAISE=y CONFIG_IMA_ARCH_POLICY=y CONFIG_IMA_APPRAISE_BUILD_POLICY=y CONFIG_IMA_APPRAISE_REQUIRE_FIRMWARE_SIGS=y CONFIG_IMA_APPRAISE_REQUIRE_KEXEC_SIGS=y CONFIG_IMA_APPRAISE_REQUIRE_MODULE_SIGS=y CONFIG_IMA_APPRAISE_REQUIRE_POLICY_SIGS=y CONFIG_IMA_APPRAISE_BOOTPARAM=y CONFIG_IMA_APPRAISE_MODSIG=y CONFIG_IMA_TRUSTED_KEYRING=y CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY=y CONFIG_IMA_BLACKLIST_KEYRING=y CONFIG_IMA_LOAD_X509=y CONFIG_IMA_X509_PATH="/etc/keys/x509_ima.der" CONFIG_IMA_APPRAISE_SIGNED_INIT=y CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT=y CONFIG_IMA_DISABLE_HTABLE=y CONFIG_EVM=y CONFIG_EVM_ATTR_FSUUID=y CONFIG_EVM_EXTRA_SMACK_XATTRS=y CONFIG_EVM_ADD_XATTRS=y CONFIG_EVM_LOAD_X509=y CONFIG_EVM_X509_PATH="/etc/keys/x509_evm.der" CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SECURITY_SMACK is not set # CONFIG_DEFAULT_SECURITY_TOMOYO is not set # CONFIG_DEFAULT_SECURITY_APPARMOR is not set # CONFIG_DEFAULT_SECURITY_DAC is not set CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor,bpf" # # Kernel hardening options # CONFIG_GCC_PLUGIN_STRUCTLEAK=y # # Memory initialization # # CONFIG_INIT_STACK_NONE is not set # CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set # CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL=y # CONFIG_GCC_PLUGIN_STRUCTLEAK_VERBOSE is not set CONFIG_GCC_PLUGIN_STACKLEAK=y # CONFIG_GCC_PLUGIN_STACKLEAK_VERBOSE is not set CONFIG_STACKLEAK_TRACK_MIN_SIZE=100 CONFIG_STACKLEAK_METRICS=y CONFIG_STACKLEAK_RUNTIME_DISABLE=y CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y CONFIG_INIT_ON_FREE_DEFAULT_ON=y CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y CONFIG_ZERO_CALL_USED_REGS=y # end of Memory initialization # CONFIG_RANDSTRUCT_NONE is not set CONFIG_RANDSTRUCT_FULL=y # CONFIG_RANDSTRUCT_PERFORMANCE is not set CONFIG_RANDSTRUCT=y CONFIG_GCC_PLUGIN_RANDSTRUCT=y # end of Kernel hardening options # end of Security options CONFIG_XOR_BLOCKS=y CONFIG_ASYNC_CORE=y CONFIG_ASYNC_MEMCPY=y CONFIG_ASYNC_XOR=y CONFIG_ASYNC_PQ=y CONFIG_ASYNC_RAID6_RECOV=y CONFIG_CRYPTO=y # # Crypto core or helper # CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_AKCIPHER2=y CONFIG_CRYPTO_AKCIPHER=y CONFIG_CRYPTO_KPP2=y CONFIG_CRYPTO_KPP=y CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y CONFIG_CRYPTO_USER=y CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_PCRYPT=y CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_AUTHENC=y CONFIG_CRYPTO_TEST=y CONFIG_CRYPTO_SIMD=y CONFIG_CRYPTO_ENGINE=y # end of Crypto core or helper # # Public-key cryptography # CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_ECC=y CONFIG_CRYPTO_ECDH=y CONFIG_CRYPTO_ECDSA=y CONFIG_CRYPTO_ECRDSA=y CONFIG_CRYPTO_SM2=y CONFIG_CRYPTO_CURVE25519=y # end of Public-key cryptography # # Block ciphers # CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_AES_TI=y CONFIG_CRYPTO_ANUBIS=y CONFIG_CRYPTO_ARIA=y CONFIG_CRYPTO_BLOWFISH=y CONFIG_CRYPTO_BLOWFISH_COMMON=y CONFIG_CRYPTO_CAMELLIA=y CONFIG_CRYPTO_CAST_COMMON=y CONFIG_CRYPTO_CAST5=y CONFIG_CRYPTO_CAST6=y CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_FCRYPT=y CONFIG_CRYPTO_KHAZAD=y CONFIG_CRYPTO_SEED=y CONFIG_CRYPTO_SERPENT=y CONFIG_CRYPTO_SM4=y CONFIG_CRYPTO_SM4_GENERIC=y CONFIG_CRYPTO_TEA=y CONFIG_CRYPTO_TWOFISH=y CONFIG_CRYPTO_TWOFISH_COMMON=y # end of Block ciphers # # Length-preserving ciphers and modes # CONFIG_CRYPTO_ADIANTUM=y CONFIG_CRYPTO_ARC4=y CONFIG_CRYPTO_CHACHA20=y CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CFB=y CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_CTS=y CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_HCTR2=y CONFIG_CRYPTO_KEYWRAP=y CONFIG_CRYPTO_LRW=y CONFIG_CRYPTO_OFB=y CONFIG_CRYPTO_PCBC=y CONFIG_CRYPTO_XCTR=y CONFIG_CRYPTO_XTS=y CONFIG_CRYPTO_NHPOLY1305=y # end of Length-preserving ciphers and modes # # AEAD (authenticated encryption with associated data) ciphers # CONFIG_CRYPTO_AEGIS128=y CONFIG_CRYPTO_CHACHA20POLY1305=y CONFIG_CRYPTO_CCM=y CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_ECHAINIV=y CONFIG_CRYPTO_ESSIV=y # end of AEAD (authenticated encryption with associated data) ciphers # # Hashes, digests, and MACs # CONFIG_CRYPTO_BLAKE2B=y CONFIG_CRYPTO_CMAC=y CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=y CONFIG_CRYPTO_POLYVAL=y CONFIG_CRYPTO_POLY1305=y CONFIG_CRYPTO_RMD160=y CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA3=y CONFIG_CRYPTO_SM3=y CONFIG_CRYPTO_SM3_GENERIC=y CONFIG_CRYPTO_STREEBOG=y CONFIG_CRYPTO_VMAC=y CONFIG_CRYPTO_WP512=y CONFIG_CRYPTO_XCBC=y CONFIG_CRYPTO_XXHASH=y # end of Hashes, digests, and MACs # # CRCs (cyclic redundancy checks) # CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_CRC64_ROCKSOFT=y # end of CRCs (cyclic redundancy checks) # # Compression # CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_842=y CONFIG_CRYPTO_LZ4=y CONFIG_CRYPTO_LZ4HC=y CONFIG_CRYPTO_ZSTD=y # end of Compression # # Random number generation # CONFIG_CRYPTO_ANSI_CPRNG=y CONFIG_CRYPTO_DRBG_MENU=y CONFIG_CRYPTO_DRBG_HMAC=y CONFIG_CRYPTO_DRBG_HASH=y CONFIG_CRYPTO_DRBG_CTR=y CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_KDF800108_CTR=y # end of Random number generation # # Userspace interface # CONFIG_CRYPTO_USER_API=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_SKCIPHER=y CONFIG_CRYPTO_USER_API_RNG=y CONFIG_CRYPTO_USER_API_RNG_CAVP=y CONFIG_CRYPTO_USER_API_AEAD=y CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y CONFIG_CRYPTO_STATS=y # end of Userspace interface CONFIG_CRYPTO_HASH_INFO=y # # Accelerated Cryptographic Algorithms for CPU (x86) # CONFIG_CRYPTO_AES_NI_INTEL=y CONFIG_CRYPTO_SERPENT_SSE2_586=y CONFIG_CRYPTO_TWOFISH_586=y CONFIG_CRYPTO_CRC32C_INTEL=y CONFIG_CRYPTO_CRC32_PCLMUL=y # end of Accelerated Cryptographic Algorithms for CPU (x86) CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_DEV_PADLOCK=y CONFIG_CRYPTO_DEV_PADLOCK_AES=y CONFIG_CRYPTO_DEV_PADLOCK_SHA=y CONFIG_CRYPTO_DEV_GEODE=y CONFIG_CRYPTO_DEV_HIFN_795X=y CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y CONFIG_CRYPTO_DEV_ATMEL_I2C=y CONFIG_CRYPTO_DEV_ATMEL_ECC=y CONFIG_CRYPTO_DEV_ATMEL_SHA204A=y CONFIG_CRYPTO_DEV_CCP=y CONFIG_CRYPTO_DEV_CCP_DD=y CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_CCP_CRYPTO=y CONFIG_CRYPTO_DEV_CCP_DEBUGFS=y CONFIG_CRYPTO_DEV_QAT=y CONFIG_CRYPTO_DEV_QAT_DH895xCC=y CONFIG_CRYPTO_DEV_QAT_C3XXX=y CONFIG_CRYPTO_DEV_QAT_C62X=y CONFIG_CRYPTO_DEV_QAT_4XXX=y CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=y CONFIG_CRYPTO_DEV_QAT_C3XXXVF=y CONFIG_CRYPTO_DEV_QAT_C62XVF=y CONFIG_CRYPTO_DEV_CHELSIO=y CONFIG_CRYPTO_DEV_VIRTIO=y CONFIG_CRYPTO_DEV_SAFEXCEL=y CONFIG_CRYPTO_DEV_CCREE=y CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG=y CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y CONFIG_PKCS8_PRIVATE_KEY_PARSER=y CONFIG_PKCS7_MESSAGE_PARSER=y CONFIG_PKCS7_TEST_KEY=y CONFIG_SIGNED_PE_FILE_VERIFICATION=y CONFIG_FIPS_SIGNATURE_SELFTEST=y # # Certificates for signature checking # CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" CONFIG_MODULE_SIG_KEY_TYPE_RSA=y # CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set CONFIG_SYSTEM_TRUSTED_KEYRING=y CONFIG_SYSTEM_TRUSTED_KEYS="" CONFIG_SYSTEM_EXTRA_CERTIFICATE=y CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096 CONFIG_SECONDARY_TRUSTED_KEYRING=y CONFIG_SYSTEM_BLACKLIST_KEYRING=y CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" CONFIG_SYSTEM_REVOCATION_LIST=y CONFIG_SYSTEM_REVOCATION_KEYS="" CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y # end of Certificates for signature checking CONFIG_BINARY_PRINTF=y # # Library routines # CONFIG_RAID6_PQ=y CONFIG_RAID6_PQ_BENCHMARK=y CONFIG_LINEAR_RANGES=y CONFIG_PACKING=y CONFIG_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y CONFIG_CORDIC=y CONFIG_PRIME_NUMBERS=y CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_IOMAP=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y # # Crypto library routines # CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y CONFIG_CRYPTO_LIB_CHACHA=y CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y CONFIG_CRYPTO_LIB_CURVE25519=y CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305=y CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC_T10DIF=y CONFIG_CRC64_ROCKSOFT=y CONFIG_CRC_ITU_T=y CONFIG_CRC32=y CONFIG_CRC32_SELFTEST=y CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_SLICEBY4 is not set # CONFIG_CRC32_SARWATE is not set # CONFIG_CRC32_BIT is not set CONFIG_CRC64=y CONFIG_CRC4=y CONFIG_CRC7=y CONFIG_LIBCRC32C=y CONFIG_CRC8=y CONFIG_XXHASH=y CONFIG_AUDIT_GENERIC=y CONFIG_RANDOM32_SELFTEST=y CONFIG_842_COMPRESS=y CONFIG_842_DECOMPRESS=y CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4_COMPRESS=y CONFIG_LZ4HC_COMPRESS=y CONFIG_LZ4_DECOMPRESS=y CONFIG_ZSTD_COMMON=y CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_IA64=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_SPARC=y CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_BCJ=y CONFIG_XZ_DEC_TEST=y CONFIG_DECOMPRESS_GZIP=y CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_LZMA=y CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_DECOMPRESS_LZ4=y CONFIG_DECOMPRESS_ZSTD=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_REED_SOLOMON=y CONFIG_REED_SOLOMON_ENC8=y CONFIG_REED_SOLOMON_DEC8=y CONFIG_REED_SOLOMON_ENC16=y CONFIG_REED_SOLOMON_DEC16=y CONFIG_BCH=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=y CONFIG_TEXTSEARCH_BM=y CONFIG_TEXTSEARCH_FSM=y CONFIG_BTREE=y CONFIG_INTERVAL_TREE=y CONFIG_XARRAY_MULTI=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y CONFIG_DMA_OPS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_SWIOTLB=y CONFIG_DMA_RESTRICTED_POOL=y CONFIG_DMA_CMA=y CONFIG_DMA_PERNUMA_CMA=y # # Default contiguous memory area size: # CONFIG_CMA_SIZE_MBYTES=0 CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set # CONFIG_CMA_SIZE_SEL_MIN is not set # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 CONFIG_DMA_API_DEBUG=y CONFIG_DMA_API_DEBUG_SG=y CONFIG_DMA_MAP_BENCHMARK=y CONFIG_SGL_ALLOC=y CONFIG_CHECK_SIGNATURE=y CONFIG_CPUMASK_OFFSTACK=y CONFIG_FORCE_NR_CPUS=y CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_GLOB=y CONFIG_GLOB_SELFTEST=y CONFIG_NLATTR=y CONFIG_LRU_CACHE=y CONFIG_CLZ_TAB=y CONFIG_IRQ_POLL=y CONFIG_MPILIB=y CONFIG_SIGNATURE=y CONFIG_DIMLIB=y CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_UCS2_STRING=y CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_VDSO_32=y CONFIG_GENERIC_VDSO_TIME_NS=y CONFIG_FONT_SUPPORT=y CONFIG_FONTS=y CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_FONT_6x11=y CONFIG_FONT_7x14=y CONFIG_FONT_PEARL_8x8=y CONFIG_FONT_ACORN_8x8=y CONFIG_FONT_MINI_4x6=y CONFIG_FONT_6x10=y CONFIG_FONT_10x18=y CONFIG_FONT_SUN8x16=y CONFIG_FONT_SUN12x22=y CONFIG_FONT_TER16x32=y CONFIG_FONT_6x8=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y CONFIG_STACKDEPOT_ALWAYS_INIT=y CONFIG_REF_TRACKER=y CONFIG_SBITMAP=y CONFIG_PARMAN=y CONFIG_OBJAGG=y # end of Library routines CONFIG_PLDMFW=y CONFIG_ASN1_ENCODER=y CONFIG_POLYNOMIAL=y # # Kernel hacking # # # printk and dmesg options # CONFIG_PRINTK_TIME=y CONFIG_PRINTK_CALLER=y CONFIG_STACKTRACE_BUILD_ID=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 CONFIG_BOOT_PRINTK_DELAY=y CONFIG_DYNAMIC_DEBUG=y CONFIG_DYNAMIC_DEBUG_CORE=y CONFIG_SYMBOLIC_ERRNAME=y CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y # # Compile-time checks and compiler options # CONFIG_AS_HAS_NON_CONST_LEB128=y CONFIG_DEBUG_INFO_NONE=y # CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set # CONFIG_DEBUG_INFO_DWARF4 is not set # CONFIG_DEBUG_INFO_DWARF5 is not set CONFIG_FRAME_WARN=2048 CONFIG_STRIP_ASM_SYMS=y CONFIG_READABLE_ASM=y CONFIG_HEADERS_INSTALL=y CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_SECTION_MISMATCH_WARN_ONLY=y CONFIG_FRAME_POINTER=y CONFIG_VMLINUX_MAP=y CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y # end of Compile-time checks and compiler options # # Generic Kernel Debugging Instruments # CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 CONFIG_MAGIC_SYSRQ_SERIAL=y CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y CONFIG_KGDB=y CONFIG_KGDB_HONOUR_BLOCKLIST=y CONFIG_KGDB_SERIAL_CONSOLE=y CONFIG_KGDB_TESTS=y CONFIG_KGDB_TESTS_ON_BOOT=y CONFIG_KGDB_TESTS_BOOT_STRING="V1F100" CONFIG_KGDB_LOW_LEVEL_TRAP=y CONFIG_KGDB_KDB=y CONFIG_KDB_DEFAULT_ENABLE=0x1 CONFIG_KDB_KEYBOARD=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_ARCH_HAS_EARLY_DEBUG=y CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y CONFIG_UBSAN=y # CONFIG_UBSAN_TRAP is not set CONFIG_CC_HAS_UBSAN_BOUNDS=y CONFIG_UBSAN_BOUNDS=y CONFIG_UBSAN_ONLY_BOUNDS=y CONFIG_UBSAN_SHIFT=y CONFIG_UBSAN_DIV_ZERO=y CONFIG_UBSAN_UNREACHABLE=y CONFIG_UBSAN_BOOL=y CONFIG_UBSAN_ENUM=y # CONFIG_UBSAN_ALIGNMENT is not set CONFIG_UBSAN_SANITIZE_ALL=y CONFIG_TEST_UBSAN=m CONFIG_HAVE_KCSAN_COMPILER=y # end of Generic Kernel Debugging Instruments # # Networking Debugging # CONFIG_NET_DEV_REFCNT_TRACKER=y CONFIG_NET_NS_REFCNT_TRACKER=y CONFIG_DEBUG_NET=y # end of Networking Debugging # # Memory Debugging # CONFIG_PAGE_EXTENSION=y CONFIG_DEBUG_PAGEALLOC=y CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y CONFIG_SLUB_DEBUG=y CONFIG_SLUB_DEBUG_ON=y CONFIG_PAGE_OWNER=y CONFIG_PAGE_POISONING=y CONFIG_DEBUG_PAGE_REF=y CONFIG_DEBUG_RODATA_TEST=y CONFIG_ARCH_HAS_DEBUG_WX=y CONFIG_DEBUG_WX=y CONFIG_GENERIC_PTDUMP=y CONFIG_PTDUMP_CORE=y CONFIG_PTDUMP_DEBUGFS=y CONFIG_DEBUG_OBJECTS=y CONFIG_DEBUG_OBJECTS_SELFTEST=y CONFIG_DEBUG_OBJECTS_FREE=y CONFIG_DEBUG_OBJECTS_TIMERS=y CONFIG_DEBUG_OBJECTS_WORK=y CONFIG_DEBUG_OBJECTS_RCU_HEAD=y CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 CONFIG_SHRINKER_DEBUG=y CONFIG_HAVE_DEBUG_KMEMLEAK=y CONFIG_DEBUG_KMEMLEAK=y CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000 CONFIG_DEBUG_KMEMLEAK_TEST=m CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y CONFIG_DEBUG_STACK_USAGE=y CONFIG_SCHED_STACK_END_CHECK=y CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y CONFIG_DEBUG_VM_IRQSOFF=y CONFIG_DEBUG_VM=y CONFIG_DEBUG_VM_MAPLE_TREE=y CONFIG_DEBUG_VM_RB=y CONFIG_DEBUG_VM_PGFLAGS=y CONFIG_DEBUG_VM_PGTABLE=y CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y CONFIG_DEBUG_VIRTUAL=y CONFIG_DEBUG_MEMORY_INIT=y CONFIG_DEBUG_PER_CPU_MAPS=y CONFIG_DEBUG_KMAP_LOCAL=y CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP=y CONFIG_DEBUG_HIGHMEM=y CONFIG_HAVE_DEBUG_STACKOVERFLOW=y CONFIG_DEBUG_STACKOVERFLOW=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y CONFIG_HAVE_ARCH_KFENCE=y CONFIG_KFENCE=y CONFIG_KFENCE_SAMPLE_INTERVAL=100 CONFIG_KFENCE_NUM_OBJECTS=255 CONFIG_KFENCE_DEFERRABLE=y CONFIG_KFENCE_STATIC_KEYS=y CONFIG_KFENCE_STRESS_TEST_FAULTS=0 CONFIG_KFENCE_KUNIT_TEST=y # end of Memory Debugging CONFIG_DEBUG_SHIRQ=y # # Debug Oops, Lockups and Hangs # CONFIG_PANIC_ON_OOPS=y CONFIG_PANIC_ON_OOPS_VALUE=1 CONFIG_PANIC_TIMEOUT=0 CONFIG_LOCKUP_DETECTOR=y CONFIG_SOFTLOCKUP_DETECTOR=y CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y CONFIG_HARDLOCKUP_DETECTOR_PERF=y CONFIG_HARDLOCKUP_DETECTOR=y CONFIG_BOOTPARAM_HARDLOCKUP_PANIC=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y CONFIG_WQ_WATCHDOG=y CONFIG_TEST_LOCKUP=m # end of Debug Oops, Lockups and Hangs # # Scheduler Debugging # CONFIG_SCHED_DEBUG=y CONFIG_SCHED_INFO=y CONFIG_SCHEDSTATS=y # end of Scheduler Debugging CONFIG_DEBUG_TIMEKEEPING=y CONFIG_DEBUG_PREEMPT=y # # Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_PROVE_LOCKING=y CONFIG_PROVE_RAW_LOCK_NESTING=y CONFIG_LOCK_STAT=y CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y CONFIG_DEBUG_RWSEMS=y CONFIG_DEBUG_LOCK_ALLOC=y CONFIG_LOCKDEP=y CONFIG_LOCKDEP_BITS=15 CONFIG_LOCKDEP_CHAINS_BITS=16 CONFIG_LOCKDEP_STACK_TRACE_BITS=19 CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 CONFIG_DEBUG_LOCKDEP=y CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_DEBUG_LOCKING_API_SELFTESTS=y CONFIG_LOCK_TORTURE_TEST=y CONFIG_WW_MUTEX_SELFTEST=y CONFIG_SCF_TORTURE_TEST=y # end of Lock Debugging (spinlocks, mutexes, etc...) CONFIG_TRACE_IRQFLAGS=y CONFIG_TRACE_IRQFLAGS_NMI=y CONFIG_DEBUG_IRQFLAGS=y CONFIG_STACKTRACE=y CONFIG_WARN_ALL_UNSEEDED_RANDOM=y CONFIG_DEBUG_KOBJECT=y CONFIG_DEBUG_KOBJECT_RELEASE=y # # Debug kernel data structures # CONFIG_DEBUG_LIST=y CONFIG_DEBUG_PLIST=y CONFIG_DEBUG_SG=y CONFIG_DEBUG_NOTIFIERS=y CONFIG_BUG_ON_DATA_CORRUPTION=y CONFIG_DEBUG_MAPLE_TREE=y # end of Debug kernel data structures CONFIG_DEBUG_CREDENTIALS=y # # RCU Debugging # CONFIG_PROVE_RCU=y CONFIG_PROVE_RCU_LIST=y CONFIG_TORTURE_TEST=y CONFIG_RCU_SCALE_TEST=y CONFIG_RCU_TORTURE_TEST=y CONFIG_RCU_REF_SCALE_TEST=y CONFIG_RCU_CPU_STALL_TIMEOUT=21 CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 CONFIG_RCU_TRACE=y CONFIG_RCU_EQS_DEBUG=y # end of RCU Debugging CONFIG_DEBUG_WQ_FORCE_RR_CPU=y CONFIG_CPU_HOTPLUG_STATE_CONTROL=y CONFIG_LATENCYTOP=y CONFIG_USER_STACKTRACE_SUPPORT=y CONFIG_NOP_TRACER=y CONFIG_HAVE_RETHOOK=y CONFIG_RETHOOK=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y CONFIG_HAVE_DYNAMIC_FTRACE_NO_PATCHABLE=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_FENTRY=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y CONFIG_BUILDTIME_MCOUNT_SORT=y CONFIG_TRACER_MAX_TRACE=y CONFIG_TRACE_CLOCK=y CONFIG_RING_BUFFER=y CONFIG_EVENT_TRACING=y CONFIG_CONTEXT_SWITCH_TRACER=y CONFIG_RING_BUFFER_ALLOW_SWAP=y CONFIG_PREEMPTIRQ_TRACEPOINTS=y CONFIG_TRACING=y CONFIG_GENERIC_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y CONFIG_BOOTTIME_TRACING=y CONFIG_FUNCTION_TRACER=y CONFIG_FUNCTION_GRAPH_TRACER=y CONFIG_DYNAMIC_FTRACE=y CONFIG_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y CONFIG_FPROBE=y CONFIG_FUNCTION_PROFILER=y CONFIG_STACK_TRACER=y CONFIG_TRACE_PREEMPT_TOGGLE=y CONFIG_IRQSOFF_TRACER=y CONFIG_PREEMPT_TRACER=y CONFIG_SCHED_TRACER=y CONFIG_HWLAT_TRACER=y CONFIG_OSNOISE_TRACER=y CONFIG_TIMERLAT_TRACER=y CONFIG_MMIOTRACE=y CONFIG_FTRACE_SYSCALLS=y CONFIG_TRACER_SNAPSHOT=y CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set CONFIG_BLK_DEV_IO_TRACE=y CONFIG_KPROBE_EVENTS=y CONFIG_KPROBE_EVENTS_ON_NOTRACE=y CONFIG_UPROBE_EVENTS=y CONFIG_BPF_EVENTS=y CONFIG_DYNAMIC_EVENTS=y CONFIG_PROBE_EVENTS=y CONFIG_BPF_KPROBE_OVERRIDE=y CONFIG_FTRACE_MCOUNT_RECORD=y CONFIG_FTRACE_MCOUNT_USE_CC=y CONFIG_TRACING_MAP=y CONFIG_SYNTH_EVENTS=y CONFIG_HIST_TRIGGERS=y CONFIG_TRACE_EVENT_INJECT=y CONFIG_TRACEPOINT_BENCHMARK=y CONFIG_RING_BUFFER_BENCHMARK=y CONFIG_TRACE_EVAL_MAP_FILE=y CONFIG_FTRACE_RECORD_RECURSION=y CONFIG_FTRACE_RECORD_RECURSION_SIZE=128 CONFIG_RING_BUFFER_RECORD_RECURSION=y CONFIG_GCOV_PROFILE_FTRACE=y CONFIG_FTRACE_SELFTEST=y CONFIG_FTRACE_STARTUP_TEST=y CONFIG_EVENT_TRACE_STARTUP_TEST=y CONFIG_EVENT_TRACE_TEST_SYSCALLS=y CONFIG_FTRACE_SORT_STARTUP_TEST=y CONFIG_RING_BUFFER_STARTUP_TEST=y CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS=y CONFIG_MMIOTRACE_TEST=m CONFIG_PREEMPTIRQ_DELAY_TEST=m CONFIG_SYNTH_EVENT_GEN_TEST=y CONFIG_KPROBE_EVENT_GEN_TEST=y CONFIG_HIST_TRIGGERS_DEBUG=y CONFIG_DA_MON_EVENTS=y CONFIG_DA_MON_EVENTS_IMPLICIT=y CONFIG_DA_MON_EVENTS_ID=y CONFIG_RV=y CONFIG_RV_MON_WIP=y CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PRINTK=y CONFIG_RV_REACT_PANIC=y CONFIG_PROVIDE_OHCI1394_DMA_INIT=y CONFIG_SAMPLES=y CONFIG_SAMPLE_AUXDISPLAY=y CONFIG_SAMPLE_TRACE_EVENTS=m CONFIG_SAMPLE_TRACE_CUSTOM_EVENTS=m CONFIG_SAMPLE_TRACE_PRINTK=m CONFIG_SAMPLE_TRACE_ARRAY=m CONFIG_SAMPLE_KOBJECT=y CONFIG_SAMPLE_KPROBES=m CONFIG_SAMPLE_KRETPROBES=m CONFIG_SAMPLE_HW_BREAKPOINT=m CONFIG_SAMPLE_FPROBE=m CONFIG_SAMPLE_KFIFO=m CONFIG_SAMPLE_KDB=m CONFIG_SAMPLE_RPMSG_CLIENT=m CONFIG_SAMPLE_CONFIGFS=m CONFIG_SAMPLE_CONNECTOR=m CONFIG_SAMPLE_FANOTIFY_ERROR=y CONFIG_SAMPLE_HIDRAW=y CONFIG_SAMPLE_LANDLOCK=y CONFIG_SAMPLE_PIDFD=y CONFIG_SAMPLE_SECCOMP=y CONFIG_SAMPLE_TIMER=y CONFIG_SAMPLE_UHID=y CONFIG_SAMPLE_VFIO_MDEV_MTTY=m CONFIG_SAMPLE_VFIO_MDEV_MDPY=m CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB=m CONFIG_SAMPLE_VFIO_MDEV_MBOCHS=m CONFIG_SAMPLE_ANDROID_BINDERFS=y CONFIG_SAMPLE_VFS=y CONFIG_SAMPLE_INTEL_MEI=y CONFIG_SAMPLE_WATCHDOG=y CONFIG_SAMPLE_WATCH_QUEUE=y CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y CONFIG_STRICT_DEVMEM=y CONFIG_IO_STRICT_DEVMEM=y # # x86 Debugging # CONFIG_EARLY_PRINTK_USB=y CONFIG_X86_VERBOSE_BOOTUP=y CONFIG_EARLY_PRINTK=y CONFIG_EARLY_PRINTK_DBGP=y CONFIG_EARLY_PRINTK_USB_XDBC=y CONFIG_EFI_PGT_DUMP=y CONFIG_DEBUG_TLBFLUSH=y CONFIG_HAVE_MMIOTRACE_SUPPORT=y # CONFIG_X86_DECODER_SELFTEST is not set CONFIG_IO_DELAY_0X80=y # CONFIG_IO_DELAY_0XED is not set # CONFIG_IO_DELAY_UDELAY is not set # CONFIG_IO_DELAY_NONE is not set CONFIG_DEBUG_BOOT_PARAMS=y CONFIG_CPA_DEBUG=y CONFIG_DEBUG_ENTRY=y CONFIG_DEBUG_NMI_SELFTEST=y CONFIG_DEBUG_IMR_SELFTEST=y CONFIG_X86_DEBUG_FPU=y CONFIG_PUNIT_ATOM_DEBUG=y CONFIG_UNWINDER_FRAME_POINTER=y # end of x86 Debugging # # Kernel Testing and Coverage # CONFIG_KUNIT=y CONFIG_KUNIT_DEBUGFS=y CONFIG_KUNIT_TEST=y CONFIG_KUNIT_EXAMPLE_TEST=y CONFIG_KUNIT_ALL_TESTS=y CONFIG_KUNIT_DEFAULT_ENABLED=y CONFIG_NOTIFIER_ERROR_INJECTION=y CONFIG_PM_NOTIFIER_ERROR_INJECT=y CONFIG_OF_RECONFIG_NOTIFIER_ERROR_INJECT=y CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=y CONFIG_FUNCTION_ERROR_INJECTION=y CONFIG_FAULT_INJECTION=y CONFIG_FAILSLAB=y CONFIG_FAIL_PAGE_ALLOC=y CONFIG_FAULT_INJECTION_USERCOPY=y CONFIG_FAIL_MAKE_REQUEST=y CONFIG_FAIL_IO_TIMEOUT=y CONFIG_FAIL_FUTEX=y CONFIG_FAULT_INJECTION_DEBUG_FS=y CONFIG_FAIL_FUNCTION=y CONFIG_FAIL_MMC_REQUEST=y CONFIG_FAIL_SUNRPC=y CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_RUNTIME_TESTING_MENU=y CONFIG_LKDTM=y CONFIG_CPUMASK_KUNIT_TEST=y CONFIG_TEST_LIST_SORT=y CONFIG_TEST_MIN_HEAP=y CONFIG_TEST_SORT=y CONFIG_TEST_DIV64=y CONFIG_KPROBES_SANITY_TEST=y CONFIG_FPROBE_SANITY_TEST=y CONFIG_BACKTRACE_SELF_TEST=y CONFIG_TEST_REF_TRACKER=y CONFIG_RBTREE_TEST=y CONFIG_REED_SOLOMON_TEST=y CONFIG_INTERVAL_TREE_TEST=y CONFIG_PERCPU_TEST=m CONFIG_ATOMIC64_SELFTEST=y CONFIG_ASYNC_RAID6_TEST=y CONFIG_TEST_HEXDUMP=y CONFIG_STRING_SELFTEST=y CONFIG_TEST_STRING_HELPERS=y # CONFIG_TEST_STRSCPY is not set CONFIG_TEST_KSTRTOX=y CONFIG_TEST_PRINTF=y CONFIG_TEST_SCANF=y CONFIG_TEST_BITMAP=y CONFIG_TEST_UUID=y CONFIG_TEST_XARRAY=y CONFIG_TEST_RHASHTABLE=y # CONFIG_TEST_SIPHASH is not set CONFIG_TEST_IDA=y CONFIG_TEST_PARMAN=y CONFIG_TEST_LKM=m CONFIG_TEST_BITOPS=m CONFIG_TEST_VMALLOC=m CONFIG_TEST_USER_COPY=m CONFIG_TEST_BPF=m CONFIG_TEST_BLACKHOLE_DEV=m CONFIG_FIND_BIT_BENCHMARK=y CONFIG_TEST_FIRMWARE=y CONFIG_TEST_SYSCTL=y CONFIG_BITFIELD_KUNIT=y CONFIG_HASH_KUNIT_TEST=y CONFIG_RESOURCE_KUNIT_TEST=y CONFIG_SYSCTL_KUNIT_TEST=y CONFIG_LIST_KUNIT_TEST=y CONFIG_LINEAR_RANGES_TEST=y CONFIG_CMDLINE_KUNIT_TEST=y CONFIG_BITS_TEST=y CONFIG_SLUB_KUNIT_TEST=y CONFIG_RATIONAL_KUNIT_TEST=y CONFIG_MEMCPY_KUNIT_TEST=y CONFIG_IS_SIGNED_TYPE_KUNIT_TEST=y CONFIG_OVERFLOW_KUNIT_TEST=y CONFIG_STACKINIT_KUNIT_TEST=y CONFIG_FORTIFY_KUNIT_TEST=y CONFIG_HW_BREAKPOINT_KUNIT_TEST=y CONFIG_TEST_UDELAY=y CONFIG_TEST_STATIC_KEYS=m CONFIG_TEST_DYNAMIC_DEBUG=y CONFIG_TEST_KMOD=m CONFIG_TEST_DEBUG_VIRTUAL=y CONFIG_TEST_MEMCAT_P=y CONFIG_TEST_OBJAGG=y CONFIG_TEST_MEMINIT=y CONFIG_TEST_FREE_PAGES=y CONFIG_TEST_FPU=y CONFIG_TEST_CLOCKSOURCE_WATCHDOG=y CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y CONFIG_HYPERV_TESTING=y # end of Kernel Testing and Coverage # # Rust hacking # # end of Rust hacking # end of Kernel hacking ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 00/12] Add support for the Cirrus Logic CS48L32 audio codecs 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-10 20:53 ` Mark Brown -1 siblings, 0 replies; 98+ messages in thread From: Mark Brown @ 2022-11-10 20:53 UTC (permalink / raw) To: Richard Fitzgerald Cc: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, tglx, maz, alsa-devel, devicetree, linux-gpio, linux-kernel, patches [-- Attachment #1: Type: text/plain, Size: 671 bytes --] On Wed, Nov 09, 2022 at 04:53:19PM +0000, Richard Fitzgerald wrote: > regulator: arizona-micsupp: Don't hardcode use of ARIZONA defines > regulator: arizona-micsupp: Don't use a common regulator name > ASoC: wm_adsp: Allow client to hook into pre_run callback The regulator and ASoC bits look good. It looks like this is going to need another spin for at least the DT and irqchip bits, I think it'd make sense to take the above cleanup patches for this release even if everything else misses it to cut down on future patch volume. I'll leave it for a bit and do that unless someone has concerns, it's going to be easier than applying and sending pull requests. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 00/12] Add support for the Cirrus Logic CS48L32 audio codecs @ 2022-11-10 20:53 ` Mark Brown 0 siblings, 0 replies; 98+ messages in thread From: Mark Brown @ 2022-11-10 20:53 UTC (permalink / raw) To: Richard Fitzgerald Cc: devicetree, alsa-devel, maz, linus.walleij, lee, linux-kernel, linux-gpio, robh+dt, krzysztof.kozlowski+dt, patches, tglx [-- Attachment #1: Type: text/plain, Size: 671 bytes --] On Wed, Nov 09, 2022 at 04:53:19PM +0000, Richard Fitzgerald wrote: > regulator: arizona-micsupp: Don't hardcode use of ARIZONA defines > regulator: arizona-micsupp: Don't use a common regulator name > ASoC: wm_adsp: Allow client to hook into pre_run callback The regulator and ASoC bits look good. It looks like this is going to need another spin for at least the DT and irqchip bits, I think it'd make sense to take the above cleanup patches for this release even if everything else misses it to cut down on future patch volume. I'll leave it for a bit and do that unless someone has concerns, it's going to be easier than applying and sending pull requests. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 00/12] Add support for the Cirrus Logic CS48L32 audio codecs 2022-11-10 20:53 ` Mark Brown @ 2022-11-11 13:50 ` Richard Fitzgerald -1 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-11 13:50 UTC (permalink / raw) To: Mark Brown Cc: lee, robh+dt, krzysztof.kozlowski+dt, linus.walleij, tglx, maz, alsa-devel, devicetree, linux-gpio, linux-kernel, patches On 10/11/2022 20:53, Mark Brown wrote: > On Wed, Nov 09, 2022 at 04:53:19PM +0000, Richard Fitzgerald wrote: > >> regulator: arizona-micsupp: Don't hardcode use of ARIZONA defines >> regulator: arizona-micsupp: Don't use a common regulator name >> ASoC: wm_adsp: Allow client to hook into pre_run callback > > The regulator and ASoC bits look good. It looks like this is going to > need another spin for at least the DT and irqchip bits, I think it'd > make sense to take the above cleanup patches for this release even if > everything else misses it to cut down on future patch volume. I'll > leave it for a bit and do that unless someone has concerns, it's going > to be easier than applying and sending pull requests. Yes, I have tested that these 3 patches can apply and build on their own and don't break the older chips. I should have put these at the start of the chain and mentioned in the cover letter that they can be taken independently. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: [PATCH 00/12] Add support for the Cirrus Logic CS48L32 audio codecs @ 2022-11-11 13:50 ` Richard Fitzgerald 0 siblings, 0 replies; 98+ messages in thread From: Richard Fitzgerald @ 2022-11-11 13:50 UTC (permalink / raw) To: Mark Brown Cc: devicetree, alsa-devel, maz, linus.walleij, lee, linux-kernel, linux-gpio, robh+dt, krzysztof.kozlowski+dt, patches, tglx On 10/11/2022 20:53, Mark Brown wrote: > On Wed, Nov 09, 2022 at 04:53:19PM +0000, Richard Fitzgerald wrote: > >> regulator: arizona-micsupp: Don't hardcode use of ARIZONA defines >> regulator: arizona-micsupp: Don't use a common regulator name >> ASoC: wm_adsp: Allow client to hook into pre_run callback > > The regulator and ASoC bits look good. It looks like this is going to > need another spin for at least the DT and irqchip bits, I think it'd > make sense to take the above cleanup patches for this release even if > everything else misses it to cut down on future patch volume. I'll > leave it for a bit and do that unless someone has concerns, it's going > to be easier than applying and sending pull requests. Yes, I have tested that these 3 patches can apply and build on their own and don't break the older chips. I should have put these at the start of the chain and mentioned in the cover letter that they can be taken independently. ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: (subset) [PATCH 00/12] Add support for the Cirrus Logic CS48L32 audio codecs 2022-11-09 16:53 ` Richard Fitzgerald @ 2022-11-23 13:11 ` Mark Brown -1 siblings, 0 replies; 98+ messages in thread From: Mark Brown @ 2022-11-23 13:11 UTC (permalink / raw) To: krzysztof.kozlowski+dt, lee, linus.walleij, maz, tglx, Richard Fitzgerald, robh+dt Cc: patches, alsa-devel, linux-kernel, devicetree, linux-gpio On Wed, 9 Nov 2022 16:53:19 +0000, Richard Fitzgerald wrote: > The CS48L32 is a high-performance low-power audio DSP for smartphones > and other portable audio devices. It has various digital audio I/O, > a programmable Halo Core DSP, fixed-function audio processors, > configurable GPIO and microphone bias regulators. > > The CS48L31 and CS48L33 were derivatives of the CS48L32. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next Thanks! [10/12] ASoC: wm_adsp: Allow client to hook into pre_run callback commit: fe07130870c8540bc0cddbaa8d4521ecdba6b560 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark ^ permalink raw reply [flat|nested] 98+ messages in thread
* Re: (subset) [PATCH 00/12] Add support for the Cirrus Logic CS48L32 audio codecs @ 2022-11-23 13:11 ` Mark Brown 0 siblings, 0 replies; 98+ messages in thread From: Mark Brown @ 2022-11-23 13:11 UTC (permalink / raw) To: krzysztof.kozlowski+dt, lee, linus.walleij, maz, tglx, Richard Fitzgerald, robh+dt Cc: alsa-devel, patches, linux-kernel, linux-gpio, devicetree On Wed, 9 Nov 2022 16:53:19 +0000, Richard Fitzgerald wrote: > The CS48L32 is a high-performance low-power audio DSP for smartphones > and other portable audio devices. It has various digital audio I/O, > a programmable Halo Core DSP, fixed-function audio processors, > configurable GPIO and microphone bias regulators. > > The CS48L31 and CS48L33 were derivatives of the CS48L32. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next Thanks! [10/12] ASoC: wm_adsp: Allow client to hook into pre_run callback commit: fe07130870c8540bc0cddbaa8d4521ecdba6b560 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark ^ permalink raw reply [flat|nested] 98+ messages in thread
end of thread, other threads:[~2022-11-23 13:31 UTC | newest] Thread overview: 98+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-11-09 16:53 [PATCH 00/12] Add support for the Cirrus Logic CS48L32 audio codecs Richard Fitzgerald 2022-11-09 16:53 ` Richard Fitzgerald 2022-11-09 16:53 ` [PATCH 01/12] dt-bindings: mfd: Add Cirrus Logic CS48L32 audio codec Richard Fitzgerald 2022-11-09 16:53 ` Richard Fitzgerald 2022-11-09 21:09 ` Rob Herring 2022-11-09 21:09 ` Rob Herring 2022-11-14 8:36 ` Krzysztof Kozlowski 2022-11-14 8:36 ` Krzysztof Kozlowski 2022-11-09 16:53 ` [PATCH 02/12] mfd: cs48l32: Add register definitions for Cirrus Logic CS48L31/32/33 Richard Fitzgerald 2022-11-09 16:53 ` Richard Fitzgerald 2022-11-09 16:53 ` [PATCH 03/12] mfd: cs48l32: Add support for CS48L31/32/33 codecs Richard Fitzgerald 2022-11-09 16:53 ` Richard Fitzgerald 2022-11-11 23:07 ` kernel test robot 2022-11-11 23:07 ` kernel test robot 2022-11-16 15:43 ` Lee Jones 2022-11-16 15:43 ` Lee Jones 2022-11-09 16:53 ` [PATCH 04/12] dt-bindings: pinctrl: Add Cirrus Logic CS48L31/32/33 Richard Fitzgerald 2022-11-09 16:53 ` Richard Fitzgerald 2022-11-09 21:09 ` Rob Herring 2022-11-09 21:09 ` Rob Herring 2022-11-14 8:39 ` Krzysztof Kozlowski 2022-11-14 8:39 ` Krzysztof Kozlowski 2022-11-09 16:53 ` [PATCH 05/12] pinctrl: cirrus: Add support for CS48L31/32/33 codecs Richard Fitzgerald 2022-11-09 16:53 ` Richard Fitzgerald 2022-11-10 10:02 ` Linus Walleij 2022-11-10 10:02 ` Linus Walleij 2022-11-10 10:55 ` Richard Fitzgerald 2022-11-10 10:55 ` Richard Fitzgerald 2022-11-12 21:01 ` kernel test robot 2022-11-12 21:01 ` kernel test robot 2022-11-09 16:53 ` [PATCH 06/12] regulator: arizona-micsupp: Don't hardcode use of ARIZONA defines Richard Fitzgerald 2022-11-09 16:53 ` Richard Fitzgerald 2022-11-09 16:53 ` [PATCH 07/12] regulator: arizona-micsupp: Don't use a common regulator name Richard Fitzgerald 2022-11-09 16:53 ` Richard Fitzgerald 2022-11-09 16:53 ` [PATCH 08/12] regulator: arizona-micsupp: Support Cirrus Logic CS48L31/32/33 Richard Fitzgerald 2022-11-09 16:53 ` Richard Fitzgerald 2022-11-09 16:53 ` [PATCH 09/12] irqchip: cirrus: Add driver for Cirrus Logic CS48L31/32/33 codecs Richard Fitzgerald 2022-11-09 16:53 ` Richard Fitzgerald 2022-11-10 8:02 ` Marc Zyngier 2022-11-10 8:02 ` Marc Zyngier 2022-11-10 11:22 ` Richard Fitzgerald 2022-11-10 11:22 ` Richard Fitzgerald 2022-11-10 12:01 ` Marc Zyngier 2022-11-10 12:01 ` Marc Zyngier 2022-11-10 13:00 ` Richard Fitzgerald 2022-11-10 13:00 ` Richard Fitzgerald 2022-11-10 15:13 ` Marc Zyngier 2022-11-10 15:13 ` Marc Zyngier 2022-11-10 16:31 ` Richard Fitzgerald 2022-11-10 16:31 ` Richard Fitzgerald 2022-11-10 16:55 ` Mark Brown 2022-11-10 16:55 ` Mark Brown 2022-11-10 18:47 ` Marc Zyngier 2022-11-10 18:47 ` Marc Zyngier 2022-11-10 20:36 ` Mark Brown 2022-11-10 20:36 ` Mark Brown 2022-11-11 8:00 ` Marc Zyngier 2022-11-11 8:00 ` Marc Zyngier 2022-11-11 11:16 ` Charles Keepax 2022-11-11 11:16 ` Charles Keepax 2022-11-11 11:49 ` Mark Brown 2022-11-11 11:49 ` Mark Brown 2022-11-11 13:01 ` Charles Keepax 2022-11-11 13:01 ` Charles Keepax 2022-11-11 13:00 ` Charles Keepax 2022-11-11 13:00 ` Charles Keepax 2022-11-16 16:44 ` Mark Brown 2022-11-16 16:44 ` Mark Brown 2022-11-10 13:14 ` Richard Fitzgerald 2022-11-10 13:14 ` Richard Fitzgerald 2022-11-10 15:40 ` Marc Zyngier 2022-11-10 15:40 ` Marc Zyngier 2022-11-10 13:01 ` Mark Brown 2022-11-10 13:01 ` Mark Brown 2022-11-09 16:53 ` [PATCH 10/12] ASoC: wm_adsp: Allow client to hook into pre_run callback Richard Fitzgerald 2022-11-09 16:53 ` Richard Fitzgerald 2022-11-09 16:53 ` [PATCH 11/12] dt-bindings: sound: Add Cirrus Logic CS48L31/32/33 codecs Richard Fitzgerald 2022-11-09 16:53 ` Richard Fitzgerald 2022-11-09 21:09 ` Rob Herring 2022-11-09 21:09 ` Rob Herring 2022-11-14 8:45 ` Krzysztof Kozlowski 2022-11-14 8:45 ` Krzysztof Kozlowski 2022-11-14 11:00 ` Richard Fitzgerald 2022-11-14 11:00 ` Richard Fitzgerald 2022-11-14 11:03 ` Krzysztof Kozlowski 2022-11-14 11:03 ` Krzysztof Kozlowski 2022-11-14 12:34 ` Richard Fitzgerald 2022-11-14 12:34 ` Richard Fitzgerald 2022-11-09 16:53 ` [PATCH 12/12] ASoC: cs48l32: Add codec driver for Cirrus Logic CS48L31/32/33 Richard Fitzgerald 2022-11-09 16:53 ` Richard Fitzgerald 2022-11-10 20:20 ` kernel test robot 2022-11-10 20:20 ` kernel test robot 2022-11-10 20:53 ` [PATCH 00/12] Add support for the Cirrus Logic CS48L32 audio codecs Mark Brown 2022-11-10 20:53 ` Mark Brown 2022-11-11 13:50 ` Richard Fitzgerald 2022-11-11 13:50 ` Richard Fitzgerald 2022-11-23 13:11 ` (subset) " Mark Brown 2022-11-23 13:11 ` Mark Brown
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