From: Vyacheslav Bocharov <adeep@lexina.in>
To: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 2/4] arm64: amlogic: mmc: meson-gx: Add dts binding include for core, tx, rx eMMC/SD/SDIO phase clock settings from devicetree data
Date: Thu, 10 Nov 2022 18:00:33 +0300 [thread overview]
Message-ID: <20221110150035.2824580-3-adeep@lexina.in> (raw)
In-Reply-To: <20221110150035.2824580-1-adeep@lexina.in>
The mmc driver has the same phase values for all meson platforms. However,
some platforms (and even some boards) require different values. This patch
transfers the values from the set in the code to the variables in the
device-tree file.
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
create mode 100644 include/dt-bindings/mmc/meson-gx-mmc.h
diff --git a/include/dt-bindings/mmc/meson-gx-mmc.h b/include/dt-bindings/mmc/meson-gx-mmc.h
new file mode 100644
index 000000000000..cfc4a9d75b2b
--- /dev/null
+++ b/include/dt-bindings/mmc/meson-gx-mmc.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2022 JetHome, Vyacheslav Bocharov
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ */
+
+#ifndef _DT_BINDINGS_MESON_GX_MMC_H
+#define _DT_BINDINGS_MESON_GX_MMC_H
+
+/*
+ * Cfg_rx_phase: RX clock phase
+ * bits: 9:8 R/W
+ * default: 0
+ * Recommended value: 0
+ *
+ * Cfg_tx_phase: TX clock phase
+ * bits: 9:8 R/W
+ * default: 0
+ * Recommended value: 2
+ *
+ * Cfg_co_phase: Core clock phase
+ * bits: 9:8 R/W
+ * default: 0
+ * Recommended value: 2
+ *
+ * values: 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.
+ */
+
+#define CLK_PHASE_0 0
+#define CLK_PHASE_90 1
+#define CLK_PHASE_180 2
+#define CLK_PHASE_270 3
+
+
+#endif
--
2.30.2
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Vyacheslav Bocharov <adeep@lexina.in>
To: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 2/4] arm64: amlogic: mmc: meson-gx: Add dts binding include for core, tx, rx eMMC/SD/SDIO phase clock settings from devicetree data
Date: Thu, 10 Nov 2022 18:00:33 +0300 [thread overview]
Message-ID: <20221110150035.2824580-3-adeep@lexina.in> (raw)
In-Reply-To: <20221110150035.2824580-1-adeep@lexina.in>
The mmc driver has the same phase values for all meson platforms. However,
some platforms (and even some boards) require different values. This patch
transfers the values from the set in the code to the variables in the
device-tree file.
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
create mode 100644 include/dt-bindings/mmc/meson-gx-mmc.h
diff --git a/include/dt-bindings/mmc/meson-gx-mmc.h b/include/dt-bindings/mmc/meson-gx-mmc.h
new file mode 100644
index 000000000000..cfc4a9d75b2b
--- /dev/null
+++ b/include/dt-bindings/mmc/meson-gx-mmc.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2022 JetHome, Vyacheslav Bocharov
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ */
+
+#ifndef _DT_BINDINGS_MESON_GX_MMC_H
+#define _DT_BINDINGS_MESON_GX_MMC_H
+
+/*
+ * Cfg_rx_phase: RX clock phase
+ * bits: 9:8 R/W
+ * default: 0
+ * Recommended value: 0
+ *
+ * Cfg_tx_phase: TX clock phase
+ * bits: 9:8 R/W
+ * default: 0
+ * Recommended value: 2
+ *
+ * Cfg_co_phase: Core clock phase
+ * bits: 9:8 R/W
+ * default: 0
+ * Recommended value: 2
+ *
+ * values: 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.
+ */
+
+#define CLK_PHASE_0 0
+#define CLK_PHASE_90 1
+#define CLK_PHASE_180 2
+#define CLK_PHASE_270 3
+
+
+#endif
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Vyacheslav Bocharov <adeep@lexina.in>
To: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 2/4] arm64: amlogic: mmc: meson-gx: Add dts binding include for core, tx, rx eMMC/SD/SDIO phase clock settings from devicetree data
Date: Thu, 10 Nov 2022 18:00:33 +0300 [thread overview]
Message-ID: <20221110150035.2824580-3-adeep@lexina.in> (raw)
In-Reply-To: <20221110150035.2824580-1-adeep@lexina.in>
The mmc driver has the same phase values for all meson platforms. However,
some platforms (and even some boards) require different values. This patch
transfers the values from the set in the code to the variables in the
device-tree file.
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
create mode 100644 include/dt-bindings/mmc/meson-gx-mmc.h
diff --git a/include/dt-bindings/mmc/meson-gx-mmc.h b/include/dt-bindings/mmc/meson-gx-mmc.h
new file mode 100644
index 000000000000..cfc4a9d75b2b
--- /dev/null
+++ b/include/dt-bindings/mmc/meson-gx-mmc.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2022 JetHome, Vyacheslav Bocharov
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ */
+
+#ifndef _DT_BINDINGS_MESON_GX_MMC_H
+#define _DT_BINDINGS_MESON_GX_MMC_H
+
+/*
+ * Cfg_rx_phase: RX clock phase
+ * bits: 9:8 R/W
+ * default: 0
+ * Recommended value: 0
+ *
+ * Cfg_tx_phase: TX clock phase
+ * bits: 9:8 R/W
+ * default: 0
+ * Recommended value: 2
+ *
+ * Cfg_co_phase: Core clock phase
+ * bits: 9:8 R/W
+ * default: 0
+ * Recommended value: 2
+ *
+ * values: 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.
+ */
+
+#define CLK_PHASE_0 0
+#define CLK_PHASE_90 1
+#define CLK_PHASE_180 2
+#define CLK_PHASE_270 3
+
+
+#endif
--
2.30.2
next prev parent reply other threads:[~2022-11-10 15:01 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-10 15:00 [PATCH 0/4] arm64: amlogic: mmc: meson-gx: Add core, tx, rx Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-10 15:00 ` [PATCH 1/4] arm64: amlogic: mmc: meson-gx: Add core, tx, rx eMMC/SD/SDIO phase clock settings from devicetree data Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-12 22:57 ` Martin Blumenstingl
2022-11-12 22:57 ` Martin Blumenstingl
2022-11-12 22:57 ` Martin Blumenstingl
2022-11-10 15:00 ` Vyacheslav Bocharov [this message]
2022-11-10 15:00 ` [PATCH 2/4] arm64: amlogic: mmc: meson-gx: Add dts binding include for " Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-12 22:59 ` Martin Blumenstingl
2022-11-12 22:59 ` Martin Blumenstingl
2022-11-12 22:59 ` Martin Blumenstingl
2022-11-10 15:00 ` [PATCH 3/4] arm64: amlogic: dts: meson: update meson-axg device-tree for new core, tx, rx phase clock settings Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-10 15:00 ` [PATCH 4/4] arm64: dts: docs: Update mmc meson-gx documentation for new config option amlogic,mmc-phase Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-10 15:00 ` Vyacheslav Bocharov
2022-11-12 23:01 ` Martin Blumenstingl
2022-11-12 23:01 ` Martin Blumenstingl
2022-11-12 23:01 ` Martin Blumenstingl
2022-11-23 16:23 ` Krzysztof Kozlowski
2022-11-23 16:23 ` Krzysztof Kozlowski
2022-11-23 16:23 ` Krzysztof Kozlowski
2022-11-13 20:06 ` [PATCH 0/4] arm64: amlogic: mmc: meson-gx: Add core, tx, rx Jerome Brunet
2022-11-13 20:06 ` Jerome Brunet
2022-11-13 20:06 ` Jerome Brunet
2022-11-24 6:22 ` Vyacheslav
2022-11-24 6:22 ` Vyacheslav
2022-11-24 6:22 ` Vyacheslav
2022-11-25 10:28 ` Jerome Brunet
2022-11-25 10:28 ` Jerome Brunet
2022-11-25 10:28 ` Jerome Brunet
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