From: Adam Skladowski <a39.skl@gmail.com> Cc: "Rafael J. Wysocki" <rafael@kernel.org>, Amit Kucheria <amitk@kernel.org>, dri-devel@lists.freedesktop.org, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, phone-devel@vger.kernel.org, Daniel Lezcano <daniel.lezcano@linaro.org>, Andy Gross <agross@kernel.org>, Zhang Rui <rui.zhang@intel.com>, devicetree@vger.kernel.org, Thara Gopinath <thara.gopinath@gmail.com>, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, Adam Skladowski <a39.skl@gmail.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Rob Herring <robh+dt@kernel.org>, ~postmarketos/upstreaming@lists.sr.ht, Sean Paul <sean@poorly.run>, Loic Poulain <loic.poulain@linaro.org>, Bjorn Andersson <andersson@kernel.org>, linux-kernel@vger.kernel.org, Konrad Dybcio <konrad.dybcio@linaro.org>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, freedreno@lists.freedesktop.org Subject: [PATCH v2 03/12] arm64: dts: qcom: sm6115: Add cpufreq-hw support Date: Wed, 30 Nov 2022 21:09:41 +0100 [thread overview] Message-ID: <20221130200950.144618-4-a39.skl@gmail.com> (raw) In-Reply-To: <20221130200950.144618-1-a39.skl@gmail.com> Add cpufreq-hw node and assign qcom,freq-domain properties to CPUs to enable CPU clock scaling. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 0340ed21be05..2a55087b103e 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -41,6 +41,7 @@ CPU0: cpu@0 { dynamic-power-coefficient = <100>; enable-method = "psci"; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -55,6 +56,7 @@ CPU1: cpu@1 { dynamic-power-coefficient = <100>; enable-method = "psci"; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; }; CPU2: cpu@2 { @@ -65,6 +67,7 @@ CPU2: cpu@2 { dynamic-power-coefficient = <100>; enable-method = "psci"; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; }; CPU3: cpu@3 { @@ -75,6 +78,7 @@ CPU3: cpu@3 { dynamic-power-coefficient = <100>; enable-method = "psci"; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; }; CPU4: cpu@100 { @@ -85,6 +89,7 @@ CPU4: cpu@100 { capacity-dmips-mhz = <1638>; dynamic-power-coefficient = <282>; next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1>; L2_1: l2-cache { compatible = "cache"; cache-level = <2>; @@ -99,6 +104,7 @@ CPU5: cpu@101 { dynamic-power-coefficient = <282>; enable-method = "psci"; next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1>; }; CPU6: cpu@102 { @@ -109,6 +115,7 @@ CPU6: cpu@102 { dynamic-power-coefficient = <282>; enable-method = "psci"; next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1>; }; CPU7: cpu@103 { @@ -119,6 +126,7 @@ CPU7: cpu@103 { dynamic-power-coefficient = <282>; enable-method = "psci"; next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1>; }; cpu-map { @@ -842,6 +850,17 @@ intc: interrupt-controller@f200000 { redistributor-stride = <0x0 0x20000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; + + cpufreq_hw: cpufreq@f521000 { + compatible = "qcom,cpufreq-hw"; + reg = <0x0f521000 0x1000>, <0x0f523000 0x1000>; + + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; }; timer { -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Adam Skladowski <a39.skl@gmail.com> To: unlisted-recipients:; (no To-header on input) Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski <a39.skl@gmail.com>, Rob Clark <robdclark@gmail.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Amit Kucheria <amitk@kernel.org>, Thara Gopinath <thara.gopinath@gmail.com>, "Rafael J. Wysocki" <rafael@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Zhang Rui <rui.zhang@intel.com>, Loic Poulain <loic.poulain@linaro.org>, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 03/12] arm64: dts: qcom: sm6115: Add cpufreq-hw support Date: Wed, 30 Nov 2022 21:09:41 +0100 [thread overview] Message-ID: <20221130200950.144618-4-a39.skl@gmail.com> (raw) In-Reply-To: <20221130200950.144618-1-a39.skl@gmail.com> Add cpufreq-hw node and assign qcom,freq-domain properties to CPUs to enable CPU clock scaling. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 0340ed21be05..2a55087b103e 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -41,6 +41,7 @@ CPU0: cpu@0 { dynamic-power-coefficient = <100>; enable-method = "psci"; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -55,6 +56,7 @@ CPU1: cpu@1 { dynamic-power-coefficient = <100>; enable-method = "psci"; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; }; CPU2: cpu@2 { @@ -65,6 +67,7 @@ CPU2: cpu@2 { dynamic-power-coefficient = <100>; enable-method = "psci"; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; }; CPU3: cpu@3 { @@ -75,6 +78,7 @@ CPU3: cpu@3 { dynamic-power-coefficient = <100>; enable-method = "psci"; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; }; CPU4: cpu@100 { @@ -85,6 +89,7 @@ CPU4: cpu@100 { capacity-dmips-mhz = <1638>; dynamic-power-coefficient = <282>; next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1>; L2_1: l2-cache { compatible = "cache"; cache-level = <2>; @@ -99,6 +104,7 @@ CPU5: cpu@101 { dynamic-power-coefficient = <282>; enable-method = "psci"; next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1>; }; CPU6: cpu@102 { @@ -109,6 +115,7 @@ CPU6: cpu@102 { dynamic-power-coefficient = <282>; enable-method = "psci"; next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1>; }; CPU7: cpu@103 { @@ -119,6 +126,7 @@ CPU7: cpu@103 { dynamic-power-coefficient = <282>; enable-method = "psci"; next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1>; }; cpu-map { @@ -842,6 +850,17 @@ intc: interrupt-controller@f200000 { redistributor-stride = <0x0 0x20000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; + + cpufreq_hw: cpufreq@f521000 { + compatible = "qcom,cpufreq-hw"; + reg = <0x0f521000 0x1000>, <0x0f523000 0x1000>; + + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; }; timer { -- 2.25.1
next prev parent reply other threads:[~2022-11-30 20:10 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-30 20:09 [PATCH v2 00/12] SM6115 DTS changes Adam Skladowski 2022-11-30 20:09 ` Adam Skladowski 2022-11-30 20:09 ` [PATCH v2 01/12] dt-bindings: display: msm: Rename mdss node name in example Adam Skladowski 2022-11-30 20:09 ` Adam Skladowski 2022-12-01 10:37 ` Krzysztof Kozlowski 2022-12-01 10:37 ` Krzysztof Kozlowski 2022-12-01 19:54 ` Dmitry Baryshkov 2022-12-01 19:54 ` Dmitry Baryshkov 2022-12-13 21:53 ` Abhinav Kumar 2022-12-13 21:53 ` Abhinav Kumar 2022-12-13 22:11 ` Dmitry Baryshkov 2022-12-13 22:11 ` Dmitry Baryshkov 2022-12-13 22:15 ` Abhinav Kumar 2022-12-13 22:15 ` Abhinav Kumar 2022-12-14 9:40 ` Dmitry Baryshkov 2022-12-14 9:40 ` Dmitry Baryshkov 2022-11-30 20:09 ` [PATCH v2 02/12] dt-bindings: thermal: tsens: Add SM6115 compatible Adam Skladowski 2022-11-30 20:09 ` Adam Skladowski 2022-12-01 19:40 ` Rob Herring 2022-12-01 19:40 ` Rob Herring 2022-11-30 20:09 ` Adam Skladowski [this message] 2022-11-30 20:09 ` [PATCH v2 03/12] arm64: dts: qcom: sm6115: Add cpufreq-hw support Adam Skladowski 2022-11-30 20:09 ` [PATCH v2 04/12] arm64: dts: qcom: sm6115: Add TSENS node Adam Skladowski 2022-11-30 20:09 ` Adam Skladowski 2022-11-30 20:09 ` [PATCH v2 05/12] arm64: dts: qcom: sm6115: Add PRNG node Adam Skladowski 2022-11-30 20:09 ` Adam Skladowski 2022-11-30 20:09 ` [PATCH v2 06/12] arm64: dts: qcom: sm6115: Add rpm-stats node Adam Skladowski 2022-11-30 20:09 ` Adam Skladowski 2022-11-30 20:09 ` [PATCH v2 07/12] arm64: dts: qcom: sm6115: Add dispcc node Adam Skladowski 2022-11-30 20:09 ` Adam Skladowski 2022-11-30 20:09 ` [PATCH v2 08/12] arm64: dts: qcom: sm6115: Add mdss/dpu node Adam Skladowski 2022-11-30 20:09 ` Adam Skladowski 2022-11-30 20:09 ` [PATCH v2 09/12] arm64: dts: qcom: sm6115: Add GPI DMA Adam Skladowski 2022-11-30 20:09 ` Adam Skladowski 2022-11-30 20:09 ` [PATCH v2 10/12] arm64: dts: qcom: sm6115: Add i2c/spi nodes Adam Skladowski 2022-11-30 20:09 ` Adam Skladowski 2022-12-02 10:51 ` Konrad Dybcio 2022-12-02 10:51 ` Konrad Dybcio 2022-11-30 20:09 ` [PATCH v2 11/12] arm64: dts: qcom: sm6115: Add WCN node Adam Skladowski 2022-11-30 20:09 ` Adam Skladowski 2022-12-01 10:38 ` Krzysztof Kozlowski 2022-12-01 10:38 ` Krzysztof Kozlowski 2022-12-05 22:49 ` Bjorn Andersson 2022-12-05 22:49 ` Bjorn Andersson 2022-11-30 20:09 ` [PATCH v2 12/12] arm64: dts: qcom: sm6115: Add smmu fallback to qcom generic compatible Adam Skladowski 2022-11-30 20:09 ` Adam Skladowski 2022-12-02 10:52 ` Konrad Dybcio 2022-12-02 10:52 ` Konrad Dybcio 2022-12-06 18:18 ` (subset) [PATCH v2 00/12] SM6115 DTS changes Bjorn Andersson 2022-12-06 18:18 ` Bjorn Andersson
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