From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: martin.petersen@oracle.com, jejb@linux.ibm.com,
andersson@kernel.org, vkoul@kernel.org
Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org,
dmitry.baryshkov@linaro.org, ahalaney@redhat.com,
abel.vesa@linaro.org, alim.akhtar@samsung.com,
avri.altman@wdc.com, bvanassche@acm.org,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v4 03/23] phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls struct
Date: Thu, 1 Dec 2022 23:13:08 +0530 [thread overview]
Message-ID: <20221201174328.870152-4-manivannan.sadhasivam@linaro.org> (raw)
In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org>
As done for Qcom PCIe PHY driver, let's move the register settings to the
common qmp_phy_cfg_tbls struct. This helps in adding any additional PHY
settings needed for functionalities like HS-G4 in the future by adding one
more instance of the qmp_phy_cfg_tbls.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 196 ++++++++++++++----------
1 file changed, 113 insertions(+), 83 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 35b77cd79e57..516027e356f0 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -527,21 +527,26 @@ struct qmp_ufs_offsets {
u16 rx2;
};
+struct qmp_phy_cfg_tbls {
+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
+ const struct qmp_phy_init_tbl *serdes;
+ int serdes_num;
+ const struct qmp_phy_init_tbl *tx;
+ int tx_num;
+ const struct qmp_phy_init_tbl *rx;
+ int rx_num;
+ const struct qmp_phy_init_tbl *pcs;
+ int pcs_num;
+};
+
/* struct qmp_phy_cfg - per-PHY initialization config */
struct qmp_phy_cfg {
int lanes;
const struct qmp_ufs_offsets *offsets;
- /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
- const struct qmp_phy_init_tbl *serdes_tbl;
- int serdes_tbl_num;
- const struct qmp_phy_init_tbl *tx_tbl;
- int tx_tbl_num;
- const struct qmp_phy_init_tbl *rx_tbl;
- int rx_tbl_num;
- const struct qmp_phy_init_tbl *pcs_tbl;
- int pcs_tbl_num;
+ /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
+ const struct qmp_phy_cfg_tbls tbls;
/* clock ids to be requested */
const char * const *clk_list;
@@ -632,12 +637,14 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
.lanes = 1,
- .serdes_tbl = msm8996_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(msm8996_ufsphy_serdes),
- .tx_tbl = msm8996_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_tx),
- .rx_tbl = msm8996_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_rx),
+ .tbls = {
+ .serdes = msm8996_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes),
+ .tx = msm8996_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(msm8996_ufsphy_tx),
+ .rx = msm8996_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(msm8996_ufsphy_rx),
+ },
.clk_list = msm8996_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
@@ -655,14 +662,16 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.offsets = &qmp_ufs_offsets_v5,
- .serdes_tbl = sm8350_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
- .tx_tbl = sm8350_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
- .rx_tbl = sm8350_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
- .pcs_tbl = sm8350_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ .tbls = {
+ .serdes = sm8350_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
+ .tx = sm8350_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
+ .rx = sm8350_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
+ .pcs = sm8350_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -673,14 +682,16 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
.lanes = 2,
- .serdes_tbl = sdm845_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
- .tx_tbl = sdm845_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx),
- .rx_tbl = sdm845_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx),
- .pcs_tbl = sdm845_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
+ .tbls = {
+ .serdes = sdm845_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
+ .tx = sdm845_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx),
+ .rx = sdm845_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sdm845_ufsphy_rx),
+ .pcs = sdm845_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -693,14 +704,16 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
.lanes = 1,
- .serdes_tbl = sm6115_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
- .tx_tbl = sm6115_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx),
- .rx_tbl = sm6115_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx),
- .pcs_tbl = sm6115_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
+ .tbls = {
+ .serdes = sm6115_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
+ .tx = sm6115_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm6115_ufsphy_tx),
+ .rx = sm6115_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm6115_ufsphy_rx),
+ .pcs = sm6115_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -713,14 +726,16 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.lanes = 2,
- .serdes_tbl = sm8150_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
- .tx_tbl = sm8150_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx),
- .rx_tbl = sm8150_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx),
- .pcs_tbl = sm8150_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
+ .tbls = {
+ .serdes = sm8150_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
+ .tx = sm8150_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
+ .rx = sm8150_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
+ .pcs = sm8150_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -731,14 +746,16 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.lanes = 2,
- .serdes_tbl = sm8350_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
- .tx_tbl = sm8350_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
- .rx_tbl = sm8350_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
- .pcs_tbl = sm8350_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ .tbls = {
+ .serdes = sm8350_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
+ .tx = sm8350_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
+ .rx = sm8350_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
+ .pcs = sm8350_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -749,14 +766,16 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.lanes = 2,
- .serdes_tbl = sm8350_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
- .tx_tbl = sm8350_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
- .rx_tbl = sm8350_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
- .pcs_tbl = sm8350_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ .tbls = {
+ .serdes = sm8350_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
+ .tx = sm8350_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
+ .rx = sm8350_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
+ .pcs = sm8350_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ },
.clk_list = sm8450_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -790,16 +809,40 @@ static void qmp_ufs_configure(void __iomem *base,
qmp_ufs_configure_lane(base, tbl, num, 0xff);
}
-static int qmp_ufs_serdes_init(struct qmp_ufs *qmp)
+static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
{
- const struct qmp_phy_cfg *cfg = qmp->cfg;
void __iomem *serdes = qmp->serdes;
- const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
- int serdes_tbl_num = cfg->serdes_tbl_num;
- qmp_ufs_configure(serdes, serdes_tbl, serdes_tbl_num);
+ qmp_ufs_configure(serdes, tbls->serdes, tbls->serdes_num);
+}
- return 0;
+static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
+{
+ const struct qmp_phy_cfg *cfg = qmp->cfg;
+ void __iomem *tx = qmp->tx;
+ void __iomem *rx = qmp->rx;
+
+ qmp_ufs_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
+ qmp_ufs_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
+
+ if (cfg->lanes >= 2) {
+ qmp_ufs_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2);
+ qmp_ufs_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2);
+ }
+}
+
+static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
+{
+ void __iomem *pcs = qmp->pcs;
+
+ qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num);
+}
+
+static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
+{
+ qmp_ufs_serdes_init(qmp, &cfg->tbls);
+ qmp_ufs_lanes_init(qmp, &cfg->tbls);
+ qmp_ufs_pcs_init(qmp, &cfg->tbls);
}
static int qmp_ufs_com_init(struct qmp_ufs *qmp)
@@ -886,25 +929,12 @@ static int qmp_ufs_power_on(struct phy *phy)
{
struct qmp_ufs *qmp = phy_get_drvdata(phy);
const struct qmp_phy_cfg *cfg = qmp->cfg;
- void __iomem *tx = qmp->tx;
- void __iomem *rx = qmp->rx;
void __iomem *pcs = qmp->pcs;
void __iomem *status;
unsigned int val;
int ret;
- qmp_ufs_serdes_init(qmp);
-
- /* Tx, Rx, and PCS configurations */
- qmp_ufs_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
- qmp_ufs_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
-
- if (cfg->lanes >= 2) {
- qmp_ufs_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
- qmp_ufs_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
- }
-
- qmp_ufs_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
+ qmp_ufs_init_registers(qmp, cfg);
ret = reset_control_deassert(qmp->ufs_reset);
if (ret)
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: martin.petersen@oracle.com, jejb@linux.ibm.com,
andersson@kernel.org, vkoul@kernel.org
Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org,
dmitry.baryshkov@linaro.org, ahalaney@redhat.com,
abel.vesa@linaro.org, alim.akhtar@samsung.com,
avri.altman@wdc.com, bvanassche@acm.org,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v4 03/23] phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls struct
Date: Thu, 1 Dec 2022 23:13:08 +0530 [thread overview]
Message-ID: <20221201174328.870152-4-manivannan.sadhasivam@linaro.org> (raw)
In-Reply-To: <20221201174328.870152-1-manivannan.sadhasivam@linaro.org>
As done for Qcom PCIe PHY driver, let's move the register settings to the
common qmp_phy_cfg_tbls struct. This helps in adding any additional PHY
settings needed for functionalities like HS-G4 in the future by adding one
more instance of the qmp_phy_cfg_tbls.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 196 ++++++++++++++----------
1 file changed, 113 insertions(+), 83 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 35b77cd79e57..516027e356f0 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -527,21 +527,26 @@ struct qmp_ufs_offsets {
u16 rx2;
};
+struct qmp_phy_cfg_tbls {
+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
+ const struct qmp_phy_init_tbl *serdes;
+ int serdes_num;
+ const struct qmp_phy_init_tbl *tx;
+ int tx_num;
+ const struct qmp_phy_init_tbl *rx;
+ int rx_num;
+ const struct qmp_phy_init_tbl *pcs;
+ int pcs_num;
+};
+
/* struct qmp_phy_cfg - per-PHY initialization config */
struct qmp_phy_cfg {
int lanes;
const struct qmp_ufs_offsets *offsets;
- /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
- const struct qmp_phy_init_tbl *serdes_tbl;
- int serdes_tbl_num;
- const struct qmp_phy_init_tbl *tx_tbl;
- int tx_tbl_num;
- const struct qmp_phy_init_tbl *rx_tbl;
- int rx_tbl_num;
- const struct qmp_phy_init_tbl *pcs_tbl;
- int pcs_tbl_num;
+ /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
+ const struct qmp_phy_cfg_tbls tbls;
/* clock ids to be requested */
const char * const *clk_list;
@@ -632,12 +637,14 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
.lanes = 1,
- .serdes_tbl = msm8996_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(msm8996_ufsphy_serdes),
- .tx_tbl = msm8996_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_tx),
- .rx_tbl = msm8996_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_rx),
+ .tbls = {
+ .serdes = msm8996_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes),
+ .tx = msm8996_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(msm8996_ufsphy_tx),
+ .rx = msm8996_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(msm8996_ufsphy_rx),
+ },
.clk_list = msm8996_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
@@ -655,14 +662,16 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.offsets = &qmp_ufs_offsets_v5,
- .serdes_tbl = sm8350_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
- .tx_tbl = sm8350_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
- .rx_tbl = sm8350_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
- .pcs_tbl = sm8350_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ .tbls = {
+ .serdes = sm8350_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
+ .tx = sm8350_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
+ .rx = sm8350_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
+ .pcs = sm8350_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -673,14 +682,16 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
.lanes = 2,
- .serdes_tbl = sdm845_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
- .tx_tbl = sdm845_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx),
- .rx_tbl = sdm845_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx),
- .pcs_tbl = sdm845_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
+ .tbls = {
+ .serdes = sdm845_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
+ .tx = sdm845_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx),
+ .rx = sdm845_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sdm845_ufsphy_rx),
+ .pcs = sdm845_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -693,14 +704,16 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
.lanes = 1,
- .serdes_tbl = sm6115_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
- .tx_tbl = sm6115_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx),
- .rx_tbl = sm6115_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx),
- .pcs_tbl = sm6115_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
+ .tbls = {
+ .serdes = sm6115_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
+ .tx = sm6115_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm6115_ufsphy_tx),
+ .rx = sm6115_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm6115_ufsphy_rx),
+ .pcs = sm6115_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -713,14 +726,16 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.lanes = 2,
- .serdes_tbl = sm8150_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
- .tx_tbl = sm8150_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx),
- .rx_tbl = sm8150_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx),
- .pcs_tbl = sm8150_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
+ .tbls = {
+ .serdes = sm8150_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
+ .tx = sm8150_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
+ .rx = sm8150_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
+ .pcs = sm8150_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -731,14 +746,16 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.lanes = 2,
- .serdes_tbl = sm8350_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
- .tx_tbl = sm8350_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
- .rx_tbl = sm8350_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
- .pcs_tbl = sm8350_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ .tbls = {
+ .serdes = sm8350_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
+ .tx = sm8350_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
+ .rx = sm8350_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
+ .pcs = sm8350_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -749,14 +766,16 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.lanes = 2,
- .serdes_tbl = sm8350_ufsphy_serdes,
- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
- .tx_tbl = sm8350_ufsphy_tx,
- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
- .rx_tbl = sm8350_ufsphy_rx,
- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
- .pcs_tbl = sm8350_ufsphy_pcs,
- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ .tbls = {
+ .serdes = sm8350_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
+ .tx = sm8350_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
+ .rx = sm8350_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
+ .pcs = sm8350_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
+ },
.clk_list = sm8450_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -790,16 +809,40 @@ static void qmp_ufs_configure(void __iomem *base,
qmp_ufs_configure_lane(base, tbl, num, 0xff);
}
-static int qmp_ufs_serdes_init(struct qmp_ufs *qmp)
+static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
{
- const struct qmp_phy_cfg *cfg = qmp->cfg;
void __iomem *serdes = qmp->serdes;
- const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
- int serdes_tbl_num = cfg->serdes_tbl_num;
- qmp_ufs_configure(serdes, serdes_tbl, serdes_tbl_num);
+ qmp_ufs_configure(serdes, tbls->serdes, tbls->serdes_num);
+}
- return 0;
+static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
+{
+ const struct qmp_phy_cfg *cfg = qmp->cfg;
+ void __iomem *tx = qmp->tx;
+ void __iomem *rx = qmp->rx;
+
+ qmp_ufs_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
+ qmp_ufs_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
+
+ if (cfg->lanes >= 2) {
+ qmp_ufs_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2);
+ qmp_ufs_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2);
+ }
+}
+
+static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
+{
+ void __iomem *pcs = qmp->pcs;
+
+ qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num);
+}
+
+static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
+{
+ qmp_ufs_serdes_init(qmp, &cfg->tbls);
+ qmp_ufs_lanes_init(qmp, &cfg->tbls);
+ qmp_ufs_pcs_init(qmp, &cfg->tbls);
}
static int qmp_ufs_com_init(struct qmp_ufs *qmp)
@@ -886,25 +929,12 @@ static int qmp_ufs_power_on(struct phy *phy)
{
struct qmp_ufs *qmp = phy_get_drvdata(phy);
const struct qmp_phy_cfg *cfg = qmp->cfg;
- void __iomem *tx = qmp->tx;
- void __iomem *rx = qmp->rx;
void __iomem *pcs = qmp->pcs;
void __iomem *status;
unsigned int val;
int ret;
- qmp_ufs_serdes_init(qmp);
-
- /* Tx, Rx, and PCS configurations */
- qmp_ufs_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
- qmp_ufs_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
-
- if (cfg->lanes >= 2) {
- qmp_ufs_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
- qmp_ufs_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
- }
-
- qmp_ufs_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
+ qmp_ufs_init_registers(qmp, cfg);
ret = reset_control_deassert(qmp->ufs_reset);
if (ret)
--
2.25.1
--
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next prev parent reply other threads:[~2022-12-01 17:44 UTC|newest]
Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-01 17:43 [PATCH v4 00/23] ufs: qcom: Add HS-G4 support Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-01 17:43 ` [PATCH v4 01/23] phy: qcom-qmp-ufs: Remove _tbl suffix from qmp_phy_init_tbl definitions Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-05 21:45 ` Dmitry Baryshkov
2022-12-05 21:45 ` Dmitry Baryshkov
2022-12-01 17:43 ` [PATCH v4 02/23] phy: qcom-qmp-ufs: Rename MSM8996 PHY definitions Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-05 21:46 ` Dmitry Baryshkov
2022-12-05 21:46 ` Dmitry Baryshkov
2022-12-01 17:43 ` Manivannan Sadhasivam [this message]
2022-12-01 17:43 ` [PATCH v4 03/23] phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls struct Manivannan Sadhasivam
2022-12-05 21:48 ` Dmitry Baryshkov
2022-12-05 21:48 ` Dmitry Baryshkov
2022-12-01 17:43 ` [PATCH v4 04/23] phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-05 21:51 ` Dmitry Baryshkov
2022-12-05 21:51 ` Dmitry Baryshkov
2022-12-06 7:12 ` Manivannan Sadhasivam
2022-12-06 7:12 ` Manivannan Sadhasivam
2022-12-01 17:43 ` [PATCH v4 05/23] phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-01 17:43 ` [PATCH v4 06/23] phy: qcom-qmp-ufs: Move HS Rate B register setting to tbls_hs_b Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-01 17:43 ` [PATCH v4 07/23] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8150 SoC Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-05 21:52 ` Dmitry Baryshkov
2022-12-05 21:52 ` Dmitry Baryshkov
2022-12-01 17:43 ` [PATCH v4 08/23] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-05 21:52 ` Dmitry Baryshkov
2022-12-05 21:52 ` Dmitry Baryshkov
2022-12-01 17:43 ` [PATCH v4 09/23] phy: qcom-qmp-ufs: Avoid setting HS G3 specific registers Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-05 21:55 ` Dmitry Baryshkov
2022-12-05 21:55 ` Dmitry Baryshkov
2022-12-06 7:16 ` Manivannan Sadhasivam
2022-12-06 7:16 ` Manivannan Sadhasivam
2022-12-01 17:43 ` [PATCH v4 10/23] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8350 SoC Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-05 21:55 ` Dmitry Baryshkov
2022-12-05 21:55 ` Dmitry Baryshkov
2022-12-01 17:43 ` [PATCH v4 11/23] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoC Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-05 21:55 ` Dmitry Baryshkov
2022-12-05 21:55 ` Dmitry Baryshkov
2022-12-01 17:43 ` [PATCH v4 12/23] phy: qcom-qmp-ufs: Add HS G4 mode support to SC8280XP SoC Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-05 21:56 ` Dmitry Baryshkov
2022-12-05 21:56 ` Dmitry Baryshkov
2022-12-01 17:43 ` [PATCH v4 13/23] scsi: ufs: ufs-qcom: Remove un-necessary goto statements Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-05 19:53 ` Asutosh Das
2022-12-05 19:53 ` Asutosh Das
2022-12-05 22:26 ` Dmitry Baryshkov
2022-12-05 22:26 ` Dmitry Baryshkov
2022-12-01 17:43 ` [PATCH v4 14/23] scsi: ufs: ufs-qcom: Remove un-necessary WARN_ON() Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-05 19:55 ` Asutosh Das
2022-12-05 19:55 ` Asutosh Das
2022-12-01 17:43 ` [PATCH v4 15/23] scsi: ufs: ufs-qcom: Use bitfields where appropriate Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-05 19:56 ` Asutosh Das
2022-12-05 19:56 ` Asutosh Das
2022-12-01 17:43 ` [PATCH v4 16/23] scsi: ufs: ufs-qcom: Use dev_err_probe() for printing probe error Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-05 19:57 ` Asutosh Das
2022-12-05 19:57 ` Asutosh Das
2022-12-01 17:43 ` [PATCH v4 17/23] scsi: ufs: ufs-qcom: Fix the Qcom register name for offset 0xD0 Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-05 19:59 ` Asutosh Das
2022-12-05 19:59 ` Asutosh Das
2022-12-01 17:43 ` [PATCH v4 18/23] scsi: ufs: core: Add reinit_notify() callback Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-01 18:05 ` Bart Van Assche
2022-12-01 18:05 ` Bart Van Assche
2022-12-02 7:32 ` Manivannan Sadhasivam
2022-12-02 7:32 ` Manivannan Sadhasivam
2022-12-01 17:43 ` [PATCH v4 19/23] scsi: ufs: core: Add support for reinitializing the UFS device Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-01 17:43 ` [PATCH v4 20/23] scsi: ufs: ufs-qcom: Factor out the logic finding the HS Gear Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-01 17:43 ` [PATCH v4 21/23] scsi: ufs: ufs-qcom: Add support for reinitializing the UFS device Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-01 17:43 ` [PATCH v4 22/23] scsi: ufs: ufs-qcom: Add support for finding max gear on new platforms Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-01 17:43 ` [PATCH v4 23/23] MAINTAINERS: Add myself as the maintainer for Qcom UFS drivers Manivannan Sadhasivam
2022-12-01 17:43 ` Manivannan Sadhasivam
2022-12-01 20:15 ` Bjorn Andersson
2022-12-01 20:15 ` Bjorn Andersson
2022-12-02 20:49 ` [PATCH v4 00/23] ufs: qcom: Add HS-G4 support Andrew Halaney
2022-12-02 20:49 ` Andrew Halaney
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