[PATCH V6 0/5] ASoC: codecs: Add Awinic AW883XX audio amplifier driver

[PATCH V6 0/5] ASoC: codecs: Add Awinic AW883XX audio amplifier driver

[wangweidong.a]

From: Weidong Wang <wangweidong.a@awinic.com>

The Awinic AW883XX is an I2S/TDM input, high efficiency
digital Smart K audio amplifier with an integrated 10.25V
smart boost convert

Add a DT schema for describing Awinic AW883xx audio amplifiers. They are
controlled using I2C.

v5 -> v6: Modify the return value of Kcontrol
          Delete error prints in Kcontrol  
          Delete the aw883xx_dynamic_create_controls function
          Release firmware immediately after memcpy()
          Change the names of the Widget's input and output
          Delete the alloc and copy for aw_wiget
          Delete all debug nodes and use regmap's debugfs
          Use be32_to_cpup instead of custom macros
          Change inefficient writing
          Verify the size of the bin file
          Changing the function name
          Register directly with the snd_soc_register_component function
          Delete the aw_dev_reg_dump function

Weidong Wang (5):
  ASoC: codecs: Add i2c and codec registration for aw883xx and their
    associated operation functions
  ASoC: codecs: Implementation of aw883xx configuration file parsing
    function
  ASoC: codecs: aw883xx chip control logic, such as power on and off
  ASoC: codecs: Configure aw883xx chip register as well as Kconfig and
    Makefile
  ASoC: dt-bindings: Add schema for "awinic,aw883xx"

 .../bindings/sound/awinic,aw883xx.yaml        |   49 +
 sound/soc/codecs/Kconfig                      |   10 +
 sound/soc/codecs/Makefile                     |    7 +
 sound/soc/codecs/aw883xx/aw883xx.c            |  909 +++++++
 sound/soc/codecs/aw883xx/aw883xx.h            |   81 +
 sound/soc/codecs/aw883xx/aw883xx_bin_parse.c  | 1324 ++++++++++
 sound/soc/codecs/aw883xx/aw883xx_bin_parse.h  |  149 ++
 sound/soc/codecs/aw883xx/aw883xx_data_type.h  |  146 ++
 sound/soc/codecs/aw883xx/aw883xx_device.c     | 1613 ++++++++++++
 sound/soc/codecs/aw883xx/aw883xx_device.h     |  537 ++++
 sound/soc/codecs/aw883xx/aw883xx_init.c       |  615 +++++
 .../soc/codecs/aw883xx/aw883xx_pid_2049_reg.h | 2300 +++++++++++++++++
 12 files changed, 7740 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx.c
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx.h
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx_bin_parse.c
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx_bin_parse.h
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx_data_type.h
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx_device.c
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx_device.h
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx_init.c
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h


base-commit: 479174d402bcf60789106eedc4def3957c060bad
-- 
2.38.1

[PATCH V6 1/5] ASoC: codecs: Add i2c and codec registration for aw883xx and their associated operation functions

[wangweidong.a]

From: Weidong Wang <wangweidong.a@awinic.com>

The Awinic AW883XX is an I2S/TDM input, high efficiency
digital Smart K audio amplifier with an integrated 10.25V
smart boost convert

Signed-off-by: Nick Li <liweilei@awinic.com>
Signed-off-by: Bruce zhao <zhaolei@awinic.com>
Signed-off-by: Weidong Wang <wangweidong.a@awinic.com>
---
 sound/soc/codecs/aw883xx/aw883xx.c | 909 +++++++++++++++++++++++++++++
 sound/soc/codecs/aw883xx/aw883xx.h |  81 +++
 2 files changed, 990 insertions(+)
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx.c
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx.h

diff --git a/sound/soc/codecs/aw883xx/aw883xx.c b/sound/soc/codecs/aw883xx/aw883xx.c
new file mode 100644
index 000000000000..f82e6d8c71a7
--- /dev/null
+++ b/sound/soc/codecs/aw883xx/aw883xx.c
@@ -0,0 +1,909 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * aw883xx.c --  ALSA Soc AW883XX codec support
+ *
+ * Copyright (c) 2022 AWINIC Technology CO., LTD
+ *
+ * Author: Bruce zhao <zhaolei@awinic.com>
+ */
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/debugfs.h>
+#include <linux/firmware.h>
+#include <linux/hrtimer.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+#include <linux/syscalls.h>
+#include <linux/timer.h>
+#include <linux/uaccess.h>
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/workqueue.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/tlv.h>
+#include "aw883xx_pid_2049_reg.h"
+#include "aw883xx.h"
+#include "aw883xx_bin_parse.h"
+#include "aw883xx_device.h"
+
+static const struct regmap_config aw883xx_remap_config = {
+	.val_bits = 16,
+	.reg_bits = 8,
+	.max_register = AW_PID_2049_REG_MAX - 1,
+};
+
+/*
+ * aw883xx dsp write/read
+ */
+static int aw883xx_dsp_write_16bit(struct aw883xx *aw883xx,
+		unsigned short dsp_addr, unsigned int dsp_data)
+{
+	int ret;
+	struct aw_dsp_mem_desc *desc = &aw883xx->aw_pa->dsp_mem_desc;
+
+	ret = regmap_write(aw883xx->regmap, desc->dsp_madd_reg, dsp_addr);
+	if (ret < 0) {
+		dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret);
+		return ret;
+	}
+
+	ret = regmap_write(aw883xx->regmap, desc->dsp_mdat_reg, (u16)dsp_data);
+	if (ret < 0) {
+		dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int aw883xx_dsp_write_32bit(struct aw883xx *aw883xx,
+		unsigned short dsp_addr, unsigned int dsp_data)
+{
+	int ret;
+	u16 temp_data = 0;
+	struct aw_dsp_mem_desc *desc = &aw883xx->aw_pa->dsp_mem_desc;
+
+	ret = regmap_write(aw883xx->regmap, desc->dsp_madd_reg, dsp_addr);
+	if (ret < 0) {
+		dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret);
+		return ret;
+	}
+
+	temp_data = dsp_data & AW_DSP_16_DATA_MASK;
+	ret = regmap_write(aw883xx->regmap, desc->dsp_mdat_reg, temp_data);
+	if (ret < 0) {
+		dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret);
+		return ret;
+	}
+
+	temp_data = dsp_data >> 16;
+	ret = regmap_write(aw883xx->regmap, desc->dsp_mdat_reg, temp_data);
+	if (ret < 0) {
+		dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+/*
+ * aw883xx clear dsp chip select state
+ */
+static void aw883xx_clear_dsp_sel_st(struct aw883xx *aw883xx)
+{
+	unsigned int reg_value;
+	u8 reg = aw883xx->aw_pa->soft_rst.reg;
+
+	regmap_read(aw883xx->regmap, reg, &reg_value);
+}
+
+int aw883xx_dsp_write(struct aw883xx *aw883xx,
+		unsigned short dsp_addr, unsigned int dsp_data, unsigned char data_type)
+{
+	int ret = -1;
+
+	mutex_lock(&aw883xx->dsp_lock);
+	switch (data_type) {
+	case AW_DSP_16_DATA:
+		ret = aw883xx_dsp_write_16bit(aw883xx, dsp_addr, dsp_data);
+		if (ret < 0)
+			dev_err(aw883xx->dev, "write dsp_addr[0x%04x] 16 bit dsp_data[%04x] failed",
+					(u32)dsp_addr, dsp_data);
+		break;
+	case AW_DSP_32_DATA:
+		ret =  aw883xx_dsp_write_32bit(aw883xx, dsp_addr, dsp_data);
+		if (ret < 0)
+			dev_err(aw883xx->dev, "write dsp_addr[0x%04x] 32 bit dsp_data[%08x] failed",
+					(u32)dsp_addr, dsp_data);
+		break;
+	default:
+		dev_err(aw883xx->dev, "data type[%d] unsupported", data_type);
+		ret = -EINVAL;
+		break;
+	}
+
+	aw883xx_clear_dsp_sel_st(aw883xx);
+	mutex_unlock(&aw883xx->dsp_lock);
+	return ret;
+}
+
+static int aw883xx_dsp_read_16bit(struct aw883xx *aw883xx,
+		unsigned short dsp_addr, unsigned int *dsp_data)
+{
+	int ret;
+	unsigned int temp_data = 0;
+	struct aw_dsp_mem_desc *desc = &aw883xx->aw_pa->dsp_mem_desc;
+
+	ret = regmap_write(aw883xx->regmap, desc->dsp_madd_reg, dsp_addr);
+	if (ret < 0) {
+		dev_err(aw883xx->dev, "i2c write error, ret=%d", ret);
+		return ret;
+	}
+
+	ret = regmap_read(aw883xx->regmap, desc->dsp_mdat_reg, &temp_data);
+	if (ret < 0) {
+		dev_err(aw883xx->dev, "i2c write error, ret=%d", ret);
+		return ret;
+	}
+
+	*dsp_data = temp_data;
+
+	return 0;
+}
+
+static int aw883xx_dsp_read_32bit(struct aw883xx *aw883xx,
+		unsigned short dsp_addr, unsigned int *dsp_data)
+{
+	int ret;
+	unsigned int temp_data = 0;
+	struct aw_dsp_mem_desc *desc = &aw883xx->aw_pa->dsp_mem_desc;
+
+	/*write dsp addr*/
+	ret = regmap_write(aw883xx->regmap, desc->dsp_madd_reg, dsp_addr);
+	if (ret < 0) {
+		dev_err(aw883xx->dev, "i2c write error, ret=%d", ret);
+		return ret;
+	}
+
+	/*get Low 16 bit data*/
+	ret = regmap_read(aw883xx->regmap, desc->dsp_mdat_reg, &temp_data);
+	if (ret < 0) {
+		dev_err(aw883xx->dev, "i2c read error, ret=%d", ret);
+		return ret;
+	}
+
+	*dsp_data = temp_data;
+
+	/*get high 16 bit data*/
+	ret = regmap_read(aw883xx->regmap, desc->dsp_mdat_reg, &temp_data);
+	if (ret < 0) {
+		dev_err(aw883xx->dev, "i2c read error, ret=%d", ret);
+		return ret;
+	}
+	*dsp_data |= (temp_data << 16);
+
+	return 0;
+}
+
+int aw883xx_dsp_read(struct aw883xx *aw883xx,
+		unsigned short dsp_addr, unsigned int *dsp_data, unsigned char data_type)
+{
+	int ret = -1;
+
+	mutex_lock(&aw883xx->dsp_lock);
+	switch (data_type) {
+	case AW_DSP_16_DATA:
+		ret = aw883xx_dsp_read_16bit(aw883xx, dsp_addr, dsp_data);
+		if (ret < 0)
+			dev_err(aw883xx->dev, "read dsp_addr[0x%04x] 16 bit dsp_data[%04x] failed",
+					(u32)dsp_addr, *dsp_data);
+		break;
+	case AW_DSP_32_DATA:
+		ret = aw883xx_dsp_read_32bit(aw883xx, dsp_addr, dsp_data);
+		if (ret < 0)
+			dev_err(aw883xx->dev, "read dsp_addr[0x%04x] 32 bit dsp_data[%08x] failed",
+					(u32)dsp_addr, *dsp_data);
+		break;
+	default:
+		dev_err(aw883xx->dev, "data type[%d] unsupported", data_type);
+		ret = -EINVAL;
+		break;
+	}
+
+	aw883xx_clear_dsp_sel_st(aw883xx);
+	mutex_unlock(&aw883xx->dsp_lock);
+	return ret;
+}
+
+static void aw883xx_start_pa(struct aw883xx *aw883xx)
+{
+	int ret, i;
+
+	if (!aw883xx->allow_pw) {
+		dev_info(aw883xx->dev, "%s:dev can not allow power", __func__);
+		return;
+	}
+
+	if (aw883xx->pstream == AW883XX_STREAM_CLOSE) {
+		dev_info(aw883xx->dev, "%s:pstream is close", __func__);
+		return;
+	}
+
+	for (i = 0; i < AW_START_RETRIES; i++) {
+		ret = aw883xx_device_start(aw883xx->aw_pa);
+		if (ret) {
+			dev_err(aw883xx->dev, "aw883xx device start failed. retry = %d", i);
+			ret = aw883xx_dev_fw_update(aw883xx->aw_pa, AW_DSP_FW_UPDATE_ON, true);
+			if (ret < 0) {
+				dev_err(aw883xx->dev, "fw update failed");
+				continue;
+			}
+		} else {
+			dev_info(aw883xx->dev, "start success\n");
+			break;
+		}
+	}
+}
+
+static void aw883xx_startup_work(struct work_struct *work)
+{
+	struct aw883xx *aw883xx =
+		container_of(work, struct aw883xx, start_work.work);
+
+	mutex_lock(&aw883xx->lock);
+	aw883xx_start_pa(aw883xx);
+	mutex_unlock(&aw883xx->lock);
+}
+
+static void aw883xx_start(struct aw883xx *aw883xx, bool sync_start)
+{
+	int ret;
+	int i;
+
+	if (aw883xx->aw_pa->fw_status != AW_DEV_FW_OK)
+		return;
+
+	if (!aw883xx->allow_pw) {
+		dev_info(aw883xx->dev, "%s:dev can not allow power", __func__);
+		return;
+	}
+
+	if (aw883xx->aw_pa->status == AW_DEV_PW_ON)
+		return;
+
+	for (i = 0; i < AW_START_RETRIES; i++) {
+		ret = aw883xx_dev_fw_update(aw883xx->aw_pa, AW_DSP_FW_UPDATE_OFF,
+					aw883xx->phase_sync);
+		if (ret < 0) {
+			dev_err(aw883xx->dev, "fw update failed. retry = %d", i);
+			continue;
+		} else {
+			/*firmware update success*/
+			if (sync_start == AW_SYNC_START)
+				aw883xx_start_pa(aw883xx);
+			else
+				queue_delayed_work(aw883xx->work_queue,
+					&aw883xx->start_work,
+					AW_START_WORK_DELAY_MS);
+			return;
+		}
+	}
+}
+
+/*
+ * Digital Audio Interface
+ */
+static int aw883xx_startup(struct snd_pcm_substream *substream,
+			struct snd_soc_dai *dai)
+{
+	struct snd_soc_component *codec = dai->component;
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec);
+
+	aw883xx->pstream = AW883XX_STREAM_OPEN;
+
+	mutex_lock(&aw883xx->lock);
+	aw883xx_start(aw883xx, AW_ASYNC_START);
+	mutex_unlock(&aw883xx->lock);
+
+	return 0;
+}
+
+static void aw883xx_shutdown(struct snd_pcm_substream *substream,
+				struct snd_soc_dai *dai)
+{
+	struct snd_soc_component *codec = dai->component;
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec);
+
+	aw883xx->pstream = AW883XX_STREAM_CLOSE;
+	cancel_delayed_work_sync(&aw883xx->start_work);
+	mutex_lock(&aw883xx->lock);
+	aw883xx_device_stop(aw883xx->aw_pa);
+	mutex_unlock(&aw883xx->lock);
+
+}
+
+static const struct snd_soc_dai_ops aw883xx_dai_ops = {
+	.startup = aw883xx_startup,
+	.shutdown = aw883xx_shutdown,
+};
+
+static struct snd_soc_dai_driver aw883xx_dai[] = {
+	{
+		.name = "aw883xx-aif",
+		.id = 1,
+		.playback = {
+			.stream_name = "Speaker_Playback",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = AW_RATES,
+			.formats = AW_FORMATS,
+		},
+		.capture = {
+			.stream_name = "Speaker_Capture",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = AW_RATES,
+			.formats = AW_FORMATS,
+		},
+		.ops = &aw883xx_dai_ops,
+	},
+};
+
+/*
+ * codec driver
+ */
+static int aw883xx_get_fade_in_time(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(component);
+	struct aw_device *aw_dev = aw883xx->aw_pa;
+
+	ucontrol->value.integer.value[0] = aw_dev->fade_in_time;
+
+	return 0;
+
+}
+
+static int aw883xx_set_fade_in_time(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned int time = 0;
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(component);
+	struct aw_device *aw_dev = aw883xx->aw_pa;
+	struct soc_mixer_control *mc =
+		(struct soc_mixer_control *)kcontrol->private_value;
+
+	time = ucontrol->value.integer.value[0];
+
+	if (time < mc->min || time > mc->max)
+		return 0;
+
+	if (time != aw_dev->fade_in_time) {
+		aw_dev->fade_in_time = time;
+		return 1;
+	}
+
+	return 0;
+}
+
+static int aw883xx_get_fade_out_time(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(component);
+	struct aw_device *aw_dev = aw883xx->aw_pa;
+
+	ucontrol->value.integer.value[0] = aw_dev->fade_out_time;
+
+	return 0;
+}
+
+static int aw883xx_set_fade_out_time(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(component);
+	struct soc_mixer_control *mc =
+		(struct soc_mixer_control *)kcontrol->private_value;
+	struct aw_device *aw_dev = aw883xx->aw_pa;
+	unsigned int time = 0;
+
+	time = ucontrol->value.integer.value[0];
+	if (time < mc->min || time > mc->max)
+		return 0;
+
+	if (time != aw_dev->fade_out_time) {
+		aw_dev->fade_out_time = time;
+		return 1;
+	}
+
+	return 0;
+}
+
+static int aw883xx_profile_info(struct snd_kcontrol *kcontrol,
+			 struct snd_ctl_elem_info *uinfo)
+{
+	int count;
+	char *name = NULL;
+	const char *prof_name = NULL;
+	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec);
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+	uinfo->count = 1;
+
+	count = aw883xx_dev_get_profile_count(aw883xx->aw_pa);
+	if (count <= 0) {
+		uinfo->value.enumerated.items = 0;
+		return 0;
+	}
+
+	uinfo->value.enumerated.items = count;
+
+	if (uinfo->value.enumerated.item >= count)
+		uinfo->value.enumerated.item = count - 1;
+
+	name = uinfo->value.enumerated.name;
+	count = uinfo->value.enumerated.item;
+
+	prof_name = aw_dev_get_prof_name(aw883xx->aw_pa, count);
+	if (!prof_name) {
+		strscpy(uinfo->value.enumerated.name, "null",
+						strlen("null") + 1);
+		return 0;
+	}
+
+	strscpy(name, prof_name, sizeof(uinfo->value.enumerated.name));
+
+	return 0;
+}
+
+static int aw883xx_profile_get(struct snd_kcontrol *kcontrol,
+			struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec);
+
+	ucontrol->value.integer.value[0] = aw883xx_dev_get_profile_index(aw883xx->aw_pa);
+
+	return 0;
+}
+
+static int aw883xx_profile_set(struct snd_kcontrol *kcontrol,
+		struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec);
+	int ret;
+	int cur_index;
+
+	/* check value valid */
+	ret = aw883xx_dev_check_profile_index(aw883xx->aw_pa, ucontrol->value.integer.value[0]);
+	if (ret)
+		return 0;
+
+	/*check cur_index == set value*/
+	cur_index = aw883xx_dev_get_profile_index(aw883xx->aw_pa);
+	if (cur_index == ucontrol->value.integer.value[0]) {
+		dev_dbg(codec->dev, "index no change");
+		return 0;
+	}
+
+	/*pa stop or stopping just set profile*/
+	mutex_lock(&aw883xx->lock);
+	aw883xx_dev_set_profile_index(aw883xx->aw_pa, ucontrol->value.integer.value[0]);
+
+	if (aw883xx->pstream) {
+		aw883xx_device_stop(aw883xx->aw_pa);
+		aw883xx_start(aw883xx, AW_SYNC_START);
+	}
+
+	mutex_unlock(&aw883xx->lock);
+
+	return 1;
+}
+
+static int aw883xx_switch_get(struct snd_kcontrol *kcontrol,
+			struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec);
+
+	ucontrol->value.integer.value[0] = aw883xx->allow_pw;
+
+	return 0;
+}
+
+static int aw883xx_switch_set(struct snd_kcontrol *kcontrol,
+		struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec);
+	struct soc_mixer_control *mc =
+		(struct soc_mixer_control *)kcontrol->private_value;
+	unsigned int value = 0;
+
+	value = ucontrol->value.integer.value[0];
+	if (value < mc->min || value > mc->max)
+		return 0;
+
+	if (value == aw883xx->allow_pw) {
+		dev_dbg(aw883xx->dev, "PA switch not change");
+		return 0;
+	}
+	aw883xx->allow_pw = value;
+
+	if (aw883xx->pstream) {
+		if (!aw883xx->allow_pw) {
+			cancel_delayed_work_sync(&aw883xx->start_work);
+			mutex_lock(&aw883xx->lock);
+			aw883xx_device_stop(aw883xx->aw_pa);
+			mutex_unlock(&aw883xx->lock);
+		} else {
+			cancel_delayed_work_sync(&aw883xx->start_work);
+			mutex_lock(&aw883xx->lock);
+			aw883xx_start(aw883xx, AW_SYNC_START);
+			mutex_unlock(&aw883xx->lock);
+		}
+	}
+
+	return 1;
+}
+
+static int aw883xx_volume_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec);
+	struct aw_volume_desc *vol_desc = &aw883xx->aw_pa->volume_desc;
+
+	ucontrol->value.integer.value[0] = vol_desc->ctl_volume;
+
+	return 0;
+}
+
+static int aw883xx_volume_set(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	int value = 0;
+	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec);
+	struct aw_volume_desc *vol_desc = &aw883xx->aw_pa->volume_desc;
+	struct soc_mixer_control *mc =
+		(struct soc_mixer_control *)kcontrol->private_value;
+
+	value = ucontrol->value.integer.value[0];
+	if (value < mc->min || value > mc->max)
+		return 0;
+
+	if (vol_desc->ctl_volume != value) {
+		vol_desc->ctl_volume = value;
+		aw883xx_dev_set_volume(aw883xx->aw_pa, vol_desc->ctl_volume);
+
+		return 1;
+	}
+
+	return 0;
+}
+
+static int aw883xx_get_fade_step(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec);
+
+	ucontrol->value.integer.value[0] = aw883xx->aw_pa->fade_step;
+
+	return 0;
+}
+static int aw883xx_set_fade_step(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	unsigned int value = 0;
+	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec);
+	struct soc_mixer_control *mc =
+		(struct soc_mixer_control *)kcontrol->private_value;
+
+	value = ucontrol->value.integer.value[0];
+	if (value < mc->min || value > mc->max)
+		return 0;
+
+	if (aw883xx->aw_pa->fade_step != value) {
+		aw883xx->aw_pa->fade_step = value;
+		return 1;
+	}
+
+	return 0;
+}
+static int aw883xx_re_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec);
+	struct aw_device *aw_dev = aw883xx->aw_pa;
+
+	ucontrol->value.integer.value[0] = aw_dev->cali_desc.cali_re;
+
+	return 0;
+}
+
+static int aw883xx_re_set(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	int value = 0;
+	struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(codec);
+	struct aw_device *aw_dev = aw883xx->aw_pa;
+	struct soc_mixer_control *mc =
+		(struct soc_mixer_control *)kcontrol->private_value;
+
+	value = ucontrol->value.integer.value[0];
+	if (value < mc->min || value > mc->max)
+		return 0;
+
+	if (aw_dev->cali_desc.cali_re != value) {
+		aw_dev->cali_desc.cali_re = value;
+		return 1;
+	}
+
+	return 0;
+}
+static const struct snd_kcontrol_new aw883xx_controls[] = {
+	SOC_SINGLE_EXT("PCM Playback Switch", SND_SOC_NOPM, 0, 1, 0,
+				aw883xx_switch_get, aw883xx_switch_set),
+	SOC_SINGLE_EXT("PCM Playback Volume", AW_PID_2049_SYSCTRL2_REG,
+		6, AW_PID_2049_MUTE_VOL, 0, aw883xx_volume_get,
+		aw883xx_volume_set),
+	SOC_SINGLE_EXT("Fade Step", 0, 0, AW_PID_2049_MUTE_VOL, 0,
+		aw883xx_get_fade_step, aw883xx_set_fade_step),
+	SOC_SINGLE_EXT("Volume Ramp Up Step", 0, 0, FADE_TIME_MAX, FADE_TIME_MIN,
+		aw883xx_get_fade_in_time, aw883xx_set_fade_in_time),
+	SOC_SINGLE_EXT("Volume Ramp Down Step", 0, 0, FADE_TIME_MAX, FADE_TIME_MIN,
+		aw883xx_get_fade_out_time, aw883xx_set_fade_out_time),
+	SOC_SINGLE_EXT("Calib", 0, 0, 100, 0,
+		aw883xx_re_get, aw883xx_re_set),
+	AW_PROFILE_EXT("Profile Set", aw883xx_profile_info,
+		aw883xx_profile_get, aw883xx_profile_set),
+};
+
+static const struct snd_soc_dapm_widget aw883xx_dapm_widgets[] = {
+	 /* playback */
+	SND_SOC_DAPM_AIF_IN("AIF_RX", "Speaker_Playback", 0, SND_SOC_NOPM, 0, 0),
+	SND_SOC_DAPM_OUTPUT("DAC Output"),
+	/* capture */
+	SND_SOC_DAPM_AIF_OUT("AIF_TX", "Speaker_Capture", 0, SND_SOC_NOPM, 0, 0),
+	SND_SOC_DAPM_INPUT("ADC Input"),
+};
+
+static const struct snd_soc_dapm_route aw883xx_audio_map[] = {
+	{"DAC Output", NULL, "AIF_RX"},
+	{"AIF_TX", NULL, "ADC Input"},
+};
+
+static int aw883xx_codec_probe(struct snd_soc_component *component)
+{
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(component);
+	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
+	int ret = 0;
+
+	/*destroy_workqueue(struct workqueue_struct *wq)*/
+	aw883xx->work_queue = create_singlethread_workqueue("aw883xx");
+	if (!aw883xx->work_queue) {
+		dev_err(aw883xx->dev, "create workqueue failed !");
+		return -EINVAL;
+	}
+
+	INIT_DELAYED_WORK(&aw883xx->start_work, aw883xx_startup_work);
+
+	/*add widgets*/
+	ret = snd_soc_dapm_new_controls(dapm, aw883xx_dapm_widgets,
+							ARRAY_SIZE(aw883xx_dapm_widgets));
+	if (ret < 0)
+		return ret;
+
+	/*add route*/
+	ret = snd_soc_dapm_add_routes(dapm, aw883xx_audio_map,
+							ARRAY_SIZE(aw883xx_audio_map));
+	if (ret < 0)
+		return ret;
+
+	ret = snd_soc_add_component_controls(component, aw883xx_controls,
+							ARRAY_SIZE(aw883xx_controls));
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+
+static void aw883xx_codec_remove(struct snd_soc_component *aw_codec)
+{
+	struct aw883xx *aw883xx = snd_soc_component_get_drvdata(aw_codec);
+
+	cancel_delayed_work_sync(&aw883xx->start_work);
+
+	if (aw883xx->work_queue)
+		destroy_workqueue(aw883xx->work_queue);
+
+}
+
+static const struct snd_soc_component_driver soc_codec_dev_aw883xx = {
+	.probe = aw883xx_codec_probe,
+	.remove = aw883xx_codec_remove,
+};
+
+static struct aw883xx *aw883xx_malloc_init(struct i2c_client *i2c)
+{
+	struct aw883xx *aw883xx = devm_kzalloc(&i2c->dev,
+			sizeof(struct aw883xx), GFP_KERNEL);
+	if (!aw883xx)
+		return NULL;
+
+	aw883xx->dev = &i2c->dev;
+	aw883xx->i2c = i2c;
+	aw883xx->aw_pa = NULL;
+	aw883xx->codec = NULL;
+	aw883xx->allow_pw = true;
+	aw883xx->work_queue = NULL;
+	mutex_init(&aw883xx->lock);
+	mutex_init(&aw883xx->dsp_lock);
+
+	return aw883xx;
+}
+
+static void aw883xx_parse_sync_flag_dt(struct aw883xx *aw883xx)
+{
+	int ret;
+	int32_t sync_enable = 0;
+	struct device_node *np = aw883xx->dev->of_node;
+
+	ret = of_property_read_u32(np, "sync-flag", &sync_enable);
+	if (ret < 0) {
+		dev_dbg(aw883xx->dev,
+			"read sync flag failed,default phase sync off");
+		sync_enable = false;
+	} else {
+		dev_dbg(aw883xx->dev,
+			"sync flag is %d", sync_enable);
+	}
+
+	aw883xx->phase_sync = sync_enable;
+}
+
+static void aw883xx_hw_reset(struct aw883xx *aw883xx)
+{
+	if (aw883xx->reset_gpio) {
+		gpiod_set_value_cansleep(aw883xx->reset_gpio, 0);
+		usleep_range(AW_1000_US, AW_1000_US + 10);
+		gpiod_set_value_cansleep(aw883xx->reset_gpio, 1);
+		usleep_range(AW_1000_US, AW_1000_US + 10);
+	} else {
+		dev_err(aw883xx->dev, "%s failed", __func__);
+	}
+}
+
+static int aw883xx_read_chipid(struct aw883xx *aw883xx)
+{
+	int ret = -1;
+	int reg_val = 0;
+
+	ret = regmap_read(aw883xx->regmap, AW_CHIP_ID_REG, &reg_val);
+	if (ret)
+		return -EIO;
+
+	dev_info(aw883xx->dev, "chip id = %x\n", reg_val);
+	aw883xx->chip_id = reg_val;
+
+	return 0;
+}
+
+static void aw883xx_parse_dt(struct aw883xx *aw883xx)
+{
+	aw883xx_parse_sync_flag_dt(aw883xx);
+
+	aw883xx->reset_gpio = devm_gpiod_get_optional(aw883xx->dev,
+								"reset", GPIOD_OUT_LOW);
+	if (IS_ERR(aw883xx->reset_gpio))
+		dev_info(aw883xx->dev, "reset gpio not defined\n");
+}
+/*
+ * i2c driver
+ */
+static int aw883xx_i2c_probe(struct i2c_client *i2c)
+{
+	struct aw883xx *aw883xx = NULL;
+	int ret = -1;
+
+	if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C)) {
+		dev_err(&i2c->dev, "check_functionality failed");
+		return -EIO;
+	}
+
+	aw883xx = aw883xx_malloc_init(i2c);
+	if (!aw883xx) {
+		dev_err(&i2c->dev, "malloc aw883xx failed");
+		return -ENOMEM;
+	}
+	i2c_set_clientdata(i2c, aw883xx);
+
+	aw883xx_parse_dt(aw883xx);
+
+	/* hardware reset */
+	aw883xx_hw_reset(aw883xx);
+
+	aw883xx->regmap = devm_regmap_init_i2c(i2c, &aw883xx_remap_config);
+	if (IS_ERR(aw883xx->regmap)) {
+		ret = PTR_ERR(aw883xx->regmap);
+		dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
+		return ret;
+	}
+
+	/* aw883xx chip id */
+	ret = aw883xx_read_chipid(aw883xx);
+	if (ret < 0) {
+		dev_err(&i2c->dev, "aw883xx_read_chipid failed ret=%d", ret);
+		return ret;
+	}
+
+	/*aw pa init*/
+	ret = aw883xx_init(aw883xx);
+	if (ret < 0)
+		return ret;
+
+	ret = aw883xx_request_firmware_file(aw883xx);
+	if (ret < 0) {
+		dev_err(aw883xx->dev, "%s failed\n", __func__);
+		return ret;
+	}
+
+	ret = snd_soc_register_component(aw883xx->dev,
+			&soc_codec_dev_aw883xx,
+			aw883xx_dai, ARRAY_SIZE(aw883xx_dai));
+	if (ret < 0) {
+		dev_err(aw883xx->dev, "failed to register aw883xx: %d", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void aw883xx_i2c_remove(struct i2c_client *i2c)
+{
+	struct aw883xx *aw883xx = i2c_get_clientdata(i2c);
+
+	aw883xx_dev_deinit(aw883xx->aw_pa);
+	snd_soc_unregister_component(&i2c->dev);
+
+	if (aw883xx->aw_cfg) {
+		vfree(aw883xx->aw_cfg);
+		aw883xx->aw_cfg = NULL;
+	}
+}
+
+static const struct i2c_device_id aw883xx_i2c_id[] = {
+	{ AW_I2C_NAME, 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, aw883xx_i2c_id);
+
+static struct i2c_driver aw883xx_i2c_driver = {
+	.driver = {
+		.name = AW_I2C_NAME,
+		.owner = THIS_MODULE,
+	},
+	.probe_new = aw883xx_i2c_probe,
+	.remove = aw883xx_i2c_remove,
+	.id_table = aw883xx_i2c_id,
+};
+module_i2c_driver(aw883xx_i2c_driver);
+
+MODULE_DESCRIPTION("ASoC AW883XX Smart PA Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/aw883xx/aw883xx.h b/sound/soc/codecs/aw883xx/aw883xx.h
new file mode 100644
index 000000000000..209851cae7ef
--- /dev/null
+++ b/sound/soc/codecs/aw883xx/aw883xx.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * aw883xx.c --  ALSA Soc AW883XX codec support
+ *
+ * Copyright (c) 2022 AWINIC Technology CO., LTD
+ *
+ * Author: Bruce zhao <zhaolei@awinic.com>
+ */
+
+#ifndef __AW883XX_H__
+#define __AW883XX_H__
+
+#include <linux/version.h>
+#include <sound/control.h>
+#include <sound/soc.h>
+#include "aw883xx_data_type.h"
+
+#define AW_CHIP_ID_REG			(0x00)
+#define AW_START_RETRIES			(5)
+#define AW_START_WORK_DELAY_MS	(0)
+
+#define AW_DSP_16_DATA_MASK	(0x0000ffff)
+
+#define AW_I2C_NAME "aw883xx_smartpa"
+
+#define AW_RATES (SNDRV_PCM_RATE_8000_48000 | \
+			SNDRV_PCM_RATE_96000)
+#define AW_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+			SNDRV_PCM_FMTBIT_S24_LE | \
+			SNDRV_PCM_FMTBIT_S32_LE)
+#define AW_REQUEST_FW_RETRIES		5	/* 5 times */
+#define AW_SYNC_LOAD
+
+#define FADE_TIME_MAX 100000
+#define FADE_TIME_MIN 0
+
+#define AW_PROFILE_EXT(xname, profile_info, profile_get, profile_set) \
+{ \
+	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
+	.name = xname, \
+	.info = profile_info, \
+	.get = profile_get, \
+	.put = profile_set, \
+}
+
+enum {
+	AW_SYNC_START = 0,
+	AW_ASYNC_START,
+};
+
+enum {
+	AW883XX_STREAM_CLOSE = 0,
+	AW883XX_STREAM_OPEN,
+};
+
+struct aw883xx {
+	struct i2c_client *i2c;
+	struct device *dev;
+	struct mutex lock;
+	struct mutex dsp_lock;
+	struct snd_soc_component *codec;
+	struct aw_device *aw_pa;
+	struct gpio_desc *reset_gpio;
+	unsigned char phase_sync;	/*phase sync*/
+	bool allow_pw;
+	u8 pstream;
+	struct workqueue_struct *work_queue;
+	struct delayed_work start_work;
+	u16 chip_id;
+	struct regmap *regmap;
+	struct aw_container *aw_cfg;
+};
+
+int aw883xx_init(struct aw883xx *aw883xx);
+
+int aw883xx_dsp_write(struct aw883xx *aw883xx,
+		unsigned short dsp_addr, unsigned int dsp_data, unsigned char data_type);
+int aw883xx_dsp_read(struct aw883xx *aw883xx,
+		unsigned short dsp_addr, unsigned int *dsp_data, unsigned char data_type);
+
+#endif
-- 
2.38.1

[PATCH V6 2/5] ASoC: codecs: Implementation of aw883xx configuration file parsing function

[wangweidong.a]

From: Weidong Wang <wangweidong.a@awinic.com>

The Awinic AW883XX is an I2S/TDM input, high efficiency
digital Smart K audio amplifier with an integrated 10.25V
smart boost convert

Signed-off-by: Nick Li <liweilei@awinic.com>
Signed-off-by: Bruce zhao <zhaolei@awinic.com>
Signed-off-by: Weidong Wang <wangweidong.a@awinic.com>
---
 sound/soc/codecs/aw883xx/aw883xx_bin_parse.c | 1324 ++++++++++++++++++
 sound/soc/codecs/aw883xx/aw883xx_bin_parse.h |  149 ++
 2 files changed, 1473 insertions(+)
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx_bin_parse.c
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx_bin_parse.h

diff --git a/sound/soc/codecs/aw883xx/aw883xx_bin_parse.c b/sound/soc/codecs/aw883xx/aw883xx_bin_parse.c
new file mode 100644
index 000000000000..f3d9b8a9fdf2
--- /dev/null
+++ b/sound/soc/codecs/aw883xx/aw883xx_bin_parse.c
@@ -0,0 +1,1324 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * aw_bin_parse.c  -- ALSA Soc AW883XX codec support
+ *
+ * Copyright (c) 2022 AWINIC Technology CO., LTD
+ */
+
+#include <linux/cdev.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/debugfs.h>
+#include <linux/firmware.h>
+#include <linux/hrtimer.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/miscdevice.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/uaccess.h>
+#include <linux/version.h>
+#include <linux/workqueue.h>
+#include "aw883xx_bin_parse.h"
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/swab.h>
+#include <linux/device.h>
+#include <linux/regmap.h>
+#include <linux/fs.h>
+#include <linux/list.h>
+#include <linux/wait.h>
+
+static char *profile_name[AW_PROFILE_MAX] = {
+	"Music", "Voice", "Voip", "Ringtone",
+	"Ringtone_hs", "Lowpower", "Bypass",
+	"Mmi", "Fm", "Notification", "Receiver"
+};
+
+static int aw_parse_bin_header_1_0_0(struct aw_bin *bin);
+
+/*
+ * Interface function
+ *
+ * return value:
+ *       value = 0 :success;
+ *       value = -1 :check bin header version
+ *       value = -2 :check bin data type
+ *       value = -3 :check sum or check bin data len error
+ *       value = -4 :check data version
+ *       value = -5 :check register num
+ *       value = -6 :check dsp reg num
+ *       value = -7 :check soc app num
+ *       value = -8 :bin is NULL point
+ *
+ */
+
+/*
+ * check sum data
+ */
+static int aw_check_sum(struct aw_bin *bin, int bin_num)
+{
+	unsigned int i = 0;
+	unsigned int sum_data = 0;
+	unsigned int check_sum = 0;
+	unsigned char *p_check_sum = NULL;
+
+	p_check_sum = &(bin->info.data[(bin->header_info[bin_num].valid_data_addr -
+						bin->header_info[bin_num].header_len)]);
+
+	pr_debug("aw_bin_parse p_check_sum = %p\n", p_check_sum);
+
+	check_sum = le32_to_cpup((void *)p_check_sum);
+
+	for (i = 4; i < bin->header_info[bin_num].bin_data_len +
+					bin->header_info[bin_num].header_len; i++) {
+		sum_data += *(p_check_sum + i);
+	}
+	pr_debug("aw_bin_parse bin_num = %d, check_sum = 0x%x, sum_data = 0x%x\n",
+						bin_num, check_sum, sum_data);
+	if (sum_data != check_sum) {
+		p_check_sum = NULL;
+		pr_err("%s. CheckSum Fail.bin_num=%d, CheckSum:0x%x, SumData:0x%x",
+				__func__, bin_num, check_sum, sum_data);
+		return -BIN_DATA_LEN_ERR;
+	}
+	p_check_sum = NULL;
+
+	return 0;
+}
+
+static int aw_check_data_version(struct aw_bin *bin, int bin_num)
+{
+	if (bin->header_info[bin_num].bin_data_ver < DATA_VERSION_V1 ||
+		bin->header_info[bin_num].bin_data_ver > DATA_VERSION_MAX) {
+		pr_err("aw_bin_parse Unrecognized this bin data version\n");
+		return -DATA_VER_ERR;
+	}
+
+	return 0;
+}
+
+static int aw_check_register_num_v1(struct aw_bin *bin, int bin_num)
+{
+	unsigned int check_register_num = 0;
+	unsigned int parse_register_num = 0;
+	unsigned char *p_check_sum = NULL;
+	struct bin_header_info temp_info;
+
+	temp_info = bin->header_info[bin_num];
+	p_check_sum = &(bin->info.data[(temp_info.valid_data_addr)]);
+	pr_debug("aw_bin_parse p_check_sum = %p\n", p_check_sum);
+	parse_register_num = le32_to_cpup((void *)p_check_sum);
+	check_register_num = (bin->header_info[bin_num].bin_data_len - 4) /
+				(bin->header_info[bin_num].reg_byte_len +
+				bin->header_info[bin_num].data_byte_len);
+	pr_debug("%s bin_num = %d,parse_register_num = 0x%x,check_register_num = 0x%x\n",
+				__func__, bin_num, parse_register_num, check_register_num);
+	if (parse_register_num != check_register_num) {
+		p_check_sum = NULL;
+		pr_err("%s bin_num = %d,parse_register_num = 0x%x,check_register_num = 0x%x\n",
+				__func__, bin_num, parse_register_num, check_register_num);
+
+		return -REG_NUM_ERR;
+	}
+	bin->header_info[bin_num].reg_num = parse_register_num;
+	bin->header_info[bin_num].valid_data_len = temp_info.bin_data_len - 4;
+	p_check_sum = NULL;
+	bin->header_info[bin_num].valid_data_addr = temp_info.valid_data_addr + 4;
+
+	return 0;
+}
+
+static int aw_check_dsp_reg_num_v1(struct aw_bin *bin, int bin_num)
+{
+	unsigned int check_dsp_reg_num = 0;
+	unsigned int parse_dsp_reg_num = 0;
+	unsigned char *p_check_sum = NULL;
+	struct bin_header_info temp_info;
+
+	temp_info = bin->header_info[bin_num];
+	p_check_sum = &(bin->info.data[(temp_info.valid_data_addr)]);
+	pr_debug("aw_bin_parse p_check_sum = %p\n", p_check_sum);
+	parse_dsp_reg_num = le32_to_cpup((void *)(p_check_sum + 4));
+	bin->header_info[bin_num].reg_data_byte_len =
+			le32_to_cpup((void *)(p_check_sum + 8));
+	check_dsp_reg_num = (bin->header_info[bin_num].bin_data_len - 12) /
+				bin->header_info[bin_num].reg_data_byte_len;
+	pr_debug("%s bin_num = %d, parse_dsp_reg_num = 0x%x, check_dsp_reg_num = 0x%x",
+					__func__, bin_num, check_dsp_reg_num, check_dsp_reg_num);
+	if (parse_dsp_reg_num != check_dsp_reg_num) {
+		p_check_sum = NULL;
+		pr_err("aw_bin_parse check dsp reg num error\n");
+		pr_err("%s bin_num = %d, parse_dsp_reg_num = 0x%x, check_dsp_reg_num = 0x%x",
+					__func__, bin_num, check_dsp_reg_num, check_dsp_reg_num);
+		return -DSP_REG_NUM_ERR;
+	}
+	bin->header_info[bin_num].download_addr = le32_to_cpup((void *)p_check_sum);
+	bin->header_info[bin_num].reg_num = parse_dsp_reg_num;
+	bin->header_info[bin_num].valid_data_len = temp_info.bin_data_len - 12;
+	p_check_sum = NULL;
+	bin->header_info[bin_num].valid_data_addr = temp_info.valid_data_addr + 12;
+	return 0;
+}
+
+static int aw_check_soc_app_num_v1(struct aw_bin *bin, int bin_num)
+{
+	unsigned int check_soc_app_num = 0;
+	unsigned int parse_soc_app_num = 0;
+	unsigned char *p_check_sum = NULL;
+	struct bin_header_info temp_info;
+
+	temp_info = bin->header_info[bin_num];
+	p_check_sum = &(bin->info.data[(temp_info.valid_data_addr)]);
+	pr_debug("aw_bin_parse p_check_sum = %p\n", p_check_sum);
+	bin->header_info[bin_num].app_version = le32_to_cpup((void *)p_check_sum);
+	parse_soc_app_num = le32_to_cpup((void *)(p_check_sum + 8));
+	check_soc_app_num = bin->header_info[bin_num].bin_data_len - 12;
+	pr_debug("%s bin_num = %d, parse_soc_app_num=0x%x, check_soc_app_num = 0x%x\n",
+					__func__, bin_num, parse_soc_app_num, check_soc_app_num);
+	if (parse_soc_app_num != check_soc_app_num) {
+		p_check_sum = NULL;
+		pr_err("aw_bin_parse check soc app num error\n");
+		pr_err("%s bin_num = %d, parse_soc_app_num=0x%x, check_soc_app_num = 0x%x\n",
+					__func__, bin_num, parse_soc_app_num, check_soc_app_num);
+
+		return -SOC_APP_NUM_ERR;
+	}
+	bin->header_info[bin_num].reg_num = parse_soc_app_num;
+	bin->header_info[bin_num].download_addr =
+			le32_to_cpup((void *)(p_check_sum + 4));
+	bin->header_info[bin_num].valid_data_len = temp_info.bin_data_len - 12;
+	p_check_sum = NULL;
+	bin->header_info[bin_num].valid_data_addr = temp_info.valid_data_addr + 12;
+	return 0;
+}
+
+/*
+ * bin header 1_0_0
+ */
+static void aw_get_single_bin_header_1_0_0(struct aw_bin *bin)
+{
+	int i = 0;
+
+	bin->header_info[bin->all_bin_parse_num].header_len = HEADER_LEN;
+	bin->header_info[bin->all_bin_parse_num].check_sum =
+							le32_to_cpup((void *)(bin->p_addr) +
+							CHECK_SUM_OFFSET);
+	bin->header_info[bin->all_bin_parse_num].header_ver =
+							le32_to_cpup((void *)(bin->p_addr +
+							HEADER_VER_OFFSET));
+	bin->header_info[bin->all_bin_parse_num].bin_data_type =
+							le32_to_cpup((void *)(bin->p_addr +
+							BIN_DATA_TYPE_OFFSET));
+	bin->header_info[bin->all_bin_parse_num].bin_data_ver =
+							le32_to_cpup((void *)(bin->p_addr +
+							BIN_DATA_VER_OFFSET));
+	bin->header_info[bin->all_bin_parse_num].bin_data_len =
+							le32_to_cpup((void *)(bin->p_addr +
+							BIN_DATA_LEN_OFFSET));
+	bin->header_info[bin->all_bin_parse_num].ui_ver =
+							le32_to_cpup((void *)(bin->p_addr +
+							UI_VER_OFFSET));
+	bin->header_info[bin->all_bin_parse_num].reg_byte_len =
+							le32_to_cpup((void *)(bin->p_addr +
+							REG_BYTE_LEN_OFFSET));
+	bin->header_info[bin->all_bin_parse_num].data_byte_len =
+							le32_to_cpup((void *)(bin->p_addr +
+							DATA_BYTE_LEN_OFFSET));
+	bin->header_info[bin->all_bin_parse_num].device_addr =
+							le32_to_cpup((void *)(bin->p_addr +
+							DEVICE_ADDR_OFFSET));
+	for (i = 0; i < 8; i++) {
+		bin->header_info[bin->all_bin_parse_num].chip_type[i] =
+						*(bin->p_addr + 24 + i);
+	}
+	bin->header_info[bin->all_bin_parse_num].reg_num = 0x00000000;
+	bin->header_info[bin->all_bin_parse_num].reg_data_byte_len = 0x00000000;
+	bin->header_info[bin->all_bin_parse_num].download_addr = 0x00000000;
+	bin->header_info[bin->all_bin_parse_num].app_version = 0x00000000;
+	bin->header_info[bin->all_bin_parse_num].valid_data_len = 0x00000000;
+	bin->all_bin_parse_num += 1;
+}
+
+static int aw_parse_one_of_multi_bins_1_0_0(unsigned int bin_num, int bin_serial_num,
+				      struct aw_bin *bin)
+{
+	int ret = 0;
+	unsigned int bin_start_addr = 0;
+	unsigned int valid_data_len = 0;
+	struct bin_header_info aw_bin_header_info;
+
+	if (bin->info.len < sizeof(struct bin_header_info)) {
+		pr_err("bin_header_info size[%d] overflow file size[%d]\n",
+				(int)sizeof(struct bin_header_info), bin->info.len);
+		return -EINVAL;
+	}
+
+	aw_bin_header_info = bin->header_info[bin->all_bin_parse_num - 1];
+	if (!bin_serial_num) {
+		bin_start_addr = le32_to_cpup((void *)(bin->p_addr + 64));
+		bin->p_addr += (60 + bin_start_addr);
+		bin->header_info[bin->all_bin_parse_num].valid_data_addr =
+			aw_bin_header_info.valid_data_addr + 4 + 8 * bin_num + 60;
+	} else {
+		valid_data_len = aw_bin_header_info.bin_data_len;
+		bin->p_addr += (60 + valid_data_len);
+		bin->header_info[bin->all_bin_parse_num].valid_data_addr =
+		    aw_bin_header_info.valid_data_addr
+		    + aw_bin_header_info.bin_data_len
+		    + 60;
+	}
+
+	ret = aw_parse_bin_header_1_0_0(bin);
+	return ret;
+}
+
+/* Get the number of bins in multi bins, and set a for loop,
+ * loop processing each bin data
+ */
+static int aw_get_multi_bin_header_1_0_0(struct aw_bin *bin)
+{
+	int i = 0;
+	int ret = 0;
+	unsigned int bin_num = 0;
+
+	bin_num = le32_to_cpup((void *)(bin->p_addr + 60));
+	if (bin->multi_bin_parse_num == 1)
+		bin->header_info[bin->all_bin_parse_num].valid_data_addr = 60;
+	aw_get_single_bin_header_1_0_0(bin);
+
+	for (i = 0; i < bin_num; i++) {
+		pr_debug("aw_bin_parse enter multi bin for is %d\n", i);
+		ret = aw_parse_one_of_multi_bins_1_0_0(bin_num, i, bin);
+		if (ret < 0)
+			return ret;
+	}
+	return 0;
+}
+
+/*
+ * If the bin framework header version is 1.0.0,
+ * determine the data type of bin, and then perform different processing
+ * according to the data type
+ * If it is a single bin data type, write the data directly
+ * into the structure array
+ * If it is a multi-bin data type, first obtain the number of bins,
+ * and then recursively call the bin frame header processing function
+ * according to the bin number to process the frame header information
+ * of each bin separately
+ */
+static int aw_parse_bin_header_1_0_0(struct aw_bin *bin)
+{
+	int ret = 0;
+	unsigned int bin_data_type;
+
+	if (bin->info.len < sizeof(struct bin_header_info)) {
+		pr_err("bin_header_info size[%d] overflow file size[%d]\n",
+				(int)sizeof(struct bin_header_info), bin->info.len);
+		return -EINVAL;
+	}
+
+	bin_data_type = le32_to_cpup((void *)(bin->p_addr + 8));
+	pr_debug("aw_bin_parse bin_data_type 0x%x\n", bin_data_type);
+	switch (bin_data_type) {
+	case DATA_TYPE_REGISTER:
+	case DATA_TYPE_DSP_REG:
+	case DATA_TYPE_SOC_APP:
+		/* Divided into two processing methods,
+		 * one is single bin processing,
+		 * and the other is single bin processing in multi bin
+		 */
+		pr_debug("aw_bin_parse enter single bin branch\n");
+		bin->single_bin_parse_num += 1;
+		pr_debug("%s bin->single_bin_parse_num is %d\n", __func__,
+						bin->single_bin_parse_num);
+		if (!bin->multi_bin_parse_num)
+			bin->header_info[bin->all_bin_parse_num].valid_data_addr = 60;
+		aw_get_single_bin_header_1_0_0(bin);
+		break;
+	case DATA_TYPE_MULTI_BINS:
+		/* Get the number of times to enter multi bins */
+		pr_debug("aw_bin_parse enter multi bin branch\n");
+		bin->multi_bin_parse_num += 1;
+		pr_debug("%s bin->multi_bin_parse_num is %d\n", __func__,
+						bin->multi_bin_parse_num);
+		ret = aw_get_multi_bin_header_1_0_0(bin);
+		if (ret < 0)
+			return ret;
+		break;
+	default:
+		pr_debug("%s There is no corresponding type\n", __func__);
+		break;
+	}
+	return 0;
+}
+
+/* get the bin's header version */
+static int aw_check_bin_header_version(struct aw_bin *bin)
+{
+	int ret = 0;
+	unsigned int header_version = 0;
+
+	header_version = le32_to_cpup((void *)(bin->p_addr + 4));
+	pr_debug("aw_bin_parse header_version 0x%x\n", header_version);
+	/* Write data to the corresponding structure array
+	 * according to different formats of the bin frame header version
+	 */
+	switch (header_version) {
+	case HEADER_VERSION_1_0_0:
+		ret = aw_parse_bin_header_1_0_0(bin);
+		return ret;
+	default:
+		pr_err("aw_bin_parse Unrecognized this bin header version\n");
+		return -BIN_HEADER_VER_ERR;
+	}
+}
+
+static int aw_parsing_bin_file(struct aw_bin *bin)
+{
+	int i = 0;
+	int ret = 0;
+
+	if (!bin) {
+		pr_err("aw_bin_parse bin is NULL\n");
+		return -BIN_IS_NULL;
+	}
+	bin->p_addr = bin->info.data;
+	bin->all_bin_parse_num = 0;
+	bin->multi_bin_parse_num = 0;
+	bin->single_bin_parse_num = 0;
+
+	/* filling bins header info */
+	ret = aw_check_bin_header_version(bin);
+	if (ret < 0) {
+		pr_err("aw_bin_parse check bin header version error\n");
+		return ret;
+	}
+	bin->p_addr = NULL;
+
+	/* check bin header info */
+	for (i = 0; i < bin->all_bin_parse_num; i++) {
+		/* check sum */
+		ret = aw_check_sum(bin, i);
+		if (ret < 0) {
+			pr_err("aw_bin_parse check sum data error\n");
+			return ret;
+		}
+		/* check bin data version */
+		ret = aw_check_data_version(bin, i);
+		if (ret < 0) {
+			pr_err("aw_bin_parse check data version error\n");
+			return ret;
+		}
+		/* check valid data */
+		if (bin->header_info[i].bin_data_ver == DATA_VERSION_V1) {
+			/* check register num */
+			switch (bin->header_info[i].bin_data_type) {
+			case DATA_TYPE_REGISTER:
+				ret = aw_check_register_num_v1(bin, i);
+				break;
+			case DATA_TYPE_DSP_REG:
+				ret = aw_check_dsp_reg_num_v1(bin, i);
+				break;
+			case DATA_TYPE_SOC_APP:
+				ret = aw_check_soc_app_num_v1(bin, i);
+				break;
+			default:
+				bin->header_info[i].valid_data_len =
+						bin->header_info[i].bin_data_len;
+				ret = 0;
+				break;
+			}
+			if (ret < 0)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+
+int aw883xx_dev_dsp_data_order(struct aw_device *aw_dev,
+				unsigned char *data, unsigned int data_len)
+{
+	int i = 0;
+	u8 tmp_val = 0;
+
+	if (data_len % 2 != 0) {
+		dev_dbg(aw_dev->dev, "data_len:%d unsupported", data_len);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < data_len; i += 2) {
+		tmp_val = data[i];
+		data[i] = data[i + 1];
+		data[i + 1] = tmp_val;
+	}
+
+	return 0;
+}
+
+static int aw_dev_parse_raw_reg(struct aw_device *aw_dev,
+		unsigned char *data, unsigned int data_len,
+		struct aw_prof_desc *prof_desc)
+{
+	prof_desc->sec_desc[AW_DATA_TYPE_REG].data = data;
+	prof_desc->sec_desc[AW_DATA_TYPE_REG].len = data_len;
+
+	prof_desc->prof_st = AW_PROFILE_OK;
+
+	return 0;
+}
+
+static int aw_dev_parse_raw_dsp_cfg(struct aw_device *aw_dev,
+		unsigned char *data, unsigned int data_len,
+		struct aw_prof_desc *prof_desc)
+{
+	int ret;
+
+	ret = aw883xx_dev_dsp_data_order(aw_dev, data, data_len);
+	if (ret < 0)
+		return ret;
+
+	prof_desc->sec_desc[AW_DATA_TYPE_DSP_CFG].data = data;
+	prof_desc->sec_desc[AW_DATA_TYPE_DSP_CFG].len = data_len;
+
+	prof_desc->prof_st = AW_PROFILE_OK;
+
+	return 0;
+}
+
+static int aw_dev_parse_raw_dsp_fw(struct aw_device *aw_dev,
+		unsigned char *data, unsigned int data_len,
+		struct aw_prof_desc *prof_desc)
+{
+	int ret;
+
+	ret = aw883xx_dev_dsp_data_order(aw_dev, data, data_len);
+	if (ret < 0)
+		return ret;
+
+	prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW].data = data;
+	prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW].len = data_len;
+
+	prof_desc->prof_st = AW_PROFILE_OK;
+
+	return 0;
+}
+
+static int aw_dev_prof_parse_multi_bin(struct aw_device *aw_dev,
+		unsigned char *data, unsigned int data_len,
+		struct aw_prof_desc *prof_desc)
+{
+	struct aw_bin *aw_bin = NULL;
+	int i;
+	int ret;
+
+	aw_bin = devm_kzalloc(aw_dev->dev, data_len + sizeof(struct aw_bin), GFP_KERNEL);
+	if (!aw_bin)
+		return -ENOMEM;
+
+	aw_bin->info.len = data_len;
+	memcpy(aw_bin->info.data, data, data_len);
+
+	ret = aw_parsing_bin_file(aw_bin);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "parse bin failed");
+		goto parse_bin_failed;
+	}
+
+	for (i = 0; i < aw_bin->all_bin_parse_num; i++) {
+		switch (aw_bin->header_info[i].bin_data_type) {
+		case DATA_TYPE_REGISTER:
+			prof_desc->sec_desc[AW_DATA_TYPE_REG].len =
+				aw_bin->header_info[i].valid_data_len;
+			prof_desc->sec_desc[AW_DATA_TYPE_REG].data =
+				data + aw_bin->header_info[i].valid_data_addr;
+			break;
+		case DATA_TYPE_DSP_REG:
+			ret = aw883xx_dev_dsp_data_order(aw_dev,
+					data + aw_bin->header_info[i].valid_data_addr,
+					aw_bin->header_info[i].valid_data_len);
+			if (ret < 0)
+				goto parse_bin_failed;
+
+			prof_desc->sec_desc[AW_DATA_TYPE_DSP_CFG].len =
+					aw_bin->header_info[i].valid_data_len;
+			prof_desc->sec_desc[AW_DATA_TYPE_DSP_CFG].data =
+					data + aw_bin->header_info[i].valid_data_addr;
+			break;
+		case DATA_TYPE_DSP_FW:
+			ret = aw883xx_dev_dsp_data_order(aw_dev,
+					data + aw_bin->header_info[i].valid_data_addr,
+					aw_bin->header_info[i].valid_data_len);
+			if (ret < 0)
+				goto parse_bin_failed;
+
+			prof_desc->fw_ver = aw_bin->header_info[i].app_version;
+			prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW].len =
+					aw_bin->header_info[i].valid_data_len;
+			prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW].data =
+					data + aw_bin->header_info[i].valid_data_addr;
+			break;
+		default:
+			dev_dbg(aw_dev->dev, "bin_data_type not found");
+			break;
+		}
+	}
+	devm_kfree(aw_dev->dev, aw_bin);
+	aw_bin = NULL;
+	prof_desc->prof_st = AW_PROFILE_OK;
+	return 0;
+
+parse_bin_failed:
+	devm_kfree(aw_dev->dev, aw_bin);
+	aw_bin = NULL;
+	return ret;
+}
+
+static int aw_dev_parse_data_by_sec_type(struct aw_device *aw_dev, struct aw_cfg_hdr *cfg_hdr,
+			struct aw_cfg_dde *cfg_dde, struct aw_prof_desc *scene_prof_desc)
+{
+	switch (cfg_dde->data_type) {
+	case ACF_SEC_TYPE_REG:
+		return aw_dev_parse_raw_reg(aw_dev,
+				(u8 *)cfg_hdr + cfg_dde->data_offset,
+				cfg_dde->data_size, scene_prof_desc);
+	case ACF_SEC_TYPE_DSP_CFG:
+		return aw_dev_parse_raw_dsp_cfg(aw_dev,
+				(u8 *)cfg_hdr + cfg_dde->data_offset,
+				cfg_dde->data_size, scene_prof_desc);
+	case ACF_SEC_TYPE_DSP_FW:
+		return aw_dev_parse_raw_dsp_fw(aw_dev,
+				(u8 *)cfg_hdr + cfg_dde->data_offset,
+				cfg_dde->data_size, scene_prof_desc);
+	case ACF_SEC_TYPE_MUTLBIN:
+		return aw_dev_prof_parse_multi_bin(aw_dev,
+				(u8 *)cfg_hdr + cfg_dde->data_offset,
+				cfg_dde->data_size, scene_prof_desc);
+	default:
+		dev_dbg(aw_dev->dev, "%s cfg_dde->data_type = %d\n", __func__, cfg_dde->data_type);
+		break;
+	}
+	return 0;
+}
+
+static int aw_dev_parse_dev_type(struct aw_device *aw_dev,
+		struct aw_cfg_hdr *prof_hdr, struct aw_all_prof_info *all_prof_info)
+{
+	int i = 0;
+	int ret;
+	int sec_num = 0;
+	struct aw_cfg_dde *cfg_dde =
+		(struct aw_cfg_dde *)((char *)prof_hdr + prof_hdr->a_hdr_offset);
+
+	for (i = 0; i < prof_hdr->a_ddt_num; i++) {
+		if ((aw_dev->i2c->adapter->nr == cfg_dde[i].dev_bus) &&
+			(aw_dev->i2c->addr == cfg_dde[i].dev_addr) &&
+			(cfg_dde[i].type == AW_DEV_TYPE_ID)) {
+			if (cfg_dde[i].data_type != ACF_SEC_TYPE_MONITOR) {
+				if (cfg_dde[i].dev_profile >= AW_PROFILE_MAX) {
+					dev_err(aw_dev->dev, "dev_profile [%d] overflow",
+						cfg_dde[i].dev_profile);
+					return -EINVAL;
+				}
+				ret = aw_dev_parse_data_by_sec_type(aw_dev, prof_hdr, &cfg_dde[i],
+					&all_prof_info->prof_desc[cfg_dde[i].dev_profile]);
+				if (ret < 0) {
+					dev_err(aw_dev->dev, "parse failed");
+					return ret;
+				}
+				sec_num++;
+			}
+		}
+	}
+
+	if (sec_num == 0) {
+		dev_dbg(aw_dev->dev, "get dev type num is %d, please use default",
+					sec_num);
+		return AW_DEV_TYPE_NONE;
+	}
+
+	return AW_DEV_TYPE_OK;
+}
+
+static int aw_dev_parse_dev_default_type(struct aw_device *aw_dev,
+		struct aw_cfg_hdr *prof_hdr, struct aw_all_prof_info *all_prof_info)
+{
+	int i = 0;
+	int ret;
+	int sec_num = 0;
+	struct aw_cfg_dde *cfg_dde =
+		(struct aw_cfg_dde *)((char *)prof_hdr + prof_hdr->a_hdr_offset);
+
+	for (i = 0; i < prof_hdr->a_ddt_num; i++) {
+		if ((aw_dev->channel == cfg_dde[i].dev_index) &&
+			(cfg_dde[i].type == AW_DEV_DEFAULT_TYPE_ID)) {
+			if (cfg_dde[i].data_type != ACF_SEC_TYPE_MONITOR) {
+				if (cfg_dde[i].dev_profile >= AW_PROFILE_MAX) {
+					dev_err(aw_dev->dev, "dev_profile [%d] overflow",
+						cfg_dde[i].dev_profile);
+					return -EINVAL;
+				}
+				ret = aw_dev_parse_data_by_sec_type(aw_dev, prof_hdr, &cfg_dde[i],
+					&all_prof_info->prof_desc[cfg_dde[i].dev_profile]);
+				if (ret < 0) {
+					dev_err(aw_dev->dev, "parse failed");
+					return ret;
+				}
+				sec_num++;
+			}
+		}
+	}
+
+	if (sec_num == 0) {
+		dev_err(aw_dev->dev, "get dev default type failed, get num[%d]", sec_num);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int aw_dev_cfg_get_vaild_prof(struct aw_device *aw_dev,
+				struct aw_all_prof_info all_prof_info)
+{
+	int i;
+	int num = 0;
+	struct aw_sec_data_desc *sec_desc = NULL;
+	struct aw_prof_desc *prof_desc = all_prof_info.prof_desc;
+	struct aw_prof_info *prof_info = &aw_dev->prof_info;
+
+	for (i = 0; i < AW_PROFILE_MAX; i++) {
+		if (prof_desc[i].prof_st == AW_PROFILE_OK) {
+			sec_desc = prof_desc[i].sec_desc;
+			if ((sec_desc[AW_DATA_TYPE_REG].data != NULL) &&
+				(sec_desc[AW_DATA_TYPE_REG].len != 0) &&
+				(sec_desc[AW_DATA_TYPE_DSP_CFG].data != NULL) &&
+				(sec_desc[AW_DATA_TYPE_DSP_CFG].len != 0) &&
+				(sec_desc[AW_DATA_TYPE_DSP_FW].data != NULL) &&
+				(sec_desc[AW_DATA_TYPE_DSP_FW].len != 0)) {
+				prof_info->count++;
+			}
+		}
+	}
+
+	dev_dbg(aw_dev->dev, "get valid profile:%d", aw_dev->prof_info.count);
+
+	if (!prof_info->count) {
+		dev_err(aw_dev->dev, "no profile data");
+		return -EPERM;
+	}
+
+	prof_info->prof_desc = devm_kzalloc(aw_dev->dev,
+					prof_info->count * sizeof(struct aw_prof_desc),
+					GFP_KERNEL);
+	if (!prof_info->prof_desc) {
+		dev_err(aw_dev->dev, "prof_desc kzalloc failed");
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < AW_PROFILE_MAX; i++) {
+		if (prof_desc[i].prof_st == AW_PROFILE_OK) {
+			sec_desc = prof_desc[i].sec_desc;
+			if ((sec_desc[AW_DATA_TYPE_REG].data != NULL) &&
+				(sec_desc[AW_DATA_TYPE_REG].len != 0) &&
+				(sec_desc[AW_DATA_TYPE_DSP_CFG].data != NULL) &&
+				(sec_desc[AW_DATA_TYPE_DSP_CFG].len != 0) &&
+				(sec_desc[AW_DATA_TYPE_DSP_FW].data != NULL) &&
+				(sec_desc[AW_DATA_TYPE_DSP_FW].len != 0)) {
+				if (num >= prof_info->count) {
+					dev_err(aw_dev->dev, "get scene num[%d] overflow count[%d]",
+						num, prof_info->count);
+					return -ENOMEM;
+				}
+				prof_info->prof_desc[num] = prof_desc[i];
+				prof_info->prof_desc[num].id = i;
+				num++;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int aw_dev_load_cfg_by_hdr(struct aw_device *aw_dev,
+		struct aw_cfg_hdr *prof_hdr)
+{
+	int ret;
+	struct aw_all_prof_info *all_prof_info;
+
+	all_prof_info = devm_kzalloc(aw_dev->dev, sizeof(struct aw_all_prof_info), GFP_KERNEL);
+	if (!all_prof_info)
+		return -ENOMEM;
+
+	ret = aw_dev_parse_dev_type(aw_dev, prof_hdr, all_prof_info);
+	if (ret < 0) {
+		goto exit;
+	} else if (ret == AW_DEV_TYPE_NONE) {
+		dev_dbg(aw_dev->dev, "get dev type num is 0, parse default dev");
+		ret = aw_dev_parse_dev_default_type(aw_dev, prof_hdr, all_prof_info);
+		if (ret < 0)
+			goto exit;
+	}
+
+	ret = aw_dev_cfg_get_vaild_prof(aw_dev, *all_prof_info);
+	if (ret < 0)
+		goto exit;
+
+	aw_dev->prof_info.prof_name_list = profile_name;
+exit:
+	devm_kfree(aw_dev->dev, all_prof_info);
+	return ret;
+}
+
+static int aw_dev_create_prof_name_list_v_1_0_0_0(struct aw_device *aw_dev)
+{
+	struct aw_prof_info *prof_info = &aw_dev->prof_info;
+	struct aw_prof_desc *prof_desc = prof_info->prof_desc;
+	int i;
+
+	if (!prof_desc) {
+		dev_err(aw_dev->dev, "prof_desc is NULL");
+		return -EINVAL;
+	}
+
+	prof_info->prof_name_list = devm_kzalloc(aw_dev->dev,
+					prof_info->count * PROFILE_STR_MAX,
+					GFP_KERNEL);
+	if (!prof_info->prof_name_list) {
+		dev_err(aw_dev->dev, "prof_name_list devm_kzalloc failed");
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < prof_info->count; i++) {
+		prof_desc[i].id = i;
+		prof_info->prof_name_list[i] = prof_desc[i].prf_str;
+		dev_dbg(aw_dev->dev, "prof name is %s", prof_info->prof_name_list[i]);
+	}
+
+	return 0;
+}
+
+static int aw_get_dde_type_info(struct aw_device *aw_dev, struct aw_container *aw_cfg)
+{
+	int i;
+	int dev_num = 0;
+	int default_num = 0;
+	struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
+	struct aw_cfg_dde_v_1_0_0_0 *cfg_dde =
+		(struct aw_cfg_dde_v_1_0_0_0 *)(aw_cfg->data + cfg_hdr->a_hdr_offset);
+
+	for (i = 0; i < cfg_hdr->a_ddt_num; i++) {
+		if (cfg_dde[i].type == AW_DEV_TYPE_ID)
+			dev_num++;
+
+		if (cfg_dde[i].type == AW_DEV_DEFAULT_TYPE_ID)
+			default_num++;
+	}
+
+	if (dev_num != 0) {
+		aw_dev->prof_info.prof_type = AW_DEV_TYPE_ID;
+	} else if (default_num != 0) {
+		aw_dev->prof_info.prof_type = AW_DEV_DEFAULT_TYPE_ID;
+	} else {
+		dev_err(aw_dev->dev, "can't find scene");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int aw_get_dev_scene_count_v_1_0_0_0(struct aw_device *aw_dev, struct aw_container *aw_cfg,
+						unsigned int *scene_num)
+{
+	int i;
+	struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
+	struct aw_cfg_dde_v_1_0_0_0 *cfg_dde =
+		(struct aw_cfg_dde_v_1_0_0_0 *)(aw_cfg->data + cfg_hdr->a_hdr_offset);
+	for (i = 0; i < cfg_hdr->a_ddt_num; ++i) {
+		if ((cfg_dde[i].data_type == ACF_SEC_TYPE_MUTLBIN) &&
+			(aw_dev->chip_id == cfg_dde[i].chip_id) &&
+			((aw_dev->i2c->adapter->nr == cfg_dde[i].dev_bus) &&
+			(aw_dev->i2c->addr == cfg_dde[i].dev_addr)))
+			(*scene_num)++;
+	}
+
+	return 0;
+}
+
+static int aw_get_default_scene_count_v_1_0_0_0(struct aw_device *aw_dev,
+						struct aw_container *aw_cfg,
+						unsigned int *scene_num)
+{
+	int i;
+	struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
+	struct aw_cfg_dde_v_1_0_0_0 *cfg_dde =
+		(struct aw_cfg_dde_v_1_0_0_0 *)(aw_cfg->data + cfg_hdr->a_hdr_offset);
+
+	for (i = 0; i < cfg_hdr->a_ddt_num; ++i) {
+		if ((cfg_dde[i].data_type == ACF_SEC_TYPE_MUTLBIN) &&
+			(aw_dev->chip_id == cfg_dde[i].chip_id) &&
+			(aw_dev->channel == cfg_dde[i].dev_index))
+			(*scene_num)++;
+	}
+
+	return 0;
+}
+
+static int aw_dev_parse_scene_count_v_1_0_0_0(struct aw_device *aw_dev,
+							struct aw_container *aw_cfg,
+							unsigned int *count)
+{
+	int ret;
+
+	ret = aw_get_dde_type_info(aw_dev, aw_cfg);
+	if (ret < 0)
+		return ret;
+
+	switch (aw_dev->prof_info.prof_type) {
+	case AW_DEV_TYPE_ID:
+		ret = aw_get_dev_scene_count_v_1_0_0_0(aw_dev, aw_cfg, count);
+		break;
+	case AW_DEV_DEFAULT_TYPE_ID:
+		ret = aw_get_default_scene_count_v_1_0_0_0(aw_dev, aw_cfg, count);
+		break;
+	default:
+		dev_err(aw_dev->dev, "unsupported prof_type[%x]",
+			aw_dev->prof_info.prof_type);
+		ret = -EINVAL;
+		break;
+	}
+
+	dev_dbg(aw_dev->dev, "scene count is %d", (*count));
+	return ret;
+}
+
+static int aw_dev_parse_data_by_sec_type_v_1_0_0_0(struct aw_device *aw_dev,
+							struct aw_cfg_hdr *prof_hdr,
+							struct aw_cfg_dde_v_1_0_0_0 *cfg_dde,
+							int *cur_scene_id)
+{
+	int ret;
+	struct aw_prof_info *prof_info = &aw_dev->prof_info;
+
+	switch (cfg_dde->data_type) {
+	case ACF_SEC_TYPE_MUTLBIN:
+		ret = aw_dev_prof_parse_multi_bin(aw_dev,
+					(u8 *)prof_hdr + cfg_dde->data_offset,
+					cfg_dde->data_size, &prof_info->prof_desc[*cur_scene_id]);
+		if (ret < 0) {
+			dev_err(aw_dev->dev, "parse multi bin failed");
+			return ret;
+		}
+		prof_info->prof_desc[*cur_scene_id].prf_str = cfg_dde->dev_profile_str;
+		prof_info->prof_desc[*cur_scene_id].id = cfg_dde->dev_profile;
+		(*cur_scene_id)++;
+		break;
+	default:
+		dev_err(aw_dev->dev, "unsupported SEC_TYPE [%d]", cfg_dde->data_type);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int aw_dev_parse_dev_type_v_1_0_0_0(struct aw_device *aw_dev,
+		struct aw_cfg_hdr *prof_hdr)
+{
+	int i = 0;
+	int ret;
+	int cur_scene_id = 0;
+	struct aw_cfg_dde_v_1_0_0_0 *cfg_dde =
+		(struct aw_cfg_dde_v_1_0_0_0 *)((char *)prof_hdr + prof_hdr->a_hdr_offset);
+
+	for (i = 0; i < prof_hdr->a_ddt_num; i++) {
+		if ((aw_dev->i2c->adapter->nr == cfg_dde[i].dev_bus) &&
+			(aw_dev->i2c->addr == cfg_dde[i].dev_addr) &&
+			(aw_dev->chip_id == cfg_dde[i].chip_id)) {
+			ret = aw_dev_parse_data_by_sec_type_v_1_0_0_0(aw_dev, prof_hdr,
+							&cfg_dde[i], &cur_scene_id);
+			if (ret < 0) {
+				dev_err(aw_dev->dev, "parse failed");
+				return ret;
+			}
+		}
+	}
+
+	if (cur_scene_id == 0) {
+		dev_err(aw_dev->dev, "get dev type failed, get num [%d]", cur_scene_id);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int aw_dev_parse_default_type_v_1_0_0_0(struct aw_device *aw_dev,
+		struct aw_cfg_hdr *prof_hdr)
+{
+	int i = 0;
+	int ret;
+	int cur_scene_id = 0;
+	struct aw_cfg_dde_v_1_0_0_0 *cfg_dde =
+		(struct aw_cfg_dde_v_1_0_0_0 *)((char *)prof_hdr + prof_hdr->a_hdr_offset);
+
+	for (i = 0; i < prof_hdr->a_ddt_num; i++) {
+		if ((aw_dev->channel == cfg_dde[i].dev_index) &&
+			(aw_dev->chip_id == cfg_dde[i].chip_id)) {
+			ret = aw_dev_parse_data_by_sec_type_v_1_0_0_0(aw_dev, prof_hdr,
+							&cfg_dde[i], &cur_scene_id);
+			if (ret < 0) {
+				dev_err(aw_dev->dev, "parse failed");
+				return ret;
+			}
+		}
+	}
+
+	if (cur_scene_id == 0) {
+		dev_err(aw_dev->dev, "get dev default type failed, get num[%d]", cur_scene_id);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int aw_dev_parse_by_hdr_v_1_0_0_0(struct aw_device *aw_dev,
+		struct aw_cfg_hdr *cfg_hdr)
+{
+	int ret = 0;
+
+	switch (aw_dev->prof_info.prof_type) {
+	case AW_DEV_TYPE_ID:
+		ret = aw_dev_parse_dev_type_v_1_0_0_0(aw_dev, cfg_hdr);
+		break;
+	case AW_DEV_DEFAULT_TYPE_ID:
+		ret = aw_dev_parse_default_type_v_1_0_0_0(aw_dev, cfg_hdr);
+		break;
+	default:
+		dev_err(aw_dev->dev, "prof type matched failed, get num[%d]",
+			aw_dev->prof_info.prof_type);
+		ret =  -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static int aw_dev_load_cfg_by_hdr_v_1_0_0_0(struct aw_device *aw_dev,
+									struct aw_container *aw_cfg)
+{
+	struct aw_prof_info *prof_info = &aw_dev->prof_info;
+	struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
+	int ret;
+
+	ret = aw_dev_parse_scene_count_v_1_0_0_0(aw_dev, aw_cfg, &prof_info->count);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "get scene count failed");
+		return ret;
+	}
+
+	prof_info->prof_desc = devm_kzalloc(aw_dev->dev,
+					prof_info->count * sizeof(struct aw_prof_desc),
+					GFP_KERNEL);
+	if (!prof_info->prof_desc)
+		return -ENOMEM;
+
+	ret = aw_dev_parse_by_hdr_v_1_0_0_0(aw_dev, cfg_hdr);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, " failed");
+		return ret;
+	}
+
+	ret = aw_dev_create_prof_name_list_v_1_0_0_0(aw_dev);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "create prof name list failed");
+		return ret;
+	}
+
+	return 0;
+}
+
+int aw883xx_dev_cfg_load(struct aw_device *aw_dev, struct aw_container *aw_cfg)
+{
+	struct aw_cfg_hdr *cfg_hdr = NULL;
+	int ret;
+
+	cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
+
+	switch (cfg_hdr->a_hdr_version) {
+	case AW_CFG_HDR_VER_0_0_0_1:
+		ret = aw_dev_load_cfg_by_hdr(aw_dev, cfg_hdr);
+		if (ret < 0) {
+			dev_err(aw_dev->dev, "hdr_cersion[0x%x] parse failed",
+						cfg_hdr->a_hdr_version);
+			return ret;
+		}
+		break;
+	case AW_CFG_HDR_VER_1_0_0_0:
+		ret = aw_dev_load_cfg_by_hdr_v_1_0_0_0(aw_dev, aw_cfg);
+		if (ret < 0) {
+			dev_err(aw_dev->dev, "hdr_cersion[0x%x] parse failed",
+						cfg_hdr->a_hdr_version);
+			return ret;
+		}
+		break;
+	default:
+		dev_err(aw_dev->dev, "unsupported hdr_version [0x%x]", cfg_hdr->a_hdr_version);
+		return -EINVAL;
+	}
+	aw_dev->fw_status = AW_DEV_FW_OK;
+	return 0;
+}
+
+static unsigned char aw_dev_crc8_check(unsigned char *data, unsigned int data_size)
+{
+	u8 crc_value = 0x00;
+	u8 pdatabuf = 0;
+	int i;
+
+	while (data_size--) {
+		pdatabuf = *data++;
+		for (i = 0; i < 8; i++) {
+			/*if the lowest bit is 1*/
+			if ((crc_value ^ (pdatabuf)) & 0x01) {
+				/*Xor multinomial*/
+				crc_value ^= 0x18;
+				crc_value >>= 1;
+				crc_value |= 0x80;
+			} else {
+				crc_value >>= 1;
+			}
+			pdatabuf >>= 1;
+		}
+	}
+	return crc_value;
+}
+
+static int aw_dev_check_cfg_by_hdr(struct aw_container *aw_cfg)
+{
+	struct aw_cfg_hdr *cfg_hdr = NULL;
+	struct aw_cfg_dde *cfg_dde = NULL;
+	unsigned int end_data_offset = 0;
+	unsigned int act_data = 0;
+	unsigned int hdr_ddt_len = 0;
+	u8 act_crc8 = 0;
+	int i;
+
+	cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
+	/*check file type id is awinic acf file*/
+	if (cfg_hdr->a_id != ACF_FILE_ID) {
+		pr_err("not acf type file");
+		return -EINVAL;
+	}
+
+	hdr_ddt_len = cfg_hdr->a_hdr_offset + cfg_hdr->a_ddt_size;
+	if (hdr_ddt_len > aw_cfg->len) {
+		pr_err("hdrlen with ddt_len [%d] overflow file size[%d]",
+		cfg_hdr->a_hdr_offset, aw_cfg->len);
+		return -EINVAL;
+	}
+
+	/*check data size*/
+	cfg_dde = (struct aw_cfg_dde *)((char *)aw_cfg->data + cfg_hdr->a_hdr_offset);
+	act_data += hdr_ddt_len;
+	for (i = 0; i < cfg_hdr->a_ddt_num; i++)
+		act_data += cfg_dde[i].data_size;
+
+	if (act_data != aw_cfg->len) {
+		pr_err("act_data[%d] not equal to file size[%d]!",
+			act_data, aw_cfg->len);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < cfg_hdr->a_ddt_num; i++) {
+		/* data check */
+		end_data_offset = cfg_dde[i].data_offset + cfg_dde[i].data_size;
+		if (end_data_offset > aw_cfg->len) {
+			pr_err("a_ddt_num[%d] end_data_offset[%d] overflow file size[%d]",
+				i, end_data_offset, aw_cfg->len);
+			return -EINVAL;
+		}
+
+		/* crc check */
+		act_crc8 = aw_dev_crc8_check(aw_cfg->data + cfg_dde[i].data_offset,
+									cfg_dde[i].data_size);
+		if (act_crc8 != cfg_dde[i].data_crc) {
+			pr_err("a_ddt_num[%d] crc8 check failed, act_crc8:0x%x != data_crc 0x%x",
+				i, (u32)act_crc8, cfg_dde[i].data_crc);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static int aw_dev_check_acf_by_hdr_v_1_0_0_0(struct aw_container *aw_cfg)
+{
+	struct aw_cfg_hdr *cfg_hdr = NULL;
+	struct aw_cfg_dde_v_1_0_0_0 *cfg_dde = NULL;
+	unsigned int end_data_offset = 0;
+	unsigned int act_data = 0;
+	unsigned int hdr_ddt_len = 0;
+	u8 act_crc8 = 0;
+	int i;
+
+	cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
+
+	/*check file type id is awinic acf file*/
+	if (cfg_hdr->a_id != ACF_FILE_ID) {
+		pr_err("not acf type file");
+		return -EINVAL;
+	}
+
+	hdr_ddt_len = cfg_hdr->a_hdr_offset + cfg_hdr->a_ddt_size;
+	if (hdr_ddt_len > aw_cfg->len) {
+		pr_err("hdrlen with ddt_len [%d] overflow file size[%d]",
+		cfg_hdr->a_hdr_offset, aw_cfg->len);
+		return -EINVAL;
+	}
+
+	/*check data size*/
+	cfg_dde = (struct aw_cfg_dde_v_1_0_0_0 *)((char *)aw_cfg->data + cfg_hdr->a_hdr_offset);
+	act_data += hdr_ddt_len;
+	for (i = 0; i < cfg_hdr->a_ddt_num; i++)
+		act_data += cfg_dde[i].data_size;
+
+	if (act_data != aw_cfg->len) {
+		pr_err("act_data[%d] not equal to file size[%d]!",
+			act_data, aw_cfg->len);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < cfg_hdr->a_ddt_num; i++) {
+		/* data check */
+		end_data_offset = cfg_dde[i].data_offset + cfg_dde[i].data_size;
+		if (end_data_offset > aw_cfg->len) {
+			pr_err("a_ddt_num[%d] end_data_offset[%d] overflow file size[%d]",
+				i, end_data_offset, aw_cfg->len);
+			return -EINVAL;
+		}
+
+		/* crc check */
+		act_crc8 = aw_dev_crc8_check(aw_cfg->data + cfg_dde[i].data_offset,
+							cfg_dde[i].data_size);
+		if (act_crc8 != cfg_dde[i].data_crc) {
+			pr_err("a_ddt_num[%d] crc8 check failed, act_crc8:0x%x != data_crc 0x%x",
+				i, (u32)act_crc8, cfg_dde[i].data_crc);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+
+}
+
+int aw883xx_dev_load_acf_check(struct aw_container *aw_cfg)
+{
+	struct aw_cfg_hdr *cfg_hdr = NULL;
+
+	if (!aw_cfg) {
+		pr_err("aw_prof is NULL");
+		return -ENOMEM;
+	}
+
+	if (aw_cfg->len < sizeof(struct aw_cfg_hdr)) {
+		pr_err("cfg hdr size[%d] overflow file size[%d]",
+			aw_cfg->len, (int)sizeof(struct aw_cfg_hdr));
+		return -EINVAL;
+	}
+
+	cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
+	switch (cfg_hdr->a_hdr_version) {
+	case AW_CFG_HDR_VER_0_0_0_1:
+		return aw_dev_check_cfg_by_hdr(aw_cfg);
+	case AW_CFG_HDR_VER_1_0_0_0:
+		return aw_dev_check_acf_by_hdr_v_1_0_0_0(aw_cfg);
+	default:
+		pr_err("unsupported hdr_version [0x%x]", cfg_hdr->a_hdr_version);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int aw883xx_dev_get_profile_count(struct aw_device *aw_dev)
+{
+	if (!aw_dev) {
+		pr_err("aw_dev is NULL");
+		return -ENOMEM;
+	}
+
+	return aw_dev->prof_info.count;
+}
+
+int aw883xx_dev_check_profile_index(struct aw_device *aw_dev, int index)
+{
+	if ((index >= aw_dev->prof_info.count) || (index < 0))
+		return -EINVAL;
+	else
+		return 0;
+}
+
+int aw883xx_dev_get_profile_index(struct aw_device *aw_dev)
+{
+	return aw_dev->set_prof;
+}
+
+int aw883xx_dev_set_profile_index(struct aw_device *aw_dev, int index)
+{
+	struct aw_prof_desc *prof_desc = NULL;
+
+	if ((index < aw_dev->prof_info.count) && (index >= 0)) {
+		aw_dev->set_prof = index;
+		prof_desc = &aw_dev->prof_info.prof_desc[index];
+
+		dev_dbg(aw_dev->dev, "set prof[%s]",
+			aw_dev->prof_info.prof_name_list[prof_desc->id]);
+	} else {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+char *aw_dev_get_prof_name(struct aw_device *aw_dev, int index)
+{
+	struct aw_prof_desc *prof_desc = NULL;
+	struct aw_prof_info *prof_info = &aw_dev->prof_info;
+
+	if ((index >= aw_dev->prof_info.count) || (index < 0)) {
+		dev_err(aw_dev->dev, "index[%d] overflow count[%d]",
+			index, aw_dev->prof_info.count);
+		return NULL;
+	}
+
+	prof_desc = &aw_dev->prof_info.prof_desc[index];
+
+	return prof_info->prof_name_list[prof_desc->id];
+}
+
+int aw883xx_dev_get_prof_data(struct aw_device *aw_dev, int index,
+			struct aw_prof_desc **prof_desc)
+{
+	if ((index >= aw_dev->prof_info.count) || (index < 0)) {
+		dev_err(aw_dev->dev, "%s: index[%d] overflow count[%d]\n",
+			__func__, index, aw_dev->prof_info.count);
+		return -EINVAL;
+	}
+
+	*prof_desc = &aw_dev->prof_info.prof_desc[index];
+
+	return 0;
+}
+
diff --git a/sound/soc/codecs/aw883xx/aw883xx_bin_parse.h b/sound/soc/codecs/aw883xx/aw883xx_bin_parse.h
new file mode 100644
index 000000000000..7f5ce0b1f899
--- /dev/null
+++ b/sound/soc/codecs/aw883xx/aw883xx_bin_parse.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * aw883xx.c --  ALSA Soc AW883XX codec support
+ *
+ * Copyright (c) 2022 AWINIC Technology CO., LTD
+ *
+ * Author: Bruce zhao <zhaolei@awinic.com>
+ */
+
+#ifndef __AW883XX_BIN_PARSE_H__
+#define __AW883XX_BIN_PARSE_H__
+
+#include "aw883xx_device.h"
+
+#define BIN_NUM_MAX				(100)
+#define HEADER_LEN				(60)
+#define CHECK_SUM_OFFSET		(0)
+#define HEADER_VER_OFFSET		(4)
+#define	BIN_DATA_TYPE_OFFSET	(8)
+#define	BIN_DATA_VER_OFFSET		(12)
+#define	BIN_DATA_LEN_OFFSET		(16)
+#define	UI_VER_OFFSET			(20)
+#define CHIP_TYPE_OFFSET		(24)
+#define	REG_BYTE_LEN_OFFSET		(32)
+#define	DATA_BYTE_LEN_OFFSET	(36)
+#define	DEVICE_ADDR_OFFSET		(40)
+
+#define AW_FW_CHECK_PART		(10)
+
+/*
+ * header information
+ */
+enum return_enum {
+	BIN_HEADER_VER_ERR = 1,
+	BIN_DATA_TYPE_ERR = 2,
+	BIN_DATA_LEN_ERR = 3,
+	DATA_VER_ERR = 4,
+	REG_NUM_ERR = 5,
+	DSP_REG_NUM_ERR = 6,
+	SOC_APP_NUM_ERR = 7,
+	BIN_IS_NULL = 8,
+};
+
+enum bin_header_version_enum {
+	HEADER_VERSION_1_0_0 = 0x01000000,
+};
+
+enum data_type_enum {
+	DATA_TYPE_REGISTER = 0x00000000,
+	DATA_TYPE_DSP_REG = 0x00000010,
+	DATA_TYPE_DSP_CFG = 0x00000011,
+	DATA_TYPE_SOC_REG = 0x00000020,
+	DATA_TYPE_SOC_APP = 0x00000021,
+	DATA_TYPE_DSP_FW = DATA_TYPE_SOC_APP,
+	DATA_TYPE_MULTI_BINS = 0x00002000,
+};
+
+/**
+ * @DATA_VERSION_V1：default little edian
+ */
+enum data_version_enum {
+	DATA_VERSION_V1 = 0X00000001,
+	DATA_VERSION_MAX,
+};
+
+/**
+ * @header_len: Frame header length
+ * @check_sum: Frame header information-Checksum
+ * @header_ver: Frame header information-Frame header version
+ * @bin_data_type: Frame header information-Data type
+ * @bin_data_ver: Frame header information-Data version
+ * @bin_data_len: Frame header information-Data length
+ * @ui_ver: Frame header information-ui version
+ * @chip_type[8]: Frame header information-chip type
+ * @reg_byte_len: Frame header information-reg byte len
+ * @data_byte_len: Frame header information-data byte len
+ * @device_addr: Frame header information-device addr
+ * @valid_data_len: Length of valid data obtained after parsing
+ * @valid_data_addr: The offset address of the valid data obtained
+ *                   after parsing relative to info
+ * @reg_num: The number of registers obtained after parsing
+ * @reg_data_byte_len: The byte length of the register obtained after parsing
+ * @download_addr: The starting address or download address obtained
+ *                 after parsing
+ * @app_version: The software version number obtained after parsing
+ */
+struct bin_header_info {
+	unsigned int header_len;
+	unsigned int check_sum;
+	unsigned int header_ver;
+	unsigned int bin_data_type;
+	unsigned int bin_data_ver;
+	unsigned int bin_data_len;
+	unsigned int ui_ver;
+	unsigned char chip_type[8];
+	unsigned int reg_byte_len;
+	unsigned int data_byte_len;
+	unsigned int device_addr;
+	unsigned int valid_data_len;
+	unsigned int valid_data_addr;
+
+	unsigned int reg_num;
+	unsigned int reg_data_byte_len;
+	unsigned int download_addr;
+	unsigned int app_version;
+};
+
+/*
+ * @len: The size of the bin file obtained from the firmware
+ * @data[]: Store the bin file obtained from the firmware
+ */
+struct bin_container {
+	unsigned int len;
+	unsigned char data[];
+};
+
+/**
+ * @p_addr: Offset pointer (backward offset pointer to obtain frame header
+ *          information and important information)
+ * @all_bin_parse_num: The number of all bin files
+ * @multi_bin_parse_num: The number of single bin files
+ * @single_bin_parse_num: The number of multiple bin files
+ * @header_info[BIN_NUM_MAX]: Frame header information and other important data
+ *                            obtained after parsing
+ * @info: Obtained bin file data that needs to be parsed
+ */
+struct aw_bin {
+	unsigned char *p_addr;
+	unsigned int all_bin_parse_num;
+	unsigned int multi_bin_parse_num;
+	unsigned int single_bin_parse_num;
+	struct bin_header_info header_info[BIN_NUM_MAX];
+	struct bin_container info;
+};
+
+/*******************awinic audio parse acf***********************/
+int aw883xx_dev_dsp_data_order(struct aw_device *aw_dev,
+				unsigned char *data, unsigned int data_len);
+int aw883xx_dev_get_prof_data(struct aw_device *aw_dev, int index,
+			struct aw_prof_desc **prof_desc);
+char *aw_dev_get_prof_name(struct aw_device *aw_dev, int index);
+int aw883xx_dev_set_profile_index(struct aw_device *aw_dev, int index);
+int aw883xx_dev_get_profile_index(struct aw_device *aw_dev);
+int aw883xx_dev_check_profile_index(struct aw_device *aw_dev, int index);
+int aw883xx_dev_get_profile_count(struct aw_device *aw_dev);
+int aw883xx_dev_cfg_load(struct aw_device *aw_dev, struct aw_container *aw_cfg);
+int aw883xx_dev_load_acf_check(struct aw_container *aw_cfg);
+
+#endif
-- 
2.38.1

[PATCH V6 3/5] ASoC: codecs: aw883xx chip control logic, such as power on and off

[wangweidong.a]

From: Weidong Wang <wangweidong.a@awinic.com>

The Awinic AW883XX is an I2S/TDM input, high efficiency
digital Smart K audio amplifier with an integrated 10.25V
smart boost convert

Signed-off-by: Nick Li <liweilei@awinic.com>
Signed-off-by: Bruce zhao <zhaolei@awinic.com>
Signed-off-by: Weidong Wang <wangweidong.a@awinic.com>
---
 sound/soc/codecs/aw883xx/aw883xx_device.c | 1613 +++++++++++++++++++++
 sound/soc/codecs/aw883xx/aw883xx_device.h |  537 +++++++
 2 files changed, 2150 insertions(+)
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx_device.c
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx_device.h

diff --git a/sound/soc/codecs/aw883xx/aw883xx_device.c b/sound/soc/codecs/aw883xx/aw883xx_device.c
new file mode 100644
index 000000000000..f4419e1a2fed
--- /dev/null
+++ b/sound/soc/codecs/aw883xx/aw883xx_device.c
@@ -0,0 +1,1613 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * aw883xx.c --  ALSA Soc AW883XX codec support
+ *
+ * Copyright (c) 2022 AWINIC Technology CO., LTD
+ *
+ * Author: Bruce zhao <zhaolei@awinic.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/debugfs.h>
+#include <linux/firmware.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/syscalls.h>
+#include <linux/version.h>
+#include <linux/uaccess.h>
+#include <linux/workqueue.h>
+#include <sound/core.h>
+#include <sound/control.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include "aw883xx_data_type.h"
+#include "aw883xx_device.h"
+#include "aw883xx_bin_parse.h"
+
+int aw883xx_dev_set_volume(struct aw_device *aw_dev, unsigned short set_vol)
+{
+	u16 hw_vol = 0;
+	int ret = -1;
+	struct aw_volume_desc *vol_desc = &aw_dev->volume_desc;
+
+	hw_vol = set_vol + vol_desc->init_volume;
+
+	ret = aw_dev->ops.aw_set_hw_volume(aw_dev, hw_vol);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "set volume failed");
+		return ret;
+	}
+
+	return 0;
+}
+
+int aw883xx_dev_get_volume(struct aw_device *aw_dev, unsigned short *get_vol)
+{
+	int ret = -1;
+	u16 hw_vol = 0;
+	struct aw_volume_desc *vol_desc = &aw_dev->volume_desc;
+
+	ret = aw_dev->ops.aw_get_hw_volume(aw_dev, &hw_vol);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "read volume failed");
+		return ret;
+	}
+
+	if (hw_vol > vol_desc->init_volume)
+		*get_vol = hw_vol - vol_desc->init_volume;
+
+	return 0;
+}
+
+static void aw_dev_fade_in(struct aw_device *aw_dev)
+{
+	int i = 0;
+	struct aw_volume_desc *desc = &aw_dev->volume_desc;
+	int fade_step = aw_dev->fade_step;
+	u16 fade_in_vol = desc->ctl_volume;
+
+	if (!aw_dev->fade_en)
+		return;
+
+	if (fade_step == 0 || aw_dev->fade_in_time == 0) {
+		aw883xx_dev_set_volume(aw_dev, fade_in_vol);
+		return;
+	}
+	/*volume up*/
+	for (i = desc->mute_volume; i >= fade_in_vol; i -= fade_step) {
+		aw883xx_dev_set_volume(aw_dev, i);
+		usleep_range(aw_dev->fade_in_time, aw_dev->fade_in_time + 10);
+	}
+	if (i != fade_in_vol)
+		aw883xx_dev_set_volume(aw_dev, fade_in_vol);
+
+}
+
+static void aw_dev_fade_out(struct aw_device *aw_dev)
+{
+	int i = 0;
+	struct aw_volume_desc *desc = &aw_dev->volume_desc;
+	int fade_step = aw_dev->fade_step;
+
+	if (!aw_dev->fade_en)
+		return;
+
+	if (fade_step == 0 || aw_dev->fade_out_time == 0) {
+		aw883xx_dev_set_volume(aw_dev, desc->mute_volume);
+		return;
+	}
+
+	for (i = desc->ctl_volume; i <= desc->mute_volume; i += fade_step) {
+		aw883xx_dev_set_volume(aw_dev, i);
+		usleep_range(aw_dev->fade_out_time, aw_dev->fade_out_time + 10);
+	}
+	if (i != desc->mute_volume) {
+		aw883xx_dev_set_volume(aw_dev, desc->mute_volume);
+		usleep_range(aw_dev->fade_out_time, aw_dev->fade_out_time + 10);
+	}
+}
+
+static uint64_t aw_dev_dsp_crc32_reflect(uint64_t ref, unsigned char ch)
+{
+	int i;
+	uint64_t value = 0;
+
+	for (i = 1; i < (ch + 1); i++) {
+		if (ref & 1)
+			value |= 1 << (ch - i);
+
+		ref >>= 1;
+	}
+
+	return value;
+}
+
+static unsigned int aw_dev_calc_dsp_cfg_crc32(unsigned char *buf, unsigned int len)
+{
+	u8 i;
+	u32 crc = 0xffffffff;
+
+	while (len--) {
+		for (i = 1; i != 0; i <<= 1) {
+			if ((crc & 0x80000000) != 0) {
+				crc <<= 1;
+				crc ^= 0x1EDC6F41;
+			} else {
+				crc <<= 1;
+			}
+
+			if ((*buf & i) != 0)
+				crc ^= 0x1EDC6F41;
+		}
+		buf++;
+	}
+
+	return (aw_dev_dsp_crc32_reflect(crc, 32)^0xffffffff);
+}
+
+static int aw_dev_set_dsp_crc32(struct aw_device *aw_dev)
+{
+	u32 crc_value = 0;
+	u32 crc_data_len = 0;
+	int ret = -1;
+	struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg;
+	struct aw_dsp_crc_desc *desc = &aw_dev->dsp_crc_desc;
+
+	/*get crc data len*/
+	crc_data_len = (desc->dsp_reg - aw_dev->dsp_mem_desc.dsp_cfg_base_addr) * 2;
+	if (crc_data_len > crc_dsp_cfg->len) {
+		dev_err(aw_dev->dev, "crc data len :%d > cfg_data len:%d",
+			crc_data_len, crc_dsp_cfg->len);
+		return -EINVAL;
+	}
+
+	if (crc_data_len % 4 != 0) {
+		dev_err(aw_dev->dev, "The crc data len :%d unsupport", crc_data_len);
+		return -EINVAL;
+	}
+
+	crc_value = aw_dev_calc_dsp_cfg_crc32(crc_dsp_cfg->data, crc_data_len);
+
+	dev_dbg(aw_dev->dev, "crc_value:0x%x", crc_value);
+	ret = aw_dev->ops.aw_dsp_write(aw_dev, desc->dsp_reg, crc_value,
+						desc->data_type);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "set dsp crc value failed");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void aw_dev_dsp_crc_check_enable(struct aw_device *aw_dev, bool flag)
+{
+	struct aw_dsp_crc_desc *dsp_crc_desc = &aw_dev->dsp_crc_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+	int ret;
+
+	if (flag) {
+		ret = aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, dsp_crc_desc->ctl_reg,
+				~dsp_crc_desc->ctl_mask, dsp_crc_desc->ctl_enable);
+		if (ret < 0) {
+			dev_err(aw_dev->dev, "enable dsp crc failed");
+			return;
+		}
+	} else {
+		ret = aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, dsp_crc_desc->ctl_reg,
+				~dsp_crc_desc->ctl_mask, dsp_crc_desc->ctl_disable);
+		if (ret < 0) {
+			dev_err(aw_dev->dev, "close dsp crc failed");
+			return;
+		}
+	}
+}
+
+static int aw_dev_dsp_st_check(struct aw_device *aw_dev)
+{
+	struct aw_sysst_desc *desc = &aw_dev->sysst_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+	int ret = -1;
+	unsigned int reg_val = 0;
+	int i;
+
+	for (i = 0; i < AW_DSP_ST_CHECK_MAX; i++) {
+		ret = aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->reg, &reg_val);
+		if (ret < 0) {
+			dev_err(aw_dev->dev, "read reg0x%x failed", desc->reg);
+			continue;
+		}
+
+		if ((reg_val & (~desc->dsp_mask)) != desc->dsp_check) {
+			dev_err(aw_dev->dev, "check dsp st fail,reg_val:0x%04x", reg_val);
+			ret = -EINVAL;
+			continue;
+		} else {
+			dev_dbg(aw_dev->dev, "dsp st check ok, reg_val:0x%04x", reg_val);
+			return 0;
+		}
+	}
+
+	return ret;
+}
+
+static int aw_dev_dsp_crc32_check(struct aw_device *aw_dev)
+{
+	int ret;
+
+	if (aw_dev->dsp_cfg == AW_DEV_DSP_BYPASS) {
+		dev_info(aw_dev->dev, "dsp bypass");
+		return 0;
+	}
+
+	ret = aw_dev_set_dsp_crc32(aw_dev);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "set dsp crc32 failed");
+		return ret;
+	}
+
+	aw_dev_dsp_crc_check_enable(aw_dev, true);
+
+	/*dsp enable*/
+	aw883xx_dev_dsp_enable(aw_dev, true);
+	usleep_range(AW_5000_US, AW_5000_US + 100);
+
+	ret = aw_dev_dsp_st_check(aw_dev);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "check crc32 fail");
+		return ret;
+	}
+
+	aw_dev_dsp_crc_check_enable(aw_dev, false);
+	aw_dev->dsp_crc_st = AW_DSP_CRC_OK;
+	return 0;
+}
+
+static void aw_dev_pwd(struct aw_device *aw_dev, bool pwd)
+{
+	struct aw_pwd_desc *pwd_desc = &aw_dev->pwd_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	if (pwd) {
+		aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, pwd_desc->reg,
+				~pwd_desc->mask,
+				pwd_desc->enable);
+	} else {
+		aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, pwd_desc->reg,
+				~pwd_desc->mask,
+				pwd_desc->disable);
+	}
+}
+
+static void aw_dev_amppd(struct aw_device *aw_dev, bool amppd)
+{
+	struct aw_amppd_desc *amppd_desc = &aw_dev->amppd_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	if (amppd) {
+		aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, amppd_desc->reg,
+				~amppd_desc->mask,
+				amppd_desc->enable);
+	} else {
+		aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, amppd_desc->reg,
+				~amppd_desc->mask,
+				amppd_desc->disable);
+	}
+}
+
+void aw883xx_dev_mute(struct aw_device *aw_dev, bool mute)
+{
+	struct aw_mute_desc *mute_desc = &aw_dev->mute_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	if (mute) {
+		aw_dev_fade_out(aw_dev);
+		aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, mute_desc->reg,
+				~mute_desc->mask, mute_desc->enable);
+	} else {
+		aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, mute_desc->reg,
+				~mute_desc->mask, mute_desc->disable);
+		aw_dev_fade_in(aw_dev);
+	}
+}
+
+int aw883xx_dev_get_hmute(struct aw_device *aw_dev)
+{
+	unsigned int reg_val = 0;
+	int ret;
+	struct aw_mute_desc *desc = &aw_dev->mute_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	ret = aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->reg, &reg_val);
+	if (ret < 0)
+		return ret;
+
+	if (reg_val & (~desc->mask))
+		ret = 1;
+	else
+		ret = 0;
+
+	return ret;
+}
+
+static int aw_dev_get_icalk(struct aw_device *aw_dev, int16_t *icalk)
+{
+	int ret = -1;
+	unsigned int reg_val = 0;
+	u16 reg_icalk = 0;
+	struct aw_vcalb_desc *desc = &aw_dev->vcalb_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	ret = aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->icalk_reg, &reg_val);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "reg read failed");
+		return ret;
+	}
+
+	reg_icalk = reg_val & (~desc->icalk_reg_mask);
+
+	if (reg_icalk & (~desc->icalk_sign_mask))
+		reg_icalk = reg_icalk | desc->icalk_neg_mask;
+
+	*icalk = (int16_t)reg_icalk;
+
+	return 0;
+}
+
+static int aw_dev_get_vcalk(struct aw_device *aw_dev, int16_t *vcalk)
+{
+	int ret = -1;
+	unsigned int reg_val = 0;
+	u16 reg_vcalk = 0;
+	struct aw_vcalb_desc *desc = &aw_dev->vcalb_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	ret = aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->vcalk_reg, &reg_val);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "reg read failed");
+		return ret;
+	}
+
+	reg_val = reg_val >> desc->vcalk_shift;
+
+	reg_vcalk = (u16)reg_val & (~desc->vcalk_reg_mask);
+
+	if (reg_vcalk & (~desc->vcalk_sign_mask))
+		reg_vcalk = reg_vcalk | desc->vcalk_neg_mask;
+
+	*vcalk = (int16_t)reg_vcalk;
+
+	return 0;
+}
+
+static int aw_dev_get_vcalk_dac(struct aw_device *aw_dev, int16_t *vcalk)
+{
+	int ret = -1;
+	unsigned int reg_val = 0;
+	u16 reg_vcalk = 0;
+	struct aw_vcalb_desc *desc = &aw_dev->vcalb_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	ret = aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->icalk_reg, &reg_val);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "reg read failed");
+		return ret;
+	}
+
+	reg_vcalk = reg_val >> desc->vcalk_dac_shift;
+
+	if (reg_vcalk & desc->vcalk_dac_mask)
+		reg_vcalk = reg_vcalk | desc->vcalk_dac_neg_mask;
+
+	*vcalk = (int16_t)reg_vcalk;
+
+	return 0;
+}
+
+int aw883xx_dev_modify_dsp_cfg(struct aw_device *aw_dev,
+			unsigned int addr, unsigned int dsp_data, unsigned char data_type)
+{
+	u32 addr_offset = 0;
+	int len = 0;
+	u8 temp_data[4] = { 0 };
+	struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg;
+
+	dev_dbg(aw_dev->dev, "addr:0x%x, dsp_data:0x%x", addr, dsp_data);
+
+	switch (data_type) {
+	case AW_DSP_16_DATA:
+		temp_data[0] = (u8)(dsp_data & 0x00ff);
+		temp_data[1] = (u8)((dsp_data & 0xff00) >> 8);
+		len = 2;
+		break;
+	case AW_DSP_32_DATA:
+		temp_data[0] = (u8)(dsp_data & 0x000000ff);
+		temp_data[1] = (u8)((dsp_data & 0x0000ff00) >> 8);
+		temp_data[2] = (u8)((dsp_data & 0x00ff0000) >> 16);
+		temp_data[3] = (u8)((dsp_data & 0xff000000) >> 24);
+		len = 4;
+		break;
+	default:
+		dev_err(aw_dev->dev, "data type[%d] unsupported", data_type);
+		return -EINVAL;
+	}
+
+	addr_offset = (addr - aw_dev->dsp_mem_desc.dsp_cfg_base_addr) * 2;
+	if (addr_offset > crc_dsp_cfg->len) {
+		dev_err(aw_dev->dev, "addr_offset[%d] > crc_dsp_cfg->len[%d]",
+				addr_offset, crc_dsp_cfg->len);
+		return -EINVAL;
+	}
+
+	memcpy(crc_dsp_cfg->data + addr_offset, temp_data, len);
+	return 0;
+}
+
+static int aw_dev_vsense_select(struct aw_device *aw_dev, int *vsense_select)
+{
+	int ret = -1;
+	struct aw_vcalb_desc *desc = &aw_dev->vcalb_desc;
+	unsigned int vsense_reg_val;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	ret = aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->vcalb_vsense_reg, &vsense_reg_val);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "read vsense_reg_val failed");
+		return ret;
+	}
+	dev_dbg(aw_dev->dev, "vsense_reg = 0x%x", vsense_reg_val);
+
+	if (vsense_reg_val & (~desc->vcalk_vdsel_mask)) {
+		*vsense_select = AW_DEV_VDSEL_VSENSE;
+		dev_dbg(aw_dev->dev, "vsense outside");
+		return 0;
+	}
+
+	*vsense_select = AW_DEV_VDSEL_DAC;
+	dev_dbg(aw_dev->dev, "vsense inside");
+	return 0;
+}
+
+static int aw_dev_set_vcalb(struct aw_device *aw_dev)
+{
+	int ret = -1;
+	u32 reg_val = 0;
+	int vcalb;
+	int icalk;
+	int vcalk;
+	int16_t icalk_val = 0;
+	int16_t vcalk_val = 0;
+	struct aw_vcalb_desc *desc = &aw_dev->vcalb_desc;
+	u32 vcalb_adj;
+	int vsense_select = -1;
+
+	ret = aw_dev->ops.aw_dsp_read(aw_dev, desc->vcalb_dsp_reg, &vcalb_adj, desc->data_type);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "read vcalb_adj failed");
+		return ret;
+	}
+
+	ret = aw_dev_vsense_select(aw_dev, &vsense_select);
+	if (ret < 0)
+		return ret;
+	dev_dbg(aw_dev->dev, "vsense_select = %d", vsense_select);
+
+	ret = aw_dev_get_icalk(aw_dev, &icalk_val);
+	if (ret < 0)
+		return ret;
+	icalk = desc->cabl_base_value + desc->icalk_value_factor * icalk_val;
+
+	switch (vsense_select) {
+	case AW_DEV_VDSEL_VSENSE:
+		ret = aw_dev_get_vcalk(aw_dev, &vcalk_val);
+		if (ret < 0)
+			return ret;
+		vcalk = desc->cabl_base_value + desc->vcalk_value_factor * vcalk_val;
+		vcalb = desc->vcal_factor * desc->vscal_factor /
+			desc->iscal_factor * icalk / vcalk * vcalb_adj;
+
+		dev_dbg(aw_dev->dev, "vcalk_factor=%d, vscal_factor=%d, icalk=%d, vcalk=%d",
+				desc->vcalk_value_factor, desc->vscal_factor, icalk, vcalk);
+		break;
+	case AW_DEV_VDSEL_DAC:
+		ret = aw_dev_get_vcalk_dac(aw_dev, &vcalk_val);
+		if (ret < 0)
+			return ret;
+		vcalk = desc->cabl_base_value + desc->vcalk_value_factor_vsense_in * vcalk_val;
+		vcalb = desc->vcal_factor * desc->vscal_factor_vsense_in /
+			desc->iscal_factor * icalk / vcalk * vcalb_adj;
+
+		dev_dbg(aw_dev->dev, "vcalk_dac_factor=%d, vscal_dac_factor=%d, icalk=%d, vcalk=%d",
+				desc->vcalk_value_factor_vsense_in,
+				desc->vscal_factor_vsense_in, icalk, vcalk);
+		break;
+	default:
+		dev_err(aw_dev->dev, "unsupport vsense status");
+		return -EINVAL;
+	}
+
+	if ((vcalk == 0) || (desc->iscal_factor == 0)) {
+		dev_err(aw_dev->dev, "vcalk:%d or desc->iscal_factor:%d unsupported",
+			vcalk, desc->iscal_factor);
+		return -EINVAL;
+	}
+
+	vcalb = vcalb >> aw_dev->vcalb_desc.vcalb_adj_shift;
+	reg_val = (u32)vcalb;
+
+	dev_dbg(aw_dev->dev, "vcalb=%d, reg_val=0x%x, vcalb_adj =0x%x",
+				vcalb, reg_val, vcalb_adj);
+
+	ret = aw_dev->ops.aw_dsp_write(aw_dev, desc->vcalb_dsp_reg, reg_val, desc->data_type);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "write vcalb failed");
+		return ret;
+	}
+
+	ret = aw883xx_dev_modify_dsp_cfg(aw_dev, desc->vcalb_dsp_reg,
+					(u32)reg_val, desc->data_type);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "modify dsp cfg failed");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int aw_dev_get_cali_f0_delay(struct aw_device *aw_dev)
+{
+	struct aw_cali_delay_desc *desc = &aw_dev->cali_delay_desc;
+	u32 cali_delay = 0;
+	int ret = -1;
+
+	ret = aw_dev->ops.aw_dsp_read(aw_dev,
+			desc->dsp_reg, &cali_delay, desc->data_type);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "read cali delay failed, ret=%d", ret);
+		return ret;
+	}
+
+	desc->delay = AW_CALI_DELAY_CACL(cali_delay);
+	dev_dbg(aw_dev->dev, "read cali delay: %d ms", desc->delay);
+
+	return 0;
+}
+
+static void aw883xx_dev_get_int_status(struct aw_device *aw_dev, unsigned short *int_status)
+{
+	int ret = -1;
+	unsigned int reg_val = 0;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	ret = aw_dev->ops.aw_reg_read(aw883xx->regmap, aw_dev->int_desc.st_reg, &reg_val);
+	if (ret < 0)
+		dev_err(aw_dev->dev, "read interrupt reg fail, ret=%d", ret);
+	else
+		*int_status = reg_val;
+
+	dev_dbg(aw_dev->dev, "read interrupt reg = 0x%04x", *int_status);
+}
+
+static void aw883xx_dev_clear_int_status(struct aw_device *aw_dev)
+{
+	u16 int_status = 0;
+
+	/*read int status and clear*/
+	aw883xx_dev_get_int_status(aw_dev, &int_status);
+	/*make sure int status is clear*/
+	aw883xx_dev_get_int_status(aw_dev, &int_status);
+}
+
+int aw883xx_dev_get_iis_status(struct aw_device *aw_dev)
+{
+	int ret = -1;
+	unsigned int reg_val = 0;
+	struct aw_sysst_desc *desc = &aw_dev->sysst_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->reg, &reg_val);
+	if ((reg_val & desc->pll_check) == desc->pll_check)
+		ret = 0;
+	else
+		dev_err(aw_dev->dev, "check pll lock fail,reg_val:0x%04x", reg_val);
+
+	return ret;
+}
+
+static int aw_dev_mode1_pll_check(struct aw_device *aw_dev)
+{
+	int ret = -1;
+	u16 i = 0;
+
+	for (i = 0; i < AW_DEV_SYSST_CHECK_MAX; i++) {
+		ret = aw883xx_dev_get_iis_status(aw_dev);
+		if (ret < 0) {
+			dev_err(aw_dev->dev, "mode1 iis signal check error");
+			usleep_range(AW_2000_US, AW_2000_US + 10);
+		} else {
+			return 0;
+		}
+	}
+
+	return ret;
+}
+
+static int aw_dev_mode2_pll_check(struct aw_device *aw_dev)
+{
+	int ret = -1;
+	u16 i = 0;
+	unsigned int reg_val = 0;
+	struct aw_cco_mux_desc *cco_mux_desc = &aw_dev->cco_mux_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	aw_dev->ops.aw_reg_read(aw883xx->regmap, cco_mux_desc->reg, &reg_val);
+	reg_val &= (~cco_mux_desc->mask);
+	if (reg_val == cco_mux_desc->divider) {
+		dev_dbg(aw_dev->dev, "CCO_MUX is already divider");
+		return ret;
+	}
+
+	/* change mode2 */
+	aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, cco_mux_desc->reg,
+		~cco_mux_desc->mask, cco_mux_desc->divider);
+
+	for (i = 0; i < AW_DEV_SYSST_CHECK_MAX; i++) {
+		ret = aw883xx_dev_get_iis_status(aw_dev);
+		if (ret < 0) {
+			dev_err(aw_dev->dev, "mode2 iis signal check error");
+			usleep_range(AW_2000_US, AW_2000_US + 10);
+		} else {
+			break;
+		}
+	}
+
+	/* change mode1*/
+	aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, cco_mux_desc->reg,
+		~cco_mux_desc->mask, cco_mux_desc->bypass);
+
+	if (ret == 0) {
+		usleep_range(AW_2000_US, AW_2000_US + 10);
+		for (i = 0; i < AW_DEV_SYSST_CHECK_MAX; i++) {
+			ret = aw_dev_mode1_pll_check(aw_dev);
+			if (ret < 0) {
+				dev_err(aw_dev->dev, "mode2 switch to mode1, iis signal check error");
+				usleep_range(AW_2000_US, AW_2000_US + 10);
+			} else {
+				break;
+			}
+		}
+	}
+
+	return ret;
+}
+
+int aw883xx_dev_syspll_check(struct aw_device *aw_dev)
+{
+	int ret = -1;
+
+	ret = aw_dev_mode1_pll_check(aw_dev);
+	if (ret < 0) {
+		dev_dbg(aw_dev->dev, "mode1 check iis failed try switch to mode2 check");
+		ret = aw_dev_mode2_pll_check(aw_dev);
+		if (ret < 0) {
+			dev_err(aw_dev->dev, "mode2 check iis failed");
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+int aw883xx_dev_sysst_check(struct aw_device *aw_dev)
+{
+	int ret = -1;
+	unsigned char i;
+	unsigned int reg_val = 0;
+	struct aw_sysst_desc *desc = &aw_dev->sysst_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	for (i = 0; i < AW_DEV_SYSST_CHECK_MAX; i++) {
+		aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->reg, &reg_val);
+		if (((reg_val & (~desc->st_mask)) & desc->st_check) != desc->st_check) {
+			dev_dbg(aw_dev->dev, "check fail, cnt=%d, reg_val=0x%04x",
+				i, reg_val);
+			usleep_range(AW_2000_US, AW_2000_US + 10);
+		} else {
+			ret = 0;
+			break;
+		}
+	}
+	if (ret < 0)
+		dev_err(aw_dev->dev, "check fail");
+
+	return ret;
+}
+
+static int aw_dev_sysint_check(struct aw_device *aw_dev)
+{
+	int ret = 0;
+	u16 reg_val = 0;
+	struct aw_int_desc *desc = &aw_dev->int_desc;
+
+	aw883xx_dev_get_int_status(aw_dev, &reg_val);
+
+	if (reg_val & (desc->intst_mask)) {
+		dev_err(aw_dev->dev, "pa stop check fail:0x%04x", reg_val);
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static void aw_dev_get_cur_mode_st(struct aw_device *aw_dev)
+{
+	unsigned int reg_val;
+	struct aw_profctrl_desc *profctrl_desc = &aw_dev->profctrl_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	aw_dev->ops.aw_reg_read(aw883xx->regmap, aw_dev->pwd_desc.reg, &reg_val);
+	if ((reg_val & (~profctrl_desc->mask)) == profctrl_desc->rcv_mode_val)
+		profctrl_desc->cur_mode = AW_RCV_MODE;
+	else
+		profctrl_desc->cur_mode = AW_NOT_RCV_MODE;
+}
+
+void aw883xx_dev_dsp_enable(struct aw_device *aw_dev, bool dsp)
+{
+	int ret = -1;
+	struct aw_dsp_en_desc *desc = &aw_dev->dsp_en_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	if (dsp) {
+		ret = aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, desc->reg,
+					~desc->mask, desc->enable);
+		if (ret < 0)
+			dev_err(aw_dev->dev, "enable dsp failed");
+	} else {
+		ret = aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, desc->reg,
+					~desc->mask, desc->disable);
+		if (ret < 0)
+			dev_err(aw_dev->dev, "disable dsp failed");
+	}
+}
+
+static void aw_dev_get_dsp_config(struct aw_device *aw_dev, unsigned char *dsp_cfg)
+{
+	int ret = -1;
+	unsigned int reg_val = 0;
+	struct aw_dsp_en_desc *desc = &aw_dev->dsp_en_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	ret = aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->reg, &reg_val);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "reg read failed");
+		return;
+	}
+
+	if (reg_val & (~desc->mask))
+		*dsp_cfg = AW_DEV_DSP_BYPASS;
+	else
+		*dsp_cfg = AW_DEV_DSP_WORK;
+}
+
+void aw883xx_dev_memclk_select(struct aw_device *aw_dev, unsigned char flag)
+{
+	struct aw_memclk_desc *desc = &aw_dev->memclk_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+	int ret = -1;
+
+	switch (flag) {
+	case AW_DEV_MEMCLK_PLL:
+		ret = aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, desc->reg,
+					~desc->mask, desc->mcu_hclk);
+		if (ret < 0)
+			dev_err(aw_dev->dev, "memclk select pll failed");
+		break;
+	case AW_DEV_MEMCLK_OSC:
+		ret = aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, desc->reg,
+					~desc->mask, desc->osc_clk);
+		if (ret < 0)
+			dev_err(aw_dev->dev, "memclk select OSC failed");
+		break;
+	default:
+		dev_err(aw_dev->dev, "unknown memclk config, flag=0x%x", flag);
+		break;
+	}
+}
+
+int aw883xx_dev_get_dsp_status(struct aw_device *aw_dev)
+{
+	int ret = -1;
+	unsigned int reg_val = 0;
+	struct aw_watch_dog_desc *desc = &aw_dev->watch_dog_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->reg, &reg_val);
+	if (reg_val & (~desc->mask))
+		ret = 0;
+
+	return ret;
+}
+
+static int aw_dev_get_vmax(struct aw_device *aw_dev, unsigned int *vmax)
+{
+	int ret = -1;
+	struct aw_vmax_desc *desc = &aw_dev->vmax_desc;
+
+	ret = aw_dev->ops.aw_dsp_read(aw_dev, desc->dsp_reg, vmax, desc->data_type);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "get vmax failed");
+		return ret;
+	}
+
+	return 0;
+}
+
+/*
+ * aw_dev update cfg
+ */
+static int aw_dev_reg_container_update(struct aw_device *aw_dev,
+				unsigned char *data, unsigned int len)
+{
+	int i, ret;
+	u8 reg_addr = 0;
+	u16 reg_val = 0;
+	unsigned int read_val = 0;
+	u16 read_vol = 0;
+	struct aw_volume_desc *vol_desc = &aw_dev->volume_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+	int16_t *reg_data = NULL;
+	int data_len;
+
+	reg_data = (int16_t *)data;
+	data_len = len >> 1;
+
+	if (data_len % 2 != 0) {
+		dev_err(aw_dev->dev, "data len:%d unsupported",
+				data_len);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < data_len; i += 2) {
+		reg_addr = reg_data[i];
+		reg_val = reg_data[i + 1];
+		dev_dbg(aw_dev->dev, "reg = 0x%02x, val = 0x%04x",
+				reg_addr, reg_val);
+		if (reg_addr == aw_dev->mute_desc.reg) {
+			aw_dev->ops.aw_reg_read(aw883xx->regmap, reg_addr, &read_val);
+			read_val &= (~aw_dev->mute_desc.mask);
+			reg_val &= aw_dev->mute_desc.mask;
+			reg_val |= read_val;
+		}
+		if (reg_addr == aw_dev->dsp_crc_desc.ctl_reg)
+			reg_val &= aw_dev->dsp_crc_desc.ctl_mask;
+
+		if (reg_addr == aw_dev->chansel_desc.txchan_reg) {
+			/*close tx*/
+			reg_val &= aw_dev->tx_en_desc.tx_en_mask;
+			reg_val |= aw_dev->tx_en_desc.tx_disable;
+		}
+
+		if (reg_addr == aw_dev->volume_desc.reg) {
+			read_vol = (reg_val & (~aw_dev->volume_desc.mask)) >>
+				aw_dev->volume_desc.shift;
+			aw_dev->volume_desc.init_volume =
+				aw_dev->ops.aw_reg_val_to_db(read_vol);
+		}
+		ret = aw_dev->ops.aw_reg_write(aw883xx->regmap, reg_addr, reg_val);
+		if (ret < 0)
+			break;
+
+	}
+
+	aw_dev_get_cur_mode_st(aw_dev);
+
+	if (aw_dev->cur_prof != aw_dev->set_prof) {
+		/*clear control volume when PA change profile*/
+		vol_desc->ctl_volume = 0;
+	} else {
+		/*keep control volume when PA start with sync mode*/
+		aw883xx_dev_set_volume(aw_dev, vol_desc->ctl_volume);
+	}
+
+	/*keep min volume*/
+	if (aw_dev->fade_en)
+		aw883xx_dev_set_volume(aw_dev, vol_desc->mute_volume);
+
+	aw_dev_get_dsp_config(aw_dev, &aw_dev->dsp_cfg);
+
+	dev_dbg(aw_dev->dev, "exit");
+
+	return ret;
+}
+
+static int aw_dev_reg_update(struct aw_device *aw_dev,
+					unsigned char *data, unsigned int len)
+{
+	int ret = 0;
+
+	dev_dbg(aw_dev->dev, "reg len:%d", len);
+
+	if (len && (data != NULL)) {
+		ret = aw_dev_reg_container_update(aw_dev, data, len);
+		if (ret < 0) {
+			dev_err(aw_dev->dev, "reg update failed");
+			return ret;
+		}
+	} else {
+		dev_err(aw_dev->dev, "reg data is null or len is 0");
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+static int aw_dev_get_ra(struct aw_cali_desc *cali_desc)
+{
+	int ret;
+	u32 dsp_ra;
+	struct aw_device *aw_dev =
+		container_of(cali_desc, struct aw_device, cali_desc);
+	struct aw_ra_desc *desc = &aw_dev->ra_desc;
+
+	ret = aw_dev->ops.aw_dsp_read(aw_dev, desc->dsp_reg,
+				&dsp_ra, desc->data_type);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "read ra error");
+		return ret;
+	}
+
+	cali_desc->ra = AW_DSP_RE_TO_SHOW_RE(dsp_ra,
+					aw_dev->adpz_re_desc.shift);
+	dev_dbg(aw_dev->dev, "get ra:%d", cali_desc->ra);
+	return 0;
+}
+
+static int aw_dev_dsp_container_update(struct aw_device *aw_dev,
+			unsigned char *data, unsigned int len, unsigned short base)
+{
+	int i;
+	struct aw_dsp_mem_desc *dsp_mem_desc = &aw_dev->dsp_mem_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+#ifdef AW_DSP_I2C_WRITES
+	u32 tmp_len = 0;
+#else
+	u16 reg_val = 0;
+#endif
+
+	mutex_lock(aw_dev->dsp_lock);
+#ifdef AW_DSP_I2C_WRITES
+	/* i2c writes */
+	aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg, base);
+
+	for (i = 0; i < len; i += AW_MAX_RAM_WRITE_BYTE_SIZE) {
+		if ((len - i) < AW_MAX_RAM_WRITE_BYTE_SIZE)
+			tmp_len = len - i;
+		else
+			tmp_len = AW_MAX_RAM_WRITE_BYTE_SIZE;
+		aw_dev->ops.aw_i2c_writes(aw883xx->regmap, dsp_mem_desc->dsp_mdat_reg,
+					&data[i], tmp_len);
+	}
+
+#else
+	/* i2c write */
+	aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg, base);
+	for (i = 0; i < len; i += 2) {
+		reg_val = (data[i] << 8) + data[i + 1];
+		aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_mdat_reg,
+					reg_val);
+	}
+#endif
+	mutex_unlock(aw_dev->dsp_lock);
+	dev_dbg(aw_dev->dev, "exit");
+
+	return 0;
+}
+
+static int aw_dev_dsp_fw_update(struct aw_device *aw_dev,
+			unsigned char *data, unsigned int len)
+{
+	struct aw_dsp_mem_desc *dsp_mem_desc = &aw_dev->dsp_mem_desc;
+
+	dev_dbg(aw_dev->dev, "dsp firmware len:%d", len);
+
+	if (len && (data != NULL)) {
+		aw_dev_dsp_container_update(aw_dev,
+			data, len, dsp_mem_desc->dsp_fw_base_addr);
+		aw_dev->dsp_fw_len = len;
+	} else {
+		dev_err(aw_dev->dev, "dsp firmware data is null or len is 0");
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+static int aw_dev_copy_to_crc_dsp_cfg(struct aw_device *aw_dev,
+			unsigned char *data, unsigned int size)
+{
+	struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg;
+	int ret;
+
+	if (!crc_dsp_cfg->data) {
+		crc_dsp_cfg->data = devm_kzalloc(aw_dev->dev, size, GFP_KERNEL);
+		if (!crc_dsp_cfg->data)
+			return -ENOMEM;
+		crc_dsp_cfg->len = size;
+	} else if (crc_dsp_cfg->len < size) {
+		devm_kfree(aw_dev->dev, crc_dsp_cfg->data);
+		crc_dsp_cfg->data = NULL;
+		crc_dsp_cfg->data = devm_kzalloc(aw_dev->dev, size, GFP_KERNEL);
+		if (!crc_dsp_cfg->data) {
+			dev_err(aw_dev->dev, "error allocating memory");
+			return -ENOMEM;
+		}
+		crc_dsp_cfg->len = size;
+	}
+	memcpy(crc_dsp_cfg->data, data, size);
+	ret = aw883xx_dev_dsp_data_order(aw_dev, crc_dsp_cfg->data, size);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+int aw883xx_dev_dsp_cfg_update(struct aw_device *aw_dev,
+			unsigned char *data, unsigned int len)
+{
+	struct aw_dsp_mem_desc *dsp_mem_desc = &aw_dev->dsp_mem_desc;
+	int ret;
+
+	dev_dbg(aw_dev->dev, "dsp config len:%d", len);
+
+	if (len && (data != NULL)) {
+		aw_dev_dsp_container_update(aw_dev,
+			data, len, dsp_mem_desc->dsp_cfg_base_addr);
+		aw_dev->dsp_cfg_len = len;
+
+		ret = aw_dev_copy_to_crc_dsp_cfg(aw_dev, data, len);
+		if (ret < 0)
+			return ret;
+
+		ret = aw_dev_set_vcalb(aw_dev);
+		if (ret < 0)
+			return ret;
+		ret = aw_dev_get_ra(&aw_dev->cali_desc);
+		if (ret < 0)
+			return ret;
+		ret = aw_dev_get_cali_f0_delay(aw_dev);
+		if (ret < 0)
+			return ret;
+
+		ret = aw_dev_get_vmax(aw_dev, &aw_dev->vmax_desc.init_vmax);
+		if (ret < 0) {
+			dev_err(aw_dev->dev, "get vmax failed");
+			return ret;
+		}
+		dev_dbg(aw_dev->dev, "get init vmax:0x%x",
+						aw_dev->vmax_desc.init_vmax);
+		aw_dev->dsp_crc_st = AW_DSP_CRC_NA;
+	} else {
+		dev_err(aw_dev->dev, "dsp config data is null or len is 0");
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+static int aw_dev_sram_check(struct aw_device *aw_dev)
+{
+	int ret = -1;
+	unsigned int reg_val = 0;
+	struct aw_dsp_mem_desc *dsp_mem_desc = &aw_dev->dsp_mem_desc;
+	struct aw883xx *aw883xx = aw_dev->private_data;
+
+	mutex_lock(aw_dev->dsp_lock);
+	/*check the odd bits of reg 0x40*/
+	aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg,
+					AW_DSP_ODD_NUM_BIT_TEST);
+	aw_dev->ops.aw_i2c_read(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg, &reg_val);
+	if (reg_val != AW_DSP_ODD_NUM_BIT_TEST) {
+		dev_err(aw_dev->dev, "check reg 0x40 odd bit failed, read[0x%x] does not match write[0x%x]",
+				reg_val, AW_DSP_ODD_NUM_BIT_TEST);
+		goto error;
+	}
+
+	/*check the even bits of reg 0x40*/
+	aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg,
+					AW_DSP_EVEN_NUM_BIT_TEST);
+	aw_dev->ops.aw_i2c_read(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg, &reg_val);
+	if (reg_val != AW_DSP_EVEN_NUM_BIT_TEST) {
+		dev_err(aw_dev->dev, "check reg 0x40 even bit failed, read[0x%x] does not match write[0x%x]",
+				reg_val, AW_DSP_EVEN_NUM_BIT_TEST);
+		goto error;
+	}
+
+	/*check dsp_fw_base_addr*/
+	aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg,
+					dsp_mem_desc->dsp_fw_base_addr);
+	aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_mdat_reg,
+					AW_DSP_EVEN_NUM_BIT_TEST);
+
+	aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg,
+					dsp_mem_desc->dsp_fw_base_addr);
+	aw_dev->ops.aw_i2c_read(aw883xx->regmap, dsp_mem_desc->dsp_mdat_reg, &reg_val);
+	if (reg_val != AW_DSP_EVEN_NUM_BIT_TEST) {
+		dev_err(aw_dev->dev, "check dsp fw addr failed, read[0x%x] does not match write[0x%x]",
+						reg_val, AW_DSP_EVEN_NUM_BIT_TEST);
+		goto error;
+	}
+
+	/*check dsp_cfg_base_addr*/
+	aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg,
+					dsp_mem_desc->dsp_cfg_base_addr);
+	aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_mdat_reg,
+					AW_DSP_ODD_NUM_BIT_TEST);
+
+	aw_dev->ops.aw_i2c_write(aw883xx->regmap, dsp_mem_desc->dsp_madd_reg,
+					dsp_mem_desc->dsp_cfg_base_addr);
+	aw_dev->ops.aw_i2c_read(aw883xx->regmap, dsp_mem_desc->dsp_mdat_reg, &reg_val);
+	if (reg_val != AW_DSP_ODD_NUM_BIT_TEST) {
+		dev_err(aw_dev->dev, "check dsp cfg failed, read[0x%x] does not match write[0x%x]",
+						reg_val, AW_DSP_ODD_NUM_BIT_TEST);
+		goto error;
+	}
+
+	mutex_unlock(aw_dev->dsp_lock);
+	return 0;
+
+error:
+	mutex_unlock(aw_dev->dsp_lock);
+	return ret;
+}
+
+int aw883xx_dev_fw_update(struct aw_device *aw_dev, bool up_dsp_fw_en, bool force_up_en)
+{
+	int ret = -1;
+	struct aw_prof_desc *set_prof_desc = NULL;
+	struct aw_sec_data_desc *sec_desc = NULL;
+	char *prof_name = NULL;
+
+	if ((aw_dev->cur_prof == aw_dev->set_prof) &&
+			(force_up_en == AW_FORCE_UPDATE_OFF)) {
+		dev_dbg(aw_dev->dev, "scene no change, not update");
+		return 0;
+	}
+
+	if (aw_dev->fw_status == AW_DEV_FW_FAILED) {
+		dev_err(aw_dev->dev, "fw status[%d] error", aw_dev->fw_status);
+		return -EPERM;
+	}
+
+	prof_name = aw_dev_get_prof_name(aw_dev, aw_dev->set_prof);
+	if (!prof_name)
+		return -ENOMEM;
+
+	dev_dbg(aw_dev->dev, "start update %s", prof_name);
+
+	ret = aw883xx_dev_get_prof_data(aw_dev, aw_dev->set_prof, &set_prof_desc);
+	if (ret < 0)
+		return ret;
+
+	/*update reg*/
+	sec_desc = set_prof_desc->sec_desc;
+	ret = aw_dev_reg_update(aw_dev, sec_desc[AW_DATA_TYPE_REG].data,
+					sec_desc[AW_DATA_TYPE_REG].len);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "update reg failed");
+		return ret;
+	}
+
+	aw883xx_dev_mute(aw_dev, true);
+
+	if (aw_dev->dsp_cfg == AW_DEV_DSP_WORK)
+		aw883xx_dev_dsp_enable(aw_dev, false);
+
+	aw883xx_dev_memclk_select(aw_dev, AW_DEV_MEMCLK_OSC);
+
+	if (up_dsp_fw_en) {
+		ret = aw_dev_sram_check(aw_dev);
+		if (ret < 0) {
+			dev_err(aw_dev->dev, "check sram failed");
+			goto error;
+		}
+
+		/*update dsp firmware*/
+		dev_dbg(aw_dev->dev, "fw_ver: [%x]", set_prof_desc->fw_ver);
+		ret = aw_dev_dsp_fw_update(aw_dev, sec_desc[AW_DATA_TYPE_DSP_FW].data,
+					sec_desc[AW_DATA_TYPE_DSP_FW].len);
+		if (ret < 0) {
+			dev_err(aw_dev->dev, "update dsp fw failed");
+			goto error;
+		}
+	}
+
+	/*update dsp config*/
+	ret = aw883xx_dev_dsp_cfg_update(aw_dev, sec_desc[AW_DATA_TYPE_DSP_CFG].data,
+					sec_desc[AW_DATA_TYPE_DSP_CFG].len);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "update dsp cfg failed");
+		goto error;
+	}
+
+	aw883xx_dev_memclk_select(aw_dev, AW_DEV_MEMCLK_PLL);
+
+	aw_dev->cur_prof = aw_dev->set_prof;
+
+	return 0;
+
+error:
+	aw883xx_dev_memclk_select(aw_dev, AW_DEV_MEMCLK_PLL);
+
+	return ret;
+}
+
+int aw883xx_dev_dsp_check(struct aw_device *aw_dev)
+{
+	int ret = -1;
+	u16 i = 0;
+
+	switch (aw_dev->dsp_cfg) {
+	case AW_DEV_DSP_BYPASS:
+		dev_dbg(aw_dev->dev, "dsp bypass");
+		ret = 0;
+		break;
+	case AW_DEV_DSP_WORK:
+		aw883xx_dev_dsp_enable(aw_dev, false);
+		aw883xx_dev_dsp_enable(aw_dev, true);
+		usleep_range(AW_1000_US, AW_1000_US + 10);
+		for (i = 0; i < AW_DEV_DSP_CHECK_MAX; i++) {
+			ret = aw883xx_dev_get_dsp_status(aw_dev);
+			if (ret < 0) {
+				dev_err(aw_dev->dev, "dsp wdt status error=%d", ret);
+				usleep_range(AW_2000_US, AW_2000_US + 10);
+			}
+		}
+		break;
+	default:
+		dev_err(aw_dev->dev, "unknown dsp cfg=%d", aw_dev->dsp_cfg);
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static void aw_dev_set_cfg_f0_fs(struct aw_device *aw_dev)
+{
+	u32 f0_fs = 0;
+	struct aw_cfgf0_fs_desc *cfgf0_fs_desc = &aw_dev->cfgf0_fs_desc;
+	int ret;
+
+	if (aw_dev->ops.aw_set_cfg_f0_fs) {
+		aw_dev->ops.aw_set_cfg_f0_fs(aw_dev, &f0_fs);
+		ret = aw883xx_dev_modify_dsp_cfg(aw_dev, cfgf0_fs_desc->dsp_reg,
+					f0_fs, cfgf0_fs_desc->data_type);
+		if (ret < 0) {
+			dev_err(aw_dev->dev, "modify dsp cfg failed");
+			return;
+		}
+	}
+}
+
+static void aw_dev_cali_re_update(struct aw_cali_desc *cali_desc)
+{
+	int ret = 0;
+	struct aw_device *aw_dev =
+		container_of(cali_desc, struct aw_device, cali_desc);
+
+	if (aw_dev->cali_desc.cali_re < AW_CALI_RE_MAX &&
+		aw_dev->cali_desc.cali_re > AW_CALI_RE_MIN) {
+		if (aw_dev->ops.aw_set_cali_re) {
+			ret = aw_dev->ops.aw_set_cali_re(aw_dev);
+			if (ret < 0)
+				dev_err(aw_dev->dev, "set cali re failed");
+		} else {
+			dev_err(aw_dev->dev, "cali_re:%d out of range, no set",
+				aw_dev->cali_desc.cali_re);
+		}
+	}
+}
+
+int aw883xx_device_start(struct aw_device *aw_dev)
+{
+	int ret = -1;
+
+	if (aw_dev->status == AW_DEV_PW_ON) {
+		dev_info(aw_dev->dev, "already power on");
+		return 0;
+	}
+
+	/*power on*/
+	aw_dev_pwd(aw_dev, false);
+	usleep_range(AW_2000_US, AW_2000_US + 10);
+
+	ret = aw883xx_dev_syspll_check(aw_dev);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "pll check failed cannot start");
+		goto pll_check_fail;
+	}
+
+	/*amppd on*/
+	aw_dev_amppd(aw_dev, false);
+	usleep_range(AW_1000_US, AW_1000_US + 50);
+
+	/*check i2s status*/
+	ret = aw883xx_dev_sysst_check(aw_dev);
+	if (ret < 0)
+		goto sysst_check_fail;
+
+	if (aw_dev->dsp_cfg == AW_DEV_DSP_WORK) {
+		/*dsp bypass*/
+		aw883xx_dev_dsp_enable(aw_dev, false);
+		if (aw_dev->ops.aw_dsp_fw_check) {
+			ret = aw_dev->ops.aw_dsp_fw_check(aw_dev);
+			if (ret < 0)
+				goto dsp_fw_check_fail;
+		}
+		aw_dev_set_cfg_f0_fs(aw_dev);
+
+		aw_dev_cali_re_update(&aw_dev->cali_desc);
+
+		if (aw_dev->dsp_crc_st != AW_DSP_CRC_OK) {
+			ret = aw_dev_dsp_crc32_check(aw_dev);
+			if (ret < 0) {
+				dev_err(aw_dev->dev, "dsp crc check failed");
+				goto crc_check_fail;
+			}
+		}
+
+		ret = aw883xx_dev_dsp_check(aw_dev);
+		if (ret < 0) {
+			dev_err(aw_dev->dev, "check dsp status failed");
+			goto dsp_check_fail;
+		}
+	} else {
+		dev_dbg(aw_dev->dev, "start pa with dsp bypass");
+	}
+
+	/*enable tx feedback*/
+	if (aw_dev->ops.aw_i2s_tx_enable)
+		aw_dev->ops.aw_i2s_tx_enable(aw_dev, true);
+
+	/*close mute*/
+	aw883xx_dev_mute(aw_dev, false);
+	/*clear inturrupt*/
+	aw883xx_dev_clear_int_status(aw_dev);
+	aw_dev->status = AW_DEV_PW_ON;
+
+	return 0;
+
+dsp_check_fail:
+crc_check_fail:
+	aw883xx_dev_dsp_enable(aw_dev, false);
+dsp_fw_check_fail:
+sysst_check_fail:
+	aw883xx_dev_clear_int_status(aw_dev);
+	aw_dev_amppd(aw_dev, true);
+pll_check_fail:
+	aw_dev_pwd(aw_dev, true);
+	aw_dev->status = AW_DEV_PW_OFF;
+	return ret;
+}
+
+int aw883xx_device_stop(struct aw_device *aw_dev)
+{
+	struct aw_sec_data_desc *dsp_cfg =
+		&aw_dev->prof_info.prof_desc[aw_dev->cur_prof].sec_desc[AW_DATA_TYPE_DSP_CFG];
+	struct aw_sec_data_desc *dsp_fw =
+		&aw_dev->prof_info.prof_desc[aw_dev->cur_prof].sec_desc[AW_DATA_TYPE_DSP_FW];
+	int int_st = 0;
+	int ret = 0;
+
+	if (aw_dev->status == AW_DEV_PW_OFF) {
+		dev_info(aw_dev->dev, "already power off");
+		return 0;
+	}
+
+	aw_dev->status = AW_DEV_PW_OFF;
+
+	/*set mute*/
+	aw883xx_dev_mute(aw_dev, true);
+	usleep_range(AW_4000_US, AW_4000_US + 100);
+
+	/*close tx feedback*/
+	if (aw_dev->ops.aw_i2s_tx_enable)
+		aw_dev->ops.aw_i2s_tx_enable(aw_dev, false);
+	usleep_range(AW_1000_US, AW_1000_US + 100);
+
+	/*check sysint state*/
+	int_st = aw_dev_sysint_check(aw_dev);
+
+	/*close dsp*/
+	aw883xx_dev_dsp_enable(aw_dev, false);
+
+	/*enable amppd*/
+	aw_dev_amppd(aw_dev, true);
+
+	if (int_st < 0) {
+		/*system status anomaly*/
+		aw883xx_dev_memclk_select(aw_dev, AW_DEV_MEMCLK_OSC);
+		ret = aw_dev_dsp_fw_update(aw_dev, dsp_fw->data, dsp_fw->len);
+		if (ret < 0)
+			dev_err(aw_dev->dev, "update dsp fw failed");
+		ret = aw883xx_dev_dsp_cfg_update(aw_dev, dsp_cfg->data, dsp_cfg->len);
+		if (ret < 0)
+			dev_err(aw_dev->dev, "update dsp cfg failed");
+		aw883xx_dev_memclk_select(aw_dev, AW_DEV_MEMCLK_PLL);
+	}
+
+	/*set power down*/
+	aw_dev_pwd(aw_dev, true);
+
+	return 0;
+}
+
+/*deinit aw_device*/
+void aw883xx_dev_deinit(struct aw_device *aw_dev)
+{
+	if (!aw_dev)
+		return;
+
+	if (aw_dev->prof_info.prof_desc) {
+		devm_kfree(aw_dev->dev, aw_dev->prof_info.prof_desc);
+		aw_dev->prof_info.prof_desc = NULL;
+	}
+	aw_dev->prof_info.count = 0;
+
+	if (aw_dev->crc_dsp_cfg.data) {
+		aw_dev->crc_dsp_cfg.len = 0;
+		devm_kfree(aw_dev->dev, aw_dev->crc_dsp_cfg.data);
+		aw_dev->crc_dsp_cfg.data = NULL;
+	}
+
+}
+
+/*init aw_device*/
+int aw883xx_device_init(struct aw_device *aw_dev, struct aw_container *aw_cfg)
+{
+	int ret;
+
+	if ((!aw_dev) || (!aw_cfg)) {
+		pr_err("aw_dev is NULL or aw_cfg is NULL");
+		return -ENOMEM;
+	}
+	ret = aw883xx_dev_cfg_load(aw_dev, aw_cfg);
+	if (ret < 0) {
+		aw883xx_dev_deinit(aw_dev);
+		dev_err(aw_dev->dev, "aw_dev acf parse failed");
+		return -EINVAL;
+	}
+	aw_dev->fade_in_time = AW_1000_US / 10;
+	aw_dev->fade_out_time = AW_1000_US >> 1;
+
+	aw_dev->cur_prof = aw_dev->prof_info.prof_desc[0].id;
+	aw_dev->set_prof = aw_dev->prof_info.prof_desc[0].id;
+	ret = aw883xx_dev_fw_update(aw_dev, AW_FORCE_UPDATE_ON,
+			AW_DSP_FW_UPDATE_ON);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "fw update failed");
+		return ret;
+	}
+
+	/*set mute*/
+	aw883xx_dev_mute(aw_dev, true);
+	usleep_range(AW_4000_US, AW_4000_US + 100);
+
+	/*close tx feedback*/
+	if (aw_dev->ops.aw_i2s_tx_enable)
+		aw_dev->ops.aw_i2s_tx_enable(aw_dev, false);
+	usleep_range(AW_1000_US, AW_1000_US + 100);
+
+	/*close dsp*/
+	aw883xx_dev_dsp_enable(aw_dev, false);
+	/*enable amppd*/
+	aw_dev_amppd(aw_dev, true);
+	/*set power down*/
+	aw_dev_pwd(aw_dev, true);
+
+	return 0;
+}
+
+static void aw883xx_parse_channel_dt(struct aw_device *aw_dev)
+{
+	int ret;
+	u32 channel_value;
+	struct device_node *np = aw_dev->dev->of_node;
+
+	ret = of_property_read_u32(np, "sound-channel", &channel_value);
+	if (ret < 0) {
+		dev_dbg(aw_dev->dev,
+			"read sound-channel failed,use default 0");
+		aw_dev->channel = AW_DEV_DEFAULT_CH;
+		return;
+	}
+
+	dev_dbg(aw_dev->dev, "read sound-channel value is: %d",
+			channel_value);
+	aw_dev->channel = channel_value;
+}
+
+static void aw883xx_parse_fade_enable_dt(struct aw_device *aw_dev)
+{
+	int ret = -1;
+	struct device_node *np = aw_dev->dev->of_node;
+	u32 fade_en;
+
+	ret = of_property_read_u32(np, "fade-enable", &fade_en);
+	if (ret < 0) {
+		dev_dbg(aw_dev->dev,
+			"read fade-enable failed, close fade_in_out");
+		fade_en = AW_FADE_IN_OUT_DEFAULT;
+	} else {
+		dev_dbg(aw_dev->dev, "read fade-enable value is: %d", fade_en);
+	}
+
+	aw_dev->fade_en = fade_en;
+}
+
+static void aw_device_parse_dt(struct aw_device *aw_dev)
+{
+	aw883xx_parse_channel_dt(aw_dev);
+	aw883xx_parse_fade_enable_dt(aw_dev);
+}
+
+int aw883xx_device_probe(struct aw_device *aw_dev)
+{
+	aw_device_parse_dt(aw_dev);
+
+	return 0;
+}
+
+int aw883xx_request_firmware_file(struct aw883xx *aw883xx)
+{
+	const struct firmware *cont = NULL;
+	int ret = -1;
+
+	aw883xx->aw_pa->fw_status = AW_DEV_FW_FAILED;
+
+	ret = request_firmware(&cont, AW_ACF_FILE, aw883xx->dev);
+	if ((ret < 0) || (!cont)) {
+		dev_err(aw883xx->dev, "load [%s] failed!", AW_ACF_FILE);
+		return ret;
+	}
+
+	dev_info(aw883xx->dev, "loaded %s - size: %zu",
+		AW_ACF_FILE, cont ? cont->size : 0);
+
+	aw883xx->aw_cfg = vzalloc(cont->size + sizeof(int));
+	if (!aw883xx->aw_cfg) {
+		release_firmware(cont);
+		return -ENOMEM;
+	}
+	aw883xx->aw_cfg->len = (int)cont->size;
+	memcpy(aw883xx->aw_cfg->data, cont->data, cont->size);
+	release_firmware(cont);
+
+	ret = aw883xx_dev_load_acf_check(aw883xx->aw_cfg);
+	if (ret < 0) {
+		dev_err(aw883xx->dev, "Load [%s] failed ....!", AW_ACF_FILE);
+		vfree(aw883xx->aw_cfg);
+		aw883xx->aw_cfg = NULL;
+		return ret;
+	}
+
+	dev_dbg(aw883xx->dev, "%s : bin load success\n", __func__);
+
+	mutex_lock(&aw883xx->lock);
+	/*aw device init*/
+	ret = aw883xx_device_init(aw883xx->aw_pa, aw883xx->aw_cfg);
+	if (ret < 0) {
+		dev_err(aw883xx->dev, "dev init failed");
+		vfree(aw883xx->aw_cfg);
+		mutex_unlock(&aw883xx->lock);
+		return ret;
+	}
+
+	mutex_unlock(&aw883xx->lock);
+
+	return 0;
+}
+
diff --git a/sound/soc/codecs/aw883xx/aw883xx_device.h b/sound/soc/codecs/aw883xx/aw883xx_device.h
new file mode 100644
index 000000000000..505cef1fd3e6
--- /dev/null
+++ b/sound/soc/codecs/aw883xx/aw883xx_device.h
@@ -0,0 +1,537 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * aw883xx.c --  ALSA Soc AW883XX codec support
+ *
+ * Copyright (c) 2022 AWINIC Technology CO., LTD
+ *
+ * Author: Bruce zhao <zhaolei@awinic.com>
+ */
+
+#ifndef __AW883XX_DEVICE_FILE_H__
+#define __AW883XX_DEVICE_FILE_H__
+
+#include "aw883xx_data_type.h"
+#include "aw883xx.h"
+
+
+#define AW_DEV_DEFAULT_CH		(0)
+#define AW_DEV_DSP_CHECK_MAX	(5)
+
+/*
+ * DSP I2C WRITES
+ */
+#define AW_DSP_I2C_WRITES
+#define AW_MAX_RAM_WRITE_BYTE_SIZE	(128)
+#define AW_DSP_ODD_NUM_BIT_TEST		(0x5555)
+#define AW_DSP_EVEN_NUM_BIT_TEST	(0xAAAA)
+#define AW_DSP_ST_CHECK_MAX		(2)
+#define AW_FADE_IN_OUT_DEFAULT		(0)
+#define AW_CALI_DELAY_CACL(value) ((value * 32) / 48)
+#define AW_CALI_RE_MAX (15000)
+#define AW_CALI_RE_MIN (4000)
+
+#define AW_GET_MIN_VALUE(value1, value2) \
+	((value1) > (value2) ? (value2) : (value1))
+
+#define AW_GET_MAX_VALUE(value1, value2) \
+	((value1) > (value2) ? (value1) : (value2))
+
+#define AW_DSP_RE_TO_SHOW_RE(re, shift) (((re) * (1000)) >> (shift))
+#define AW_SHOW_RE_TO_DSP_RE(re, shift)  (((re) << shift) / (1000))
+
+#define AW_ACF_FILE	"aw883xx_acf.bin"
+#define AW_DEV_SYSST_CHECK_MAX   (10)
+
+enum {
+	AW_EXT_DSP_WRITE_NONE = 0,
+	AW_EXT_DSP_WRITE,
+};
+
+struct aw_device;
+
+enum {
+	AW_DEV_VDSEL_DAC = 0,
+	AW_DEV_VDSEL_VSENSE = 1,
+};
+
+enum {
+	AW_DSP_CRC_NA = 0,
+	AW_DSP_CRC_OK = 1,
+};
+
+enum {
+	AW_DSP_FW_UPDATE_OFF = 0,
+	AW_DSP_FW_UPDATE_ON = 1,
+};
+
+enum {
+	AW_FORCE_UPDATE_OFF = 0,
+	AW_FORCE_UPDATE_ON = 1,
+};
+
+enum {
+	AW_1000_US = 1000,
+	AW_2000_US = 2000,
+	AW_3000_US = 3000,
+	AW_4000_US = 4000,
+	AW_5000_US = 5000,
+	AW_10000_US = 10000,
+	AW_100000_US = 100000,
+};
+
+enum {
+	AW_DEV_TYPE_OK = 0,
+	AW_DEV_TYPE_NONE = 1,
+};
+
+
+enum AW_DEV_STATUS {
+	AW_DEV_PW_OFF = 0,
+	AW_DEV_PW_ON,
+};
+
+enum AW_DEV_FW_STATUS {
+	AW_DEV_FW_FAILED = 0,
+	AW_DEV_FW_OK,
+};
+
+enum AW_DEV_MEMCLK {
+	AW_DEV_MEMCLK_OSC = 0,
+	AW_DEV_MEMCLK_PLL = 1,
+};
+
+enum AW_DEV_DSP_CFG {
+	AW_DEV_DSP_WORK = 0,
+	AW_DEV_DSP_BYPASS = 1,
+};
+
+enum {
+	AW_DSP_16_DATA = 0,
+	AW_DSP_32_DATA = 1,
+};
+
+enum {
+	AW_NOT_RCV_MODE = 0,
+	AW_RCV_MODE = 1,
+};
+
+struct aw_device_ops {
+	int (*aw_i2c_writes)(struct regmap *map, unsigned int reg_addr,
+								const void *val, size_t val_len);
+	int (*aw_i2c_write)(struct regmap *map, unsigned int reg, unsigned int val);
+	int (*aw_i2c_read)(struct regmap *map, unsigned int reg, unsigned int *val);
+
+	int (*aw_reg_write)(struct regmap *map, unsigned int reg, unsigned int val);
+	int (*aw_reg_read)(struct regmap *map, unsigned int reg, unsigned int *val);
+	int (*aw_reg_write_bits)(struct regmap *map, unsigned int reg,
+						unsigned int mask, unsigned int val);
+
+	int (*aw_dsp_write)(struct aw_device *aw_dev,
+						unsigned short dsp_addr,
+						unsigned int reg_data,
+						unsigned char data_type);
+	int (*aw_dsp_read)(struct aw_device *aw_dev,
+						unsigned short dsp_addr,
+						unsigned int *dsp_data,
+						unsigned char data_type);
+	int (*aw_dsp_write_bits)(struct aw_device *aw_dev, unsigned short dsp_addr,
+								unsigned short mask, unsigned short dsp_data);
+
+	int (*aw_set_hw_volume)(struct aw_device *aw_dev, unsigned short value);
+	int (*aw_get_hw_volume)(struct aw_device *aw_dev, unsigned short *value);
+	unsigned int (*aw_reg_val_to_db)(unsigned int value);
+
+	void (*aw_i2s_tx_enable)(struct aw_device *aw_dev, bool flag);
+
+	bool (*aw_check_wr_access)(int reg);
+	int (*aw_get_reg_num)(void);
+	int (*aw_get_version)(char *buf, int size);
+	int (*aw_read_dsp_pid)(struct aw_device *aw_dev);
+	void (*aw_set_cfg_f0_fs)(struct aw_device *aw_dev, unsigned int *f0_fs);
+	int (*aw_dsp_fw_check)(struct aw_device *aw_dev);
+	int (*aw_set_cali_re)(struct aw_device *aw_dev);
+};
+
+struct aw_int_desc {
+	unsigned int mask_reg;			/*interrupt mask reg*/
+	unsigned int st_reg;			/*interrupt status reg*/
+	unsigned int mask_default;		/*default mask close all*/
+	unsigned int int_mask;			/*set mask*/
+	unsigned int intst_mask;		/*interrupt check mask*/
+	u16 sysint_st;			/*interrupt reg status*/
+};
+
+struct aw_pwd_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int enable;
+	unsigned int disable;
+};
+
+struct aw_vcalb_desc {
+	unsigned int icalk_reg;
+	unsigned int icalk_reg_mask;
+	unsigned int icalk_sign_mask;
+	unsigned int icalk_neg_mask;
+	int icalk_value_factor;
+
+	unsigned int vcalk_reg;
+	unsigned int vcalk_reg_mask;
+	unsigned int vcalk_sign_mask;
+	unsigned int vcalk_neg_mask;
+	unsigned int vcalk_shift;
+	int vcalk_value_factor;
+
+	unsigned int vcalb_dsp_reg;
+	unsigned char data_type;
+	int cabl_base_value;
+	int vcal_factor;
+	int vscal_factor;
+	int iscal_factor;
+
+	unsigned int vcalb_adj_shift;
+
+	unsigned int vcalb_vsense_reg;
+	int vscal_factor_vsense_in;
+	int vcalk_value_factor_vsense_in;
+	unsigned int vcalk_dac_shift;
+	unsigned int vcalk_dac_mask;
+	unsigned int vcalk_dac_neg_mask;
+	unsigned int vcalk_vdsel_mask;
+};
+
+struct aw_mute_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int enable;
+	unsigned int disable;
+};
+
+struct aw_sysst_desc {
+	unsigned int reg;
+	unsigned int st_check;
+	unsigned int st_mask;
+	unsigned int pll_check;
+	unsigned int dsp_check;
+	unsigned int dsp_mask;
+};
+
+struct aw_profctrl_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int rcv_mode_val;
+	unsigned int cur_mode;
+};
+
+struct aw_volume_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int shift;
+	unsigned int init_volume;
+	unsigned int mute_volume;
+	unsigned int ctl_volume;
+	unsigned int max_volume;
+};
+
+struct aw_dsp_en_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int enable;
+	unsigned int disable;
+};
+
+struct aw_memclk_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int mcu_hclk;
+	unsigned int osc_clk;
+};
+
+struct aw_watch_dog_desc {
+	unsigned int reg;
+	unsigned int mask;
+};
+
+struct aw_dsp_mem_desc {
+	unsigned int dsp_madd_reg;
+	unsigned int dsp_mdat_reg;
+	unsigned int dsp_fw_base_addr;
+	unsigned int dsp_cfg_base_addr;
+};
+
+struct aw_voltage_desc {
+	unsigned int reg;
+	unsigned int vbat_range;
+	unsigned int int_bit;
+};
+
+struct aw_temperature_desc {
+	unsigned int reg;
+	unsigned int sign_mask;
+	unsigned int neg_mask;
+};
+
+struct aw_ipeak_desc {
+	unsigned int reg;
+	unsigned int mask;
+};
+
+struct aw_vmax_desc {
+	unsigned int dsp_reg;
+	unsigned char data_type;
+	unsigned int init_vmax;
+};
+
+struct aw_soft_rst {
+	u8 reg;
+	u16 reg_value;
+};
+
+struct aw_cali_cfg_desc {
+	unsigned int actampth_reg;
+	unsigned char actampth_data_type;
+
+	unsigned int noiseampth_reg;
+	unsigned char noiseampth_data_type;
+
+	unsigned int ustepn_reg;
+	unsigned char ustepn_data_type;
+
+	unsigned int alphan_reg;
+	unsigned int alphan_data_type;
+};
+
+struct aw_dsp_vol_desc {
+	unsigned int reg;
+	unsigned int mute_st;
+	unsigned int noise_st;
+	unsigned int mask;
+};
+
+struct aw_amppd_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int enable;
+	unsigned int disable;
+};
+
+struct aw_f0_desc {
+	unsigned int dsp_reg;
+	unsigned char data_type;
+	unsigned int shift;
+};
+
+struct aw_cfgf0_fs_desc {
+	unsigned int dsp_reg;
+	unsigned char data_type;
+};
+
+struct aw_q_desc {
+	unsigned int dsp_reg;
+	unsigned char data_type;
+	unsigned int shift;
+};
+
+struct aw_ra_desc {
+	unsigned int dsp_reg;
+	unsigned char data_type;
+};
+
+struct aw_noise_desc {
+	unsigned int dsp_reg;
+	unsigned char data_type;
+	unsigned int mask;
+};
+
+struct aw_ste_re_desc {
+	unsigned int dsp_reg;
+	unsigned char data_type;
+	unsigned int shift;
+};
+
+struct aw_adpz_re_desc {
+	unsigned int dsp_reg;
+	unsigned char data_type;
+	unsigned int shift;
+};
+
+struct aw_adpz_t0_desc {
+	unsigned int dsp_reg;
+	unsigned char data_type;
+	u16 coilalpha_reg;
+	unsigned char coil_type;
+};
+
+struct aw_spkr_temp_desc {
+	unsigned int reg;
+};
+
+struct aw_dsp_crc_desc {
+	unsigned int ctl_reg;
+	unsigned int ctl_mask;
+	unsigned int ctl_enable;
+	unsigned int ctl_disable;
+
+	unsigned int dsp_reg;
+	unsigned char data_type;
+};
+
+struct aw_cco_mux_desc {
+	unsigned int reg;
+	unsigned int mask;
+	unsigned int divider;
+	unsigned int bypass;
+};
+
+struct aw_hw_temp_desc {
+	unsigned int dsp_reg;
+	unsigned char data_type;
+};
+
+struct aw_cali_delay_desc {
+	unsigned int dsp_reg;
+	unsigned char data_type;
+	unsigned int delay;
+};
+
+struct aw_chansel_desc {
+	unsigned int rxchan_reg;
+	unsigned int rxchan_mask;
+	unsigned int txchan_reg;
+	unsigned int txchan_mask;
+
+	unsigned int rx_left;
+	unsigned int rx_right;
+	unsigned int tx_left;
+	unsigned int tx_right;
+};
+
+struct aw_tx_en_desc {
+	unsigned int tx_en_mask;
+	unsigned int tx_disable;
+};
+
+struct aw_dsp_st {
+	unsigned int dsp_reg_s1;
+	unsigned int dsp_reg_e1;
+
+	unsigned int dsp_reg_s2;
+	unsigned int dsp_reg_e2;
+};
+
+struct aw_cali_desc {
+	u32 cali_re;	/*cali value*/
+	u32 ra;
+};
+
+struct aw_container {
+	int len;
+	u8 data[];
+};
+
+struct aw_device {
+	int status;
+	struct mutex *dsp_lock;
+
+	unsigned char cur_prof;	/*current profile index*/
+	unsigned char set_prof;	/*set profile index*/
+	unsigned char dsp_crc_st;
+	u16 chip_id;
+
+	unsigned int channel;	/*pa channel select*/
+	unsigned int fade_step;
+
+	struct i2c_client *i2c;
+	struct device *dev;
+	char *acf;
+	void *private_data;
+
+	u32 fade_en;
+	unsigned char dsp_cfg;
+
+	u32 dsp_fw_len;
+	u32 dsp_cfg_len;
+	u8 platform;
+	u8 fw_status;	/*load cfg status*/
+
+	unsigned int fade_in_time;
+	unsigned int fade_out_time;
+
+	struct aw_prof_info prof_info;
+	struct aw_sec_data_desc crc_dsp_cfg;
+	struct aw_int_desc int_desc;
+	struct aw_pwd_desc pwd_desc;
+	struct aw_mute_desc mute_desc;
+	struct aw_vcalb_desc vcalb_desc;
+	struct aw_sysst_desc sysst_desc;
+	struct aw_profctrl_desc profctrl_desc;
+	struct aw_volume_desc volume_desc;
+	struct aw_dsp_en_desc dsp_en_desc;
+	struct aw_memclk_desc memclk_desc;
+	struct aw_watch_dog_desc watch_dog_desc;
+	struct aw_dsp_mem_desc dsp_mem_desc;
+	struct aw_voltage_desc voltage_desc;
+	struct aw_temperature_desc temp_desc;
+	struct aw_vmax_desc vmax_desc;
+	struct aw_ipeak_desc ipeak_desc;
+	struct aw_soft_rst soft_rst;
+	struct aw_cali_cfg_desc cali_cfg_desc;
+	struct aw_ra_desc ra_desc;
+	struct aw_dsp_vol_desc dsp_vol_desc;
+	struct aw_noise_desc noise_desc;
+	struct aw_f0_desc f0_desc;
+	struct aw_cfgf0_fs_desc cfgf0_fs_desc;
+	struct aw_q_desc q_desc;
+	struct aw_ste_re_desc ste_re_desc;
+	struct aw_adpz_re_desc adpz_re_desc;
+	struct aw_adpz_t0_desc t0_desc;
+	struct aw_amppd_desc amppd_desc;
+	struct aw_spkr_temp_desc spkr_temp_desc;
+	struct aw_dsp_crc_desc dsp_crc_desc;
+	struct aw_cco_mux_desc cco_mux_desc;
+	struct aw_hw_temp_desc hw_temp_desc;
+
+	struct aw_chansel_desc chansel_desc;
+	struct aw_tx_en_desc tx_en_desc;
+	struct aw_cali_delay_desc cali_delay_desc;
+	struct aw_dsp_st dsp_st_desc;
+	struct aw_cali_desc cali_desc;
+
+	struct aw_device_ops ops;
+};
+
+void aw883xx_dev_deinit(struct aw_device *aw_dev);
+int aw883xx_device_init(struct aw_device *aw_dev, struct aw_container *aw_prof);
+int aw883xx_device_start(struct aw_device *aw_dev);
+int aw883xx_device_stop(struct aw_device *aw_dev);
+
+int aw883xx_dev_fw_update(struct aw_device *aw_dev, bool up_dsp_fw_en, bool force_up_en);
+
+int aw883xx_device_probe(struct aw_device *aw_dev);
+int aw883xx_device_remove(struct aw_device *aw_dev);
+int aw883xx_dev_syspll_check(struct aw_device *aw_dev);
+int aw883xx_dev_get_dsp_status(struct aw_device *aw_dev);
+
+int aw883xx_dev_get_hmute(struct aw_device *aw_dev);
+int aw883xx_dev_sysst_check(struct aw_device *aw_dev);
+
+int aw883xx_dev_dsp_check(struct aw_device *aw_dev);
+void aw883xx_dev_memclk_select(struct aw_device *aw_dev, unsigned char flag);
+
+void aw883xx_dev_dsp_enable(struct aw_device *aw_dev, bool dsp);
+
+void aw883xx_dev_mute(struct aw_device *aw_dev, bool mute);
+int aw883xx_dev_dsp_fw_update(struct aw_device *aw_dev,
+			unsigned char *data, unsigned int len);
+int aw883xx_dev_dsp_cfg_update(struct aw_device *aw_dev,
+			unsigned char *data, unsigned int len);
+int aw883xx_dev_modify_dsp_cfg(struct aw_device *aw_dev,
+			unsigned int addr, unsigned int dsp_data, unsigned char data_type);
+int aw883xx_dev_get_iis_status(struct aw_device *aw_dev);
+
+int aw883xx_dev_set_volume(struct aw_device *aw_dev, unsigned short set_vol);
+int aw883xx_dev_get_volume(struct aw_device *aw_dev, unsigned short *get_vol);
+int aw883xx_request_firmware_file(struct aw883xx *aw883xx);
+
+#endif
+
-- 
2.38.1

[PATCH V6 4/5] ASoC: codecs: Configure aw883xx chip register as well as Kconfig and Makefile

[wangweidong.a]

From: Weidong Wang <wangweidong.a@awinic.com>

The Awinic AW883XX is an I2S/TDM input, high efficiency
digital Smart K audio amplifier with an integrated 10.25V
smart boost convert

Signed-off-by: Nick Li <liweilei@awinic.com>
Signed-off-by: Bruce zhao <zhaolei@awinic.com>
Signed-off-by: Weidong Wang <wangweidong.a@awinic.com>
---
 sound/soc/codecs/Kconfig                      |   10 +
 sound/soc/codecs/Makefile                     |    7 +
 sound/soc/codecs/aw883xx/aw883xx_data_type.h  |  146 ++
 sound/soc/codecs/aw883xx/aw883xx_init.c       |  615 +++++
 .../soc/codecs/aw883xx/aw883xx_pid_2049_reg.h | 2300 +++++++++++++++++
 5 files changed, 3078 insertions(+)
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx_data_type.h
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx_init.c
 create mode 100644 sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h

diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 7022e6286e6c..f14e0a78acd4 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -54,6 +54,7 @@ config SND_SOC_ALL_CODECS
 	imply SND_SOC_ALC5623
 	imply SND_SOC_ALC5632
 	imply SND_SOC_AW8738
+	imply SND_SOC_AW883XX
 	imply SND_SOC_BT_SCO
 	imply SND_SOC_BD28623
 	imply SND_SOC_CQ0093VC
@@ -2161,4 +2162,13 @@ config SND_SOC_LPASS_TX_MACRO
 	select SND_SOC_LPASS_MACRO_COMMON
 	tristate "Qualcomm TX Macro in LPASS(Low Power Audio SubSystem)"
 
+config SND_SOC_AW883XX
+	tristate "Soc Audio for awinic aw883xx series"
+	depends on I2C
+	help
+	  this option enables support for aw883xx series Smart PA.
+	  The Awinic AW883XX is an I2S/TDM input, high efficiency
+	  digital Smart K audio amplifier with an integrated 10V
+	  smart boost convert.
+
 endmenu
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 9170ee1447dd..858ca24ad398 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -357,6 +357,11 @@ snd-soc-tas2780-objs := tas2780.o
 # Mux
 snd-soc-simple-mux-objs := simple-mux.o
 
+snd_soc_aw883xx-objs := aw883xx/aw883xx.o \
+						aw883xx/aw883xx_init.o \
+						aw883xx/aw883xx_device.o \
+						aw883xx/aw883xx_bin_parse.o \
+
 obj-$(CONFIG_SND_SOC_88PM860X)	+= snd-soc-88pm860x.o
 obj-$(CONFIG_SND_SOC_AB8500_CODEC)	+= snd-soc-ab8500-codec.o
 obj-$(CONFIG_SND_SOC_AC97_CODEC)	+= snd-soc-ac97.o
@@ -719,3 +724,5 @@ obj-$(CONFIG_SND_SOC_LPASS_TX_MACRO)	+= snd-soc-lpass-tx-macro.o
 
 # Mux
 obj-$(CONFIG_SND_SOC_SIMPLE_MUX)	+= snd-soc-simple-mux.o
+
+obj-$(CONFIG_SND_SOC_AW883XX) +=snd_soc_aw883xx.o
diff --git a/sound/soc/codecs/aw883xx/aw883xx_data_type.h b/sound/soc/codecs/aw883xx/aw883xx_data_type.h
new file mode 100644
index 000000000000..3aacf5eedde6
--- /dev/null
+++ b/sound/soc/codecs/aw883xx/aw883xx_data_type.h
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * aw883xx.c --  ALSA Soc AW883XX codec support
+ *
+ * Copyright (c) 2022 AWINIC Technology CO., LTD
+ *
+ * Author: Bruce zhao <zhaolei@awinic.com>
+ */
+
+#ifndef __AW883XX_DATA_TYPE_H__
+#define __AW883XX_DATA_TYPE_H__
+
+/*
+ * aw profile
+ */
+#define PROJECT_NAME_MAX (24)
+#define CUSTOMER_NAME_MAX (16)
+#define CFG_VERSION_MAX (4)
+#define DEV_NAME_MAX (16)
+#define PROFILE_STR_MAX (32)
+
+#define ACF_FILE_ID (0xa15f908)
+
+enum aw_cfg_hdr_version {
+	AW_CFG_HDR_VER_0_0_0_1 = 0x00000001,
+	AW_CFG_HDR_VER_1_0_0_0 = 0x01000000,
+};
+
+enum aw_cfg_dde_type {
+	AW_DEV_NONE_TYPE_ID = 0xFFFFFFFF,
+	AW_DEV_TYPE_ID = 0x00000000,
+	AW_SKT_TYPE_ID = 0x00000001,
+	AW_DEV_DEFAULT_TYPE_ID = 0x00000002,
+};
+
+enum aw_sec_type {
+	ACF_SEC_TYPE_REG = 0,
+	ACF_SEC_TYPE_DSP,
+	ACF_SEC_TYPE_DSP_CFG,
+	ACF_SEC_TYPE_DSP_FW,
+	ACF_SEC_TYPE_HDR_REG,
+	ACF_SEC_TYPE_HDR_DSP_CFG,
+	ACF_SEC_TYPE_HDR_DSP_FW,
+	ACF_SEC_TYPE_MUTLBIN,
+	ACF_SEC_TYPE_SKT_PROJECT,
+	ACF_SEC_TYPE_DSP_PROJECT,
+	ACF_SEC_TYPE_MONITOR,
+	ACF_SEC_TYPE_MAX,
+};
+
+enum profile_data_type {
+	AW_DATA_TYPE_REG = 0,
+	AW_DATA_TYPE_DSP_CFG,
+	AW_DATA_TYPE_DSP_FW,
+	AW_DATA_TYPE_MAX,
+};
+
+enum aw_prof_type {
+	AW_PROFILE_MUSIC = 0,
+	AW_PROFILE_VOICE,
+	AW_PROFILE_VOIP,
+	AW_PROFILE_RINGTONE,
+	AW_PROFILE_RINGTONE_HS,
+	AW_PROFILE_LOWPOWER,
+	AW_PROFILE_BYPASS,
+	AW_PROFILE_MMI,
+	AW_PROFILE_FM,
+	AW_PROFILE_NOTIFICATION,
+	AW_PROFILE_RECEIVER,
+	AW_PROFILE_MAX,
+};
+
+enum aw_profile_status {
+	AW_PROFILE_WAIT = 0,
+	AW_PROFILE_OK,
+};
+
+struct aw_cfg_hdr {
+	u32 a_id;					/*acf file ID 0xa15f908*/
+	char a_project[PROJECT_NAME_MAX];		/*project name*/
+	char a_custom[CUSTOMER_NAME_MAX];		/*custom name :huawei xiaomi vivo oppo*/
+	char a_version[CFG_VERSION_MAX];		/*author update version*/
+	u32 a_author_id;				/*author id*/
+	u32 a_ddt_size;				/*sub section table entry size*/
+	u32 a_ddt_num;				/*sub section table entry num*/
+	u32 a_hdr_offset;				/*sub section table offset in file*/
+	u32 a_hdr_version;				/*sub section table version*/
+	u32 reserve[3];
+};
+
+struct aw_cfg_dde {
+	u32 type;					/*DDE type id*/
+	char dev_name[DEV_NAME_MAX];
+	u16 dev_index;				/*dev id*/
+	u16 dev_bus;				/*dev bus id*/
+	u16 dev_addr;				/*dev addr id*/
+	u16 dev_profile;				/*dev profile id*/
+	u32 data_type;				/*data type id*/
+	u32 data_size;
+	u32 data_offset;
+	u32 data_crc;
+	u32 reserve[5];
+};
+
+struct aw_cfg_dde_v_1_0_0_0 {
+	u32 type;					/*DDE type id*/
+	char dev_name[DEV_NAME_MAX];
+	u16 dev_index;				/*dev id*/
+	u16 dev_bus;				/*dev bus id*/
+	u16 dev_addr;				/*dev addr id*/
+	u16 dev_profile;				/*dev profile id*/
+	u32 data_type;				/*data type id*/
+	u32 data_size;
+	u32 data_offset;
+	u32 data_crc;
+	char dev_profile_str[PROFILE_STR_MAX];
+	u32 chip_id;
+	u32 reserve[4];
+};
+
+struct aw_sec_data_desc {
+	u32 len;
+	unsigned char *data;
+};
+
+struct aw_prof_desc {
+	u32 id;
+	u32 prof_st;
+	char *prf_str;
+	u32 fw_ver;
+	struct aw_sec_data_desc sec_desc[AW_DATA_TYPE_MAX];
+};
+
+struct aw_all_prof_info {
+	struct aw_prof_desc prof_desc[AW_PROFILE_MAX];
+};
+
+struct aw_prof_info {
+	int count;
+	int prof_type;
+	char **prof_name_list;
+	struct aw_prof_desc *prof_desc;
+};
+
+#endif
+
diff --git a/sound/soc/codecs/aw883xx/aw883xx_init.c b/sound/soc/codecs/aw883xx/aw883xx_init.c
new file mode 100644
index 000000000000..2ef62fdebb57
--- /dev/null
+++ b/sound/soc/codecs/aw883xx/aw883xx_init.c
@@ -0,0 +1,615 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * aw883xx.c --  ALSA Soc AW883XX codec support
+ *
+ * Copyright (c) 2022 AWINIC Technology CO., LTD
+ *
+ * Author: Bruce zhao <zhaolei@awinic.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/firmware.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+#include <linux/syscalls.h>
+#include <linux/uaccess.h>
+#include <linux/version.h>
+#include <linux/workqueue.h>
+#include <sound/control.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include "aw883xx.h"
+#include "aw883xx_bin_parse.h"
+#include "aw883xx_pid_2049_reg.h"
+
+static const unsigned char aw_pid_2049_reg_access[AW_PID_2049_REG_MAX] = {
+	[AW_PID_2049_ID_REG]		= (REG_RD_ACCESS),
+	[AW_PID_2049_SYSST_REG]		= (REG_RD_ACCESS),
+	[AW_PID_2049_SYSINT_REG]	= (REG_RD_ACCESS),
+	[AW_PID_2049_SYSINTM_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_SYSCTRL_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_SYSCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_I2SCTRL_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_I2SCFG1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_I2SCFG2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_HAGCCFG1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_HAGCCFG2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_HAGCCFG3_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_HAGCCFG4_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_HAGCCFG5_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_HAGCCFG6_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_HAGCCFG7_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_MPDCFG_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_PWMCTRL_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_I2SCFG3_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_DBGCTRL_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_HAGCST_REG]	= (REG_RD_ACCESS),
+	[AW_PID_2049_VBAT_REG]		= (REG_RD_ACCESS),
+	[AW_PID_2049_TEMP_REG]		= (REG_RD_ACCESS),
+	[AW_PID_2049_PVDD_REG]		= (REG_RD_ACCESS),
+	[AW_PID_2049_ISNDAT_REG]	= (REG_RD_ACCESS),
+	[AW_PID_2049_VSNDAT_REG]	= (REG_RD_ACCESS),
+	[AW_PID_2049_I2SINT_REG]	= (REG_RD_ACCESS),
+	[AW_PID_2049_I2SCAPCNT_REG]	= (REG_RD_ACCESS),
+	[AW_PID_2049_ANASTA1_REG]	= (REG_RD_ACCESS),
+	[AW_PID_2049_ANASTA2_REG]	= (REG_RD_ACCESS),
+	[AW_PID_2049_ANASTA3_REG]	= (REG_RD_ACCESS),
+	[AW_PID_2049_ANASTA4_REG]	= (REG_RD_ACCESS),
+	[AW_PID_2049_TESTDET_REG]	= (REG_RD_ACCESS),
+	[AW_PID_2049_TESTIN_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_TESTOUT_REG]	= (REG_RD_ACCESS),
+	[AW_PID_2049_DSPMADD_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_DSPMDAT_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_WDT_REG]		= (REG_RD_ACCESS),
+	[AW_PID_2049_ACR1_REG]		= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_ACR2_REG]		= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_ASR1_REG]		= (REG_RD_ACCESS),
+	[AW_PID_2049_ASR2_REG]		= (REG_RD_ACCESS),
+	[AW_PID_2049_DSPCFG_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_ASR3_REG]		= (REG_RD_ACCESS),
+	[AW_PID_2049_ASR4_REG]		= (REG_RD_ACCESS),
+	[AW_PID_2049_VSNCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_ISNCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_PLLCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_PLLCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_PLLCTRL3_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_CDACTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_CDACTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_SADCCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_SADCCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_CPCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_BSTCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_BSTCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_BSTCTRL3_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_BSTCTRL4_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_BSTCTRL5_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_BSTCTRL6_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_BSTCTRL7_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_DSMCFG1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_DSMCFG2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_DSMCFG3_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_DSMCFG4_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_DSMCFG5_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_DSMCFG6_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_DSMCFG7_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_DSMCFG8_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_TESTCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_TESTCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_EFCTRL1_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_EFCTRL2_REG]	= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_EFWH_REG]		= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_EFWM2_REG]		= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_EFWM1_REG]		= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_EFWL_REG]		= (REG_RD_ACCESS | REG_WR_ACCESS),
+	[AW_PID_2049_EFRH_REG]		= (REG_RD_ACCESS),
+	[AW_PID_2049_EFRM2_REG]		= (REG_RD_ACCESS),
+	[AW_PID_2049_EFRM1_REG]		= (REG_RD_ACCESS),
+	[AW_PID_2049_EFRL_REG]		= (REG_RD_ACCESS),
+	[AW_PID_2049_TM_REG]		= (REG_NONE_ACCESS),
+};
+
+static int aw883xx_dev_dsp_write(struct aw_device *aw_dev,
+			unsigned short dsp_addr, unsigned int dsp_data, unsigned char data_type)
+{
+	struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
+
+	return aw883xx_dsp_write(aw883xx, dsp_addr, dsp_data, data_type);
+}
+
+static int aw883xx_dev_dsp_read(struct aw_device *aw_dev,
+			unsigned short dsp_addr, unsigned int *dsp_data, unsigned char data_type)
+{
+	struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
+
+	return aw883xx_dsp_read(aw883xx, dsp_addr, dsp_data, data_type);
+}
+
+/*
+ * aw883xx i2c write/read
+ */
+/*[9 : 6]: -6DB ; [5 : 0]: -0.125DB  real_value = value * 8 : 0.125db --> 1*/
+static unsigned int aw_pid_2049_reg_val_to_db(unsigned int value)
+{
+	return (((value >> AW_PID_2049_VOL_6DB_START) * AW_PID_2049_VOLUME_STEP_DB) +
+			((value & 0x3f) % AW_PID_2049_VOLUME_STEP_DB));
+}
+
+/*[9 : 6]: -6DB ; [5 : 0]: -0.125DB reg_value = value / step << 6 + value % step ; step = 6 * 8*/
+static unsigned short aw_pid_2049_db_val_to_reg(unsigned short value)
+{
+	return (((value / AW_PID_2049_VOLUME_STEP_DB) << AW_PID_2049_VOL_6DB_START) +
+			(value % AW_PID_2049_VOLUME_STEP_DB));
+}
+
+static int aw883xx_set_volume(struct aw883xx *aw883xx, unsigned short value)
+{
+	unsigned int reg_value = 0;
+	u16 real_value = 0;
+	u16 volume = 0;
+	struct aw_volume_desc *vol_desc = &aw883xx->aw_pa->volume_desc;
+
+	volume = AW_GET_MIN_VALUE(value, vol_desc->mute_volume);
+	real_value = aw_pid_2049_db_val_to_reg(volume);
+
+	/* cal real value */
+	regmap_read(aw883xx->regmap, AW_PID_2049_SYSCTRL2_REG, &reg_value);
+
+	dev_dbg(aw883xx->dev, "value 0x%x , reg:0x%x", value, real_value);
+
+	/*[15 : 6] volume*/
+	real_value = (real_value << AW_PID_2049_VOL_START_BIT) | (reg_value & AW_PID_2049_VOL_MASK);
+
+	/* write value */
+	regmap_write(aw883xx->regmap, AW_PID_2049_SYSCTRL2_REG, real_value);
+
+	return 0;
+}
+
+static int aw883xx_get_volume(struct aw883xx *aw883xx, unsigned short *value)
+{
+	unsigned int reg_value = 0;
+	u16 real_value = 0;
+
+	/* read value */
+	regmap_read(aw883xx->regmap, AW_PID_2049_SYSCTRL2_REG, &reg_value);
+
+	/*[15 : 6] volume*/
+	real_value = reg_value >> AW_PID_2049_VOL_START_BIT;
+
+	real_value = aw_pid_2049_reg_val_to_db(real_value);
+
+	*value = real_value;
+
+	return 0;
+}
+
+static int aw_pid_2049_set_volume(struct aw_device *aw_dev, unsigned short value)
+{
+	struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
+
+	return aw883xx_set_volume(aw883xx, value);
+}
+
+static int aw_pid_2049_get_volume(struct aw_device *aw_dev, unsigned short *value)
+{
+	struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
+
+	return aw883xx_get_volume(aw883xx, value);
+}
+
+static void aw_pid_2049_i2s_tx_enable(struct aw_device *aw_dev, bool flag)
+{
+	struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
+
+	if (flag) {
+		regmap_update_bits(aw883xx->regmap, AW_PID_2049_I2SCFG1_REG,
+				~AW_PID_2049_I2STXEN_MASK,
+				AW_PID_2049_I2STXEN_ENABLE_VALUE);
+	} else {
+		regmap_update_bits(aw883xx->regmap, AW_PID_2049_I2SCFG1_REG,
+				~AW_PID_2049_I2STXEN_MASK,
+				AW_PID_2049_I2STXEN_DISABLE_VALUE);
+	}
+}
+
+static void aw_pid_2049_set_cfg_f0_fs(struct aw_device *aw_dev, unsigned int *f0_fs)
+{
+	unsigned int rate_data = 0;
+	u32 fs = 0;
+	struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
+
+	regmap_read(aw883xx->regmap, AW_PID_2049_I2SCTRL_REG, &rate_data);
+
+	switch (rate_data & (~AW_PID_2049_I2SSR_MASK)) {
+	case AW_PID_2049_I2SSR_8_KHZ_VALUE:
+		fs = 8000;
+		break;
+	case AW_PID_2049_I2SSR_16_KHZ_VALUE:
+		fs = 16000;
+		break;
+	case AW_PID_2049_I2SSR_32_KHZ_VALUE:
+		fs = 32000;
+		break;
+	case AW_PID_2049_I2SSR_44_KHZ_VALUE:
+		fs = 44000;
+		break;
+	case AW_PID_2049_I2SSR_48_KHZ_VALUE:
+		fs = 48000;
+		break;
+	case AW_PID_2049_I2SSR_96_KHZ_VALUE:
+		fs = 96000;
+		break;
+	case AW_PID_2049_I2SSR_192KHZ_VALUE:
+		fs = 192000;
+		break;
+	default:
+		fs = 48000;
+		dev_err(aw883xx->dev,
+			"rate can not support, use default 48k");
+		break;
+	}
+
+	dev_dbg(aw883xx->dev, "get i2s fs:%d", fs);
+	*f0_fs = fs / 8;
+
+	aw883xx_dsp_write(aw883xx,
+		AW_PID_2049_DSP_REG_CFGF0_FS, *f0_fs, AW_DSP_32_DATA);
+}
+
+static bool aw_pid_2049_check_wr_access(int reg)
+{
+	if (reg >= AW_PID_2049_REG_MAX)
+		return false;
+
+	if (aw_pid_2049_reg_access[reg] & REG_WR_ACCESS)
+		return true;
+	else
+		return false;
+}
+
+static int aw_pid_2049_get_reg_num(void)
+{
+	return AW_PID_2049_REG_MAX;
+}
+
+static int aw_pid_2049_dsp_fw_check(struct aw_device *aw_dev)
+{
+	struct aw_prof_desc *set_prof_desc = NULL;
+	struct aw_sec_data_desc *dsp_fw_desc = NULL;
+	u16 base_addr = AW_PID_2049_DSP_FW_ADDR;
+	u16 addr = base_addr;
+	int ret, i;
+	u32 dsp_val;
+	u16 bin_val;
+
+	ret = aw883xx_dev_get_prof_data(aw_dev, aw_dev->cur_prof, &set_prof_desc);
+	if (ret < 0)
+		return ret;
+
+	/*update reg*/
+	dsp_fw_desc = &set_prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW];
+
+	for (i = 0; i < AW_FW_CHECK_PART; i++) {
+		ret = aw883xx_dev_dsp_read(aw_dev, addr, &dsp_val, AW_DSP_16_DATA);
+		if (ret  < 0) {
+			dev_err(aw_dev->dev, "dsp read failed");
+			return ret;
+		}
+
+		bin_val = be16_to_cpup((void *)&dsp_fw_desc->data[2 * (addr - base_addr)]);
+
+		if (dsp_val != bin_val) {
+			dev_err(aw_dev->dev, "check failed, addr[0x%x], read[0x%x] != bindata[0x%x]",
+					addr, dsp_val, bin_val);
+			return -EINVAL;
+		}
+
+		addr += (dsp_fw_desc->len / 2) / AW_FW_CHECK_PART;
+		if ((addr - base_addr) > dsp_fw_desc->len) {
+			dev_err(aw_dev->dev, "check failed, addr[0x%x] too large", addr);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static int aw_pid_2049_set_cali_re_to_dsp(struct aw_device *aw_dev)
+{
+	struct aw_adpz_re_desc *adpz_re_desc = &aw_dev->adpz_re_desc;
+	u32 cali_re = 0;
+	int ret = 0;
+
+	cali_re = AW_SHOW_RE_TO_DSP_RE((aw_dev->cali_desc.cali_re +
+		aw_dev->cali_desc.ra), adpz_re_desc->shift);
+
+	/* set cali re to aw883xx */
+	ret = aw_dev->ops.aw_dsp_write(aw_dev,
+			adpz_re_desc->dsp_reg, cali_re, adpz_re_desc->data_type);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "set cali re error");
+		return ret;
+	}
+
+	ret = aw883xx_dev_modify_dsp_cfg(aw_dev, adpz_re_desc->dsp_reg,
+				cali_re, adpz_re_desc->data_type);
+	if (ret < 0) {
+		dev_err(aw_dev->dev, "modify dsp cfg failed");
+		return ret;
+	}
+
+	return ret;
+
+}
+
+static int aw883xx_pid_2049_dev_init(struct aw883xx *aw883xx)
+{
+	struct aw_device *aw_pa = NULL;
+
+	aw_pa = devm_kzalloc(aw883xx->dev, sizeof(struct aw_device), GFP_KERNEL);
+	if (!aw_pa)
+		return -ENOMEM;
+
+	/*call aw device init func*/
+	aw_pa->acf = NULL;
+	aw_pa->prof_info.prof_desc = NULL;
+	aw_pa->prof_info.count = 0;
+	aw_pa->prof_info.prof_type = AW_DEV_NONE_TYPE_ID;
+	aw_pa->channel = 0;
+	aw_pa->dsp_lock = &aw883xx->dsp_lock;
+	aw_pa->i2c = aw883xx->i2c;
+	aw_pa->fw_status = AW_DEV_FW_FAILED;
+	aw_pa->fade_step = AW_PID_2049_VOLUME_STEP_DB;
+
+	aw_pa->chip_id = aw883xx->chip_id;
+	aw_pa->private_data = (void *)aw883xx;
+	aw_pa->dev = aw883xx->dev;
+	aw_pa->ops.aw_i2c_writes = regmap_raw_write;
+	aw_pa->ops.aw_i2c_write = regmap_write;
+	aw_pa->ops.aw_reg_write = regmap_write;
+	aw_pa->ops.aw_reg_write_bits = regmap_update_bits;
+	aw_pa->ops.aw_i2c_read = regmap_read;
+	aw_pa->ops.aw_reg_read = regmap_read;
+	aw_pa->ops.aw_dsp_read = aw883xx_dev_dsp_read;
+	aw_pa->ops.aw_dsp_write = aw883xx_dev_dsp_write;
+
+	aw_pa->ops.aw_get_hw_volume = aw_pid_2049_get_volume;
+	aw_pa->ops.aw_set_hw_volume = aw_pid_2049_set_volume;
+	aw_pa->ops.aw_reg_val_to_db = aw_pid_2049_reg_val_to_db;
+
+	aw_pa->ops.aw_check_wr_access = aw_pid_2049_check_wr_access;
+	aw_pa->ops.aw_get_reg_num = aw_pid_2049_get_reg_num;
+
+	aw_pa->ops.aw_i2s_tx_enable = aw_pid_2049_i2s_tx_enable;
+
+	aw_pa->ops.aw_set_cfg_f0_fs = aw_pid_2049_set_cfg_f0_fs;
+	aw_pa->ops.aw_dsp_fw_check = aw_pid_2049_dsp_fw_check;
+
+	aw_pa->ops.aw_set_cali_re = aw_pid_2049_set_cali_re_to_dsp;
+
+	aw_pa->int_desc.mask_reg = AW_PID_2049_SYSINTM_REG;
+	aw_pa->int_desc.mask_default = AW_PID_2049_SYSINTM_DEFAULT;
+	aw_pa->int_desc.int_mask = AW_PID_2049_SYSINTM_DEFAULT;
+	aw_pa->int_desc.st_reg = AW_PID_2049_SYSINT_REG;
+	aw_pa->int_desc.intst_mask = AW_PID_2049_BIT_SYSINT_CHECK;
+
+	aw_pa->pwd_desc.reg = AW_PID_2049_SYSCTRL_REG;
+	aw_pa->pwd_desc.mask = AW_PID_2049_PWDN_MASK;
+	aw_pa->pwd_desc.enable = AW_PID_2049_PWDN_POWER_DOWN_VALUE;
+	aw_pa->pwd_desc.disable = AW_PID_2049_PWDN_WORKING_VALUE;
+
+	aw_pa->mute_desc.reg = AW_PID_2049_SYSCTRL_REG;
+	aw_pa->mute_desc.mask = AW_PID_2049_HMUTE_MASK;
+	aw_pa->mute_desc.enable = AW_PID_2049_HMUTE_ENABLE_VALUE;
+	aw_pa->mute_desc.disable = AW_PID_2049_HMUTE_DISABLE_VALUE;
+
+	aw_pa->vcalb_desc.vcalb_dsp_reg = AW_PID_2049_DSP_REG_VCALB;
+	aw_pa->vcalb_desc.data_type = AW_DSP_16_DATA;
+	aw_pa->vcalb_desc.vcal_factor = AW_PID_2049_VCAL_FACTOR;
+	aw_pa->vcalb_desc.cabl_base_value = AW_PID_2049_CABL_BASE_VALUE;
+	aw_pa->vcalb_desc.vscal_factor = AW_PID_2049_VSCAL_FACTOR;
+	aw_pa->vcalb_desc.iscal_factor = AW_PID_2049_ISCAL_FACTOR;
+
+	aw_pa->vcalb_desc.vcalb_adj_shift = AW_PID_2049_VCALB_ADJ_FACTOR;
+
+	aw_pa->vcalb_desc.icalk_value_factor = AW_PID_2049_ICABLK_FACTOR;
+	aw_pa->vcalb_desc.icalk_reg = AW_PID_2049_EFRM2_REG;
+	aw_pa->vcalb_desc.icalk_reg_mask = AW_PID_2049_EF_ISN_GESLP_MASK;
+	aw_pa->vcalb_desc.icalk_sign_mask = AW_PID_2049_EF_ISN_GESLP_SIGN_MASK;
+	aw_pa->vcalb_desc.icalk_neg_mask = AW_PID_2049_EF_ISN_GESLP_SIGN_NEG;
+
+	aw_pa->vcalb_desc.vcalk_reg = AW_PID_2049_EFRH_REG;
+	aw_pa->vcalb_desc.vcalk_reg_mask = AW_PID_2049_EF_VSN_GESLP_MASK;
+	aw_pa->vcalb_desc.vcalk_sign_mask = AW_PID_2049_EF_VSN_GESLP_SIGN_MASK;
+	aw_pa->vcalb_desc.vcalk_neg_mask = AW_PID_2049_EF_VSN_GESLP_SIGN_NEG;
+	aw_pa->vcalb_desc.vcalk_value_factor = AW_PID_2049_VCABLK_FACTOR;
+	aw_pa->vcalb_desc.vcalk_shift = AW_PID_2049_EF_VSENSE_GAIN_SHIFT;
+
+	aw_pa->vcalb_desc.vcalb_vsense_reg = AW_PID_2049_I2SCFG3_REG;
+	aw_pa->vcalb_desc.vcalk_vdsel_mask = AW_PID_2049_VDSEL_MASK;
+	aw_pa->vcalb_desc.vcalk_value_factor_vsense_in = AW_PID_2049_VCABLK_FACTOR_DAC;
+	aw_pa->vcalb_desc.vscal_factor_vsense_in = AW_PID_2049_VSCAL_FACTOR_DAC;
+	aw_pa->vcalb_desc.vcalk_dac_shift = AW_PID_2049_EF_DAC_GESLP_SHIFT;
+	aw_pa->vcalb_desc.vcalk_dac_mask = AW_PID_2049_EF_DAC_GESLP_SIGN_MASK;
+	aw_pa->vcalb_desc.vcalk_dac_neg_mask = AW_PID_2049_EF_DAC_GESLP_SIGN_NEG;
+
+	aw_pa->sysst_desc.reg = AW_PID_2049_SYSST_REG;
+	aw_pa->sysst_desc.st_check = AW_PID_2049_BIT_SYSST_CHECK;
+	aw_pa->sysst_desc.st_mask = AW_PID_2049_BIT_SYSST_CHECK_MASK;
+	aw_pa->sysst_desc.pll_check = AW_PID_2049_BIT_PLL_CHECK;
+	aw_pa->sysst_desc.dsp_check = AW_PID_2049_DSPS_NORMAL_VALUE;
+	aw_pa->sysst_desc.dsp_mask = AW_PID_2049_DSPS_MASK;
+
+	aw_pa->profctrl_desc.reg = AW_PID_2049_SYSCTRL_REG;
+	aw_pa->profctrl_desc.mask = AW_PID_2049_RCV_MODE_MASK;
+	aw_pa->profctrl_desc.rcv_mode_val = AW_PID_2049_RCV_MODE_RECEIVER_VALUE;
+
+	aw_pa->volume_desc.reg = AW_PID_2049_SYSCTRL2_REG;
+	aw_pa->volume_desc.mask = AW_PID_2049_VOL_MASK;
+	aw_pa->volume_desc.shift = AW_PID_2049_VOL_START_BIT;
+	aw_pa->volume_desc.mute_volume = AW_PID_2049_MUTE_VOL;
+	aw_pa->volume_desc.max_volume = AW_PID_2049_VOL_DEFAULT_VALUE;
+	aw_pa->volume_desc.ctl_volume = AW_PID_2049_VOL_DEFAULT_VALUE;
+
+	aw_pa->dsp_en_desc.reg = AW_PID_2049_SYSCTRL_REG;
+	aw_pa->dsp_en_desc.mask = AW_PID_2049_DSPBY_MASK;
+	aw_pa->dsp_en_desc.enable = AW_PID_2049_DSPBY_WORKING_VALUE;
+	aw_pa->dsp_en_desc.disable = AW_PID_2049_DSPBY_BYPASS_VALUE;
+
+	aw_pa->memclk_desc.reg = AW_PID_2049_DBGCTRL_REG;
+	aw_pa->memclk_desc.mask = AW_PID_2049_MEM_CLKSEL_MASK;
+	aw_pa->memclk_desc.mcu_hclk = AW_PID_2049_MEM_CLKSEL_DAP_HCLK_VALUE;
+	aw_pa->memclk_desc.osc_clk = AW_PID_2049_MEM_CLKSEL_OSC_CLK_VALUE;
+
+	aw_pa->watch_dog_desc.reg = AW_PID_2049_WDT_REG;
+	aw_pa->watch_dog_desc.mask = AW_PID_2049_WDT_CNT_MASK;
+
+	aw_pa->dsp_mem_desc.dsp_madd_reg = AW_PID_2049_DSPMADD_REG;
+	aw_pa->dsp_mem_desc.dsp_mdat_reg = AW_PID_2049_DSPMDAT_REG;
+	aw_pa->dsp_mem_desc.dsp_cfg_base_addr = AW_PID_2049_DSP_CFG_ADDR;
+	aw_pa->dsp_mem_desc.dsp_fw_base_addr = AW_PID_2049_DSP_FW_ADDR;
+
+	aw_pa->voltage_desc.reg = AW_PID_2049_VBAT_REG;
+	aw_pa->voltage_desc.vbat_range = AW_PID_2049_VBAT_RANGE;
+	aw_pa->voltage_desc.int_bit = AW_PID_2049_INT_10BIT;
+
+	aw_pa->temp_desc.reg = AW_PID_2049_TEMP_REG;
+	aw_pa->temp_desc.sign_mask = AW_PID_2049_TEMP_SIGN_MASK;
+	aw_pa->temp_desc.neg_mask = AW_PID_2049_TEMP_NEG_MASK;
+
+	aw_pa->vmax_desc.dsp_reg = AW_PID_2049_DSP_REG_VMAX;
+	aw_pa->vmax_desc.data_type = AW_DSP_16_DATA;
+
+	aw_pa->ipeak_desc.reg = AW_PID_2049_SYSCTRL2_REG;
+	aw_pa->ipeak_desc.mask = AW_PID_2049_BST_IPEAK_MASK;
+
+	aw_pa->soft_rst.reg = AW_PID_2049_ID_REG;
+	aw_pa->soft_rst.reg_value = AW_PID_2049_SOFT_RESET_VALUE;
+
+	aw_pa->dsp_vol_desc.reg = AW_PID_2049_DSPCFG_REG;
+	aw_pa->dsp_vol_desc.mask = AW_PID_2049_DSP_VOL_MASK;
+	aw_pa->dsp_vol_desc.mute_st = AW_PID_2049_DSP_VOL_MUTE;
+	aw_pa->dsp_vol_desc.noise_st = AW_PID_2049_DSP_VOL_NOISE_ST;
+
+	aw_pa->amppd_desc.reg = AW_PID_2049_SYSCTRL_REG;
+	aw_pa->amppd_desc.mask = AW_PID_2049_AMPPD_MASK;
+	aw_pa->amppd_desc.enable = AW_PID_2049_AMPPD_POWER_DOWN_VALUE;
+	aw_pa->amppd_desc.disable = AW_PID_2049_AMPPD_WORKING_VALUE;
+
+	aw_pa->spkr_temp_desc.reg = AW_PID_2049_ASR2_REG;
+
+	/*32-bit data types need bypass dsp*/
+	aw_pa->ra_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_RA;
+	aw_pa->ra_desc.data_type = AW_DSP_32_DATA;
+
+	/*32-bit data types need bypass dsp*/
+	aw_pa->cali_cfg_desc.actampth_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_ACTAMPTH;
+	aw_pa->cali_cfg_desc.actampth_data_type = AW_DSP_32_DATA;
+
+	/*32-bit data types need bypass dsp*/
+	aw_pa->cali_cfg_desc.noiseampth_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_NOISEAMPTH;
+	aw_pa->cali_cfg_desc.noiseampth_data_type = AW_DSP_32_DATA;
+
+	aw_pa->cali_cfg_desc.ustepn_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_USTEPN;
+	aw_pa->cali_cfg_desc.ustepn_data_type = AW_DSP_16_DATA;
+
+	aw_pa->cali_cfg_desc.alphan_reg = AW_PID_2049_DSP_REG_CFG_RE_ALPHA;
+	aw_pa->cali_cfg_desc.alphan_data_type = AW_DSP_16_DATA;
+
+	/*32-bit data types need bypass dsp*/
+	aw_pa->adpz_re_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_RE;
+	aw_pa->adpz_re_desc.data_type = AW_DSP_32_DATA;
+	aw_pa->adpz_re_desc.shift = AW_PID_2049_DSP_RE_SHIFT;
+
+	aw_pa->t0_desc.dsp_reg = AW_PID_2049_DSP_CFG_ADPZ_T0;
+	aw_pa->t0_desc.data_type = AW_DSP_16_DATA;
+	aw_pa->t0_desc.coilalpha_reg = AW_PID_2049_DSP_CFG_ADPZ_COILALPHA;
+	aw_pa->t0_desc.coil_type = AW_DSP_16_DATA;
+
+	aw_pa->ste_re_desc.shift = AW_PID_2049_DSP_REG_CALRE_SHIFT;
+	aw_pa->ste_re_desc.dsp_reg = AW_PID_2049_DSP_REG_CALRE;
+	aw_pa->ste_re_desc.data_type = AW_DSP_16_DATA;
+
+	aw_pa->noise_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_GLBCFG;
+	aw_pa->noise_desc.data_type = AW_DSP_16_DATA;
+	aw_pa->noise_desc.mask = AW_PID_2049_DSP_REG_NOISE_MASK;
+
+	aw_pa->f0_desc.dsp_reg = AW_PID_2049_DSP_REG_RESULT_F0;
+	aw_pa->f0_desc.shift = AW_PID_2049_DSP_F0_SHIFT;
+	aw_pa->f0_desc.data_type = AW_DSP_16_DATA;
+
+	/*32-bit data types need bypass dsp*/
+	aw_pa->cfgf0_fs_desc.dsp_reg = AW_PID_2049_DSP_REG_CFGF0_FS;
+	aw_pa->cfgf0_fs_desc.data_type = AW_DSP_32_DATA;
+
+	aw_pa->q_desc.dsp_reg = AW_PID_2049_DSP_REG_RESULT_Q;
+	aw_pa->q_desc.shift = AW_PID_2049_DSP_Q_SHIFT;
+	aw_pa->q_desc.data_type = AW_DSP_16_DATA;
+
+	/*32-bit data types need bypass dsp*/
+	aw_pa->dsp_crc_desc.dsp_reg = AW_PID_2049_DSP_REG_CRC_ADDR;
+	aw_pa->dsp_crc_desc.data_type = AW_DSP_32_DATA;
+
+	aw_pa->dsp_crc_desc.ctl_reg = AW_PID_2049_HAGCCFG7_REG;
+	aw_pa->dsp_crc_desc.ctl_mask = AW_PID_2049_AGC_DSP_CTL_MASK;
+	aw_pa->dsp_crc_desc.ctl_enable = AW_PID_2049_AGC_DSP_CTL_ENABLE_VALUE;
+	aw_pa->dsp_crc_desc.ctl_disable = AW_PID_2049_AGC_DSP_CTL_DISABLE_VALUE;
+
+	aw_pa->cco_mux_desc.reg = AW_PID_2049_PLLCTRL1_REG;
+	aw_pa->cco_mux_desc.mask = AW_PID_2049_CCO_MUX_MASK;
+	aw_pa->cco_mux_desc.divider = AW_PID_2049_CCO_MUX_DIVIDED_VALUE;
+	aw_pa->cco_mux_desc.bypass = AW_PID_2049_CCO_MUX_BYPASS_VALUE;
+
+	/*hw monitor temp reg*/
+	aw_pa->hw_temp_desc.dsp_reg = AW_PID_2049_DSP_REG_TEMP_ADDR;
+	aw_pa->hw_temp_desc.data_type = AW_DSP_16_DATA;
+
+	aw_pa->chansel_desc.rxchan_reg = AW_PID_2049_I2SCTRL_REG;
+	aw_pa->chansel_desc.rxchan_mask = AW_PID_2049_CHSEL_MASK;
+	aw_pa->chansel_desc.txchan_reg = AW_PID_2049_I2SCFG1_REG;
+	aw_pa->chansel_desc.txchan_mask = AW_PID_2049_I2SCHS_MASK;
+
+	aw_pa->chansel_desc.rx_left = AW_PID_2049_CHSEL_LEFT_VALUE;
+	aw_pa->chansel_desc.rx_right = AW_PID_2049_CHSEL_RIGHT_VALUE;
+	aw_pa->chansel_desc.tx_left = AW_PID_2049_I2SCHS_LEFT_VALUE;
+	aw_pa->chansel_desc.tx_right = AW_PID_2049_I2SCHS_RIGHT_VALUE;
+
+	aw_pa->tx_en_desc.tx_en_mask = AW_PID_2049_I2STXEN_MASK;
+	aw_pa->tx_en_desc.tx_disable = AW_PID_2049_I2STXEN_DISABLE_VALUE;
+
+	aw_pa->cali_delay_desc.dsp_reg = AW_PID_2049_DSP_CALI_F0_DELAY;
+	aw_pa->cali_delay_desc.data_type = AW_DSP_16_DATA;
+
+	aw_pa->dsp_st_desc.dsp_reg_s1 = AW_PID_2049_DSP_ST_S1;
+	aw_pa->dsp_st_desc.dsp_reg_e1 = AW_PID_2049_DSP_ST_E1;
+	aw_pa->dsp_st_desc.dsp_reg_s2 = AW_PID_2049_DSP_ST_S2;
+	aw_pa->dsp_st_desc.dsp_reg_e2 = AW_PID_2049_DSP_ST_E2;
+
+	aw883xx_device_probe(aw_pa);
+
+	aw883xx->aw_pa = aw_pa;
+
+	return 0;
+}
+
+int aw883xx_init(struct aw883xx *aw883xx)
+{
+	int ret = 0;
+
+	switch (aw883xx->chip_id) {
+	case AW883XX_PID_2049:
+		ret = aw883xx_pid_2049_dev_init(aw883xx);
+		break;
+	default:
+		ret = -EINVAL;
+		dev_err(aw883xx->dev, "unsupported device");
+		break;
+	}
+	return ret;
+}
+
diff --git a/sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h b/sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h
new file mode 100644
index 000000000000..e7c4703d1627
--- /dev/null
+++ b/sound/soc/codecs/aw883xx/aw883xx_pid_2049_reg.h
@@ -0,0 +1,2300 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * aw883xx.c --  ALSA Soc AW883XX codec support
+ *
+ * Copyright (c) 2022 AWINIC Technology CO., LTD
+ *
+ * Author: Bruce zhao <zhaolei@awinic.com>
+ */
+
+#ifndef __AW883XX_PID_2049_REG_H__
+#define __AW883XX_PID_2049_REG_H__
+
+#define AW_PID_2049_ID_REG				(0x00)
+#define AW_PID_2049_SYSST_REG			(0x01)
+#define AW_PID_2049_SYSINT_REG			(0x02)
+#define AW_PID_2049_SYSINTM_REG			(0x03)
+#define AW_PID_2049_SYSCTRL_REG			(0x04)
+#define AW_PID_2049_SYSCTRL2_REG		(0x05)
+#define AW_PID_2049_I2SCTRL_REG			(0x06)
+#define AW_PID_2049_I2SCFG1_REG			(0x07)
+#define AW_PID_2049_I2SCFG2_REG			(0x08)
+#define AW_PID_2049_HAGCCFG1_REG		(0x09)
+#define AW_PID_2049_HAGCCFG2_REG		(0x0A)
+#define AW_PID_2049_HAGCCFG3_REG		(0x0B)
+#define AW_PID_2049_HAGCCFG4_REG		(0x0C)
+#define AW_PID_2049_HAGCCFG5_REG		(0x0D)
+#define AW_PID_2049_HAGCCFG6_REG		(0x0E)
+#define AW_PID_2049_HAGCCFG7_REG		(0x0F)
+#define AW_PID_2049_MPDCFG_REG			(0x10)
+#define AW_PID_2049_PWMCTRL_REG			(0x11)
+#define AW_PID_2049_I2SCFG3_REG			(0x12)
+#define AW_PID_2049_DBGCTRL_REG			(0x13)
+#define AW_PID_2049_HAGCST_REG			(0x20)
+#define AW_PID_2049_VBAT_REG			(0x21)
+#define AW_PID_2049_TEMP_REG			(0x22)
+#define AW_PID_2049_PVDD_REG			(0x23)
+#define AW_PID_2049_ISNDAT_REG			(0x24)
+#define AW_PID_2049_VSNDAT_REG			(0x25)
+#define AW_PID_2049_I2SINT_REG			(0x26)
+#define AW_PID_2049_I2SCAPCNT_REG		(0x27)
+#define AW_PID_2049_ANASTA1_REG			(0x28)
+#define AW_PID_2049_ANASTA2_REG			(0x29)
+#define AW_PID_2049_ANASTA3_REG			(0x2A)
+#define AW_PID_2049_ANASTA4_REG			(0x2B)
+#define AW_PID_2049_TESTDET_REG			(0x2C)
+#define AW_PID_2049_TESTIN_REG			(0x38)
+#define AW_PID_2049_TESTOUT_REG			(0x39)
+#define AW_PID_2049_DSPMADD_REG			(0x40)
+#define AW_PID_2049_DSPMDAT_REG			(0x41)
+#define AW_PID_2049_WDT_REG				(0x42)
+#define AW_PID_2049_ACR1_REG			(0x43)
+#define AW_PID_2049_ACR2_REG			(0x44)
+#define AW_PID_2049_ASR1_REG			(0x45)
+#define AW_PID_2049_ASR2_REG			(0x46)
+#define AW_PID_2049_DSPCFG_REG			(0x47)
+#define AW_PID_2049_ASR3_REG			(0x48)
+#define AW_PID_2049_ASR4_REG			(0x49)
+#define AW_PID_2049_VSNCTRL1_REG		(0x50)
+#define AW_PID_2049_ISNCTRL1_REG		(0x51)
+#define AW_PID_2049_PLLCTRL1_REG		(0x52)
+#define AW_PID_2049_PLLCTRL2_REG		(0x53)
+#define AW_PID_2049_PLLCTRL3_REG		(0x54)
+#define AW_PID_2049_CDACTRL1_REG		(0x55)
+#define AW_PID_2049_CDACTRL2_REG		(0x56)
+#define AW_PID_2049_SADCCTRL1_REG		(0x57)
+#define AW_PID_2049_SADCCTRL2_REG		(0x58)
+#define AW_PID_2049_CPCTRL1_REG			(0x59)
+#define AW_PID_2049_BSTCTRL1_REG		(0x60)
+#define AW_PID_2049_BSTCTRL2_REG		(0x61)
+#define AW_PID_2049_BSTCTRL3_REG		(0x62)
+#define AW_PID_2049_BSTCTRL4_REG		(0x63)
+#define AW_PID_2049_BSTCTRL5_REG		(0x64)
+#define AW_PID_2049_BSTCTRL6_REG		(0x65)
+#define AW_PID_2049_BSTCTRL7_REG		(0x66)
+#define AW_PID_2049_DSMCFG1_REG			(0x67)
+#define AW_PID_2049_DSMCFG2_REG			(0x68)
+#define AW_PID_2049_DSMCFG3_REG			(0x69)
+#define AW_PID_2049_DSMCFG4_REG			(0x6A)
+#define AW_PID_2049_DSMCFG5_REG			(0x6B)
+#define AW_PID_2049_DSMCFG6_REG			(0x6C)
+#define AW_PID_2049_DSMCFG7_REG			(0x6D)
+#define AW_PID_2049_DSMCFG8_REG			(0x6E)
+#define AW_PID_2049_TESTCTRL1_REG		(0x70)
+#define AW_PID_2049_TESTCTRL2_REG		(0x71)
+#define AW_PID_2049_EFCTRL1_REG			(0x72)
+#define AW_PID_2049_EFCTRL2_REG			(0x73)
+#define AW_PID_2049_EFWH_REG			(0x74)
+#define AW_PID_2049_EFWM2_REG			(0x75)
+#define AW_PID_2049_EFWM1_REG			(0x76)
+#define AW_PID_2049_EFWL_REG			(0x77)
+#define AW_PID_2049_EFRH_REG			(0x78)
+#define AW_PID_2049_EFRM2_REG			(0x79)
+#define AW_PID_2049_EFRM1_REG			(0x7A)
+#define AW_PID_2049_EFRL_REG			(0x7B)
+#define AW_PID_2049_TM_REG				(0x7C)
+
+/*
+ * Register Access
+ */
+enum aw883xx_id {
+	AW883XX_PID_2049 = 0x2049,
+};
+
+#define AW_PID_2049_REG_MAX				(0x7D)
+
+#define REG_NONE_ACCESS					(0)
+#define REG_RD_ACCESS					(1 << 0)
+#define REG_WR_ACCESS					(1 << 1)
+
+#define AW_PID_2049_VOLUME_STEP_DB	(6 * 8)
+
+/* detail information of registers begin */
+/* ID (0x00) detail */
+/* IDCODE bit 15:0 (ID 0x00) */
+#define AW_PID_2049_IDCODE_START_BIT	(0)
+#define AW_PID_2049_IDCODE_BITS_LEN		(16)
+#define AW_PID_2049_IDCODE_MASK			\
+	(~(((1<<AW_PID_2049_IDCODE_BITS_LEN)-1) << AW_PID_2049_IDCODE_START_BIT))
+
+#define AW_PID_2049_IDCODE_DEFAULT_VALUE	(0x2049)
+#define AW_PID_2049_IDCODE_DEFAULT		\
+	(AW_PID_2049_IDCODE_DEFAULT_VALUE << AW_PID_2049_IDCODE_START_BIT)
+
+#define AW_PID_2049_SOFT_RESET_VALUE	(0x55aa)
+
+/* default value of ID (0x00) */
+/* #define AW_PID_2049_ID_DEFAULT		(0x2049) */
+
+/* SYSST (0x01) detail */
+/* OVP2S bit 15 (SYSST 0x01) */
+#define AW_PID_2049_OVP2S_START_BIT		(15)
+#define AW_PID_2049_OVP2S_BITS_LEN		(1)
+#define AW_PID_2049_OVP2S_MASK			\
+	(~(((1<<AW_PID_2049_OVP2S_BITS_LEN)-1) << AW_PID_2049_OVP2S_START_BIT))
+
+#define AW_PID_2049_OVP2S_NORMAL		(0)
+#define AW_PID_2049_OVP2S_NORMAL_VALUE	\
+	(AW_PID_2049_OVP2S_NORMAL << AW_PID_2049_OVP2S_START_BIT)
+
+#define AW_PID_2049_OVP2S_OVP			(1)
+#define AW_PID_2049_OVP2S_OVP_VALUE		\
+	(AW_PID_2049_OVP2S_OVP << AW_PID_2049_OVP2S_START_BIT)
+
+#define AW_PID_2049_OVP2S_DEFAULT_VALUE	(0)
+#define AW_PID_2049_OVP2S_DEFAULT		\
+	(AW_PID_2049_OVP2S_DEFAULT_VALUE << AW_PID_2049_OVP2S_START_BIT)
+
+/* UVLS bit 14 (SYSST 0x01) */
+#define AW_PID_2049_UVLS_START_BIT		(14)
+#define AW_PID_2049_UVLS_BITS_LEN		(1)
+#define AW_PID_2049_UVLS_MASK			\
+	(~(((1<<AW_PID_2049_UVLS_BITS_LEN)-1) << AW_PID_2049_UVLS_START_BIT))
+
+#define AW_PID_2049_UVLS_NORMAL			(0)
+#define AW_PID_2049_UVLS_NORMAL_VALUE	\
+	(AW_PID_2049_UVLS_NORMAL << AW_PID_2049_UVLS_START_BIT)
+
+#define AW_PID_2049_UVLS_UVLO			(1)
+#define AW_PID_2049_UVLS_UVLO_VALUE		\
+	(AW_PID_2049_UVLS_UVLO << AW_PID_2049_UVLS_START_BIT)
+
+#define AW_PID_2049_UVLS_DEFAULT_VALUE	(0)
+#define AW_PID_2049_UVLS_DEFAULT		\
+	(AW_PID_2049_UVLS_DEFAULT_VALUE << AW_PID_2049_UVLS_START_BIT)
+
+/* ADPS bit 13 (SYSST 0x01) */
+#define AW_PID_2049_ADPS_START_BIT		(13)
+#define AW_PID_2049_ADPS_BITS_LEN		(1)
+#define AW_PID_2049_ADPS_MASK			\
+	(~(((1<<AW_PID_2049_ADPS_BITS_LEN)-1) << AW_PID_2049_ADPS_START_BIT))
+
+#define AW_PID_2049_ADPS_TRANSPARENT	(0)
+#define AW_PID_2049_ADPS_TRANSPARENT_VALUE	\
+	(AW_PID_2049_ADPS_TRANSPARENT << AW_PID_2049_ADPS_START_BIT)
+
+#define AW_PID_2049_ADPS_BOOST			(1)
+#define AW_PID_2049_ADPS_BOOST_VALUE	\
+	(AW_PID_2049_ADPS_BOOST << AW_PID_2049_ADPS_START_BIT)
+
+#define AW_PID_2049_ADPS_DEFAULT_VALUE	(0)
+#define AW_PID_2049_ADPS_DEFAULT		\
+	(AW_PID_2049_ADPS_DEFAULT_VALUE << AW_PID_2049_ADPS_START_BIT)
+
+/* DSPS bit 12 (SYSST 0x01) */
+#define AW_PID_2049_DSPS_START_BIT		(12)
+#define AW_PID_2049_DSPS_BITS_LEN		(1)
+#define AW_PID_2049_DSPS_MASK			\
+	(~(((1<<AW_PID_2049_DSPS_BITS_LEN)-1) << AW_PID_2049_DSPS_START_BIT))
+
+#define AW_PID_2049_DSPS_NORMAL			(0)
+#define AW_PID_2049_DSPS_NORMAL_VALUE	\
+	(AW_PID_2049_DSPS_NORMAL << AW_PID_2049_DSPS_START_BIT)
+
+#define AW_PID_2049_DSPS_DSP_STABLE		(1)
+#define AW_PID_2049_DSPS_DSP_STABLE_VALUE	\
+	(AW_PID_2049_DSPS_DSP_STABLE << AW_PID_2049_DSPS_START_BIT)
+
+#define AW_PID_2049_DSPS_DEFAULT_VALUE	(0)
+#define AW_PID_2049_DSPS_DEFAULT		\
+	(AW_PID_2049_DSPS_DEFAULT_VALUE << AW_PID_2049_DSPS_START_BIT)
+
+/* BSTOCS bit 11 (SYSST 0x01) */
+#define AW_PID_2049_BSTOCS_START_BIT	(11)
+#define AW_PID_2049_BSTOCS_BITS_LEN		(1)
+#define AW_PID_2049_BSTOCS_MASK			\
+	(~(((1<<AW_PID_2049_BSTOCS_BITS_LEN)-1) << AW_PID_2049_BSTOCS_START_BIT))
+
+#define AW_PID_2049_BSTOCS_NORMAL		(0)
+#define AW_PID_2049_BSTOCS_NORMAL_VALUE	\
+	(AW_PID_2049_BSTOCS_NORMAL << AW_PID_2049_BSTOCS_START_BIT)
+
+#define AW_PID_2049_BSTOCS_OVER_CURRENT	(1)
+#define AW_PID_2049_BSTOCS_OVER_CURRENT_VALUE	\
+	(AW_PID_2049_BSTOCS_OVER_CURRENT << AW_PID_2049_BSTOCS_START_BIT)
+
+#define AW_PID_2049_BSTOCS_DEFAULT_VALUE	(0)
+#define AW_PID_2049_BSTOCS_DEFAULT		\
+	(AW_PID_2049_BSTOCS_DEFAULT_VALUE << AW_PID_2049_BSTOCS_START_BIT)
+
+/* OVPS bit 10 (SYSST 0x01) */
+#define AW_PID_2049_OVPS_START_BIT		(10)
+#define AW_PID_2049_OVPS_BITS_LEN		(1)
+#define AW_PID_2049_OVPS_MASK			\
+	(~(((1<<AW_PID_2049_OVPS_BITS_LEN)-1) << AW_PID_2049_OVPS_START_BIT))
+
+#define AW_PID_2049_OVPS_NORMAL			(0)
+#define AW_PID_2049_OVPS_NORMAL_VALUE	\
+	(AW_PID_2049_OVPS_NORMAL << AW_PID_2049_OVPS_START_BIT)
+
+#define AW_PID_2049_OVPS_OVP			(1)
+#define AW_PID_2049_OVPS_OVP_VALUE		\
+	(AW_PID_2049_OVPS_OVP << AW_PID_2049_OVPS_START_BIT)
+
+#define AW_PID_2049_OVPS_DEFAULT_VALUE	(0)
+#define AW_PID_2049_OVPS_DEFAULT		\
+	(AW_PID_2049_OVPS_DEFAULT_VALUE << AW_PID_2049_OVPS_START_BIT)
+
+/* BSTS bit 9 (SYSST 0x01) */
+#define AW_PID_2049_BSTS_START_BIT		(9)
+#define AW_PID_2049_BSTS_BITS_LEN		(1)
+#define AW_PID_2049_BSTS_MASK			\
+	(~(((1<<AW_PID_2049_BSTS_BITS_LEN)-1) << AW_PID_2049_BSTS_START_BIT))
+
+#define AW_PID_2049_BSTS_NOT_FINISHED	(0)
+#define AW_PID_2049_BSTS_NOT_FINISHED_VALUE	\
+	(AW_PID_2049_BSTS_NOT_FINISHED << AW_PID_2049_BSTS_START_BIT)
+
+#define AW_PID_2049_BSTS_FINISHED		(1)
+#define AW_PID_2049_BSTS_FINISHED_VALUE	\
+	(AW_PID_2049_BSTS_FINISHED << AW_PID_2049_BSTS_START_BIT)
+
+#define AW_PID_2049_BSTS_DEFAULT_VALUE	(0)
+#define AW_PID_2049_BSTS_DEFAULT		\
+	(AW_PID_2049_BSTS_DEFAULT_VALUE << AW_PID_2049_BSTS_START_BIT)
+
+/* SWS bit 8 (SYSST 0x01) */
+#define AW_PID_2049_SWS_START_BIT		(8)
+#define AW_PID_2049_SWS_BITS_LEN		(1)
+#define AW_PID_2049_SWS_MASK			\
+	(~(((1<<AW_PID_2049_SWS_BITS_LEN)-1) << AW_PID_2049_SWS_START_BIT))
+
+#define AW_PID_2049_SWS_NOT_SWITCHING	(0)
+#define AW_PID_2049_SWS_NOT_SWITCHING_VALUE	\
+	(AW_PID_2049_SWS_NOT_SWITCHING << AW_PID_2049_SWS_START_BIT)
+
+#define AW_PID_2049_SWS_SWITCHING		(1)
+#define AW_PID_2049_SWS_SWITCHING_VALUE	\
+	(AW_PID_2049_SWS_SWITCHING << AW_PID_2049_SWS_START_BIT)
+
+#define AW_PID_2049_SWS_DEFAULT_VALUE	(0)
+#define AW_PID_2049_SWS_DEFAULT			\
+	(AW_PID_2049_SWS_DEFAULT_VALUE << AW_PID_2049_SWS_START_BIT)
+
+/* CLIPS bit 7 (SYSST 0x01) */
+#define AW_PID_2049_CLIPS_START_BIT		(7)
+#define AW_PID_2049_CLIPS_BITS_LEN		(1)
+#define AW_PID_2049_CLIPS_MASK			\
+	(~(((1<<AW_PID_2049_CLIPS_BITS_LEN)-1) << AW_PID_2049_CLIPS_START_BIT))
+
+#define AW_PID_2049_CLIPS_NOT_CLIPPING	(0)
+#define AW_PID_2049_CLIPS_NOT_CLIPPING_VALUE	\
+	(AW_PID_2049_CLIPS_NOT_CLIPPING << AW_PID_2049_CLIPS_START_BIT)
+
+#define AW_PID_2049_CLIPS_CLIPPING		(1)
+#define AW_PID_2049_CLIPS_CLIPPING_VALUE	\
+	(AW_PID_2049_CLIPS_CLIPPING << AW_PID_2049_CLIPS_START_BIT)
+
+#define AW_PID_2049_CLIPS_DEFAULT_VALUE	(0)
+#define AW_PID_2049_CLIPS_DEFAULT		\
+	(AW_PID_2049_CLIPS_DEFAULT_VALUE << AW_PID_2049_CLIPS_START_BIT)
+
+/* WDS bit 6 (SYSST 0x01) */
+#define AW_PID_2049_WDS_START_BIT		(6)
+#define AW_PID_2049_WDS_BITS_LEN		(1)
+#define AW_PID_2049_WDS_MASK			\
+	(~(((1<<AW_PID_2049_WDS_BITS_LEN)-1) << AW_PID_2049_WDS_START_BIT))
+
+#define AW_PID_2049_WDS_NORMAL			(0)
+#define AW_PID_2049_WDS_NORMAL_VALUE	\
+	(AW_PID_2049_WDS_NORMAL << AW_PID_2049_WDS_START_BIT)
+
+#define AW_PID_2049_WDS_ABNORMAL		(1)
+#define AW_PID_2049_WDS_ABNORMAL_VALUE	\
+	(AW_PID_2049_WDS_ABNORMAL << AW_PID_2049_WDS_START_BIT)
+
+#define AW_PID_2049_WDS_DEFAULT_VALUE	(0)
+#define AW_PID_2049_WDS_DEFAULT			\
+	(AW_PID_2049_WDS_DEFAULT_VALUE << AW_PID_2049_WDS_START_BIT)
+
+/* NOCLKS bit 5 (SYSST 0x01) */
+#define AW_PID_2049_NOCLKS_START_BIT	(5)
+#define AW_PID_2049_NOCLKS_BITS_LEN		(1)
+#define AW_PID_2049_NOCLKS_MASK			\
+	(~(((1<<AW_PID_2049_NOCLKS_BITS_LEN)-1) << AW_PID_2049_NOCLKS_START_BIT))
+
+#define AW_PID_2049_NOCLKS_CLOCK_OK		(0)
+#define AW_PID_2049_NOCLKS_CLOCK_OK_VALUE	\
+	(AW_PID_2049_NOCLKS_CLOCK_OK << AW_PID_2049_NOCLKS_START_BIT)
+
+#define AW_PID_2049_NOCLKS_NO_CLOCK		(1)
+#define AW_PID_2049_NOCLKS_NO_CLOCK_VALUE	\
+	(AW_PID_2049_NOCLKS_NO_CLOCK << AW_PID_2049_NOCLKS_START_BIT)
+
+#define AW_PID_2049_NOCLKS_DEFAULT_VALUE	(0)
+#define AW_PID_2049_NOCLKS_DEFAULT		\
+	(AW_PID_2049_NOCLKS_DEFAULT_VALUE << AW_PID_2049_NOCLKS_START_BIT)
+
+/* CLKS bit 4 (SYSST 0x01) */
+#define AW_PID_2049_CLKS_START_BIT		(4)
+#define AW_PID_2049_CLKS_BITS_LEN		(1)
+#define AW_PID_2049_CLKS_MASK			\
+	(~(((1<<AW_PID_2049_CLKS_BITS_LEN)-1) << AW_PID_2049_CLKS_START_BIT))
+
+#define AW_PID_2049_CLKS_NOT_STABLE		(0)
+#define AW_PID_2049_CLKS_NOT_STABLE_VALUE	\
+	(AW_PID_2049_CLKS_NOT_STABLE << AW_PID_2049_CLKS_START_BIT)
+
+#define AW_PID_2049_CLKS_STABLE			(1)
+#define AW_PID_2049_CLKS_STABLE_VALUE	\
+	(AW_PID_2049_CLKS_STABLE << AW_PID_2049_CLKS_START_BIT)
+
+#define AW_PID_2049_CLKS_DEFAULT_VALUE	(0)
+#define AW_PID_2049_CLKS_DEFAULT		\
+	(AW_PID_2049_CLKS_DEFAULT_VALUE << AW_PID_2049_CLKS_START_BIT)
+
+/* OCDS bit 3 (SYSST 0x01) */
+#define AW_PID_2049_OCDS_START_BIT		(3)
+#define AW_PID_2049_OCDS_BITS_LEN		(1)
+#define AW_PID_2049_OCDS_MASK			\
+	(~(((1<<AW_PID_2049_OCDS_BITS_LEN)-1) << AW_PID_2049_OCDS_START_BIT))
+
+#define AW_PID_2049_OCDS_NORAML			(0)
+#define AW_PID_2049_OCDS_NORAML_VALUE	\
+	(AW_PID_2049_OCDS_NORAML << AW_PID_2049_OCDS_START_BIT)
+
+#define AW_PID_2049_OCDS_OC				(1)
+#define AW_PID_2049_OCDS_OC_VALUE		\
+	(AW_PID_2049_OCDS_OC << AW_PID_2049_OCDS_START_BIT)
+
+#define AW_PID_2049_OCDS_DEFAULT_VALUE	(0)
+#define AW_PID_2049_OCDS_DEFAULT		\
+	(AW_PID_2049_OCDS_DEFAULT_VALUE << AW_PID_2049_OCDS_START_BIT)
+
+/* CLIP_PRES bit 2 (SYSST 0x01) */
+#define AW_PID_2049_CLIP_PRES_START_BIT	(2)
+#define AW_PID_2049_CLIP_PRES_BITS_LEN	(1)
+#define AW_PID_2049_CLIP_PRES_MASK		\
+	(~(((1<<AW_PID_2049_CLIP_PRES_BITS_LEN)-1) << AW_PID_2049_CLIP_PRES_START_BIT))
+
+#define AW_PID_2049_CLIP_PRES_NOT_CLIPPING	(0)
+#define AW_PID_2049_CLIP_PRES_NOT_CLIPPING_VALUE	\
+	(AW_PID_2049_CLIP_PRES_NOT_CLIPPING << AW_PID_2049_CLIP_PRES_START_BIT)
+
+#define AW_PID_2049_CLIP_PRES_CLIPPING	(1)
+#define AW_PID_2049_CLIP_PRES_CLIPPING_VALUE	\
+	(AW_PID_2049_CLIP_PRES_CLIPPING << AW_PID_2049_CLIP_PRES_START_BIT)
+
+#define AW_PID_2049_CLIP_PRES_DEFAULT_VALUE	(0)
+#define AW_PID_2049_CLIP_PRES_DEFAULT	\
+	(AW_PID_2049_CLIP_PRES_DEFAULT_VALUE << AW_PID_2049_CLIP_PRES_START_BIT)
+
+/* OTHS bit 1 (SYSST 0x01) */
+#define AW_PID_2049_OTHS_START_BIT		(1)
+#define AW_PID_2049_OTHS_BITS_LEN		(1)
+#define AW_PID_2049_OTHS_MASK			\
+	(~(((1<<AW_PID_2049_OTHS_BITS_LEN)-1) << AW_PID_2049_OTHS_START_BIT))
+
+#define AW_PID_2049_OTHS_NORMAL			(0)
+#define AW_PID_2049_OTHS_NORMAL_VALUE	\
+	(AW_PID_2049_OTHS_NORMAL << AW_PID_2049_OTHS_START_BIT)
+
+#define AW_PID_2049_OTHS_OT				(1)
+#define AW_PID_2049_OTHS_OT_VALUE		\
+	(AW_PID_2049_OTHS_OT << AW_PID_2049_OTHS_START_BIT)
+
+#define AW_PID_2049_OTHS_DEFAULT_VALUE	(0)
+#define AW_PID_2049_OTHS_DEFAULT		\
+	(AW_PID_2049_OTHS_DEFAULT_VALUE << AW_PID_2049_OTHS_START_BIT)
+
+/* PLLS bit 0 (SYSST 0x01) */
+#define AW_PID_2049_PLLS_START_BIT		(0)
+#define AW_PID_2049_PLLS_BITS_LEN		(1)
+#define AW_PID_2049_PLLS_MASK			\
+	(~(((1<<AW_PID_2049_PLLS_BITS_LEN)-1) << AW_PID_2049_PLLS_START_BIT))
+
+#define AW_PID_2049_PLLS_UNLOCKED		(0)
+#define AW_PID_2049_PLLS_UNLOCKED_VALUE	\
+	(AW_PID_2049_PLLS_UNLOCKED << AW_PID_2049_PLLS_START_BIT)
+
+#define AW_PID_2049_PLLS_LOCKED			(1)
+#define AW_PID_2049_PLLS_LOCKED_VALUE	\
+	(AW_PID_2049_PLLS_LOCKED << AW_PID_2049_PLLS_START_BIT)
+
+#define AW_PID_2049_PLLS_DEFAULT_VALUE	(0)
+#define AW_PID_2049_PLLS_DEFAULT		\
+	(AW_PID_2049_PLLS_DEFAULT_VALUE << AW_PID_2049_PLLS_START_BIT)
+
+
+
+#define AW_PID_2049_BIT_PLL_CHECK \
+		(AW_PID_2049_CLKS_STABLE_VALUE | \
+		AW_PID_2049_PLLS_LOCKED_VALUE)
+
+
+#define AW_PID_2049_BIT_SYSST_CHECK_MASK \
+		(~(AW_PID_2049_UVLS_NORMAL_VALUE | \
+		AW_PID_2049_BSTOCS_OVER_CURRENT_VALUE | \
+		AW_PID_2049_BSTS_FINISHED_VALUE | \
+		AW_PID_2049_SWS_SWITCHING_VALUE | \
+		AW_PID_2049_NOCLKS_NO_CLOCK_VALUE | \
+		AW_PID_2049_CLKS_STABLE_VALUE | \
+		AW_PID_2049_OCDS_OC_VALUE | \
+		AW_PID_2049_OTHS_OT_VALUE | \
+		AW_PID_2049_PLLS_LOCKED_VALUE))
+
+#define AW_PID_2049_BIT_SYSST_CHECK \
+		(AW_PID_2049_BSTS_FINISHED_VALUE | \
+		AW_PID_2049_SWS_SWITCHING_VALUE | \
+		AW_PID_2049_CLKS_STABLE_VALUE | \
+		AW_PID_2049_PLLS_LOCKED_VALUE)
+
+/* default value of SYSST (0x01) */
+/* #define AW_PID_2049_SYSST_DEFAULT		(0x0000) */
+
+/* SYSINT (0x02) detail */
+/* OVP2I bit 15 (SYSINT 0x02) */
+#define AW_PID_2049_OVP2I_START_BIT		(15)
+#define AW_PID_2049_OVP2I_BITS_LEN		(1)
+#define AW_PID_2049_OVP2I_MASK			\
+	(~(((1<<AW_PID_2049_OVP2I_BITS_LEN)-1) << AW_PID_2049_OVP2I_START_BIT))
+
+#define AW_PID_2049_OVP2I_DEFAULT_VALUE	(0)
+#define AW_PID_2049_OVP2I_DEFAULT		\
+	(AW_PID_2049_OVP2I_DEFAULT_VALUE << AW_PID_2049_OVP2I_START_BIT)
+
+/* UVLI bit 14 (SYSINT 0x02) */
+#define AW_PID_2049_UVLI_START_BIT		(14)
+#define AW_PID_2049_UVLI_BITS_LEN		(1)
+#define AW_PID_2049_UVLI_MASK			\
+	(~(((1<<AW_PID_2049_UVLI_BITS_LEN)-1) << AW_PID_2049_UVLI_START_BIT))
+
+#define AW_PID_2049_UVLI_DEFAULT_VALUE	(0)
+#define AW_PID_2049_UVLI_DEFAULT		\
+	(AW_PID_2049_UVLI_DEFAULT_VALUE << AW_PID_2049_UVLI_START_BIT)
+
+/* ADPI bit 13 (SYSINT 0x02) */
+#define AW_PID_2049_ADPI_START_BIT		(13)
+#define AW_PID_2049_ADPI_BITS_LEN		(1)
+#define AW_PID_2049_ADPI_MASK			\
+	(~(((1<<AW_PID_2049_ADPI_BITS_LEN)-1) << AW_PID_2049_ADPI_START_BIT))
+
+#define AW_PID_2049_ADPI_DEFAULT_VALUE	(0)
+#define AW_PID_2049_ADPI_DEFAULT		\
+	(AW_PID_2049_ADPI_DEFAULT_VALUE << AW_PID_2049_ADPI_START_BIT)
+
+/* DSPI bit 12 (SYSINT 0x02) */
+#define AW_PID_2049_DSPI_START_BIT		(12)
+#define AW_PID_2049_DSPI_BITS_LEN		(1)
+#define AW_PID_2049_DSPI_MASK			\
+	(~(((1<<AW_PID_2049_DSPI_BITS_LEN)-1) << AW_PID_2049_DSPI_START_BIT))
+
+#define AW_PID_2049_DSPI_DEFAULT_VALUE	(0)
+#define AW_PID_2049_DSPI_DEFAULT		\
+	(AW_PID_2049_DSPI_DEFAULT_VALUE << AW_PID_2049_DSPI_START_BIT)
+
+/* BSTOCI bit 11 (SYSINT 0x02) */
+#define AW_PID_2049_BSTOCI_START_BIT	(11)
+#define AW_PID_2049_BSTOCI_BITS_LEN		(1)
+#define AW_PID_2049_BSTOCI_MASK			\
+	(~(((1<<AW_PID_2049_BSTOCI_BITS_LEN)-1) << AW_PID_2049_BSTOCI_START_BIT))
+
+#define AW_PID_2049_BSTOCI_DEFAULT_VALUE	(0)
+#define AW_PID_2049_BSTOCI_DEFAULT		\
+	(AW_PID_2049_BSTOCI_DEFAULT_VALUE << AW_PID_2049_BSTOCI_START_BIT)
+
+/* OVPI bit 10 (SYSINT 0x02) */
+#define AW_PID_2049_OVPI_START_BIT		(10)
+#define AW_PID_2049_OVPI_BITS_LEN		(1)
+#define AW_PID_2049_OVPI_MASK			\
+	(~(((1<<AW_PID_2049_OVPI_BITS_LEN)-1) << AW_PID_2049_OVPI_START_BIT))
+
+#define AW_PID_2049_OVPI_DEFAULT_VALUE	(0)
+#define AW_PID_2049_OVPI_DEFAULT		\
+	(AW_PID_2049_OVPI_DEFAULT_VALUE << AW_PID_2049_OVPI_START_BIT)
+
+/* BSTI bit 9 (SYSINT 0x02) */
+#define AW_PID_2049_BSTI_START_BIT		(9)
+#define AW_PID_2049_BSTI_BITS_LEN		(1)
+#define AW_PID_2049_BSTI_MASK			\
+	(~(((1<<AW_PID_2049_BSTI_BITS_LEN)-1) << AW_PID_2049_BSTI_START_BIT))
+
+#define AW_PID_2049_BSTI_DEFAULT_VALUE	(0)
+#define AW_PID_2049_BSTI_DEFAULT		\
+	(AW_PID_2049_BSTI_DEFAULT_VALUE << AW_PID_2049_BSTI_START_BIT)
+
+/* SWI bit 8 (SYSINT 0x02) */
+#define AW_PID_2049_SWI_START_BIT		(8)
+#define AW_PID_2049_SWI_BITS_LEN		(1)
+#define AW_PID_2049_SWI_MASK			\
+	(~(((1<<AW_PID_2049_SWI_BITS_LEN)-1) << AW_PID_2049_SWI_START_BIT))
+
+#define AW_PID_2049_SWI_DEFAULT_VALUE	(0)
+#define AW_PID_2049_SWI_DEFAULT			\
+	(AW_PID_2049_SWI_DEFAULT_VALUE << AW_PID_2049_SWI_START_BIT)
+
+/* CLIPI bit 7 (SYSINT 0x02) */
+#define AW_PID_2049_CLIPI_START_BIT		(7)
+#define AW_PID_2049_CLIPI_BITS_LEN		(1)
+#define AW_PID_2049_CLIPI_MASK			\
+	(~(((1<<AW_PID_2049_CLIPI_BITS_LEN)-1) << AW_PID_2049_CLIPI_START_BIT))
+
+#define AW_PID_2049_CLIPI_DEFAULT_VALUE	(0)
+#define AW_PID_2049_CLIPI_DEFAULT		\
+	(AW_PID_2049_CLIPI_DEFAULT_VALUE << AW_PID_2049_CLIPI_START_BIT)
+
+/* WDI bit 6 (SYSINT 0x02) */
+#define AW_PID_2049_WDI_START_BIT		(6)
+#define AW_PID_2049_WDI_BITS_LEN		(1)
+#define AW_PID_2049_WDI_MASK			\
+	(~(((1<<AW_PID_2049_WDI_BITS_LEN)-1) << AW_PID_2049_WDI_START_BIT))
+
+#define AW_PID_2049_WDI_DEFAULT_VALUE	(0)
+#define AW_PID_2049_WDI_INT_VALUE	(1)
+#define AW_PID_2049_WDI_DEFAULT			\
+	(AW_PID_2049_WDI_DEFAULT_VALUE << AW_PID_2049_WDI_START_BIT)
+#define AW_PID_2049_WDI_INTERRUPT		\
+	(AW_PID_2049_WDI_INT_VALUE << AW_PID_2049_WDI_START_BIT)
+
+/* NOCLKI bit 5 (SYSINT 0x02) */
+#define AW_PID_2049_NOCLKI_START_BIT	(5)
+#define AW_PID_2049_NOCLKI_BITS_LEN		(1)
+#define AW_PID_2049_NOCLKI_MASK			\
+	(~(((1<<AW_PID_2049_NOCLKI_BITS_LEN)-1) << AW_PID_2049_NOCLKI_START_BIT))
+
+#define AW_PID_2049_NOCLKI_DEFAULT_VALUE	(0)
+#define AW_PID_2049_NOCLKI_INT_VALUE	(1)
+#define AW_PID_2049_NOCLKI_DEFAULT		\
+	(AW_PID_2049_NOCLKI_DEFAULT_VALUE << AW_PID_2049_NOCLKI_START_BIT)
+#define AW_PID_2049_NOCLKI_INTERRUPT		\
+	(AW_PID_2049_NOCLKI_INT_VALUE << AW_PID_2049_NOCLKI_START_BIT)
+
+/* CLKI bit 4 (SYSINT 0x02) */
+#define AW_PID_2049_CLKI_START_BIT		(4)
+#define AW_PID_2049_CLKI_BITS_LEN		(1)
+#define AW_PID_2049_CLKI_MASK			\
+	(~(((1<<AW_PID_2049_CLKI_BITS_LEN)-1) << AW_PID_2049_CLKI_START_BIT))
+
+#define AW_PID_2049_CLKI_DEFAULT_VALUE	(0)
+#define AW_PID_2049_CLKI_INT_VALUE	(1)
+#define AW_PID_2049_CLKI_DEFAULT		\
+	(AW_PID_2049_CLKI_DEFAULT_VALUE << AW_PID_2049_CLKI_START_BIT)
+#define AW_PID_2049_CLKI_INTERRUPT		\
+	(AW_PID_2049_CLKI_INT_VALUE << AW_PID_2049_CLKI_START_BIT)
+
+/* OCDI bit 3 (SYSINT 0x02) */
+#define AW_PID_2049_OCDI_START_BIT		(3)
+#define AW_PID_2049_OCDI_BITS_LEN		(1)
+#define AW_PID_2049_OCDI_MASK			\
+	(~(((1<<AW_PID_2049_OCDI_BITS_LEN)-1) << AW_PID_2049_OCDI_START_BIT))
+
+#define AW_PID_2049_OCDI_DEFAULT_VALUE	(0)
+#define AW_PID_2049_OCDI_DEFAULT		\
+	(AW_PID_2049_OCDI_DEFAULT_VALUE << AW_PID_2049_OCDI_START_BIT)
+
+/* CLIP_PREI bit 2 (SYSINT 0x02) */
+#define AW_PID_2049_CLIP_PREI_START_BIT	(2)
+#define AW_PID_2049_CLIP_PREI_BITS_LEN	(1)
+#define AW_PID_2049_CLIP_PREI_MASK		\
+	(~(((1<<AW_PID_2049_CLIP_PREI_BITS_LEN)-1) << AW_PID_2049_CLIP_PREI_START_BIT))
+
+#define AW_PID_2049_CLIP_PREI_DEFAULT_VALUE	(0)
+#define AW_PID_2049_CLIP_PREI_DEFAULT	\
+	(AW_PID_2049_CLIP_PREI_DEFAULT_VALUE << AW_PID_2049_CLIP_PREI_START_BIT)
+
+/* OTHI bit 1 (SYSINT 0x02) */
+#define AW_PID_2049_OTHI_START_BIT		(1)
+#define AW_PID_2049_OTHI_BITS_LEN		(1)
+#define AW_PID_2049_OTHI_MASK			\
+	(~(((1<<AW_PID_2049_OTHI_BITS_LEN)-1) << AW_PID_2049_OTHI_START_BIT))
+
+#define AW_PID_2049_OTHI_DEFAULT_VALUE	(0)
+#define AW_PID_2049_OTHI_DEFAULT		\
+	(AW_PID_2049_OTHI_DEFAULT_VALUE << AW_PID_2049_OTHI_START_BIT)
+
+/* PLLI bit 0 (SYSINT 0x02) */
+#define AW_PID_2049_PLLI_START_BIT		(0)
+#define AW_PID_2049_PLLI_BITS_LEN		(1)
+#define AW_PID_2049_PLLI_MASK			\
+	(~(((1<<AW_PID_2049_PLLI_BITS_LEN)-1) << AW_PID_2049_PLLI_START_BIT))
+
+#define AW_PID_2049_PLLI_DEFAULT_VALUE	(0)
+#define AW_PID_2049_PLLI_INT_VALUE	(1)
+#define AW_PID_2049_PLLI_DEFAULT		\
+	(AW_PID_2049_PLLI_DEFAULT_VALUE << AW_PID_2049_PLLI_START_BIT)
+#define AW_PID_2049_PLLI_INTERRUPT		\
+	(AW_PID_2049_PLLI_INT_VALUE << AW_PID_2049_PLLI_START_BIT)
+
+/* default value of SYSINT (0x02) */
+/* #define AW_PID_2049_SYSINT_DEFAULT		(0x0000) */
+
+#define AW_PID_2049_BIT_SYSINT_CHECK \
+		(AW_PID_2049_WDI_INTERRUPT | \
+		AW_PID_2049_CLKI_INTERRUPT | \
+		AW_PID_2049_NOCLKI_INTERRUPT | \
+		AW_PID_2049_PLLI_INTERRUPT)
+
+/* SYSINTM (0x03) detail */
+/* OVP2M bit 15 (SYSINTM 0x03) */
+#define AW_PID_2049_OVP2M_START_BIT		(15)
+#define AW_PID_2049_OVP2M_BITS_LEN		(1)
+#define AW_PID_2049_OVP2M_MASK			\
+	(~(((1<<AW_PID_2049_OVP2M_BITS_LEN)-1) << AW_PID_2049_OVP2M_START_BIT))
+
+#define AW_PID_2049_OVP2M_DEFAULT_VALUE	(1)
+#define AW_PID_2049_OVP2M_DEFAULT		\
+	(AW_PID_2049_OVP2M_DEFAULT_VALUE << AW_PID_2049_OVP2M_START_BIT)
+
+/* UVLM bit 14 (SYSINTM 0x03) */
+#define AW_PID_2049_UVLM_START_BIT		(14)
+#define AW_PID_2049_UVLM_BITS_LEN		(1)
+#define AW_PID_2049_UVLM_MASK			\
+	(~(((1<<AW_PID_2049_UVLM_BITS_LEN)-1) << AW_PID_2049_UVLM_START_BIT))
+
+#define AW_PID_2049_UVLM_DEFAULT_VALUE	(1)
+#define AW_PID_2049_UVLM_DEFAULT		\
+	(AW_PID_2049_UVLM_DEFAULT_VALUE << AW_PID_2049_UVLM_START_BIT)
+
+/* ADPM bit 13 (SYSINTM 0x03) */
+#define AW_PID_2049_ADPM_START_BIT		(13)
+#define AW_PID_2049_ADPM_BITS_LEN		(1)
+#define AW_PID_2049_ADPM_MASK			\
+	(~(((1<<AW_PID_2049_ADPM_BITS_LEN)-1) << AW_PID_2049_ADPM_START_BIT))
+
+#define AW_PID_2049_ADPM_DEFAULT_VALUE	(1)
+#define AW_PID_2049_ADPM_DEFAULT		\
+	(AW_PID_2049_ADPM_DEFAULT_VALUE << AW_PID_2049_ADPM_START_BIT)
+
+/* DSPM bit 12 (SYSINTM 0x03) */
+#define AW_PID_2049_DSPM_START_BIT		(12)
+#define AW_PID_2049_DSPM_BITS_LEN		(1)
+#define AW_PID_2049_DSPM_MASK			\
+	(~(((1<<AW_PID_2049_DSPM_BITS_LEN)-1) << AW_PID_2049_DSPM_START_BIT))
+
+#define AW_PID_2049_DSPM_DEFAULT_VALUE	(1)
+#define AW_PID_2049_DSPM_DEFAULT		\
+	(AW_PID_2049_DSPM_DEFAULT_VALUE << AW_PID_2049_DSPM_START_BIT)
+
+/* BSTOCM bit 11 (SYSINTM 0x03) */
+#define AW_PID_2049_BSTOCM_START_BIT	(11)
+#define AW_PID_2049_BSTOCM_BITS_LEN		(1)
+#define AW_PID_2049_BSTOCM_MASK			\
+	(~(((1<<AW_PID_2049_BSTOCM_BITS_LEN)-1) << AW_PID_2049_BSTOCM_START_BIT))
+
+#define AW_PID_2049_BSTOCM_DEFAULT_VALUE	(1)
+#define AW_PID_2049_BSTOCM_DEFAULT		\
+	(AW_PID_2049_BSTOCM_DEFAULT_VALUE << AW_PID_2049_BSTOCM_START_BIT)
+
+/* OVPM bit 10 (SYSINTM 0x03) */
+#define AW_PID_2049_OVPM_START_BIT		(10)
+#define AW_PID_2049_OVPM_BITS_LEN		(1)
+#define AW_PID_2049_OVPM_MASK			\
+	(~(((1<<AW_PID_2049_OVPM_BITS_LEN)-1) << AW_PID_2049_OVPM_START_BIT))
+
+#define AW_PID_2049_OVPM_DEFAULT_VALUE	(1)
+#define AW_PID_2049_OVPM_DEFAULT		\
+	(AW_PID_2049_OVPM_DEFAULT_VALUE << AW_PID_2049_OVPM_START_BIT)
+
+/* BSTM bit 9 (SYSINTM 0x03) */
+#define AW_PID_2049_BSTM_START_BIT		(9)
+#define AW_PID_2049_BSTM_BITS_LEN		(1)
+#define AW_PID_2049_BSTM_MASK			\
+	(~(((1<<AW_PID_2049_BSTM_BITS_LEN)-1) << AW_PID_2049_BSTM_START_BIT))
+
+#define AW_PID_2049_BSTM_DEFAULT_VALUE	(1)
+#define AW_PID_2049_BSTM_DEFAULT		\
+	(AW_PID_2049_BSTM_DEFAULT_VALUE << AW_PID_2049_BSTM_START_BIT)
+
+/* SWM bit 8 (SYSINTM 0x03) */
+#define AW_PID_2049_SWM_START_BIT		(8)
+#define AW_PID_2049_SWM_BITS_LEN		(1)
+#define AW_PID_2049_SWM_MASK			\
+	(~(((1<<AW_PID_2049_SWM_BITS_LEN)-1) << AW_PID_2049_SWM_START_BIT))
+
+#define AW_PID_2049_SWM_DEFAULT_VALUE	(1)
+#define AW_PID_2049_SWM_DEFAULT			\
+	(AW_PID_2049_SWM_DEFAULT_VALUE << AW_PID_2049_SWM_START_BIT)
+
+/* CLIPM bit 7 (SYSINTM 0x03) */
+#define AW_PID_2049_CLIPM_START_BIT		(7)
+#define AW_PID_2049_CLIPM_BITS_LEN		(1)
+#define AW_PID_2049_CLIPM_MASK			\
+	(~(((1<<AW_PID_2049_CLIPM_BITS_LEN)-1) << AW_PID_2049_CLIPM_START_BIT))
+
+#define AW_PID_2049_CLIPM_DEFAULT_VALUE	(1)
+#define AW_PID_2049_CLIPM_DEFAULT		\
+	(AW_PID_2049_CLIPM_DEFAULT_VALUE << AW_PID_2049_CLIPM_START_BIT)
+
+/* WDM bit 6 (SYSINTM 0x03) */
+#define AW_PID_2049_WDM_START_BIT		(6)
+#define AW_PID_2049_WDM_BITS_LEN		(1)
+#define AW_PID_2049_WDM_MASK			\
+	(~(((1<<AW_PID_2049_WDM_BITS_LEN)-1) << AW_PID_2049_WDM_START_BIT))
+
+#define AW_PID_2049_WDM_DEFAULT_VALUE	(1)
+#define AW_PID_2049_WDM_DEFAULT			\
+	(AW_PID_2049_WDM_DEFAULT_VALUE << AW_PID_2049_WDM_START_BIT)
+
+/* NOCLKM bit 5 (SYSINTM 0x03) */
+#define AW_PID_2049_NOCLKM_START_BIT	(5)
+#define AW_PID_2049_NOCLKM_BITS_LEN		(1)
+#define AW_PID_2049_NOCLKM_MASK			\
+	(~(((1<<AW_PID_2049_NOCLKM_BITS_LEN)-1) << AW_PID_2049_NOCLKM_START_BIT))
+
+#define AW_PID_2049_NOCLKM_DEFAULT_VALUE	(1)
+#define AW_PID_2049_NOCLKM_DEFAULT		\
+	(AW_PID_2049_NOCLKM_DEFAULT_VALUE << AW_PID_2049_NOCLKM_START_BIT)
+
+/* CLKM bit 4 (SYSINTM 0x03) */
+#define AW_PID_2049_CLKM_START_BIT		(4)
+#define AW_PID_2049_CLKM_BITS_LEN		(1)
+#define AW_PID_2049_CLKM_MASK			\
+	(~(((1<<AW_PID_2049_CLKM_BITS_LEN)-1) << AW_PID_2049_CLKM_START_BIT))
+
+#define AW_PID_2049_CLKM_DEFAULT_VALUE	(1)
+#define AW_PID_2049_CLKM_DEFAULT		\
+	(AW_PID_2049_CLKM_DEFAULT_VALUE << AW_PID_2049_CLKM_START_BIT)
+
+/* OCDM bit 3 (SYSINTM 0x03) */
+#define AW_PID_2049_OCDM_START_BIT		(3)
+#define AW_PID_2049_OCDM_BITS_LEN		(1)
+#define AW_PID_2049_OCDM_MASK			\
+	(~(((1<<AW_PID_2049_OCDM_BITS_LEN)-1) << AW_PID_2049_OCDM_START_BIT))
+
+#define AW_PID_2049_OCDM_DEFAULT_VALUE	(1)
+#define AW_PID_2049_OCDM_DEFAULT		\
+	(AW_PID_2049_OCDM_DEFAULT_VALUE << AW_PID_2049_OCDM_START_BIT)
+
+/* CLIP_PREM bit 2 (SYSINTM 0x03) */
+#define AW_PID_2049_CLIP_PREM_START_BIT	(2)
+#define AW_PID_2049_CLIP_PREM_BITS_LEN	(1)
+#define AW_PID_2049_CLIP_PREM_MASK		\
+	(~(((1<<AW_PID_2049_CLIP_PREM_BITS_LEN)-1) << AW_PID_2049_CLIP_PREM_START_BIT))
+
+#define AW_PID_2049_CLIP_PREM_DEFAULT_VALUE	(1)
+#define AW_PID_2049_CLIP_PREM_DEFAULT	\
+	(AW_PID_2049_CLIP_PREM_DEFAULT_VALUE << AW_PID_2049_CLIP_PREM_START_BIT)
+
+/* OTHM bit 1 (SYSINTM 0x03) */
+#define AW_PID_2049_OTHM_START_BIT		(1)
+#define AW_PID_2049_OTHM_BITS_LEN		(1)
+#define AW_PID_2049_OTHM_MASK			\
+	(~(((1<<AW_PID_2049_OTHM_BITS_LEN)-1) << AW_PID_2049_OTHM_START_BIT))
+
+#define AW_PID_2049_OTHM_DEFAULT_VALUE	(1)
+#define AW_PID_2049_OTHM_DEFAULT		\
+	(AW_PID_2049_OTHM_DEFAULT_VALUE << AW_PID_2049_OTHM_START_BIT)
+
+/* PLLM bit 0 (SYSINTM 0x03) */
+#define AW_PID_2049_PLLM_START_BIT		(0)
+#define AW_PID_2049_PLLM_BITS_LEN		(1)
+#define AW_PID_2049_PLLM_MASK			\
+	(~(((1<<AW_PID_2049_PLLM_BITS_LEN)-1) << AW_PID_2049_PLLM_START_BIT))
+
+#define AW_PID_2049_PLLM_DEFAULT_VALUE	(1)
+#define AW_PID_2049_PLLM_DEFAULT		\
+	(AW_PID_2049_PLLM_DEFAULT_VALUE << AW_PID_2049_PLLM_START_BIT)
+
+/* default value of SYSINTM (0x03) */
+#define AW_PID_2049_SYSINTM_DEFAULT		(0xFFFF)
+
+/* SYSCTRL (0x04) detail */
+/* SPK_GAIN bit 14:12 (SYSCTRL 0x04) */
+#define AW_PID_2049_SPK_GAIN_START_BIT	(12)
+#define AW_PID_2049_SPK_GAIN_BITS_LEN	(3)
+#define AW_PID_2049_SPK_GAIN_MASK		\
+	(~(((1<<AW_PID_2049_SPK_GAIN_BITS_LEN)-1) << AW_PID_2049_SPK_GAIN_START_BIT))
+
+#define AW_PID_2049_SPK_GAIN_4_AV		(0)
+#define AW_PID_2049_SPK_GAIN_4_AV_VALUE	\
+	(AW_PID_2049_SPK_GAIN_4_AV << AW_PID_2049_SPK_GAIN_START_BIT)
+
+#define AW_PID_2049_SPK_GAIN_4P67_AV	(1)
+#define AW_PID_2049_SPK_GAIN_4P67_AV_VALUE	\
+	(AW_PID_2049_SPK_GAIN_4P67_AV << AW_PID_2049_SPK_GAIN_START_BIT)
+
+#define AW_PID_2049_SPK_GAIN_6_AV		(2)
+#define AW_PID_2049_SPK_GAIN_6_AV_VALUE	\
+	(AW_PID_2049_SPK_GAIN_6_AV << AW_PID_2049_SPK_GAIN_START_BIT)
+
+#define AW_PID_2049_SPK_GAIN_7_AV		(3)
+#define AW_PID_2049_SPK_GAIN_7_AV_VALUE	\
+	(AW_PID_2049_SPK_GAIN_7_AV << AW_PID_2049_SPK_GAIN_START_BIT)
+
+#define AW_PID_2049_SPK_GAIN_12_AV		(4)
+#define AW_PID_2049_SPK_GAIN_12_AV_VALUE	\
+	(AW_PID_2049_SPK_GAIN_12_AV << AW_PID_2049_SPK_GAIN_START_BIT)
+
+#define AW_PID_2049_SPK_GAIN_14_AV		(5)
+#define AW_PID_2049_SPK_GAIN_14_AV_VALUE	\
+	(AW_PID_2049_SPK_GAIN_14_AV << AW_PID_2049_SPK_GAIN_START_BIT)
+
+#define AW_PID_2049_SPK_GAIN_DEFAULT_VALUE	(0x5)
+#define AW_PID_2049_SPK_GAIN_DEFAULT	\
+	(AW_PID_2049_SPK_GAIN_DEFAULT_VALUE << AW_PID_2049_SPK_GAIN_START_BIT)
+
+/* RMSE bit 11 (SYSCTRL 0x04) */
+#define AW_PID_2049_RMSE_START_BIT		(11)
+#define AW_PID_2049_RMSE_BITS_LEN		(1)
+#define AW_PID_2049_RMSE_MASK			\
+	(~(((1<<AW_PID_2049_RMSE_BITS_LEN)-1) << AW_PID_2049_RMSE_START_BIT))
+
+#define AW_PID_2049_RMSE_PEAK_AGC		(0)
+#define AW_PID_2049_RMSE_PEAK_AGC_VALUE	\
+	(AW_PID_2049_RMSE_PEAK_AGC << AW_PID_2049_RMSE_START_BIT)
+
+#define AW_PID_2049_RMSE_RMS_AGC		(1)
+#define AW_PID_2049_RMSE_RMS_AGC_VALUE	\
+	(AW_PID_2049_RMSE_RMS_AGC << AW_PID_2049_RMSE_START_BIT)
+
+#define AW_PID_2049_RMSE_DEFAULT_VALUE	(0)
+#define AW_PID_2049_RMSE_DEFAULT		\
+	(AW_PID_2049_RMSE_DEFAULT_VALUE << AW_PID_2049_RMSE_START_BIT)
+
+/* HAGCE bit 10 (SYSCTRL 0x04) */
+#define AW_PID_2049_HAGCE_START_BIT		(10)
+#define AW_PID_2049_HAGCE_BITS_LEN		(1)
+#define AW_PID_2049_HAGCE_MASK			\
+	(~(((1<<AW_PID_2049_HAGCE_BITS_LEN)-1) << AW_PID_2049_HAGCE_START_BIT))
+
+#define AW_PID_2049_HAGCE_DISABLE		(0)
+#define AW_PID_2049_HAGCE_DISABLE_VALUE	\
+	(AW_PID_2049_HAGCE_DISABLE << AW_PID_2049_HAGCE_START_BIT)
+
+#define AW_PID_2049_HAGCE_ENABLE		(1)
+#define AW_PID_2049_HAGCE_ENABLE_VALUE	\
+	(AW_PID_2049_HAGCE_ENABLE << AW_PID_2049_HAGCE_START_BIT)
+
+#define AW_PID_2049_HAGCE_DEFAULT_VALUE	(0)
+#define AW_PID_2049_HAGCE_DEFAULT		\
+	(AW_PID_2049_HAGCE_DEFAULT_VALUE << AW_PID_2049_HAGCE_START_BIT)
+
+/* HDCCE bit 9 (SYSCTRL 0x04) */
+#define AW_PID_2049_HDCCE_START_BIT		(9)
+#define AW_PID_2049_HDCCE_BITS_LEN		(1)
+#define AW_PID_2049_HDCCE_MASK			\
+	(~(((1<<AW_PID_2049_HDCCE_BITS_LEN)-1) << AW_PID_2049_HDCCE_START_BIT))
+
+#define AW_PID_2049_HDCCE_DISABLE		(0)
+#define AW_PID_2049_HDCCE_DISABLE_VALUE	\
+	(AW_PID_2049_HDCCE_DISABLE << AW_PID_2049_HDCCE_START_BIT)
+
+#define AW_PID_2049_HDCCE_ENABLE		(1)
+#define AW_PID_2049_HDCCE_ENABLE_VALUE	\
+	(AW_PID_2049_HDCCE_ENABLE << AW_PID_2049_HDCCE_START_BIT)
+
+#define AW_PID_2049_HDCCE_DEFAULT_VALUE	(1)
+#define AW_PID_2049_HDCCE_DEFAULT		\
+	(AW_PID_2049_HDCCE_DEFAULT_VALUE << AW_PID_2049_HDCCE_START_BIT)
+
+/* HMUTE bit 8 (SYSCTRL 0x04) */
+#define AW_PID_2049_HMUTE_START_BIT		(8)
+#define AW_PID_2049_HMUTE_BITS_LEN		(1)
+#define AW_PID_2049_HMUTE_MASK			\
+	(~(((1<<AW_PID_2049_HMUTE_BITS_LEN)-1) << AW_PID_2049_HMUTE_START_BIT))
+
+#define AW_PID_2049_HMUTE_DISABLE		(0)
+#define AW_PID_2049_HMUTE_DISABLE_VALUE	\
+	(AW_PID_2049_HMUTE_DISABLE << AW_PID_2049_HMUTE_START_BIT)
+
+#define AW_PID_2049_HMUTE_ENABLE		(1)
+#define AW_PID_2049_HMUTE_ENABLE_VALUE	\
+	(AW_PID_2049_HMUTE_ENABLE << AW_PID_2049_HMUTE_START_BIT)
+
+#define AW_PID_2049_HMUTE_DEFAULT_VALUE	(1)
+#define AW_PID_2049_HMUTE_DEFAULT		\
+	(AW_PID_2049_HMUTE_DEFAULT_VALUE << AW_PID_2049_HMUTE_START_BIT)
+
+/* RCV_MODE bit 7 (SYSCTRL 0x04) */
+#define AW_PID_2049_RCV_MODE_START_BIT	(7)
+#define AW_PID_2049_RCV_MODE_BITS_LEN	(1)
+#define AW_PID_2049_RCV_MODE_MASK		\
+	(~(((1<<AW_PID_2049_RCV_MODE_BITS_LEN)-1) << AW_PID_2049_RCV_MODE_START_BIT))
+
+#define AW_PID_2049_RCV_MODE_SPEAKER	(0)
+#define AW_PID_2049_RCV_MODE_SPEAKER_VALUE	\
+	(AW_PID_2049_RCV_MODE_SPEAKER << AW_PID_2049_RCV_MODE_START_BIT)
+
+#define AW_PID_2049_RCV_MODE_RECEIVER	(1)
+#define AW_PID_2049_RCV_MODE_RECEIVER_VALUE	\
+	(AW_PID_2049_RCV_MODE_RECEIVER << AW_PID_2049_RCV_MODE_START_BIT)
+
+#define AW_PID_2049_RCV_MODE_DEFAULT_VALUE	(0)
+#define AW_PID_2049_RCV_MODE_DEFAULT	\
+	(AW_PID_2049_RCV_MODE_DEFAULT_VALUE << AW_PID_2049_RCV_MODE_START_BIT)
+
+/* I2SEN bit 6 (SYSCTRL 0x04) */
+#define AW_PID_2049_I2SEN_START_BIT		(6)
+#define AW_PID_2049_I2SEN_BITS_LEN		(1)
+#define AW_PID_2049_I2SEN_MASK			\
+	(~(((1<<AW_PID_2049_I2SEN_BITS_LEN)-1) << AW_PID_2049_I2SEN_START_BIT))
+
+#define AW_PID_2049_I2SEN_DISABLE		(0)
+#define AW_PID_2049_I2SEN_DISABLE_VALUE	\
+	(AW_PID_2049_I2SEN_DISABLE << AW_PID_2049_I2SEN_START_BIT)
+
+#define AW_PID_2049_I2SEN_ENABLE		(1)
+#define AW_PID_2049_I2SEN_ENABLE_VALUE	\
+	(AW_PID_2049_I2SEN_ENABLE << AW_PID_2049_I2SEN_START_BIT)
+
+#define AW_PID_2049_I2SEN_DEFAULT_VALUE	(0)
+#define AW_PID_2049_I2SEN_DEFAULT		\
+	(AW_PID_2049_I2SEN_DEFAULT_VALUE << AW_PID_2049_I2SEN_START_BIT)
+
+/* WSINV bit 5 (SYSCTRL 0x04) */
+#define AW_PID_2049_WSINV_START_BIT		(5)
+#define AW_PID_2049_WSINV_BITS_LEN		(1)
+#define AW_PID_2049_WSINV_MASK			\
+	(~(((1<<AW_PID_2049_WSINV_BITS_LEN)-1) << AW_PID_2049_WSINV_START_BIT))
+
+#define AW_PID_2049_WSINV_NOT_SWITCH	(0)
+#define AW_PID_2049_WSINV_NOT_SWITCH_VALUE	\
+	(AW_PID_2049_WSINV_NOT_SWITCH << AW_PID_2049_WSINV_START_BIT)
+
+#define AW_PID_2049_WSINV_SWITCH		(1)
+#define AW_PID_2049_WSINV_SWITCH_VALUE	\
+	(AW_PID_2049_WSINV_SWITCH << AW_PID_2049_WSINV_START_BIT)
+
+#define AW_PID_2049_WSINV_DEFAULT_VALUE	(0)
+#define AW_PID_2049_WSINV_DEFAULT		\
+	(AW_PID_2049_WSINV_DEFAULT_VALUE << AW_PID_2049_WSINV_START_BIT)
+
+/* BCKINV bit 4 (SYSCTRL 0x04) */
+#define AW_PID_2049_BCKINV_START_BIT	(4)
+#define AW_PID_2049_BCKINV_BITS_LEN		(1)
+#define AW_PID_2049_BCKINV_MASK			\
+	(~(((1<<AW_PID_2049_BCKINV_BITS_LEN)-1) << AW_PID_2049_BCKINV_START_BIT))
+
+#define AW_PID_2049_BCKINV_NOT_INVERT	(0)
+#define AW_PID_2049_BCKINV_NOT_INVERT_VALUE	\
+	(AW_PID_2049_BCKINV_NOT_INVERT << AW_PID_2049_BCKINV_START_BIT)
+
+#define AW_PID_2049_BCKINV_INVERTED		(1)
+#define AW_PID_2049_BCKINV_INVERTED_VALUE	\
+	(AW_PID_2049_BCKINV_INVERTED << AW_PID_2049_BCKINV_START_BIT)
+
+#define AW_PID_2049_BCKINV_DEFAULT_VALUE	(0)
+#define AW_PID_2049_BCKINV_DEFAULT		\
+	(AW_PID_2049_BCKINV_DEFAULT_VALUE << AW_PID_2049_BCKINV_START_BIT)
+
+/* IPLL bit 3 (SYSCTRL 0x04) */
+#define AW_PID_2049_IPLL_START_BIT		(3)
+#define AW_PID_2049_IPLL_BITS_LEN		(1)
+#define AW_PID_2049_IPLL_MASK			\
+	(~(((1<<AW_PID_2049_IPLL_BITS_LEN)-1) << AW_PID_2049_IPLL_START_BIT))
+
+#define AW_PID_2049_IPLL_BCK			(0)
+#define AW_PID_2049_IPLL_BCK_VALUE		\
+	(AW_PID_2049_IPLL_BCK << AW_PID_2049_IPLL_START_BIT)
+
+#define AW_PID_2049_IPLL_WCK			(1)
+#define AW_PID_2049_IPLL_WCK_VALUE		\
+	(AW_PID_2049_IPLL_WCK << AW_PID_2049_IPLL_START_BIT)
+
+#define AW_PID_2049_IPLL_DEFAULT_VALUE	(0)
+#define AW_PID_2049_IPLL_DEFAULT		\
+	(AW_PID_2049_IPLL_DEFAULT_VALUE << AW_PID_2049_IPLL_START_BIT)
+
+/* DSPBY bit 2 (SYSCTRL 0x04) */
+#define AW_PID_2049_DSPBY_START_BIT		(2)
+#define AW_PID_2049_DSPBY_BITS_LEN		(1)
+#define AW_PID_2049_DSPBY_MASK			\
+	(~(((1<<AW_PID_2049_DSPBY_BITS_LEN)-1) << AW_PID_2049_DSPBY_START_BIT))
+
+#define AW_PID_2049_DSPBY_WORKING		(0)
+#define AW_PID_2049_DSPBY_WORKING_VALUE	\
+	(AW_PID_2049_DSPBY_WORKING << AW_PID_2049_DSPBY_START_BIT)
+
+#define AW_PID_2049_DSPBY_BYPASS		(1)
+#define AW_PID_2049_DSPBY_BYPASS_VALUE	\
+	(AW_PID_2049_DSPBY_BYPASS << AW_PID_2049_DSPBY_START_BIT)
+
+#define AW_PID_2049_DSPBY_DEFAULT_VALUE	(1)
+#define AW_PID_2049_DSPBY_DEFAULT		\
+	(AW_PID_2049_DSPBY_DEFAULT_VALUE << AW_PID_2049_DSPBY_START_BIT)
+
+/* AMPPD bit 1 (SYSCTRL 0x04) */
+#define AW_PID_2049_AMPPD_START_BIT		(1)
+#define AW_PID_2049_AMPPD_BITS_LEN		(1)
+#define AW_PID_2049_AMPPD_MASK			\
+	(~(((1<<AW_PID_2049_AMPPD_BITS_LEN)-1) << AW_PID_2049_AMPPD_START_BIT))
+
+#define AW_PID_2049_AMPPD_WORKING		(0)
+#define AW_PID_2049_AMPPD_WORKING_VALUE	\
+	(AW_PID_2049_AMPPD_WORKING << AW_PID_2049_AMPPD_START_BIT)
+
+#define AW_PID_2049_AMPPD_POWER_DOWN	(1)
+#define AW_PID_2049_AMPPD_POWER_DOWN_VALUE	\
+	(AW_PID_2049_AMPPD_POWER_DOWN << AW_PID_2049_AMPPD_START_BIT)
+
+#define AW_PID_2049_AMPPD_DEFAULT_VALUE	(1)
+#define AW_PID_2049_AMPPD_DEFAULT		\
+	(AW_PID_2049_AMPPD_DEFAULT_VALUE << AW_PID_2049_AMPPD_START_BIT)
+
+/* PWDN bit 0 (SYSCTRL 0x04) */
+#define AW_PID_2049_PWDN_START_BIT		(0)
+#define AW_PID_2049_PWDN_BITS_LEN		(1)
+#define AW_PID_2049_PWDN_MASK			\
+	(~(((1<<AW_PID_2049_PWDN_BITS_LEN)-1) << AW_PID_2049_PWDN_START_BIT))
+
+#define AW_PID_2049_PWDN_WORKING		(0)
+#define AW_PID_2049_PWDN_WORKING_VALUE	\
+	(AW_PID_2049_PWDN_WORKING << AW_PID_2049_PWDN_START_BIT)
+
+#define AW_PID_2049_PWDN_POWER_DOWN		(1)
+#define AW_PID_2049_PWDN_POWER_DOWN_VALUE	\
+	(AW_PID_2049_PWDN_POWER_DOWN << AW_PID_2049_PWDN_START_BIT)
+
+#define AW_PID_2049_PWDN_DEFAULT_VALUE	(1)
+#define AW_PID_2049_PWDN_DEFAULT		\
+	(AW_PID_2049_PWDN_DEFAULT_VALUE << AW_PID_2049_PWDN_START_BIT)
+
+/* default value of SYSCTRL (0x04) */
+/* #define AW_PID_2049_SYSCTRL_DEFAULT		(0x5307) */
+
+/* SYSCTRL2 (0x05) detail */
+/* VOL bit 15:6 (SYSCTRL2 0x05) */
+#define AW_PID_2049_MUTE_VOL		(90 * 8)
+#define AW_PID_2049_VOLUME_STEP_DB		(6 * 8)
+
+#define AW_PID_2049_VOL_6DB_START				(6)
+#define AW_PID_2049_VOL_START_BIT		(6)
+#define AW_PID_2049_VOL_BITS_LEN		(10)
+#define AW_PID_2049_VOL_MASK			\
+	(~(((1<<AW_PID_2049_VOL_BITS_LEN)-1) << AW_PID_2049_VOL_START_BIT))
+
+#define AW_PID_2049_VOL_DEFAULT_VALUE	(0)
+#define AW_PID_2049_VOL_DEFAULT			\
+	(AW_PID_2049_VOL_DEFAULT_VALUE << AW_PID_2049_VOL_START_BIT)
+
+/* INTMODE bit 5 (SYSCTRL2 0x05) */
+#define AW_PID_2049_INTMODE_START_BIT	(5)
+#define AW_PID_2049_INTMODE_BITS_LEN	(1)
+#define AW_PID_2049_INTMODE_MASK		\
+	(~(((1<<AW_PID_2049_INTMODE_BITS_LEN)-1) << AW_PID_2049_INTMODE_START_BIT))
+
+#define AW_PID_2049_INTMODE_OPENMINUS_DRAIN	(0)
+#define AW_PID_2049_INTMODE_OPENMINUS_DRAIN_VALUE	\
+	(AW_PID_2049_INTMODE_OPENMINUS_DRAIN << AW_PID_2049_INTMODE_START_BIT)
+
+#define AW_PID_2049_INTMODE_PUSHPULL	(1)
+#define AW_PID_2049_INTMODE_PUSHPULL_VALUE	\
+	(AW_PID_2049_INTMODE_PUSHPULL << AW_PID_2049_INTMODE_START_BIT)
+
+#define AW_PID_2049_INTMODE_DEFAULT_VALUE	(0)
+#define AW_PID_2049_INTMODE_DEFAULT		\
+	(AW_PID_2049_INTMODE_DEFAULT_VALUE << AW_PID_2049_INTMODE_START_BIT)
+
+/* INTN bit 4 (SYSCTRL2 0x05) */
+#define AW_PID_2049_INTN_START_BIT		(4)
+#define AW_PID_2049_INTN_BITS_LEN		(1)
+#define AW_PID_2049_INTN_MASK			\
+	(~(((1<<AW_PID_2049_INTN_BITS_LEN)-1) << AW_PID_2049_INTN_START_BIT))
+
+#define AW_PID_2049_INTN_SYSINT			(0)
+#define AW_PID_2049_INTN_SYSINT_VALUE	\
+	(AW_PID_2049_INTN_SYSINT << AW_PID_2049_INTN_START_BIT)
+
+#define AW_PID_2049_INTN_SYSST			(1)
+#define AW_PID_2049_INTN_SYSST_VALUE	\
+	(AW_PID_2049_INTN_SYSST << AW_PID_2049_INTN_START_BIT)
+
+#define AW_PID_2049_INTN_DEFAULT_VALUE	(0)
+#define AW_PID_2049_INTN_DEFAULT		\
+	(AW_PID_2049_INTN_DEFAULT_VALUE << AW_PID_2049_INTN_START_BIT)
+
+/* BST_IPEAK bit 3:0 (SYSCTRL2 0x05) */
+#define AW_PID_2049_BST_IPEAK_START_BIT	(0)
+#define AW_PID_2049_BST_IPEAK_BITS_LEN	(4)
+#define AW_PID_2049_BST_IPEAK_MASK		\
+	(~(((1<<AW_PID_2049_BST_IPEAK_BITS_LEN)-1) << AW_PID_2049_BST_IPEAK_START_BIT))
+
+#define AW_PID_2049_BST_IPEAK_1P50A		(0)
+#define AW_PID_2049_BST_IPEAK_1P50A_VALUE	\
+	(AW_PID_2049_BST_IPEAK_1P50A << AW_PID_2049_BST_IPEAK_START_BIT)
+
+#define AW_PID_2049_BST_IPEAK_1P75A		(1)
+#define AW_PID_2049_BST_IPEAK_1P75A_VALUE	\
+	(AW_PID_2049_BST_IPEAK_1P75A << AW_PID_2049_BST_IPEAK_START_BIT)
+
+#define AW_PID_2049_BST_IPEAK_2P00A		(2)
+#define AW_PID_2049_BST_IPEAK_2P00A_VALUE	\
+	(AW_PID_2049_BST_IPEAK_2P00A << AW_PID_2049_BST_IPEAK_START_BIT)
+
+#define AW_PID_2049_BST_IPEAK_2P25A		(3)
+#define AW_PID_2049_BST_IPEAK_2P25A_VALUE	\
+	(AW_PID_2049_BST_IPEAK_2P25A << AW_PID_2049_BST_IPEAK_START_BIT)
+
+#define AW_PID_2049_BST_IPEAK_2P50A		(4)
+#define AW_PID_2049_BST_IPEAK_2P50A_VALUE	\
+	(AW_PID_2049_BST_IPEAK_2P50A << AW_PID_2049_BST_IPEAK_START_BIT)
+
+#define AW_PID_2049_BST_IPEAK_2P75A		(5)
+#define AW_PID_2049_BST_IPEAK_2P75A_VALUE	\
+	(AW_PID_2049_BST_IPEAK_2P75A << AW_PID_2049_BST_IPEAK_START_BIT)
+
+#define AW_PID_2049_BST_IPEAK_3P00A		(6)
+#define AW_PID_2049_BST_IPEAK_3P00A_VALUE	\
+	(AW_PID_2049_BST_IPEAK_3P00A << AW_PID_2049_BST_IPEAK_START_BIT)
+
+#define AW_PID_2049_BST_IPEAK_3P25A		(7)
+#define AW_PID_2049_BST_IPEAK_3P25A_VALUE	\
+	(AW_PID_2049_BST_IPEAK_3P25A << AW_PID_2049_BST_IPEAK_START_BIT)
+
+#define AW_PID_2049_BST_IPEAK_3P50A		(8)
+#define AW_PID_2049_BST_IPEAK_3P50A_VALUE	\
+	(AW_PID_2049_BST_IPEAK_3P50A << AW_PID_2049_BST_IPEAK_START_BIT)
+
+#define AW_PID_2049_BST_IPEAK_3P75A		(9)
+#define AW_PID_2049_BST_IPEAK_3P75A_VALUE	\
+	(AW_PID_2049_BST_IPEAK_3P75A << AW_PID_2049_BST_IPEAK_START_BIT)
+
+#define AW_PID_2049_BST_IPEAK_4P00A		(10)
+#define AW_PID_2049_BST_IPEAK_4P00A_VALUE	\
+	(AW_PID_2049_BST_IPEAK_4P00A << AW_PID_2049_BST_IPEAK_START_BIT)
+
+#define AW_PID_2049_BST_IPEAK_4P25A		(11)
+#define AW_PID_2049_BST_IPEAK_4P25A_VALUE	\
+	(AW_PID_2049_BST_IPEAK_4P25A << AW_PID_2049_BST_IPEAK_START_BIT)
+
+#define AW_PID_2049_BST_IPEAK_4P50A		(12)
+#define AW_PID_2049_BST_IPEAK_4P50A_VALUE	\
+	(AW_PID_2049_BST_IPEAK_4P50A << AW_PID_2049_BST_IPEAK_START_BIT)
+
+#define AW_PID_2049_BST_IPEAK_DEFAULT_VALUE	(9)
+#define AW_PID_2049_BST_IPEAK_DEFAULT	\
+	(AW_PID_2049_BST_IPEAK_DEFAULT_VALUE << AW_PID_2049_BST_IPEAK_START_BIT)
+
+/* default value of SYSCTRL2 (0x05) */
+/* #define AW_PID_2049_SYSCTRL2_DEFAULT		(0x0009) */
+
+/* I2SCTRL (0x06) detail */
+/* SLOT_NUM bit 14:12 (I2SCTRL 0x06) */
+#define AW_PID_2049_SLOT_NUM_START_BIT	(12)
+#define AW_PID_2049_SLOT_NUM_BITS_LEN	(3)
+#define AW_PID_2049_SLOT_NUM_MASK		\
+	(~(((1<<AW_PID_2049_SLOT_NUM_BITS_LEN)-1) << AW_PID_2049_SLOT_NUM_START_BIT))
+
+#define AW_PID_2049_SLOT_NUM_I2S_MODE	(0)
+#define AW_PID_2049_SLOT_NUM_I2S_MODE_VALUE	\
+	(AW_PID_2049_SLOT_NUM_I2S_MODE << AW_PID_2049_SLOT_NUM_START_BIT)
+
+#define AW_PID_2049_SLOT_NUM_TDM1S		(1)
+#define AW_PID_2049_SLOT_NUM_TDM1S_VALUE	\
+	(AW_PID_2049_SLOT_NUM_TDM1S << AW_PID_2049_SLOT_NUM_START_BIT)
+
+#define AW_PID_2049_SLOT_NUM_TDM2S		(2)
+#define AW_PID_2049_SLOT_NUM_TDM2S_VALUE	\
+	(AW_PID_2049_SLOT_NUM_TDM2S << AW_PID_2049_SLOT_NUM_START_BIT)
+
+#define AW_PID_2049_SLOT_NUM_TDM4S		(3)
+#define AW_PID_2049_SLOT_NUM_TDM4S_VALUE	\
+	(AW_PID_2049_SLOT_NUM_TDM4S << AW_PID_2049_SLOT_NUM_START_BIT)
+
+#define AW_PID_2049_SLOT_NUM_TDM6S		(4)
+#define AW_PID_2049_SLOT_NUM_TDM6S_VALUE	\
+	(AW_PID_2049_SLOT_NUM_TDM6S << AW_PID_2049_SLOT_NUM_START_BIT)
+
+#define AW_PID_2049_SLOT_NUM_TDM8S		(5)
+#define AW_PID_2049_SLOT_NUM_TDM8S_VALUE	\
+	(AW_PID_2049_SLOT_NUM_TDM8S << AW_PID_2049_SLOT_NUM_START_BIT)
+
+#define AW_PID_2049_SLOT_NUM_TDM16S		(6)
+#define AW_PID_2049_SLOT_NUM_TDM16S_VALUE	\
+	(AW_PID_2049_SLOT_NUM_TDM16S << AW_PID_2049_SLOT_NUM_START_BIT)
+
+#define AW_PID_2049_SLOT_NUM_RESERVED	(7)
+#define AW_PID_2049_SLOT_NUM_RESERVED_VALUE	\
+	(AW_PID_2049_SLOT_NUM_RESERVED << AW_PID_2049_SLOT_NUM_START_BIT)
+
+#define AW_PID_2049_SLOT_NUM_DEFAULT_VALUE	(0)
+#define AW_PID_2049_SLOT_NUM_DEFAULT	\
+	(AW_PID_2049_SLOT_NUM_DEFAULT_VALUE << AW_PID_2049_SLOT_NUM_START_BIT)
+
+/* CHSEL bit 11:10 (I2SCTRL 0x06) */
+#define AW_PID_2049_CHSEL_START_BIT		(10)
+#define AW_PID_2049_CHSEL_BITS_LEN		(2)
+#define AW_PID_2049_CHSEL_MASK			\
+	(~(((1<<AW_PID_2049_CHSEL_BITS_LEN)-1) << AW_PID_2049_CHSEL_START_BIT))
+
+#define AW_PID_2049_CHSEL_RESERVED		(0)
+#define AW_PID_2049_CHSEL_RESERVED_VALUE	\
+	(AW_PID_2049_CHSEL_RESERVED << AW_PID_2049_CHSEL_START_BIT)
+
+#define AW_PID_2049_CHSEL_LEFT			(1)
+#define AW_PID_2049_CHSEL_LEFT_VALUE	\
+	(AW_PID_2049_CHSEL_LEFT << AW_PID_2049_CHSEL_START_BIT)
+
+#define AW_PID_2049_CHSEL_RIGHT			(2)
+#define AW_PID_2049_CHSEL_RIGHT_VALUE	\
+	(AW_PID_2049_CHSEL_RIGHT << AW_PID_2049_CHSEL_START_BIT)
+
+#define AW_PID_2049_CHSEL_MONO			(3)
+#define AW_PID_2049_CHSEL_MONO_VALUE	\
+	(AW_PID_2049_CHSEL_MONO << AW_PID_2049_CHSEL_START_BIT)
+
+#define AW_PID_2049_CHSEL_DEFAULT_VALUE	(1)
+#define AW_PID_2049_CHSEL_DEFAULT		\
+	(AW_PID_2049_CHSEL_DEFAULT_VALUE << AW_PID_2049_CHSEL_START_BIT)
+
+/* I2SMD bit 9:8 (I2SCTRL 0x06) */
+#define AW_PID_2049_I2SMD_START_BIT		(8)
+#define AW_PID_2049_I2SMD_BITS_LEN		(2)
+#define AW_PID_2049_I2SMD_MASK			\
+	(~(((1<<AW_PID_2049_I2SMD_BITS_LEN)-1) << AW_PID_2049_I2SMD_START_BIT))
+
+#define AW_PID_2049_I2SMD_PHILIP_STANDARD	(0)
+#define AW_PID_2049_I2SMD_PHILIP_STANDARD_VALUE	\
+	(AW_PID_2049_I2SMD_PHILIP_STANDARD << AW_PID_2049_I2SMD_START_BIT)
+
+#define AW_PID_2049_I2SMD_MSB_JUSTIFIED	(1)
+#define AW_PID_2049_I2SMD_MSB_JUSTIFIED_VALUE	\
+	(AW_PID_2049_I2SMD_MSB_JUSTIFIED << AW_PID_2049_I2SMD_START_BIT)
+
+#define AW_PID_2049_I2SMD_LSB_JUSTIFIED	(2)
+#define AW_PID_2049_I2SMD_LSB_JUSTIFIED_VALUE	\
+	(AW_PID_2049_I2SMD_LSB_JUSTIFIED << AW_PID_2049_I2SMD_START_BIT)
+
+#define AW_PID_2049_I2SMD_RESERVED		(3)
+#define AW_PID_2049_I2SMD_RESERVED_VALUE	\
+	(AW_PID_2049_I2SMD_RESERVED << AW_PID_2049_I2SMD_START_BIT)
+
+#define AW_PID_2049_I2SMD_DEFAULT_VALUE	(0)
+#define AW_PID_2049_I2SMD_DEFAULT		\
+	(AW_PID_2049_I2SMD_DEFAULT_VALUE << AW_PID_2049_I2SMD_START_BIT)
+
+/* I2SFS bit 7:6 (I2SCTRL 0x06) */
+#define AW_PID_2049_I2SFS_START_BIT		(6)
+#define AW_PID_2049_I2SFS_BITS_LEN		(2)
+#define AW_PID_2049_I2SFS_MASK			\
+	(~(((1<<AW_PID_2049_I2SFS_BITS_LEN)-1) << AW_PID_2049_I2SFS_START_BIT))
+
+#define AW_PID_2049_I2SFS_16_BITS		(0)
+#define AW_PID_2049_I2SFS_16_BITS_VALUE	\
+	(AW_PID_2049_I2SFS_16_BITS << AW_PID_2049_I2SFS_START_BIT)
+
+#define AW_PID_2049_I2SFS_20_BITS		(1)
+#define AW_PID_2049_I2SFS_20_BITS_VALUE	\
+	(AW_PID_2049_I2SFS_20_BITS << AW_PID_2049_I2SFS_START_BIT)
+
+#define AW_PID_2049_I2SFS_24_BITS		(2)
+#define AW_PID_2049_I2SFS_24_BITS_VALUE	\
+	(AW_PID_2049_I2SFS_24_BITS << AW_PID_2049_I2SFS_START_BIT)
+
+#define AW_PID_2049_I2SFS_32_BITS		(3)
+#define AW_PID_2049_I2SFS_32_BITS_VALUE	\
+	(AW_PID_2049_I2SFS_32_BITS << AW_PID_2049_I2SFS_START_BIT)
+
+#define AW_PID_2049_I2SFS_DEFAULT_VALUE	(3)
+#define AW_PID_2049_I2SFS_DEFAULT		\
+	(AW_PID_2049_I2SFS_DEFAULT_VALUE << AW_PID_2049_I2SFS_START_BIT)
+
+/* I2SBCK bit 5:4 (I2SCTRL 0x06) */
+#define AW_PID_2049_I2SBCK_START_BIT	(4)
+#define AW_PID_2049_I2SBCK_BITS_LEN		(2)
+#define AW_PID_2049_I2SBCK_MASK			\
+	(~(((1<<AW_PID_2049_I2SBCK_BITS_LEN)-1) << AW_PID_2049_I2SBCK_START_BIT))
+
+#define AW_PID_2049_I2SBCK_32FS			(0)
+#define AW_PID_2049_I2SBCK_32FS_VALUE	\
+	(AW_PID_2049_I2SBCK_32FS << AW_PID_2049_I2SBCK_START_BIT)
+
+#define AW_PID_2049_I2SBCK_48FS			(1)
+#define AW_PID_2049_I2SBCK_48FS_VALUE	\
+	(AW_PID_2049_I2SBCK_48FS << AW_PID_2049_I2SBCK_START_BIT)
+
+#define AW_PID_2049_I2SBCK_64FS			(2)
+#define AW_PID_2049_I2SBCK_64FS_VALUE	\
+	(AW_PID_2049_I2SBCK_64FS << AW_PID_2049_I2SBCK_START_BIT)
+
+#define AW_PID_2049_I2SBCK_RESERVED		(3)
+#define AW_PID_2049_I2SBCK_RESERVED_VALUE	\
+	(AW_PID_2049_I2SBCK_RESERVED << AW_PID_2049_I2SBCK_START_BIT)
+
+#define AW_PID_2049_I2SBCK_DEFAULT_VALUE	(2)
+#define AW_PID_2049_I2SBCK_DEFAULT		\
+	(AW_PID_2049_I2SBCK_DEFAULT_VALUE << AW_PID_2049_I2SBCK_START_BIT)
+
+/* I2SSR bit 3:0 (I2SCTRL 0x06) */
+#define AW_PID_2049_I2SSR_START_BIT		(0)
+#define AW_PID_2049_I2SSR_BITS_LEN		(4)
+#define AW_PID_2049_I2SSR_MASK			\
+	(~(((1<<AW_PID_2049_I2SSR_BITS_LEN)-1) << AW_PID_2049_I2SSR_START_BIT))
+
+#define AW_PID_2049_I2SSR_8_KHZ			(0)
+#define AW_PID_2049_I2SSR_8_KHZ_VALUE	\
+	(AW_PID_2049_I2SSR_8_KHZ << AW_PID_2049_I2SSR_START_BIT)
+
+#define AW_PID_2049_I2SSR_11_KHZ		(1)
+#define AW_PID_2049_I2SSR_11_KHZ_VALUE	\
+	(AW_PID_2049_I2SSR_11_KHZ << AW_PID_2049_I2SSR_START_BIT)
+
+#define AW_PID_2049_I2SSR_12_KHZ		(2)
+#define AW_PID_2049_I2SSR_12_KHZ_VALUE	\
+	(AW_PID_2049_I2SSR_12_KHZ << AW_PID_2049_I2SSR_START_BIT)
+
+#define AW_PID_2049_I2SSR_16_KHZ		(3)
+#define AW_PID_2049_I2SSR_16_KHZ_VALUE	\
+	(AW_PID_2049_I2SSR_16_KHZ << AW_PID_2049_I2SSR_START_BIT)
+
+#define AW_PID_2049_I2SSR_22_KHZ		(4)
+#define AW_PID_2049_I2SSR_22_KHZ_VALUE	\
+	(AW_PID_2049_I2SSR_22_KHZ << AW_PID_2049_I2SSR_START_BIT)
+
+#define AW_PID_2049_I2SSR_24_KHZ		(5)
+#define AW_PID_2049_I2SSR_24_KHZ_VALUE	\
+	(AW_PID_2049_I2SSR_24_KHZ << AW_PID_2049_I2SSR_START_BIT)
+
+#define AW_PID_2049_I2SSR_32_KHZ		(6)
+#define AW_PID_2049_I2SSR_32_KHZ_VALUE	\
+	(AW_PID_2049_I2SSR_32_KHZ << AW_PID_2049_I2SSR_START_BIT)
+
+#define AW_PID_2049_I2SSR_44_KHZ		(7)
+#define AW_PID_2049_I2SSR_44_KHZ_VALUE	\
+	(AW_PID_2049_I2SSR_44_KHZ << AW_PID_2049_I2SSR_START_BIT)
+
+#define AW_PID_2049_I2SSR_48_KHZ		(8)
+#define AW_PID_2049_I2SSR_48_KHZ_VALUE	\
+	(AW_PID_2049_I2SSR_48_KHZ << AW_PID_2049_I2SSR_START_BIT)
+
+#define AW_PID_2049_I2SSR_96_KHZ		(9)
+#define AW_PID_2049_I2SSR_96_KHZ_VALUE	\
+	(AW_PID_2049_I2SSR_96_KHZ << AW_PID_2049_I2SSR_START_BIT)
+
+#define AW_PID_2049_I2SSR_192KHZ		(10)
+#define AW_PID_2049_I2SSR_192KHZ_VALUE	\
+	(AW_PID_2049_I2SSR_192KHZ << AW_PID_2049_I2SSR_START_BIT)
+
+#define AW_PID_2049_I2SSR_DEFAULT_VALUE	(8)
+#define AW_PID_2049_I2SSR_DEFAULT		\
+	(AW_PID_2049_I2SSR_DEFAULT_VALUE << AW_PID_2049_I2SSR_START_BIT)
+
+/* default value of I2SCTRL (0x06) */
+/* #define AW_PID_2049_I2SCTRL_DEFAULT		(0x04E8) */
+
+/* I2SCFG1 (0x07) detail */
+/* I2S_RXL_SLOTVLD bit 15:12 (I2SCFG1 0x07) */
+#define AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT	(12)
+#define AW_PID_2049_I2S_RXL_SLOTVLD_BITS_LEN	(4)
+#define AW_PID_2049_I2S_RXL_SLOTVLD_MASK	\
+	(~(((1<<AW_PID_2049_I2S_RXL_SLOTVLD_BITS_LEN)-1) << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT))
+
+#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_0	(0)
+#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_0_VALUE	\
+	(AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_0 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT)
+
+#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_1	(1)
+#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_1_VALUE	\
+	(AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_1 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT)
+
+#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_2	(2)
+#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_2_VALUE	\
+	(AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_2 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT)
+
+#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_3	(3)
+#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_3_VALUE	\
+	(AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_3 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT)
+
+#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_15	(15)
+#define AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_15_VALUE	\
+	(AW_PID_2049_I2S_RXL_SLOTVLD_SLOT_15 << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT)
+
+#define AW_PID_2049_I2S_RXL_SLOTVLD_DEFAULT_VALUE	(0)
+#define AW_PID_2049_I2S_RXL_SLOTVLD_DEFAULT	\
+	(AW_PID_2049_I2S_RXL_SLOTVLD_DEFAULT_VALUE << AW_PID_2049_I2S_RXL_SLOTVLD_START_BIT)
+
+/* I2S_RXR_SLOTVLD bit 11:8 (I2SCFG1 0x07) */
+#define AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT	(8)
+#define AW_PID_2049_I2S_RXR_SLOTVLD_BITS_LEN	(4)
+#define AW_PID_2049_I2S_RXR_SLOTVLD_MASK	\
+	(~(((1<<AW_PID_2049_I2S_RXR_SLOTVLD_BITS_LEN)-1) << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT))
+
+#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_0	(0)
+#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_0_VALUE	\
+	(AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_0 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT)
+
+#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_1	(1)
+#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_1_VALUE	\
+	(AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_1 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT)
+
+#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_2	(2)
+#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_2_VALUE	\
+	(AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_2 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT)
+
+#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_3	(3)
+#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_3_VALUE	\
+	(AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_3 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT)
+
+#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_15	(15)
+#define AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_15_VALUE	\
+	(AW_PID_2049_I2S_RXR_SLOTVLD_SLOT_15 << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT)
+
+#define AW_PID_2049_I2S_RXR_SLOTVLD_DEFAULT_VALUE	(1)
+#define AW_PID_2049_I2S_RXR_SLOTVLD_DEFAULT	\
+	(AW_PID_2049_I2S_RXR_SLOTVLD_DEFAULT_VALUE << AW_PID_2049_I2S_RXR_SLOTVLD_START_BIT)
+
+/* I2S_TX_SLOTVLD bit 7:4 (I2SCFG1 0x07) */
+#define AW_PID_2049_I2S_TX_SLOTVLD_START_BIT	(4)
+#define AW_PID_2049_I2S_TX_SLOTVLD_BITS_LEN	(4)
+#define AW_PID_2049_I2S_TX_SLOTVLD_MASK	\
+	(~(((1<<AW_PID_2049_I2S_TX_SLOTVLD_BITS_LEN)-1) << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT))
+
+#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_0	(0)
+#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_0_VALUE	\
+	(AW_PID_2049_I2S_TX_SLOTVLD_SLOT_0 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT)
+
+#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_1	(1)
+#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_1_VALUE	\
+	(AW_PID_2049_I2S_TX_SLOTVLD_SLOT_1 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT)
+
+#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_2	(2)
+#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_2_VALUE	\
+	(AW_PID_2049_I2S_TX_SLOTVLD_SLOT_2 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT)
+
+#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_3	(3)
+#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_3_VALUE	\
+	(AW_PID_2049_I2S_TX_SLOTVLD_SLOT_3 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT)
+
+#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_15	(15)
+#define AW_PID_2049_I2S_TX_SLOTVLD_SLOT_15_VALUE	\
+	(AW_PID_2049_I2S_TX_SLOTVLD_SLOT_15 << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT)
+
+#define AW_PID_2049_I2S_TX_SLOTVLD_DEFAULT_VALUE	(0)
+#define AW_PID_2049_I2S_TX_SLOTVLD_DEFAULT	\
+	(AW_PID_2049_I2S_TX_SLOTVLD_DEFAULT_VALUE << AW_PID_2049_I2S_TX_SLOTVLD_START_BIT)
+
+/* FSYNC_TYPE bit 3 (I2SCFG1 0x07) */
+#define AW_PID_2049_FSYNC_TYPE_START_BIT	(3)
+#define AW_PID_2049_FSYNC_TYPE_BITS_LEN	(1)
+#define AW_PID_2049_FSYNC_TYPE_MASK		\
+	(~(((1<<AW_PID_2049_FSYNC_TYPE_BITS_LEN)-1) << AW_PID_2049_FSYNC_TYPE_START_BIT))
+
+#define AW_PID_2049_FSYNC_TYPE_ONEMINUS_SLOT	(0)
+#define AW_PID_2049_FSYNC_TYPE_ONEMINUS_SLOT_VALUE	\
+	(AW_PID_2049_FSYNC_TYPE_ONEMINUS_SLOT << AW_PID_2049_FSYNC_TYPE_START_BIT)
+
+#define AW_PID_2049_FSYNC_TYPE_ONEMINUS_BCK	(1)
+#define AW_PID_2049_FSYNC_TYPE_ONEMINUS_BCK_VALUE	\
+	(AW_PID_2049_FSYNC_TYPE_ONEMINUS_BCK << AW_PID_2049_FSYNC_TYPE_START_BIT)
+
+#define AW_PID_2049_FSYNC_TYPE_DEFAULT_VALUE	(0)
+#define AW_PID_2049_FSYNC_TYPE_DEFAULT	\
+	(AW_PID_2049_FSYNC_TYPE_DEFAULT_VALUE << AW_PID_2049_FSYNC_TYPE_START_BIT)
+
+/* I2SCHS bit 2 (I2SCFG1 0x07) */
+#define AW_PID_2049_I2SCHS_START_BIT	(2)
+#define AW_PID_2049_I2SCHS_BITS_LEN		(1)
+#define AW_PID_2049_I2SCHS_MASK			\
+	(~(((1<<AW_PID_2049_I2SCHS_BITS_LEN)-1) << AW_PID_2049_I2SCHS_START_BIT))
+
+#define AW_PID_2049_I2SCHS_LEFT			(0)
+#define AW_PID_2049_I2SCHS_LEFT_VALUE	\
+	(AW_PID_2049_I2SCHS_LEFT << AW_PID_2049_I2SCHS_START_BIT)
+
+#define AW_PID_2049_I2SCHS_RIGHT		(1)
+#define AW_PID_2049_I2SCHS_RIGHT_VALUE	\
+	(AW_PID_2049_I2SCHS_RIGHT << AW_PID_2049_I2SCHS_START_BIT)
+
+#define AW_PID_2049_I2SCHS_DEFAULT_VALUE	(0)
+#define AW_PID_2049_I2SCHS_DEFAULT		\
+	(AW_PID_2049_I2SCHS_DEFAULT_VALUE << AW_PID_2049_I2SCHS_START_BIT)
+
+/* I2SRXEN bit 1 (I2SCFG1 0x07) */
+#define AW_PID_2049_I2SRXEN_START_BIT	(1)
+#define AW_PID_2049_I2SRXEN_BITS_LEN	(1)
+#define AW_PID_2049_I2SRXEN_MASK		\
+	(~(((1<<AW_PID_2049_I2SRXEN_BITS_LEN)-1) << AW_PID_2049_I2SRXEN_START_BIT))
+
+#define AW_PID_2049_I2SRXEN_DISABLE		(0)
+#define AW_PID_2049_I2SRXEN_DISABLE_VALUE	\
+	(AW_PID_2049_I2SRXEN_DISABLE << AW_PID_2049_I2SRXEN_START_BIT)
+
+#define AW_PID_2049_I2SRXEN_ENABLE		(1)
+#define AW_PID_2049_I2SRXEN_ENABLE_VALUE	\
+	(AW_PID_2049_I2SRXEN_ENABLE << AW_PID_2049_I2SRXEN_START_BIT)
+
+#define AW_PID_2049_I2SRXEN_DEFAULT_VALUE	(1)
+#define AW_PID_2049_I2SRXEN_DEFAULT		\
+	(AW_PID_2049_I2SRXEN_DEFAULT_VALUE << AW_PID_2049_I2SRXEN_START_BIT)
+
+/* I2STXEN bit 0 (I2SCFG1 0x07) */
+#define AW_PID_2049_I2STXEN_START_BIT	(0)
+#define AW_PID_2049_I2STXEN_BITS_LEN	(1)
+#define AW_PID_2049_I2STXEN_MASK		\
+	(~(((1<<AW_PID_2049_I2STXEN_BITS_LEN)-1) << AW_PID_2049_I2STXEN_START_BIT))
+
+#define AW_PID_2049_I2STXEN_DISABLE		(0)
+#define AW_PID_2049_I2STXEN_DISABLE_VALUE	\
+	(AW_PID_2049_I2STXEN_DISABLE << AW_PID_2049_I2STXEN_START_BIT)
+
+#define AW_PID_2049_I2STXEN_ENABLE		(1)
+#define AW_PID_2049_I2STXEN_ENABLE_VALUE	\
+	(AW_PID_2049_I2STXEN_ENABLE << AW_PID_2049_I2STXEN_START_BIT)
+
+#define AW_PID_2049_I2STXEN_DEFAULT_VALUE	(0)
+#define AW_PID_2049_I2STXEN_DEFAULT		\
+	(AW_PID_2049_I2STXEN_DEFAULT_VALUE << AW_PID_2049_I2STXEN_START_BIT)
+
+/* default value of I2SCFG1 (0x07) */
+/* #define AW_PID_2049_I2SCFG1_DEFAULT		(0x0102) */
+
+/* I2SCFG2 (0x08) detail */
+/* ULS_FIR_MD bit 14 (I2SCFG2 0x08) */
+#define AW_PID_2049_ULS_FIR_MD_START_BIT	(14)
+#define AW_PID_2049_ULS_FIR_MD_BITS_LEN	(1)
+#define AW_PID_2049_ULS_FIR_MD_MASK		\
+	(~(((1<<AW_PID_2049_ULS_FIR_MD_BITS_LEN)-1) << AW_PID_2049_ULS_FIR_MD_START_BIT))
+
+#define AW_PID_2049_ULS_FIR_MD_NOTMINUS_USED	(0)
+#define AW_PID_2049_ULS_FIR_MD_NOTMINUS_USED_VALUE	\
+	(AW_PID_2049_ULS_FIR_MD_NOTMINUS_USED << AW_PID_2049_ULS_FIR_MD_START_BIT)
+
+#define AW_PID_2049_ULS_FIR_MD_USED		(1)
+#define AW_PID_2049_ULS_FIR_MD_USED_VALUE	\
+	(AW_PID_2049_ULS_FIR_MD_USED << AW_PID_2049_ULS_FIR_MD_START_BIT)
+
+#define AW_PID_2049_ULS_FIR_MD_DEFAULT_VALUE	(0)
+#define AW_PID_2049_ULS_FIR_MD_DEFAULT	\
+	(AW_PID_2049_ULS_FIR_MD_DEFAULT_VALUE << AW_PID_2049_ULS_FIR_MD_START_BIT)
+
+/* ULS_MODE bit 13 (I2SCFG2 0x08) */
+#define AW_PID_2049_ULS_MODE_START_BIT	(13)
+#define AW_PID_2049_ULS_MODE_BITS_LEN	(1)
+#define AW_PID_2049_ULS_MODE_MASK		\
+	(~(((1<<AW_PID_2049_ULS_MODE_BITS_LEN)-1) << AW_PID_2049_ULS_MODE_START_BIT))
+
+#define AW_PID_2049_ULS_MODE_LOWPASS	(0)
+#define AW_PID_2049_ULS_MODE_LOWPASS_VALUE	\
+	(AW_PID_2049_ULS_MODE_LOWPASS << AW_PID_2049_ULS_MODE_START_BIT)
+
+#define AW_PID_2049_ULS_MODE_TDM		(1)
+#define AW_PID_2049_ULS_MODE_TDM_VALUE	\
+	(AW_PID_2049_ULS_MODE_TDM << AW_PID_2049_ULS_MODE_START_BIT)
+
+#define AW_PID_2049_ULS_MODE_DEFAULT_VALUE	(0)
+#define AW_PID_2049_ULS_MODE_DEFAULT	\
+	(AW_PID_2049_ULS_MODE_DEFAULT_VALUE << AW_PID_2049_ULS_MODE_START_BIT)
+
+/* ULS_EN bit 12 (I2SCFG2 0x08) */
+#define AW_PID_2049_ULS_EN_START_BIT	(12)
+#define AW_PID_2049_ULS_EN_BITS_LEN		(1)
+#define AW_PID_2049_ULS_EN_MASK			\
+	(~(((1<<AW_PID_2049_ULS_EN_BITS_LEN)-1) << AW_PID_2049_ULS_EN_START_BIT))
+
+#define AW_PID_2049_ULS_EN_DISABLE		(0)
+#define AW_PID_2049_ULS_EN_DISABLE_VALUE	\
+	(AW_PID_2049_ULS_EN_DISABLE << AW_PID_2049_ULS_EN_START_BIT)
+
+#define AW_PID_2049_ULS_EN_ENABLE		(1)
+#define AW_PID_2049_ULS_EN_ENABLE_VALUE	\
+	(AW_PID_2049_ULS_EN_ENABLE << AW_PID_2049_ULS_EN_START_BIT)
+
+#define AW_PID_2049_ULS_EN_DEFAULT_VALUE	(0)
+#define AW_PID_2049_ULS_EN_DEFAULT		\
+	(AW_PID_2049_ULS_EN_DEFAULT_VALUE << AW_PID_2049_ULS_EN_START_BIT)
+
+/* IV2CH bit 9 (I2SCFG2 0x08) */
+#define AW_PID_2049_IV2CH_START_BIT		(9)
+#define AW_PID_2049_IV2CH_BITS_LEN		(1)
+#define AW_PID_2049_IV2CH_MASK			\
+	(~(((1<<AW_PID_2049_IV2CH_BITS_LEN)-1) << AW_PID_2049_IV2CH_START_BIT))
+
+#define AW_PID_2049_IV2CH_LEGACY		(0)
+#define AW_PID_2049_IV2CH_LEGACY_VALUE	\
+	(AW_PID_2049_IV2CH_LEGACY << AW_PID_2049_IV2CH_START_BIT)
+
+#define AW_PID_2049_IV2CH_SPECIAL		(1)
+#define AW_PID_2049_IV2CH_SPECIAL_VALUE	\
+	(AW_PID_2049_IV2CH_SPECIAL << AW_PID_2049_IV2CH_START_BIT)
+
+#define AW_PID_2049_IV2CH_DEFAULT_VALUE	(0)
+#define AW_PID_2049_IV2CH_DEFAULT		\
+	(AW_PID_2049_IV2CH_DEFAULT_VALUE << AW_PID_2049_IV2CH_START_BIT)
+
+/* I2S_TXEDGE bit 8 (I2SCFG2 0x08) */
+#define AW_PID_2049_I2S_TXEDGE_START_BIT	(8)
+#define AW_PID_2049_I2S_TXEDGE_BITS_LEN	(1)
+#define AW_PID_2049_I2S_TXEDGE_MASK		\
+	(~(((1<<AW_PID_2049_I2S_TXEDGE_BITS_LEN)-1) << AW_PID_2049_I2S_TXEDGE_START_BIT))
+
+#define AW_PID_2049_I2S_TXEDGE_NEGEDGE	(0)
+#define AW_PID_2049_I2S_TXEDGE_NEGEDGE_VALUE	\
+	(AW_PID_2049_I2S_TXEDGE_NEGEDGE << AW_PID_2049_I2S_TXEDGE_START_BIT)
+
+#define AW_PID_2049_I2S_TXEDGE_POSEDGE	(1)
+#define AW_PID_2049_I2S_TXEDGE_POSEDGE_VALUE	\
+	(AW_PID_2049_I2S_TXEDGE_POSEDGE << AW_PID_2049_I2S_TXEDGE_START_BIT)
+
+#define AW_PID_2049_I2S_TXEDGE_DEFAULT_VALUE	(0)
+#define AW_PID_2049_I2S_TXEDGE_DEFAULT	\
+	(AW_PID_2049_I2S_TXEDGE_DEFAULT_VALUE << AW_PID_2049_I2S_TXEDGE_START_BIT)
+
+/* I2SDOSEL bit 7 (I2SCFG2 0x08) */
+#define AW_PID_2049_I2SDOSEL_START_BIT	(7)
+#define AW_PID_2049_I2SDOSEL_BITS_LEN	(1)
+#define AW_PID_2049_I2SDOSEL_MASK		\
+	(~(((1<<AW_PID_2049_I2SDOSEL_BITS_LEN)-1) << AW_PID_2049_I2SDOSEL_START_BIT))
+
+#define AW_PID_2049_I2SDOSEL_ZEROS		(0)
+#define AW_PID_2049_I2SDOSEL_ZEROS_VALUE	\
+	(AW_PID_2049_I2SDOSEL_ZEROS << AW_PID_2049_I2SDOSEL_START_BIT)
+
+#define AW_PID_2049_I2SDOSEL_TXDATA		(1)
+#define AW_PID_2049_I2SDOSEL_TXDATA_VALUE	\
+	(AW_PID_2049_I2SDOSEL_TXDATA << AW_PID_2049_I2SDOSEL_START_BIT)
+
+#define AW_PID_2049_I2SDOSEL_DEFAULT_VALUE	(0)
+#define AW_PID_2049_I2SDOSEL_DEFAULT	\
+	(AW_PID_2049_I2SDOSEL_DEFAULT_VALUE << AW_PID_2049_I2SDOSEL_START_BIT)
+
+/* DOHZ bit 6 (I2SCFG2 0x08) */
+#define AW_PID_2049_DOHZ_START_BIT		(6)
+#define AW_PID_2049_DOHZ_BITS_LEN		(1)
+#define AW_PID_2049_DOHZ_MASK			\
+	(~(((1<<AW_PID_2049_DOHZ_BITS_LEN)-1) << AW_PID_2049_DOHZ_START_BIT))
+
+#define AW_PID_2049_DOHZ_ALL			(0)
+#define AW_PID_2049_DOHZ_ALL_VALUE		\
+	(AW_PID_2049_DOHZ_ALL << AW_PID_2049_DOHZ_START_BIT)
+
+#define AW_PID_2049_DOHZ_HIZ			(1)
+#define AW_PID_2049_DOHZ_HIZ_VALUE		\
+	(AW_PID_2049_DOHZ_HIZ << AW_PID_2049_DOHZ_START_BIT)
+
+#define AW_PID_2049_DOHZ_DEFAULT_VALUE	(1)
+#define AW_PID_2049_DOHZ_DEFAULT		\
+	(AW_PID_2049_DOHZ_DEFAULT_VALUE << AW_PID_2049_DOHZ_START_BIT)
+
+/* DRVSTREN bit 5 (I2SCFG2 0x08) */
+#define AW_PID_2049_DRVSTREN_START_BIT	(5)
+#define AW_PID_2049_DRVSTREN_BITS_LEN	(1)
+#define AW_PID_2049_DRVSTREN_MASK		\
+	(~(((1<<AW_PID_2049_DRVSTREN_BITS_LEN)-1) << AW_PID_2049_DRVSTREN_START_BIT))
+
+#define AW_PID_2049_DRVSTREN_4MA		(0)
+#define AW_PID_2049_DRVSTREN_4MA_VALUE	\
+	(AW_PID_2049_DRVSTREN_4MA << AW_PID_2049_DRVSTREN_START_BIT)
+
+#define AW_PID_2049_DRVSTREN_12MA		(1)
+#define AW_PID_2049_DRVSTREN_12MA_VALUE	\
+	(AW_PID_2049_DRVSTREN_12MA << AW_PID_2049_DRVSTREN_START_BIT)
+
+#define AW_PID_2049_DRVSTREN_DEFAULT_VALUE	(1)
+#define AW_PID_2049_DRVSTREN_DEFAULT	\
+	(AW_PID_2049_DRVSTREN_DEFAULT_VALUE << AW_PID_2049_DRVSTREN_START_BIT)
+
+/* INPLEV bit 4 (I2SCFG2 0x08) */
+#define AW_PID_2049_INPLEV_START_BIT	(4)
+#define AW_PID_2049_INPLEV_BITS_LEN		(1)
+#define AW_PID_2049_INPLEV_MASK			\
+	(~(((1<<AW_PID_2049_INPLEV_BITS_LEN)-1) << AW_PID_2049_INPLEV_START_BIT))
+
+#define AW_PID_2049_INPLEV_NOT_ATTENUATED	(0)
+#define AW_PID_2049_INPLEV_NOT_ATTENUATED_VALUE	\
+	(AW_PID_2049_INPLEV_NOT_ATTENUATED << AW_PID_2049_INPLEV_START_BIT)
+
+#define AW_PID_2049_INPLEV_ATTENUATED	(1)
+#define AW_PID_2049_INPLEV_ATTENUATED_VALUE	\
+	(AW_PID_2049_INPLEV_ATTENUATED << AW_PID_2049_INPLEV_START_BIT)
+
+#define AW_PID_2049_INPLEV_DEFAULT_VALUE	(0)
+#define AW_PID_2049_INPLEV_DEFAULT		\
+	(AW_PID_2049_INPLEV_DEFAULT_VALUE << AW_PID_2049_INPLEV_START_BIT)
+
+/* CFSEL bit 2:0 (I2SCFG2 0x08) */
+#define AW_PID_2049_CFSEL_START_BIT		(0)
+#define AW_PID_2049_CFSEL_BITS_LEN		(3)
+#define AW_PID_2049_CFSEL_MASK			\
+	(~(((1<<AW_PID_2049_CFSEL_BITS_LEN)-1) << AW_PID_2049_CFSEL_START_BIT))
+
+#define AW_PID_2049_CFSEL_HAGC			(0)
+#define AW_PID_2049_CFSEL_HAGC_VALUE	\
+	(AW_PID_2049_CFSEL_HAGC << AW_PID_2049_CFSEL_START_BIT)
+
+#define AW_PID_2049_CFSEL_DFIFO			(1)
+#define AW_PID_2049_CFSEL_DFIFO_VALUE	\
+	(AW_PID_2049_CFSEL_DFIFO << AW_PID_2049_CFSEL_START_BIT)
+
+#define AW_PID_2049_CFSEL_ULS			(2)
+#define AW_PID_2049_CFSEL_ULS_VALUE		\
+	(AW_PID_2049_CFSEL_ULS << AW_PID_2049_CFSEL_START_BIT)
+
+#define AW_PID_2049_CFSEL_IVT_FS		(3)
+#define AW_PID_2049_CFSEL_IVT_FS_VALUE	\
+	(AW_PID_2049_CFSEL_IVT_FS << AW_PID_2049_CFSEL_START_BIT)
+
+#define AW_PID_2049_CFSEL_IVT_IPVT		(4)
+#define AW_PID_2049_CFSEL_IVT_IPVT_VALUE	\
+	(AW_PID_2049_CFSEL_IVT_IPVT << AW_PID_2049_CFSEL_START_BIT)
+
+#define AW_PID_2049_CFSEL_DEFAULT_VALUE	(0)
+#define AW_PID_2049_CFSEL_DEFAULT		\
+	(AW_PID_2049_CFSEL_DEFAULT_VALUE << AW_PID_2049_CFSEL_START_BIT)
+
+/* default value of I2SCFG2 (0x08) */
+/* #define AW_PID_2049_I2SCFG2_DEFAULT		(0x0060) */
+
+/* HAGCCFG1 (0x09) detail */
+/* RVTH bit 15:8 (HAGCCFG1 0x09) */
+#define AW_PID_2049_RVTH_START_BIT		(8)
+#define AW_PID_2049_RVTH_BITS_LEN		(8)
+#define AW_PID_2049_RVTH_MASK			\
+	(~(((1<<AW_PID_2049_RVTH_BITS_LEN)-1) << AW_PID_2049_RVTH_START_BIT))
+
+#define AW_PID_2049_RVTH_DEFAULT_VALUE	(0x39)
+#define AW_PID_2049_RVTH_DEFAULT		\
+	(AW_PID_2049_RVTH_DEFAULT_VALUE << AW_PID_2049_RVTH_START_BIT)
+
+/* AVTH bit 7:0 (HAGCCFG1 0x09) */
+#define AW_PID_2049_AVTH_START_BIT		(0)
+#define AW_PID_2049_AVTH_BITS_LEN		(8)
+#define AW_PID_2049_AVTH_MASK			\
+	(~(((1<<AW_PID_2049_AVTH_BITS_LEN)-1) << AW_PID_2049_AVTH_START_BIT))
+
+#define AW_PID_2049_AVTH_DEFAULT_VALUE	(0x40)
+#define AW_PID_2049_AVTH_DEFAULT		\
+	(AW_PID_2049_AVTH_DEFAULT_VALUE << AW_PID_2049_AVTH_START_BIT)
+
+/* default value of HAGCCFG1 (0x09) */
+/* #define AW_PID_2049_HAGCCFG1_DEFAULT		(0x3940) */
+
+/* HAGCCFG2 (0x0A) detail */
+/* ATTH bit 15:0 (HAGCCFG2 0x0A) */
+#define AW_PID_2049_ATTH_START_BIT		(0)
+#define AW_PID_2049_ATTH_BITS_LEN		(16)
+#define AW_PID_2049_ATTH_MASK			\
+	(~(((1<<AW_PID_2049_ATTH_BITS_LEN)-1) << AW_PID_2049_ATTH_START_BIT))
+
+#define AW_PID_2049_ATTH_RESERVED		(0)
+#define AW_PID_2049_ATTH_RESERVED_VALUE	\
+	(AW_PID_2049_ATTH_RESERVED << AW_PID_2049_ATTH_START_BIT)
+
+#define AW_PID_2049_ATTH_DEFAULT_VALUE	(0x0030)
+#define AW_PID_2049_ATTH_DEFAULT		\
+	(AW_PID_2049_ATTH_DEFAULT_VALUE << AW_PID_2049_ATTH_START_BIT)
+
+/* default value of HAGCCFG2 (0x0A) */
+/* #define AW_PID_2049_HAGCCFG2_DEFAULT		(0x0030) */
+
+/* HAGCCFG3 (0x0B) detail */
+/* RTTH bit 15:0 (HAGCCFG3 0x0B) */
+#define AW_PID_2049_RTTH_START_BIT		(0)
+#define AW_PID_2049_RTTH_BITS_LEN		(16)
+#define AW_PID_2049_RTTH_MASK			\
+	(~(((1<<AW_PID_2049_RTTH_BITS_LEN)-1) << AW_PID_2049_RTTH_START_BIT))
+
+#define AW_PID_2049_RTTH_RESERVED		(0)
+#define AW_PID_2049_RTTH_RESERVED_VALUE	\
+	(AW_PID_2049_RTTH_RESERVED << AW_PID_2049_RTTH_START_BIT)
+
+#define AW_PID_2049_RTTH_DEFAULT_VALUE	(0x01E0)
+#define AW_PID_2049_RTTH_DEFAULT		\
+	(AW_PID_2049_RTTH_DEFAULT_VALUE << AW_PID_2049_RTTH_START_BIT)
+
+/* default value of HAGCCFG3 (0x0B) */
+/* #define AW_PID_2049_HAGCCFG3_DEFAULT		(0x01E0) */
+
+/* HAGCCFG4 (0x0C) detail */
+/* IIC_GEN_ADDR bit 15:9 (HAGCCFG4 0x0C) */
+#define AW_PID_2049_IIC_GEN_ADDR_START_BIT	(9)
+#define AW_PID_2049_IIC_GEN_ADDR_BITS_LEN	(7)
+#define AW_PID_2049_IIC_GEN_ADDR_MASK	\
+	(~(((1<<AW_PID_2049_IIC_GEN_ADDR_BITS_LEN)-1) << AW_PID_2049_IIC_GEN_ADDR_START_BIT))
+
+#define AW_PID_2049_IIC_GEN_ADDR_DEFAULT_VALUE	(0x0E)
+#define AW_PID_2049_IIC_GEN_ADDR_DEFAULT	\
+	(AW_PID_2049_IIC_GEN_ADDR_DEFAULT_VALUE << AW_PID_2049_IIC_GEN_ADDR_START_BIT)
+
+/* IIC_GEN_EN bit 8 (HAGCCFG4 0x0C) */
+#define AW_PID_2049_IIC_GEN_EN_START_BIT	(8)
+#define AW_PID_2049_IIC_GEN_EN_BITS_LEN	(1)
+#define AW_PID_2049_IIC_GEN_EN_MASK		\
+	(~(((1<<AW_PID_2049_IIC_GEN_EN_BITS_LEN)-1) << AW_PID_2049_IIC_GEN_EN_START_BIT))
+
+#define AW_PID_2049_IIC_GEN_EN_DISABLE	(0)
+#define AW_PID_2049_IIC_GEN_EN_DISABLE_VALUE	\
+	(AW_PID_2049_IIC_GEN_EN_DISABLE << AW_PID_2049_IIC_GEN_EN_START_BIT)
+
+#define AW_PID_2049_IIC_GEN_EN_ENABLE	(1)
+#define AW_PID_2049_IIC_GEN_EN_ENABLE_VALUE	\
+	(AW_PID_2049_IIC_GEN_EN_ENABLE << AW_PID_2049_IIC_GEN_EN_START_BIT)
+
+#define AW_PID_2049_IIC_GEN_EN_DEFAULT_VALUE	(0)
+#define AW_PID_2049_IIC_GEN_EN_DEFAULT	\
+	(AW_PID_2049_IIC_GEN_EN_DEFAULT_VALUE << AW_PID_2049_IIC_GEN_EN_START_BIT)
+
+/* HOLDTH bit 7:0 (HAGCCFG4 0x0C) */
+#define AW_PID_2049_HOLDTH_START_BIT	(0)
+#define AW_PID_2049_HOLDTH_BITS_LEN		(8)
+#define AW_PID_2049_HOLDTH_MASK			\
+	(~(((1<<AW_PID_2049_HOLDTH_BITS_LEN)-1) << AW_PID_2049_HOLDTH_START_BIT))
+
+#define AW_PID_2049_HOLDTH_RESERVED		(0)
+#define AW_PID_2049_HOLDTH_RESERVED_VALUE	\
+	(AW_PID_2049_HOLDTH_RESERVED << AW_PID_2049_HOLDTH_START_BIT)
+
+#define AW_PID_2049_HOLDTH_DEFAULT_VALUE	(0x64)
+#define AW_PID_2049_HOLDTH_DEFAULT		\
+	(AW_PID_2049_HOLDTH_DEFAULT_VALUE << AW_PID_2049_HOLDTH_START_BIT)
+
+/* default value of HAGCCFG4 (0x0C) */
+/* #define AW_PID_2049_HAGCCFG4_DEFAULT		(0x1C64) */
+
+/* AGC_DSP_CTL bit 15 (HAGCCFG7 0x0F) */
+#define AW_PID_2049_AGC_DSP_CTL_START_BIT	(15)
+#define AW_PID_2049_AGC_DSP_CTL_BITS_LEN	(1)
+#define AW_PID_2049_AGC_DSP_CTL_MASK	\
+	(~(((1<<AW_PID_2049_AGC_DSP_CTL_BITS_LEN)-1) << AW_PID_2049_AGC_DSP_CTL_START_BIT))
+
+#define AW_PID_2049_AGC_DSP_CTL_DISABLE	(0)
+#define AW_PID_2049_AGC_DSP_CTL_DISABLE_VALUE	\
+	(AW_PID_2049_AGC_DSP_CTL_DISABLE << AW_PID_2049_AGC_DSP_CTL_START_BIT)
+
+#define AW_PID_2049_AGC_DSP_CTL_ENABLE	(1)
+#define AW_PID_2049_AGC_DSP_CTL_ENABLE_VALUE	\
+	(AW_PID_2049_AGC_DSP_CTL_ENABLE << AW_PID_2049_AGC_DSP_CTL_START_BIT)
+/* VDSEL bit 0 (I2SCFG3 0x12) */
+#define AW_PID_2049_VDSEL_START_BIT		(0)
+#define AW_PID_2049_VDSEL_BITS_LEN		(1)
+#define AW_PID_2049_VDSEL_MASK			\
+	(~(((1<<AW_PID_2049_VDSEL_BITS_LEN)-1) << AW_PID_2049_VDSEL_START_BIT))
+
+/* MEM_CLKSEL bit 3 (DBGCTRL 0x13) */
+#define AW_PID_2049_MEM_CLKSEL_START_BIT	(3)
+#define AW_PID_2049_MEM_CLKSEL_BITS_LEN	(1)
+#define AW_PID_2049_MEM_CLKSEL_MASK		\
+	(~(((1<<AW_PID_2049_MEM_CLKSEL_BITS_LEN)-1) << AW_PID_2049_MEM_CLKSEL_START_BIT))
+
+#define AW_PID_2049_MEM_CLKSEL_OSC_CLK	(0)
+#define AW_PID_2049_MEM_CLKSEL_OSC_CLK_VALUE	\
+	(AW_PID_2049_MEM_CLKSEL_OSC_CLK << AW_PID_2049_MEM_CLKSEL_START_BIT)
+
+#define AW_PID_2049_MEM_CLKSEL_DAP_HCLK	(1)
+#define AW_PID_2049_MEM_CLKSEL_DAP_HCLK_VALUE	\
+	(AW_PID_2049_MEM_CLKSEL_DAP_HCLK << AW_PID_2049_MEM_CLKSEL_START_BIT)
+
+/* HAGCST (0x20) detail */
+/* SPK_GAIN_ST bit 10:8 (HAGCST 0x20) */
+#define AW_PID_2049_SPK_GAIN_ST_START_BIT	(8)
+#define AW_PID_2049_SPK_GAIN_ST_BITS_LEN	(3)
+#define AW_PID_2049_SPK_GAIN_ST_MASK	\
+	(~(((1<<AW_PID_2049_SPK_GAIN_ST_BITS_LEN)-1) << AW_PID_2049_SPK_GAIN_ST_START_BIT))
+
+#define AW_PID_2049_SPK_GAIN_ST_4_AV	(0)
+#define AW_PID_2049_SPK_GAIN_ST_4_AV_VALUE	\
+	(AW_PID_2049_SPK_GAIN_ST_4_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT)
+
+#define AW_PID_2049_SPK_GAIN_ST_4P67_AV	(1)
+#define AW_PID_2049_SPK_GAIN_ST_4P67_AV_VALUE	\
+	(AW_PID_2049_SPK_GAIN_ST_4P67_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT)
+
+#define AW_PID_2049_SPK_GAIN_ST_6_AV	(2)
+#define AW_PID_2049_SPK_GAIN_ST_6_AV_VALUE	\
+	(AW_PID_2049_SPK_GAIN_ST_6_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT)
+
+#define AW_PID_2049_SPK_GAIN_ST_7_AV	(3)
+#define AW_PID_2049_SPK_GAIN_ST_7_AV_VALUE	\
+	(AW_PID_2049_SPK_GAIN_ST_7_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT)
+
+#define AW_PID_2049_SPK_GAIN_ST_12_AV	(4)
+#define AW_PID_2049_SPK_GAIN_ST_12_AV_VALUE	\
+	(AW_PID_2049_SPK_GAIN_ST_12_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT)
+
+#define AW_PID_2049_SPK_GAIN_ST_14_AV	(5)
+#define AW_PID_2049_SPK_GAIN_ST_14_AV_VALUE	\
+	(AW_PID_2049_SPK_GAIN_ST_14_AV << AW_PID_2049_SPK_GAIN_ST_START_BIT)
+
+#define AW_PID_2049_SPK_GAIN_ST_DEFAULT_VALUE	(5)
+#define AW_PID_2049_SPK_GAIN_ST_DEFAULT	\
+	(AW_PID_2049_SPK_GAIN_ST_DEFAULT_VALUE << AW_PID_2049_SPK_GAIN_ST_START_BIT)
+
+/* BSTVOUT_ST bit 5:0 (HAGCST 0x20) */
+#define AW_PID_2049_BSTVOUT_ST_START_BIT	(0)
+#define AW_PID_2049_BSTVOUT_ST_BITS_LEN	(6)
+#define AW_PID_2049_BSTVOUT_ST_MASK		\
+	(~(((1<<AW_PID_2049_BSTVOUT_ST_BITS_LEN)-1) << AW_PID_2049_BSTVOUT_ST_START_BIT))
+
+#define AW_PID_2049_BSTVOUT_ST_3P125V	(0)
+#define AW_PID_2049_BSTVOUT_ST_3P125V_VALUE	\
+	(AW_PID_2049_BSTVOUT_ST_3P125V << AW_PID_2049_BSTVOUT_ST_START_BIT)
+
+#define AW_PID_2049_BSTVOUT_ST_3P250V	(1)
+#define AW_PID_2049_BSTVOUT_ST_3P250V_VALUE	\
+	(AW_PID_2049_BSTVOUT_ST_3P250V << AW_PID_2049_BSTVOUT_ST_START_BIT)
+
+#define AW_PID_2049_BSTVOUT_ST_3P375V	(2)
+#define AW_PID_2049_BSTVOUT_ST_3P375V_VALUE	\
+	(AW_PID_2049_BSTVOUT_ST_3P375V << AW_PID_2049_BSTVOUT_ST_START_BIT)
+
+#define AW_PID_2049_BSTVOUT_ST_3P500V	(3)
+#define AW_PID_2049_BSTVOUT_ST_3P500V_VALUE	\
+	(AW_PID_2049_BSTVOUT_ST_3P500V << AW_PID_2049_BSTVOUT_ST_START_BIT)
+
+#define AW_PID_2049_BSTVOUT_ST_3P625V	(4)
+#define AW_PID_2049_BSTVOUT_ST_3P625V_VALUE	\
+	(AW_PID_2049_BSTVOUT_ST_3P625V << AW_PID_2049_BSTVOUT_ST_START_BIT)
+
+#define AW_PID_2049_BSTVOUT_ST_3P750V	(5)
+#define AW_PID_2049_BSTVOUT_ST_3P750V_VALUE	\
+	(AW_PID_2049_BSTVOUT_ST_3P750V << AW_PID_2049_BSTVOUT_ST_START_BIT)
+
+#define AW_PID_2049_BSTVOUT_ST_11P000V	(63)
+#define AW_PID_2049_BSTVOUT_ST_11P000V_VALUE	\
+	(AW_PID_2049_BSTVOUT_ST_11P000V << AW_PID_2049_BSTVOUT_ST_START_BIT)
+
+#define AW_PID_2049_BSTVOUT_ST_DEFAULT_VALUE	(0)
+#define AW_PID_2049_BSTVOUT_ST_DEFAULT	\
+	(AW_PID_2049_BSTVOUT_ST_DEFAULT_VALUE << AW_PID_2049_BSTVOUT_ST_START_BIT)
+
+/* default value of HAGCST (0x20) */
+/* #define AW_PID_2049_HAGCST_DEFAULT		(0x0500) */
+
+/* VBAT (0x21) detail */
+/* VBAT_DET bit 9:0 (VBAT 0x21) */
+#define AW_PID_2049_VBAT_DET_START_BIT	(0)
+#define AW_PID_2049_VBAT_DET_BITS_LEN	(10)
+#define AW_PID_2049_VBAT_DET_MASK		\
+	(~(((1<<AW_PID_2049_VBAT_DET_BITS_LEN)-1) << AW_PID_2049_VBAT_DET_START_BIT))
+
+#define AW_PID_2049_VBAT_DET_DEFAULT_VALUE	(0x263)
+#define AW_PID_2049_VBAT_DET_DEFAULT	\
+	(AW_PID_2049_VBAT_DET_DEFAULT_VALUE << AW_PID_2049_VBAT_DET_START_BIT)
+
+#define AW_PID_2049_VBAT_RANGE	(6025)
+#define AW_PID_2049_INT_10BIT	(1023)
+/* default value of VBAT (0x21) */
+/* #define AW_PID_2049_VBAT_DEFAULT		(0x0263) */
+
+/* TEMP (0x22) detail */
+/* TEMP_DET bit 9:0 (TEMP 0x22) */
+#define AW_PID_2049_TEMP_DET_START_BIT	(0)
+#define AW_PID_2049_TEMP_DET_BITS_LEN	(10)
+#define AW_PID_2049_TEMP_DET_MASK		\
+	(~(((1<<AW_PID_2049_TEMP_DET_BITS_LEN)-1) << AW_PID_2049_TEMP_DET_START_BIT))
+
+#define AW_PID_2049_TEMP_DET_MINUS_40	(0x3D8)
+#define AW_PID_2049_TEMP_DET_MINUS_40_VALUE	\
+	(AW_PID_2049_TEMP_DET_MINUS_40 << AW_PID_2049_TEMP_DET_START_BIT)
+
+#define AW_PID_2049_TEMP_DET_0			(0x00)
+#define AW_PID_2049_TEMP_DET_0_VALUE	\
+	(AW_PID_2049_TEMP_DET_0 << AW_PID_2049_TEMP_DET_START_BIT)
+
+#define AW_PID_2049_TEMP_DET_1			(0x01)
+#define AW_PID_2049_TEMP_DET_1_VALUE	\
+	(AW_PID_2049_TEMP_DET_1 << AW_PID_2049_TEMP_DET_START_BIT)
+
+#define AW_PID_2049_TEMP_DET_25			(0x19)
+#define AW_PID_2049_TEMP_DET_25_VALUE	\
+	(AW_PID_2049_TEMP_DET_25 << AW_PID_2049_TEMP_DET_START_BIT)
+
+#define AW_PID_2049_TEMP_DET_55			(0x37)
+#define AW_PID_2049_TEMP_DET_55_VALUE	\
+	(AW_PID_2049_TEMP_DET_55 << AW_PID_2049_TEMP_DET_START_BIT)
+
+#define AW_PID_2049_TEMP_DET_DEFAULT_VALUE	(0x019)
+#define AW_PID_2049_TEMP_DET_DEFAULT	\
+	(AW_PID_2049_TEMP_DET_DEFAULT_VALUE << AW_PID_2049_TEMP_DET_START_BIT)
+#define AW_PID_2049_TEMP_SIGN_MASK	(~(1 << 9))
+#define AW_PID_2049_TEMP_NEG_MASK	(0XFC00)
+
+/* default value of TEMP (0x22) */
+/* #define AW_PID_2049_TEMP_DEFAULT		(0x0019) */
+
+/* PVDD (0x23) detail */
+/* PVDD_DET bit 9:0 (PVDD 0x23) */
+#define AW_PID_2049_PVDD_DET_START_BIT	(0)
+#define AW_PID_2049_PVDD_DET_BITS_LEN	(10)
+#define AW_PID_2049_PVDD_DET_MASK		\
+	(~(((1<<AW_PID_2049_PVDD_DET_BITS_LEN)-1) << AW_PID_2049_PVDD_DET_START_BIT))
+
+#define AW_PID_2049_PVDD_DET_DEFAULT_VALUE	(0x263)
+#define AW_PID_2049_PVDD_DET_DEFAULT	\
+	(AW_PID_2049_PVDD_DET_DEFAULT_VALUE << AW_PID_2049_PVDD_DET_START_BIT)
+
+/* default value of PVDD (0x23) */
+/* #define AW_PID_2049_PVDD_DEFAULT		(0x0263) */
+
+/* BSTCTRL1 (0x60) detail */
+/* BST_RTH bit 13:8 (BSTCTRL1 0x60) */
+#define AW_PID_2049_BST_RTH_START_BIT	(8)
+#define AW_PID_2049_BST_RTH_BITS_LEN	(6)
+#define AW_PID_2049_BST_RTH_MASK		\
+	(~(((1<<AW_PID_2049_BST_RTH_BITS_LEN)-1) << AW_PID_2049_BST_RTH_START_BIT))
+
+#define AW_PID_2049_BST_RTH_DEFAULT_VALUE	(4)
+#define AW_PID_2049_BST_RTH_DEFAULT		\
+	(AW_PID_2049_BST_RTH_DEFAULT_VALUE << AW_PID_2049_BST_RTH_START_BIT)
+
+/* BST_ATH bit 5:0 (BSTCTRL1 0x60) */
+#define AW_PID_2049_BST_ATH_START_BIT	(0)
+#define AW_PID_2049_BST_ATH_BITS_LEN	(6)
+#define AW_PID_2049_BST_ATH_MASK		\
+	(~(((1<<AW_PID_2049_BST_ATH_BITS_LEN)-1) << AW_PID_2049_BST_ATH_START_BIT))
+
+#define AW_PID_2049_BST_ATH_DEFAULT_VALUE	(2)
+#define AW_PID_2049_BST_ATH_DEFAULT		\
+	(AW_PID_2049_BST_ATH_DEFAULT_VALUE << AW_PID_2049_BST_ATH_START_BIT)
+
+/* default value of BSTCTRL1 (0x60) */
+/* #define AW_PID_2049_BSTCTRL1_DEFAULT		(0x0402) */
+
+/* BSTCTRL2 (0x61) detail */
+/* BST_MODE bit 14:12 (BSTCTRL2 0x61) */
+#define AW_PID_2049_BST_MODE_START_BIT	(12)
+#define AW_PID_2049_BST_MODE_BITS_LEN	(3)
+#define AW_PID_2049_BST_MODE_MASK		\
+	(~(((1<<AW_PID_2049_BST_MODE_BITS_LEN)-1) << AW_PID_2049_BST_MODE_START_BIT))
+
+#define AW_PID_2049_BST_MODE_TRANSPARENT	(0)
+#define AW_PID_2049_BST_MODE_TRANSPARENT_VALUE	\
+	(AW_PID_2049_BST_MODE_TRANSPARENT << AW_PID_2049_BST_MODE_START_BIT)
+
+#define AW_PID_2049_BST_MODE_FORCE_BOOST	(1)
+#define AW_PID_2049_BST_MODE_FORCE_BOOST_VALUE	\
+	(AW_PID_2049_BST_MODE_FORCE_BOOST << AW_PID_2049_BST_MODE_START_BIT)
+
+#define AW_PID_2049_BST_MODE_SMART_BOOST1	(5)
+#define AW_PID_2049_BST_MODE_SMART_BOOST1_VALUE	\
+	(AW_PID_2049_BST_MODE_SMART_BOOST1 << AW_PID_2049_BST_MODE_START_BIT)
+
+#define AW_PID_2049_BST_MODE_SMART_BOOST2	(6)
+#define AW_PID_2049_BST_MODE_SMART_BOOST2_VALUE	\
+	(AW_PID_2049_BST_MODE_SMART_BOOST2 << AW_PID_2049_BST_MODE_START_BIT)
+
+#define AW_PID_2049_BST_MODE_DEFAULT_VALUE	(0x6)
+#define AW_PID_2049_BST_MODE_DEFAULT	\
+	(AW_PID_2049_BST_MODE_DEFAULT_VALUE << AW_PID_2049_BST_MODE_START_BIT)
+
+/* WDT_CNT bit 7:0 (WDT 0x42) */
+#define AW_PID_2049_WDT_CNT_START_BIT	(0)
+#define AW_PID_2049_WDT_CNT_BITS_LEN	(8)
+#define AW_PID_2049_WDT_CNT_MASK		\
+	(~(((1<<AW_PID_2049_WDT_CNT_BITS_LEN)-1) << AW_PID_2049_WDT_CNT_START_BIT))
+
+/* BST_TDEG bit 11:8 (BSTCTRL2 0x61) */
+#define AW_PID_2049_BST_TDEG_START_BIT	(8)
+#define AW_PID_2049_BST_TDEG_BITS_LEN	(4)
+#define AW_PID_2049_BST_TDEG_MASK		\
+	(~(((1<<AW_PID_2049_BST_TDEG_BITS_LEN)-1) << AW_PID_2049_BST_TDEG_START_BIT))
+
+#define AW_PID_2049_BST_TDEG_0P50_MS	(0)
+#define AW_PID_2049_BST_TDEG_0P50_MS_VALUE	\
+	(AW_PID_2049_BST_TDEG_0P50_MS << AW_PID_2049_BST_TDEG_START_BIT)
+
+#define AW_PID_2049_BST_TDEG_1P00_MS	(1)
+#define AW_PID_2049_BST_TDEG_1P00_MS_VALUE	\
+	(AW_PID_2049_BST_TDEG_1P00_MS << AW_PID_2049_BST_TDEG_START_BIT)
+
+#define AW_PID_2049_BST_TDEG_2P00_MS	(2)
+#define AW_PID_2049_BST_TDEG_2P00_MS_VALUE	\
+	(AW_PID_2049_BST_TDEG_2P00_MS << AW_PID_2049_BST_TDEG_START_BIT)
+
+#define AW_PID_2049_BST_TDEG_4P00_MS	(3)
+#define AW_PID_2049_BST_TDEG_4P00_MS_VALUE	\
+	(AW_PID_2049_BST_TDEG_4P00_MS << AW_PID_2049_BST_TDEG_START_BIT)
+
+#define AW_PID_2049_BST_TDEG_8P00_MS	(4)
+#define AW_PID_2049_BST_TDEG_8P00_MS_VALUE	\
+	(AW_PID_2049_BST_TDEG_8P00_MS << AW_PID_2049_BST_TDEG_START_BIT)
+
+#define AW_PID_2049_BST_TDEG_10P7_MS	(5)
+#define AW_PID_2049_BST_TDEG_10P7_MS_VALUE	\
+	(AW_PID_2049_BST_TDEG_10P7_MS << AW_PID_2049_BST_TDEG_START_BIT)
+
+/* ReAbs bit 3 (ASR1 0x45) */
+#define AW_PID_2049_ReAbs_START_BIT		(3)
+#define AW_PID_2049_ReAbs_BITS_LEN		(1)
+#define AW_PID_2049_ReAbs_MASK			\
+	(~(((1<<AW_PID_2049_ReAbs_BITS_LEN)-1) << AW_PID_2049_ReAbs_START_BIT))
+
+#define AW_PID_2049_BST_TDEG_13P3_MS	(6)
+#define AW_PID_2049_BST_TDEG_13P3_MS_VALUE	\
+	(AW_PID_2049_BST_TDEG_13P3_MS << AW_PID_2049_BST_TDEG_START_BIT)
+
+/* DSP_VOL bit 15:8 (DSPCFG 0x47) */
+#define AW_PID_2049_DSP_VOL_START_BIT	(8)
+#define AW_PID_2049_DSP_VOL_BITS_LEN	(8)
+#define AW_PID_2049_DSP_VOL_MASK		\
+	(~(((1<<AW_PID_2049_DSP_VOL_BITS_LEN)-1) << AW_PID_2049_DSP_VOL_START_BIT))
+
+#define AW_PID_2049_DSP_VOL_MUTE			(0XFF00)
+#define AW_PID_2049_DSP_VOL_NOISE_ST		(0X1800)
+
+#define AW_PID_2049_BST_TDEG_16P0_MS	(7)
+#define AW_PID_2049_BST_TDEG_16P0_MS_VALUE	\
+	(AW_PID_2049_BST_TDEG_16P0_MS << AW_PID_2049_BST_TDEG_START_BIT)
+
+#define AW_PID_2049_BST_TDEG_18P6_MS	(8)
+#define AW_PID_2049_BST_TDEG_18P6_MS_VALUE	\
+	(AW_PID_2049_BST_TDEG_18P6_MS << AW_PID_2049_BST_TDEG_START_BIT)
+
+#define AW_PID_2049_BST_TDEG_21P3_MS	(9)
+#define AW_PID_2049_BST_TDEG_21P3_MS_VALUE	\
+	(AW_PID_2049_BST_TDEG_21P3_MS << AW_PID_2049_BST_TDEG_START_BIT)
+
+#define AW_PID_2049_BST_TDEG_24P0_MS	(10)
+#define AW_PID_2049_BST_TDEG_24P0_MS_VALUE	\
+	(AW_PID_2049_BST_TDEG_24P0_MS << AW_PID_2049_BST_TDEG_START_BIT)
+
+#define AW_PID_2049_BST_TDEG_32P0_MS	(11)
+#define AW_PID_2049_BST_TDEG_32P0_MS_VALUE	\
+	(AW_PID_2049_BST_TDEG_32P0_MS << AW_PID_2049_BST_TDEG_START_BIT)
+
+#define AW_PID_2049_BST_TDEG_64P0_MS	(12)
+#define AW_PID_2049_BST_TDEG_64P0_MS_VALUE	\
+	(AW_PID_2049_BST_TDEG_64P0_MS << AW_PID_2049_BST_TDEG_START_BIT)
+
+#define AW_PID_2049_BST_TDEG_128_MS		(13)
+#define AW_PID_2049_BST_TDEG_128_MS_VALUE	\
+	(AW_PID_2049_BST_TDEG_128_MS << AW_PID_2049_BST_TDEG_START_BIT)
+
+#define AW_PID_2049_BST_TDEG_256_MS		(14)
+#define AW_PID_2049_BST_TDEG_256_MS_VALUE	\
+	(AW_PID_2049_BST_TDEG_256_MS << AW_PID_2049_BST_TDEG_START_BIT)
+
+#define AW_PID_2049_BST_TDEG_1200_MS	(15)
+#define AW_PID_2049_BST_TDEG_1200_MS_VALUE	\
+	(AW_PID_2049_BST_TDEG_1200_MS << AW_PID_2049_BST_TDEG_START_BIT)
+
+#define AW_PID_2049_BST_TDEG_DEFAULT_VALUE	(11)
+#define AW_PID_2049_BST_TDEG_DEFAULT	\
+	(AW_PID_2049_BST_TDEG_DEFAULT_VALUE << AW_PID_2049_BST_TDEG_START_BIT)
+
+/* VOUT_VREFSET bit 5:0 (BSTCTRL2 0x61) */
+/* CCO_MUX bit 14 (PLLCTRL1 0x52) */
+#define AW_PID_2049_CCO_MUX_START_BIT	(14)
+#define AW_PID_2049_CCO_MUX_BITS_LEN	(1)
+#define AW_PID_2049_CCO_MUX_MASK		\
+	(~(((1<<AW_PID_2049_CCO_MUX_BITS_LEN)-1) << AW_PID_2049_CCO_MUX_START_BIT))
+
+#define AW_PID_2049_CCO_MUX_DIVIDED		(0)
+#define AW_PID_2049_CCO_MUX_DIVIDED_VALUE	\
+	(AW_PID_2049_CCO_MUX_DIVIDED << AW_PID_2049_CCO_MUX_START_BIT)
+
+#define AW_PID_2049_CCO_MUX_BYPASS		(1)
+#define AW_PID_2049_CCO_MUX_BYPASS_VALUE	\
+	(AW_PID_2049_CCO_MUX_BYPASS << AW_PID_2049_CCO_MUX_START_BIT)
+
+#define AW_PID_2049_VOUT_VREFSET_START_BIT	(0)
+#define AW_PID_2049_VOUT_VREFSET_BITS_LEN	(6)
+#define AW_PID_2049_VOUT_VREFSET_MASK	\
+	(~(((1<<AW_PID_2049_VOUT_VREFSET_BITS_LEN)-1) << AW_PID_2049_VOUT_VREFSET_START_BIT))
+
+#define AW_PID_2049_VOUT_VREFSET_3P125V	(0)
+#define AW_PID_2049_VOUT_VREFSET_3P125V_VALUE	\
+	(AW_PID_2049_VOUT_VREFSET_3P125V << AW_PID_2049_VOUT_VREFSET_START_BIT)
+
+#define AW_PID_2049_VOUT_VREFSET_3P250V	(1)
+#define AW_PID_2049_VOUT_VREFSET_3P250V_VALUE	\
+	(AW_PID_2049_VOUT_VREFSET_3P250V << AW_PID_2049_VOUT_VREFSET_START_BIT)
+
+#define AW_PID_2049_VOUT_VREFSET_3P375V	(2)
+#define AW_PID_2049_VOUT_VREFSET_3P375V_VALUE	\
+	(AW_PID_2049_VOUT_VREFSET_3P375V << AW_PID_2049_VOUT_VREFSET_START_BIT)
+
+#define AW_PID_2049_VOUT_VREFSET_3P500V	(3)
+#define AW_PID_2049_VOUT_VREFSET_3P500V_VALUE	\
+	(AW_PID_2049_VOUT_VREFSET_3P500V << AW_PID_2049_VOUT_VREFSET_START_BIT)
+
+#define AW_PID_2049_VOUT_VREFSET_3P625V	(4)
+#define AW_PID_2049_VOUT_VREFSET_3P625V_VALUE	\
+	(AW_PID_2049_VOUT_VREFSET_3P625V << AW_PID_2049_VOUT_VREFSET_START_BIT)
+
+#define AW_PID_2049_VOUT_VREFSET_3P750V	(5)
+#define AW_PID_2049_VOUT_VREFSET_3P750V_VALUE	\
+	(AW_PID_2049_VOUT_VREFSET_3P750V << AW_PID_2049_VOUT_VREFSET_START_BIT)
+
+#define AW_PID_2049_VOUT_VREFSET_11P000V	(63)
+#define AW_PID_2049_VOUT_VREFSET_11P000V_VALUE	\
+	(AW_PID_2049_VOUT_VREFSET_11P000V << AW_PID_2049_VOUT_VREFSET_START_BIT)
+
+#define AW_PID_2049_VOUT_VREFSET_DEFAULT_VALUE	(0x33)
+#define AW_PID_2049_VOUT_VREFSET_DEFAULT	\
+	(AW_PID_2049_VOUT_VREFSET_DEFAULT_VALUE << AW_PID_2049_VOUT_VREFSET_START_BIT)
+
+/* default value of BSTCTRL2 (0x61) */
+/* #define AW_PID_2049_BSTCTRL2_DEFAULT		(0x6B33) */
+
+/* detail information of registers end */
+
+/* EF_VSN_GESLP bit 9:0 (EFRH 0x78) */
+#define AW_PID_2049_EF_VSN_GESLP_START_BIT	(0)
+#define AW_PID_2049_EF_VSN_GESLP_BITS_LEN	(10)
+#define AW_PID_2049_EF_VSN_GESLP_MASK	\
+	(~(((1<<AW_PID_2049_EF_VSN_GESLP_BITS_LEN)-1) << AW_PID_2049_EF_VSN_GESLP_START_BIT))
+
+#define AW_PID_2049_EF_VSN_GESLP_SIGN_MASK		(~(1 << 9))
+#define AW_PID_2049_EF_VSN_GESLP_SIGN_NEG		(0xfe00)
+/* EF_ISN_GESLP bit 9:0 (EFRM2 0x79) */
+#define AW_PID_2049_EF_ISN_GESLP_START_BIT	(0)
+#define AW_PID_2049_EF_ISN_GESLP_BITS_LEN	(10)
+#define AW_PID_2049_EF_ISN_GESLP_MASK	\
+	(~(((1<<AW_PID_2049_EF_ISN_GESLP_BITS_LEN)-1) << AW_PID_2049_EF_ISN_GESLP_START_BIT))
+
+#define AW_PID_2049_EF_ISN_GESLP_SIGN_MASK		(~(1 << 9))
+#define AW_PID_2049_EF_ISN_GESLP_SIGN_NEG		(0xfe00)
+/*
+ * Vcalb
+ */
+
+#define AW_PID_2049_CABL_BASE_VALUE			(1000)
+#define AW_PID_2049_ICABLK_FACTOR			(1)
+#define AW_PID_2049_VCABLK_FACTOR			(1)
+#define AW_PID_2049_VCAL_FACTOR				(1 << 12)
+#define AW_PID_2049_VSCAL_FACTOR			(16500)
+#define AW_PID_2049_ISCAL_FACTOR			(3667)
+#define AW_PID_2049_EF_VSENSE_GAIN_SHIFT		(0)
+
+#define AW_PID_2049_VCABLK_FACTOR_DAC			(2)
+#define AW_PID_2049_VSCAL_FACTOR_DAC			(11790)
+#define AW_PID_2049_EF_DAC_GESLP_SHIFT			(10)
+#define AW_PID_2049_EF_DAC_GESLP_SIGN_MASK		(1 << 5)
+#define AW_PID_2049_EF_DAC_GESLP_SIGN_NEG		(0xffc0)
+
+#define AW_PID_2049_VCALB_ADJ_FACTOR			(12)
+
+/*
+ * AW883XX DSP
+ */
+#define AW_PID_2049_DSP_CFG_ADDR			(0x9C80)
+#define AW_PID_2049_DSP_FW_ADDR				(0x8C00)
+
+#define AW_PID_2049_DSP_REG_RESULT_F0			(0x9C58)
+#define AW_PID_2049_DSP_F0_SHIFT			(1)
+
+#define AW_PID_2049_DSP_REG_CALRE			(0x9C5A)
+#define AW_PID_2049_DSP_REG_CALRE_SHIFT			(10)
+#define AW_PID_2049_DSP_REG_RESULT_Q			(0x9C5C)
+#define AW_PID_2049_DSP_Q_SHIFT				(11)
+
+#define AW_PID_2049_DSP_REG_VMAX			(0x9C94)
+
+
+#define AW_PID_2049_DSP_REG_CFG_MBMEC_GLBCFG		(0x9CE2)
+/* bit 0 */
+#define AW_PID_2049_DSP_MONITOR_MASK			(~(1 << 0))
+#define AW_PID_2049_DSP_MONITOR_ENABLE			(1 << 0)
+#define AW_PID_2049_DSP_MONITOR_DISABLE			(0 << 0)
+/*bit 4*/
+#define AW_PID_2049_DSP_REG_NOISE_MASK			(~(1 << 4))
+
+#define AW_PID_2049_DSP_TEMP_PEAK_MASK			(~(1 << 4))
+#define AW_PID_2049_DSP_TEMP_SEL_FLAG			(~(1 << 14))
+
+#define AW_PID_2049_DSP_REG_CFG_MBMEC_ACTAMPTH		(0x9CE4)/*32bit*/
+#define AW_PID_2049_DSP_REG_CFG_MBMEC_NOISEAMPTH	(0x9CE6)/*32bit*/
+#define AW_PID_2049_DSP_REG_VCALB			(0x9CF7)
+
+#define AW_PID_2049_DSP_REG_CFG_ADPZ_RE			(0x9D00)/*32bit*/
+#define AW_PID_2049_DSP_RE_SHIFT			(12)
+
+#define AW_PID_2049_DSP_REG_CFG_ADPZ_RA			(0x9D02)/*32bit*/
+
+#define AW_PID_2049_DSP_REG_CFG_ADPZ_USTEPN		(0x9D08)
+
+
+#define AW_PID_2049_DSP_REG_CRC_ADDR			(0x9F42)/*32bit*/
+#define AW_PID_2049_DSP_REG_CFGF0_FS			(0x9F44)/*32bit*/
+#define AW_PID_2049_DSP_REG_CFG_RE_ALPHA		(0x9F47)
+#define AW_PID_2049_DSP_REG_TEMP_ADDR			(0x9C5D)
+#define AW_PID_2049_DSP_REG_TEMP_SWITCH			(0x9D71)/*16bit*/
+#define AW_PID_2049_DSP_CALI_F0_DELAY			(0x9CFD)
+#define AW_PID_2049_DSP_CFG_ADPZ_T0			(0x9D11)/*16bit*/
+#define AW_PID_2049_DSP_CFG_ADPZ_COILALPHA		(0x9D0F)/*16bit*/
+#define AW_PID_2049_DSP_ST_S1				(0x8180)
+#define AW_PID_2049_DSP_ST_E1				(0x83FD)
+#define AW_PID_2049_DSP_ST_S2				(0x9C00)
+#define AW_PID_2049_DSP_ST_E2				(0x9C5D)
+
+#endif  /* #ifndef  __AW_PID_2049_REG_H__ */
-- 
2.38.1

[PATCH V6 5/5] ASoC: dt-bindings: Add schema for "awinic,aw883xx"

[wangweidong.a]

From: Weidong Wang <wangweidong.a@awinic.com>

Add a DT schema for describing Awinic AW883xx audio amplifiers. They are
controlled using I2C.
Signed-off-by: Weidong Wang <wangweidong.a@awinic.com>
---
 .../bindings/sound/awinic,aw883xx.yaml        | 49 +++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml

diff --git a/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml b/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml
new file mode 100644
index 000000000000..b72c9177ebb7
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/awinic,aw883xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Awinic AW883xx Smart Audio Amplifier
+
+maintainers:
+  - Stephan Gerhold <stephan@gerhold.net>
+
+description:
+  The Awinic AW883XX is an I2S/TDM input, high efficiency
+  digital Smart K audio amplifier with an integrated 10.25V
+  smart boost convert.
+
+allOf:
+  - $ref: name-prefix.yaml#
+
+properties:
+  compatible:
+    const: awinic,aw883xx_smartpa
+
+  reg:
+    maxItems: 1
+
+  reset-gpios:
+    maxItems: 1
+
+  sound-name-prefix: true
+
+required:
+  - compatible
+  - reg
+  - reset-gpios
+
+additionalProperties: false
+
+examples:
+  - |
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        audio-codec@34 {
+            compatible = "awinic,aw883xx_smartpa";
+            reg = <0x34>;
+            reset-gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+        };
+    };
-- 
2.38.1

Re: [PATCH V6 1/5] ASoC: codecs: Add i2c and codec registration for aw883xx and their associated operation functions

[Amadeusz Sławiński]

On 12/8/2022 1:23 PM, wangweidong.a@awinic.com wrote:
> From: Weidong Wang <wangweidong.a@awinic.com>
> 
> The Awinic AW883XX is an I2S/TDM input, high efficiency
> digital Smart K audio amplifier with an integrated 10.25V
> smart boost convert
> 
> Signed-off-by: Nick Li <liweilei@awinic.com>
> Signed-off-by: Bruce zhao <zhaolei@awinic.com>
> Signed-off-by: Weidong Wang <wangweidong.a@awinic.com>
> ---
>   sound/soc/codecs/aw883xx/aw883xx.c | 909 +++++++++++++++++++++++++++++
>   sound/soc/codecs/aw883xx/aw883xx.h |  81 +++
>   2 files changed, 990 insertions(+)
>   create mode 100644 sound/soc/codecs/aw883xx/aw883xx.c
>   create mode 100644 sound/soc/codecs/aw883xx/aw883xx.h
> 
> diff --git a/sound/soc/codecs/aw883xx/aw883xx.c b/sound/soc/codecs/aw883xx/aw883xx.c
> new file mode 100644
> index 000000000000..f82e6d8c71a7
> --- /dev/null
> +++ b/sound/soc/codecs/aw883xx/aw883xx.c
> @@ -0,0 +1,909 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * aw883xx.c --  ALSA Soc AW883XX codec support

Soc -> SoC

> + *
> + * Copyright (c) 2022 AWINIC Technology CO., LTD
> + *
> + * Author: Bruce zhao <zhaolei@awinic.com>
> + */
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/debugfs.h>
> +#include <linux/firmware.h>
> +#include <linux/hrtimer.h>
> +#include <linux/i2c.h>
> +#include <linux/input.h>
> +#include <linux/module.h>
> +#include <linux/of_gpio.h>
> +#include <linux/regmap.h>
> +#include <linux/syscalls.h>
> +#include <linux/timer.h>
> +#include <linux/uaccess.h>
> +#include <linux/version.h>
> +#include <linux/vmalloc.h>
> +#include <linux/workqueue.h>

Are all those headers really needed? Just picking few, for example 
debugfs.h, version.h and vmalloc.h seems unnecessary to me, and I 
suspect few more can be removed.

> +#include <sound/core.h>
> +#include <sound/pcm.h>
> +#include <sound/pcm_params.h>
> +#include <sound/soc.h>
> +#include <sound/tlv.h>
> +#include "aw883xx_pid_2049_reg.h"
> +#include "aw883xx.h"
> +#include "aw883xx_bin_parse.h"
> +#include "aw883xx_device.h"
> +
> +static const struct regmap_config aw883xx_remap_config = {
> +	.val_bits = 16,
> +	.reg_bits = 8,
> +	.max_register = AW_PID_2049_REG_MAX - 1,
> +};
> +
> +/*
> + * aw883xx dsp write/read
> + */
> +static int aw883xx_dsp_write_16bit(struct aw883xx *aw883xx,
> +		unsigned short dsp_addr, unsigned int dsp_data)
> +{
> +	int ret;
> +	struct aw_dsp_mem_desc *desc = &aw883xx->aw_pa->dsp_mem_desc;
> +
> +	ret = regmap_write(aw883xx->regmap, desc->dsp_madd_reg, dsp_addr);
> +	if (ret < 0) {
> +		dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret);
> +		return ret;
> +	}
> +
> +	ret = regmap_write(aw883xx->regmap, desc->dsp_mdat_reg, (u16)dsp_data);
> +	if (ret < 0) {
> +		dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int aw883xx_dsp_write_32bit(struct aw883xx *aw883xx,
> +		unsigned short dsp_addr, unsigned int dsp_data)
> +{
> +	int ret;
> +	u16 temp_data = 0;
> +	struct aw_dsp_mem_desc *desc = &aw883xx->aw_pa->dsp_mem_desc;
> +
> +	ret = regmap_write(aw883xx->regmap, desc->dsp_madd_reg, dsp_addr);
> +	if (ret < 0) {
> +		dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret);
> +		return ret;
> +	}
> +
> +	temp_data = dsp_data & AW_DSP_16_DATA_MASK;
> +	ret = regmap_write(aw883xx->regmap, desc->dsp_mdat_reg, temp_data);
> +	if (ret < 0) {
> +		dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret);
> +		return ret;
> +	}
> +
> +	temp_data = dsp_data >> 16;
> +	ret = regmap_write(aw883xx->regmap, desc->dsp_mdat_reg, temp_data);
> +	if (ret < 0) {
> +		dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +/*
> + * aw883xx clear dsp chip select state
> + */
> +static void aw883xx_clear_dsp_sel_st(struct aw883xx *aw883xx)
> +{
> +	unsigned int reg_value;
> +	u8 reg = aw883xx->aw_pa->soft_rst.reg;
> +
> +	regmap_read(aw883xx->regmap, reg, &reg_value);
> +}

Is it enough to just read register to clear it?

> +
> +int aw883xx_dsp_write(struct aw883xx *aw883xx,
> +		unsigned short dsp_addr, unsigned int dsp_data, unsigned char data_type)
> +{
> +	int ret = -1;


No need to set "-1" value here, as following switch always sets ret and 
-1 == -EPERM, which may lead to some confusion if something is changed 
later and ret is returned. If you want to set it to anything, just set 
it to -EINVAL.

There is few more places in the patch, where ret is initialized to -1 
only to be overwritten later, I won't mark them all, but it seems weird 
to me and should probably be fixed.

> +
> +	mutex_lock(&aw883xx->dsp_lock);
> +	switch (data_type) {
> +	case AW_DSP_16_DATA:
> +		ret = aw883xx_dsp_write_16bit(aw883xx, dsp_addr, dsp_data);
> +		if (ret < 0)
> +			dev_err(aw883xx->dev, "write dsp_addr[0x%04x] 16 bit dsp_data[%04x] failed",
> +					(u32)dsp_addr, dsp_data);
> +		break;
> +	case AW_DSP_32_DATA:
> +		ret =  aw883xx_dsp_write_32bit(aw883xx, dsp_addr, dsp_data);

remove double space after '='

> +		if (ret < 0)
> +			dev_err(aw883xx->dev, "write dsp_addr[0x%04x] 32 bit dsp_data[%08x] failed",
> +					(u32)dsp_addr, dsp_data);
> +		break;
> +	default:
> +		dev_err(aw883xx->dev, "data type[%d] unsupported", data_type);
> +		ret = -EINVAL;
> +		break;
> +	}
> +
> +	aw883xx_clear_dsp_sel_st(aw883xx);
> +	mutex_unlock(&aw883xx->dsp_lock);
> +	return ret;
> +}
> +

(...)

> diff --git a/sound/soc/codecs/aw883xx/aw883xx.h b/sound/soc/codecs/aw883xx/aw883xx.h
> new file mode 100644
> index 000000000000..209851cae7ef
> --- /dev/null
> +++ b/sound/soc/codecs/aw883xx/aw883xx.h
> @@ -0,0 +1,81 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * aw883xx.c --  ALSA Soc AW883XX codec support

Soc -> SoC

> + *
> + * Copyright (c) 2022 AWINIC Technology CO., LTD
> + *
> + * Author: Bruce zhao <zhaolei@awinic.com>
> + */
> +
> +#ifndef __AW883XX_H__
> +#define __AW883XX_H__
> +
> +#include <linux/version.h>

This header should be unnecessary

> +#include <sound/control.h>
> +#include <sound/soc.h>
> +#include "aw883xx_data_type.h"
> +
> +#define AW_CHIP_ID_REG			(0x00)
> +#define AW_START_RETRIES			(5)
> +#define AW_START_WORK_DELAY_MS	(0)
> +
> +#define AW_DSP_16_DATA_MASK	(0x0000ffff)
> +
> +#define AW_I2C_NAME "aw883xx_smartpa"
> +
> +#define AW_RATES (SNDRV_PCM_RATE_8000_48000 | \
> +			SNDRV_PCM_RATE_96000)
> +#define AW_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
> +			SNDRV_PCM_FMTBIT_S24_LE | \
> +			SNDRV_PCM_FMTBIT_S32_LE)
> +#define AW_REQUEST_FW_RETRIES		5	/* 5 times */

Unnecessary comment

> +#define AW_SYNC_LOAD
> +
> +#define FADE_TIME_MAX 100000
> +#define FADE_TIME_MIN 0
> +
> +#define AW_PROFILE_EXT(xname, profile_info, profile_get, profile_set) \
> +{ \
> +	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
> +	.name = xname, \
> +	.info = profile_info, \
> +	.get = profile_get, \
> +	.put = profile_set, \
> +}
> +
> +enum {
> +	AW_SYNC_START = 0,
> +	AW_ASYNC_START,
> +};
> +
> +enum {
> +	AW883XX_STREAM_CLOSE = 0,
> +	AW883XX_STREAM_OPEN,
> +};
> +
> +struct aw883xx {
> +	struct i2c_client *i2c;
> +	struct device *dev;
> +	struct mutex lock;
> +	struct mutex dsp_lock;
> +	struct snd_soc_component *codec;
> +	struct aw_device *aw_pa;
> +	struct gpio_desc *reset_gpio;
> +	unsigned char phase_sync;	/*phase sync*/

Also unnecessary comment

> +	bool allow_pw;
> +	u8 pstream;
> +	struct workqueue_struct *work_queue;
> +	struct delayed_work start_work;
> +	u16 chip_id;
> +	struct regmap *regmap;
> +	struct aw_container *aw_cfg;
> +};
> +
> +int aw883xx_init(struct aw883xx *aw883xx);
> +
> +int aw883xx_dsp_write(struct aw883xx *aw883xx,
> +		unsigned short dsp_addr, unsigned int dsp_data, unsigned char data_type);
> +int aw883xx_dsp_read(struct aw883xx *aw883xx,
> +		unsigned short dsp_addr, unsigned int *dsp_data, unsigned char data_type);
> +
> +#endif

Re: [PATCH V6 2/5] ASoC: codecs: Implementation of aw883xx configuration file parsing function

[Amadeusz Sławiński]

On 12/8/2022 1:23 PM, wangweidong.a@awinic.com wrote:
> From: Weidong Wang <wangweidong.a@awinic.com>
> 
> The Awinic AW883XX is an I2S/TDM input, high efficiency
> digital Smart K audio amplifier with an integrated 10.25V
> smart boost convert
> 
> Signed-off-by: Nick Li <liweilei@awinic.com>
> Signed-off-by: Bruce zhao <zhaolei@awinic.com>
> Signed-off-by: Weidong Wang <wangweidong.a@awinic.com>
> ---
>   sound/soc/codecs/aw883xx/aw883xx_bin_parse.c | 1324 ++++++++++++++++++
>   sound/soc/codecs/aw883xx/aw883xx_bin_parse.h |  149 ++
>   2 files changed, 1473 insertions(+)
>   create mode 100644 sound/soc/codecs/aw883xx/aw883xx_bin_parse.c
>   create mode 100644 sound/soc/codecs/aw883xx/aw883xx_bin_parse.h
> 
> diff --git a/sound/soc/codecs/aw883xx/aw883xx_bin_parse.c b/sound/soc/codecs/aw883xx/aw883xx_bin_parse.c
> new file mode 100644
> index 000000000000..f3d9b8a9fdf2
> --- /dev/null
> +++ b/sound/soc/codecs/aw883xx/aw883xx_bin_parse.c
> @@ -0,0 +1,1324 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * aw_bin_parse.c  -- ALSA Soc AW883XX codec support

Soc -> SoC

> + *
> + * Copyright (c) 2022 AWINIC Technology CO., LTD
> + */
> +
> +#include <linux/cdev.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/debugfs.h>
> +#include <linux/firmware.h>
> +#include <linux/hrtimer.h>
> +#include <linux/input.h>
> +#include <linux/i2c.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/list.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/miscdevice.h>
> +#include <linux/of_gpio.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +#include <linux/string.h>
> +#include <linux/timer.h>
> +#include <linux/uaccess.h>
> +#include <linux/version.h>
> +#include <linux/workqueue.h>
> +#include "aw883xx_bin_parse.h"
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +#include <linux/swab.h>
> +#include <linux/device.h>
> +#include <linux/regmap.h>
> +#include <linux/fs.h>
> +#include <linux/list.h>
> +#include <linux/wait.h>

Same as on patch 1, there seems to be quite a few unnecessary headers, 
and this one even has duplicates.

> +
> +static char *profile_name[AW_PROFILE_MAX] = {
> +	"Music", "Voice", "Voip", "Ringtone",
> +	"Ringtone_hs", "Lowpower", "Bypass",
> +	"Mmi", "Fm", "Notification", "Receiver"
> +};
> +
> +static int aw_parse_bin_header_1_0_0(struct aw_bin *bin);
> +
> +/*
> + * Interface function
> + *
> + * return value:
> + *       value = 0 :success;
> + *       value = -1 :check bin header version
> + *       value = -2 :check bin data type
> + *       value = -3 :check sum or check bin data len error
> + *       value = -4 :check data version
> + *       value = -5 :check register num
> + *       value = -6 :check dsp reg num
> + *       value = -7 :check soc app num
> + *       value = -8 :bin is NULL point
> + *
> + */
> +
> +/*
> + * check sum data
> + */
> +static int aw_check_sum(struct aw_bin *bin, int bin_num)
> +{
> +	unsigned int i = 0;
> +	unsigned int sum_data = 0;
> +	unsigned int check_sum = 0;
> +	unsigned char *p_check_sum = NULL;
> +
> +	p_check_sum = &(bin->info.data[(bin->header_info[bin_num].valid_data_addr -
> +						bin->header_info[bin_num].header_len)]);
> +
> +	pr_debug("aw_bin_parse p_check_sum = %p\n", p_check_sum);
> +
> +	check_sum = le32_to_cpup((void *)p_check_sum);
> +
> +	for (i = 4; i < bin->header_info[bin_num].bin_data_len +
> +					bin->header_info[bin_num].header_len; i++) {
> +		sum_data += *(p_check_sum + i);
> +	}
> +	pr_debug("aw_bin_parse bin_num = %d, check_sum = 0x%x, sum_data = 0x%x\n",
> +						bin_num, check_sum, sum_data);
> +	if (sum_data != check_sum) {
> +		p_check_sum = NULL;
No need to assign NULL to pointer?

> +		pr_err("%s. CheckSum Fail.bin_num=%d, CheckSum:0x%x, SumData:0x%x",
> +				__func__, bin_num, check_sum, sum_data);
> +		return -BIN_DATA_LEN_ERR;

Any reason to invent your own error codes, I went through few call paths 
and you don't seem to use them anywhere, might as well return -EINVAL?

> +	}
> +	p_check_sum = NULL;

Same here, no need to set this to NULL?

> +
> +	return 0;
> +}
> +
> +static int aw_check_data_version(struct aw_bin *bin, int bin_num)
> +{
> +	if (bin->header_info[bin_num].bin_data_ver < DATA_VERSION_V1 ||
> +		bin->header_info[bin_num].bin_data_ver > DATA_VERSION_MAX) {
> +		pr_err("aw_bin_parse Unrecognized this bin data version\n");
> +		return -DATA_VER_ERR;

Return -EINVAL?

> +	}
> +
> +	return 0;
> +}
> +
> +static int aw_check_register_num_v1(struct aw_bin *bin, int bin_num)
> +{
> +	unsigned int check_register_num = 0;
> +	unsigned int parse_register_num = 0;
> +	unsigned char *p_check_sum = NULL;
> +	struct bin_header_info temp_info;
> +
> +	temp_info = bin->header_info[bin_num];
> +	p_check_sum = &(bin->info.data[(temp_info.valid_data_addr)]);
> +	pr_debug("aw_bin_parse p_check_sum = %p\n", p_check_sum);
> +	parse_register_num = le32_to_cpup((void *)p_check_sum);
> +	check_register_num = (bin->header_info[bin_num].bin_data_len - 4) /
> +				(bin->header_info[bin_num].reg_byte_len +
> +				bin->header_info[bin_num].data_byte_len);
> +	pr_debug("%s bin_num = %d,parse_register_num = 0x%x,check_register_num = 0x%x\n",
> +				__func__, bin_num, parse_register_num, check_register_num);
> +	if (parse_register_num != check_register_num) {
> +		p_check_sum = NULL;
Same weird pattern as in previous function.

> +		pr_err("%s bin_num = %d,parse_register_num = 0x%x,check_register_num = 0x%x\n",
> +				__func__, bin_num, parse_register_num, check_register_num);
> +
> +		return -REG_NUM_ERR;

-EINVAL?

> +	}
> +	bin->header_info[bin_num].reg_num = parse_register_num;
> +	bin->header_info[bin_num].valid_data_len = temp_info.bin_data_len - 4;
> +	p_check_sum = NULL;

Again. I see that it is same in following function, I won't comment 
them, but it should be also fixed there.

> +	bin->header_info[bin_num].valid_data_addr = temp_info.valid_data_addr + 4;
> +
> +	return 0;
> +}
> +

(...)

> +
> +static int aw_dev_parse_dev_default_type(struct aw_device *aw_dev,
> +		struct aw_cfg_hdr *prof_hdr, struct aw_all_prof_info *all_prof_info)
> +{
> +	int i = 0;
> +	int ret;
> +	int sec_num = 0;
> +	struct aw_cfg_dde *cfg_dde =
> +		(struct aw_cfg_dde *)((char *)prof_hdr + prof_hdr->a_hdr_offset);
> +
> +	for (i = 0; i < prof_hdr->a_ddt_num; i++) {
> +		if ((aw_dev->channel == cfg_dde[i].dev_index) &&
> +			(cfg_dde[i].type == AW_DEV_DEFAULT_TYPE_ID)) {
> +			if (cfg_dde[i].data_type != ACF_SEC_TYPE_MONITOR) {

"if" containing another "if", you can just use &&, so:
if ((aw_dev->channel == cfg_dde[i].dev_index) &&
	(cfg_dde[i].type == AW_DEV_DEFAULT_TYPE_ID) &&
	(cfg_dde[i].data_type != ACF_SEC_TYPE_MONITOR)) {
and then you can reduce one level of intendation here.


> +				if (cfg_dde[i].dev_profile >= AW_PROFILE_MAX) {
> +					dev_err(aw_dev->dev, "dev_profile [%d] overflow",
> +						cfg_dde[i].dev_profile);
> +					return -EINVAL;
> +				}
> +				ret = aw_dev_parse_data_by_sec_type(aw_dev, prof_hdr, &cfg_dde[i],
> +					&all_prof_info->prof_desc[cfg_dde[i].dev_profile]);
> +				if (ret < 0) {
> +					dev_err(aw_dev->dev, "parse failed");
> +					return ret;
> +				}
> +				sec_num++;
> +			}
> +		}
> +	}
> +
> +	if (sec_num == 0) {
> +		dev_err(aw_dev->dev, "get dev default type failed, get num[%d]", sec_num);
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
> +static int aw_dev_cfg_get_vaild_prof(struct aw_device *aw_dev,
> +				struct aw_all_prof_info all_prof_info)
> +{
> +	int i;
> +	int num = 0;
> +	struct aw_sec_data_desc *sec_desc = NULL;
> +	struct aw_prof_desc *prof_desc = all_prof_info.prof_desc;
> +	struct aw_prof_info *prof_info = &aw_dev->prof_info;
> +
> +	for (i = 0; i < AW_PROFILE_MAX; i++) {
> +		if (prof_desc[i].prof_st == AW_PROFILE_OK) {
> +			sec_desc = prof_desc[i].sec_desc;
> +			if ((sec_desc[AW_DATA_TYPE_REG].data != NULL) &&
> +				(sec_desc[AW_DATA_TYPE_REG].len != 0) &&
> +				(sec_desc[AW_DATA_TYPE_DSP_CFG].data != NULL) &&
> +				(sec_desc[AW_DATA_TYPE_DSP_CFG].len != 0) &&
> +				(sec_desc[AW_DATA_TYPE_DSP_FW].data != NULL) &&
> +				(sec_desc[AW_DATA_TYPE_DSP_FW].len != 0)) {
> +				prof_info->count++;
> +			}
> +		}
> +	}
> +
> +	dev_dbg(aw_dev->dev, "get valid profile:%d", aw_dev->prof_info.count);
> +
> +	if (!prof_info->count) {
> +		dev_err(aw_dev->dev, "no profile data");
> +		return -EPERM;
> +	}
> +
> +	prof_info->prof_desc = devm_kzalloc(aw_dev->dev,
> +					prof_info->count * sizeof(struct aw_prof_desc),
> +					GFP_KERNEL);
> +	if (!prof_info->prof_desc) {
> +		dev_err(aw_dev->dev, "prof_desc kzalloc failed");
> +		return -ENOMEM;
> +	}
> +
> +	for (i = 0; i < AW_PROFILE_MAX; i++) {
> +		if (prof_desc[i].prof_st == AW_PROFILE_OK) {
> +			sec_desc = prof_desc[i].sec_desc;
> +			if ((sec_desc[AW_DATA_TYPE_REG].data != NULL) &&
> +				(sec_desc[AW_DATA_TYPE_REG].len != 0) &&
> +				(sec_desc[AW_DATA_TYPE_DSP_CFG].data != NULL) &&
> +				(sec_desc[AW_DATA_TYPE_DSP_CFG].len != 0) &&
> +				(sec_desc[AW_DATA_TYPE_DSP_FW].data != NULL) &&
> +				(sec_desc[AW_DATA_TYPE_DSP_FW].len != 0)) {
> +				if (num >= prof_info->count) {
> +					dev_err(aw_dev->dev, "get scene num[%d] overflow count[%d]",
> +						num, prof_info->count);
> +					return -ENOMEM;
> +				}
> +				prof_info->prof_desc[num] = prof_desc[i];
> +				prof_info->prof_desc[num].id = i;
> +				num++;
> +			}
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static int aw_dev_load_cfg_by_hdr(struct aw_device *aw_dev,
> +		struct aw_cfg_hdr *prof_hdr)
> +{
> +	int ret;
> +	struct aw_all_prof_info *all_prof_info;
> +
> +	all_prof_info = devm_kzalloc(aw_dev->dev, sizeof(struct aw_all_prof_info), GFP_KERNEL);
> +	if (!all_prof_info)
> +		return -ENOMEM;
> +
> +	ret = aw_dev_parse_dev_type(aw_dev, prof_hdr, all_prof_info);
> +	if (ret < 0) {
> +		goto exit;
> +	} else if (ret == AW_DEV_TYPE_NONE) {
> +		dev_dbg(aw_dev->dev, "get dev type num is 0, parse default dev");
> +		ret = aw_dev_parse_dev_default_type(aw_dev, prof_hdr, all_prof_info);
> +		if (ret < 0)
> +			goto exit;
> +	}
> +
> +	ret = aw_dev_cfg_get_vaild_prof(aw_dev, *all_prof_info);
> +	if (ret < 0)
> +		goto exit;
> +
> +	aw_dev->prof_info.prof_name_list = profile_name;
> +exit:
> +	devm_kfree(aw_dev->dev, all_prof_info);
> +	return ret;
> +}
> +
> +static int aw_dev_create_prof_name_list_v_1_0_0_0(struct aw_device *aw_dev)
> +{
> +	struct aw_prof_info *prof_info = &aw_dev->prof_info;
> +	struct aw_prof_desc *prof_desc = prof_info->prof_desc;
> +	int i;
> +
> +	if (!prof_desc) {
> +		dev_err(aw_dev->dev, "prof_desc is NULL");
> +		return -EINVAL;
> +	}
> +
> +	prof_info->prof_name_list = devm_kzalloc(aw_dev->dev,
> +					prof_info->count * PROFILE_STR_MAX,
> +					GFP_KERNEL);

You seem to be allocating an array here, consider devm_kcalloc instead?

> +	if (!prof_info->prof_name_list) {
> +		dev_err(aw_dev->dev, "prof_name_list devm_kzalloc failed");
> +		return -ENOMEM;
> +	}
> +
> +	for (i = 0; i < prof_info->count; i++) {
> +		prof_desc[i].id = i;
> +		prof_info->prof_name_list[i] = prof_desc[i].prf_str;
> +		dev_dbg(aw_dev->dev, "prof name is %s", prof_info->prof_name_list[i]);
> +	}
> +
> +	return 0;
> +}
> +

(...)

> +
> +static int aw_dev_load_cfg_by_hdr_v_1_0_0_0(struct aw_device *aw_dev,
> +									struct aw_container *aw_cfg)
> +{
> +	struct aw_prof_info *prof_info = &aw_dev->prof_info;
> +	struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
> +	int ret;
> +
> +	ret = aw_dev_parse_scene_count_v_1_0_0_0(aw_dev, aw_cfg, &prof_info->count);
> +	if (ret < 0) {
> +		dev_err(aw_dev->dev, "get scene count failed");
> +		return ret;
> +	}
> +
> +	prof_info->prof_desc = devm_kzalloc(aw_dev->dev,
> +					prof_info->count * sizeof(struct aw_prof_desc),
> +					GFP_KERNEL);

You seem to be allocating an array here, consider devm_kcalloc instead?

> +	if (!prof_info->prof_desc)
> +		return -ENOMEM;
> +
> +	ret = aw_dev_parse_by_hdr_v_1_0_0_0(aw_dev, cfg_hdr);
> +	if (ret < 0) {
> +		dev_err(aw_dev->dev, " failed");
> +		return ret;
> +	}
> +
> +	ret = aw_dev_create_prof_name_list_v_1_0_0_0(aw_dev);
> +	if (ret < 0) {
> +		dev_err(aw_dev->dev, "create prof name list failed");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +int aw883xx_dev_cfg_load(struct aw_device *aw_dev, struct aw_container *aw_cfg)
> +{
> +	struct aw_cfg_hdr *cfg_hdr = NULL;
> +	int ret;
> +
> +	cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
> +
> +	switch (cfg_hdr->a_hdr_version) {
> +	case AW_CFG_HDR_VER_0_0_0_1:
> +		ret = aw_dev_load_cfg_by_hdr(aw_dev, cfg_hdr);
> +		if (ret < 0) {
> +			dev_err(aw_dev->dev, "hdr_cersion[0x%x] parse failed",
> +						cfg_hdr->a_hdr_version);
> +			return ret;
> +		}
> +		break;
> +	case AW_CFG_HDR_VER_1_0_0_0:
> +		ret = aw_dev_load_cfg_by_hdr_v_1_0_0_0(aw_dev, aw_cfg);
> +		if (ret < 0) {
> +			dev_err(aw_dev->dev, "hdr_cersion[0x%x] parse failed",
> +						cfg_hdr->a_hdr_version);
> +			return ret;
> +		}
> +		break;
> +	default:
> +		dev_err(aw_dev->dev, "unsupported hdr_version [0x%x]", cfg_hdr->a_hdr_version);
> +		return -EINVAL;
> +	}
> +	aw_dev->fw_status = AW_DEV_FW_OK;
> +	return 0;
> +}
> +
> +static unsigned char aw_dev_crc8_check(unsigned char *data, unsigned int data_size)
> +{
> +	u8 crc_value = 0x00;
> +	u8 pdatabuf = 0;
> +	int i;
> +
> +	while (data_size--) {
> +		pdatabuf = *data++;
> +		for (i = 0; i < 8; i++) {
> +			/*if the lowest bit is 1*/
> +			if ((crc_value ^ (pdatabuf)) & 0x01) {
> +				/*Xor multinomial*/
> +				crc_value ^= 0x18;
> +				crc_value >>= 1;
> +				crc_value |= 0x80;
> +			} else {
> +				crc_value >>= 1;
> +			}
> +			pdatabuf >>= 1;
> +		}
> +	}
> +	return crc_value;
> +}

There seems to be crc8 implementation in Linux already, any reason to 
implement your own?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/crc8.h
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/lib/crc8.c

> +
> +static int aw_dev_check_cfg_by_hdr(struct aw_container *aw_cfg)
> +{
> +	struct aw_cfg_hdr *cfg_hdr = NULL;
> +	struct aw_cfg_dde *cfg_dde = NULL;
> +	unsigned int end_data_offset = 0;
> +	unsigned int act_data = 0;
> +	unsigned int hdr_ddt_len = 0;
> +	u8 act_crc8 = 0;
> +	int i;
> +
> +	cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
> +	/*check file type id is awinic acf file*/
> +	if (cfg_hdr->a_id != ACF_FILE_ID) {
> +		pr_err("not acf type file");
> +		return -EINVAL;
> +	}
> +
> +	hdr_ddt_len = cfg_hdr->a_hdr_offset + cfg_hdr->a_ddt_size;
> +	if (hdr_ddt_len > aw_cfg->len) {
> +		pr_err("hdrlen with ddt_len [%d] overflow file size[%d]",
> +		cfg_hdr->a_hdr_offset, aw_cfg->len);
> +		return -EINVAL;
> +	}
> +
> +	/*check data size*/
> +	cfg_dde = (struct aw_cfg_dde *)((char *)aw_cfg->data + cfg_hdr->a_hdr_offset);
> +	act_data += hdr_ddt_len;
> +	for (i = 0; i < cfg_hdr->a_ddt_num; i++)
> +		act_data += cfg_dde[i].data_size;
> +
> +	if (act_data != aw_cfg->len) {
> +		pr_err("act_data[%d] not equal to file size[%d]!",
> +			act_data, aw_cfg->len);
> +		return -EINVAL;
> +	}
> +
> +	for (i = 0; i < cfg_hdr->a_ddt_num; i++) {
> +		/* data check */
> +		end_data_offset = cfg_dde[i].data_offset + cfg_dde[i].data_size;
> +		if (end_data_offset > aw_cfg->len) {
> +			pr_err("a_ddt_num[%d] end_data_offset[%d] overflow file size[%d]",
> +				i, end_data_offset, aw_cfg->len);
> +			return -EINVAL;
> +		}
> +
> +		/* crc check */
> +		act_crc8 = aw_dev_crc8_check(aw_cfg->data + cfg_dde[i].data_offset,
> +									cfg_dde[i].data_size);
> +		if (act_crc8 != cfg_dde[i].data_crc) {
> +			pr_err("a_ddt_num[%d] crc8 check failed, act_crc8:0x%x != data_crc 0x%x",
> +				i, (u32)act_crc8, cfg_dde[i].data_crc);
> +			return -EINVAL;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static int aw_dev_check_acf_by_hdr_v_1_0_0_0(struct aw_container *aw_cfg)
> +{
> +	struct aw_cfg_hdr *cfg_hdr = NULL;
> +	struct aw_cfg_dde_v_1_0_0_0 *cfg_dde = NULL;
> +	unsigned int end_data_offset = 0;
> +	unsigned int act_data = 0;
> +	unsigned int hdr_ddt_len = 0;
> +	u8 act_crc8 = 0;
> +	int i;
> +
> +	cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
> +
> +	/*check file type id is awinic acf file*/
> +	if (cfg_hdr->a_id != ACF_FILE_ID) {
> +		pr_err("not acf type file");
> +		return -EINVAL;
> +	}
> +
> +	hdr_ddt_len = cfg_hdr->a_hdr_offset + cfg_hdr->a_ddt_size;
> +	if (hdr_ddt_len > aw_cfg->len) {
> +		pr_err("hdrlen with ddt_len [%d] overflow file size[%d]",
> +		cfg_hdr->a_hdr_offset, aw_cfg->len);
> +		return -EINVAL;
> +	}
> +
> +	/*check data size*/
> +	cfg_dde = (struct aw_cfg_dde_v_1_0_0_0 *)((char *)aw_cfg->data + cfg_hdr->a_hdr_offset);
> +	act_data += hdr_ddt_len;
> +	for (i = 0; i < cfg_hdr->a_ddt_num; i++)
> +		act_data += cfg_dde[i].data_size;
> +
> +	if (act_data != aw_cfg->len) {
> +		pr_err("act_data[%d] not equal to file size[%d]!",
> +			act_data, aw_cfg->len);
> +		return -EINVAL;
> +	}
> +
> +	for (i = 0; i < cfg_hdr->a_ddt_num; i++) {
> +		/* data check */
> +		end_data_offset = cfg_dde[i].data_offset + cfg_dde[i].data_size;
> +		if (end_data_offset > aw_cfg->len) {
> +			pr_err("a_ddt_num[%d] end_data_offset[%d] overflow file size[%d]",
> +				i, end_data_offset, aw_cfg->len);
> +			return -EINVAL;
> +		}
> +
> +		/* crc check */
> +		act_crc8 = aw_dev_crc8_check(aw_cfg->data + cfg_dde[i].data_offset,
> +							cfg_dde[i].data_size);
> +		if (act_crc8 != cfg_dde[i].data_crc) {
> +			pr_err("a_ddt_num[%d] crc8 check failed, act_crc8:0x%x != data_crc 0x%x",
> +				i, (u32)act_crc8, cfg_dde[i].data_crc);
> +			return -EINVAL;
> +		}
> +	}
> +
> +	return 0;
> +
> +}
> +
> +int aw883xx_dev_load_acf_check(struct aw_container *aw_cfg)
> +{
> +	struct aw_cfg_hdr *cfg_hdr = NULL;
> +
> +	if (!aw_cfg) {
> +		pr_err("aw_prof is NULL");
> +		return -ENOMEM;
> +	}
> +
> +	if (aw_cfg->len < sizeof(struct aw_cfg_hdr)) {
> +		pr_err("cfg hdr size[%d] overflow file size[%d]",
> +			aw_cfg->len, (int)sizeof(struct aw_cfg_hdr));
> +		return -EINVAL;
> +	}
> +
> +	cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
> +	switch (cfg_hdr->a_hdr_version) {
> +	case AW_CFG_HDR_VER_0_0_0_1:
> +		return aw_dev_check_cfg_by_hdr(aw_cfg);
> +	case AW_CFG_HDR_VER_1_0_0_0:
> +		return aw_dev_check_acf_by_hdr_v_1_0_0_0(aw_cfg);
> +	default:
> +		pr_err("unsupported hdr_version [0x%x]", cfg_hdr->a_hdr_version);
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
> +int aw883xx_dev_get_profile_count(struct aw_device *aw_dev)
> +{
> +	if (!aw_dev) {
> +		pr_err("aw_dev is NULL");
> +		return -ENOMEM;
> +	}
> +
> +	return aw_dev->prof_info.count;
> +}
> +
> +int aw883xx_dev_check_profile_index(struct aw_device *aw_dev, int index)
> +{
> +	if ((index >= aw_dev->prof_info.count) || (index < 0))
> +		return -EINVAL;
> +	else
> +		return 0;
> +}

No need to do "else return 0;", you can just "return 0;" It looks bit 
cleaner when it is:
{
if (check something)
	return -EINVAL;

return 0;
}

> +
> +int aw883xx_dev_get_profile_index(struct aw_device *aw_dev)
> +{
> +	return aw_dev->set_prof;
> +}
> +
> +int aw883xx_dev_set_profile_index(struct aw_device *aw_dev, int index)
> +{
> +	struct aw_prof_desc *prof_desc = NULL;
> +
> +	if ((index < aw_dev->prof_info.count) && (index >= 0)) {
> +		aw_dev->set_prof = index;
> +		prof_desc = &aw_dev->prof_info.prof_desc[index];
> +
> +		dev_dbg(aw_dev->dev, "set prof[%s]",
> +			aw_dev->prof_info.prof_name_list[prof_desc->id]);
> +	} else {
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}

Similarly here, you can just check before hand and success path later:
if ((index >= aw_dev->prof_info.count) || (index < 0))
	return -EINVAL;

aw_dev->set_prof = index;
...
return 0;

> +
> +char *aw_dev_get_prof_name(struct aw_device *aw_dev, int index)
> +{
> +	struct aw_prof_desc *prof_desc = NULL;
> +	struct aw_prof_info *prof_info = &aw_dev->prof_info;
> +
> +	if ((index >= aw_dev->prof_info.count) || (index < 0)) {
> +		dev_err(aw_dev->dev, "index[%d] overflow count[%d]",
> +			index, aw_dev->prof_info.count);
> +		return NULL;
> +	}
> +
> +	prof_desc = &aw_dev->prof_info.prof_desc[index];
> +
> +	return prof_info->prof_name_list[prof_desc->id];
> +}
> +
> +int aw883xx_dev_get_prof_data(struct aw_device *aw_dev, int index,
> +			struct aw_prof_desc **prof_desc)
> +{
> +	if ((index >= aw_dev->prof_info.count) || (index < 0)) {
> +		dev_err(aw_dev->dev, "%s: index[%d] overflow count[%d]\n",
> +			__func__, index, aw_dev->prof_info.count);
> +		return -EINVAL;
> +	}
> +
> +	*prof_desc = &aw_dev->prof_info.prof_desc[index];
> +
> +	return 0;
> +}
> +
> diff --git a/sound/soc/codecs/aw883xx/aw883xx_bin_parse.h b/sound/soc/codecs/aw883xx/aw883xx_bin_parse.h
> new file mode 100644
> index 000000000000..7f5ce0b1f899
> --- /dev/null
> +++ b/sound/soc/codecs/aw883xx/aw883xx_bin_parse.h
> @@ -0,0 +1,149 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * aw883xx.c --  ALSA Soc AW883XX codec support

Soc -> SoC

> + *
> + * Copyright (c) 2022 AWINIC Technology CO., LTD
> + *
> + * Author: Bruce zhao <zhaolei@awinic.com>
> + */
> +
> +#ifndef __AW883XX_BIN_PARSE_H__
> +#define __AW883XX_BIN_PARSE_H__
> +
> +#include "aw883xx_device.h"
> +
> +#define BIN_NUM_MAX				(100)
> +#define HEADER_LEN				(60)
> +#define CHECK_SUM_OFFSET		(0)
> +#define HEADER_VER_OFFSET		(4)
> +#define	BIN_DATA_TYPE_OFFSET	(8)
> +#define	BIN_DATA_VER_OFFSET		(12)
> +#define	BIN_DATA_LEN_OFFSET		(16)
> +#define	UI_VER_OFFSET			(20)
> +#define CHIP_TYPE_OFFSET		(24)
> +#define	REG_BYTE_LEN_OFFSET		(32)
> +#define	DATA_BYTE_LEN_OFFSET	(36)
> +#define	DEVICE_ADDR_OFFSET		(40)
> +
> +#define AW_FW_CHECK_PART		(10)
> +
> +/*
> + * header information
> + */
> +enum return_enum {
> +	BIN_HEADER_VER_ERR = 1,
> +	BIN_DATA_TYPE_ERR = 2,
> +	BIN_DATA_LEN_ERR = 3,
> +	DATA_VER_ERR = 4,
> +	REG_NUM_ERR = 5,
> +	DSP_REG_NUM_ERR = 6,
> +	SOC_APP_NUM_ERR = 7,
> +	BIN_IS_NULL = 8,
> +};

As mentioned in the beginning, do you even need your own error values, 
they seem to be just passed up to be later converted to -EINVAL, might 
as well return -EINVAL directly.

> +
> +enum bin_header_version_enum {
> +	HEADER_VERSION_1_0_0 = 0x01000000,
> +};
> +
> +enum data_type_enum {
> +	DATA_TYPE_REGISTER = 0x00000000,
> +	DATA_TYPE_DSP_REG = 0x00000010,
> +	DATA_TYPE_DSP_CFG = 0x00000011,
> +	DATA_TYPE_SOC_REG = 0x00000020,
> +	DATA_TYPE_SOC_APP = 0x00000021,
> +	DATA_TYPE_DSP_FW = DATA_TYPE_SOC_APP,
> +	DATA_TYPE_MULTI_BINS = 0x00002000,
> +};
> +
> +/**
> + * @DATA_VERSION_V1：default little edian
> + */
> +enum data_version_enum {
> +	DATA_VERSION_V1 = 0X00000001,
> +	DATA_VERSION_MAX,
> +};
> +
> +/**
> + * @header_len: Frame header length
> + * @check_sum: Frame header information-Checksum
> + * @header_ver: Frame header information-Frame header version
> + * @bin_data_type: Frame header information-Data type
> + * @bin_data_ver: Frame header information-Data version
> + * @bin_data_len: Frame header information-Data length
> + * @ui_ver: Frame header information-ui version
> + * @chip_type[8]: Frame header information-chip type
> + * @reg_byte_len: Frame header information-reg byte len
> + * @data_byte_len: Frame header information-data byte len
> + * @device_addr: Frame header information-device addr
> + * @valid_data_len: Length of valid data obtained after parsing
> + * @valid_data_addr: The offset address of the valid data obtained
> + *                   after parsing relative to info
> + * @reg_num: The number of registers obtained after parsing
> + * @reg_data_byte_len: The byte length of the register obtained after parsing
> + * @download_addr: The starting address or download address obtained
> + *                 after parsing
> + * @app_version: The software version number obtained after parsing
> + */
> +struct bin_header_info {
> +	unsigned int header_len;
> +	unsigned int check_sum;
> +	unsigned int header_ver;
> +	unsigned int bin_data_type;
> +	unsigned int bin_data_ver;
> +	unsigned int bin_data_len;
> +	unsigned int ui_ver;
> +	unsigned char chip_type[8];
> +	unsigned int reg_byte_len;
> +	unsigned int data_byte_len;
> +	unsigned int device_addr;
> +	unsigned int valid_data_len;
> +	unsigned int valid_data_addr;
> +
> +	unsigned int reg_num;
> +	unsigned int reg_data_byte_len;
> +	unsigned int download_addr;
> +	unsigned int app_version;
> +};
> +
> +/*
> + * @len: The size of the bin file obtained from the firmware
> + * @data[]: Store the bin file obtained from the firmware
> + */
> +struct bin_container {
> +	unsigned int len;
> +	unsigned char data[];
> +};
> +
> +/**
> + * @p_addr: Offset pointer (backward offset pointer to obtain frame header
> + *          information and important information)
> + * @all_bin_parse_num: The number of all bin files
> + * @multi_bin_parse_num: The number of single bin files
> + * @single_bin_parse_num: The number of multiple bin files
> + * @header_info[BIN_NUM_MAX]: Frame header information and other important data
> + *                            obtained after parsing
> + * @info: Obtained bin file data that needs to be parsed
> + */
> +struct aw_bin {
> +	unsigned char *p_addr;
> +	unsigned int all_bin_parse_num;
> +	unsigned int multi_bin_parse_num;
> +	unsigned int single_bin_parse_num;
> +	struct bin_header_info header_info[BIN_NUM_MAX];
> +	struct bin_container info;
> +};
> +
> +/*******************awinic audio parse acf***********************/
> +int aw883xx_dev_dsp_data_order(struct aw_device *aw_dev,
> +				unsigned char *data, unsigned int data_len);
> +int aw883xx_dev_get_prof_data(struct aw_device *aw_dev, int index,
> +			struct aw_prof_desc **prof_desc);
> +char *aw_dev_get_prof_name(struct aw_device *aw_dev, int index);
> +int aw883xx_dev_set_profile_index(struct aw_device *aw_dev, int index);
> +int aw883xx_dev_get_profile_index(struct aw_device *aw_dev);
> +int aw883xx_dev_check_profile_index(struct aw_device *aw_dev, int index);
> +int aw883xx_dev_get_profile_count(struct aw_device *aw_dev);
> +int aw883xx_dev_cfg_load(struct aw_device *aw_dev, struct aw_container *aw_cfg);
> +int aw883xx_dev_load_acf_check(struct aw_container *aw_cfg);
> +
> +#endif

Re: [PATCH V6 3/5] ASoC: codecs: aw883xx chip control logic, such as power on and off

[Amadeusz Sławiński]

On 12/8/2022 1:23 PM, wangweidong.a@awinic.com wrote:
> From: Weidong Wang <wangweidong.a@awinic.com>
> 
> The Awinic AW883XX is an I2S/TDM input, high efficiency
> digital Smart K audio amplifier with an integrated 10.25V
> smart boost convert
> 
> Signed-off-by: Nick Li <liweilei@awinic.com>
> Signed-off-by: Bruce zhao <zhaolei@awinic.com>
> Signed-off-by: Weidong Wang <wangweidong.a@awinic.com>
> ---
>   sound/soc/codecs/aw883xx/aw883xx_device.c | 1613 +++++++++++++++++++++
>   sound/soc/codecs/aw883xx/aw883xx_device.h |  537 +++++++
>   2 files changed, 2150 insertions(+)
>   create mode 100644 sound/soc/codecs/aw883xx/aw883xx_device.c
>   create mode 100644 sound/soc/codecs/aw883xx/aw883xx_device.h
> 
> diff --git a/sound/soc/codecs/aw883xx/aw883xx_device.c b/sound/soc/codecs/aw883xx/aw883xx_device.c
> new file mode 100644
> index 000000000000..f4419e1a2fed
> --- /dev/null
> +++ b/sound/soc/codecs/aw883xx/aw883xx_device.c
> @@ -0,0 +1,1613 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * aw883xx.c --  ALSA Soc AW883XX codec support

Soc -> SoC

> + *
> + * Copyright (c) 2022 AWINIC Technology CO., LTD
> + *
> + * Author: Bruce zhao <zhaolei@awinic.com>
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/debugfs.h>
> +#include <linux/firmware.h>
> +#include <linux/i2c.h>
> +#include <linux/module.h>
> +#include <linux/of_gpio.h>
> +#include <linux/syscalls.h>
> +#include <linux/version.h>
> +#include <linux/uaccess.h>
> +#include <linux/workqueue.h>

Again, there seem to be unnecessary headers included.

> +#include <sound/core.h>
> +#include <sound/control.h>
> +#include <sound/pcm.h>
> +#include <sound/pcm_params.h>
> +#include <sound/soc.h>
> +#include "aw883xx_data_type.h"
> +#include "aw883xx_device.h"
> +#include "aw883xx_bin_parse.h"
> +
> +int aw883xx_dev_set_volume(struct aw_device *aw_dev, unsigned short set_vol)
> +{
> +	u16 hw_vol = 0;
> +	int ret = -1;

As mentioned in previous patchset this mey lead to returning "-1" 
somewhere which maps to -EPERM, just set it to -EINVAL if you want to 
set it to something... same for the rest of the patchset (won't be 
commenting each occurence in file.)

> +	struct aw_volume_desc *vol_desc = &aw_dev->volume_desc;
> +
> +	hw_vol = set_vol + vol_desc->init_volume;
> +
> +	ret = aw_dev->ops.aw_set_hw_volume(aw_dev, hw_vol);
> +	if (ret < 0) {
> +		dev_err(aw_dev->dev, "set volume failed");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +int aw883xx_dev_get_volume(struct aw_device *aw_dev, unsigned short *get_vol)
> +{
> +	int ret = -1;
> +	u16 hw_vol = 0;
> +	struct aw_volume_desc *vol_desc = &aw_dev->volume_desc;
> +
> +	ret = aw_dev->ops.aw_get_hw_volume(aw_dev, &hw_vol);
> +	if (ret < 0) {
> +		dev_err(aw_dev->dev, "read volume failed");
> +		return ret;
> +	}
> +
> +	if (hw_vol > vol_desc->init_volume)
> +		*get_vol = hw_vol - vol_desc->init_volume;
> +
> +	return 0;
> +}
> +
> +static void aw_dev_fade_in(struct aw_device *aw_dev)
> +{
> +	int i = 0;
> +	struct aw_volume_desc *desc = &aw_dev->volume_desc;
> +	int fade_step = aw_dev->fade_step;
> +	u16 fade_in_vol = desc->ctl_volume;
> +
> +	if (!aw_dev->fade_en)
> +		return;
> +
> +	if (fade_step == 0 || aw_dev->fade_in_time == 0) {
> +		aw883xx_dev_set_volume(aw_dev, fade_in_vol);
> +		return;
> +	}
> +	/*volume up*/
> +	for (i = desc->mute_volume; i >= fade_in_vol; i -= fade_step) {
> +		aw883xx_dev_set_volume(aw_dev, i);
> +		usleep_range(aw_dev->fade_in_time, aw_dev->fade_in_time + 10);
> +	}
> +	if (i != fade_in_vol)
> +		aw883xx_dev_set_volume(aw_dev, fade_in_vol);
> +
> +}
> +
> +static void aw_dev_fade_out(struct aw_device *aw_dev)
> +{
> +	int i = 0;
> +	struct aw_volume_desc *desc = &aw_dev->volume_desc;
> +	int fade_step = aw_dev->fade_step;
> +
> +	if (!aw_dev->fade_en)
> +		return;
> +
> +	if (fade_step == 0 || aw_dev->fade_out_time == 0) {
> +		aw883xx_dev_set_volume(aw_dev, desc->mute_volume);
> +		return;
> +	}
> +
> +	for (i = desc->ctl_volume; i <= desc->mute_volume; i += fade_step) {
> +		aw883xx_dev_set_volume(aw_dev, i);
> +		usleep_range(aw_dev->fade_out_time, aw_dev->fade_out_time + 10);
> +	}
> +	if (i != desc->mute_volume) {
> +		aw883xx_dev_set_volume(aw_dev, desc->mute_volume);
> +		usleep_range(aw_dev->fade_out_time, aw_dev->fade_out_time + 10);
> +	}
> +}
> +
> +static uint64_t aw_dev_dsp_crc32_reflect(uint64_t ref, unsigned char ch)
> +{
> +	int i;
> +	uint64_t value = 0;
> +
> +	for (i = 1; i < (ch + 1); i++) {
> +		if (ref & 1)
> +			value |= 1 << (ch - i);
> +
> +		ref >>= 1;
> +	}
> +
> +	return value;
> +}
> +
> +static unsigned int aw_dev_calc_dsp_cfg_crc32(unsigned char *buf, unsigned int len)
> +{
> +	u8 i;
> +	u32 crc = 0xffffffff;
> +
> +	while (len--) {
> +		for (i = 1; i != 0; i <<= 1) {
> +			if ((crc & 0x80000000) != 0) {
> +				crc <<= 1;
> +				crc ^= 0x1EDC6F41;
> +			} else {
> +				crc <<= 1;
> +			}
> +
> +			if ((*buf & i) != 0)
> +				crc ^= 0x1EDC6F41;
> +		}
> +		buf++;
> +	}
> +
> +	return (aw_dev_dsp_crc32_reflect(crc, 32)^0xffffffff);
> +}
> +
> +static int aw_dev_set_dsp_crc32(struct aw_device *aw_dev)
> +{
> +	u32 crc_value = 0;
> +	u32 crc_data_len = 0;
> +	int ret = -1;
> +	struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg;
> +	struct aw_dsp_crc_desc *desc = &aw_dev->dsp_crc_desc;
> +
> +	/*get crc data len*/
> +	crc_data_len = (desc->dsp_reg - aw_dev->dsp_mem_desc.dsp_cfg_base_addr) * 2;
> +	if (crc_data_len > crc_dsp_cfg->len) {
> +		dev_err(aw_dev->dev, "crc data len :%d > cfg_data len:%d",
> +			crc_data_len, crc_dsp_cfg->len);
> +		return -EINVAL;
> +	}
> +
> +	if (crc_data_len % 4 != 0) {
> +		dev_err(aw_dev->dev, "The crc data len :%d unsupport", crc_data_len);
> +		return -EINVAL;
> +	}
> +
> +	crc_value = aw_dev_calc_dsp_cfg_crc32(crc_dsp_cfg->data, crc_data_len);
> +
> +	dev_dbg(aw_dev->dev, "crc_value:0x%x", crc_value);
> +	ret = aw_dev->ops.aw_dsp_write(aw_dev, desc->dsp_reg, crc_value,
> +						desc->data_type);
> +	if (ret < 0) {
> +		dev_err(aw_dev->dev, "set dsp crc value failed");
> +		return ret;
> +	}
> +
> +	return 0;
> +}


Similarly to crc8, Linux implements crc32
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/crc32.h
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/lib/crc32.c
no need to implement your own.

> +
> +static void aw_dev_dsp_crc_check_enable(struct aw_device *aw_dev, bool flag)
> +{
> +	struct aw_dsp_crc_desc *dsp_crc_desc = &aw_dev->dsp_crc_desc;
> +	struct aw883xx *aw883xx = aw_dev->private_data;
> +	int ret;
> +
> +	if (flag) {
> +		ret = aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, dsp_crc_desc->ctl_reg,
> +				~dsp_crc_desc->ctl_mask, dsp_crc_desc->ctl_enable);
> +		if (ret < 0) {
> +			dev_err(aw_dev->dev, "enable dsp crc failed");
> +			return;
> +		}
> +	} else {
> +		ret = aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, dsp_crc_desc->ctl_reg,
> +				~dsp_crc_desc->ctl_mask, dsp_crc_desc->ctl_disable);
> +		if (ret < 0) {
> +			dev_err(aw_dev->dev, "close dsp crc failed");
> +			return;
> +		}
> +	}
> +}
> +

(...)

> +
> +void aw883xx_dev_memclk_select(struct aw_device *aw_dev, unsigned char flag)
> +{
> +	struct aw_memclk_desc *desc = &aw_dev->memclk_desc;
> +	struct aw883xx *aw883xx = aw_dev->private_data;
> +	int ret = -1;
> +
> +	switch (flag) {
> +	case AW_DEV_MEMCLK_PLL:
> +		ret = aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, desc->reg,
> +					~desc->mask, desc->mcu_hclk);
> +		if (ret < 0)
> +			dev_err(aw_dev->dev, "memclk select pll failed");
> +		break;
> +	case AW_DEV_MEMCLK_OSC:
> +		ret = aw_dev->ops.aw_reg_write_bits(aw883xx->regmap, desc->reg,
> +					~desc->mask, desc->osc_clk);
> +		if (ret < 0)
> +			dev_err(aw_dev->dev, "memclk select OSC failed");
> +		break;
> +	default:
> +		dev_err(aw_dev->dev, "unknown memclk config, flag=0x%x", flag);
> +		break;
> +	}
> +}
> +
> +int aw883xx_dev_get_dsp_status(struct aw_device *aw_dev)
> +{
> +	int ret = -1;
> +	unsigned int reg_val = 0;
> +	struct aw_watch_dog_desc *desc = &aw_dev->watch_dog_desc;
> +	struct aw883xx *aw883xx = aw_dev->private_data;
> +
> +	aw_dev->ops.aw_reg_read(aw883xx->regmap, desc->reg, &reg_val);
> +	if (reg_val & (~desc->mask))
> +		ret = 0;
> +
> +	return ret;

Here is example of what I'm talking about, when talking about setting 
"ret = -1" you can return -1 here, and in call stack it gets mixed with 
kernel return values, like -EINVAL so it can be potentially interpreted 
as -EPERM somewhere.

> +}
> +
> +static int aw_dev_get_vmax(struct aw_device *aw_dev, unsigned int *vmax)
> +{
> +	int ret = -1;
> +	struct aw_vmax_desc *desc = &aw_dev->vmax_desc;
> +
> +	ret = aw_dev->ops.aw_dsp_read(aw_dev, desc->dsp_reg, vmax, desc->data_type);
> +	if (ret < 0) {
> +		dev_err(aw_dev->dev, "get vmax failed");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +

(...)

> +
> +static int aw_dev_dsp_fw_update(struct aw_device *aw_dev,
> +			unsigned char *data, unsigned int len)
> +{
> +	struct aw_dsp_mem_desc *dsp_mem_desc = &aw_dev->dsp_mem_desc;
> +
> +	dev_dbg(aw_dev->dev, "dsp firmware len:%d", len);
> +
> +	if (len && (data != NULL)) {
> +		aw_dev_dsp_container_update(aw_dev,
> +			data, len, dsp_mem_desc->dsp_fw_base_addr);
> +		aw_dev->dsp_fw_len = len;
> +	} else {
> +		dev_err(aw_dev->dev, "dsp firmware data is null or len is 0");
> +		return -EPERM;
> +	}
> +
> +	return 0;
> +}
> +
> +static int aw_dev_copy_to_crc_dsp_cfg(struct aw_device *aw_dev,
> +			unsigned char *data, unsigned int size)
> +{
> +	struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg;
> +	int ret;
> +
> +	if (!crc_dsp_cfg->data) {
> +		crc_dsp_cfg->data = devm_kzalloc(aw_dev->dev, size, GFP_KERNEL);
> +		if (!crc_dsp_cfg->data)
> +			return -ENOMEM;
> +		crc_dsp_cfg->len = size;
> +	} else if (crc_dsp_cfg->len < size) {
> +		devm_kfree(aw_dev->dev, crc_dsp_cfg->data);
> +		crc_dsp_cfg->data = NULL;
> +		crc_dsp_cfg->data = devm_kzalloc(aw_dev->dev, size, GFP_KERNEL);

No need for NULL assignment above, the variable gets set one line later 
anyway.

> +		if (!crc_dsp_cfg->data) {
> +			dev_err(aw_dev->dev, "error allocating memory");
> +			return -ENOMEM;
> +		}
> +		crc_dsp_cfg->len = size;
> +	}
> +	memcpy(crc_dsp_cfg->data, data, size);
> +	ret = aw883xx_dev_dsp_data_order(aw_dev, crc_dsp_cfg->data, size);
> +	if (ret < 0)
> +		return ret;
> +
> +	return 0;
> +}
> +

(...)

> diff --git a/sound/soc/codecs/aw883xx/aw883xx_device.h b/sound/soc/codecs/aw883xx/aw883xx_device.h
> new file mode 100644
> index 000000000000..505cef1fd3e6
> --- /dev/null
> +++ b/sound/soc/codecs/aw883xx/aw883xx_device.h
> @@ -0,0 +1,537 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * aw883xx.c --  ALSA Soc AW883XX codec support
> + *
> + * Copyright (c) 2022 AWINIC Technology CO., LTD
> + *
> + * Author: Bruce zhao <zhaolei@awinic.com>
> + */
> +
> +#ifndef __AW883XX_DEVICE_FILE_H__
> +#define __AW883XX_DEVICE_FILE_H__
> +
> +#include "aw883xx_data_type.h"
> +#include "aw883xx.h"
> +
> +
> +#define AW_DEV_DEFAULT_CH		(0)
> +#define AW_DEV_DSP_CHECK_MAX	(5)
> +
> +/*
> + * DSP I2C WRITES
> + */
> +#define AW_DSP_I2C_WRITES
> +#define AW_MAX_RAM_WRITE_BYTE_SIZE	(128)
> +#define AW_DSP_ODD_NUM_BIT_TEST		(0x5555)
> +#define AW_DSP_EVEN_NUM_BIT_TEST	(0xAAAA)
> +#define AW_DSP_ST_CHECK_MAX		(2)
> +#define AW_FADE_IN_OUT_DEFAULT		(0)
> +#define AW_CALI_DELAY_CACL(value) ((value * 32) / 48)
> +#define AW_CALI_RE_MAX (15000)
> +#define AW_CALI_RE_MIN (4000)
> +
> +#define AW_GET_MIN_VALUE(value1, value2) \
> +	((value1) > (value2) ? (value2) : (value1))
> +
> +#define AW_GET_MAX_VALUE(value1, value2) \
> +	((value1) > (value2) ? (value1) : (value2))

Linux already has min and max macros?


(...)

Re: [PATCH V6 4/5] ASoC: codecs: Configure aw883xx chip register as well as Kconfig and Makefile

[Amadeusz Sławiński]

On 12/8/2022 1:23 PM, wangweidong.a@awinic.com wrote:

(...)

> diff --git a/sound/soc/codecs/aw883xx/aw883xx_init.c b/sound/soc/codecs/aw883xx/aw883xx_init.c
> new file mode 100644
> index 000000000000..2ef62fdebb57
> --- /dev/null
> +++ b/sound/soc/codecs/aw883xx/aw883xx_init.c
> @@ -0,0 +1,615 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * aw883xx.c --  ALSA Soc AW883XX codec support
> + *
> + * Copyright (c) 2022 AWINIC Technology CO., LTD
> + *
> + * Author: Bruce zhao <zhaolei@awinic.com>
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/firmware.h>
> +#include <linux/i2c.h>
> +#include <linux/module.h>
> +#include <linux/of_gpio.h>
> +#include <linux/regmap.h>
> +#include <linux/syscalls.h>
> +#include <linux/uaccess.h>
> +#include <linux/version.h>
> +#include <linux/workqueue.h>

Again headers, picking at random: firmware.h, of_gpio, uaccess.h, 
version.h, from quick check seem unnecessary and likely some others can 
also be removed.

> +#include <sound/control.h>
> +#include <sound/core.h>
> +#include <sound/pcm.h>
> +#include <sound/pcm_params.h>
> +#include <sound/soc.h>
> +#include "aw883xx.h"
> +#include "aw883xx_bin_parse.h"
> +#include "aw883xx_pid_2049_reg.h"
> +

(...)

Re: [PATCH V6 4/5] ASoC: codecs: Configure aw883xx chip register as well as Kconfig and Makefile

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 6216 bytes --]

Hi,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on 479174d402bcf60789106eedc4def3957c060bad]

url:    https://github.com/intel-lab-lkp/linux/commits/wangweidong-a-awinic-com/ASoC-codecs-Add-Awinic-AW883XX-audio-amplifier-driver/20221208-202807
base:   479174d402bcf60789106eedc4def3957c060bad
patch link:    https://lore.kernel.org/r/20221208122313.55118-5-wangweidong.a%40awinic.com
patch subject: [PATCH V6 4/5] ASoC: codecs: Configure aw883xx chip register as well as Kconfig and Makefile
config: sh-allmodconfig
compiler: sh4-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/b1c5682d5348424259f7c253f0c60c9cb6655e6a
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review wangweidong-a-awinic-com/ASoC-codecs-Add-Awinic-AW883XX-audio-amplifier-driver/20221208-202807
        git checkout b1c5682d5348424259f7c253f0c60c9cb6655e6a
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=sh SHELL=/bin/bash sound/soc/codecs/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>

All error/warnings (new ones prefixed by >>):

   sound/soc/codecs/aw883xx/aw883xx_device.c: In function 'aw883xx_request_firmware_file':
>> sound/soc/codecs/aw883xx/aw883xx_device.c:1580:27: error: implicit declaration of function 'vzalloc'; did you mean 'kvzalloc'? [-Werror=implicit-function-declaration]
    1580 |         aw883xx->aw_cfg = vzalloc(cont->size + sizeof(int));
         |                           ^~~~~~~
         |                           kvzalloc
>> sound/soc/codecs/aw883xx/aw883xx_device.c:1580:25: warning: assignment to 'struct aw_container *' from 'int' makes pointer from integer without a cast [-Wint-conversion]
    1580 |         aw883xx->aw_cfg = vzalloc(cont->size + sizeof(int));
         |                         ^
>> sound/soc/codecs/aw883xx/aw883xx_device.c:1592:17: error: implicit declaration of function 'vfree'; did you mean 'kfree'? [-Werror=implicit-function-declaration]
    1592 |                 vfree(aw883xx->aw_cfg);
         |                 ^~~~~
         |                 kfree
   cc1: some warnings being treated as errors


vim +1580 sound/soc/codecs/aw883xx/aw883xx_device.c

a64b410ec778e4 Weidong Wang 2022-12-08  1563  
a64b410ec778e4 Weidong Wang 2022-12-08  1564  int aw883xx_request_firmware_file(struct aw883xx *aw883xx)
a64b410ec778e4 Weidong Wang 2022-12-08  1565  {
a64b410ec778e4 Weidong Wang 2022-12-08  1566  	const struct firmware *cont = NULL;
a64b410ec778e4 Weidong Wang 2022-12-08  1567  	int ret = -1;
a64b410ec778e4 Weidong Wang 2022-12-08  1568  
a64b410ec778e4 Weidong Wang 2022-12-08  1569  	aw883xx->aw_pa->fw_status = AW_DEV_FW_FAILED;
a64b410ec778e4 Weidong Wang 2022-12-08  1570  
a64b410ec778e4 Weidong Wang 2022-12-08  1571  	ret = request_firmware(&cont, AW_ACF_FILE, aw883xx->dev);
a64b410ec778e4 Weidong Wang 2022-12-08  1572  	if ((ret < 0) || (!cont)) {
a64b410ec778e4 Weidong Wang 2022-12-08  1573  		dev_err(aw883xx->dev, "load [%s] failed!", AW_ACF_FILE);
a64b410ec778e4 Weidong Wang 2022-12-08  1574  		return ret;
a64b410ec778e4 Weidong Wang 2022-12-08  1575  	}
a64b410ec778e4 Weidong Wang 2022-12-08  1576  
a64b410ec778e4 Weidong Wang 2022-12-08  1577  	dev_info(aw883xx->dev, "loaded %s - size: %zu",
a64b410ec778e4 Weidong Wang 2022-12-08  1578  		AW_ACF_FILE, cont ? cont->size : 0);
a64b410ec778e4 Weidong Wang 2022-12-08  1579  
a64b410ec778e4 Weidong Wang 2022-12-08 @1580  	aw883xx->aw_cfg = vzalloc(cont->size + sizeof(int));
a64b410ec778e4 Weidong Wang 2022-12-08  1581  	if (!aw883xx->aw_cfg) {
a64b410ec778e4 Weidong Wang 2022-12-08  1582  		release_firmware(cont);
a64b410ec778e4 Weidong Wang 2022-12-08  1583  		return -ENOMEM;
a64b410ec778e4 Weidong Wang 2022-12-08  1584  	}
a64b410ec778e4 Weidong Wang 2022-12-08  1585  	aw883xx->aw_cfg->len = (int)cont->size;
a64b410ec778e4 Weidong Wang 2022-12-08  1586  	memcpy(aw883xx->aw_cfg->data, cont->data, cont->size);
a64b410ec778e4 Weidong Wang 2022-12-08  1587  	release_firmware(cont);
a64b410ec778e4 Weidong Wang 2022-12-08  1588  
a64b410ec778e4 Weidong Wang 2022-12-08  1589  	ret = aw883xx_dev_load_acf_check(aw883xx->aw_cfg);
a64b410ec778e4 Weidong Wang 2022-12-08  1590  	if (ret < 0) {
a64b410ec778e4 Weidong Wang 2022-12-08  1591  		dev_err(aw883xx->dev, "Load [%s] failed ....!", AW_ACF_FILE);
a64b410ec778e4 Weidong Wang 2022-12-08 @1592  		vfree(aw883xx->aw_cfg);
a64b410ec778e4 Weidong Wang 2022-12-08  1593  		aw883xx->aw_cfg = NULL;
a64b410ec778e4 Weidong Wang 2022-12-08  1594  		return ret;
a64b410ec778e4 Weidong Wang 2022-12-08  1595  	}
a64b410ec778e4 Weidong Wang 2022-12-08  1596  
a64b410ec778e4 Weidong Wang 2022-12-08  1597  	dev_dbg(aw883xx->dev, "%s : bin load success\n", __func__);
a64b410ec778e4 Weidong Wang 2022-12-08  1598  
a64b410ec778e4 Weidong Wang 2022-12-08  1599  	mutex_lock(&aw883xx->lock);
a64b410ec778e4 Weidong Wang 2022-12-08  1600  	/*aw device init*/
a64b410ec778e4 Weidong Wang 2022-12-08  1601  	ret = aw883xx_device_init(aw883xx->aw_pa, aw883xx->aw_cfg);
a64b410ec778e4 Weidong Wang 2022-12-08  1602  	if (ret < 0) {
a64b410ec778e4 Weidong Wang 2022-12-08  1603  		dev_err(aw883xx->dev, "dev init failed");
a64b410ec778e4 Weidong Wang 2022-12-08  1604  		vfree(aw883xx->aw_cfg);
a64b410ec778e4 Weidong Wang 2022-12-08  1605  		mutex_unlock(&aw883xx->lock);
a64b410ec778e4 Weidong Wang 2022-12-08  1606  		return ret;
a64b410ec778e4 Weidong Wang 2022-12-08  1607  	}
a64b410ec778e4 Weidong Wang 2022-12-08  1608  
a64b410ec778e4 Weidong Wang 2022-12-08  1609  	mutex_unlock(&aw883xx->lock);
a64b410ec778e4 Weidong Wang 2022-12-08  1610  
a64b410ec778e4 Weidong Wang 2022-12-08  1611  	return 0;
a64b410ec778e4 Weidong Wang 2022-12-08  1612  }
a64b410ec778e4 Weidong Wang 2022-12-08  1613  

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

[-- Attachment #2: config --]
[-- Type: text/plain, Size: 244157 bytes --]

#
# Automatically generated file; DO NOT EDIT.
# Linux/sh 6.1.0-rc8 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="sh4-linux-gcc (GCC) 12.1.0"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=120100
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=23800
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=23800
CONFIG_LLD_VERSION=0
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_PAHOLE_VERSION=123
CONFIG_CONSTRUCTORS=y
CONFIG_IRQ_WORK=y

#
# General setup
#
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_COMPILE_TEST=y
# CONFIG_WERROR is not set
CONFIG_LOCALVERSION=""
CONFIG_BUILD_SALT=""
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_BZIP2=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
CONFIG_WATCH_QUEUE=y
CONFIG_USELIB=y
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_INJECTION=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_SIM=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
CONFIG_GENERIC_IRQ_DEBUGFS=y
# end of IRQ subsystem

CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_TIME_KUNIT_TEST=m

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

CONFIG_BPF=y

#
# BPF subsystem
#
CONFIG_BPF_SYSCALL=y
CONFIG_BPF_UNPRIV_DEFAULT_OFF=y
CONFIG_USERMODE_DRIVER=y
# end of BPF subsystem

CONFIG_PREEMPT_NONE_BUILD=y
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_PREEMPT_COUNT=y

#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_PSI=y
CONFIG_PSI_DEFAULT_DISABLED=y
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TINY_RCU=y
CONFIG_RCU_EXPERT=y
CONFIG_SRCU=y
CONFIG_TINY_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_FORCE_TASKS_RCU=y
CONFIG_TASKS_RCU=y
CONFIG_FORCE_TASKS_RUDE_RCU=y
CONFIG_TASKS_RUDE_RCU=y
CONFIG_FORCE_TASKS_TRACE_RCU=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_NEED_SEGCBLIST=y
CONFIG_TASKS_TRACE_RCU_READ_MB=y
# end of RCU Subsystem

CONFIG_BUILD_BIN2C=y
CONFIG_IKCONFIG=m
CONFIG_IKCONFIG_PROC=y
CONFIG_IKHEADERS=m
CONFIG_LOG_BUF_SHIFT=17
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
CONFIG_PRINTK_INDEX=y
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
# end of Scheduler features

CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_GCC12_NO_ARRAY_BOUNDS=y
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
CONFIG_CGROUP_FAVOR_DYNMODS=y
CONFIG_MEMCG=y
CONFIG_MEMCG_KMEM=y
CONFIG_BLK_CGROUP=y
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
CONFIG_CGROUP_MISC=y
CONFIG_CGROUP_DEBUG=y
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_SCHED_AUTOGROUP=y
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
CONFIG_BOOT_CONFIG_EMBED=y
CONFIG_BOOT_CONFIG_EMBED_FILE=""
CONFIG_INITRAMFS_PRESERVE_MTIME=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_HAVE_UID16=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
CONFIG_SYSFS_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_AIO=y
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_KCMP=y
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PC104=y

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
CONFIG_DEBUG_PERF_USE_VMALLOC=y
# end of Kernel Performance Events And Counters

CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
# end of General setup

CONFIG_SUPERH=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_NO_IOPORT_MAP=y
CONFIG_PGTABLE_LEVELS=2

#
# System type
#
CONFIG_CPU_SH2=y
CONFIG_CPU_SUBTYPE_SH7619=y
# CONFIG_CPU_SUBTYPE_J2 is not set
# CONFIG_CPU_SUBTYPE_SH7201 is not set
# CONFIG_CPU_SUBTYPE_SH7203 is not set
# CONFIG_CPU_SUBTYPE_SH7206 is not set
# CONFIG_CPU_SUBTYPE_SH7263 is not set
# CONFIG_CPU_SUBTYPE_SH7264 is not set
# CONFIG_CPU_SUBTYPE_SH7269 is not set
# CONFIG_CPU_SUBTYPE_MXG is not set
# CONFIG_CPU_SUBTYPE_SH7705 is not set
# CONFIG_CPU_SUBTYPE_SH7706 is not set
# CONFIG_CPU_SUBTYPE_SH7707 is not set
# CONFIG_CPU_SUBTYPE_SH7708 is not set
# CONFIG_CPU_SUBTYPE_SH7709 is not set
# CONFIG_CPU_SUBTYPE_SH7710 is not set
# CONFIG_CPU_SUBTYPE_SH7712 is not set
# CONFIG_CPU_SUBTYPE_SH7720 is not set
# CONFIG_CPU_SUBTYPE_SH7721 is not set
# CONFIG_CPU_SUBTYPE_SH7750 is not set
# CONFIG_CPU_SUBTYPE_SH7091 is not set
# CONFIG_CPU_SUBTYPE_SH7750R is not set
# CONFIG_CPU_SUBTYPE_SH7750S is not set
# CONFIG_CPU_SUBTYPE_SH7751 is not set
# CONFIG_CPU_SUBTYPE_SH7751R is not set
# CONFIG_CPU_SUBTYPE_SH7760 is not set
# CONFIG_CPU_SUBTYPE_SH4_202 is not set
# CONFIG_CPU_SUBTYPE_SH7723 is not set
# CONFIG_CPU_SUBTYPE_SH7724 is not set
# CONFIG_CPU_SUBTYPE_SH7734 is not set
# CONFIG_CPU_SUBTYPE_SH7757 is not set
# CONFIG_CPU_SUBTYPE_SH7763 is not set
# CONFIG_CPU_SUBTYPE_SH7770 is not set
# CONFIG_CPU_SUBTYPE_SH7780 is not set
# CONFIG_CPU_SUBTYPE_SH7785 is not set
# CONFIG_CPU_SUBTYPE_SH7786 is not set
# CONFIG_CPU_SUBTYPE_SHX3 is not set
# CONFIG_CPU_SUBTYPE_SH7343 is not set
# CONFIG_CPU_SUBTYPE_SH7722 is not set
# CONFIG_CPU_SUBTYPE_SH7366 is not set

#
# Memory management options
#
CONFIG_PAGE_OFFSET=0x00000000
CONFIG_ARCH_FORCE_MAX_ORDER=14
CONFIG_MEMORY_START=0x08000000
CONFIG_MEMORY_SIZE=0x04000000
CONFIG_32BIT=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PAGE_SIZE_16KB is not set
# CONFIG_PAGE_SIZE_64KB is not set
# end of Memory management options

#
# Cache configuration
#
# CONFIG_CACHE_WRITEBACK is not set
CONFIG_CACHE_WRITETHROUGH=y
# CONFIG_CACHE_OFF is not set
# end of Cache configuration

#
# Processor features
#
CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_SH_FPU_EMU=y
# end of Processor features

#
# Board support
#
CONFIG_SOLUTION_ENGINE=y
CONFIG_SH_CUSTOM_CLK=y
CONFIG_SH_7619_SOLUTION_ENGINE=y
# end of Board support

#
# Timer and clock configuration
#
CONFIG_SH_PCLK_FREQ=31250000
CONFIG_SH_CLK_CPG=y
CONFIG_SH_CLK_CPG_LEGACY=y
# end of Timer and clock configuration

#
# CPU Frequency scaling
#

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_USERSPACE=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=m
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=m
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_SH_CPU_FREQ=m
# end of CPU Frequency scaling
# end of CPU Frequency scaling

#
# DMA support
#
# end of DMA support

#
# Companion Chips
#
# end of Companion Chips

#
# Additional SuperH Device Drivers
#
CONFIG_HEARTBEAT=y
CONFIG_PUSH_SWITCH=m
# end of Additional SuperH Device Drivers
# end of System type

#
# Kernel features
#
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
CONFIG_SCHED_HRTICK=y
CONFIG_CRASH_DUMP=y
CONFIG_PHYSICAL_START=0x08000000
CONFIG_GUSA=y

#
# SuperH / SH-Mobile Driver Options
#
CONFIG_SH_INTC=y

#
# Interrupt controller options
#
CONFIG_INTC_USERIMASK=y
CONFIG_INTC_MAPPING_DEBUG=y
# end of SuperH / SH-Mobile Driver Options
# end of Kernel features

#
# Boot options
#
CONFIG_ZERO_PAGE_OFFSET=0x00001000
CONFIG_BOOT_LINK_OFFSET=0x00800000
CONFIG_ENTRY_OFFSET=0x00001000
CONFIG_CMDLINE_OVERWRITE=y
# CONFIG_CMDLINE_EXTEND is not set
CONFIG_CMDLINE="console=ttySC1,115200"
# end of Boot options

#
# Bus options
#
# end of Bus options

#
# Power management options (EXPERIMENTAL)
#
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
CONFIG_DPM_WATCHDOG=y
CONFIG_DPM_WATCHDOG_TIMEOUT=120
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
CONFIG_PM_GENERIC_DOMAINS_OF=y

#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_GOV_TEO=y
# end of CPU Idle
# end of Power management options (EXPERIMENTAL)

#
# General architecture-dependent options
#
CONFIG_KPROBES=y
CONFIG_KRETPROBES=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_SECCOMP_FILTER=y
CONFIG_SECCOMP_CACHE_DEBUG=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_LTO_NONE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_ISA_BUS_API=y
CONFIG_OLD_SIGSUSPEND=y
CONFIG_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPU_NO_EFFICIENT_FFS=y
CONFIG_LOCK_EVENT_COUNTS=y

#
# GCOV-based kernel profiling
#
CONFIG_GCOV_KERNEL=y
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULE_SIG_FORMAT=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODULE_UNLOAD_TAINT_TRACKING=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_MODULE_SIG=y
CONFIG_MODULE_SIG_FORCE=y
CONFIG_MODULE_SIG_ALL=y
CONFIG_MODULE_SIG_SHA1=y
# CONFIG_MODULE_SIG_SHA224 is not set
# CONFIG_MODULE_SIG_SHA256 is not set
# CONFIG_MODULE_SIG_SHA384 is not set
# CONFIG_MODULE_SIG_SHA512 is not set
CONFIG_MODULE_SIG_HASH="sha1"
CONFIG_MODULE_COMPRESS_NONE=y
# CONFIG_MODULE_COMPRESS_GZIP is not set
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y
CONFIG_MODPROBE_PATH="/sbin/modprobe"
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLOCK_LEGACY_AUTOLOAD=y
CONFIG_BLK_RQ_ALLOC_TIME=y
CONFIG_BLK_CGROUP_RWSTAT=y
CONFIG_BLK_DEV_BSG_COMMON=y
CONFIG_BLK_ICQ=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_INTEGRITY_T10=m
CONFIG_BLK_DEV_ZONED=y
CONFIG_BLK_DEV_THROTTLING=y
CONFIG_BLK_DEV_THROTTLING_LOW=y
CONFIG_BLK_WBT=y
CONFIG_BLK_WBT_MQ=y
CONFIG_BLK_CGROUP_IOLATENCY=y
CONFIG_BLK_CGROUP_IOCOST=y
CONFIG_BLK_CGROUP_IOPRIO=y
CONFIG_BLK_DEBUG_FS=y
CONFIG_BLK_DEBUG_FS_ZONED=y
CONFIG_BLK_SED_OPAL=y
CONFIG_BLK_INLINE_ENCRYPTION=y
CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
CONFIG_ACORN_PARTITION=y
CONFIG_ACORN_PARTITION_CUMANA=y
CONFIG_ACORN_PARTITION_EESOX=y
CONFIG_ACORN_PARTITION_ICS=y
CONFIG_ACORN_PARTITION_ADFS=y
CONFIG_ACORN_PARTITION_POWERTEC=y
CONFIG_ACORN_PARTITION_RISCIX=y
CONFIG_AIX_PARTITION=y
CONFIG_OSF_PARTITION=y
CONFIG_AMIGA_PARTITION=y
CONFIG_ATARI_PARTITION=y
CONFIG_MAC_PARTITION=y
CONFIG_MSDOS_PARTITION=y
CONFIG_BSD_DISKLABEL=y
CONFIG_MINIX_SUBPARTITION=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_UNIXWARE_DISKLABEL=y
CONFIG_LDM_PARTITION=y
CONFIG_LDM_DEBUG=y
CONFIG_SGI_PARTITION=y
CONFIG_ULTRIX_PARTITION=y
CONFIG_SUN_PARTITION=y
CONFIG_KARMA_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_SYSV68_PARTITION=y
CONFIG_CMDLINE_PARTITION=y
# end of Partition Types

CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_HOLDER_DEPRECATED=y
CONFIG_BLK_MQ_STACKING=y

#
# IO Schedulers
#
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=m
CONFIG_IOSCHED_BFQ=m
CONFIG_BFQ_GROUP_IOSCHED=y
CONFIG_BFQ_CGROUP_DEBUG=y
# end of IO Schedulers

CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_FREEZER=y

#
# Executable file formats
#
CONFIG_BINFMT_ELF_FDPIC=y
CONFIG_ELFCORE=y
CONFIG_BINFMT_SCRIPT=m
CONFIG_ARCH_HAS_BINFMT_FLAT=y
CONFIG_BINFMT_FLAT=y
CONFIG_BINFMT_FLAT_OLD=y
CONFIG_BINFMT_ZFLAT=y
CONFIG_BINFMT_MISC=m
CONFIG_COREDUMP=y
# end of Executable file formats

#
# Memory Management options
#

#
# SLAB allocator options
#
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
CONFIG_SLAB_FREELIST_RANDOM=y
CONFIG_SLAB_FREELIST_HARDENED=y
CONFIG_SLUB_STATS=y
# end of SLAB allocator options

CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
CONFIG_COMPAT_BRK=y
CONFIG_MMAP_ALLOW_UNINITIALIZED=y
CONFIG_SELECT_MEMORY_MODEL=y
# CONFIG_FLATMEM_MANUAL is not set
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_STATIC=y
CONFIG_SPLIT_PTLOCK_CPUS=999999
CONFIG_MEMORY_BALLOON=y
CONFIG_PAGE_REPORTING=y
CONFIG_NOMMU_INITIAL_TRIM_EXCESS=1
CONFIG_NEED_PER_CPU_KM=y
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_PERCPU_STATS=y
CONFIG_GUP_TEST=y
CONFIG_ARCH_HAS_PTE_SPECIAL=y

#
# Data Access Monitoring
#
CONFIG_DAMON=y
CONFIG_DAMON_SYSFS=y
# end of Data Access Monitoring
# end of Memory Management options

CONFIG_NET=y
CONFIG_NET_INGRESS=y
CONFIG_NET_EGRESS=y
CONFIG_NET_REDIRECT=y
CONFIG_SKB_EXTENSIONS=y

#
# Networking options
#
CONFIG_PACKET=m
CONFIG_PACKET_DIAG=m
CONFIG_UNIX=m
CONFIG_UNIX_SCM=y
CONFIG_AF_UNIX_OOB=y
CONFIG_UNIX_DIAG=m
CONFIG_TLS=m
CONFIG_TLS_DEVICE=y
CONFIG_TLS_TOE=y
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=m
CONFIG_XFRM_USER=m
CONFIG_XFRM_INTERFACE=m
CONFIG_XFRM_SUB_POLICY=y
CONFIG_XFRM_MIGRATE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_XFRM_AH=m
CONFIG_XFRM_ESP=m
CONFIG_XFRM_IPCOMP=m
CONFIG_NET_KEY=m
CONFIG_NET_KEY_MIGRATE=y
CONFIG_XFRM_ESPINTCP=y
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=m
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_FIB_TRIE_STATS=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_ROUTE_CLASSID=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE_DEMUX=m
CONFIG_NET_IP_TUNNEL=m
CONFIG_NET_IPGRE=m
CONFIG_NET_IPGRE_BROADCAST=y
CONFIG_IP_MROUTE_COMMON=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=m
CONFIG_NET_UDP_TUNNEL=m
CONFIG_NET_FOU=m
CONFIG_NET_FOU_IP_TUNNELS=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_ESP_OFFLOAD=m
CONFIG_INET_ESPINTCP=y
CONFIG_INET_IPCOMP=m
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_DIAG=m
CONFIG_INET_TCP_DIAG=m
CONFIG_INET_UDP_DIAG=m
CONFIG_INET_RAW_DIAG=m
CONFIG_INET_DIAG_DESTROY=y
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=m
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_NV=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
CONFIG_TCP_CONG_DCTCP=m
CONFIG_TCP_CONG_CDG=m
CONFIG_TCP_CONG_BBR=m
CONFIG_DEFAULT_RENO=y
CONFIG_DEFAULT_TCP_CONG="reno"
CONFIG_TCP_MD5SIG=y
CONFIG_IPV6=m
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_IPV6_OPTIMISTIC_DAD=y
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_ESP_OFFLOAD=m
CONFIG_INET6_ESPINTCP=y
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_MIP6=m
CONFIG_IPV6_ILA=m
CONFIG_INET6_XFRM_TUNNEL=m
CONFIG_INET6_TUNNEL=m
CONFIG_IPV6_VTI=m
CONFIG_IPV6_SIT=m
CONFIG_IPV6_SIT_6RD=y
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=m
CONFIG_IPV6_GRE=m
CONFIG_IPV6_FOU=m
CONFIG_IPV6_FOU_TUNNEL=m
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
CONFIG_IPV6_PIMSM_V2=y
CONFIG_IPV6_SEG6_LWTUNNEL=y
CONFIG_IPV6_SEG6_HMAC=y
CONFIG_IPV6_RPL_LWTUNNEL=y
CONFIG_IPV6_IOAM6_LWTUNNEL=y
CONFIG_NETLABEL=y
CONFIG_MPTCP=y
CONFIG_INET_MPTCP_DIAG=m
CONFIG_MPTCP_KUNIT_TEST=m
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NETWORK_PHY_TIMESTAMPING=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=m

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_EGRESS=y
CONFIG_NETFILTER_SKIP_EGRESS=y
CONFIG_NETFILTER_NETLINK=m
CONFIG_NETFILTER_FAMILY_BRIDGE=y
CONFIG_NETFILTER_FAMILY_ARP=y
CONFIG_NETFILTER_NETLINK_HOOK=m
CONFIG_NETFILTER_NETLINK_ACCT=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NETFILTER_NETLINK_OSF=m
CONFIG_NF_CONNTRACK=m
CONFIG_NF_LOG_SYSLOG=m
CONFIG_NETFILTER_CONNCOUNT=m
CONFIG_NF_CONNTRACK_MARK=y
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_ZONES=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CONNTRACK_TIMEOUT=y
CONFIG_NF_CONNTRACK_TIMESTAMP=y
CONFIG_NF_CONNTRACK_LABELS=y
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_GRE=y
CONFIG_NF_CT_PROTO_SCTP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_BROADCAST=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_SNMP=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
CONFIG_NF_CT_NETLINK_TIMEOUT=m
CONFIG_NF_CT_NETLINK_HELPER=m
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=m
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_SIP=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NF_TABLES=m
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_OBJREF=m
CONFIG_NFT_QUEUE=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_FIB=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_XFRM=m
CONFIG_NFT_SOCKET=m
CONFIG_NFT_OSF=m
CONFIG_NFT_TPROXY=m
CONFIG_NFT_SYNPROXY=m
CONFIG_NF_DUP_NETDEV=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
CONFIG_NFT_REJECT_NETDEV=m
CONFIG_NF_FLOW_TABLE_INET=m
CONFIG_NF_FLOW_TABLE=m
CONFIG_NF_FLOW_TABLE_PROCFS=y
CONFIG_NETFILTER_XTABLES=m

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=m
CONFIG_NETFILTER_XT_CONNMARK=m
CONFIG_NETFILTER_XT_SET=m

#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_AUDIT=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
CONFIG_NETFILTER_XT_TARGET_CT=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_HMARK=m
CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
CONFIG_NETFILTER_XT_TARGET_LED=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_NAT=m
CONFIG_NETFILTER_XT_TARGET_NETMAP=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
CONFIG_NETFILTER_XT_TARGET_RATEEST=m
CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
CONFIG_NETFILTER_XT_TARGET_TEE=m
CONFIG_NETFILTER_XT_TARGET_TPROXY=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
CONFIG_NETFILTER_XT_TARGET_SECMARK=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m

#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
CONFIG_NETFILTER_XT_MATCH_BPF=m
CONFIG_NETFILTER_XT_MATCH_CGROUP=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_CPU=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ECN=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=m
CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_NETFILTER_XT_MATCH_L2TP=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_NFACCT=m
CONFIG_NETFILTER_XT_MATCH_OSF=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_SOCKET=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
# end of Core Netfilter Configuration

CONFIG_IP_SET=m
CONFIG_IP_SET_MAX=256
CONFIG_IP_SET_BITMAP_IP=m
CONFIG_IP_SET_BITMAP_IPMAC=m
CONFIG_IP_SET_BITMAP_PORT=m
CONFIG_IP_SET_HASH_IP=m
CONFIG_IP_SET_HASH_IPMARK=m
CONFIG_IP_SET_HASH_IPPORT=m
CONFIG_IP_SET_HASH_IPPORTIP=m
CONFIG_IP_SET_HASH_IPPORTNET=m
CONFIG_IP_SET_HASH_IPMAC=m
CONFIG_IP_SET_HASH_MAC=m
CONFIG_IP_SET_HASH_NETPORTNET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_IP_SET_HASH_NETNET=m
CONFIG_IP_SET_HASH_NETPORT=m
CONFIG_IP_SET_HASH_NETIFACE=m
CONFIG_IP_SET_LIST_SET=m
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
CONFIG_IP_VS_DEBUG=y
CONFIG_IP_VS_TAB_BITS=12

#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
CONFIG_IP_VS_PROTO_SCTP=y

#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_FO=m
CONFIG_IP_VS_OVF=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_MH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m
CONFIG_IP_VS_TWOS=m

#
# IPVS SH scheduler
#
CONFIG_IP_VS_SH_TAB_BITS=8

#
# IPVS MH scheduler
#
CONFIG_IP_VS_MH_TAB_INDEX=12

#
# IPVS application helper
#
CONFIG_IP_VS_FTP=m
CONFIG_IP_VS_NFCT=y
CONFIG_IP_VS_PE_SIP=m

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=m
CONFIG_NF_SOCKET_IPV4=m
CONFIG_NF_TPROXY_IPV4=m
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_DUP_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NF_LOG_IPV4=m
CONFIG_NF_REJECT_IPV4=m
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_RPFILTER=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_SYNPROXY=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_CLUSTERIP=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_SECURITY=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
# end of IP: Netfilter Configuration

#
# IPv6: Netfilter Configuration
#
CONFIG_NF_SOCKET_IPV6=m
CONFIG_NF_TPROXY_IPV6=m
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_DUP_IPV6=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_NF_LOG_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_TARGET_SYNPROXY=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP6_NF_SECURITY=m
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_IP6_NF_TARGET_NPT=m
# end of IPv6: Netfilter Configuration

CONFIG_NF_DEFRAG_IPV6=m
CONFIG_NF_TABLES_BRIDGE=m
CONFIG_NFT_BRIDGE_META=m
CONFIG_NFT_BRIDGE_REJECT=m
CONFIG_NF_CONNTRACK_BRIDGE=m
CONFIG_BRIDGE_NF_EBTABLES=m
CONFIG_BRIDGE_EBT_BROUTE=m
CONFIG_BRIDGE_EBT_T_FILTER=m
CONFIG_BRIDGE_EBT_T_NAT=m
CONFIG_BRIDGE_EBT_802_3=m
CONFIG_BRIDGE_EBT_AMONG=m
CONFIG_BRIDGE_EBT_ARP=m
CONFIG_BRIDGE_EBT_IP=m
CONFIG_BRIDGE_EBT_IP6=m
CONFIG_BRIDGE_EBT_LIMIT=m
CONFIG_BRIDGE_EBT_MARK=m
CONFIG_BRIDGE_EBT_PKTTYPE=m
CONFIG_BRIDGE_EBT_STP=m
CONFIG_BRIDGE_EBT_VLAN=m
CONFIG_BRIDGE_EBT_ARPREPLY=m
CONFIG_BRIDGE_EBT_DNAT=m
CONFIG_BRIDGE_EBT_MARK_T=m
CONFIG_BRIDGE_EBT_REDIRECT=m
CONFIG_BRIDGE_EBT_SNAT=m
CONFIG_BRIDGE_EBT_LOG=m
CONFIG_BRIDGE_EBT_NFLOG=m
CONFIG_BPFILTER=y
CONFIG_IP_DCCP=m
CONFIG_INET_DCCP_DIAG=m

#
# DCCP CCIDs Configuration
#
CONFIG_IP_DCCP_CCID2_DEBUG=y
CONFIG_IP_DCCP_CCID3=y
CONFIG_IP_DCCP_CCID3_DEBUG=y
CONFIG_IP_DCCP_TFRC_LIB=y
CONFIG_IP_DCCP_TFRC_DEBUG=y
# end of DCCP CCIDs Configuration

#
# DCCP Kernel Hacking
#
CONFIG_IP_DCCP_DEBUG=y
# end of DCCP Kernel Hacking

CONFIG_IP_SCTP=m
CONFIG_SCTP_DBG_OBJCNT=y
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_INET_SCTP_DIAG=m
CONFIG_RDS=m
CONFIG_RDS_TCP=m
CONFIG_RDS_DEBUG=y
CONFIG_TIPC=m
CONFIG_TIPC_MEDIA_UDP=y
CONFIG_TIPC_CRYPTO=y
CONFIG_TIPC_DIAG=m
CONFIG_ATM=m
CONFIG_ATM_CLIP=m
CONFIG_ATM_CLIP_NO_ICMP=y
CONFIG_ATM_LANE=m
CONFIG_ATM_MPOA=m
CONFIG_ATM_BR2684=m
CONFIG_ATM_BR2684_IPFILTER=y
CONFIG_L2TP=m
CONFIG_L2TP_DEBUGFS=m
CONFIG_L2TP_V3=y
CONFIG_L2TP_IP=m
CONFIG_L2TP_ETH=m
CONFIG_STP=m
CONFIG_GARP=m
CONFIG_MRP=m
CONFIG_BRIDGE=m
CONFIG_BRIDGE_IGMP_SNOOPING=y
CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_BRIDGE_MRP=y
CONFIG_BRIDGE_CFM=y
CONFIG_NET_DSA=m
CONFIG_NET_DSA_TAG_AR9331=m
CONFIG_NET_DSA_TAG_BRCM_COMMON=m
CONFIG_NET_DSA_TAG_BRCM=m
CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
CONFIG_NET_DSA_TAG_HELLCREEK=m
CONFIG_NET_DSA_TAG_GSWIP=m
CONFIG_NET_DSA_TAG_DSA_COMMON=m
CONFIG_NET_DSA_TAG_DSA=m
CONFIG_NET_DSA_TAG_EDSA=m
CONFIG_NET_DSA_TAG_MTK=m
CONFIG_NET_DSA_TAG_KSZ=m
CONFIG_NET_DSA_TAG_OCELOT=m
CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
CONFIG_NET_DSA_TAG_QCA=m
CONFIG_NET_DSA_TAG_RTL4_A=m
CONFIG_NET_DSA_TAG_RTL8_4=m
CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
CONFIG_NET_DSA_TAG_LAN9303=m
CONFIG_NET_DSA_TAG_SJA1105=m
CONFIG_NET_DSA_TAG_TRAILER=m
CONFIG_NET_DSA_TAG_XRS700X=m
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
CONFIG_VLAN_8021Q_MVRP=y
CONFIG_LLC=m
CONFIG_LLC2=m
CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
CONFIG_X25=m
CONFIG_LAPB=m
CONFIG_PHONET=m
CONFIG_6LOWPAN=m
CONFIG_6LOWPAN_DEBUGFS=y
CONFIG_6LOWPAN_NHC=m
CONFIG_6LOWPAN_NHC_DEST=m
CONFIG_6LOWPAN_NHC_FRAGMENT=m
CONFIG_6LOWPAN_NHC_HOP=m
CONFIG_6LOWPAN_NHC_IPV6=m
CONFIG_6LOWPAN_NHC_MOBILITY=m
CONFIG_6LOWPAN_NHC_ROUTING=m
CONFIG_6LOWPAN_NHC_UDP=m
CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
CONFIG_6LOWPAN_GHC_UDP=m
CONFIG_6LOWPAN_GHC_ICMPV6=m
CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
CONFIG_IEEE802154=m
CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
CONFIG_IEEE802154_SOCKET=m
CONFIG_IEEE802154_6LOWPAN=m
CONFIG_MAC802154=m
CONFIG_NET_SCHED=y

#
# Queueing/Scheduling
#
CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_ATM=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFB=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_CBS=m
CONFIG_NET_SCH_ETF=m
CONFIG_NET_SCH_TAPRIO=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
CONFIG_NET_SCH_MQPRIO=m
CONFIG_NET_SCH_SKBPRIO=m
CONFIG_NET_SCH_CHOKE=m
CONFIG_NET_SCH_QFQ=m
CONFIG_NET_SCH_CODEL=m
CONFIG_NET_SCH_FQ_CODEL=m
CONFIG_NET_SCH_CAKE=m
CONFIG_NET_SCH_FQ=m
CONFIG_NET_SCH_HHF=m
CONFIG_NET_SCH_PIE=m
CONFIG_NET_SCH_FQ_PIE=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_SCH_PLUG=m
CONFIG_NET_SCH_ETS=m
CONFIG_NET_SCH_DEFAULT=y
# CONFIG_DEFAULT_FQ is not set
# CONFIG_DEFAULT_CODEL is not set
# CONFIG_DEFAULT_FQ_CODEL is not set
# CONFIG_DEFAULT_FQ_PIE is not set
# CONFIG_DEFAULT_SFQ is not set
CONFIG_DEFAULT_PFIFO_FAST=y
CONFIG_DEFAULT_NET_SCH="pfifo_fast"

#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_CLS_U32_PERF=y
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_RSVP=m
CONFIG_NET_CLS_RSVP6=m
CONFIG_NET_CLS_FLOW=m
CONFIG_NET_CLS_CGROUP=m
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_MATCHALL=m
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_EMATCH_CANID=m
CONFIG_NET_EMATCH_IPSET=m
CONFIG_NET_EMATCH_IPT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_SAMPLE=m
CONFIG_NET_ACT_IPT=m
CONFIG_NET_ACT_NAT=m
CONFIG_NET_ACT_PEDIT=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_CSUM=m
CONFIG_NET_ACT_MPLS=m
CONFIG_NET_ACT_VLAN=m
CONFIG_NET_ACT_BPF=m
CONFIG_NET_ACT_CONNMARK=m
CONFIG_NET_ACT_CTINFO=m
CONFIG_NET_ACT_SKBMOD=m
CONFIG_NET_ACT_IFE=m
CONFIG_NET_ACT_TUNNEL_KEY=m
CONFIG_NET_ACT_CT=m
CONFIG_NET_ACT_GATE=m
CONFIG_NET_IFE_SKBMARK=m
CONFIG_NET_IFE_SKBPRIO=m
CONFIG_NET_IFE_SKBTCINDEX=m
CONFIG_NET_TC_SKB_EXT=y
CONFIG_NET_SCH_FIFO=y
CONFIG_DCB=y
CONFIG_DNS_RESOLVER=m
CONFIG_BATMAN_ADV=m
CONFIG_BATMAN_ADV_BATMAN_V=y
CONFIG_BATMAN_ADV_BLA=y
CONFIG_BATMAN_ADV_DAT=y
CONFIG_BATMAN_ADV_NC=y
CONFIG_BATMAN_ADV_MCAST=y
CONFIG_BATMAN_ADV_DEBUG=y
CONFIG_BATMAN_ADV_TRACING=y
CONFIG_OPENVSWITCH=m
CONFIG_OPENVSWITCH_GRE=m
CONFIG_OPENVSWITCH_VXLAN=m
CONFIG_OPENVSWITCH_GENEVE=m
CONFIG_VSOCKETS=m
CONFIG_VSOCKETS_DIAG=m
CONFIG_VSOCKETS_LOOPBACK=m
CONFIG_VIRTIO_VSOCKETS=m
CONFIG_VIRTIO_VSOCKETS_COMMON=m
CONFIG_NETLINK_DIAG=m
CONFIG_MPLS=y
CONFIG_NET_MPLS_GSO=m
CONFIG_MPLS_ROUTING=m
CONFIG_MPLS_IPTUNNEL=m
CONFIG_NET_NSH=m
CONFIG_HSR=m
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
CONFIG_QRTR=m
CONFIG_QRTR_SMD=m
CONFIG_QRTR_TUN=m
CONFIG_QRTR_MHI=m
CONFIG_NET_NCSI=y
CONFIG_NCSI_OEM_CMD_GET_MAC=y
CONFIG_NCSI_OEM_CMD_KEEP_PHY=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_HWBM=y
CONFIG_CGROUP_NET_PRIO=y
CONFIG_CGROUP_NET_CLASSID=y
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_STREAM_PARSER=y

#
# Network testing
#
CONFIG_NET_PKTGEN=m
CONFIG_NET_DROP_MONITOR=m
# end of Network testing
# end of Networking options

CONFIG_HAMRADIO=y

#
# Packet Radio protocols
#
CONFIG_AX25=m
CONFIG_AX25_DAMA_SLAVE=y
CONFIG_NETROM=m
CONFIG_ROSE=m

#
# AX.25 network device drivers
#
CONFIG_MKISS=m
CONFIG_6PACK=m
CONFIG_BPQETHER=m
CONFIG_BAYCOM_SER_FDX=m
CONFIG_BAYCOM_SER_HDX=m
CONFIG_BAYCOM_PAR=m
CONFIG_BAYCOM_EPP=m
CONFIG_YAM=m
# end of AX.25 network device drivers

CONFIG_CAN=m
CONFIG_CAN_RAW=m
CONFIG_CAN_BCM=m
CONFIG_CAN_GW=m
CONFIG_CAN_J1939=m
CONFIG_CAN_ISOTP=m
CONFIG_BT=m
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_CMTP=m
CONFIG_BT_HIDP=m
CONFIG_BT_HS=y
CONFIG_BT_LE=y
CONFIG_BT_6LOWPAN=m
CONFIG_BT_LEDS=y
CONFIG_BT_MSFTEXT=y
CONFIG_BT_AOSPEXT=y
CONFIG_BT_DEBUGFS=y
CONFIG_BT_SELFTEST=y
CONFIG_BT_SELFTEST_ECDH=y
CONFIG_BT_SELFTEST_SMP=y

#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=m
CONFIG_BT_BCM=m
CONFIG_BT_RTL=m
CONFIG_BT_QCA=m
CONFIG_BT_MTK=m
CONFIG_BT_HCIBTUSB=m
CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y
CONFIG_BT_HCIBTUSB_BCM=y
CONFIG_BT_HCIBTUSB_MTK=y
CONFIG_BT_HCIBTUSB_RTL=y
CONFIG_BT_HCIBTSDIO=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_SERDEV=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_NOKIA=m
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_INTEL=y
CONFIG_BT_HCIUART_BCM=y
CONFIG_BT_HCIUART_QCA=y
CONFIG_BT_HCIUART_AG6XX=y
CONFIG_BT_HCIUART_MRVL=y
CONFIG_BT_HCIBCM203X=m
CONFIG_BT_HCIBPA10X=m
CONFIG_BT_HCIBFUSB=m
CONFIG_BT_HCIDTL1=m
CONFIG_BT_HCIBT3C=m
CONFIG_BT_HCIBLUECARD=m
CONFIG_BT_HCIVHCI=m
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_ATH3K=m
CONFIG_BT_MTKSDIO=m
CONFIG_BT_MTKUART=m
CONFIG_BT_QCOMSMD=m
CONFIG_BT_HCIRSI=m
CONFIG_BT_VIRTIO=m
# end of Bluetooth device drivers

CONFIG_AF_RXRPC=m
CONFIG_AF_RXRPC_IPV6=y
CONFIG_AF_RXRPC_INJECT_LOSS=y
CONFIG_AF_RXRPC_DEBUG=y
CONFIG_RXKAD=y
CONFIG_AF_KCM=m
CONFIG_STREAM_PARSER=y
CONFIG_MCTP=y
CONFIG_MCTP_FLOWS=y
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WIRELESS_EXT=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_WEXT_SPY=y
CONFIG_WEXT_PRIV=y
CONFIG_CFG80211=m
CONFIG_NL80211_TESTMODE=y
CONFIG_CFG80211_DEVELOPER_WARNINGS=y
CONFIG_CFG80211_CERTIFICATION_ONUS=y
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_EXTRA_REGDB_KEYDIR=""
CONFIG_CFG80211_REG_CELLULAR_HINTS=y
CONFIG_CFG80211_REG_RELAX_NO_IR=y
CONFIG_CFG80211_DEFAULT_PS=y
CONFIG_CFG80211_DEBUGFS=y
CONFIG_CFG80211_CRDA_SUPPORT=y
CONFIG_CFG80211_WEXT=y
CONFIG_CFG80211_WEXT_EXPORT=y
CONFIG_LIB80211=m
CONFIG_LIB80211_CRYPT_WEP=m
CONFIG_LIB80211_CRYPT_CCMP=m
CONFIG_LIB80211_CRYPT_TKIP=m
CONFIG_LIB80211_DEBUG=y
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_MESH=y
CONFIG_MAC80211_LEDS=y
CONFIG_MAC80211_DEBUGFS=y
CONFIG_MAC80211_MESSAGE_TRACING=y
CONFIG_MAC80211_DEBUG_MENU=y
CONFIG_MAC80211_NOINLINE=y
CONFIG_MAC80211_VERBOSE_DEBUG=y
CONFIG_MAC80211_MLME_DEBUG=y
CONFIG_MAC80211_STA_DEBUG=y
CONFIG_MAC80211_HT_DEBUG=y
CONFIG_MAC80211_OCB_DEBUG=y
CONFIG_MAC80211_IBSS_DEBUG=y
CONFIG_MAC80211_PS_DEBUG=y
CONFIG_MAC80211_MPL_DEBUG=y
CONFIG_MAC80211_MPATH_DEBUG=y
CONFIG_MAC80211_MHWMP_DEBUG=y
CONFIG_MAC80211_MESH_SYNC_DEBUG=y
CONFIG_MAC80211_MESH_CSA_DEBUG=y
CONFIG_MAC80211_MESH_PS_DEBUG=y
CONFIG_MAC80211_TDLS_DEBUG=y
CONFIG_MAC80211_DEBUG_COUNTERS=y
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
CONFIG_RFKILL=m
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=m
CONFIG_NET_9P=m
CONFIG_NET_9P_FD=m
CONFIG_NET_9P_VIRTIO=m
CONFIG_NET_9P_DEBUG=y
CONFIG_CAIF=m
CONFIG_CAIF_DEBUG=y
CONFIG_CAIF_NETDEV=m
CONFIG_CAIF_USB=m
CONFIG_CEPH_LIB=m
CONFIG_CEPH_LIB_PRETTYDEBUG=y
CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y
CONFIG_NFC=m
CONFIG_NFC_DIGITAL=m
CONFIG_NFC_NCI=m
CONFIG_NFC_NCI_SPI=m
CONFIG_NFC_NCI_UART=m
CONFIG_NFC_HCI=m
CONFIG_NFC_SHDLC=y

#
# Near Field Communication (NFC) devices
#
CONFIG_NFC_TRF7970A=m
CONFIG_NFC_SIM=m
CONFIG_NFC_PORT100=m
CONFIG_NFC_VIRTUAL_NCI=m
CONFIG_NFC_FDP=m
CONFIG_NFC_FDP_I2C=m
CONFIG_NFC_PN544=m
CONFIG_NFC_PN544_I2C=m
CONFIG_NFC_PN533=m
CONFIG_NFC_PN533_USB=m
CONFIG_NFC_PN533_I2C=m
CONFIG_NFC_PN532_UART=m
CONFIG_NFC_MICROREAD=m
CONFIG_NFC_MICROREAD_I2C=m
CONFIG_NFC_MRVL=m
CONFIG_NFC_MRVL_USB=m
CONFIG_NFC_MRVL_UART=m
CONFIG_NFC_MRVL_I2C=m
CONFIG_NFC_MRVL_SPI=m
CONFIG_NFC_ST21NFCA=m
CONFIG_NFC_ST21NFCA_I2C=m
CONFIG_NFC_ST_NCI=m
CONFIG_NFC_ST_NCI_I2C=m
CONFIG_NFC_ST_NCI_SPI=m
CONFIG_NFC_NXP_NCI=m
CONFIG_NFC_NXP_NCI_I2C=m
CONFIG_NFC_S3FWRN5=m
CONFIG_NFC_S3FWRN5_I2C=m
CONFIG_NFC_S3FWRN82_UART=m
CONFIG_NFC_ST95HF=m
# end of Near Field Communication (NFC) devices

CONFIG_PSAMPLE=m
CONFIG_NET_IFE=m
CONFIG_LWTUNNEL=y
CONFIG_LWTUNNEL_BPF=y
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
CONFIG_SOCK_VALIDATE_XMIT=y
CONFIG_NET_SELFTESTS=m
CONFIG_NET_SOCK_MSG=y
CONFIG_NET_DEVLINK=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_FAILOVER=m
CONFIG_ETHTOOL_NETLINK=y
CONFIG_NETDEV_ADDR_LIST_TEST=m

#
# Device Drivers
#
CONFIG_PCCARD=m
CONFIG_PCMCIA=m
CONFIG_PCMCIA_LOAD_CIS=y

#
# PC-card bridges
#

#
# Generic Driver Options
#
CONFIG_AUXILIARY_BUS=y
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DEVTMPFS_SAFE=y
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y

#
# Firmware loader
#
CONFIG_FW_LOADER=m
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
CONFIG_FW_LOADER_COMPRESS=y
CONFIG_FW_LOADER_COMPRESS_XZ=y
CONFIG_FW_LOADER_COMPRESS_ZSTD=y
CONFIG_FW_UPLOAD=y
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
CONFIG_DEBUG_DRIVER=y
CONFIG_DEBUG_DEVRES=y
CONFIG_DEBUG_TEST_DRIVER_REMOVE=y
CONFIG_TEST_ASYNC_DRIVER_PROBE=m
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_AC97=m
CONFIG_REGMAP_I2C=m
CONFIG_REGMAP_SLIMBUS=m
CONFIG_REGMAP_SPI=y
CONFIG_REGMAP_SPMI=m
CONFIG_REGMAP_W1=m
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SOUNDWIRE=m
CONFIG_REGMAP_SOUNDWIRE_MBQ=m
CONFIG_REGMAP_SCCB=m
CONFIG_REGMAP_I3C=m
CONFIG_REGMAP_SPI_AVMM=m
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_FENCE_TRACE=y
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_ARM_INTEGRATOR_LM=y
CONFIG_BT1_APB=y
CONFIG_BT1_AXI=y
CONFIG_MOXTET=m
CONFIG_HISILICON_LPC=y
CONFIG_INTEL_IXP4XX_EB=y
CONFIG_QCOM_EBI2=y
CONFIG_MHI_BUS=m
CONFIG_MHI_BUS_DEBUG=y
CONFIG_MHI_BUS_EP=m
# end of Bus devices

CONFIG_CONNECTOR=m

#
# Firmware Drivers
#

#
# ARM System Control and Management Interface Protocol
#
CONFIG_ARM_SCMI_PROTOCOL=m
CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
CONFIG_ARM_SCMI_HAVE_SHMEM=y
CONFIG_ARM_SCMI_HAVE_MSG=y
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y
CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE=y
CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE=y
CONFIG_ARM_SCMI_POWER_DOMAIN=m
CONFIG_ARM_SCMI_POWER_CONTROL=m
# end of ARM System Control and Management Interface Protocol

CONFIG_ARM_SCPI_PROTOCOL=m
CONFIG_ARM_SCPI_POWER_DOMAIN=m
CONFIG_FIRMWARE_MEMMAP=y
CONFIG_MTK_ADSP_IPC=m
CONFIG_QCOM_SCM=m
CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT=y
CONFIG_BCM47XX_NVRAM=y
CONFIG_BCM47XX_SPROM=y
CONFIG_TEE_BNXT_FW=m
CONFIG_CS_DSP=m
CONFIG_GOOGLE_FIRMWARE=y
CONFIG_GOOGLE_COREBOOT_TABLE=m
CONFIG_GOOGLE_MEMCONSOLE=m
CONFIG_GOOGLE_FRAMEBUFFER_COREBOOT=m
CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=m
CONFIG_GOOGLE_VPD=m
CONFIG_IMX_DSP=m
CONFIG_IMX_SCU=y
CONFIG_IMX_SCU_PD=y

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_GNSS=m
CONFIG_GNSS_SERIAL=m
CONFIG_GNSS_MTK_SERIAL=m
CONFIG_GNSS_SIRF_SERIAL=m
CONFIG_GNSS_UBX_SERIAL=m
CONFIG_GNSS_USB=m
CONFIG_MTD=m
CONFIG_MTD_TESTS=m

#
# Partition parsers
#
CONFIG_MTD_AR7_PARTS=m
CONFIG_MTD_BCM63XX_PARTS=y
CONFIG_MTD_BRCM_U_BOOT=m
CONFIG_MTD_CMDLINE_PARTS=m
CONFIG_MTD_OF_PARTS=m
CONFIG_MTD_OF_PARTS_BCM4908=y
CONFIG_MTD_OF_PARTS_LINKSYS_NS=y
CONFIG_MTD_PARSER_IMAGETAG=m
CONFIG_MTD_PARSER_TRX=m
CONFIG_MTD_SHARPSL_PARTS=m
CONFIG_MTD_REDBOOT_PARTS=m
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
CONFIG_MTD_REDBOOT_PARTS_READONLY=y
CONFIG_MTD_QCOMSMEM_PARTS=m
# end of Partition parsers

#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=m
CONFIG_MTD_BLOCK=m
CONFIG_MTD_BLOCK_RO=m

#
# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
#
CONFIG_FTL=m
CONFIG_NFTL=m
CONFIG_NFTL_RW=y
CONFIG_INFTL=m
CONFIG_RFD_FTL=m
CONFIG_SSFDC=m
CONFIG_SM_FTL=m
CONFIG_MTD_OOPS=m
CONFIG_MTD_PSTORE=m
CONFIG_MTD_PARTITIONED_MASTER=y

#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=m
CONFIG_MTD_JEDECPROBE=m
CONFIG_MTD_GEN_PROBE=m
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_NOSWAP=y
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_MAP_BANK_WIDTH_8=y
CONFIG_MTD_MAP_BANK_WIDTH_16=y
CONFIG_MTD_MAP_BANK_WIDTH_32=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
CONFIG_MTD_CFI_I4=y
CONFIG_MTD_CFI_I8=y
CONFIG_MTD_OTP=y
CONFIG_MTD_CFI_INTELEXT=m
CONFIG_MTD_CFI_AMDSTD=m
CONFIG_MTD_CFI_STAA=m
CONFIG_MTD_CFI_UTIL=m
CONFIG_MTD_RAM=m
CONFIG_MTD_ROM=m
CONFIG_MTD_ABSENT=m
# end of RAM/ROM/Flash chip drivers

#
# Mapping drivers for chip access
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=m
CONFIG_MTD_PHYSMAP_COMPAT=y
CONFIG_MTD_PHYSMAP_START=0x8000000
CONFIG_MTD_PHYSMAP_LEN=0
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_PHYSMAP_BT1_ROM=y
CONFIG_MTD_PHYSMAP_VERSATILE=y
CONFIG_MTD_PHYSMAP_GEMINI=y
CONFIG_MTD_PHYSMAP_GPIO_ADDR=y
CONFIG_MTD_SC520CDP=m
CONFIG_MTD_NETSC520=m
CONFIG_MTD_TS5500=m
CONFIG_MTD_SOLUTIONENGINE=m
CONFIG_MTD_PCMCIA=m
CONFIG_MTD_PCMCIA_ANONYMOUS=y
CONFIG_MTD_PLATRAM=m
# end of Mapping drivers for chip access

#
# Self-contained MTD device drivers
#
CONFIG_MTD_DATAFLASH=m
CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y
CONFIG_MTD_DATAFLASH_OTP=y
CONFIG_MTD_MCHP23K256=m
CONFIG_MTD_MCHP48L640=m
CONFIG_MTD_SPEAR_SMI=m
CONFIG_MTD_SST25L=m
CONFIG_MTD_SLRAM=m
CONFIG_MTD_PHRAM=m
CONFIG_MTD_MTDRAM=m
CONFIG_MTDRAM_TOTAL_SIZE=4096
CONFIG_MTDRAM_ERASE_SIZE=128
CONFIG_MTD_BLOCK2MTD=m

#
# Disk-On-Chip Device Drivers
#
CONFIG_MTD_DOCG3=m
CONFIG_BCH_CONST_M=14
CONFIG_BCH_CONST_T=4
# end of Self-contained MTD device drivers

#
# NAND
#
CONFIG_MTD_NAND_CORE=m
CONFIG_MTD_ONENAND=m
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
CONFIG_MTD_ONENAND_GENERIC=m
CONFIG_MTD_ONENAND_SAMSUNG=m
CONFIG_MTD_ONENAND_OTP=y
CONFIG_MTD_ONENAND_2X_PROGRAM=y
CONFIG_MTD_RAW_NAND=m

#
# Raw/parallel NAND flash controllers
#
CONFIG_MTD_NAND_AMS_DELTA=m
CONFIG_MTD_NAND_OMAP2=m
CONFIG_MTD_NAND_OMAP_BCH=y
CONFIG_MTD_NAND_OMAP_BCH_BUILD=m
CONFIG_MTD_NAND_SHARPSL=m
CONFIG_MTD_NAND_ATMEL=m
CONFIG_MTD_NAND_MARVELL=m
CONFIG_MTD_NAND_SLC_LPC32XX=m
CONFIG_MTD_NAND_MLC_LPC32XX=m
CONFIG_MTD_NAND_BRCMNAND=m
CONFIG_MTD_NAND_BRCMNAND_BCM63XX=m
CONFIG_MTD_NAND_BRCMNAND_BCMBCA=m
CONFIG_MTD_NAND_BRCMNAND_BRCMSTB=m
CONFIG_MTD_NAND_BRCMNAND_IPROC=m
CONFIG_MTD_NAND_OXNAS=m
CONFIG_MTD_NAND_FSL_IFC=m
CONFIG_MTD_NAND_VF610_NFC=m
CONFIG_MTD_NAND_MXC=m
CONFIG_MTD_NAND_SH_FLCTL=m
CONFIG_MTD_NAND_DAVINCI=m
CONFIG_MTD_NAND_TXX9NDFMC=m
CONFIG_MTD_NAND_JZ4780=m
CONFIG_MTD_NAND_INGENIC_ECC=y
CONFIG_MTD_NAND_JZ4740_ECC=m
CONFIG_MTD_NAND_JZ4725B_BCH=m
CONFIG_MTD_NAND_JZ4780_BCH=m
CONFIG_MTD_NAND_FSMC=m
CONFIG_MTD_NAND_SUNXI=m
CONFIG_MTD_NAND_HISI504=m
CONFIG_MTD_NAND_QCOM=m
CONFIG_MTD_NAND_MTK=m
CONFIG_MTD_NAND_MXIC=m
CONFIG_MTD_NAND_TEGRA=m
CONFIG_MTD_NAND_STM32_FMC2=m
CONFIG_MTD_NAND_GPIO=m
CONFIG_MTD_NAND_PLATFORM=m
CONFIG_MTD_NAND_CADENCE=m
CONFIG_MTD_NAND_INTEL_LGM=m
CONFIG_MTD_NAND_RENESAS=m

#
# Misc
#
CONFIG_MTD_NAND_NANDSIM=m
CONFIG_MTD_NAND_DISKONCHIP=m
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
CONFIG_MTD_SPI_NAND=m

#
# ECC engine support
#
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y
CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND_ECC_MXIC=y
CONFIG_MTD_NAND_ECC_MEDIATEK=m
# end of ECC engine support
# end of NAND

#
# LPDDR & LPDDR2 PCM memory drivers
#
CONFIG_MTD_LPDDR=m
CONFIG_MTD_QINFO_PROBE=m
# end of LPDDR & LPDDR2 PCM memory drivers

CONFIG_MTD_SPI_NOR=m
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
CONFIG_SPI_HISI_SFC=m
CONFIG_SPI_NXP_SPIFI=m
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_GLUEBI=m
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_HYPERBUS=m
CONFIG_HBMC_AM654=m
CONFIG_DTC=y
CONFIG_OF=y
CONFIG_OF_UNITTEST=y
CONFIG_OF_ALL_DTBS=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_PARPORT=m
CONFIG_PARPORT_PC=m
CONFIG_PARPORT_PC_FIFO=y
CONFIG_PARPORT_PC_SUPERIO=y
CONFIG_PARPORT_PC_PCMCIA=m
CONFIG_PARPORT_AX88796=m
CONFIG_PARPORT_1284=y
CONFIG_PARPORT_NOT_PC=y
CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_NULL_BLK=m
CONFIG_BLK_DEV_NULL_BLK_FAULT_INJECTION=y
CONFIG_CDROM=m
CONFIG_PARIDE=m

#
# Parallel IDE high-level drivers
#
CONFIG_PARIDE_PD=m
CONFIG_PARIDE_PCD=m
CONFIG_PARIDE_PF=m
CONFIG_PARIDE_PT=m
CONFIG_PARIDE_PG=m

#
# Parallel IDE protocol modules
#
CONFIG_PARIDE_ATEN=m
CONFIG_PARIDE_BPCK=m
CONFIG_PARIDE_BPCK6=m
CONFIG_PARIDE_COMM=m
CONFIG_PARIDE_DSTR=m
CONFIG_PARIDE_FIT2=m
CONFIG_PARIDE_FIT3=m
CONFIG_PARIDE_EPAT=m
CONFIG_PARIDE_EPATC8=y
CONFIG_PARIDE_EPIA=m
CONFIG_PARIDE_FRIQ=m
CONFIG_PARIDE_FRPW=m
CONFIG_PARIDE_KBIC=m
CONFIG_PARIDE_KTTI=m
CONFIG_PARIDE_ON20=m
CONFIG_PARIDE_ON26=m
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
CONFIG_BLK_DEV_DRBD=m
CONFIG_DRBD_FAULT_INJECTION=y
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=m
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_CDROM_PKTCDVD=m
CONFIG_CDROM_PKTCDVD_BUFFERS=8
CONFIG_CDROM_PKTCDVD_WCACHE=y
CONFIG_ATA_OVER_ETH=m
CONFIG_VIRTIO_BLK=m
CONFIG_BLK_DEV_RBD=m
CONFIG_BLK_DEV_UBLK=m

#
# NVME Support
#
CONFIG_NVME_COMMON=m
CONFIG_NVME_CORE=m
CONFIG_NVME_MULTIPATH=y
CONFIG_NVME_VERBOSE_ERRORS=y
CONFIG_NVME_HWMON=y
CONFIG_NVME_FABRICS=m
CONFIG_NVME_TCP=m
CONFIG_NVME_AUTH=y
CONFIG_NVME_APPLE=m
CONFIG_NVME_TARGET=m
CONFIG_NVME_TARGET_PASSTHRU=y
CONFIG_NVME_TARGET_LOOP=m
CONFIG_NVME_TARGET_TCP=m
CONFIG_NVME_TARGET_AUTH=y
# end of NVME Support

#
# Misc devices
#
CONFIG_SENSORS_LIS3LV02D=m
CONFIG_AD525X_DPOT=m
CONFIG_AD525X_DPOT_I2C=m
CONFIG_AD525X_DPOT_SPI=m
CONFIG_DUMMY_IRQ=m
CONFIG_ICS932S401=m
CONFIG_ATMEL_SSC=m
CONFIG_ENCLOSURE_SERVICES=m
CONFIG_GEHC_ACHC=m
CONFIG_HI6421V600_IRQ=m
CONFIG_QCOM_COINCELL=m
CONFIG_QCOM_FASTRPC=m
CONFIG_APDS9802ALS=m
CONFIG_ISL29003=m
CONFIG_ISL29020=m
CONFIG_SENSORS_TSL2550=m
CONFIG_SENSORS_BH1770=m
CONFIG_SENSORS_APDS990X=m
CONFIG_HMC6352=m
CONFIG_DS1682=m
CONFIG_LATTICE_ECP3_CONFIG=m
CONFIG_SRAM=y
CONFIG_XILINX_SDFEC=m
CONFIG_MISC_RTSX=m
CONFIG_HISI_HIKEY_USB=m
CONFIG_OPEN_DICE=m
CONFIG_VCPU_STALL_DETECTOR=m
CONFIG_C2PORT=m

#
# EEPROM support
#
CONFIG_EEPROM_AT24=m
CONFIG_EEPROM_AT25=m
CONFIG_EEPROM_LEGACY=m
CONFIG_EEPROM_MAX6875=m
CONFIG_EEPROM_93CX6=m
CONFIG_EEPROM_93XX46=m
CONFIG_EEPROM_IDT_89HPESX=m
CONFIG_EEPROM_EE1004=m
# end of EEPROM support

#
# Texas Instruments shared transport line discipline
#
CONFIG_TI_ST=m
# end of Texas Instruments shared transport line discipline

CONFIG_SENSORS_LIS3_SPI=m
CONFIG_SENSORS_LIS3_I2C=m

#
# Altera FPGA firmware download module (requires I2C)
#
CONFIG_ALTERA_STAPL=m
CONFIG_ECHO=m
CONFIG_MISC_RTSX_USB=m
CONFIG_UACCE=m
CONFIG_PVPANIC=y
CONFIG_PVPANIC_MMIO=m
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=m
CONFIG_RAID_ATTRS=m
CONFIG_SCSI_COMMON=m
CONFIG_SCSI=m
CONFIG_SCSI_NETLINK=y
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=m
CONFIG_CHR_DEV_ST=m
CONFIG_BLK_DEV_SR=m
CONFIG_CHR_DEV_SG=m
CONFIG_BLK_DEV_BSG=y
CONFIG_CHR_DEV_SCH=m
CONFIG_SCSI_ENCLOSURE=m
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SCAN_ASYNC=y

#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=m
CONFIG_SCSI_FC_ATTRS=m
CONFIG_SCSI_ISCSI_ATTRS=m
CONFIG_SCSI_SAS_ATTRS=m
CONFIG_SCSI_SAS_LIBSAS=m
CONFIG_SCSI_SAS_ATA=y
CONFIG_SCSI_SAS_HOST_SMP=y
CONFIG_SCSI_SRP_ATTRS=m
# end of SCSI Transports

CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
CONFIG_ISCSI_BOOT_SYSFS=m
CONFIG_SCSI_HISI_SAS=m
CONFIG_SCSI_HISI_SAS_DEBUGFS_DEFAULT_ENABLE=y
CONFIG_LIBFC=m
CONFIG_LIBFCOE=m
CONFIG_SCSI_FDOMAIN=m
CONFIG_SCSI_PPA=m
CONFIG_SCSI_IMM=m
CONFIG_SCSI_IZIP_EPP16=y
CONFIG_SCSI_IZIP_SLOW_CTR=y
CONFIG_SCSI_DEBUG=m
CONFIG_SCSI_VIRTIO=m
CONFIG_SCSI_LOWLEVEL_PCMCIA=y
CONFIG_PCMCIA_AHA152X=m
CONFIG_PCMCIA_FDOMAIN=m
CONFIG_PCMCIA_NINJA_SCSI=m
CONFIG_PCMCIA_QLOGIC=m
CONFIG_PCMCIA_SYM53C500=m
CONFIG_SCSI_DH=y
CONFIG_SCSI_DH_RDAC=m
CONFIG_SCSI_DH_HP_SW=m
CONFIG_SCSI_DH_EMC=m
CONFIG_SCSI_DH_ALUA=m
# end of SCSI device support

CONFIG_HAVE_PATA_PLATFORM=y
CONFIG_ATA=m
CONFIG_SATA_HOST=y
CONFIG_PATA_TIMINGS=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_FORCE=y
CONFIG_SATA_PMP=y
CONFIG_ATA_SFF=y

#
# SFF controllers with custom DMA interface
#

#
# PIO-only SFF controllers
#
CONFIG_PATA_IXP4XX_CF=m
CONFIG_PATA_PCMCIA=m
CONFIG_PATA_PLATFORM=m
CONFIG_PATA_OF_PLATFORM=m
CONFIG_PATA_SAMSUNG_CF=m

#
# Generic fallback / legacy drivers
#
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
CONFIG_MD_CLUSTER=m
CONFIG_BCACHE=m
CONFIG_BCACHE_DEBUG=y
CONFIG_BCACHE_CLOSURES_DEBUG=y
CONFIG_BCACHE_ASYNC_REGISTRATION=y
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=m
CONFIG_DM_DEBUG=y
CONFIG_DM_BUFIO=m
CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING=y
CONFIG_DM_DEBUG_BLOCK_STACK_TRACING=y
CONFIG_DM_BIO_PRISON=m
CONFIG_DM_PERSISTENT_DATA=m
CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
CONFIG_DM_CACHE=m
CONFIG_DM_CACHE_SMQ=m
CONFIG_DM_WRITECACHE=m
CONFIG_DM_EBS=m
CONFIG_DM_ERA=m
CONFIG_DM_CLONE=m
CONFIG_DM_MIRROR=m
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
CONFIG_DM_MULTIPATH_HST=m
CONFIG_DM_MULTIPATH_IOA=m
CONFIG_DM_DELAY=m
CONFIG_DM_DUST=m
CONFIG_DM_UEVENT=y
CONFIG_DM_FLAKEY=m
CONFIG_DM_VERITY=m
CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y
CONFIG_DM_VERITY_FEC=y
CONFIG_DM_SWITCH=m
CONFIG_DM_LOG_WRITES=m
CONFIG_DM_INTEGRITY=m
CONFIG_DM_ZONED=m
CONFIG_DM_AUDIT=y
CONFIG_TARGET_CORE=m
CONFIG_TCM_IBLOCK=m
CONFIG_TCM_FILEIO=m
CONFIG_TCM_PSCSI=m
CONFIG_LOOPBACK_TARGET=m
CONFIG_TCM_FC=m
CONFIG_ISCSI_TARGET=m
CONFIG_SBP_TARGET=m

#
# IEEE 1394 (FireWire) support
#
CONFIG_FIREWIRE=m
CONFIG_FIREWIRE_SBP2=m
CONFIG_FIREWIRE_NET=m
# end of IEEE 1394 (FireWire) support

CONFIG_NETDEVICES=y
CONFIG_MII=m
CONFIG_NET_CORE=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_WIREGUARD=m
CONFIG_WIREGUARD_DEBUG=y
CONFIG_EQUALIZER=m
CONFIG_IFB=m
CONFIG_NET_TEAM=m
CONFIG_NET_TEAM_MODE_BROADCAST=m
CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
CONFIG_NET_TEAM_MODE_RANDOM=m
CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
CONFIG_NET_TEAM_MODE_LOADBALANCE=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_IPVLAN_L3S=y
CONFIG_IPVLAN=m
CONFIG_IPVTAP=m
CONFIG_VXLAN=m
CONFIG_GENEVE=m
CONFIG_BAREUDP=m
CONFIG_GTP=m
CONFIG_AMT=m
CONFIG_MACSEC=m
CONFIG_NETCONSOLE=m
CONFIG_NETCONSOLE_DYNAMIC=y
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=m
CONFIG_TAP=m
CONFIG_TUN_VNET_CROSS_LE=y
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_NLMON=m
CONFIG_NET_VRF=m
CONFIG_VSOCKMON=m
CONFIG_MHI_NET=m
CONFIG_ARCNET=m
CONFIG_ARCNET_1201=m
CONFIG_ARCNET_1051=m
CONFIG_ARCNET_RAW=m
CONFIG_ARCNET_CAP=m
CONFIG_ARCNET_COM90xx=m
CONFIG_ARCNET_COM90xxIO=m
CONFIG_ARCNET_RIM_I=m
CONFIG_ARCNET_COM20020=m
CONFIG_ARCNET_COM20020_CS=m
CONFIG_ATM_DRIVERS=y
CONFIG_ATM_DUMMY=m
CONFIG_ATM_TCP=m
CONFIG_CAIF_DRIVERS=y
CONFIG_CAIF_TTY=m

#
# Distributed Switch Architecture drivers
#
CONFIG_B53=m
CONFIG_B53_SPI_DRIVER=m
CONFIG_B53_MDIO_DRIVER=m
CONFIG_B53_MMAP_DRIVER=m
CONFIG_B53_SRAB_DRIVER=m
CONFIG_B53_SERDES=m
CONFIG_NET_DSA_BCM_SF2=m
CONFIG_NET_DSA_LOOP=m
CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
CONFIG_NET_DSA_LANTIQ_GSWIP=m
CONFIG_NET_DSA_MT7530=m
CONFIG_NET_DSA_MV88E6060=m
CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
CONFIG_NET_DSA_MV88E6XXX=m
CONFIG_NET_DSA_MV88E6XXX_PTP=y
CONFIG_NET_DSA_MSCC_SEVILLE=m
CONFIG_NET_DSA_AR9331=m
CONFIG_NET_DSA_QCA8K=m
CONFIG_NET_DSA_SJA1105=m
CONFIG_NET_DSA_SJA1105_PTP=y
CONFIG_NET_DSA_SJA1105_TAS=y
CONFIG_NET_DSA_SJA1105_VL=y
CONFIG_NET_DSA_XRS700X=m
CONFIG_NET_DSA_XRS700X_I2C=m
CONFIG_NET_DSA_XRS700X_MDIO=m
CONFIG_NET_DSA_REALTEK=m
CONFIG_NET_DSA_REALTEK_MDIO=m
CONFIG_NET_DSA_REALTEK_SMI=m
CONFIG_NET_DSA_REALTEK_RTL8365MB=m
CONFIG_NET_DSA_REALTEK_RTL8366RB=m
CONFIG_NET_DSA_SMSC_LAN9303=m
CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
CONFIG_NET_DSA_VITESSE_VSC73XX=m
CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
# end of Distributed Switch Architecture drivers

CONFIG_ETHERNET=y
CONFIG_MDIO=m
CONFIG_NET_VENDOR_3COM=y
CONFIG_PCMCIA_3C574=m
CONFIG_PCMCIA_3C589=m
CONFIG_NET_VENDOR_ACTIONS=y
CONFIG_OWL_EMAC=m
CONFIG_NET_VENDOR_ALACRITECH=y
CONFIG_NET_VENDOR_AMAZON=y
CONFIG_NET_VENDOR_AMD=y
CONFIG_PCMCIA_NMCLAN=m
CONFIG_AMD_XGBE=m
CONFIG_AMD_XGBE_DCB=y
CONFIG_NET_XGENE=m
CONFIG_NET_XGENE_V2=m
CONFIG_NET_VENDOR_AQUANTIA=y
CONFIG_NET_VENDOR_ARC=y
CONFIG_ARC_EMAC_CORE=m
CONFIG_ARC_EMAC=m
CONFIG_EMAC_ROCKCHIP=m
CONFIG_NET_VENDOR_ASIX=y
CONFIG_SPI_AX88796C=m
CONFIG_SPI_AX88796C_COMPRESSION=y
CONFIG_NET_VENDOR_CADENCE=y
CONFIG_NET_CALXEDA_XGMAC=m
CONFIG_NET_VENDOR_CAVIUM=y
CONFIG_NET_VENDOR_CIRRUS=y
CONFIG_CS89x0=m
CONFIG_CS89x0_PLATFORM=m
CONFIG_EP93XX_ETH=m
CONFIG_NET_VENDOR_CORTINA=y
CONFIG_GEMINI_ETHERNET=m
CONFIG_NET_VENDOR_DAVICOM=y
CONFIG_DM9000=m
CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y
CONFIG_DM9051=m
CONFIG_DNET=m
CONFIG_NET_VENDOR_ENGLEDER=y
CONFIG_NET_VENDOR_EZCHIP=y
CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=m
CONFIG_NET_VENDOR_FARADAY=y
CONFIG_FTMAC100=m
CONFIG_FTGMAC100=m
CONFIG_NET_VENDOR_FREESCALE=y
CONFIG_FEC=m
CONFIG_FSL_FMAN=m
CONFIG_FSL_PQ_MDIO=m
CONFIG_FSL_XGMAC_MDIO=m
CONFIG_FSL_DPAA2_SWITCH=m
CONFIG_FSL_ENETC_IERB=m
CONFIG_NET_VENDOR_FUJITSU=y
CONFIG_PCMCIA_FMVJ18X=m
CONFIG_NET_VENDOR_FUNGIBLE=y
CONFIG_NET_VENDOR_GOOGLE=y
CONFIG_NET_VENDOR_HISILICON=y
CONFIG_HIX5HD2_GMAC=m
CONFIG_HISI_FEMAC=m
CONFIG_HIP04_ETH=m
CONFIG_HI13X1_GMAC=y
CONFIG_HNS_MDIO=m
CONFIG_HNS=m
CONFIG_HNS_DSAF=m
CONFIG_HNS_ENET=m
CONFIG_NET_VENDOR_HUAWEI=y
CONFIG_NET_VENDOR_I825XX=y
CONFIG_NET_VENDOR_INTEL=y
CONFIG_NET_VENDOR_WANGXUN=y
CONFIG_KORINA=m
CONFIG_NET_VENDOR_ADI=y
CONFIG_ADIN1110=m
CONFIG_NET_VENDOR_LITEX=y
CONFIG_LITEX_LITEETH=m
CONFIG_NET_VENDOR_MARVELL=y
CONFIG_MV643XX_ETH=m
CONFIG_MVMDIO=m
CONFIG_MVNETA_BM_ENABLE=m
CONFIG_MVNETA=m
CONFIG_MVNETA_BM=m
CONFIG_MVPP2=m
CONFIG_MVPP2_PTP=y
CONFIG_PXA168_ETH=m
CONFIG_PRESTERA=m
CONFIG_NET_VENDOR_MEDIATEK=y
CONFIG_NET_MEDIATEK_SOC_WED=y
CONFIG_NET_MEDIATEK_SOC=m
CONFIG_NET_MEDIATEK_STAR_EMAC=m
CONFIG_NET_VENDOR_MELLANOX=y
CONFIG_MLXSW_CORE=m
CONFIG_MLXSW_CORE_HWMON=y
CONFIG_MLXSW_CORE_THERMAL=y
CONFIG_MLXSW_I2C=m
CONFIG_MLXSW_MINIMAL=m
CONFIG_MLXFW=m
CONFIG_MLXBF_GIGE=m
CONFIG_NET_VENDOR_MICREL=y
CONFIG_KS8851=m
CONFIG_KS8851_MLL=m
CONFIG_NET_VENDOR_MICROCHIP=y
CONFIG_ENC28J60=m
CONFIG_ENC28J60_WRITEVERIFY=y
CONFIG_ENCX24J600=m
CONFIG_LAN966X_SWITCH=m
CONFIG_SPARX5_SWITCH=m
CONFIG_NET_VENDOR_MICROSEMI=y
CONFIG_MSCC_OCELOT_SWITCH_LIB=m
CONFIG_MSCC_OCELOT_SWITCH=m
CONFIG_NET_VENDOR_MICROSOFT=y
CONFIG_NET_VENDOR_NI=y
CONFIG_NET_VENDOR_NATSEMI=y
CONFIG_NET_VENDOR_NETRONOME=y
CONFIG_NET_VENDOR_8390=y
CONFIG_PCMCIA_AXNET=m
CONFIG_AX88796=m
CONFIG_AX88796_93CX6=y
CONFIG_PCMCIA_PCNET=m
CONFIG_STNIC=m
CONFIG_LPC_ENET=m
CONFIG_NET_VENDOR_PENSANDO=y
CONFIG_NET_VENDOR_QUALCOMM=y
CONFIG_QCA7000=m
CONFIG_QCA7000_SPI=m
CONFIG_QCA7000_UART=m
CONFIG_RMNET=m
CONFIG_NET_VENDOR_RENESAS=y
CONFIG_SH_ETH=m
CONFIG_RAVB=m
CONFIG_NET_VENDOR_ROCKER=y
CONFIG_NET_VENDOR_SAMSUNG=y
CONFIG_NET_VENDOR_SEEQ=y
CONFIG_NET_VENDOR_SOLARFLARE=y
CONFIG_NET_VENDOR_SMSC=y
CONFIG_SMC91X=m
CONFIG_PCMCIA_SMC91C92=m
CONFIG_SMC911X=m
CONFIG_SMSC911X=m
CONFIG_NET_VENDOR_SOCIONEXT=y
CONFIG_SNI_AVE=m
CONFIG_SNI_NETSEC=m
CONFIG_NET_VENDOR_STMICRO=y
CONFIG_NET_VENDOR_SUNPLUS=y
CONFIG_SP7021_EMAC=m
CONFIG_NET_VENDOR_SYNOPSYS=y
CONFIG_NET_VENDOR_VERTEXCOM=y
CONFIG_MSE102X=m
CONFIG_NET_VENDOR_VIA=y
CONFIG_NET_VENDOR_WIZNET=y
CONFIG_WIZNET_W5100=m
CONFIG_WIZNET_W5300=m
# CONFIG_WIZNET_BUS_DIRECT is not set
# CONFIG_WIZNET_BUS_INDIRECT is not set
CONFIG_WIZNET_BUS_ANY=y
CONFIG_WIZNET_W5100_SPI=m
CONFIG_NET_VENDOR_XILINX=y
CONFIG_XILINX_EMACLITE=m
CONFIG_XILINX_AXI_EMAC=m
CONFIG_XILINX_LL_TEMAC=m
CONFIG_NET_VENDOR_XIRCOM=y
CONFIG_PCMCIA_XIRC2PS=m
CONFIG_QCOM_IPA=m
CONFIG_PHYLINK=m
CONFIG_PHYLIB=m
CONFIG_SWPHY=y
CONFIG_LED_TRIGGER_PHY=y
CONFIG_FIXED_PHY=m
CONFIG_SFP=m

#
# MII PHY device drivers
#
CONFIG_AMD_PHY=m
CONFIG_MESON_GXL_PHY=m
CONFIG_ADIN_PHY=m
CONFIG_ADIN1100_PHY=m
CONFIG_AQUANTIA_PHY=m
CONFIG_AX88796B_PHY=m
CONFIG_BROADCOM_PHY=m
CONFIG_BCM54140_PHY=m
CONFIG_BCM63XX_PHY=m
CONFIG_BCM7XXX_PHY=m
CONFIG_BCM84881_PHY=m
CONFIG_BCM87XX_PHY=m
CONFIG_BCM_CYGNUS_PHY=m
CONFIG_BCM_NET_PHYLIB=m
CONFIG_BCM_NET_PHYPTP=m
CONFIG_CICADA_PHY=m
CONFIG_CORTINA_PHY=m
CONFIG_DAVICOM_PHY=m
CONFIG_ICPLUS_PHY=m
CONFIG_LXT_PHY=m
CONFIG_INTEL_XWAY_PHY=m
CONFIG_LSI_ET1011C_PHY=m
CONFIG_MARVELL_PHY=m
CONFIG_MARVELL_10G_PHY=m
CONFIG_MARVELL_88X2222_PHY=m
CONFIG_MAXLINEAR_GPHY=m
CONFIG_MEDIATEK_GE_PHY=m
CONFIG_MICREL_PHY=m
CONFIG_MICROCHIP_PHY=m
CONFIG_MICROCHIP_T1_PHY=m
CONFIG_MICROSEMI_PHY=m
CONFIG_MOTORCOMM_PHY=m
CONFIG_NATIONAL_PHY=m
CONFIG_NXP_C45_TJA11XX_PHY=m
CONFIG_NXP_TJA11XX_PHY=m
CONFIG_AT803X_PHY=m
CONFIG_QSEMI_PHY=m
CONFIG_REALTEK_PHY=m
CONFIG_RENESAS_PHY=m
CONFIG_ROCKCHIP_PHY=m
CONFIG_SMSC_PHY=m
CONFIG_STE10XP=m
CONFIG_TERANETICS_PHY=m
CONFIG_DP83822_PHY=m
CONFIG_DP83TC811_PHY=m
CONFIG_DP83848_PHY=m
CONFIG_DP83867_PHY=m
CONFIG_DP83869_PHY=m
CONFIG_DP83TD510_PHY=m
CONFIG_VITESSE_PHY=m
CONFIG_XILINX_GMII2RGMII=m
CONFIG_MICREL_KS8995MA=m
CONFIG_PSE_CONTROLLER=y
CONFIG_PSE_REGULATOR=m
CONFIG_CAN_DEV=m
CONFIG_CAN_VCAN=m
CONFIG_CAN_VXCAN=m
CONFIG_CAN_NETLINK=y
CONFIG_CAN_CALC_BITTIMING=y
CONFIG_CAN_RX_OFFLOAD=y
CONFIG_CAN_AT91=m
CONFIG_CAN_CAN327=m
CONFIG_CAN_FLEXCAN=m
CONFIG_CAN_SLCAN=m
CONFIG_CAN_SUN4I=m
CONFIG_CAN_C_CAN=m
CONFIG_CAN_C_CAN_PLATFORM=m
CONFIG_CAN_CC770=m
CONFIG_CAN_CC770_ISA=m
CONFIG_CAN_CC770_PLATFORM=m
CONFIG_CAN_CTUCANFD=m
CONFIG_CAN_CTUCANFD_PLATFORM=m
CONFIG_CAN_IFI_CANFD=m
CONFIG_CAN_M_CAN=m
CONFIG_CAN_M_CAN_PLATFORM=m
CONFIG_CAN_M_CAN_TCAN4X5X=m
CONFIG_CAN_RCAR=m
CONFIG_CAN_RCAR_CANFD=m
CONFIG_CAN_SJA1000=m
CONFIG_CAN_EMS_PCMCIA=m
CONFIG_CAN_SJA1000_ISA=m
CONFIG_CAN_SJA1000_PLATFORM=m
CONFIG_CAN_SOFTING=m
CONFIG_CAN_SOFTING_CS=m

#
# CAN SPI interfaces
#
CONFIG_CAN_HI311X=m
CONFIG_CAN_MCP251X=m
CONFIG_CAN_MCP251XFD=m
CONFIG_CAN_MCP251XFD_SANITY=y
# end of CAN SPI interfaces

#
# CAN USB interfaces
#
CONFIG_CAN_8DEV_USB=m
CONFIG_CAN_EMS_USB=m
CONFIG_CAN_ESD_USB=m
CONFIG_CAN_ETAS_ES58X=m
CONFIG_CAN_GS_USB=m
CONFIG_CAN_KVASER_USB=m
CONFIG_CAN_MCBA_USB=m
CONFIG_CAN_PEAK_USB=m
CONFIG_CAN_UCAN=m
# end of CAN USB interfaces

CONFIG_CAN_DEBUG_DEVICES=y

#
# MCTP Device Drivers
#
CONFIG_MCTP_SERIAL=m
CONFIG_MCTP_TRANSPORT_I2C=m
# end of MCTP Device Drivers

CONFIG_MDIO_DEVICE=m
CONFIG_MDIO_BUS=m
CONFIG_FWNODE_MDIO=m
CONFIG_OF_MDIO=m
CONFIG_MDIO_DEVRES=m
CONFIG_MDIO_SUN4I=m
CONFIG_MDIO_XGENE=m
CONFIG_MDIO_ASPEED=m
CONFIG_MDIO_BITBANG=m
CONFIG_MDIO_BCM_IPROC=m
CONFIG_MDIO_BCM_UNIMAC=m
CONFIG_MDIO_CAVIUM=m
CONFIG_MDIO_GPIO=m
CONFIG_MDIO_HISI_FEMAC=m
CONFIG_MDIO_I2C=m
CONFIG_MDIO_MVUSB=m
CONFIG_MDIO_MSCC_MIIM=m
CONFIG_MDIO_MOXART=m
CONFIG_MDIO_OCTEON=m
CONFIG_MDIO_IPQ8064=m

#
# MDIO Multiplexers
#
CONFIG_MDIO_BUS_MUX=m
CONFIG_MDIO_BUS_MUX_BCM6368=m
CONFIG_MDIO_BUS_MUX_BCM_IPROC=m
CONFIG_MDIO_BUS_MUX_GPIO=m
CONFIG_MDIO_BUS_MUX_MULTIPLEXER=m
CONFIG_MDIO_BUS_MUX_MMIOREG=m

#
# PCS device drivers
#
CONFIG_PCS_XPCS=m
CONFIG_PCS_LYNX=m
CONFIG_PCS_RZN1_MIIC=m
# end of PCS device drivers

CONFIG_PLIP=m
CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOATM=m
CONFIG_PPPOE=m
CONFIG_PPTP=m
CONFIG_PPPOL2TP=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_SLIP=m
CONFIG_SLHC=m
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_SMART=y
CONFIG_SLIP_MODE_SLIP6=y

#
# Host-side USB support is needed for USB Network Adapter support
#
CONFIG_USB_NET_DRIVERS=m
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
CONFIG_USB_LAN78XX=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_AX8817X=m
CONFIG_USB_NET_AX88179_178A=m
CONFIG_USB_NET_CDCETHER=m
CONFIG_USB_NET_CDC_EEM=m
CONFIG_USB_NET_CDC_NCM=m
CONFIG_USB_NET_HUAWEI_CDC_NCM=m
CONFIG_USB_NET_CDC_MBIM=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_SR9700=m
CONFIG_USB_NET_SR9800=m
CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_NET1080=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
CONFIG_USB_NET_CDC_SUBSET=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_BELKIN=y
CONFIG_USB_ARMLINUX=y
CONFIG_USB_EPSON2888=y
CONFIG_USB_KC2190=y
CONFIG_USB_NET_ZAURUS=m
CONFIG_USB_NET_CX82310_ETH=m
CONFIG_USB_NET_KALMIA=m
CONFIG_USB_NET_QMI_WWAN=m
CONFIG_USB_HSO=m
CONFIG_USB_NET_INT51X1=m
CONFIG_USB_CDC_PHONET=m
CONFIG_USB_IPHETH=m
CONFIG_USB_SIERRA_NET=m
CONFIG_USB_VL600=m
CONFIG_USB_NET_CH9200=m
CONFIG_USB_NET_AQC111=m
CONFIG_USB_RTL8153_ECM=m
CONFIG_WLAN=y
CONFIG_WLAN_VENDOR_ADMTEK=y
CONFIG_ATH_COMMON=m
CONFIG_WLAN_VENDOR_ATH=y
CONFIG_ATH_DEBUG=y
CONFIG_ATH_TRACEPOINTS=y
CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS=y
CONFIG_ATH_REG_DYNAMIC_USER_CERT_TESTING=y
CONFIG_ATH9K_HW=m
CONFIG_ATH9K_COMMON=m
CONFIG_ATH9K_COMMON_DEBUG=y
CONFIG_ATH9K_BTCOEX_SUPPORT=y
CONFIG_ATH9K_HTC=m
CONFIG_ATH9K_HTC_DEBUGFS=y
CONFIG_ATH9K_COMMON_SPECTRAL=y
CONFIG_CARL9170=m
CONFIG_CARL9170_LEDS=y
CONFIG_CARL9170_DEBUGFS=y
CONFIG_CARL9170_WPC=y
CONFIG_CARL9170_HWRNG=y
CONFIG_ATH6KL=m
CONFIG_ATH6KL_SDIO=m
CONFIG_ATH6KL_USB=m
CONFIG_ATH6KL_DEBUG=y
CONFIG_ATH6KL_TRACING=y
CONFIG_ATH6KL_REGDOMAIN=y
CONFIG_AR5523=m
CONFIG_WLAN_VENDOR_ATMEL=y
CONFIG_ATMEL=m
CONFIG_PCMCIA_ATMEL=m
CONFIG_AT76C50X_USB=m
CONFIG_WLAN_VENDOR_BROADCOM=y
CONFIG_BRCMUTIL=m
CONFIG_BRCMFMAC=m
CONFIG_BRCMFMAC_PROTO_BCDC=y
CONFIG_BRCMFMAC_SDIO=y
CONFIG_BRCMFMAC_USB=y
CONFIG_BRCM_TRACING=y
CONFIG_BRCMDBG=y
CONFIG_WLAN_VENDOR_CISCO=y
CONFIG_AIRO_CS=m
CONFIG_WLAN_VENDOR_INTEL=y
CONFIG_WLAN_VENDOR_INTERSIL=y
CONFIG_HOSTAP=m
CONFIG_HOSTAP_FIRMWARE=y
CONFIG_HOSTAP_FIRMWARE_NVRAM=y
CONFIG_HOSTAP_CS=m
CONFIG_HERMES=m
CONFIG_HERMES_PRISM=y
CONFIG_HERMES_CACHE_FW_ON_INIT=y
CONFIG_ORINOCO_USB=m
CONFIG_P54_COMMON=m
CONFIG_P54_USB=m
CONFIG_P54_SPI=m
CONFIG_P54_SPI_DEFAULT_EEPROM=y
CONFIG_P54_LEDS=y
CONFIG_WLAN_VENDOR_MARVELL=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_USB=m
CONFIG_LIBERTAS_SDIO=m
CONFIG_LIBERTAS_SPI=m
CONFIG_LIBERTAS_DEBUG=y
CONFIG_LIBERTAS_MESH=y
CONFIG_LIBERTAS_THINFIRM=m
CONFIG_LIBERTAS_THINFIRM_DEBUG=y
CONFIG_LIBERTAS_THINFIRM_USB=m
CONFIG_MWIFIEX=m
CONFIG_MWIFIEX_SDIO=m
CONFIG_MWIFIEX_USB=m
CONFIG_WLAN_VENDOR_MEDIATEK=y
CONFIG_MT7601U=m
CONFIG_MT76_CORE=m
CONFIG_MT76_LEDS=y
CONFIG_MT76_USB=m
CONFIG_MT76_SDIO=m
CONFIG_MT76x02_LIB=m
CONFIG_MT76x02_USB=m
CONFIG_MT76_CONNAC_LIB=m
CONFIG_MT76x0_COMMON=m
CONFIG_MT76x0U=m
CONFIG_MT76x2_COMMON=m
CONFIG_MT76x2U=m
CONFIG_MT7615_COMMON=m
CONFIG_MT7663_USB_SDIO_COMMON=m
CONFIG_MT7663U=m
CONFIG_MT7663S=m
CONFIG_MT7921_COMMON=m
CONFIG_MT7921S=m
CONFIG_MT7921U=m
CONFIG_WLAN_VENDOR_MICROCHIP=y
CONFIG_WILC1000=m
CONFIG_WILC1000_SDIO=m
CONFIG_WILC1000_SPI=m
CONFIG_WILC1000_HW_OOB_INTR=y
CONFIG_WLAN_VENDOR_PURELIFI=y
CONFIG_PLFXLC=m
CONFIG_WLAN_VENDOR_RALINK=y
CONFIG_WLAN_VENDOR_REALTEK=y
CONFIG_RTL8187=m
CONFIG_RTL8187_LEDS=y
CONFIG_RTL_CARDS=m
CONFIG_RTL8192CU=m
CONFIG_RTLWIFI=m
CONFIG_RTLWIFI_USB=m
CONFIG_RTLWIFI_DEBUG=y
CONFIG_RTL8192C_COMMON=m
CONFIG_RTL8XXXU=m
CONFIG_RTL8XXXU_UNTESTED=y
CONFIG_RTW88=m
CONFIG_RTW89=m
CONFIG_WLAN_VENDOR_RSI=y
CONFIG_RSI_91X=m
CONFIG_RSI_DEBUGFS=y
CONFIG_RSI_SDIO=m
CONFIG_RSI_USB=m
CONFIG_RSI_COEX=y
CONFIG_WLAN_VENDOR_SILABS=y
CONFIG_WFX=m
CONFIG_WLAN_VENDOR_ST=y
CONFIG_CW1200=m
CONFIG_CW1200_WLAN_SDIO=m
CONFIG_CW1200_WLAN_SPI=m
CONFIG_WLAN_VENDOR_TI=y
CONFIG_WL1251=m
CONFIG_WL1251_SPI=m
CONFIG_WL1251_SDIO=m
CONFIG_WL12XX=m
CONFIG_WL18XX=m
CONFIG_WLCORE=m
CONFIG_WLCORE_SPI=m
CONFIG_WLCORE_SDIO=m
CONFIG_WILINK_PLATFORM_DATA=y
CONFIG_WLAN_VENDOR_ZYDAS=y
CONFIG_USB_ZD1201=m
CONFIG_ZD1211RW=m
CONFIG_ZD1211RW_DEBUG=y
CONFIG_WLAN_VENDOR_QUANTENNA=y
CONFIG_PCMCIA_RAYCS=m
CONFIG_PCMCIA_WL3501=m
CONFIG_MAC80211_HWSIM=m
CONFIG_USB_NET_RNDIS_WLAN=m
CONFIG_VIRT_WIFI=m
CONFIG_WAN=y
CONFIG_HDLC=m
CONFIG_HDLC_RAW=m
CONFIG_HDLC_RAW_ETH=m
CONFIG_HDLC_CISCO=m
CONFIG_HDLC_FR=m
CONFIG_HDLC_PPP=m
CONFIG_HDLC_X25=m
CONFIG_FSL_UCC_HDLC=m
CONFIG_SLIC_DS26522=m
CONFIG_LAPBETHER=m
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
CONFIG_IEEE802154_AT86RF230=m
CONFIG_IEEE802154_MRF24J40=m
CONFIG_IEEE802154_CC2520=m
CONFIG_IEEE802154_ATUSB=m
CONFIG_IEEE802154_ADF7242=m
CONFIG_IEEE802154_MCR20A=m
CONFIG_IEEE802154_HWSIM=m

#
# Wireless WAN
#
CONFIG_WWAN=m
CONFIG_WWAN_DEBUGFS=y
CONFIG_WWAN_HWSIM=m
CONFIG_MHI_WWAN_CTRL=m
CONFIG_MHI_WWAN_MBIM=m
CONFIG_QCOM_BAM_DMUX=m
CONFIG_RPMSG_WWAN_CTRL=m
# end of Wireless WAN

CONFIG_NETDEVSIM=m
CONFIG_NET_FAILOVER=m
CONFIG_ISDN=y
CONFIG_ISDN_CAPI=y
CONFIG_CAPI_TRACE=y
CONFIG_ISDN_CAPI_MIDDLEWARE=y
CONFIG_MISDN=m
CONFIG_MISDN_DSP=m
CONFIG_MISDN_L1OIP=m

#
# mISDN hardware drivers
#
CONFIG_MISDN_HFCUSB=m

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=m
CONFIG_INPUT_FF_MEMLESS=m
CONFIG_INPUT_SPARSEKMAP=m
CONFIG_INPUT_MATRIXKMAP=m
CONFIG_INPUT_VIVALDIFMAP=m

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=m
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=m
CONFIG_INPUT_EVDEV=m
CONFIG_INPUT_EVBUG=m

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ADC=m
CONFIG_KEYBOARD_ADP5588=m
CONFIG_KEYBOARD_ADP5589=m
CONFIG_KEYBOARD_ATKBD=m
CONFIG_KEYBOARD_QT1050=m
CONFIG_KEYBOARD_QT1070=m
CONFIG_KEYBOARD_QT2160=m
CONFIG_KEYBOARD_CLPS711X=m
CONFIG_KEYBOARD_DLINK_DIR685=m
CONFIG_KEYBOARD_LKKBD=m
CONFIG_KEYBOARD_EP93XX=m
CONFIG_KEYBOARD_GPIO=m
CONFIG_KEYBOARD_GPIO_POLLED=m
CONFIG_KEYBOARD_TCA6416=m
CONFIG_KEYBOARD_TCA8418=m
CONFIG_KEYBOARD_MATRIX=m
CONFIG_KEYBOARD_LM8323=m
CONFIG_KEYBOARD_LM8333=m
CONFIG_KEYBOARD_MAX7359=m
CONFIG_KEYBOARD_MCS=m
CONFIG_KEYBOARD_MPR121=m
CONFIG_KEYBOARD_SNVS_PWRKEY=m
CONFIG_KEYBOARD_IMX=m
CONFIG_KEYBOARD_IMX_SC_KEY=m
CONFIG_KEYBOARD_NEWTON=m
CONFIG_KEYBOARD_OPENCORES=m
CONFIG_KEYBOARD_PINEPHONE=m
CONFIG_KEYBOARD_PMIC8XXX=m
CONFIG_KEYBOARD_SAMSUNG=m
CONFIG_KEYBOARD_GOLDFISH_EVENTS=m
CONFIG_KEYBOARD_STOWAWAY=m
CONFIG_KEYBOARD_ST_KEYSCAN=m
CONFIG_KEYBOARD_SUNKBD=m
CONFIG_KEYBOARD_SH_KEYSC=m
CONFIG_KEYBOARD_STMPE=m
CONFIG_KEYBOARD_IQS62X=m
CONFIG_KEYBOARD_OMAP4=m
CONFIG_KEYBOARD_TM2_TOUCHKEY=m
CONFIG_KEYBOARD_XTKBD=m
CONFIG_KEYBOARD_CROS_EC=m
CONFIG_KEYBOARD_CAP11XX=m
CONFIG_KEYBOARD_BCM=m
CONFIG_KEYBOARD_MT6779=m
CONFIG_KEYBOARD_MTK_PMIC=m
CONFIG_KEYBOARD_CYPRESS_SF=m
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=m
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
CONFIG_MOUSE_PS2_SENTELIC=y
CONFIG_MOUSE_PS2_TOUCHKIT=y
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_PS2_SMBUS=y
CONFIG_MOUSE_SERIAL=m
CONFIG_MOUSE_APPLETOUCH=m
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_CYAPA=m
CONFIG_MOUSE_ELAN_I2C=m
CONFIG_MOUSE_ELAN_I2C_I2C=y
CONFIG_MOUSE_ELAN_I2C_SMBUS=y
CONFIG_MOUSE_VSXXXAA=m
CONFIG_MOUSE_GPIO=m
CONFIG_MOUSE_SYNAPTICS_I2C=m
CONFIG_MOUSE_SYNAPTICS_USB=m
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_ANALOG=m
CONFIG_JOYSTICK_A3D=m
CONFIG_JOYSTICK_ADC=m
CONFIG_JOYSTICK_ADI=m
CONFIG_JOYSTICK_COBRA=m
CONFIG_JOYSTICK_GF2K=m
CONFIG_JOYSTICK_GRIP=m
CONFIG_JOYSTICK_GRIP_MP=m
CONFIG_JOYSTICK_GUILLEMOT=m
CONFIG_JOYSTICK_INTERACT=m
CONFIG_JOYSTICK_SIDEWINDER=m
CONFIG_JOYSTICK_TMDC=m
CONFIG_JOYSTICK_IFORCE=m
CONFIG_JOYSTICK_IFORCE_USB=m
CONFIG_JOYSTICK_IFORCE_232=m
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
CONFIG_JOYSTICK_SPACEORB=m
CONFIG_JOYSTICK_SPACEBALL=m
CONFIG_JOYSTICK_STINGER=m
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
CONFIG_JOYSTICK_DB9=m
CONFIG_JOYSTICK_GAMECON=m
CONFIG_JOYSTICK_TURBOGRAFX=m
CONFIG_JOYSTICK_AS5011=m
CONFIG_JOYSTICK_JOYDUMP=m
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
CONFIG_JOYSTICK_WALKERA0701=m
CONFIG_JOYSTICK_PSXPAD_SPI=m
CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
CONFIG_JOYSTICK_PXRC=m
CONFIG_JOYSTICK_QWIIC=m
CONFIG_JOYSTICK_FSIA6B=m
CONFIG_JOYSTICK_SENSEHAT=m
CONFIG_INPUT_TABLET=y
CONFIG_TABLET_USB_ACECAD=m
CONFIG_TABLET_USB_AIPTEK=m
CONFIG_TABLET_USB_HANWANG=m
CONFIG_TABLET_USB_KBTAB=m
CONFIG_TABLET_USB_PEGASUS=m
CONFIG_TABLET_SERIAL_WACOM4=m
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=m
CONFIG_TOUCHSCREEN_AD7877=m
CONFIG_TOUCHSCREEN_AD7879=m
CONFIG_TOUCHSCREEN_AD7879_I2C=m
CONFIG_TOUCHSCREEN_AD7879_SPI=m
CONFIG_TOUCHSCREEN_ADC=m
CONFIG_TOUCHSCREEN_AR1021_I2C=m
CONFIG_TOUCHSCREEN_ATMEL_MXT=m
CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y
CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
CONFIG_TOUCHSCREEN_BU21013=m
CONFIG_TOUCHSCREEN_BU21029=m
CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m
CONFIG_TOUCHSCREEN_CY8CTMA140=m
CONFIG_TOUCHSCREEN_CY8CTMG110=m
CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
CONFIG_TOUCHSCREEN_DA9052=m
CONFIG_TOUCHSCREEN_DYNAPRO=m
CONFIG_TOUCHSCREEN_HAMPSHIRE=m
CONFIG_TOUCHSCREEN_EETI=m
CONFIG_TOUCHSCREEN_EGALAX=m
CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
CONFIG_TOUCHSCREEN_EXC3000=m
CONFIG_TOUCHSCREEN_FUJITSU=m
CONFIG_TOUCHSCREEN_GOODIX=m
CONFIG_TOUCHSCREEN_HIDEEP=m
CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
CONFIG_TOUCHSCREEN_ILI210X=m
CONFIG_TOUCHSCREEN_ILITEK=m
CONFIG_TOUCHSCREEN_IPROC=m
CONFIG_TOUCHSCREEN_S6SY761=m
CONFIG_TOUCHSCREEN_GUNZE=m
CONFIG_TOUCHSCREEN_EKTF2127=m
CONFIG_TOUCHSCREEN_ELAN=m
CONFIG_TOUCHSCREEN_ELO=m
CONFIG_TOUCHSCREEN_WACOM_W8001=m
CONFIG_TOUCHSCREEN_WACOM_I2C=m
CONFIG_TOUCHSCREEN_MAX11801=m
CONFIG_TOUCHSCREEN_MCS5000=m
CONFIG_TOUCHSCREEN_MMS114=m
CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
CONFIG_TOUCHSCREEN_MSG2638=m
CONFIG_TOUCHSCREEN_MTOUCH=m
CONFIG_TOUCHSCREEN_IMAGIS=m
CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
CONFIG_TOUCHSCREEN_INEXIO=m
CONFIG_TOUCHSCREEN_MK712=m
CONFIG_TOUCHSCREEN_PENMOUNT=m
CONFIG_TOUCHSCREEN_EDT_FT5X06=m
CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m
CONFIG_TOUCHSCREEN_MIGOR=m
CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
CONFIG_TOUCHSCREEN_TOUCHWIN=m
CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m
CONFIG_TOUCHSCREEN_UCB1400=m
CONFIG_TOUCHSCREEN_PIXCIR=m
CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
CONFIG_TOUCHSCREEN_WM831X=m
CONFIG_TOUCHSCREEN_WM97XX=m
CONFIG_TOUCHSCREEN_WM9705=y
CONFIG_TOUCHSCREEN_WM9712=y
CONFIG_TOUCHSCREEN_WM9713=y
CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
CONFIG_TOUCHSCREEN_MXS_LRADC=m
CONFIG_TOUCHSCREEN_MX25=m
CONFIG_TOUCHSCREEN_MC13783=m
CONFIG_TOUCHSCREEN_USB_EGALAX=y
CONFIG_TOUCHSCREEN_USB_PANJIT=y
CONFIG_TOUCHSCREEN_USB_3M=y
CONFIG_TOUCHSCREEN_USB_ITM=y
CONFIG_TOUCHSCREEN_USB_ETURBO=y
CONFIG_TOUCHSCREEN_USB_GUNZE=y
CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
CONFIG_TOUCHSCREEN_USB_GOTOP=y
CONFIG_TOUCHSCREEN_USB_JASTEC=y
CONFIG_TOUCHSCREEN_USB_ELO=y
CONFIG_TOUCHSCREEN_USB_E2I=y
CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
CONFIG_TOUCHSCREEN_USB_NEXIO=y
CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
CONFIG_TOUCHSCREEN_TOUCHIT213=m
CONFIG_TOUCHSCREEN_TS4800=m
CONFIG_TOUCHSCREEN_TSC_SERIO=m
CONFIG_TOUCHSCREEN_TSC200X_CORE=m
CONFIG_TOUCHSCREEN_TSC2004=m
CONFIG_TOUCHSCREEN_TSC2005=m
CONFIG_TOUCHSCREEN_TSC2007=m
CONFIG_TOUCHSCREEN_TSC2007_IIO=y
CONFIG_TOUCHSCREEN_PCAP=m
CONFIG_TOUCHSCREEN_RM_TS=m
CONFIG_TOUCHSCREEN_SILEAD=m
CONFIG_TOUCHSCREEN_SIS_I2C=m
CONFIG_TOUCHSCREEN_ST1232=m
CONFIG_TOUCHSCREEN_STMFTS=m
CONFIG_TOUCHSCREEN_STMPE=m
CONFIG_TOUCHSCREEN_SUN4I=m
CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
CONFIG_TOUCHSCREEN_SX8654=m
CONFIG_TOUCHSCREEN_TPS6507X=m
CONFIG_TOUCHSCREEN_ZET6223=m
CONFIG_TOUCHSCREEN_ZFORCE=m
CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
CONFIG_TOUCHSCREEN_ROHM_BU21023=m
CONFIG_TOUCHSCREEN_IQS5XX=m
CONFIG_TOUCHSCREEN_ZINITIX=m
CONFIG_INPUT_MISC=y
CONFIG_INPUT_88PM80X_ONKEY=m
CONFIG_INPUT_AD714X=m
CONFIG_INPUT_AD714X_I2C=m
CONFIG_INPUT_AD714X_SPI=m
CONFIG_INPUT_ARIEL_PWRBUTTON=m
CONFIG_INPUT_ARIZONA_HAPTICS=m
CONFIG_INPUT_ATC260X_ONKEY=m
CONFIG_INPUT_ATMEL_CAPTOUCH=m
CONFIG_INPUT_BMA150=m
CONFIG_INPUT_E3X0_BUTTON=m
CONFIG_INPUT_PM8941_PWRKEY=m
CONFIG_INPUT_PM8XXX_VIBRATOR=m
CONFIG_INPUT_PMIC8XXX_PWRKEY=m
CONFIG_INPUT_MAX77650_ONKEY=m
CONFIG_INPUT_MAX77693_HAPTIC=m
CONFIG_INPUT_MC13783_PWRBUTTON=m
CONFIG_INPUT_MMA8450=m
CONFIG_INPUT_GPIO_BEEPER=m
CONFIG_INPUT_GPIO_DECODER=m
CONFIG_INPUT_GPIO_VIBRA=m
CONFIG_INPUT_CPCAP_PWRBUTTON=m
CONFIG_INPUT_ATI_REMOTE2=m
CONFIG_INPUT_KEYSPAN_REMOTE=m
CONFIG_INPUT_KXTJ9=m
CONFIG_INPUT_POWERMATE=m
CONFIG_INPUT_YEALINK=m
CONFIG_INPUT_CM109=m
CONFIG_INPUT_REGULATOR_HAPTIC=m
CONFIG_INPUT_RETU_PWRBUTTON=m
CONFIG_INPUT_TPS65218_PWRBUTTON=m
CONFIG_INPUT_AXP20X_PEK=m
CONFIG_INPUT_UINPUT=m
CONFIG_INPUT_PCF50633_PMU=m
CONFIG_INPUT_PCF8574=m
CONFIG_INPUT_PWM_BEEPER=m
CONFIG_INPUT_PWM_VIBRA=m
CONFIG_INPUT_RK805_PWRKEY=m
CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
CONFIG_INPUT_DA7280_HAPTICS=m
CONFIG_INPUT_DA9052_ONKEY=m
CONFIG_INPUT_DA9063_ONKEY=m
CONFIG_INPUT_WM831X_ON=m
CONFIG_INPUT_PCAP=m
CONFIG_INPUT_ADXL34X=m
CONFIG_INPUT_ADXL34X_I2C=m
CONFIG_INPUT_ADXL34X_SPI=m
CONFIG_INPUT_IBM_PANEL=m
CONFIG_INPUT_IMS_PCU=m
CONFIG_INPUT_IQS269A=m
CONFIG_INPUT_IQS626A=m
CONFIG_INPUT_IQS7222=m
CONFIG_INPUT_CMA3000=m
CONFIG_INPUT_CMA3000_I2C=m
CONFIG_INPUT_DRV260X_HAPTICS=m
CONFIG_INPUT_DRV2665_HAPTICS=m
CONFIG_INPUT_DRV2667_HAPTICS=m
CONFIG_INPUT_HISI_POWERKEY=m
CONFIG_INPUT_RAVE_SP_PWRBUTTON=m
CONFIG_INPUT_SC27XX_VIBRA=m
CONFIG_INPUT_RT5120_PWRKEY=m
CONFIG_RMI4_CORE=m
CONFIG_RMI4_I2C=m
CONFIG_RMI4_SPI=m
CONFIG_RMI4_SMB=m
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=m
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
CONFIG_RMI4_F34=y
CONFIG_RMI4_F3A=y
CONFIG_RMI4_F54=y
CONFIG_RMI4_F55=y

#
# Hardware I/O ports
#
CONFIG_SERIO=m
CONFIG_SERIO_SERPORT=m
CONFIG_SERIO_PARKBD=m
CONFIG_SERIO_LIBPS2=m
CONFIG_SERIO_RAW=m
CONFIG_SERIO_ALTERA_PS2=m
CONFIG_SERIO_PS2MULT=m
CONFIG_SERIO_ARC_PS2=m
CONFIG_SERIO_APBPS2=m
CONFIG_SERIO_OLPC_APSP=m
CONFIG_SERIO_SUN4I_PS2=m
CONFIG_SERIO_GPIO_PS2=m
CONFIG_USERIO=m
CONFIG_GAMEPORT=m
CONFIG_GAMEPORT_NS558=m
CONFIG_GAMEPORT_L4=m
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_LDISC_AUTOLOAD=y

#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=m
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_16550A_VARIANTS=y
CONFIG_SERIAL_8250_FINTEK=y
CONFIG_SERIAL_8250_CS=m
CONFIG_SERIAL_8250_MEN_MCB=m
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_ASPEED_VUART=m
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_BCM2835AUX=m
CONFIG_SERIAL_8250_DW=m
CONFIG_SERIAL_8250_EM=m
CONFIG_SERIAL_8250_IOC3=m
CONFIG_SERIAL_8250_RT288X=y
CONFIG_SERIAL_8250_OMAP=m
CONFIG_SERIAL_8250_LPC18XX=m
CONFIG_SERIAL_8250_MT6577=m
CONFIG_SERIAL_8250_UNIPHIER=m
CONFIG_SERIAL_8250_INGENIC=m
CONFIG_SERIAL_8250_PXA=m
CONFIG_SERIAL_8250_TEGRA=m
CONFIG_SERIAL_8250_BCM7271=m
CONFIG_SERIAL_OF_PLATFORM=m

#
# Non-8250 serial port support
#
CONFIG_SERIAL_AMBA_PL010=m
CONFIG_SERIAL_KGDB_NMI=y
CONFIG_SERIAL_MESON=m
CONFIG_SERIAL_MESON_CONSOLE=y
CONFIG_SERIAL_CLPS711X=m
CONFIG_SERIAL_SAMSUNG=m
CONFIG_SERIAL_SAMSUNG_UARTS_4=y
CONFIG_SERIAL_SAMSUNG_UARTS=4
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
CONFIG_SERIAL_TEGRA=m
CONFIG_SERIAL_TEGRA_TCU=m
CONFIG_SERIAL_MAX3100=m
CONFIG_SERIAL_MAX310X=m
CONFIG_SERIAL_IMX=m
CONFIG_SERIAL_IMX_CONSOLE=m
CONFIG_SERIAL_IMX_EARLYCON=y
CONFIG_SERIAL_UARTLITE=m
CONFIG_SERIAL_UARTLITE_NR_UARTS=1
CONFIG_SERIAL_SH_SCI=m
CONFIG_SERIAL_SH_SCI_NR_UARTS=10
CONFIG_SERIAL_HS_LPC32XX=m
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_CONSOLE_POLL=y
CONFIG_SERIAL_MSM=m
CONFIG_SERIAL_QCOM_GENI=m
CONFIG_SERIAL_QCOM_GENI_CONSOLE=y
CONFIG_SERIAL_VT8500=y
CONFIG_SERIAL_VT8500_CONSOLE=y
CONFIG_SERIAL_OMAP=m
CONFIG_SERIAL_SIFIVE=m
CONFIG_SERIAL_LANTIQ=m
CONFIG_SERIAL_QE=m
CONFIG_SERIAL_SCCNXP=m
CONFIG_SERIAL_SC16IS7XX_CORE=m
CONFIG_SERIAL_SC16IS7XX=m
CONFIG_SERIAL_SC16IS7XX_I2C=y
CONFIG_SERIAL_SC16IS7XX_SPI=y
CONFIG_SERIAL_TIMBERDALE=m
CONFIG_SERIAL_BCM63XX=m
CONFIG_SERIAL_ALTERA_JTAGUART=m
CONFIG_SERIAL_ALTERA_UART=m
CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
CONFIG_SERIAL_MXS_AUART=m
CONFIG_SERIAL_XILINX_PS_UART=m
CONFIG_SERIAL_MPS2_UART_CONSOLE=y
CONFIG_SERIAL_MPS2_UART=y
CONFIG_SERIAL_ARC=m
CONFIG_SERIAL_ARC_NR_PORTS=1
CONFIG_SERIAL_FSL_LINFLEXUART=m
CONFIG_SERIAL_CONEXANT_DIGICOLOR=m
CONFIG_SERIAL_ST_ASC=m
CONFIG_SERIAL_MEN_Z135=m
CONFIG_SERIAL_STM32=m
CONFIG_SERIAL_OWL=m
CONFIG_SERIAL_RDA=y
CONFIG_SERIAL_RDA_CONSOLE=y
CONFIG_SERIAL_MILBEAUT_USIO=m
CONFIG_SERIAL_MILBEAUT_USIO_PORTS=4
CONFIG_SERIAL_LITEUART=m
CONFIG_SERIAL_LITEUART_MAX_PORTS=1
CONFIG_SERIAL_SUNPLUS=m
CONFIG_SERIAL_SUNPLUS_CONSOLE=y
# end of Serial drivers

CONFIG_SERIAL_MCTRL_GPIO=m
CONFIG_SERIAL_NONSTANDARD=y
CONFIG_N_HDLC=m
CONFIG_N_GSM=m
CONFIG_NULL_TTY=m
CONFIG_HVC_DRIVER=y
CONFIG_RPMSG_TTY=m
CONFIG_SERIAL_DEV_BUS=m
CONFIG_TTY_PRINTK=m
CONFIG_TTY_PRINTK_LEVEL=6
CONFIG_PRINTER=m
CONFIG_LP_CONSOLE=y
CONFIG_PPDEV=m
CONFIG_VIRTIO_CONSOLE=m
CONFIG_IPMI_HANDLER=m
CONFIG_IPMI_PLAT_DATA=y
CONFIG_IPMI_PANIC_EVENT=y
CONFIG_IPMI_PANIC_STRING=y
CONFIG_IPMI_DEVICE_INTERFACE=m
CONFIG_IPMI_SI=m
CONFIG_IPMI_SSIF=m
CONFIG_IPMI_IPMB=m
CONFIG_IPMI_WATCHDOG=m
CONFIG_IPMI_POWEROFF=m
CONFIG_IPMI_KCS_BMC=m
CONFIG_ASPEED_KCS_IPMI_BMC=m
CONFIG_NPCM7XX_KCS_IPMI_BMC=m
CONFIG_IPMI_KCS_BMC_CDEV_IPMI=m
CONFIG_IPMI_KCS_BMC_SERIO=m
CONFIG_ASPEED_BT_IPMI_BMC=m
CONFIG_IPMB_DEVICE_INTERFACE=m
CONFIG_HW_RANDOM=m
CONFIG_HW_RANDOM_TIMERIOMEM=m
CONFIG_HW_RANDOM_ATMEL=m
CONFIG_HW_RANDOM_BA431=m
CONFIG_HW_RANDOM_BCM2835=m
CONFIG_HW_RANDOM_IPROC_RNG200=m
CONFIG_HW_RANDOM_IXP4XX=m
CONFIG_HW_RANDOM_OMAP=m
CONFIG_HW_RANDOM_OMAP3_ROM=m
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_IMX_RNGC=m
CONFIG_HW_RANDOM_NOMADIK=m
CONFIG_HW_RANDOM_STM32=m
CONFIG_HW_RANDOM_POLARFIRE_SOC=m
CONFIG_HW_RANDOM_MESON=m
CONFIG_HW_RANDOM_MTK=m
CONFIG_HW_RANDOM_EXYNOS=m
CONFIG_HW_RANDOM_NPCM=m
CONFIG_HW_RANDOM_KEYSTONE=m
CONFIG_HW_RANDOM_CCTRNG=m
CONFIG_HW_RANDOM_XIPHERA=m

#
# PCMCIA character devices
#
CONFIG_SYNCLINK_CS=m
CONFIG_CARDMAN_4000=m
CONFIG_CARDMAN_4040=m
CONFIG_SCR24X=m
CONFIG_IPWIRELESS=m
# end of PCMCIA character devices

CONFIG_DEVMEM=y
CONFIG_TCG_TPM=y
CONFIG_TCG_TIS_CORE=m
CONFIG_TCG_TIS=m
CONFIG_TCG_TIS_SPI=m
CONFIG_TCG_TIS_SPI_CR50=y
CONFIG_TCG_TIS_I2C=m
CONFIG_TCG_TIS_SYNQUACER=m
CONFIG_TCG_TIS_I2C_CR50=m
CONFIG_TCG_TIS_I2C_ATMEL=m
CONFIG_TCG_TIS_I2C_INFINEON=m
CONFIG_TCG_TIS_I2C_NUVOTON=m
CONFIG_TCG_VTPM_PROXY=m
CONFIG_TCG_TIS_ST33ZP24=m
CONFIG_TCG_TIS_ST33ZP24_I2C=m
CONFIG_TCG_TIS_ST33ZP24_SPI=m
CONFIG_XILLYBUS_CLASS=m
CONFIG_XILLYBUS=m
CONFIG_XILLYUSB=m
CONFIG_RANDOM_TRUST_CPU=y
CONFIG_RANDOM_TRUST_BOOTLOADER=y
# end of Character devices

#
# I2C support
#
CONFIG_I2C=m
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_MUX=m

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=m
CONFIG_I2C_MUX_GPIO=m
CONFIG_I2C_MUX_GPMUX=m
CONFIG_I2C_MUX_LTC4306=m
CONFIG_I2C_MUX_PCA9541=m
CONFIG_I2C_MUX_PCA954x=m
CONFIG_I2C_MUX_PINCTRL=m
CONFIG_I2C_MUX_REG=m
CONFIG_I2C_DEMUX_PINCTRL=m
CONFIG_I2C_MUX_MLXCPLD=m
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_SMBUS=m
CONFIG_I2C_ALGOBIT=m
CONFIG_I2C_ALGOPCA=m

#
# I2C Hardware Bus support
#
CONFIG_I2C_HIX5HD2=m

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
CONFIG_I2C_ALTERA=m
CONFIG_I2C_ASPEED=m
CONFIG_I2C_AT91=m
CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL=m
CONFIG_I2C_AXXIA=m
CONFIG_I2C_BCM_IPROC=m
CONFIG_I2C_BCM_KONA=m
CONFIG_I2C_BRCMSTB=m
CONFIG_I2C_CADENCE=m
CONFIG_I2C_CBUS_GPIO=m
CONFIG_I2C_DAVINCI=m
CONFIG_I2C_DESIGNWARE_CORE=m
CONFIG_I2C_DESIGNWARE_SLAVE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=m
CONFIG_I2C_DIGICOLOR=m
CONFIG_I2C_EMEV2=m
CONFIG_I2C_EXYNOS5=m
CONFIG_I2C_GPIO=m
CONFIG_I2C_GPIO_FAULT_INJECTOR=y
CONFIG_I2C_HIGHLANDER=m
CONFIG_I2C_HISI=m
CONFIG_I2C_IMG=m
CONFIG_I2C_IMX=m
CONFIG_I2C_IMX_LPI2C=m
CONFIG_I2C_IOP3XX=m
CONFIG_I2C_JZ4780=m
CONFIG_I2C_KEMPLD=m
CONFIG_I2C_LPC2K=m
CONFIG_I2C_MICROCHIP_CORE=m
CONFIG_I2C_MT65XX=m
CONFIG_I2C_MT7621=m
CONFIG_I2C_MV64XXX=m
CONFIG_I2C_MXS=m
CONFIG_I2C_NPCM=m
CONFIG_I2C_OCORES=m
CONFIG_I2C_OMAP=m
CONFIG_I2C_OWL=m
CONFIG_I2C_APPLE=m
CONFIG_I2C_PCA_PLATFORM=m
CONFIG_I2C_PNX=m
CONFIG_I2C_PXA=m
CONFIG_I2C_PXA_SLAVE=y
CONFIG_I2C_QCOM_CCI=m
CONFIG_I2C_QCOM_GENI=m
CONFIG_I2C_QUP=m
CONFIG_I2C_RIIC=m
CONFIG_I2C_RZV2M=m
CONFIG_I2C_S3C2410=m
CONFIG_I2C_SH_MOBILE=m
CONFIG_I2C_SIMTEC=m
CONFIG_I2C_ST=m
CONFIG_I2C_STM32F4=m
CONFIG_I2C_STM32F7=m
CONFIG_I2C_SUN6I_P2WI=m
CONFIG_I2C_SYNQUACER=m
CONFIG_I2C_TEGRA=m
CONFIG_I2C_TEGRA_BPMP=m
CONFIG_I2C_UNIPHIER=m
CONFIG_I2C_UNIPHIER_F=m
CONFIG_I2C_VERSATILE=m
CONFIG_I2C_WMT=m
CONFIG_I2C_XILINX=m
CONFIG_I2C_XLP9XX=m
CONFIG_I2C_RCAR=m

#
# External I2C/SMBus adapter drivers
#
CONFIG_I2C_DIOLAN_U2C=m
CONFIG_I2C_DLN2=m
CONFIG_I2C_CP2615=m
CONFIG_I2C_PARPORT=m
CONFIG_I2C_ROBOTFUZZ_OSIF=m
CONFIG_I2C_TAOS_EVM=m
CONFIG_I2C_TINY_USB=m
CONFIG_I2C_VIPERBOARD=m

#
# Other I2C/SMBus bus drivers
#
CONFIG_I2C_MLXCPLD=m
CONFIG_I2C_CROS_EC_TUNNEL=m
CONFIG_I2C_FSI=m
CONFIG_I2C_VIRTIO=m
# end of I2C Hardware Bus support

CONFIG_I2C_STUB=m
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=m
CONFIG_I2C_SLAVE_TESTUNIT=m
CONFIG_I2C_DEBUG_CORE=y
CONFIG_I2C_DEBUG_ALGO=y
CONFIG_I2C_DEBUG_BUS=y
# end of I2C support

CONFIG_I3C=m
CONFIG_CDNS_I3C_MASTER=m
CONFIG_DW_I3C_MASTER=m
CONFIG_SVC_I3C_MASTER=m
CONFIG_MIPI_I3C_HCI=m
CONFIG_SPI=y
CONFIG_SPI_DEBUG=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y

#
# SPI Master Controller Drivers
#
CONFIG_SPI_ALTERA=m
CONFIG_SPI_ALTERA_CORE=m
CONFIG_SPI_ALTERA_DFL=m
CONFIG_SPI_AR934X=m
CONFIG_SPI_ATH79=m
CONFIG_SPI_ARMADA_3700=m
CONFIG_SPI_ASPEED_SMC=m
CONFIG_SPI_ATMEL=m
CONFIG_SPI_AT91_USART=m
CONFIG_SPI_ATMEL_QUADSPI=m
CONFIG_SPI_AXI_SPI_ENGINE=m
CONFIG_SPI_BCM2835=m
CONFIG_SPI_BCM2835AUX=m
CONFIG_SPI_BCM63XX=m
CONFIG_SPI_BCM63XX_HSSPI=m
CONFIG_SPI_BCM_QSPI=m
CONFIG_SPI_BITBANG=m
CONFIG_SPI_BUTTERFLY=m
CONFIG_SPI_CADENCE=m
CONFIG_SPI_CADENCE_QUADSPI=m
CONFIG_SPI_CADENCE_XSPI=m
CONFIG_SPI_CLPS711X=m
CONFIG_SPI_DESIGNWARE=m
CONFIG_SPI_DW_DMA=y
CONFIG_SPI_DW_MMIO=m
CONFIG_SPI_DW_BT1=m
CONFIG_SPI_DW_BT1_DIRMAP=y
CONFIG_SPI_DLN2=m
CONFIG_SPI_EP93XX=m
CONFIG_SPI_FSI=m
CONFIG_SPI_FSL_LPSPI=m
CONFIG_SPI_FSL_QUADSPI=m
CONFIG_SPI_GXP=m
CONFIG_SPI_HISI_KUNPENG=m
CONFIG_SPI_HISI_SFC_V3XX=m
CONFIG_SPI_NXP_FLEXSPI=m
CONFIG_SPI_GPIO=m
CONFIG_SPI_IMG_SPFI=m
CONFIG_SPI_IMX=m
CONFIG_SPI_INGENIC=m
CONFIG_SPI_INTEL=m
CONFIG_SPI_INTEL_PLATFORM=m
CONFIG_SPI_JCORE=m
CONFIG_SPI_LM70_LLP=m
CONFIG_SPI_LP8841_RTC=m
CONFIG_SPI_FSL_LIB=m
CONFIG_SPI_FSL_SPI=m
CONFIG_SPI_FSL_DSPI=m
CONFIG_SPI_MESON_SPIFC=m
CONFIG_SPI_MICROCHIP_CORE=m
CONFIG_SPI_MICROCHIP_CORE_QSPI=m
CONFIG_SPI_MT65XX=m
CONFIG_SPI_MT7621=m
CONFIG_SPI_MTK_NOR=m
CONFIG_SPI_MTK_SNFI=m
CONFIG_SPI_NPCM_FIU=m
CONFIG_SPI_NPCM_PSPI=m
CONFIG_SPI_LANTIQ_SSC=m
CONFIG_SPI_OC_TINY=m
CONFIG_SPI_OMAP24XX=m
CONFIG_SPI_TI_QSPI=m
CONFIG_SPI_OMAP_100K=m
CONFIG_SPI_ORION=m
CONFIG_SPI_PIC32=m
CONFIG_SPI_PIC32_SQI=m
CONFIG_SPI_PXA2XX=m
CONFIG_SPI_ROCKCHIP=m
CONFIG_SPI_RPCIF=m
CONFIG_SPI_RSPI=m
CONFIG_SPI_QUP=m
CONFIG_SPI_QCOM_GENI=m
CONFIG_SPI_S3C64XX=m
CONFIG_SPI_SC18IS602=m
CONFIG_SPI_SH_MSIOF=m
CONFIG_SPI_SH=m
CONFIG_SPI_SH_SCI=m
CONFIG_SPI_SH_HSPI=m
CONFIG_SPI_SIFIVE=m
CONFIG_SPI_SLAVE_MT27XX=m
CONFIG_SPI_SPRD=m
CONFIG_SPI_SPRD_ADI=m
CONFIG_SPI_STM32=m
CONFIG_SPI_STM32_QSPI=m
CONFIG_SPI_ST_SSC4=m
CONFIG_SPI_SUN4I=m
CONFIG_SPI_SUN6I=m
CONFIG_SPI_SUNPLUS_SP7021=m
CONFIG_SPI_SYNQUACER=m
CONFIG_SPI_MXIC=m
CONFIG_SPI_TEGRA210_QUAD=m
CONFIG_SPI_TEGRA114=m
CONFIG_SPI_TEGRA20_SFLASH=m
CONFIG_SPI_TEGRA20_SLINK=m
CONFIG_SPI_UNIPHIER=m
CONFIG_SPI_XCOMM=m
CONFIG_SPI_XILINX=m
CONFIG_SPI_XLP=m
CONFIG_SPI_XTENSA_XTFPGA=m
CONFIG_SPI_ZYNQ_QSPI=m
CONFIG_SPI_ZYNQMP_GQSPI=m
CONFIG_SPI_AMD=m

#
# SPI Multiplexer support
#
CONFIG_SPI_MUX=m

#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=m
CONFIG_SPI_LOOPBACK_TEST=m
CONFIG_SPI_TLE62X0=m
CONFIG_SPI_SLAVE=y
CONFIG_SPI_SLAVE_TIME=m
CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m
CONFIG_SPI_DYNAMIC=y
CONFIG_SPMI=m
CONFIG_SPMI_HISI3670=m
CONFIG_SPMI_MSM_PMIC_ARB=m
CONFIG_SPMI_MTK_PMIF=m
CONFIG_HSI=m
CONFIG_HSI_BOARDINFO=y

#
# HSI controllers
#

#
# HSI clients
#
CONFIG_HSI_CHAR=m
CONFIG_PPS=m
CONFIG_PPS_DEBUG=y

#
# PPS clients support
#
CONFIG_PPS_CLIENT_KTIMER=m
CONFIG_PPS_CLIENT_LDISC=m
CONFIG_PPS_CLIENT_PARPORT=m
CONFIG_PPS_CLIENT_GPIO=m

#
# PPS generators support
#

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=m
CONFIG_PTP_1588_CLOCK_OPTIONAL=m
CONFIG_PTP_1588_CLOCK_DTE=m
CONFIG_PTP_1588_CLOCK_QORIQ=m
CONFIG_DP83640_PHY=m
CONFIG_PTP_1588_CLOCK_INES=m
CONFIG_PTP_1588_CLOCK_IDT82P33=m
CONFIG_PTP_1588_CLOCK_IDTCM=m
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
CONFIG_DEBUG_PINCTRL=y
CONFIG_PINCTRL_AMD=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_PINCTRL_AXP209=m
CONFIG_PINCTRL_BM1880=y
CONFIG_PINCTRL_CY8C95X0=m
CONFIG_PINCTRL_DA850_PUPD=m
CONFIG_PINCTRL_DA9062=m
CONFIG_PINCTRL_EQUILIBRIUM=m
CONFIG_PINCTRL_INGENIC=y
CONFIG_PINCTRL_LPC18XX=y
CONFIG_PINCTRL_MCP23S08_I2C=m
CONFIG_PINCTRL_MCP23S08_SPI=m
CONFIG_PINCTRL_MCP23S08=m
CONFIG_PINCTRL_MICROCHIP_SGPIO=m
CONFIG_PINCTRL_OCELOT=m
CONFIG_PINCTRL_PISTACHIO=y
CONFIG_PINCTRL_RK805=m
CONFIG_PINCTRL_ROCKCHIP=m
CONFIG_PINCTRL_SINGLE=m
CONFIG_PINCTRL_STMFX=m
CONFIG_PINCTRL_OWL=y
CONFIG_PINCTRL_S500=y
CONFIG_PINCTRL_S700=y
CONFIG_PINCTRL_S900=y
CONFIG_PINCTRL_ASPEED=y
CONFIG_PINCTRL_ASPEED_G4=y
CONFIG_PINCTRL_ASPEED_G5=y
CONFIG_PINCTRL_ASPEED_G6=y
CONFIG_PINCTRL_BCM281XX=y
CONFIG_PINCTRL_BCM2835=m
CONFIG_PINCTRL_BCM4908=m
CONFIG_PINCTRL_BCM63XX=y
CONFIG_PINCTRL_BCM6318=y
CONFIG_PINCTRL_BCM6328=y
CONFIG_PINCTRL_BCM6358=y
CONFIG_PINCTRL_BCM6362=y
CONFIG_PINCTRL_BCM6368=y
CONFIG_PINCTRL_BCM63268=y
CONFIG_PINCTRL_IPROC_GPIO=y
CONFIG_PINCTRL_CYGNUS_MUX=y
CONFIG_PINCTRL_NS=y
CONFIG_PINCTRL_NSP_GPIO=y
CONFIG_PINCTRL_NS2_MUX=y
CONFIG_PINCTRL_NSP_MUX=y
CONFIG_PINCTRL_BERLIN=y
CONFIG_PINCTRL_AS370=y
CONFIG_PINCTRL_BERLIN_BG4CT=y
CONFIG_PINCTRL_MADERA=m
CONFIG_PINCTRL_CS47L15=y
CONFIG_PINCTRL_CS47L35=y
CONFIG_PINCTRL_CS47L85=y
CONFIG_PINCTRL_CS47L90=y
CONFIG_PINCTRL_CS47L92=y
CONFIG_PINCTRL_IMX=m
CONFIG_PINCTRL_IMX8MM=m
CONFIG_PINCTRL_IMX8MN=m
CONFIG_PINCTRL_IMX8MP=m
CONFIG_PINCTRL_IMX8MQ=m

#
# Intel pinctrl drivers
#
# end of Intel pinctrl drivers

#
# MediaTek pinctrl drivers
#
CONFIG_EINT_MTK=y
CONFIG_PINCTRL_MTK=y
CONFIG_PINCTRL_MTK_V2=y
CONFIG_PINCTRL_MTK_MOORE=y
CONFIG_PINCTRL_MTK_PARIS=y
CONFIG_PINCTRL_MT2701=y
CONFIG_PINCTRL_MT7623=y
CONFIG_PINCTRL_MT7629=y
CONFIG_PINCTRL_MT8135=y
CONFIG_PINCTRL_MT8127=y
CONFIG_PINCTRL_MT2712=y
CONFIG_PINCTRL_MT6765=m
CONFIG_PINCTRL_MT6779=m
CONFIG_PINCTRL_MT6795=y
CONFIG_PINCTRL_MT6797=y
CONFIG_PINCTRL_MT7622=y
CONFIG_PINCTRL_MT7986=y
CONFIG_PINCTRL_MT8167=y
CONFIG_PINCTRL_MT8173=y
CONFIG_PINCTRL_MT8183=y
CONFIG_PINCTRL_MT8186=y
CONFIG_PINCTRL_MT8188=y
CONFIG_PINCTRL_MT8192=y
CONFIG_PINCTRL_MT8195=y
CONFIG_PINCTRL_MT8365=y
CONFIG_PINCTRL_MT8516=y
CONFIG_PINCTRL_MT6397=y
# end of MediaTek pinctrl drivers

CONFIG_PINCTRL_MESON=m
CONFIG_PINCTRL_WPCM450=m
CONFIG_PINCTRL_NPCM7XX=y
CONFIG_PINCTRL_PXA=y
CONFIG_PINCTRL_PXA25X=m
CONFIG_PINCTRL_PXA27X=m
CONFIG_PINCTRL_MSM=m
CONFIG_PINCTRL_APQ8064=m
CONFIG_PINCTRL_APQ8084=m
CONFIG_PINCTRL_IPQ4019=m
CONFIG_PINCTRL_IPQ8064=m
CONFIG_PINCTRL_IPQ8074=m
CONFIG_PINCTRL_IPQ6018=m
CONFIG_PINCTRL_MSM8226=m
CONFIG_PINCTRL_MSM8660=m
CONFIG_PINCTRL_MSM8960=m
CONFIG_PINCTRL_MDM9607=m
CONFIG_PINCTRL_MDM9615=m
CONFIG_PINCTRL_MSM8X74=m
CONFIG_PINCTRL_MSM8909=m
CONFIG_PINCTRL_MSM8916=m
CONFIG_PINCTRL_MSM8953=m
CONFIG_PINCTRL_MSM8976=m
CONFIG_PINCTRL_MSM8994=m
CONFIG_PINCTRL_MSM8996=m
CONFIG_PINCTRL_MSM8998=m
CONFIG_PINCTRL_QCM2290=m
CONFIG_PINCTRL_QCS404=m
CONFIG_PINCTRL_QCOM_SPMI_PMIC=m
CONFIG_PINCTRL_QCOM_SSBI_PMIC=m
CONFIG_PINCTRL_SC7180=m
CONFIG_PINCTRL_SC7280=m
CONFIG_PINCTRL_SC7280_LPASS_LPI=m
CONFIG_PINCTRL_SC8180X=m
CONFIG_PINCTRL_SC8280XP=m
CONFIG_PINCTRL_SDM660=m
CONFIG_PINCTRL_SDM845=m
CONFIG_PINCTRL_SDX55=m
CONFIG_PINCTRL_SM6115=m
CONFIG_PINCTRL_SM6125=m
CONFIG_PINCTRL_SM6350=m
CONFIG_PINCTRL_SM6375=m
CONFIG_PINCTRL_SDX65=m
CONFIG_PINCTRL_SM8150=m
CONFIG_PINCTRL_SM8250=m
CONFIG_PINCTRL_SM8250_LPASS_LPI=m
CONFIG_PINCTRL_SM8350=m
CONFIG_PINCTRL_SM8450=m
CONFIG_PINCTRL_SM8450_LPASS_LPI=m
CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
CONFIG_PINCTRL_LPASS_LPI=m

#
# Renesas pinctrl drivers
#
CONFIG_PINCTRL_RENESAS=y
CONFIG_PINCTRL_SH_PFC=y
CONFIG_PINCTRL_SH_PFC_GPIO=y
CONFIG_PINCTRL_SH_FUNC_GPIO=y
CONFIG_PINCTRL_PFC_EMEV2=y
CONFIG_PINCTRL_PFC_R8A77995=y
CONFIG_PINCTRL_PFC_R8A7794=y
CONFIG_PINCTRL_PFC_R8A77990=y
CONFIG_PINCTRL_PFC_R8A7779=y
CONFIG_PINCTRL_PFC_R8A7790=y
CONFIG_PINCTRL_PFC_R8A77950=y
CONFIG_PINCTRL_PFC_R8A77951=y
CONFIG_PINCTRL_PFC_R8A7778=y
CONFIG_PINCTRL_PFC_R8A7793=y
CONFIG_PINCTRL_PFC_R8A7791=y
CONFIG_PINCTRL_PFC_R8A77965=y
CONFIG_PINCTRL_PFC_R8A77960=y
CONFIG_PINCTRL_PFC_R8A77961=y
CONFIG_PINCTRL_PFC_R8A779F0=y
CONFIG_PINCTRL_PFC_R8A7792=y
CONFIG_PINCTRL_PFC_R8A77980=y
CONFIG_PINCTRL_PFC_R8A77970=y
CONFIG_PINCTRL_PFC_R8A779A0=y
CONFIG_PINCTRL_PFC_R8A779G0=y
CONFIG_PINCTRL_PFC_R8A7740=y
CONFIG_PINCTRL_PFC_R8A73A4=y
CONFIG_PINCTRL_RZA1=y
CONFIG_PINCTRL_RZA2=y
CONFIG_PINCTRL_RZG2L=y
CONFIG_PINCTRL_PFC_R8A77470=y
CONFIG_PINCTRL_PFC_R8A7745=y
CONFIG_PINCTRL_PFC_R8A7742=y
CONFIG_PINCTRL_PFC_R8A7743=y
CONFIG_PINCTRL_PFC_R8A7744=y
CONFIG_PINCTRL_PFC_R8A774C0=y
CONFIG_PINCTRL_PFC_R8A774E1=y
CONFIG_PINCTRL_PFC_R8A774A1=y
CONFIG_PINCTRL_PFC_R8A774B1=y
CONFIG_PINCTRL_RZN1=y
CONFIG_PINCTRL_RZV2M=y
CONFIG_PINCTRL_PFC_SH7203=y
CONFIG_PINCTRL_PFC_SH7264=y
CONFIG_PINCTRL_PFC_SH7269=y
CONFIG_PINCTRL_PFC_SH7720=y
CONFIG_PINCTRL_PFC_SH7722=y
CONFIG_PINCTRL_PFC_SH7734=y
CONFIG_PINCTRL_PFC_SH7757=y
CONFIG_PINCTRL_PFC_SH7785=y
CONFIG_PINCTRL_PFC_SH7786=y
CONFIG_PINCTRL_PFC_SH73A0=y
CONFIG_PINCTRL_PFC_SH7723=y
CONFIG_PINCTRL_PFC_SH7724=y
CONFIG_PINCTRL_PFC_SHX3=y
# end of Renesas pinctrl drivers

CONFIG_PINCTRL_SAMSUNG=y
CONFIG_PINCTRL_EXYNOS=y
CONFIG_PINCTRL_EXYNOS_ARM=y
CONFIG_PINCTRL_EXYNOS_ARM64=y
CONFIG_PINCTRL_S3C24XX=y
CONFIG_PINCTRL_S3C64XX=y
CONFIG_PINCTRL_SPRD=m
CONFIG_PINCTRL_SPRD_SC9860=m
CONFIG_PINCTRL_STARFIVE_JH7100=m
CONFIG_PINCTRL_STM32=y
CONFIG_PINCTRL_STM32F429=y
CONFIG_PINCTRL_STM32F469=y
CONFIG_PINCTRL_STM32F746=y
CONFIG_PINCTRL_STM32F769=y
CONFIG_PINCTRL_STM32H743=y
CONFIG_PINCTRL_STM32MP135=y
CONFIG_PINCTRL_STM32MP157=y
CONFIG_PINCTRL_TI_IODELAY=m
CONFIG_PINCTRL_UNIPHIER=y
CONFIG_PINCTRL_UNIPHIER_LD4=y
CONFIG_PINCTRL_UNIPHIER_PRO4=y
CONFIG_PINCTRL_UNIPHIER_SLD8=y
CONFIG_PINCTRL_UNIPHIER_PRO5=y
CONFIG_PINCTRL_UNIPHIER_PXS2=y
CONFIG_PINCTRL_UNIPHIER_LD6B=y
CONFIG_PINCTRL_UNIPHIER_LD11=y
CONFIG_PINCTRL_UNIPHIER_LD20=y
CONFIG_PINCTRL_UNIPHIER_PXS3=y
CONFIG_PINCTRL_UNIPHIER_NX1=y
CONFIG_PINCTRL_VISCONTI=y
CONFIG_PINCTRL_TMPV7700=y
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_REGMAP=y
CONFIG_GPIO_MAX730X=m

#
# Memory mapped GPIO drivers
#
CONFIG_GPIO_74XX_MMIO=m
CONFIG_GPIO_ALTERA=m
CONFIG_GPIO_ASPEED=m
CONFIG_GPIO_ASPEED_SGPIO=y
CONFIG_GPIO_ATH79=m
CONFIG_GPIO_RASPBERRYPI_EXP=m
CONFIG_GPIO_BCM_KONA=y
CONFIG_GPIO_BCM_XGS_IPROC=m
CONFIG_GPIO_BRCMSTB=m
CONFIG_GPIO_CADENCE=m
CONFIG_GPIO_CLPS711X=m
CONFIG_GPIO_DWAPB=m
CONFIG_GPIO_EIC_SPRD=m
CONFIG_GPIO_EM=m
CONFIG_GPIO_FTGPIO010=y
CONFIG_GPIO_GENERIC_PLATFORM=m
CONFIG_GPIO_GRGPIO=m
CONFIG_GPIO_HISI=m
CONFIG_GPIO_HLWD=m
CONFIG_GPIO_IMX_SCU=y
CONFIG_GPIO_IOP=m
CONFIG_GPIO_LOGICVC=m
CONFIG_GPIO_LPC18XX=m
CONFIG_GPIO_LPC32XX=m
CONFIG_GPIO_MB86S7X=m
CONFIG_GPIO_MENZ127=m
CONFIG_GPIO_MPC8XXX=y
CONFIG_GPIO_MT7621=y
CONFIG_GPIO_MXC=m
CONFIG_GPIO_MXS=y
CONFIG_GPIO_PMIC_EIC_SPRD=m
CONFIG_GPIO_PXA=y
CONFIG_GPIO_RCAR=m
CONFIG_GPIO_RDA=y
CONFIG_GPIO_ROCKCHIP=m
CONFIG_GPIO_SAMA5D2_PIOBU=m
CONFIG_GPIO_SIFIVE=y
CONFIG_GPIO_SIOX=m
CONFIG_GPIO_SNPS_CREG=y
CONFIG_GPIO_SPRD=m
CONFIG_GPIO_STP_XWAY=y
CONFIG_GPIO_SYSCON=m
CONFIG_GPIO_TEGRA=m
CONFIG_GPIO_TEGRA186=m
CONFIG_GPIO_TS4800=m
CONFIG_GPIO_UNIPHIER=m
CONFIG_GPIO_VISCONTI=m
CONFIG_GPIO_WCD934X=m
CONFIG_GPIO_XGENE_SB=m
CONFIG_GPIO_XILINX=m
CONFIG_GPIO_XLP=m
CONFIG_GPIO_AMD_FCH=m
CONFIG_GPIO_IDT3243X=m
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
CONFIG_GPIO_ADNP=m
CONFIG_GPIO_GW_PLD=m
CONFIG_GPIO_MAX7300=m
CONFIG_GPIO_MAX732X=m
CONFIG_GPIO_PCA953X=m
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GPIO_PCA9570=m
CONFIG_GPIO_PCF857X=m
CONFIG_GPIO_TPIC2810=m
CONFIG_GPIO_TS4900=m
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
CONFIG_GPIO_ARIZONA=m
CONFIG_GPIO_BD9571MWV=m
CONFIG_GPIO_DA9052=m
CONFIG_GPIO_DLN2=m
CONFIG_GPIO_KEMPLD=m
CONFIG_GPIO_LP3943=m
CONFIG_GPIO_LP873X=m
CONFIG_GPIO_LP87565=m
CONFIG_GPIO_MADERA=m
CONFIG_GPIO_MAX77650=m
CONFIG_GPIO_SL28CPLD=m
CONFIG_GPIO_STMPE=y
CONFIG_GPIO_TPS65086=m
CONFIG_GPIO_TPS65218=m
CONFIG_GPIO_TPS65912=m
CONFIG_GPIO_UCB1400=m
CONFIG_GPIO_WM831X=m
CONFIG_GPIO_WM8994=m
# end of MFD GPIO expanders

#
# SPI GPIO expanders
#
CONFIG_GPIO_74X164=m
CONFIG_GPIO_MAX3191X=m
CONFIG_GPIO_MAX7301=m
CONFIG_GPIO_MC33880=m
CONFIG_GPIO_PISOSR=m
CONFIG_GPIO_XRA1403=m
CONFIG_GPIO_MOXTET=m
# end of SPI GPIO expanders

#
# USB GPIO expanders
#
CONFIG_GPIO_VIPERBOARD=m
# end of USB GPIO expanders

#
# Virtual GPIO drivers
#
CONFIG_GPIO_AGGREGATOR=m
CONFIG_GPIO_MOCKUP=m
CONFIG_GPIO_VIRTIO=m
CONFIG_GPIO_SIM=m
# end of Virtual GPIO drivers

CONFIG_W1=m
CONFIG_W1_CON=y

#
# 1-wire Bus Masters
#
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
CONFIG_W1_MASTER_MXC=m
CONFIG_W1_MASTER_DS1WM=m
CONFIG_W1_MASTER_GPIO=m
CONFIG_W1_MASTER_SGI=m
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
CONFIG_W1_SLAVE_DS2405=m
CONFIG_W1_SLAVE_DS2408=m
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2413=m
CONFIG_W1_SLAVE_DS2406=m
CONFIG_W1_SLAVE_DS2423=m
CONFIG_W1_SLAVE_DS2805=m
CONFIG_W1_SLAVE_DS2430=m
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2433_CRC=y
CONFIG_W1_SLAVE_DS2438=m
CONFIG_W1_SLAVE_DS250X=m
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=m
CONFIG_W1_SLAVE_DS28E17=m
# end of 1-wire Slaves

CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_ATC260X=m
CONFIG_POWER_RESET_BRCMKONA=y
CONFIG_POWER_RESET_BRCMSTB=y
CONFIG_POWER_RESET_GEMINI_POWEROFF=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
CONFIG_POWER_RESET_LINKSTATION=m
CONFIG_POWER_RESET_OCELOT_RESET=y
CONFIG_POWER_RESET_LTC2952=y
CONFIG_POWER_RESET_MT6323=y
CONFIG_POWER_RESET_REGULATOR=y
CONFIG_POWER_RESET_RESTART=y
CONFIG_POWER_RESET_TPS65086=y
CONFIG_POWER_RESET_KEYSTONE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_POWER_RESET_RMOBILE=m
CONFIG_REBOOT_MODE=m
CONFIG_SYSCON_REBOOT_MODE=m
CONFIG_POWER_RESET_SC27XX=m
CONFIG_NVMEM_REBOOT_MODE=m
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_SUPPLY_DEBUG=y
CONFIG_PDA_POWER=m
CONFIG_GENERIC_ADC_BATTERY=m
CONFIG_IP5XXX_POWER=m
CONFIG_WM831X_BACKUP=m
CONFIG_WM831X_POWER=m
CONFIG_TEST_POWER=m
CONFIG_CHARGER_ADP5061=m
CONFIG_BATTERY_ACT8945A=m
CONFIG_BATTERY_CPCAP=m
CONFIG_BATTERY_CW2015=m
CONFIG_BATTERY_DS2760=m
CONFIG_BATTERY_DS2780=m
CONFIG_BATTERY_DS2781=m
CONFIG_BATTERY_DS2782=m
CONFIG_BATTERY_LEGO_EV3=m
CONFIG_BATTERY_OLPC=m
CONFIG_BATTERY_SAMSUNG_SDI=y
CONFIG_BATTERY_INGENIC=m
CONFIG_BATTERY_SBS=m
CONFIG_CHARGER_SBS=m
CONFIG_MANAGER_SBS=m
CONFIG_BATTERY_BQ27XXX=m
CONFIG_BATTERY_BQ27XXX_I2C=m
CONFIG_BATTERY_BQ27XXX_HDQ=m
CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM=y
CONFIG_BATTERY_DA9052=m
CONFIG_CHARGER_DA9150=m
CONFIG_BATTERY_DA9150=m
CONFIG_CHARGER_AXP20X=m
CONFIG_BATTERY_AXP20X=m
CONFIG_AXP20X_POWER=m
CONFIG_BATTERY_MAX17040=m
CONFIG_BATTERY_MAX17042=m
CONFIG_BATTERY_MAX1721X=m
CONFIG_CHARGER_PCF50633=m
CONFIG_CHARGER_CPCAP=m
CONFIG_CHARGER_ISP1704=m
CONFIG_CHARGER_MAX8903=m
CONFIG_CHARGER_LP8727=m
CONFIG_CHARGER_GPIO=m
CONFIG_CHARGER_MANAGER=m
CONFIG_CHARGER_LT3651=m
CONFIG_CHARGER_LTC4162L=m
CONFIG_CHARGER_MAX14577=m
CONFIG_CHARGER_DETECTOR_MAX14656=m
CONFIG_CHARGER_MAX77650=m
CONFIG_CHARGER_MAX77693=m
CONFIG_CHARGER_MAX77976=m
CONFIG_CHARGER_MP2629=m
CONFIG_CHARGER_MT6360=m
CONFIG_CHARGER_MT6370=m
CONFIG_CHARGER_QCOM_SMBB=m
CONFIG_CHARGER_BQ2415X=m
CONFIG_CHARGER_BQ24190=m
CONFIG_CHARGER_BQ24257=m
CONFIG_CHARGER_BQ24735=m
CONFIG_CHARGER_BQ2515X=m
CONFIG_CHARGER_BQ25890=m
CONFIG_CHARGER_BQ25980=m
CONFIG_CHARGER_BQ256XX=m
CONFIG_CHARGER_RK817=m
CONFIG_CHARGER_SMB347=m
CONFIG_CHARGER_TPS65217=m
CONFIG_BATTERY_GAUGE_LTC2941=m
CONFIG_BATTERY_GOLDFISH=m
CONFIG_BATTERY_RT5033=m
CONFIG_CHARGER_RT9455=m
CONFIG_CHARGER_CROS_USBPD=m
CONFIG_CHARGER_CROS_PCHG=m
CONFIG_CHARGER_SC2731=m
CONFIG_FUEL_GAUGE_SC27XX=m
CONFIG_CHARGER_UCS1002=m
CONFIG_CHARGER_BD99954=m
CONFIG_RN5T618_POWER=m
CONFIG_BATTERY_ACER_A500=m
CONFIG_BATTERY_UG3105=m
CONFIG_HWMON=m
CONFIG_HWMON_VID=m
CONFIG_HWMON_DEBUG_CHIP=y

#
# Native drivers
#
CONFIG_SENSORS_AD7314=m
CONFIG_SENSORS_AD7414=m
CONFIG_SENSORS_AD7418=m
CONFIG_SENSORS_ADM1025=m
CONFIG_SENSORS_ADM1026=m
CONFIG_SENSORS_ADM1029=m
CONFIG_SENSORS_ADM1031=m
CONFIG_SENSORS_ADM1177=m
CONFIG_SENSORS_ADM9240=m
CONFIG_SENSORS_ADT7X10=m
CONFIG_SENSORS_ADT7310=m
CONFIG_SENSORS_ADT7410=m
CONFIG_SENSORS_ADT7411=m
CONFIG_SENSORS_ADT7462=m
CONFIG_SENSORS_ADT7470=m
CONFIG_SENSORS_ADT7475=m
CONFIG_SENSORS_AHT10=m
CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m
CONFIG_SENSORS_AS370=m
CONFIG_SENSORS_ASC7621=m
CONFIG_SENSORS_AXI_FAN_CONTROL=m
CONFIG_SENSORS_ARM_SCMI=m
CONFIG_SENSORS_ARM_SCPI=m
CONFIG_SENSORS_ASB100=m
CONFIG_SENSORS_ASPEED=m
CONFIG_SENSORS_ATXP1=m
CONFIG_SENSORS_BT1_PVT=m
CONFIG_SENSORS_BT1_PVT_ALARMS=y
CONFIG_SENSORS_CORSAIR_CPRO=m
CONFIG_SENSORS_CORSAIR_PSU=m
CONFIG_SENSORS_DRIVETEMP=m
CONFIG_SENSORS_DS620=m
CONFIG_SENSORS_DS1621=m
CONFIG_SENSORS_DA9052_ADC=m
CONFIG_SENSORS_SPARX5=m
CONFIG_SENSORS_F71805F=m
CONFIG_SENSORS_F71882FG=m
CONFIG_SENSORS_F75375S=m
CONFIG_SENSORS_GSC=m
CONFIG_SENSORS_MC13783_ADC=m
CONFIG_SENSORS_FSCHMD=m
CONFIG_SENSORS_FTSTEUTATES=m
CONFIG_SENSORS_GL518SM=m
CONFIG_SENSORS_GL520SM=m
CONFIG_SENSORS_G760A=m
CONFIG_SENSORS_G762=m
CONFIG_SENSORS_GPIO_FAN=m
CONFIG_SENSORS_HIH6130=m
CONFIG_SENSORS_IBMAEM=m
CONFIG_SENSORS_IBMPEX=m
CONFIG_SENSORS_IIO_HWMON=m
CONFIG_SENSORS_IT87=m
CONFIG_SENSORS_JC42=m
CONFIG_SENSORS_POWR1220=m
CONFIG_SENSORS_LAN966X=m
CONFIG_SENSORS_LINEAGE=m
CONFIG_SENSORS_LTC2945=m
CONFIG_SENSORS_LTC2947=m
CONFIG_SENSORS_LTC2947_I2C=m
CONFIG_SENSORS_LTC2947_SPI=m
CONFIG_SENSORS_LTC2990=m
CONFIG_SENSORS_LTC2992=m
CONFIG_SENSORS_LTC4151=m
CONFIG_SENSORS_LTC4215=m
CONFIG_SENSORS_LTC4222=m
CONFIG_SENSORS_LTC4245=m
CONFIG_SENSORS_LTC4260=m
CONFIG_SENSORS_LTC4261=m
CONFIG_SENSORS_MAX1111=m
CONFIG_SENSORS_MAX127=m
CONFIG_SENSORS_MAX16065=m
CONFIG_SENSORS_MAX1619=m
CONFIG_SENSORS_MAX1668=m
CONFIG_SENSORS_MAX197=m
CONFIG_SENSORS_MAX31722=m
CONFIG_SENSORS_MAX31730=m
CONFIG_SENSORS_MAX31760=m
CONFIG_SENSORS_MAX6620=m
CONFIG_SENSORS_MAX6621=m
CONFIG_SENSORS_MAX6639=m
CONFIG_SENSORS_MAX6650=m
CONFIG_SENSORS_MAX6697=m
CONFIG_SENSORS_MAX31790=m
CONFIG_SENSORS_MCP3021=m
CONFIG_SENSORS_MLXREG_FAN=m
CONFIG_SENSORS_TC654=m
CONFIG_SENSORS_TPS23861=m
CONFIG_SENSORS_MENF21BMC_HWMON=m
CONFIG_SENSORS_MR75203=m
CONFIG_SENSORS_ADCXX=m
CONFIG_SENSORS_LM63=m
CONFIG_SENSORS_LM70=m
CONFIG_SENSORS_LM73=m
CONFIG_SENSORS_LM75=m
CONFIG_SENSORS_LM77=m
CONFIG_SENSORS_LM78=m
CONFIG_SENSORS_LM80=m
CONFIG_SENSORS_LM83=m
CONFIG_SENSORS_LM85=m
CONFIG_SENSORS_LM87=m
CONFIG_SENSORS_LM90=m
CONFIG_SENSORS_LM92=m
CONFIG_SENSORS_LM93=m
CONFIG_SENSORS_LM95234=m
CONFIG_SENSORS_LM95241=m
CONFIG_SENSORS_LM95245=m
CONFIG_SENSORS_PC87360=m
CONFIG_SENSORS_PC87427=m
CONFIG_SENSORS_NTC_THERMISTOR=m
CONFIG_SENSORS_NCT6683=m
CONFIG_SENSORS_NCT6775_CORE=m
CONFIG_SENSORS_NCT6775=m
CONFIG_SENSORS_NCT6775_I2C=m
CONFIG_SENSORS_NCT7802=m
CONFIG_SENSORS_NCT7904=m
CONFIG_SENSORS_NPCM7XX=m
CONFIG_SENSORS_NSA320=m
CONFIG_SENSORS_NZXT_KRAKEN2=m
CONFIG_SENSORS_NZXT_SMART2=m
CONFIG_SENSORS_OCC_P8_I2C=m
CONFIG_SENSORS_OCC_P9_SBE=m
CONFIG_SENSORS_OCC=m
CONFIG_SENSORS_PCF8591=m
CONFIG_SENSORS_PECI_CPUTEMP=m
CONFIG_SENSORS_PECI_DIMMTEMP=m
CONFIG_SENSORS_PECI=m
CONFIG_PMBUS=m
CONFIG_SENSORS_PMBUS=m
CONFIG_SENSORS_ADM1266=m
CONFIG_SENSORS_ADM1275=m
CONFIG_SENSORS_BEL_PFE=m
CONFIG_SENSORS_BPA_RS600=m
CONFIG_SENSORS_DELTA_AHE50DC_FAN=m
CONFIG_SENSORS_FSP_3Y=m
CONFIG_SENSORS_IBM_CFFPS=m
CONFIG_SENSORS_DPS920AB=m
CONFIG_SENSORS_INSPUR_IPSPS=m
CONFIG_SENSORS_IR35221=m
CONFIG_SENSORS_IR36021=m
CONFIG_SENSORS_IR38064=m
CONFIG_SENSORS_IR38064_REGULATOR=y
CONFIG_SENSORS_IRPS5401=m
CONFIG_SENSORS_ISL68137=m
CONFIG_SENSORS_LM25066=m
CONFIG_SENSORS_LM25066_REGULATOR=y
CONFIG_SENSORS_LT7182S=m
CONFIG_SENSORS_LTC2978=m
CONFIG_SENSORS_LTC2978_REGULATOR=y
CONFIG_SENSORS_LTC3815=m
CONFIG_SENSORS_MAX15301=m
CONFIG_SENSORS_MAX16064=m
CONFIG_SENSORS_MAX16601=m
CONFIG_SENSORS_MAX20730=m
CONFIG_SENSORS_MAX20751=m
CONFIG_SENSORS_MAX31785=m
CONFIG_SENSORS_MAX34440=m
CONFIG_SENSORS_MAX8688=m
CONFIG_SENSORS_MP2888=m
CONFIG_SENSORS_MP2975=m
CONFIG_SENSORS_MP5023=m
CONFIG_SENSORS_PIM4328=m
CONFIG_SENSORS_PLI1209BC=m
CONFIG_SENSORS_PLI1209BC_REGULATOR=y
CONFIG_SENSORS_PM6764TR=m
CONFIG_SENSORS_PXE1610=m
CONFIG_SENSORS_Q54SJ108A2=m
CONFIG_SENSORS_STPDDC60=m
CONFIG_SENSORS_TPS40422=m
CONFIG_SENSORS_TPS53679=m
CONFIG_SENSORS_TPS546D24=m
CONFIG_SENSORS_UCD9000=m
CONFIG_SENSORS_UCD9200=m
CONFIG_SENSORS_XDPE152=m
CONFIG_SENSORS_XDPE122=m
CONFIG_SENSORS_XDPE122_REGULATOR=y
CONFIG_SENSORS_ZL6100=m
CONFIG_SENSORS_PWM_FAN=m
CONFIG_SENSORS_RASPBERRYPI_HWMON=m
CONFIG_SENSORS_SL28CPLD=m
CONFIG_SENSORS_SBTSI=m
CONFIG_SENSORS_SBRMI=m
CONFIG_SENSORS_SHT15=m
CONFIG_SENSORS_SHT21=m
CONFIG_SENSORS_SHT3x=m
CONFIG_SENSORS_SHT4x=m
CONFIG_SENSORS_SHTC1=m
CONFIG_SENSORS_SY7636A=m
CONFIG_SENSORS_DME1737=m
CONFIG_SENSORS_EMC1403=m
CONFIG_SENSORS_EMC2103=m
CONFIG_SENSORS_EMC2305=m
CONFIG_SENSORS_EMC6W201=m
CONFIG_SENSORS_SMSC47M1=m
CONFIG_SENSORS_SMSC47M192=m
CONFIG_SENSORS_SMSC47B397=m
CONFIG_SENSORS_SCH56XX_COMMON=m
CONFIG_SENSORS_SCH5627=m
CONFIG_SENSORS_SCH5636=m
CONFIG_SENSORS_STTS751=m
CONFIG_SENSORS_SMM665=m
CONFIG_SENSORS_ADC128D818=m
CONFIG_SENSORS_ADS7828=m
CONFIG_SENSORS_ADS7871=m
CONFIG_SENSORS_AMC6821=m
CONFIG_SENSORS_INA209=m
CONFIG_SENSORS_INA2XX=m
CONFIG_SENSORS_INA238=m
CONFIG_SENSORS_INA3221=m
CONFIG_SENSORS_TC74=m
CONFIG_SENSORS_THMC50=m
CONFIG_SENSORS_TMP102=m
CONFIG_SENSORS_TMP103=m
CONFIG_SENSORS_TMP108=m
CONFIG_SENSORS_TMP401=m
CONFIG_SENSORS_TMP421=m
CONFIG_SENSORS_TMP464=m
CONFIG_SENSORS_TMP513=m
CONFIG_SENSORS_VT1211=m
CONFIG_SENSORS_W83773G=m
CONFIG_SENSORS_W83781D=m
CONFIG_SENSORS_W83791D=m
CONFIG_SENSORS_W83792D=m
CONFIG_SENSORS_W83793=m
CONFIG_SENSORS_W83795=m
CONFIG_SENSORS_W83795_FANCTRL=y
CONFIG_SENSORS_W83L785TS=m
CONFIG_SENSORS_W83L786NG=m
CONFIG_SENSORS_W83627HF=m
CONFIG_SENSORS_W83627EHF=m
CONFIG_SENSORS_WM831X=m
CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m
CONFIG_THERMAL=y
CONFIG_THERMAL_NETLINK=y
CONFIG_THERMAL_STATISTICS=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_BANG_BANG=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_CPU_IDLE_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_THERMAL_EMULATION=y
CONFIG_THERMAL_MMIO=m
CONFIG_HISI_THERMAL=m
CONFIG_IMX_THERMAL=m
CONFIG_IMX_SC_THERMAL=m
CONFIG_IMX8MM_THERMAL=m
CONFIG_K3_THERMAL=m
CONFIG_QORIQ_THERMAL=m
CONFIG_SPEAR_THERMAL=m
CONFIG_SUN8I_THERMAL=m
CONFIG_ROCKCHIP_THERMAL=m
CONFIG_RCAR_THERMAL=m
CONFIG_RCAR_GEN3_THERMAL=m
CONFIG_RZG2L_THERMAL=m
CONFIG_KIRKWOOD_THERMAL=m
CONFIG_DOVE_THERMAL=m
CONFIG_ARMADA_THERMAL=m
CONFIG_DA9062_THERMAL=m
CONFIG_MTK_THERMAL=m

#
# Intel thermal drivers
#

#
# ACPI INT340X thermal drivers
#
# end of ACPI INT340X thermal drivers
# end of Intel thermal drivers

#
# Broadcom thermal drivers
#
CONFIG_BCM2711_THERMAL=m
CONFIG_BCM2835_THERMAL=m
CONFIG_BRCMSTB_THERMAL=m
CONFIG_BCM_NS_THERMAL=m
CONFIG_BCM_SR_THERMAL=m
# end of Broadcom thermal drivers

#
# Texas Instruments thermal drivers
#
CONFIG_TI_SOC_THERMAL=m
CONFIG_TI_THERMAL=y
CONFIG_OMAP3_THERMAL=y
CONFIG_OMAP4_THERMAL=y
CONFIG_OMAP5_THERMAL=y
CONFIG_DRA752_THERMAL=y
# end of Texas Instruments thermal drivers

#
# Samsung thermal drivers
#
CONFIG_EXYNOS_THERMAL=m
# end of Samsung thermal drivers

#
# NVIDIA Tegra thermal drivers
#
CONFIG_TEGRA_SOCTHERM=m
CONFIG_TEGRA_BPMP_THERMAL=m
CONFIG_TEGRA30_TSENSOR=m
# end of NVIDIA Tegra thermal drivers

CONFIG_GENERIC_ADC_THERMAL=m

#
# Qualcomm thermal drivers
#
CONFIG_QCOM_TSENS=m
CONFIG_QCOM_SPMI_ADC_TM5=m
CONFIG_QCOM_SPMI_TEMP_ALARM=m
# end of Qualcomm thermal drivers

CONFIG_UNIPHIER_THERMAL=m
CONFIG_SPRD_THERMAL=m
CONFIG_KHADAS_MCU_FAN_THERMAL=m
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
CONFIG_WATCHDOG_SYSFS=y
CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT=y

#
# Watchdog Pretimeout Governors
#
CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=m
CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=m
# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y

#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=m
CONFIG_SOFT_WATCHDOG_PRETIMEOUT=y
CONFIG_DA9052_WATCHDOG=m
CONFIG_DA9055_WATCHDOG=m
CONFIG_DA9063_WATCHDOG=m
CONFIG_DA9062_WATCHDOG=m
CONFIG_GPIO_WATCHDOG=m
CONFIG_MENF21BMC_WATCHDOG=m
CONFIG_MENZ069_WATCHDOG=m
CONFIG_WM831X_WATCHDOG=m
CONFIG_XILINX_WATCHDOG=m
CONFIG_ZIIRAVE_WATCHDOG=m
CONFIG_RAVE_SP_WATCHDOG=m
CONFIG_MLX_WDT=m
CONFIG_SL28CPLD_WATCHDOG=m
CONFIG_ARMADA_37XX_WATCHDOG=m
CONFIG_ASM9260_WATCHDOG=m
CONFIG_AT91RM9200_WATCHDOG=m
CONFIG_AT91SAM9X_WATCHDOG=m
CONFIG_SAMA5D4_WATCHDOG=m
CONFIG_CADENCE_WATCHDOG=m
CONFIG_FTWDT010_WATCHDOG=m
CONFIG_S3C2410_WATCHDOG=m
CONFIG_DW_WATCHDOG=m
CONFIG_EP93XX_WATCHDOG=m
CONFIG_OMAP_WATCHDOG=m
CONFIG_PNX4008_WATCHDOG=m
CONFIG_DAVINCI_WATCHDOG=m
CONFIG_K3_RTI_WATCHDOG=m
CONFIG_RN5T618_WATCHDOG=m
CONFIG_SUNXI_WATCHDOG=m
CONFIG_NPCM7XX_WATCHDOG=m
CONFIG_STMP3XXX_RTC_WATCHDOG=m
CONFIG_TS4800_WATCHDOG=m
CONFIG_TS72XX_WATCHDOG=m
CONFIG_MAX63XX_WATCHDOG=m
CONFIG_MAX77620_WATCHDOG=m
CONFIG_IMX2_WDT=m
CONFIG_IMX7ULP_WDT=m
CONFIG_RETU_WATCHDOG=m
CONFIG_MOXART_WDT=m
CONFIG_ST_LPC_WATCHDOG=m
CONFIG_TEGRA_WATCHDOG=m
CONFIG_QCOM_WDT=m
CONFIG_MESON_GXBB_WATCHDOG=m
CONFIG_MESON_WATCHDOG=m
CONFIG_MEDIATEK_WATCHDOG=m
CONFIG_DIGICOLOR_WATCHDOG=m
CONFIG_LPC18XX_WATCHDOG=m
CONFIG_RENESAS_WDT=m
CONFIG_RENESAS_RZAWDT=m
CONFIG_RENESAS_RZN1WDT=m
CONFIG_RENESAS_RZG2LWDT=m
CONFIG_ASPEED_WATCHDOG=m
CONFIG_UNIPHIER_WATCHDOG=m
CONFIG_RTD119X_WATCHDOG=y
CONFIG_SPRD_WATCHDOG=m
CONFIG_PM8916_WATCHDOG=m
CONFIG_VISCONTI_WATCHDOG=m
CONFIG_MSC313E_WATCHDOG=m
CONFIG_APPLE_WATCHDOG=m
CONFIG_SUNPLUS_WATCHDOG=m
CONFIG_SC520_WDT=m
CONFIG_KEMPLD_WDT=m
CONFIG_BCM47XX_WDT=m
CONFIG_BCM2835_WDT=m
CONFIG_BCM_KONA_WDT=m
CONFIG_BCM_KONA_WDT_DEBUG=y
CONFIG_BCM7038_WDT=m
CONFIG_IMGPDC_WDT=m
CONFIG_MPC5200_WDT=y
CONFIG_MEN_A21_WDT=m
CONFIG_SH_WDT=m
CONFIG_UML_WATCHDOG=m

#
# USB-based Watchdog Cards
#
CONFIG_USBPCWATCHDOG=m

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
CONFIG_MFD_ACT8945A=m
CONFIG_MFD_SUN4I_GPADC=m
CONFIG_MFD_AT91_USART=m
CONFIG_MFD_ATMEL_FLEXCOM=m
CONFIG_MFD_ATMEL_HLCDC=m
CONFIG_MFD_ATMEL_SMC=y
CONFIG_MFD_BCM590XX=m
CONFIG_MFD_BD9571MWV=m
CONFIG_MFD_AXP20X=m
CONFIG_MFD_AXP20X_I2C=m
CONFIG_MFD_CROS_EC_DEV=m
CONFIG_MFD_MADERA=m
CONFIG_MFD_MADERA_I2C=m
CONFIG_MFD_MADERA_SPI=m
CONFIG_MFD_CS47L15=y
CONFIG_MFD_CS47L35=y
CONFIG_MFD_CS47L85=y
CONFIG_MFD_CS47L90=y
CONFIG_MFD_CS47L92=y
CONFIG_MFD_ASIC3=y
CONFIG_PMIC_DA9052=y
CONFIG_MFD_DA9052_SPI=y
CONFIG_MFD_DA9062=m
CONFIG_MFD_DA9063=m
CONFIG_MFD_DA9150=m
CONFIG_MFD_DLN2=m
CONFIG_MFD_ENE_KB3930=m
CONFIG_MFD_EXYNOS_LPASS=m
CONFIG_MFD_GATEWORKS_GSC=m
CONFIG_MFD_MC13XXX=m
CONFIG_MFD_MC13XXX_SPI=m
CONFIG_MFD_MC13XXX_I2C=m
CONFIG_MFD_MP2629=m
CONFIG_MFD_MXS_LRADC=m
CONFIG_MFD_MX25_TSADC=m
CONFIG_MFD_HI6421_PMIC=m
CONFIG_MFD_HI6421_SPMI=m
CONFIG_MFD_HI655X_PMIC=m
CONFIG_HTC_PASIC3=m
CONFIG_MFD_IQS62X=m
CONFIG_MFD_KEMPLD=m
CONFIG_MFD_88PM800=m
CONFIG_MFD_88PM805=m
CONFIG_MFD_MAX14577=m
CONFIG_MFD_MAX77650=m
CONFIG_MFD_MAX77686=m
CONFIG_MFD_MAX77693=m
CONFIG_MFD_MAX77714=m
CONFIG_MFD_MAX8907=m
CONFIG_MFD_MT6360=m
CONFIG_MFD_MT6370=m
CONFIG_MFD_MT6397=m
CONFIG_MFD_MENF21BMC=m
CONFIG_MFD_OCELOT=m
CONFIG_EZX_PCAP=y
CONFIG_MFD_CPCAP=m
CONFIG_MFD_VIPERBOARD=m
CONFIG_MFD_NTXEC=m
CONFIG_MFD_RETU=m
CONFIG_MFD_PCF50633=m
CONFIG_PCF50633_ADC=m
CONFIG_PCF50633_GPIO=m
CONFIG_UCB1400_CORE=m
CONFIG_MFD_PM8XXX=m
CONFIG_MFD_SPMI_PMIC=m
CONFIG_MFD_SY7636A=m
CONFIG_MFD_RT4831=m
CONFIG_MFD_RT5033=m
CONFIG_MFD_RT5120=m
CONFIG_MFD_RK808=m
CONFIG_MFD_RN5T618=m
CONFIG_MFD_SI476X_CORE=m
CONFIG_MFD_SIMPLE_MFD_I2C=m
CONFIG_MFD_SL28CPLD=m
CONFIG_MFD_SKY81452=m
CONFIG_MFD_SC27XX_PMIC=m
CONFIG_ABX500_CORE=y
CONFIG_MFD_STMPE=y

#
# STMicroelectronics STMPE Interface Drivers
#
CONFIG_STMPE_SPI=y
# end of STMicroelectronics STMPE Interface Drivers

CONFIG_MFD_SUN6I_PRCM=y
CONFIG_MFD_SYSCON=y
CONFIG_MFD_TI_AM335X_TSCADC=m
CONFIG_MFD_LP3943=m
CONFIG_MFD_TI_LMU=m
CONFIG_TPS6105X=m
CONFIG_TPS65010=m
CONFIG_TPS6507X=m
CONFIG_MFD_TPS65086=m
CONFIG_MFD_TPS65217=m
CONFIG_MFD_TI_LP873X=m
CONFIG_MFD_TI_LP87565=m
CONFIG_MFD_TPS65218=m
CONFIG_MFD_TPS65912=m
CONFIG_MFD_TPS65912_I2C=m
CONFIG_MFD_TPS65912_SPI=m
CONFIG_MFD_WL1273_CORE=m
CONFIG_MFD_LM3533=m
CONFIG_MFD_TQMX86=m
CONFIG_MFD_ARIZONA=m
CONFIG_MFD_ARIZONA_I2C=m
CONFIG_MFD_ARIZONA_SPI=m
CONFIG_MFD_CS47L24=y
CONFIG_MFD_WM5102=y
CONFIG_MFD_WM5110=y
CONFIG_MFD_WM8997=y
CONFIG_MFD_WM8998=y
CONFIG_MFD_WM831X=y
CONFIG_MFD_WM831X_SPI=y
CONFIG_MFD_WM8994=m
CONFIG_MFD_STW481X=m
CONFIG_MFD_STM32_LPTIMER=m
CONFIG_MFD_STM32_TIMERS=m
CONFIG_MFD_STMFX=m
CONFIG_MFD_WCD934X=m
CONFIG_MFD_ATC260X=m
CONFIG_MFD_ATC260X_I2C=m
CONFIG_MFD_KHADAS_MCU=m
CONFIG_MFD_ACER_A500_EC=m
CONFIG_MFD_QCOM_PM8008=m
CONFIG_RAVE_SP_CORE=m
CONFIG_MFD_INTEL_M10_BMC=m
CONFIG_MFD_RSMU_I2C=m
CONFIG_MFD_RSMU_SPI=m
# end of Multifunction device drivers

CONFIG_REGULATOR=y
CONFIG_REGULATOR_DEBUG=y
CONFIG_REGULATOR_FIXED_VOLTAGE=m
CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
CONFIG_REGULATOR_USERSPACE_CONSUMER=m
CONFIG_REGULATOR_88PG86X=m
CONFIG_REGULATOR_88PM800=m
CONFIG_REGULATOR_ACT8865=m
CONFIG_REGULATOR_ACT8945A=m
CONFIG_REGULATOR_AD5398=m
CONFIG_REGULATOR_ANATOP=m
CONFIG_REGULATOR_ARIZONA_LDO1=m
CONFIG_REGULATOR_ARIZONA_MICSUPP=m
CONFIG_REGULATOR_ARM_SCMI=m
CONFIG_REGULATOR_ATC260X=m
CONFIG_REGULATOR_AXP20X=m
CONFIG_REGULATOR_BCM590XX=m
CONFIG_REGULATOR_BD9571MWV=m
CONFIG_REGULATOR_CPCAP=m
CONFIG_REGULATOR_CROS_EC=m
CONFIG_REGULATOR_DA9052=m
CONFIG_REGULATOR_DA9062=m
CONFIG_REGULATOR_DA9063=m
CONFIG_REGULATOR_DA9121=m
CONFIG_REGULATOR_DA9210=m
CONFIG_REGULATOR_DA9211=m
CONFIG_REGULATOR_FAN53555=m
CONFIG_REGULATOR_FAN53880=m
CONFIG_REGULATOR_GPIO=m
CONFIG_REGULATOR_HI6421=m
CONFIG_REGULATOR_HI6421V530=m
CONFIG_REGULATOR_HI655X=m
CONFIG_REGULATOR_HI6421V600=m
CONFIG_REGULATOR_ISL9305=m
CONFIG_REGULATOR_ISL6271A=m
CONFIG_REGULATOR_LM363X=m
CONFIG_REGULATOR_LP3971=m
CONFIG_REGULATOR_LP3972=m
CONFIG_REGULATOR_LP872X=m
CONFIG_REGULATOR_LP873X=m
CONFIG_REGULATOR_LP8755=m
CONFIG_REGULATOR_LP87565=m
CONFIG_REGULATOR_LTC3589=m
CONFIG_REGULATOR_LTC3676=m
CONFIG_REGULATOR_MAX14577=m
CONFIG_REGULATOR_MAX1586=m
CONFIG_REGULATOR_MAX77620=m
CONFIG_REGULATOR_MAX77650=m
CONFIG_REGULATOR_MAX8649=m
CONFIG_REGULATOR_MAX8660=m
CONFIG_REGULATOR_MAX8893=m
CONFIG_REGULATOR_MAX8907=m
CONFIG_REGULATOR_MAX8952=m
CONFIG_REGULATOR_MAX8973=m
CONFIG_REGULATOR_MAX20086=m
CONFIG_REGULATOR_MAX77686=m
CONFIG_REGULATOR_MAX77693=m
CONFIG_REGULATOR_MAX77802=m
CONFIG_REGULATOR_MAX77826=m
CONFIG_REGULATOR_MC13XXX_CORE=m
CONFIG_REGULATOR_MC13783=m
CONFIG_REGULATOR_MC13892=m
CONFIG_REGULATOR_MCP16502=m
CONFIG_REGULATOR_MP5416=m
CONFIG_REGULATOR_MP8859=m
CONFIG_REGULATOR_MP886X=m
CONFIG_REGULATOR_MPQ7920=m
CONFIG_REGULATOR_MT6311=m
CONFIG_REGULATOR_MT6315=m
CONFIG_REGULATOR_MT6323=m
CONFIG_REGULATOR_MT6331=m
CONFIG_REGULATOR_MT6332=m
CONFIG_REGULATOR_MT6358=m
CONFIG_REGULATOR_MT6359=m
CONFIG_REGULATOR_MT6360=m
CONFIG_REGULATOR_MT6370=m
CONFIG_REGULATOR_MT6380=m
CONFIG_REGULATOR_MT6397=m
CONFIG_REGULATOR_PBIAS=m
CONFIG_REGULATOR_PCA9450=m
CONFIG_REGULATOR_PCAP=m
CONFIG_REGULATOR_PCF50633=m
CONFIG_REGULATOR_PF8X00=m
CONFIG_REGULATOR_PFUZE100=m
CONFIG_REGULATOR_PV88060=m
CONFIG_REGULATOR_PV88080=m
CONFIG_REGULATOR_PV88090=m
CONFIG_REGULATOR_PWM=m
CONFIG_REGULATOR_QCOM_RPMH=m
CONFIG_REGULATOR_QCOM_SMD_RPM=m
CONFIG_REGULATOR_QCOM_SPMI=m
CONFIG_REGULATOR_QCOM_USB_VBUS=m
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
CONFIG_REGULATOR_RK808=m
CONFIG_REGULATOR_RN5T618=m
CONFIG_REGULATOR_RT4801=m
CONFIG_REGULATOR_RT4831=m
CONFIG_REGULATOR_RT5033=m
CONFIG_REGULATOR_RT5120=m
CONFIG_REGULATOR_RT5190A=m
CONFIG_REGULATOR_RT5759=m
CONFIG_REGULATOR_RT6160=m
CONFIG_REGULATOR_RT6245=m
CONFIG_REGULATOR_RTQ2134=m
CONFIG_REGULATOR_RTMV20=m
CONFIG_REGULATOR_RTQ6752=m
CONFIG_REGULATOR_S2MPA01=m
CONFIG_REGULATOR_S2MPS11=m
CONFIG_REGULATOR_S5M8767=m
CONFIG_REGULATOR_SC2731=m
CONFIG_REGULATOR_SKY81452=m
CONFIG_REGULATOR_SLG51000=m
CONFIG_REGULATOR_STM32_BOOSTER=m
CONFIG_REGULATOR_STM32_VREFBUF=m
CONFIG_REGULATOR_STM32_PWR=y
CONFIG_REGULATOR_TI_ABB=m
CONFIG_REGULATOR_STW481X_VMMC=y
CONFIG_REGULATOR_SY7636A=m
CONFIG_REGULATOR_SY8106A=m
CONFIG_REGULATOR_SY8824X=m
CONFIG_REGULATOR_SY8827N=m
CONFIG_REGULATOR_TPS51632=m
CONFIG_REGULATOR_TPS6105X=m
CONFIG_REGULATOR_TPS62360=m
CONFIG_REGULATOR_TPS6286X=m
CONFIG_REGULATOR_TPS65023=m
CONFIG_REGULATOR_TPS6507X=m
CONFIG_REGULATOR_TPS65086=m
CONFIG_REGULATOR_TPS65132=m
CONFIG_REGULATOR_TPS65217=m
CONFIG_REGULATOR_TPS65218=m
CONFIG_REGULATOR_TPS6524X=m
CONFIG_REGULATOR_TPS65912=m
CONFIG_REGULATOR_TPS68470=m
CONFIG_REGULATOR_UNIPHIER=m
CONFIG_REGULATOR_VCTRL=m
CONFIG_REGULATOR_WM831X=m
CONFIG_REGULATOR_WM8994=m
CONFIG_REGULATOR_QCOM_LABIBB=m
CONFIG_RC_CORE=m
CONFIG_LIRC=y
CONFIG_RC_MAP=m
CONFIG_RC_DECODERS=y
CONFIG_IR_IMON_DECODER=m
CONFIG_IR_JVC_DECODER=m
CONFIG_IR_MCE_KBD_DECODER=m
CONFIG_IR_NEC_DECODER=m
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
CONFIG_IR_RCMM_DECODER=m
CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SHARP_DECODER=m
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_XMP_DECODER=m
CONFIG_RC_DEVICES=y
CONFIG_IR_ENE=m
CONFIG_IR_FINTEK=m
CONFIG_IR_GPIO_CIR=m
CONFIG_IR_GPIO_TX=m
CONFIG_IR_HIX5HD2=m
CONFIG_IR_IGORPLUGUSB=m
CONFIG_IR_IGUANA=m
CONFIG_IR_IMON=m
CONFIG_IR_IMON_RAW=m
CONFIG_IR_ITE_CIR=m
CONFIG_IR_MCEUSB=m
CONFIG_IR_MESON=m
CONFIG_IR_MESON_TX=m
CONFIG_IR_MTK=m
CONFIG_IR_NUVOTON=m
CONFIG_IR_PWM_TX=m
CONFIG_IR_REDRAT3=m
CONFIG_IR_RX51=m
CONFIG_IR_SERIAL=m
CONFIG_IR_SERIAL_TRANSMITTER=y
CONFIG_IR_SPI=m
CONFIG_IR_STREAMZAP=m
CONFIG_IR_SUNXI=m
CONFIG_IR_TOY=m
CONFIG_IR_TTUSBIR=m
CONFIG_IR_WINBOND_CIR=m
CONFIG_RC_ATI_REMOTE=m
CONFIG_RC_LOOPBACK=m
CONFIG_RC_ST=m
CONFIG_RC_XBOX_DVD=m
CONFIG_IR_IMG=m
CONFIG_IR_IMG_RAW=y
CONFIG_IR_IMG_HW=y
CONFIG_IR_IMG_NEC=y
CONFIG_IR_IMG_JVC=y
CONFIG_IR_IMG_SONY=y
CONFIG_IR_IMG_SHARP=y
CONFIG_IR_IMG_SANYO=y
CONFIG_IR_IMG_RC5=y
CONFIG_IR_IMG_RC6=y
CONFIG_CEC_CORE=m
CONFIG_CEC_NOTIFIER=y
CONFIG_CEC_PIN=y

#
# CEC support
#
CONFIG_MEDIA_CEC_RC=y
CONFIG_CEC_PIN_ERROR_INJ=y
CONFIG_MEDIA_CEC_SUPPORT=y
CONFIG_CEC_CH7322=m
CONFIG_CEC_CROS_EC=m
CONFIG_CEC_MESON_AO=m
CONFIG_CEC_GPIO=m
CONFIG_CEC_SAMSUNG_S5P=m
CONFIG_CEC_STI=m
CONFIG_CEC_STM32=m
CONFIG_CEC_TEGRA=m
CONFIG_USB_PULSE8_CEC=m
CONFIG_USB_RAINSHADOW_CEC=m
# end of CEC support

CONFIG_MEDIA_SUPPORT=m
CONFIG_MEDIA_SUPPORT_FILTER=y
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y

#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
CONFIG_MEDIA_RADIO_SUPPORT=y
CONFIG_MEDIA_SDR_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_MEDIA_TEST_SUPPORT=y
# end of Media device types

CONFIG_VIDEO_DEV=m
CONFIG_MEDIA_CONTROLLER=y
CONFIG_DVB_CORE=m

#
# Video4Linux options
#
CONFIG_VIDEO_V4L2_I2C=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEO_ADV_DEBUG=y
CONFIG_VIDEO_FIXED_MINOR_RANGES=y
CONFIG_VIDEO_TUNER=m
CONFIG_V4L2_JPEG_HELPER=m
CONFIG_V4L2_H264=m
CONFIG_V4L2_VP9=m
CONFIG_V4L2_MEM2MEM_DEV=m
CONFIG_V4L2_FLASH_LED_CLASS=m
CONFIG_V4L2_FWNODE=m
CONFIG_V4L2_ASYNC=m
CONFIG_VIDEOBUF_GEN=m
CONFIG_VIDEOBUF_VMALLOC=m
CONFIG_VIDEOBUF_DMA_CONTIG=m
# end of Video4Linux options

#
# Media controller options
#
CONFIG_MEDIA_CONTROLLER_DVB=y
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
# end of Media controller options

#
# Digital TV options
#
CONFIG_DVB_MMAP=y
CONFIG_DVB_NET=y
CONFIG_DVB_MAX_ADAPTERS=16
CONFIG_DVB_DYNAMIC_MINORS=y
CONFIG_DVB_DEMUX_SECTION_LOSS_LOG=y
CONFIG_DVB_ULE_DEBUG=y
# end of Digital TV options

#
# Media drivers
#

#
# Drivers filtered as selected at 'Filter media drivers'
#

#
# Media drivers
#
CONFIG_MEDIA_USB_SUPPORT=y

#
# Webcam devices
#
CONFIG_USB_GSPCA=m
CONFIG_USB_GSPCA_BENQ=m
CONFIG_USB_GSPCA_CONEX=m
CONFIG_USB_GSPCA_CPIA1=m
CONFIG_USB_GSPCA_DTCS033=m
CONFIG_USB_GSPCA_ETOMS=m
CONFIG_USB_GSPCA_FINEPIX=m
CONFIG_USB_GSPCA_JEILINJ=m
CONFIG_USB_GSPCA_JL2005BCD=m
CONFIG_USB_GSPCA_KINECT=m
CONFIG_USB_GSPCA_KONICA=m
CONFIG_USB_GSPCA_MARS=m
CONFIG_USB_GSPCA_MR97310A=m
CONFIG_USB_GSPCA_NW80X=m
CONFIG_USB_GSPCA_OV519=m
CONFIG_USB_GSPCA_OV534=m
CONFIG_USB_GSPCA_OV534_9=m
CONFIG_USB_GSPCA_PAC207=m
CONFIG_USB_GSPCA_PAC7302=m
CONFIG_USB_GSPCA_PAC7311=m
CONFIG_USB_GSPCA_SE401=m
CONFIG_USB_GSPCA_SN9C2028=m
CONFIG_USB_GSPCA_SN9C20X=m
CONFIG_USB_GSPCA_SONIXB=m
CONFIG_USB_GSPCA_SONIXJ=m
CONFIG_USB_GSPCA_SPCA1528=m
CONFIG_USB_GSPCA_SPCA500=m
CONFIG_USB_GSPCA_SPCA501=m
CONFIG_USB_GSPCA_SPCA505=m
CONFIG_USB_GSPCA_SPCA506=m
CONFIG_USB_GSPCA_SPCA508=m
CONFIG_USB_GSPCA_SPCA561=m
CONFIG_USB_GSPCA_SQ905=m
CONFIG_USB_GSPCA_SQ905C=m
CONFIG_USB_GSPCA_SQ930X=m
CONFIG_USB_GSPCA_STK014=m
CONFIG_USB_GSPCA_STK1135=m
CONFIG_USB_GSPCA_STV0680=m
CONFIG_USB_GSPCA_SUNPLUS=m
CONFIG_USB_GSPCA_T613=m
CONFIG_USB_GSPCA_TOPRO=m
CONFIG_USB_GSPCA_TOUPTEK=m
CONFIG_USB_GSPCA_TV8532=m
CONFIG_USB_GSPCA_VC032X=m
CONFIG_USB_GSPCA_VICAM=m
CONFIG_USB_GSPCA_XIRLINK_CIT=m
CONFIG_USB_GSPCA_ZC3XX=m
CONFIG_USB_GL860=m
CONFIG_USB_M5602=m
CONFIG_USB_STV06XX=m
CONFIG_USB_PWC=m
CONFIG_USB_PWC_DEBUG=y
CONFIG_USB_PWC_INPUT_EVDEV=y
CONFIG_USB_S2255=m
CONFIG_VIDEO_USBTV=m
CONFIG_USB_VIDEO_CLASS=m
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y

#
# Analog TV USB devices
#
CONFIG_VIDEO_GO7007=m
CONFIG_VIDEO_GO7007_USB=m
CONFIG_VIDEO_GO7007_LOADER=m
CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
CONFIG_VIDEO_HDPVR=m
CONFIG_VIDEO_PVRUSB2=m
CONFIG_VIDEO_PVRUSB2_SYSFS=y
CONFIG_VIDEO_PVRUSB2_DVB=y
CONFIG_VIDEO_PVRUSB2_DEBUGIFC=y
CONFIG_VIDEO_STK1160_COMMON=m
CONFIG_VIDEO_STK1160=m

#
# Analog/digital TV USB devices
#
CONFIG_VIDEO_AU0828=m
CONFIG_VIDEO_AU0828_V4L2=y
CONFIG_VIDEO_AU0828_RC=y
CONFIG_VIDEO_CX231XX=m
CONFIG_VIDEO_CX231XX_RC=y
CONFIG_VIDEO_CX231XX_ALSA=m
CONFIG_VIDEO_CX231XX_DVB=m

#
# Digital TV USB devices
#
CONFIG_DVB_AS102=m
CONFIG_DVB_B2C2_FLEXCOP_USB=m
CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG=y
CONFIG_DVB_USB_V2=m
CONFIG_DVB_USB_AF9015=m
CONFIG_DVB_USB_AF9035=m
CONFIG_DVB_USB_ANYSEE=m
CONFIG_DVB_USB_AU6610=m
CONFIG_DVB_USB_AZ6007=m
CONFIG_DVB_USB_CE6230=m
CONFIG_DVB_USB_DVBSKY=m
CONFIG_DVB_USB_EC168=m
CONFIG_DVB_USB_GL861=m
CONFIG_DVB_USB_LME2510=m
CONFIG_DVB_USB_MXL111SF=m
CONFIG_DVB_USB_RTL28XXU=m
CONFIG_DVB_USB_ZD1301=m
CONFIG_DVB_USB=m
CONFIG_DVB_USB_DEBUG=y
CONFIG_DVB_USB_A800=m
CONFIG_DVB_USB_AF9005=m
CONFIG_DVB_USB_AF9005_REMOTE=m
CONFIG_DVB_USB_AZ6027=m
CONFIG_DVB_USB_CINERGY_T2=m
CONFIG_DVB_USB_CXUSB=m
CONFIG_DVB_USB_CXUSB_ANALOG=y
CONFIG_DVB_USB_DIB0700=m
CONFIG_DVB_USB_DIB3000MC=m
CONFIG_DVB_USB_DIBUSB_MB=m
CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
CONFIG_DVB_USB_DIBUSB_MC=m
CONFIG_DVB_USB_DIGITV=m
CONFIG_DVB_USB_DTT200U=m
CONFIG_DVB_USB_DTV5100=m
CONFIG_DVB_USB_DW2102=m
CONFIG_DVB_USB_GP8PSK=m
CONFIG_DVB_USB_M920X=m
CONFIG_DVB_USB_NOVA_T_USB2=m
CONFIG_DVB_USB_OPERA1=m
CONFIG_DVB_USB_PCTV452E=m
CONFIG_DVB_USB_TECHNISAT_USB2=m
CONFIG_DVB_USB_TTUSB2=m
CONFIG_DVB_USB_UMT_010=m
CONFIG_DVB_USB_VP702X=m
CONFIG_DVB_USB_VP7045=m

#
# Webcam, TV (analog/digital) USB devices
#
CONFIG_VIDEO_EM28XX=m
CONFIG_VIDEO_EM28XX_V4L2=m
CONFIG_VIDEO_EM28XX_ALSA=m
CONFIG_VIDEO_EM28XX_DVB=m
CONFIG_VIDEO_EM28XX_RC=m

#
# Software defined radio USB devices
#
CONFIG_USB_AIRSPY=m
CONFIG_USB_HACKRF=m
CONFIG_USB_MSI2500=m
CONFIG_RADIO_ADAPTERS=m
CONFIG_RADIO_SAA7706H=m
CONFIG_RADIO_SHARK=m
CONFIG_RADIO_SHARK2=m
CONFIG_RADIO_SI4713=m
CONFIG_RADIO_SI476X=m
CONFIG_RADIO_TEA575X=m
CONFIG_RADIO_TEA5764=m
CONFIG_RADIO_TEF6862=m
CONFIG_RADIO_WL1273=m
CONFIG_USB_DSBR=m
CONFIG_USB_KEENE=m
CONFIG_USB_MA901=m
CONFIG_USB_MR800=m
CONFIG_USB_RAREMONO=m
CONFIG_RADIO_SI470X=m
CONFIG_USB_SI470X=m
CONFIG_I2C_SI470X=m
CONFIG_USB_SI4713=m
CONFIG_PLATFORM_SI4713=m
CONFIG_I2C_SI4713=m
CONFIG_RADIO_WL128X=m
CONFIG_V4L_RADIO_ISA_DRIVERS=y
CONFIG_RADIO_AZTECH=m
CONFIG_RADIO_CADET=m
CONFIG_RADIO_GEMTEK=m
CONFIG_RADIO_ISA=m
CONFIG_RADIO_RTRACK=m
CONFIG_RADIO_RTRACK2=m
CONFIG_RADIO_SF16FMI=m
CONFIG_RADIO_SF16FMR2=m
CONFIG_RADIO_TERRATEC=m
CONFIG_RADIO_TRUST=m
CONFIG_RADIO_TYPHOON=m
CONFIG_RADIO_ZOLTRIX=m
CONFIG_MEDIA_PLATFORM_DRIVERS=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_SDR_PLATFORM_DRIVERS=y
CONFIG_DVB_PLATFORM_DRIVERS=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_MUX=m

#
# Allegro DVT media platform drivers
#
CONFIG_VIDEO_ALLEGRO_DVT=m

#
# Amlogic media platform drivers
#
CONFIG_VIDEO_MESON_GE2D=m

#
# Amphion drivers
#
CONFIG_VIDEO_AMPHION_VPU=m

#
# Aspeed media platform drivers
#
CONFIG_VIDEO_ASPEED=m

#
# Atmel media platform drivers
#
CONFIG_VIDEO_ATMEL_ISI=m

#
# Cadence media platform drivers
#
CONFIG_VIDEO_CADENCE_CSI2RX=m
CONFIG_VIDEO_CADENCE_CSI2TX=m

#
# Chips&Media media platform drivers
#
CONFIG_VIDEO_CODA=m
CONFIG_VIDEO_IMX_VDOA=m

#
# Intel media platform drivers
#
CONFIG_VIDEO_PXA27x=m

#
# Marvell media platform drivers
#

#
# Mediatek media platform drivers
#
CONFIG_VIDEO_MEDIATEK_JPEG=m
CONFIG_VIDEO_MEDIATEK_MDP=m
CONFIG_VIDEO_MEDIATEK_VCODEC_VPU=y
CONFIG_VIDEO_MEDIATEK_VCODEC=m
CONFIG_VIDEO_MEDIATEK_VPU=m

#
# NVidia media platform drivers
#
CONFIG_VIDEO_TEGRA_VDE=m

#
# NXP media platform drivers
#
CONFIG_VIDEO_IMX_MIPI_CSIS=m
CONFIG_VIDEO_IMX_PXP=m
CONFIG_VIDEO_MX2_EMMAPRP=m
CONFIG_VIDEO_DW100=m
CONFIG_VIDEO_IMX8_JPEG=m

#
# Qualcomm media platform drivers
#
CONFIG_VIDEO_QCOM_CAMSS=m
CONFIG_VIDEO_QCOM_VENUS=m

#
# Renesas media platform drivers
#
CONFIG_VIDEO_RENESAS_CEU=m
CONFIG_VIDEO_RCAR_ISP=m
CONFIG_VIDEO_SH_VOU=m
CONFIG_VIDEO_RCAR_CSI2=m
CONFIG_VIDEO_RCAR_VIN=m
CONFIG_VIDEO_RENESAS_FCP=m
CONFIG_VIDEO_RENESAS_FDP1=m
CONFIG_VIDEO_RENESAS_JPU=m
CONFIG_VIDEO_RENESAS_VSP1=m
CONFIG_VIDEO_RCAR_DRIF=m

#
# Rockchip media platform drivers
#
CONFIG_VIDEO_ROCKCHIP_RGA=m
CONFIG_VIDEO_ROCKCHIP_ISP1=m

#
# Samsung media platform drivers
#
CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
CONFIG_VIDEO_S3C_CAMIF=m
CONFIG_VIDEO_SAMSUNG_S5P_G2D=m
CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m
CONFIG_VIDEO_SAMSUNG_S5P_MFC=m

#
# STMicroelectronics media platform drivers
#
CONFIG_VIDEO_STI_BDISP=m
CONFIG_DVB_C8SECTPFE=m
CONFIG_VIDEO_STI_DELTA=m
CONFIG_VIDEO_STI_DELTA_MJPEG=y
CONFIG_VIDEO_STI_DELTA_DRIVER=m
CONFIG_VIDEO_STI_HVA=m
CONFIG_VIDEO_STI_HVA_DEBUGFS=y
CONFIG_VIDEO_STM32_DCMI=m
CONFIG_VIDEO_STM32_DMA2D=m

#
# Sunxi media platform drivers
#

#
# Texas Instruments drivers
#
CONFIG_VIDEO_TI_VPDMA=m
CONFIG_VIDEO_TI_SC=m
CONFIG_VIDEO_TI_CSC=m
CONFIG_VIDEO_TI_CAL=m
CONFIG_VIDEO_TI_CAL_MC=y
CONFIG_VIDEO_TI_VPE=m
CONFIG_VIDEO_TI_VPE_DEBUG=y
CONFIG_VIDEO_AM437X_VPFE=m
CONFIG_VIDEO_DAVINCI_VPIF_DISPLAY=m
CONFIG_VIDEO_DAVINCI_VPIF_CAPTURE=m
CONFIG_VIDEO_DAVINCI_VPBE_DISPLAY=m

#
# Verisilicon media platform drivers
#
CONFIG_VIDEO_HANTRO=m
CONFIG_VIDEO_HANTRO_IMX8M=y
CONFIG_VIDEO_HANTRO_SAMA5D4=y
CONFIG_VIDEO_HANTRO_ROCKCHIP=y
CONFIG_VIDEO_HANTRO_SUNXI=y

#
# VIA media platform drivers
#

#
# Xilinx media platform drivers
#
CONFIG_V4L_TEST_DRIVERS=y
CONFIG_VIDEO_VIM2M=m
CONFIG_VIDEO_VICODEC=m
CONFIG_VIDEO_VIMC=m
CONFIG_DVB_TEST_DRIVERS=y
CONFIG_DVB_VIDTV=m

#
# FireWire (IEEE 1394) Adapters
#
CONFIG_DVB_FIREDTV=m
CONFIG_DVB_FIREDTV_INPUT=y
CONFIG_CYPRESS_FIRMWARE=m
CONFIG_TTPCI_EEPROM=m
CONFIG_VIDEO_CX2341X=m
CONFIG_VIDEO_TVEEPROM=m
CONFIG_DVB_B2C2_FLEXCOP=m
CONFIG_DVB_B2C2_FLEXCOP_DEBUG=y
CONFIG_VIDEO_V4L2_TPG=m
CONFIG_VIDEOBUF2_CORE=m
CONFIG_VIDEOBUF2_V4L2=m
CONFIG_VIDEOBUF2_MEMOPS=m
CONFIG_VIDEOBUF2_DMA_CONTIG=m
CONFIG_VIDEOBUF2_VMALLOC=m
CONFIG_VIDEOBUF2_DMA_SG=m
# end of Media drivers

#
# Media ancillary drivers
#
CONFIG_MEDIA_ATTACH=y

#
# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
#
CONFIG_VIDEO_IR_I2C=m

#
# Camera sensor devices
#
CONFIG_VIDEO_APTINA_PLL=m
CONFIG_VIDEO_CCS_PLL=m
CONFIG_VIDEO_AR0521=m
CONFIG_VIDEO_HI556=m
CONFIG_VIDEO_HI846=m
CONFIG_VIDEO_HI847=m
CONFIG_VIDEO_IMX208=m
CONFIG_VIDEO_IMX214=m
CONFIG_VIDEO_IMX219=m
CONFIG_VIDEO_IMX258=m
CONFIG_VIDEO_IMX274=m
CONFIG_VIDEO_IMX290=m
CONFIG_VIDEO_IMX319=m
CONFIG_VIDEO_IMX334=m
CONFIG_VIDEO_IMX335=m
CONFIG_VIDEO_IMX355=m
CONFIG_VIDEO_IMX412=m
CONFIG_VIDEO_MAX9271_LIB=m
CONFIG_VIDEO_MT9M001=m
CONFIG_VIDEO_MT9M032=m
CONFIG_VIDEO_MT9M111=m
CONFIG_VIDEO_MT9P031=m
CONFIG_VIDEO_MT9T001=m
CONFIG_VIDEO_MT9T112=m
CONFIG_VIDEO_MT9V011=m
CONFIG_VIDEO_MT9V032=m
CONFIG_VIDEO_MT9V111=m
CONFIG_VIDEO_NOON010PC30=m
CONFIG_VIDEO_OG01A1B=m
CONFIG_VIDEO_OV02A10=m
CONFIG_VIDEO_OV08D10=m
CONFIG_VIDEO_OV13858=m
CONFIG_VIDEO_OV13B10=m
CONFIG_VIDEO_OV2640=m
CONFIG_VIDEO_OV2659=m
CONFIG_VIDEO_OV2680=m
CONFIG_VIDEO_OV2685=m
CONFIG_VIDEO_OV2740=m
CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
CONFIG_VIDEO_OV5647=m
CONFIG_VIDEO_OV5648=m
CONFIG_VIDEO_OV5670=m
CONFIG_VIDEO_OV5675=m
CONFIG_VIDEO_OV5693=m
CONFIG_VIDEO_OV5695=m
CONFIG_VIDEO_OV6650=m
CONFIG_VIDEO_OV7251=m
CONFIG_VIDEO_OV7640=m
CONFIG_VIDEO_OV7670=m
CONFIG_VIDEO_OV772X=m
CONFIG_VIDEO_OV7740=m
CONFIG_VIDEO_OV8856=m
CONFIG_VIDEO_OV8865=m
CONFIG_VIDEO_OV9282=m
CONFIG_VIDEO_OV9640=m
CONFIG_VIDEO_OV9650=m
CONFIG_VIDEO_OV9734=m
CONFIG_VIDEO_RDACM20=m
CONFIG_VIDEO_RDACM21=m
CONFIG_VIDEO_RJ54N1=m
CONFIG_VIDEO_S5C73M3=m
CONFIG_VIDEO_S5K4ECGX=m
CONFIG_VIDEO_S5K5BAF=m
CONFIG_VIDEO_S5K6A3=m
CONFIG_VIDEO_S5K6AA=m
CONFIG_VIDEO_SR030PC30=m
CONFIG_VIDEO_VS6624=m
CONFIG_VIDEO_CCS=m
CONFIG_VIDEO_ET8EK8=m
CONFIG_VIDEO_M5MOLS=m
# end of Camera sensor devices

#
# Lens drivers
#
CONFIG_VIDEO_AD5820=m
CONFIG_VIDEO_AK7375=m
CONFIG_VIDEO_DW9714=m
CONFIG_VIDEO_DW9768=m
CONFIG_VIDEO_DW9807_VCM=m
# end of Lens drivers

#
# Flash devices
#
CONFIG_VIDEO_ADP1653=m
CONFIG_VIDEO_LM3560=m
CONFIG_VIDEO_LM3646=m
# end of Flash devices

#
# Audio decoders, processors and mixers
#
CONFIG_VIDEO_CS3308=m
CONFIG_VIDEO_CS5345=m
CONFIG_VIDEO_CS53L32A=m
CONFIG_VIDEO_MSP3400=m
CONFIG_VIDEO_SONY_BTF_MPX=m
CONFIG_VIDEO_TDA1997X=m
CONFIG_VIDEO_TDA7432=m
CONFIG_VIDEO_TDA9840=m
CONFIG_VIDEO_TEA6415C=m
CONFIG_VIDEO_TEA6420=m
CONFIG_VIDEO_TLV320AIC23B=m
CONFIG_VIDEO_TVAUDIO=m
CONFIG_VIDEO_UDA1342=m
CONFIG_VIDEO_VP27SMPX=m
CONFIG_VIDEO_WM8739=m
CONFIG_VIDEO_WM8775=m
# end of Audio decoders, processors and mixers

#
# RDS decoders
#
CONFIG_VIDEO_SAA6588=m
# end of RDS decoders

#
# Video decoders
#
CONFIG_VIDEO_ADV7180=m
CONFIG_VIDEO_ADV7183=m
CONFIG_VIDEO_ADV748X=m
CONFIG_VIDEO_ADV7604=m
CONFIG_VIDEO_ADV7604_CEC=y
CONFIG_VIDEO_ADV7842=m
CONFIG_VIDEO_ADV7842_CEC=y
CONFIG_VIDEO_BT819=m
CONFIG_VIDEO_BT856=m
CONFIG_VIDEO_BT866=m
CONFIG_VIDEO_ISL7998X=m
CONFIG_VIDEO_KS0127=m
CONFIG_VIDEO_MAX9286=m
CONFIG_VIDEO_ML86V7667=m
CONFIG_VIDEO_SAA7110=m
CONFIG_VIDEO_SAA711X=m
CONFIG_VIDEO_TC358743=m
CONFIG_VIDEO_TC358743_CEC=y
CONFIG_VIDEO_TVP514X=m
CONFIG_VIDEO_TVP5150=m
CONFIG_VIDEO_TVP7002=m
CONFIG_VIDEO_TW2804=m
CONFIG_VIDEO_TW9903=m
CONFIG_VIDEO_TW9906=m
CONFIG_VIDEO_TW9910=m
CONFIG_VIDEO_VPX3220=m

#
# Video and audio decoders
#
CONFIG_VIDEO_SAA717X=m
CONFIG_VIDEO_CX25840=m
# end of Video decoders

#
# Video encoders
#
CONFIG_VIDEO_AD9389B=m
CONFIG_VIDEO_ADV7170=m
CONFIG_VIDEO_ADV7175=m
CONFIG_VIDEO_ADV7343=m
CONFIG_VIDEO_ADV7393=m
CONFIG_VIDEO_ADV7511=m
CONFIG_VIDEO_ADV7511_CEC=y
CONFIG_VIDEO_AK881X=m
CONFIG_VIDEO_SAA7127=m
CONFIG_VIDEO_SAA7185=m
CONFIG_VIDEO_THS8200=m
# end of Video encoders

#
# Video improvement chips
#
CONFIG_VIDEO_UPD64031A=m
CONFIG_VIDEO_UPD64083=m
# end of Video improvement chips

#
# Audio/Video compression chips
#
CONFIG_VIDEO_SAA6752HS=m
# end of Audio/Video compression chips

#
# SDR tuner chips
#
CONFIG_SDR_MAX2175=m
# end of SDR tuner chips

#
# Miscellaneous helper chips
#
CONFIG_VIDEO_I2C=m
CONFIG_VIDEO_M52790=m
CONFIG_VIDEO_ST_MIPID02=m
CONFIG_VIDEO_THS7303=m
# end of Miscellaneous helper chips

#
# Media SPI Adapters
#
CONFIG_CXD2880_SPI_DRV=m
CONFIG_VIDEO_GS1662=m
# end of Media SPI Adapters

CONFIG_MEDIA_TUNER=m

#
# Customize TV tuners
#
CONFIG_MEDIA_TUNER_E4000=m
CONFIG_MEDIA_TUNER_FC0011=m
CONFIG_MEDIA_TUNER_FC0012=m
CONFIG_MEDIA_TUNER_FC0013=m
CONFIG_MEDIA_TUNER_FC2580=m
CONFIG_MEDIA_TUNER_IT913X=m
CONFIG_MEDIA_TUNER_M88RS6000T=m
CONFIG_MEDIA_TUNER_MAX2165=m
CONFIG_MEDIA_TUNER_MC44S803=m
CONFIG_MEDIA_TUNER_MSI001=m
CONFIG_MEDIA_TUNER_MT2060=m
CONFIG_MEDIA_TUNER_MT2063=m
CONFIG_MEDIA_TUNER_MT20XX=m
CONFIG_MEDIA_TUNER_MT2131=m
CONFIG_MEDIA_TUNER_MT2266=m
CONFIG_MEDIA_TUNER_MXL301RF=m
CONFIG_MEDIA_TUNER_MXL5005S=m
CONFIG_MEDIA_TUNER_MXL5007T=m
CONFIG_MEDIA_TUNER_QM1D1B0004=m
CONFIG_MEDIA_TUNER_QM1D1C0042=m
CONFIG_MEDIA_TUNER_QT1010=m
CONFIG_MEDIA_TUNER_R820T=m
CONFIG_MEDIA_TUNER_SI2157=m
CONFIG_MEDIA_TUNER_SIMPLE=m
CONFIG_MEDIA_TUNER_TDA18212=m
CONFIG_MEDIA_TUNER_TDA18218=m
CONFIG_MEDIA_TUNER_TDA18250=m
CONFIG_MEDIA_TUNER_TDA18271=m
CONFIG_MEDIA_TUNER_TDA827X=m
CONFIG_MEDIA_TUNER_TDA8290=m
CONFIG_MEDIA_TUNER_TDA9887=m
CONFIG_MEDIA_TUNER_TEA5761=m
CONFIG_MEDIA_TUNER_TEA5767=m
CONFIG_MEDIA_TUNER_TUA9001=m
CONFIG_MEDIA_TUNER_XC2028=m
CONFIG_MEDIA_TUNER_XC4000=m
CONFIG_MEDIA_TUNER_XC5000=m
# end of Customize TV tuners

#
# Customise DVB Frontends
#

#
# Multistandard (satellite) frontends
#
CONFIG_DVB_M88DS3103=m
CONFIG_DVB_MXL5XX=m
CONFIG_DVB_STB0899=m
CONFIG_DVB_STB6100=m
CONFIG_DVB_STV090x=m
CONFIG_DVB_STV0910=m
CONFIG_DVB_STV6110x=m
CONFIG_DVB_STV6111=m

#
# Multistandard (cable + terrestrial) frontends
#
CONFIG_DVB_DRXK=m
CONFIG_DVB_MN88472=m
CONFIG_DVB_MN88473=m
CONFIG_DVB_SI2165=m
CONFIG_DVB_TDA18271C2DD=m

#
# DVB-S (satellite) frontends
#
CONFIG_DVB_CX24110=m
CONFIG_DVB_CX24116=m
CONFIG_DVB_CX24117=m
CONFIG_DVB_CX24120=m
CONFIG_DVB_CX24123=m
CONFIG_DVB_DS3000=m
CONFIG_DVB_MB86A16=m
CONFIG_DVB_MT312=m
CONFIG_DVB_S5H1420=m
CONFIG_DVB_SI21XX=m
CONFIG_DVB_STB6000=m
CONFIG_DVB_STV0288=m
CONFIG_DVB_STV0299=m
CONFIG_DVB_STV0900=m
CONFIG_DVB_STV6110=m
CONFIG_DVB_TDA10071=m
CONFIG_DVB_TDA10086=m
CONFIG_DVB_TDA8083=m
CONFIG_DVB_TDA8261=m
CONFIG_DVB_TDA826X=m
CONFIG_DVB_TS2020=m
CONFIG_DVB_TUA6100=m
CONFIG_DVB_TUNER_CX24113=m
CONFIG_DVB_TUNER_ITD1000=m
CONFIG_DVB_VES1X93=m
CONFIG_DVB_ZL10036=m
CONFIG_DVB_ZL10039=m

#
# DVB-T (terrestrial) frontends
#
CONFIG_DVB_AF9013=m
CONFIG_DVB_AS102_FE=m
CONFIG_DVB_CX22700=m
CONFIG_DVB_CX22702=m
CONFIG_DVB_CXD2820R=m
CONFIG_DVB_CXD2841ER=m
CONFIG_DVB_DIB3000MB=m
CONFIG_DVB_DIB3000MC=m
CONFIG_DVB_DIB7000M=m
CONFIG_DVB_DIB7000P=m
CONFIG_DVB_DIB9000=m
CONFIG_DVB_DRXD=m
CONFIG_DVB_EC100=m
CONFIG_DVB_GP8PSK_FE=m
CONFIG_DVB_L64781=m
CONFIG_DVB_MT352=m
CONFIG_DVB_NXT6000=m
CONFIG_DVB_RTL2830=m
CONFIG_DVB_RTL2832=m
CONFIG_DVB_RTL2832_SDR=m
CONFIG_DVB_S5H1432=m
CONFIG_DVB_SI2168=m
CONFIG_DVB_SP887X=m
CONFIG_DVB_STV0367=m
CONFIG_DVB_TDA10048=m
CONFIG_DVB_TDA1004X=m
CONFIG_DVB_ZD1301_DEMOD=m
CONFIG_DVB_ZL10353=m
CONFIG_DVB_CXD2880=m

#
# DVB-C (cable) frontends
#
CONFIG_DVB_STV0297=m
CONFIG_DVB_TDA10021=m
CONFIG_DVB_TDA10023=m
CONFIG_DVB_VES1820=m

#
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
#
CONFIG_DVB_AU8522=m
CONFIG_DVB_AU8522_DTV=m
CONFIG_DVB_AU8522_V4L=m
CONFIG_DVB_BCM3510=m
CONFIG_DVB_LG2160=m
CONFIG_DVB_LGDT3305=m
CONFIG_DVB_LGDT3306A=m
CONFIG_DVB_LGDT330X=m
CONFIG_DVB_MXL692=m
CONFIG_DVB_NXT200X=m
CONFIG_DVB_OR51132=m
CONFIG_DVB_OR51211=m
CONFIG_DVB_S5H1409=m
CONFIG_DVB_S5H1411=m

#
# ISDB-T (terrestrial) frontends
#
CONFIG_DVB_DIB8000=m
CONFIG_DVB_MB86A20S=m
CONFIG_DVB_S921=m

#
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
#
CONFIG_DVB_MN88443X=m
CONFIG_DVB_TC90522=m

#
# Digital terrestrial only tuners/PLL
#
CONFIG_DVB_PLL=m
CONFIG_DVB_TUNER_DIB0070=m
CONFIG_DVB_TUNER_DIB0090=m

#
# SEC control devices for DVB-S
#
CONFIG_DVB_A8293=m
CONFIG_DVB_AF9033=m
CONFIG_DVB_ASCOT2E=m
CONFIG_DVB_ATBM8830=m
CONFIG_DVB_HELENE=m
CONFIG_DVB_HORUS3A=m
CONFIG_DVB_ISL6405=m
CONFIG_DVB_ISL6421=m
CONFIG_DVB_ISL6423=m
CONFIG_DVB_IX2505V=m
CONFIG_DVB_LGS8GL5=m
CONFIG_DVB_LGS8GXX=m
CONFIG_DVB_LNBH25=m
CONFIG_DVB_LNBH29=m
CONFIG_DVB_LNBP21=m
CONFIG_DVB_LNBP22=m
CONFIG_DVB_M88RS2000=m
CONFIG_DVB_TDA665x=m
CONFIG_DVB_DRX39XYJ=m

#
# Common Interface (EN50221) controller drivers
#
CONFIG_DVB_CXD2099=m
CONFIG_DVB_SP2=m
# end of Customise DVB Frontends

#
# Tools to develop new frontends
#
CONFIG_DVB_DUMMY_FE=m
# end of Media ancillary drivers

#
# Graphics support
#
CONFIG_APERTURE_HELPERS=y
CONFIG_IMX_IPUV3_CORE=m
CONFIG_DRM_DEBUG_MODESET_LOCK=y

#
# ARM devices
#
# end of ARM devices

#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=m
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_CFB_FILLRECT=m
CONFIG_FB_CFB_COPYAREA=m
CONFIG_FB_CFB_IMAGEBLIT=m
CONFIG_FB_CFB_REV_PIXELS_IN_BYTE=y
CONFIG_FB_SYS_FILLRECT=m
CONFIG_FB_SYS_COPYAREA=m
CONFIG_FB_SYS_IMAGEBLIT=m
CONFIG_FB_FOREIGN_ENDIAN=y
CONFIG_FB_BOTH_ENDIAN=y
# CONFIG_FB_BIG_ENDIAN is not set
# CONFIG_FB_LITTLE_ENDIAN is not set
CONFIG_FB_SYS_FOPS=m
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_BACKLIGHT=m
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y

#
# Frame buffer hardware drivers
#
CONFIG_FB_CLPS711X=m
CONFIG_FB_IMX=m
CONFIG_FB_ARC=m
CONFIG_FB_UVESA=m
CONFIG_FB_PVR2=m
CONFIG_FB_S1D13XXX=m
CONFIG_FB_ATMEL=m
CONFIG_FB_PXA168=m
CONFIG_FB_W100=m
CONFIG_FB_SH_MOBILE_LCDC=m
CONFIG_FB_TMIO=m
CONFIG_FB_TMIO_ACCELL=y
CONFIG_FB_S3C=m
CONFIG_FB_S3C_DEBUG_REGWRITE=y
CONFIG_FB_SMSCUFX=m
CONFIG_FB_UDL=m
CONFIG_FB_IBM_GXT4500=m
CONFIG_FB_GOLDFISH=m
CONFIG_FB_DA8XX=m
CONFIG_FB_VIRTUAL=m
CONFIG_FB_METRONOME=m
CONFIG_FB_BROADSHEET=m
CONFIG_FB_SIMPLE=m
CONFIG_FB_SSD1307=m
CONFIG_FB_OMAP2=m
CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
CONFIG_FB_OMAP2_NUM_FBS=3
CONFIG_FB_OMAP2_DSS_INIT=y
CONFIG_FB_OMAP2_DSS=m
CONFIG_FB_OMAP2_DSS_DEBUG=y
CONFIG_FB_OMAP2_DSS_DEBUGFS=y
CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS=y
CONFIG_FB_OMAP2_DSS_DPI=y
CONFIG_FB_OMAP2_DSS_VENC=y
CONFIG_FB_OMAP2_DSS_HDMI_COMMON=y
CONFIG_FB_OMAP4_DSS_HDMI=y
CONFIG_FB_OMAP5_DSS_HDMI=y
CONFIG_FB_OMAP2_DSS_SDI=y
CONFIG_FB_OMAP2_DSS_DSI=y
CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK=0
CONFIG_FB_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y

#
# OMAPFB Panel and Encoder Drivers
#
CONFIG_FB_OMAP2_ENCODER_OPA362=m
CONFIG_FB_OMAP2_ENCODER_TFP410=m
CONFIG_FB_OMAP2_ENCODER_TPD12S015=m
CONFIG_FB_OMAP2_CONNECTOR_DVI=m
CONFIG_FB_OMAP2_CONNECTOR_HDMI=m
CONFIG_FB_OMAP2_CONNECTOR_ANALOG_TV=m
CONFIG_FB_OMAP2_PANEL_DPI=m
CONFIG_FB_OMAP2_PANEL_DSI_CM=m
CONFIG_FB_OMAP2_PANEL_SONY_ACX565AKM=m
CONFIG_FB_OMAP2_PANEL_LGPHILIPS_LB035Q02=m
CONFIG_FB_OMAP2_PANEL_SHARP_LS037V7DW01=m
CONFIG_FB_OMAP2_PANEL_TPO_TD028TTEC1=m
CONFIG_FB_OMAP2_PANEL_TPO_TD043MTEA1=m
CONFIG_FB_OMAP2_PANEL_NEC_NL8048HL11=m
# end of OMAPFB Panel and Encoder Drivers

CONFIG_MMP_DISP=m
CONFIG_MMP_DISP_CONTROLLER=y
CONFIG_MMP_DISP_SPI=y
CONFIG_MMP_PANEL_TPOHVGA=y
CONFIG_MMP_FB=m
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=m
CONFIG_LCD_L4F00242T03=m
CONFIG_LCD_LMS283GF05=m
CONFIG_LCD_LTV350QV=m
CONFIG_LCD_ILI922X=m
CONFIG_LCD_ILI9320=m
CONFIG_LCD_TDO24M=m
CONFIG_LCD_VGG2432A4=m
CONFIG_LCD_PLATFORM=m
CONFIG_LCD_AMS369FG06=m
CONFIG_LCD_LMS501KF03=m
CONFIG_LCD_HX8357=m
CONFIG_LCD_OTM3225A=m
CONFIG_BACKLIGHT_CLASS_DEVICE=m
CONFIG_BACKLIGHT_ATMEL_LCDC=y
CONFIG_BACKLIGHT_KTD253=m
CONFIG_BACKLIGHT_LM3533=m
CONFIG_BACKLIGHT_OMAP1=m
CONFIG_BACKLIGHT_PWM=m
CONFIG_BACKLIGHT_DA9052=m
CONFIG_BACKLIGHT_MT6370=m
CONFIG_BACKLIGHT_QCOM_WLED=m
CONFIG_BACKLIGHT_RT4831=m
CONFIG_BACKLIGHT_WM831X=m
CONFIG_BACKLIGHT_ADP8860=m
CONFIG_BACKLIGHT_ADP8870=m
CONFIG_BACKLIGHT_PCF50633=m
CONFIG_BACKLIGHT_LM3630A=m
CONFIG_BACKLIGHT_LM3639=m
CONFIG_BACKLIGHT_LP855X=m
CONFIG_BACKLIGHT_SKY81452=m
CONFIG_BACKLIGHT_TPS65217=m
CONFIG_BACKLIGHT_GPIO=m
CONFIG_BACKLIGHT_LV5207LP=m
CONFIG_BACKLIGHT_BD6107=m
CONFIG_BACKLIGHT_ARCXCNN=m
CONFIG_BACKLIGHT_RAVE_SP=m
CONFIG_BACKLIGHT_LED=m
# end of Backlight & LCD device support

CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
# end of Console display driver support

CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
CONFIG_LOGO_SUPERH_MONO=y
CONFIG_LOGO_SUPERH_VGA16=y
CONFIG_LOGO_SUPERH_CLUT224=y
# end of Graphics support

CONFIG_SOUND=m
CONFIG_SOUND_OSS_CORE=y
CONFIG_SOUND_OSS_CORE_PRECLAIM=y
CONFIG_SND=m
CONFIG_SND_TIMER=m
CONFIG_SND_PCM=m
CONFIG_SND_PCM_ELD=y
CONFIG_SND_PCM_IEC958=y
CONFIG_SND_DMAENGINE_PCM=m
CONFIG_SND_HWDEP=m
CONFIG_SND_SEQ_DEVICE=m
CONFIG_SND_RAWMIDI=m
CONFIG_SND_COMPRESS_OFFLOAD=m
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=m
CONFIG_SND_PCM_OSS=m
CONFIG_SND_PCM_OSS_PLUGINS=y
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=m
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
CONFIG_SND_SUPPORT_OLD_API=y
CONFIG_SND_PROC_FS=y
CONFIG_SND_VERBOSE_PROCFS=y
CONFIG_SND_VERBOSE_PRINTK=y
CONFIG_SND_CTL_FAST_LOOKUP=y
CONFIG_SND_DEBUG=y
CONFIG_SND_DEBUG_VERBOSE=y
CONFIG_SND_PCM_XRUN_DEBUG=y
CONFIG_SND_CTL_INPUT_VALIDATION=y
CONFIG_SND_CTL_DEBUG=y
CONFIG_SND_JACK_INJECTION_DEBUG=y
CONFIG_SND_VMASTER=y
CONFIG_SND_CTL_LED=m
CONFIG_SND_SEQUENCER=m
CONFIG_SND_SEQ_DUMMY=m
CONFIG_SND_SEQUENCER_OSS=m
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
CONFIG_SND_SEQ_MIDI_EVENT=m
CONFIG_SND_SEQ_MIDI=m
CONFIG_SND_SEQ_VIRMIDI=m
CONFIG_SND_MPU401_UART=m
CONFIG_SND_VX_LIB=m
CONFIG_SND_AC97_CODEC=m
CONFIG_SND_DRIVERS=y
CONFIG_SND_DUMMY=m
CONFIG_SND_ALOOP=m
CONFIG_SND_VIRMIDI=m
CONFIG_SND_MTPAV=m
CONFIG_SND_MTS64=m
CONFIG_SND_SERIAL_U16550=m
CONFIG_SND_SERIAL_GENERIC=m
CONFIG_SND_MPU401=m
CONFIG_SND_PORTMAN2X4=m
CONFIG_SND_AC97_POWER_SAVE=y
CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0

#
# HD-Audio
#
CONFIG_SND_HDA=m
CONFIG_SND_HDA_GENERIC_LEDS=y
CONFIG_SND_HDA_HWDEP=y
CONFIG_SND_HDA_RECONFIG=y
CONFIG_SND_HDA_INPUT_BEEP=y
CONFIG_SND_HDA_INPUT_BEEP_MODE=1
CONFIG_SND_HDA_PATCH_LOADER=y
CONFIG_SND_HDA_CODEC_REALTEK=m
CONFIG_SND_HDA_CODEC_ANALOG=m
CONFIG_SND_HDA_CODEC_SIGMATEL=m
CONFIG_SND_HDA_CODEC_VIA=m
CONFIG_SND_HDA_CODEC_HDMI=m
CONFIG_SND_HDA_CODEC_CIRRUS=m
CONFIG_SND_HDA_CODEC_CS8409=m
CONFIG_SND_HDA_CODEC_CONEXANT=m
CONFIG_SND_HDA_CODEC_CA0110=m
CONFIG_SND_HDA_CODEC_CA0132=m
CONFIG_SND_HDA_CODEC_CA0132_DSP=y
CONFIG_SND_HDA_CODEC_CMEDIA=m
CONFIG_SND_HDA_CODEC_SI3054=m
CONFIG_SND_HDA_GENERIC=m
CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
# end of HD-Audio

CONFIG_SND_HDA_CORE=m
CONFIG_SND_HDA_DSP_LOADER=y
CONFIG_SND_HDA_EXT_CORE=m
CONFIG_SND_HDA_PREALLOC_SIZE=64
CONFIG_SND_INTEL_DSP_CONFIG=m
CONFIG_SND_PXA2XX_LIB=m
CONFIG_SND_SPI=y
CONFIG_SND_AT73C213=m
CONFIG_SND_AT73C213_TARGET_BITRATE=48000
CONFIG_SND_SUPERH=y
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_USB_US122L=m
CONFIG_SND_USB_6FIRE=m
CONFIG_SND_USB_HIFACE=m
CONFIG_SND_BCD2000=m
CONFIG_SND_USB_LINE6=m
CONFIG_SND_USB_POD=m
CONFIG_SND_USB_PODHD=m
CONFIG_SND_USB_TONEPORT=m
CONFIG_SND_USB_VARIAX=m
CONFIG_SND_FIREWIRE=y
CONFIG_SND_FIREWIRE_LIB=m
CONFIG_SND_DICE=m
CONFIG_SND_OXFW=m
CONFIG_SND_ISIGHT=m
CONFIG_SND_FIREWORKS=m
CONFIG_SND_BEBOB=m
CONFIG_SND_FIREWIRE_DIGI00X=m
CONFIG_SND_FIREWIRE_TASCAM=m
CONFIG_SND_FIREWIRE_MOTU=m
CONFIG_SND_FIREFACE=m
CONFIG_SND_PCMCIA=y
CONFIG_SND_VXPOCKET=m
CONFIG_SND_PDAUDIOCF=m
CONFIG_SND_SOC=m
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
CONFIG_SND_SOC_COMPRESS=y
CONFIG_SND_SOC_TOPOLOGY=y
CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=m
CONFIG_SND_SOC_UTILS_KUNIT_TEST=m
CONFIG_SND_SOC_ADI=m
CONFIG_SND_SOC_ADI_AXI_I2S=m
CONFIG_SND_SOC_ADI_AXI_SPDIF=m
CONFIG_SND_SOC_AMD_ACP=m
CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
CONFIG_SND_AMD_ACP_CONFIG=m
CONFIG_SND_SOC_APPLE_MCA=m
CONFIG_SND_ATMEL_SOC=m
CONFIG_SND_ATMEL_SOC_PDC=y
CONFIG_SND_ATMEL_SOC_DMA=y
CONFIG_SND_ATMEL_SOC_SSC=m
CONFIG_SND_ATMEL_SOC_SSC_PDC=m
CONFIG_SND_ATMEL_SOC_SSC_DMA=m
CONFIG_SND_AT91_SOC_SAM9G20_WM8731=m
CONFIG_SND_ATMEL_SOC_WM8904=m
CONFIG_SND_AT91_SOC_SAM9X5_WM8731=m
CONFIG_SND_ATMEL_SOC_CLASSD=m
CONFIG_SND_ATMEL_SOC_PDMIC=m
CONFIG_SND_ATMEL_SOC_I2S=m
CONFIG_SND_SOC_MIKROE_PROTO=m
CONFIG_SND_MCHP_SOC_I2S_MCC=m
CONFIG_SND_MCHP_SOC_SPDIFTX=m
CONFIG_SND_MCHP_SOC_PDMC=m
CONFIG_SND_BCM2835_SOC_I2S=m
CONFIG_SND_SOC_CYGNUS=m
CONFIG_SND_BCM63XX_I2S_WHISTLER=m
CONFIG_SND_EP93XX_SOC=m
CONFIG_SND_DESIGNWARE_I2S=m
CONFIG_SND_DESIGNWARE_PCM=y

#
# SoC Audio for Freescale CPUs
#

#
# Common SoC Audio options for Freescale CPUs:
#
CONFIG_SND_SOC_FSL_SAI=m
CONFIG_SND_SOC_FSL_MQS=m
CONFIG_SND_SOC_FSL_AUDMIX=m
CONFIG_SND_SOC_FSL_SSI=m
CONFIG_SND_SOC_FSL_SPDIF=m
CONFIG_SND_SOC_FSL_ESAI=m
CONFIG_SND_SOC_FSL_MICFIL=m
CONFIG_SND_SOC_FSL_XCVR=m
CONFIG_SND_SOC_FSL_AUD2HTX=m
CONFIG_SND_SOC_FSL_UTILS=m
CONFIG_SND_SOC_IMX_PCM_DMA=m
CONFIG_SND_SOC_IMX_AUDIO_RPMSG=m
CONFIG_SND_SOC_IMX_PCM_RPMSG=m
CONFIG_SND_SOC_IMX_AUDMUX=m
CONFIG_SND_IMX_SOC=m

#
# SoC Audio support for Freescale i.MX boards:
#
CONFIG_SND_SOC_IMX_ES8328=m
CONFIG_SND_SOC_IMX_SGTL5000=m
CONFIG_SND_SOC_IMX_SPDIF=m
CONFIG_SND_SOC_FSL_ASOC_CARD=m
CONFIG_SND_SOC_IMX_AUDMIX=m
CONFIG_SND_SOC_IMX_HDMI=m
CONFIG_SND_SOC_IMX_RPMSG=m
CONFIG_SND_SOC_IMX_CARD=m
# end of SoC Audio for Freescale CPUs

CONFIG_SND_I2S_HI6210_I2S=m
CONFIG_SND_JZ4740_SOC_I2S=m
CONFIG_SND_KIRKWOOD_SOC=m
CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB=m
CONFIG_SND_SOC_IMG=y
CONFIG_SND_SOC_IMG_I2S_IN=m
CONFIG_SND_SOC_IMG_I2S_OUT=m
CONFIG_SND_SOC_IMG_PARALLEL_OUT=m
CONFIG_SND_SOC_IMG_SPDIF_IN=m
CONFIG_SND_SOC_IMG_SPDIF_OUT=m
CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=m
CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y
CONFIG_SND_SOC_ACPI_INTEL_MATCH=m
CONFIG_SND_SOC_INTEL_MACH=y
CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES=y
CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH=m
CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH=m
CONFIG_SND_SOC_INTEL_BROADWELL_MACH=m
CONFIG_SND_SOC_MTK_BTCVSD=m
CONFIG_SND_PXA2XX_SOC=m
CONFIG_SND_SOC_QCOM=m
CONFIG_SND_SOC_LPASS_CPU=m
CONFIG_SND_SOC_LPASS_HDMI=m
CONFIG_SND_SOC_LPASS_PLATFORM=m
CONFIG_SND_SOC_LPASS_CDC_DMA=m
CONFIG_SND_SOC_LPASS_IPQ806X=m
CONFIG_SND_SOC_LPASS_APQ8016=m
CONFIG_SND_SOC_LPASS_SC7180=m
CONFIG_SND_SOC_LPASS_SC7280=m
CONFIG_SND_SOC_STORM=m
CONFIG_SND_SOC_APQ8016_SBC=m
CONFIG_SND_SOC_QCOM_COMMON=m
CONFIG_SND_SOC_SC7180=m
CONFIG_SND_SOC_SC7280=m
CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_ROCKCHIP_I2S=m
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
CONFIG_SND_SOC_ROCKCHIP_PDM=m
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
CONFIG_SND_SOC_ROCKCHIP_RT5645=m
CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m
CONFIG_SND_SOC_RK3399_GRU_SOUND=m

#
# SoC Audio support for Renesas SoCs
#
CONFIG_SND_SOC_SH4_FSI=m
CONFIG_SND_SOC_RZ=m
# end of SoC Audio support for Renesas SoCs

CONFIG_SND_SOC_SOF_TOPLEVEL=y
CONFIG_SND_SOC_SOF_ACPI=m
CONFIG_SND_SOC_SOF_ACPI_DEV=m
CONFIG_SND_SOC_SOF_OF=m
CONFIG_SND_SOC_SOF_OF_DEV=m
CONFIG_SND_SOC_SOF_COMPRESS=y
CONFIG_SND_SOC_SOF_CLIENT=m
CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT=y
CONFIG_SND_SOC_SOF_FORCE_PROBE_WORKQUEUE=y
CONFIG_SND_SOC_SOF_NOCODEC=m
CONFIG_SND_SOC_SOF_NOCODEC_SUPPORT=y
CONFIG_SND_SOC_SOF_STRICT_ABI_CHECKS=y
CONFIG_SND_SOC_SOF_DEBUG=y
CONFIG_SND_SOC_SOF_FORCE_NOCODEC_MODE=y
CONFIG_SND_SOC_SOF_DEBUG_XRUN_STOP=y
CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC=y
CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION=y
CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE=y
CONFIG_SND_SOC_SOF_DEBUG_ENABLE_FIRMWARE_TRACE=y
CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST=m
CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST_NUM=2
CONFIG_SND_SOC_SOF_DEBUG_IPC_MSG_INJECTOR=m
CONFIG_SND_SOC_SOF_DEBUG_RETAIN_DSP_CONTEXT=y
CONFIG_SND_SOC_SOF=m
CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE=y
CONFIG_SND_SOC_SOF_IPC3=y
CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=m
CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y
CONFIG_SND_SOC_SOF_IMX_COMMON=m
CONFIG_SND_SOC_SOF_IMX8=m
CONFIG_SND_SOC_SOF_IMX8M=m
CONFIG_SND_SOC_SOF_IMX8ULP=m
CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL=y
CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC=m
CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP=m
CONFIG_SND_SOC_SOF_INTEL_COMMON=m
CONFIG_SND_SOC_SOF_BAYTRAIL=m
CONFIG_SND_SOC_SOF_BROADWELL=m
CONFIG_SND_SOC_SOF_MTK_TOPLEVEL=y
CONFIG_SND_SOC_SOF_MTK_COMMON=m
CONFIG_SND_SOC_SOF_MT8186=m
CONFIG_SND_SOC_SOF_MT8195=m
CONFIG_SND_SOC_SOF_XTENSA=m
CONFIG_SND_SOC_SPRD=m
CONFIG_SND_SOC_SPRD_MCDT=m
CONFIG_SND_SOC_STI=m

#
# STMicroelectronics STM32 SOC audio support
#
CONFIG_SND_SOC_STM32_SPDIFRX=m
CONFIG_SND_SOC_STM32_DFSDM=m
# end of STMicroelectronics STM32 SOC audio support

#
# Allwinner SoC Audio support
#
CONFIG_SND_SUN4I_CODEC=m
CONFIG_SND_SUN8I_CODEC_ANALOG=m
CONFIG_SND_SUN50I_CODEC_ANALOG=m
CONFIG_SND_SUN4I_I2S=m
CONFIG_SND_SUN4I_SPDIF=m
CONFIG_SND_SUN50I_DMIC=m
CONFIG_SND_SUN8I_ADDA_PR_REGMAP=m
# end of Allwinner SoC Audio support

#
# Audio support for Texas Instruments SoCs
#
CONFIG_SND_SOC_TI_EDMA_PCM=m
CONFIG_SND_SOC_TI_SDMA_PCM=m

#
# Texas Instruments DAI support for:
#
CONFIG_SND_SOC_DAVINCI_ASP=m
CONFIG_SND_SOC_DAVINCI_VCIF=m
CONFIG_SND_SOC_OMAP_MCPDM=m

#
# Audio support for boards with Texas Instruments SoCs
#
CONFIG_SND_SOC_OMAP_HDMI=m
# end of Audio support for Texas Instruments SoCs

CONFIG_SND_SOC_UNIPHIER=m
CONFIG_SND_SOC_UNIPHIER_AIO=m
CONFIG_SND_SOC_UNIPHIER_LD11=m
CONFIG_SND_SOC_UNIPHIER_PXS2=m
CONFIG_SND_SOC_UNIPHIER_EVEA_CODEC=m
CONFIG_SND_SOC_XILINX_I2S=m
CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m
CONFIG_SND_SOC_XILINX_SPDIF=m
CONFIG_SND_SOC_XTFPGA_I2S=m
CONFIG_SND_SOC_I2C_AND_SPI=m

#
# CODEC drivers
#
CONFIG_SND_SOC_ALL_CODECS=m
# CONFIG_SND_SOC_88PM860X is not set
CONFIG_SND_SOC_ARIZONA=m
CONFIG_SND_SOC_WM_HUBS=m
CONFIG_SND_SOC_WM_ADSP=m
CONFIG_SND_SOC_AB8500_CODEC=m
CONFIG_SND_SOC_AC97_CODEC=m
CONFIG_SND_SOC_AD1836=m
CONFIG_SND_SOC_AD193X=m
CONFIG_SND_SOC_AD193X_SPI=m
CONFIG_SND_SOC_AD193X_I2C=m
CONFIG_SND_SOC_AD1980=m
CONFIG_SND_SOC_AD73311=m
CONFIG_SND_SOC_ADAU_UTILS=m
CONFIG_SND_SOC_ADAU1372=m
CONFIG_SND_SOC_ADAU1372_I2C=m
CONFIG_SND_SOC_ADAU1372_SPI=m
CONFIG_SND_SOC_ADAU1373=m
CONFIG_SND_SOC_ADAU1701=m
CONFIG_SND_SOC_ADAU17X1=m
CONFIG_SND_SOC_ADAU1761=m
CONFIG_SND_SOC_ADAU1761_I2C=m
CONFIG_SND_SOC_ADAU1761_SPI=m
CONFIG_SND_SOC_ADAU1781=m
CONFIG_SND_SOC_ADAU1781_I2C=m
CONFIG_SND_SOC_ADAU1781_SPI=m
CONFIG_SND_SOC_ADAU1977=m
CONFIG_SND_SOC_ADAU1977_SPI=m
CONFIG_SND_SOC_ADAU1977_I2C=m
CONFIG_SND_SOC_ADAU7002=m
CONFIG_SND_SOC_ADAU7118=m
CONFIG_SND_SOC_ADAU7118_HW=m
CONFIG_SND_SOC_ADAU7118_I2C=m
CONFIG_SND_SOC_ADAV80X=m
CONFIG_SND_SOC_ADAV801=m
CONFIG_SND_SOC_ADAV803=m
CONFIG_SND_SOC_ADS117X=m
CONFIG_SND_SOC_AK4104=m
CONFIG_SND_SOC_AK4118=m
CONFIG_SND_SOC_AK4375=m
CONFIG_SND_SOC_AK4458=m
CONFIG_SND_SOC_AK4535=m
CONFIG_SND_SOC_AK4554=m
CONFIG_SND_SOC_AK4613=m
CONFIG_SND_SOC_AK4641=m
CONFIG_SND_SOC_AK4642=m
CONFIG_SND_SOC_AK4671=m
CONFIG_SND_SOC_AK5386=m
CONFIG_SND_SOC_AK5558=m
CONFIG_SND_SOC_ALC5623=m
CONFIG_SND_SOC_ALC5632=m
CONFIG_SND_SOC_AW8738=m
CONFIG_SND_SOC_BD28623=m
CONFIG_SND_SOC_BT_SCO=m
CONFIG_SND_SOC_CPCAP=m
CONFIG_SND_SOC_CQ0093VC=m
CONFIG_SND_SOC_CROS_EC_CODEC=m
CONFIG_SND_SOC_CS35L32=m
CONFIG_SND_SOC_CS35L33=m
CONFIG_SND_SOC_CS35L34=m
CONFIG_SND_SOC_CS35L35=m
CONFIG_SND_SOC_CS35L36=m
CONFIG_SND_SOC_CS35L41_LIB=m
CONFIG_SND_SOC_CS35L41=m
CONFIG_SND_SOC_CS35L41_SPI=m
CONFIG_SND_SOC_CS35L41_I2C=m
CONFIG_SND_SOC_CS35L45_TABLES=m
CONFIG_SND_SOC_CS35L45=m
CONFIG_SND_SOC_CS35L45_SPI=m
CONFIG_SND_SOC_CS35L45_I2C=m
CONFIG_SND_SOC_CS42L42_CORE=m
CONFIG_SND_SOC_CS42L42=m
CONFIG_SND_SOC_CS42L51=m
CONFIG_SND_SOC_CS42L51_I2C=m
CONFIG_SND_SOC_CS42L52=m
CONFIG_SND_SOC_CS42L56=m
CONFIG_SND_SOC_CS42L73=m
CONFIG_SND_SOC_CS42L83=m
CONFIG_SND_SOC_CS4234=m
CONFIG_SND_SOC_CS4265=m
CONFIG_SND_SOC_CS4270=m
CONFIG_SND_SOC_CS4271=m
CONFIG_SND_SOC_CS4271_I2C=m
CONFIG_SND_SOC_CS4271_SPI=m
CONFIG_SND_SOC_CS42XX8=m
CONFIG_SND_SOC_CS42XX8_I2C=m
CONFIG_SND_SOC_CS43130=m
CONFIG_SND_SOC_CS4341=m
CONFIG_SND_SOC_CS4349=m
CONFIG_SND_SOC_CS47L15=m
CONFIG_SND_SOC_CS47L24=m
CONFIG_SND_SOC_CS47L35=m
CONFIG_SND_SOC_CS47L85=m
CONFIG_SND_SOC_CS47L90=m
CONFIG_SND_SOC_CS47L92=m
CONFIG_SND_SOC_CS53L30=m
CONFIG_SND_SOC_CX20442=m
CONFIG_SND_SOC_CX2072X=m
CONFIG_SND_SOC_JZ4740_CODEC=m
CONFIG_SND_SOC_JZ4725B_CODEC=m
CONFIG_SND_SOC_JZ4760_CODEC=m
CONFIG_SND_SOC_JZ4770_CODEC=m
CONFIG_SND_SOC_L3=m
CONFIG_SND_SOC_DA7210=m
CONFIG_SND_SOC_DA7213=m
CONFIG_SND_SOC_DA7218=m
CONFIG_SND_SOC_DA7219=m
CONFIG_SND_SOC_DA732X=m
CONFIG_SND_SOC_DA9055=m
CONFIG_SND_SOC_DMIC=m
CONFIG_SND_SOC_HDMI_CODEC=m
CONFIG_SND_SOC_ES7134=m
CONFIG_SND_SOC_ES7241=m
CONFIG_SND_SOC_ES8316=m
CONFIG_SND_SOC_ES8326=m
CONFIG_SND_SOC_ES8328=m
CONFIG_SND_SOC_ES8328_I2C=m
CONFIG_SND_SOC_ES8328_SPI=m
CONFIG_SND_SOC_GTM601=m
CONFIG_SND_SOC_HDAC_HDMI=m
CONFIG_SND_SOC_HDAC_HDA=m
CONFIG_SND_SOC_HDA=m
CONFIG_SND_SOC_ICS43432=m
CONFIG_SND_SOC_INNO_RK3036=m
CONFIG_SND_SOC_ISABELLE=m
CONFIG_SND_SOC_LM49453=m
CONFIG_SND_SOC_LOCHNAGAR_SC=m
CONFIG_SND_SOC_MADERA=m
CONFIG_SND_SOC_MAX98088=m
CONFIG_SND_SOC_MAX98090=m
CONFIG_SND_SOC_MAX98095=m
CONFIG_SND_SOC_MAX98357A=m
CONFIG_SND_SOC_MAX98371=m
CONFIG_SND_SOC_MAX98504=m
CONFIG_SND_SOC_MAX9867=m
CONFIG_SND_SOC_MAX98925=m
CONFIG_SND_SOC_MAX98926=m
CONFIG_SND_SOC_MAX98927=m
CONFIG_SND_SOC_MAX98520=m
CONFIG_SND_SOC_MAX98373=m
CONFIG_SND_SOC_MAX98373_I2C=m
CONFIG_SND_SOC_MAX98373_SDW=m
CONFIG_SND_SOC_MAX98390=m
CONFIG_SND_SOC_MAX98396=m
CONFIG_SND_SOC_MAX9850=m
CONFIG_SND_SOC_MAX9860=m
CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
CONFIG_SND_SOC_PCM1681=m
CONFIG_SND_SOC_PCM1789=m
CONFIG_SND_SOC_PCM1789_I2C=m
CONFIG_SND_SOC_PCM179X=m
CONFIG_SND_SOC_PCM179X_I2C=m
CONFIG_SND_SOC_PCM179X_SPI=m
CONFIG_SND_SOC_PCM186X=m
CONFIG_SND_SOC_PCM186X_I2C=m
CONFIG_SND_SOC_PCM186X_SPI=m
CONFIG_SND_SOC_PCM3008=m
CONFIG_SND_SOC_PCM3060=m
CONFIG_SND_SOC_PCM3060_I2C=m
CONFIG_SND_SOC_PCM3060_SPI=m
CONFIG_SND_SOC_PCM3168A=m
CONFIG_SND_SOC_PCM3168A_I2C=m
CONFIG_SND_SOC_PCM3168A_SPI=m
CONFIG_SND_SOC_PCM5102A=m
CONFIG_SND_SOC_PCM512x=m
CONFIG_SND_SOC_PCM512x_I2C=m
CONFIG_SND_SOC_PCM512x_SPI=m
CONFIG_SND_SOC_RK3328=m
CONFIG_SND_SOC_RK817=m
CONFIG_SND_SOC_RL6231=m
CONFIG_SND_SOC_RL6347A=m
CONFIG_SND_SOC_RT274=m
CONFIG_SND_SOC_RT286=m
CONFIG_SND_SOC_RT298=m
CONFIG_SND_SOC_RT1011=m
CONFIG_SND_SOC_RT1015=m
CONFIG_SND_SOC_RT1015P=m
CONFIG_SND_SOC_RT1016=m
CONFIG_SND_SOC_RT1019=m
CONFIG_SND_SOC_RT1305=m
CONFIG_SND_SOC_RT1308=m
CONFIG_SND_SOC_RT1308_SDW=m
CONFIG_SND_SOC_RT1316_SDW=m
CONFIG_SND_SOC_RT5514=m
CONFIG_SND_SOC_RT5514_SPI=m
CONFIG_SND_SOC_RT5616=m
CONFIG_SND_SOC_RT5631=m
CONFIG_SND_SOC_RT5640=m
CONFIG_SND_SOC_RT5645=m
CONFIG_SND_SOC_RT5651=m
CONFIG_SND_SOC_RT5659=m
CONFIG_SND_SOC_RT5660=m
CONFIG_SND_SOC_RT5663=m
CONFIG_SND_SOC_RT5665=m
CONFIG_SND_SOC_RT5668=m
CONFIG_SND_SOC_RT5670=m
CONFIG_SND_SOC_RT5677=m
CONFIG_SND_SOC_RT5677_SPI=m
CONFIG_SND_SOC_RT5682=m
CONFIG_SND_SOC_RT5682_I2C=m
CONFIG_SND_SOC_RT5682_SDW=m
CONFIG_SND_SOC_RT5682S=m
CONFIG_SND_SOC_RT700=m
CONFIG_SND_SOC_RT700_SDW=m
CONFIG_SND_SOC_RT711=m
CONFIG_SND_SOC_RT711_SDW=m
CONFIG_SND_SOC_RT711_SDCA_SDW=m
CONFIG_SND_SOC_RT715=m
CONFIG_SND_SOC_RT715_SDW=m
CONFIG_SND_SOC_RT715_SDCA_SDW=m
CONFIG_SND_SOC_RT9120=m
CONFIG_SND_SOC_SDW_MOCKUP=m
CONFIG_SND_SOC_SGTL5000=m
CONFIG_SND_SOC_SI476X=m
CONFIG_SND_SOC_SIGMADSP=m
CONFIG_SND_SOC_SIGMADSP_I2C=m
CONFIG_SND_SOC_SIGMADSP_REGMAP=m
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
CONFIG_SND_SOC_SIMPLE_MUX=m
CONFIG_SND_SOC_SPDIF=m
CONFIG_SND_SOC_SRC4XXX_I2C=m
CONFIG_SND_SOC_SRC4XXX=m
CONFIG_SND_SOC_SSM2305=m
CONFIG_SND_SOC_SSM2518=m
CONFIG_SND_SOC_SSM2602=m
CONFIG_SND_SOC_SSM2602_SPI=m
CONFIG_SND_SOC_SSM2602_I2C=m
CONFIG_SND_SOC_SSM4567=m
CONFIG_SND_SOC_STA32X=m
CONFIG_SND_SOC_STA350=m
CONFIG_SND_SOC_STA529=m
CONFIG_SND_SOC_STAC9766=m
CONFIG_SND_SOC_STI_SAS=m
CONFIG_SND_SOC_TAS2552=m
CONFIG_SND_SOC_TAS2562=m
CONFIG_SND_SOC_TAS2764=m
CONFIG_SND_SOC_TAS2770=m
CONFIG_SND_SOC_TAS2780=m
CONFIG_SND_SOC_TAS5086=m
CONFIG_SND_SOC_TAS571X=m
CONFIG_SND_SOC_TAS5720=m
CONFIG_SND_SOC_TAS5805M=m
CONFIG_SND_SOC_TAS6424=m
CONFIG_SND_SOC_TDA7419=m
CONFIG_SND_SOC_TFA9879=m
CONFIG_SND_SOC_TFA989X=m
CONFIG_SND_SOC_TLV320ADC3XXX=m
CONFIG_SND_SOC_TLV320AIC23=m
CONFIG_SND_SOC_TLV320AIC23_I2C=m
CONFIG_SND_SOC_TLV320AIC23_SPI=m
CONFIG_SND_SOC_TLV320AIC26=m
CONFIG_SND_SOC_TLV320AIC31XX=m
# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
CONFIG_SND_SOC_TLV320AIC3X=m
CONFIG_SND_SOC_TLV320AIC3X_I2C=m
CONFIG_SND_SOC_TLV320AIC3X_SPI=m
CONFIG_SND_SOC_TLV320DAC33=m
CONFIG_SND_SOC_TLV320ADCX140=m
CONFIG_SND_SOC_TS3A227E=m
CONFIG_SND_SOC_TSCS42XX=m
CONFIG_SND_SOC_TSCS454=m
# CONFIG_SND_SOC_TWL4030 is not set
# CONFIG_SND_SOC_TWL6040 is not set
CONFIG_SND_SOC_UDA1334=m
CONFIG_SND_SOC_UDA134X=m
CONFIG_SND_SOC_UDA1380=m
CONFIG_SND_SOC_WCD9335=m
CONFIG_SND_SOC_WCD_MBHC=m
# CONFIG_SND_SOC_WCD934X is not set
CONFIG_SND_SOC_WCD938X=m
CONFIG_SND_SOC_WCD938X_SDW=m
CONFIG_SND_SOC_WL1273=m
CONFIG_SND_SOC_WM0010=m
CONFIG_SND_SOC_WM1250_EV1=m
CONFIG_SND_SOC_WM2000=m
CONFIG_SND_SOC_WM2200=m
CONFIG_SND_SOC_WM5100=m
CONFIG_SND_SOC_WM5102=m
CONFIG_SND_SOC_WM5110=m
# CONFIG_SND_SOC_WM8350 is not set
# CONFIG_SND_SOC_WM8400 is not set
CONFIG_SND_SOC_WM8510=m
CONFIG_SND_SOC_WM8523=m
CONFIG_SND_SOC_WM8524=m
CONFIG_SND_SOC_WM8580=m
CONFIG_SND_SOC_WM8711=m
CONFIG_SND_SOC_WM8727=m
CONFIG_SND_SOC_WM8728=m
CONFIG_SND_SOC_WM8731=m
CONFIG_SND_SOC_WM8731_I2C=m
CONFIG_SND_SOC_WM8731_SPI=m
CONFIG_SND_SOC_WM8737=m
CONFIG_SND_SOC_WM8741=m
CONFIG_SND_SOC_WM8750=m
CONFIG_SND_SOC_WM8753=m
CONFIG_SND_SOC_WM8770=m
CONFIG_SND_SOC_WM8776=m
CONFIG_SND_SOC_WM8782=m
CONFIG_SND_SOC_WM8804=m
CONFIG_SND_SOC_WM8804_I2C=m
CONFIG_SND_SOC_WM8804_SPI=m
CONFIG_SND_SOC_WM8900=m
CONFIG_SND_SOC_WM8903=m
CONFIG_SND_SOC_WM8904=m
CONFIG_SND_SOC_WM8940=m
CONFIG_SND_SOC_WM8955=m
CONFIG_SND_SOC_WM8960=m
CONFIG_SND_SOC_WM8961=m
CONFIG_SND_SOC_WM8962=m
CONFIG_SND_SOC_WM8971=m
CONFIG_SND_SOC_WM8974=m
CONFIG_SND_SOC_WM8978=m
CONFIG_SND_SOC_WM8983=m
CONFIG_SND_SOC_WM8985=m
CONFIG_SND_SOC_WM8988=m
CONFIG_SND_SOC_WM8990=m
CONFIG_SND_SOC_WM8991=m
CONFIG_SND_SOC_WM8993=m
CONFIG_SND_SOC_WM8994=m
CONFIG_SND_SOC_WM8995=m
CONFIG_SND_SOC_WM8996=m
CONFIG_SND_SOC_WM8997=m
CONFIG_SND_SOC_WM8998=m
CONFIG_SND_SOC_WM9081=m
CONFIG_SND_SOC_WM9090=m
CONFIG_SND_SOC_WM9705=m
CONFIG_SND_SOC_WM9712=m
CONFIG_SND_SOC_WM9713=m
CONFIG_SND_SOC_WSA881X=m
CONFIG_SND_SOC_WSA883X=m
CONFIG_SND_SOC_ZL38060=m
CONFIG_SND_SOC_LM4857=m
CONFIG_SND_SOC_MAX9759=m
CONFIG_SND_SOC_MAX9768=m
CONFIG_SND_SOC_MAX9877=m
CONFIG_SND_SOC_MC13783=m
CONFIG_SND_SOC_ML26124=m
CONFIG_SND_SOC_MT6351=m
CONFIG_SND_SOC_MT6358=m
CONFIG_SND_SOC_MT6359=m
CONFIG_SND_SOC_MT6359_ACCDET=m
CONFIG_SND_SOC_MT6660=m
CONFIG_SND_SOC_NAU8315=m
CONFIG_SND_SOC_NAU8540=m
CONFIG_SND_SOC_NAU8810=m
CONFIG_SND_SOC_NAU8821=m
CONFIG_SND_SOC_NAU8822=m
CONFIG_SND_SOC_NAU8824=m
CONFIG_SND_SOC_NAU8825=m
CONFIG_SND_SOC_TPA6130A2=m
CONFIG_SND_SOC_LPASS_MACRO_COMMON=m
# CONFIG_SND_SOC_LPASS_RX_MACRO is not set
# CONFIG_SND_SOC_LPASS_TX_MACRO is not set
CONFIG_SND_SOC_AW883XX=m
# end of CODEC drivers

CONFIG_SND_SIMPLE_CARD_UTILS=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_SND_AUDIO_GRAPH_CARD2=m
CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
CONFIG_SND_TEST_COMPONENT=m
CONFIG_SND_VIRTIO=m
CONFIG_AC97_BUS=m

#
# HID support
#
CONFIG_HID=m
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
CONFIG_UHID=m
CONFIG_HID_GENERIC=m

#
# Special HID drivers
#
CONFIG_HID_A4TECH=m
CONFIG_HID_ACCUTOUCH=m
CONFIG_HID_ACRUX=m
CONFIG_HID_ACRUX_FF=y
CONFIG_HID_APPLE=m
CONFIG_HID_APPLEIR=m
CONFIG_HID_ASUS=m
CONFIG_HID_AUREAL=m
CONFIG_HID_BELKIN=m
CONFIG_HID_BETOP_FF=m
CONFIG_HID_BIGBEN_FF=m
CONFIG_HID_CHERRY=m
CONFIG_HID_CHICONY=m
CONFIG_HID_CORSAIR=m
CONFIG_HID_COUGAR=m
CONFIG_HID_MACALLY=m
CONFIG_HID_PRODIKEYS=m
CONFIG_HID_CMEDIA=m
CONFIG_HID_CP2112=m
CONFIG_HID_CREATIVE_SB0540=m
CONFIG_HID_CYPRESS=m
CONFIG_HID_DRAGONRISE=m
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=m
CONFIG_HID_ELAN=m
CONFIG_HID_ELECOM=m
CONFIG_HID_ELO=m
CONFIG_HID_EZKEY=m
CONFIG_HID_FT260=m
CONFIG_HID_GEMBIRD=m
CONFIG_HID_GFRM=m
CONFIG_HID_GLORIOUS=m
CONFIG_HID_HOLTEK=m
CONFIG_HOLTEK_FF=y
CONFIG_HID_VIVALDI_COMMON=m
CONFIG_HID_GOOGLE_HAMMER=m
CONFIG_HID_VIVALDI=m
CONFIG_HID_GT683R=m
CONFIG_HID_KEYTOUCH=m
CONFIG_HID_KYE=m
CONFIG_HID_UCLOGIC=m
CONFIG_HID_WALTOP=m
CONFIG_HID_VIEWSONIC=m
CONFIG_HID_VRC2=m
CONFIG_HID_XIAOMI=m
CONFIG_HID_GYRATION=m
CONFIG_HID_ICADE=m
CONFIG_HID_ITE=m
CONFIG_HID_JABRA=m
CONFIG_HID_TWINHAN=m
CONFIG_HID_KENSINGTON=m
CONFIG_HID_LCPOWER=m
CONFIG_HID_LED=m
CONFIG_HID_LENOVO=m
CONFIG_HID_LETSKETCH=m
CONFIG_HID_LOGITECH=m
CONFIG_HID_LOGITECH_DJ=m
CONFIG_HID_LOGITECH_HIDPP=m
CONFIG_LOGITECH_FF=y
CONFIG_LOGIRUMBLEPAD2_FF=y
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWHEELS_FF=y
CONFIG_HID_MAGICMOUSE=m
CONFIG_HID_MALTRON=m
CONFIG_HID_MAYFLASH=m
CONFIG_HID_MEGAWORLD_FF=m
CONFIG_HID_REDRAGON=m
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=m
CONFIG_HID_MULTITOUCH=m
CONFIG_HID_NINTENDO=m
CONFIG_NINTENDO_FF=y
CONFIG_HID_NTI=m
CONFIG_HID_NTRIG=m
CONFIG_HID_ORTEK=m
CONFIG_HID_PANTHERLORD=m
CONFIG_PANTHERLORD_FF=y
CONFIG_HID_PENMOUNT=m
CONFIG_HID_PETALYNX=m
CONFIG_HID_PICOLCD=m
CONFIG_HID_PICOLCD_FB=y
CONFIG_HID_PICOLCD_BACKLIGHT=y
CONFIG_HID_PICOLCD_LCD=y
CONFIG_HID_PICOLCD_LEDS=y
CONFIG_HID_PICOLCD_CIR=y
CONFIG_HID_PLANTRONICS=m
CONFIG_HID_PLAYSTATION=m
CONFIG_PLAYSTATION_FF=y
CONFIG_HID_PXRC=m
CONFIG_HID_RAZER=m
CONFIG_HID_PRIMAX=m
CONFIG_HID_RETRODE=m
CONFIG_HID_ROCCAT=m
CONFIG_HID_SAITEK=m
CONFIG_HID_SAMSUNG=m
CONFIG_HID_SEMITEK=m
CONFIG_HID_SIGMAMICRO=m
CONFIG_HID_SONY=m
CONFIG_SONY_FF=y
CONFIG_HID_SPEEDLINK=m
CONFIG_HID_STEAM=m
CONFIG_HID_STEELSERIES=m
CONFIG_HID_SUNPLUS=m
CONFIG_HID_RMI=m
CONFIG_HID_GREENASIA=m
CONFIG_GREENASIA_FF=y
CONFIG_HID_SMARTJOYPLUS=m
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TIVO=m
CONFIG_HID_TOPSEED=m
CONFIG_HID_TOPRE=m
CONFIG_HID_THINGM=m
CONFIG_HID_THRUSTMASTER=m
CONFIG_THRUSTMASTER_FF=y
CONFIG_HID_UDRAW_PS3=m
CONFIG_HID_U2FZERO=m
CONFIG_HID_WACOM=m
CONFIG_HID_WIIMOTE=m
CONFIG_HID_XINMO=m
CONFIG_HID_ZEROPLUS=m
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=m
CONFIG_HID_SENSOR_HUB=m
CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
CONFIG_HID_ALPS=m
CONFIG_HID_MCP2221=m
# end of Special HID drivers

#
# USB HID support
#
CONFIG_USB_HID=m
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y

#
# USB HID Boot Protocol drivers
#
CONFIG_USB_KBD=m
CONFIG_USB_MOUSE=m
# end of USB HID Boot Protocol drivers
# end of USB HID support

#
# I2C HID support
#
CONFIG_I2C_HID_OF=m
CONFIG_I2C_HID_OF_ELAN=m
CONFIG_I2C_HID_OF_GOODIX=m
# end of I2C HID support

CONFIG_I2C_HID_CORE=m
# end of HID support

CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=m
CONFIG_USB_LED_TRIG=y
CONFIG_USB_ULPI_BUS=m
CONFIG_USB_CONN_GPIO=m
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=m
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
CONFIG_USB_FEW_INIT_RETRIES=y
CONFIG_USB_DYNAMIC_MINORS=y
CONFIG_USB_OTG=y
CONFIG_USB_OTG_PRODUCTLIST=y
CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB=y
CONFIG_USB_OTG_FSM=m
CONFIG_USB_LEDS_TRIGGER_USBPORT=m
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_MON=m

#
# USB Host Controller Drivers
#
CONFIG_USB_C67X00_HCD=m
CONFIG_USB_BRCMSTB=m
CONFIG_USB_OXU210HP_HCD=m
CONFIG_USB_ISP116X_HCD=m
CONFIG_USB_ISP1362_HCD=m
CONFIG_USB_MAX3421_HCD=m
CONFIG_USB_U132_HCD=m
CONFIG_USB_SL811_HCD=m
CONFIG_USB_SL811_HCD_ISO=y
CONFIG_USB_SL811_CS=m
CONFIG_USB_R8A66597_HCD=m
CONFIG_USB_RENESAS_USBHS_HCD=m
CONFIG_USB_HCD_TEST_MODE=y
CONFIG_USB_RENESAS_USBHS=m

#
# USB Device Class drivers
#
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=m
CONFIG_USB_TMC=m

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=m
CONFIG_USB_STORAGE_DEBUG=y
CONFIG_USB_STORAGE_REALTEK=m
CONFIG_REALTEK_AUTOPM=y
CONFIG_USB_STORAGE_DATAFAB=m
CONFIG_USB_STORAGE_FREECOM=m
CONFIG_USB_STORAGE_ISD200=m
CONFIG_USB_STORAGE_USBAT=m
CONFIG_USB_STORAGE_SDDR09=m
CONFIG_USB_STORAGE_SDDR55=m
CONFIG_USB_STORAGE_JUMPSHOT=m
CONFIG_USB_STORAGE_ALAUDA=m
CONFIG_USB_STORAGE_ONETOUCH=m
CONFIG_USB_STORAGE_KARMA=m
CONFIG_USB_STORAGE_CYPRESS_ATACB=m
CONFIG_USB_STORAGE_ENE_UB6250=m
CONFIG_USB_UAS=m

#
# USB Imaging devices
#
CONFIG_USB_MDC800=m
CONFIG_USB_MICROTEK=m
CONFIG_USBIP_CORE=m
CONFIG_USBIP_VHCI_HCD=m
CONFIG_USBIP_VHCI_HC_PORTS=8
CONFIG_USBIP_VHCI_NR_HCS=1
CONFIG_USBIP_HOST=m
CONFIG_USBIP_VUDC=m
CONFIG_USBIP_DEBUG=y
CONFIG_USB_MTU3=m
# CONFIG_USB_MTU3_HOST is not set
# CONFIG_USB_MTU3_GADGET is not set
CONFIG_USB_MTU3_DUAL_ROLE=y
CONFIG_USB_MTU3_DEBUG=y
CONFIG_USB_MUSB_HDRC=m
CONFIG_USB_MUSB_HOST=y

#
# Platform Glue Layer
#
CONFIG_USB_MUSB_TUSB6010=m
CONFIG_USB_MUSB_DSPS=m
CONFIG_USB_MUSB_UX500=m
CONFIG_USB_MUSB_MEDIATEK=m
CONFIG_USB_MUSB_POLARFIRE_SOC=m

#
# MUSB DMA mode
#
CONFIG_MUSB_PIO_ONLY=y
CONFIG_USB_ISP1760=m
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_ISP1761_UDC=y
# CONFIG_USB_ISP1760_HOST_ROLE is not set
# CONFIG_USB_ISP1760_GADGET_ROLE is not set
CONFIG_USB_ISP1760_DUAL_ROLE=y

#
# USB port drivers
#
CONFIG_USB_USS720=m
CONFIG_USB_SERIAL=m
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=m
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=m
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
CONFIG_USB_SERIAL_CP210X=m
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=m
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=m
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_F81232=m
CONFIG_USB_SERIAL_F8153X=m
CONFIG_USB_SERIAL_GARMIN=m
CONFIG_USB_SERIAL_IPW=m
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_METRO=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7715_PARPORT=y
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_MXUPORT=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=m
CONFIG_USB_SERIAL_OTI6858=m
CONFIG_USB_SERIAL_QCAUX=m
CONFIG_USB_SERIAL_QUALCOMM=m
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_SAFE=m
CONFIG_USB_SERIAL_SAFE_PADDED=y
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
CONFIG_USB_SERIAL_SYMBOL=m
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
CONFIG_USB_SERIAL_WWAN=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=m
CONFIG_USB_SERIAL_XSENS_MT=m
CONFIG_USB_SERIAL_WISHBONE=m
CONFIG_USB_SERIAL_SSU100=m
CONFIG_USB_SERIAL_QT2=m
CONFIG_USB_SERIAL_UPD78F0730=m
CONFIG_USB_SERIAL_XR=m
CONFIG_USB_SERIAL_DEBUG=m

#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=m
CONFIG_USB_LEGOTOWER=m
CONFIG_USB_LCD=m
CONFIG_USB_CYPRESS_CY7C63=m
CONFIG_USB_CYTHERM=m
CONFIG_USB_IDMOUSE=m
CONFIG_USB_FTDI_ELAN=m
CONFIG_USB_APPLEDISPLAY=m
CONFIG_USB_QCOM_EUD=m
CONFIG_APPLE_MFI_FASTCHARGE=m
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_LD=m
CONFIG_USB_TRANCEVIBRATOR=m
CONFIG_USB_IOWARRIOR=m
CONFIG_USB_TEST=m
CONFIG_USB_EHSET_TEST_FIXTURE=m
CONFIG_USB_ISIGHTFW=m
CONFIG_USB_YUREX=m
CONFIG_USB_EZUSB_FX2=m
CONFIG_USB_HUB_USB251XB=m
CONFIG_USB_HSIC_USB3503=m
CONFIG_USB_HSIC_USB4604=m
CONFIG_USB_LINK_LAYER_TEST=m
CONFIG_USB_CHAOSKEY=m
CONFIG_BRCM_USB_PINMAP=m
CONFIG_USB_ONBOARD_HUB=m
CONFIG_USB_ATM=m
CONFIG_USB_SPEEDTOUCH=m
CONFIG_USB_CXACRU=m
CONFIG_USB_UEAGLEATM=m
CONFIG_USB_XUSBATM=m

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_KEYSTONE_USB_PHY=m
CONFIG_NOP_USB_XCEIV=m
CONFIG_AM335X_CONTROL_USB=m
CONFIG_AM335X_PHY_USB=m
CONFIG_USB_GPIO_VBUS=m
CONFIG_TAHVO_USB=m
CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y
CONFIG_USB_ISP1301=m
CONFIG_USB_TEGRA_PHY=m
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_JZ4770_PHY=m
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=m
CONFIG_USB_GADGET_DEBUG=y
CONFIG_USB_GADGET_VERBOSE=y
CONFIG_USB_GADGET_DEBUG_FILES=y
CONFIG_USB_GADGET_DEBUG_FS=y
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
CONFIG_U_SERIAL_CONSOLE=y

#
# USB Peripheral Controller
#
CONFIG_USB_LPC32XX=m
CONFIG_USB_RENESAS_USBHS_UDC=m
CONFIG_USB_RENESAS_USB3=m
CONFIG_USB_PXA27X=m
CONFIG_USB_M66592=m
CONFIG_USB_NET2272=m
CONFIG_USB_MAX3420_UDC=m
CONFIG_USB_ASPEED_UDC=m
CONFIG_USB_ASPEED_VHUB=m
CONFIG_USB_DUMMY_HCD=m
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=m
CONFIG_USB_F_ACM=m
CONFIG_USB_F_SS_LB=m
CONFIG_USB_U_SERIAL=m
CONFIG_USB_U_ETHER=m
CONFIG_USB_U_AUDIO=m
CONFIG_USB_F_SERIAL=m
CONFIG_USB_F_OBEX=m
CONFIG_USB_F_NCM=m
CONFIG_USB_F_ECM=m
CONFIG_USB_F_PHONET=m
CONFIG_USB_F_EEM=m
CONFIG_USB_F_SUBSET=m
CONFIG_USB_F_RNDIS=m
CONFIG_USB_F_MASS_STORAGE=m
CONFIG_USB_F_FS=m
CONFIG_USB_F_UAC1=m
CONFIG_USB_F_UAC1_LEGACY=m
CONFIG_USB_F_UAC2=m
CONFIG_USB_F_UVC=m
CONFIG_USB_F_MIDI=m
CONFIG_USB_F_HID=m
CONFIG_USB_F_PRINTER=m
CONFIG_USB_F_TCM=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
CONFIG_USB_CONFIGFS_NCM=y
CONFIG_USB_CONFIGFS_ECM=y
CONFIG_USB_CONFIGFS_ECM_SUBSET=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_EEM=y
CONFIG_USB_CONFIGFS_PHONET=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_LB_SS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_MIDI=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_F_PRINTER=y
CONFIG_USB_CONFIGFS_F_TCM=y

#
# USB Gadget precomposed configurations
#
CONFIG_USB_ZERO=m
CONFIG_USB_ZERO_HNPTEST=y
CONFIG_USB_AUDIO=m
CONFIG_GADGET_UAC1=y
CONFIG_GADGET_UAC1_LEGACY=y
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
CONFIG_USB_ETH_EEM=y
CONFIG_USB_G_NCM=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_FUNCTIONFS=m
CONFIG_USB_FUNCTIONFS_ETH=y
CONFIG_USB_FUNCTIONFS_RNDIS=y
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_GADGET_TARGET=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_NOKIA=m
CONFIG_USB_G_ACM_MS=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_RNDIS=y
CONFIG_USB_G_MULTI_CDC=y
CONFIG_USB_G_HID=m
CONFIG_USB_G_DBGP=m
# CONFIG_USB_G_DBGP_PRINTK is not set
CONFIG_USB_G_DBGP_SERIAL=y
CONFIG_USB_G_WEBCAM=m
CONFIG_USB_RAW_GADGET=m
# end of USB Gadget precomposed configurations

CONFIG_TYPEC=m
CONFIG_TYPEC_TCPM=m
CONFIG_TYPEC_TCPCI=m
CONFIG_TYPEC_RT1711H=m
CONFIG_TYPEC_MT6360=m
CONFIG_TYPEC_TCPCI_MT6370=m
CONFIG_TYPEC_TCPCI_MAXIM=m
CONFIG_TYPEC_FUSB302=m
CONFIG_TYPEC_UCSI=m
CONFIG_UCSI_CCG=m
CONFIG_UCSI_STM32G0=m
CONFIG_TYPEC_TPS6598X=m
CONFIG_TYPEC_ANX7411=m
CONFIG_TYPEC_RT1719=m
CONFIG_TYPEC_HD3SS3220=m
CONFIG_TYPEC_STUSB160X=m
CONFIG_TYPEC_QCOM_PMIC=m
CONFIG_TYPEC_WUSB3801=m

#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
CONFIG_TYPEC_MUX_FSA4480=m
CONFIG_TYPEC_MUX_PI3USB30532=m
# end of USB Type-C Multiplexer/DeMultiplexer Switch support

#
# USB Type-C Alternate Mode drivers
#
# end of USB Type-C Alternate Mode drivers

CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=m
CONFIG_PWRSEQ_EMMC=m
CONFIG_PWRSEQ_SD8787=m
CONFIG_PWRSEQ_SIMPLE=m
CONFIG_MMC_BLOCK=m
CONFIG_MMC_BLOCK_MINORS=8
CONFIG_SDIO_UART=m
CONFIG_MMC_TEST=m
CONFIG_MMC_CRYPTO=y

#
# MMC/SD/SDIO Host Controller Drivers
#
CONFIG_MMC_DEBUG=y
CONFIG_MMC_MOXART=m
CONFIG_MMC_OMAP_HS=m
CONFIG_MMC_DAVINCI=m
CONFIG_MMC_SPI=m
CONFIG_MMC_S3C=m
CONFIG_MMC_S3C_HW_SDIO_IRQ=y
CONFIG_MMC_S3C_PIO=y
# CONFIG_MMC_S3C_DMA is not set
CONFIG_MMC_TMIO_CORE=m
CONFIG_MMC_TMIO=m
CONFIG_MMC_SDHI=m
CONFIG_MMC_SDHI_SYS_DMAC=m
CONFIG_MMC_SDHI_INTERNAL_DMAC=m
CONFIG_MMC_UNIPHIER=m
CONFIG_MMC_DW=m
CONFIG_MMC_DW_PLTFM=m
CONFIG_MMC_DW_BLUEFIELD=m
CONFIG_MMC_DW_EXYNOS=m
CONFIG_MMC_DW_HI3798CV200=m
CONFIG_MMC_DW_K3=m
CONFIG_MMC_SH_MMCIF=m
CONFIG_MMC_VUB300=m
CONFIG_MMC_USHC=m
CONFIG_MMC_REALTEK_USB=m
CONFIG_MMC_HSQ=m
CONFIG_MMC_BCM2835=m
CONFIG_MMC_LITEX=m
CONFIG_MEMSTICK=m
CONFIG_MEMSTICK_DEBUG=y

#
# MemoryStick drivers
#
CONFIG_MEMSTICK_UNSAFE_RESUME=y
CONFIG_MSPRO_BLOCK=m
CONFIG_MS_BLOCK=m

#
# MemoryStick Host Controller Drivers
#
CONFIG_MEMSTICK_REALTEK_USB=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m
CONFIG_LEDS_CLASS_FLASH=m
CONFIG_LEDS_CLASS_MULTICOLOR=m
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y

#
# LED drivers
#
CONFIG_LEDS_AN30259A=m
CONFIG_LEDS_ARIEL=m
CONFIG_LEDS_AW2013=m
CONFIG_LEDS_BCM6328=m
CONFIG_LEDS_BCM6358=m
CONFIG_LEDS_CPCAP=m
CONFIG_LEDS_CR0014114=m
CONFIG_LEDS_EL15203000=m
CONFIG_LEDS_TURRIS_OMNIA=m
CONFIG_LEDS_LM3530=m
CONFIG_LEDS_LM3532=m
CONFIG_LEDS_LM3533=m
CONFIG_LEDS_LM3642=m
CONFIG_LEDS_LM3692X=m
CONFIG_LEDS_MT6323=m
CONFIG_LEDS_S3C24XX=m
CONFIG_LEDS_COBALT_QUBE=m
CONFIG_LEDS_PCA9532=m
CONFIG_LEDS_PCA9532_GPIO=y
CONFIG_LEDS_GPIO=m
CONFIG_LEDS_LP3944=m
CONFIG_LEDS_LP3952=m
CONFIG_LEDS_LP50XX=m
CONFIG_LEDS_LP55XX_COMMON=m
CONFIG_LEDS_LP5521=m
CONFIG_LEDS_LP5523=m
CONFIG_LEDS_LP5562=m
CONFIG_LEDS_LP8501=m
CONFIG_LEDS_LP8860=m
CONFIG_LEDS_PCA955X=m
CONFIG_LEDS_PCA955X_GPIO=y
CONFIG_LEDS_PCA963X=m
CONFIG_LEDS_WM831X_STATUS=m
CONFIG_LEDS_DA9052=m
CONFIG_LEDS_DAC124S085=m
CONFIG_LEDS_PWM=m
CONFIG_LEDS_REGULATOR=m
CONFIG_LEDS_BD2802=m
CONFIG_LEDS_LT3593=m
CONFIG_LEDS_MC13783=m
CONFIG_LEDS_NS2=m
CONFIG_LEDS_NETXBIG=m
CONFIG_LEDS_TCA6507=m
CONFIG_LEDS_TLC591XX=m
CONFIG_LEDS_MAX77650=m
CONFIG_LEDS_LM355x=m
CONFIG_LEDS_OT200=m
CONFIG_LEDS_MENF21BMC=m
CONFIG_LEDS_IS31FL319X=m
CONFIG_LEDS_IS31FL32XX=m
CONFIG_LEDS_SC27XX_BLTC=m

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
CONFIG_LEDS_BLINKM=m
CONFIG_LEDS_PM8058=m
CONFIG_LEDS_MLXREG=m
CONFIG_LEDS_USER=m
CONFIG_LEDS_SPI_BYTE=m
CONFIG_LEDS_TI_LMU_COMMON=m
CONFIG_LEDS_LM3697=m
CONFIG_LEDS_LM36274=m
CONFIG_LEDS_TPS6105X=m
CONFIG_LEDS_IP30=m
CONFIG_LEDS_ACER_A500=m
CONFIG_LEDS_BCM63138=m
CONFIG_LEDS_LGM=m

#
# Flash and Torch LED drivers
#
CONFIG_LEDS_AAT1290=m
CONFIG_LEDS_AS3645A=m
CONFIG_LEDS_KTD2692=m
CONFIG_LEDS_LM3601X=m
CONFIG_LEDS_MAX77693=m
CONFIG_LEDS_MT6360=m
CONFIG_LEDS_RT4505=m
CONFIG_LEDS_RT8515=m
CONFIG_LEDS_SGM3140=m

#
# RGB LED drivers
#
CONFIG_LEDS_PWM_MULTICOLOR=m
CONFIG_LEDS_QCOM_LPG=m

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=m
CONFIG_LEDS_TRIGGER_ONESHOT=m
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=m
CONFIG_LEDS_TRIGGER_BACKLIGHT=m
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_ACTIVITY=m
CONFIG_LEDS_TRIGGER_GPIO=m
CONFIG_LEDS_TRIGGER_DEFAULT_ON=m

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=m
CONFIG_LEDS_TRIGGER_CAMERA=m
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_NETDEV=m
CONFIG_LEDS_TRIGGER_PATTERN=m
CONFIG_LEDS_TRIGGER_AUDIO=m
CONFIG_LEDS_TRIGGER_TTY=m

#
# Simple LED drivers
#
CONFIG_ACCESSIBILITY=y
CONFIG_A11Y_BRAILLE_CONSOLE=y

#
# Speakup console speech
#
CONFIG_SPEAKUP=m
CONFIG_SPEAKUP_SERIALIO=y
CONFIG_SPEAKUP_SYNTH_ACNTSA=m
CONFIG_SPEAKUP_SYNTH_ACNTPC=m
CONFIG_SPEAKUP_SYNTH_APOLLO=m
CONFIG_SPEAKUP_SYNTH_AUDPTR=m
CONFIG_SPEAKUP_SYNTH_BNS=m
CONFIG_SPEAKUP_SYNTH_DECTLK=m
CONFIG_SPEAKUP_SYNTH_DECEXT=m
CONFIG_SPEAKUP_SYNTH_DECPC=m
CONFIG_SPEAKUP_SYNTH_DTLK=m
CONFIG_SPEAKUP_SYNTH_KEYPC=m
CONFIG_SPEAKUP_SYNTH_LTLK=m
CONFIG_SPEAKUP_SYNTH_SOFT=m
CONFIG_SPEAKUP_SYNTH_SPKOUT=m
CONFIG_SPEAKUP_SYNTH_TXPRT=m
CONFIG_SPEAKUP_SYNTH_DUMMY=m
# end of Speakup console speech

CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
CONFIG_RTC_DEBUG=y
CONFIG_RTC_LIB_KUNIT_TEST=m
CONFIG_RTC_NVMEM=y

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
CONFIG_RTC_DRV_TEST=m

#
# I2C RTC drivers
#
CONFIG_RTC_DRV_88PM80X=m
CONFIG_RTC_DRV_ABB5ZES3=m
CONFIG_RTC_DRV_ABEOZ9=m
CONFIG_RTC_DRV_ABX80X=m
CONFIG_RTC_DRV_BRCMSTB=m
CONFIG_RTC_DRV_DS1307=m
CONFIG_RTC_DRV_DS1307_CENTURY=y
CONFIG_RTC_DRV_DS1374=m
CONFIG_RTC_DRV_DS1374_WDT=y
CONFIG_RTC_DRV_DS1672=m
CONFIG_RTC_DRV_HYM8563=m
CONFIG_RTC_DRV_MAX6900=m
CONFIG_RTC_DRV_MAX8907=m
CONFIG_RTC_DRV_MAX77686=m
CONFIG_RTC_DRV_NCT3018Y=m
CONFIG_RTC_DRV_RK808=m
CONFIG_RTC_DRV_RS5C372=m
CONFIG_RTC_DRV_ISL1208=m
CONFIG_RTC_DRV_ISL12022=m
CONFIG_RTC_DRV_ISL12026=m
CONFIG_RTC_DRV_X1205=m
CONFIG_RTC_DRV_PCF8523=m
CONFIG_RTC_DRV_PCF85063=m
CONFIG_RTC_DRV_PCF85363=m
CONFIG_RTC_DRV_PCF8563=m
CONFIG_RTC_DRV_PCF8583=m
CONFIG_RTC_DRV_M41T80=m
CONFIG_RTC_DRV_M41T80_WDT=y
CONFIG_RTC_DRV_BQ32K=m
CONFIG_RTC_DRV_RC5T619=m
CONFIG_RTC_DRV_S35390A=m
CONFIG_RTC_DRV_FM3130=m
CONFIG_RTC_DRV_RX8010=m
CONFIG_RTC_DRV_RX8581=m
CONFIG_RTC_DRV_RX8025=m
CONFIG_RTC_DRV_EM3027=m
CONFIG_RTC_DRV_RV3028=m
CONFIG_RTC_DRV_RV3032=m
CONFIG_RTC_DRV_RV8803=m
CONFIG_RTC_DRV_S5M=m
CONFIG_RTC_DRV_SD3078=m

#
# SPI RTC drivers
#
CONFIG_RTC_DRV_M41T93=m
CONFIG_RTC_DRV_M41T94=m
CONFIG_RTC_DRV_DS1302=m
CONFIG_RTC_DRV_DS1305=m
CONFIG_RTC_DRV_DS1343=m
CONFIG_RTC_DRV_DS1347=m
CONFIG_RTC_DRV_DS1390=m
CONFIG_RTC_DRV_MAX6916=m
CONFIG_RTC_DRV_R9701=m
CONFIG_RTC_DRV_RX4581=m
CONFIG_RTC_DRV_RS5C348=m
CONFIG_RTC_DRV_MAX6902=m
CONFIG_RTC_DRV_PCF2123=m
CONFIG_RTC_DRV_MCP795=m
CONFIG_RTC_I2C_AND_SPI=m

#
# SPI and I2C RTC drivers
#
CONFIG_RTC_DRV_DS3232=m
CONFIG_RTC_DRV_DS3232_HWMON=y
CONFIG_RTC_DRV_PCF2127=m
CONFIG_RTC_DRV_RV3029C2=m
CONFIG_RTC_DRV_RV3029_HWMON=y
CONFIG_RTC_DRV_RX6110=m

#
# Platform RTC drivers
#
CONFIG_RTC_DRV_DS1286=m
CONFIG_RTC_DRV_DS1511=m
CONFIG_RTC_DRV_DS1553=m
CONFIG_RTC_DRV_DS1685_FAMILY=m
CONFIG_RTC_DRV_DS1685=y
# CONFIG_RTC_DRV_DS1689 is not set
# CONFIG_RTC_DRV_DS17285 is not set
# CONFIG_RTC_DRV_DS17485 is not set
# CONFIG_RTC_DRV_DS17885 is not set
CONFIG_RTC_DRV_DS1742=m
CONFIG_RTC_DRV_DS2404=m
CONFIG_RTC_DRV_DA9052=m
CONFIG_RTC_DRV_DA9063=m
CONFIG_RTC_DRV_STK17TA8=m
CONFIG_RTC_DRV_M48T86=m
CONFIG_RTC_DRV_M48T35=m
CONFIG_RTC_DRV_M48T59=m
CONFIG_RTC_DRV_MSM6242=m
CONFIG_RTC_DRV_BQ4802=m
CONFIG_RTC_DRV_RP5C01=m
CONFIG_RTC_DRV_V3020=m
CONFIG_RTC_DRV_GAMECUBE=m
CONFIG_RTC_DRV_WM831X=m
CONFIG_RTC_DRV_SC27XX=m
CONFIG_RTC_DRV_SPEAR=m
CONFIG_RTC_DRV_PCF50633=m
CONFIG_RTC_DRV_ZYNQMP=m
CONFIG_RTC_DRV_CROS_EC=m
CONFIG_RTC_DRV_NTXEC=m

#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_ASM9260=m
CONFIG_RTC_DRV_DAVINCI=m
CONFIG_RTC_DRV_DIGICOLOR=m
CONFIG_RTC_DRV_FSL_FTM_ALARM=m
CONFIG_RTC_DRV_MESON=m
CONFIG_RTC_DRV_MESON_VRTC=m
CONFIG_RTC_DRV_OMAP=m
CONFIG_RTC_DRV_S3C=m
CONFIG_RTC_DRV_EP93XX=m
CONFIG_RTC_DRV_SH=m
CONFIG_RTC_DRV_AT91RM9200=m
CONFIG_RTC_DRV_AT91SAM9=m
CONFIG_RTC_DRV_RZN1=m
CONFIG_RTC_DRV_GENERIC=m
CONFIG_RTC_DRV_VT8500=m
CONFIG_RTC_DRV_SUNXI=m
CONFIG_RTC_DRV_MV=m
CONFIG_RTC_DRV_ARMADA38X=m
CONFIG_RTC_DRV_CADENCE=m
CONFIG_RTC_DRV_FTRTC010=m
CONFIG_RTC_DRV_STMP=m
CONFIG_RTC_DRV_PCAP=m
CONFIG_RTC_DRV_MC13XXX=m
CONFIG_RTC_DRV_JZ4740=m
CONFIG_RTC_DRV_LPC24XX=m
CONFIG_RTC_DRV_LPC32XX=m
CONFIG_RTC_DRV_PM8XXX=m
CONFIG_RTC_DRV_TEGRA=m
CONFIG_RTC_DRV_MXC=m
CONFIG_RTC_DRV_MXC_V2=m
CONFIG_RTC_DRV_SNVS=m
CONFIG_RTC_DRV_MOXART=m
CONFIG_RTC_DRV_MT2712=m
CONFIG_RTC_DRV_MT6397=m
CONFIG_RTC_DRV_MT7622=m
CONFIG_RTC_DRV_XGENE=m
CONFIG_RTC_DRV_R7301=m
CONFIG_RTC_DRV_STM32=m
CONFIG_RTC_DRV_CPCAP=m
CONFIG_RTC_DRV_RTD119X=y
CONFIG_RTC_DRV_ASPEED=m
CONFIG_RTC_DRV_TI_K3=m

#
# HID Sensor RTC drivers
#
CONFIG_RTC_DRV_HID_SENSOR_TIME=m
CONFIG_RTC_DRV_GOLDFISH=m
CONFIG_RTC_DRV_MSC313=m

#
# DMABUF options
#
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
CONFIG_UDMABUF=y
CONFIG_DMABUF_MOVE_NOTIFY=y
CONFIG_DMABUF_DEBUG=y
CONFIG_DMABUF_SELFTESTS=m
CONFIG_DMABUF_HEAPS=y
CONFIG_DMABUF_SYSFS_STATS=y
CONFIG_DMABUF_HEAPS_SYSTEM=y
# end of DMABUF options

CONFIG_AUXDISPLAY=y
CONFIG_CHARLCD=m
CONFIG_LINEDISP=m
CONFIG_HD44780_COMMON=m
CONFIG_HD44780=m
CONFIG_KS0108=m
CONFIG_KS0108_PORT=0x378
CONFIG_KS0108_DELAY=2
CONFIG_IMG_ASCII_LCD=m
CONFIG_HT16K33=m
CONFIG_LCD2S=m
CONFIG_PARPORT_PANEL=m
CONFIG_PANEL_PARPORT=0
CONFIG_PANEL_PROFILE=5
CONFIG_PANEL_CHANGE_MESSAGE=y
CONFIG_PANEL_BOOT_MESSAGE=""
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_PANEL=m
CONFIG_VFIO=m
CONFIG_VFIO_VIRQFD=m
CONFIG_VFIO_NOIOMMU=y
CONFIG_VFIO_PLATFORM=m
CONFIG_VFIO_AMBA=m
CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET=m
CONFIG_VFIO_PLATFORM_AMDXGBE_RESET=m
CONFIG_VFIO_PLATFORM_BCMFLEXRM_RESET=m
CONFIG_VFIO_MDEV=m
CONFIG_IRQ_BYPASS_MANAGER=m
CONFIG_VIRT_DRIVERS=y
CONFIG_VIRTIO_ANCHOR=y
CONFIG_VIRTIO=m
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_VDPA=m
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VDPA=m
CONFIG_VHOST_IOTLB=m
CONFIG_VHOST=m
CONFIG_VHOST_MENU=y
CONFIG_VHOST_NET=m
CONFIG_VHOST_SCSI=m
CONFIG_VHOST_VSOCK=m
CONFIG_VHOST_VDPA=m
CONFIG_VHOST_CROSS_ENDIAN_LEGACY=y

#
# Microsoft Hyper-V guest support
#
# end of Microsoft Hyper-V guest support

CONFIG_GREYBUS=m
CONFIG_GREYBUS_ES2=m
CONFIG_COMEDI=m
CONFIG_COMEDI_DEBUG=y
CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
CONFIG_COMEDI_MISC_DRIVERS=y
CONFIG_COMEDI_BOND=m
CONFIG_COMEDI_TEST=m
CONFIG_COMEDI_PARPORT=m
CONFIG_COMEDI_SSV_DNP=m
CONFIG_COMEDI_ISA_DRIVERS=y
CONFIG_COMEDI_PCL711=m
CONFIG_COMEDI_PCL724=m
CONFIG_COMEDI_PCL726=m
CONFIG_COMEDI_PCL730=m
CONFIG_COMEDI_PCL812=m
CONFIG_COMEDI_PCL816=m
CONFIG_COMEDI_PCL818=m
CONFIG_COMEDI_PCM3724=m
CONFIG_COMEDI_AMPLC_DIO200_ISA=m
CONFIG_COMEDI_AMPLC_PC236_ISA=m
CONFIG_COMEDI_AMPLC_PC263_ISA=m
CONFIG_COMEDI_RTI800=m
CONFIG_COMEDI_RTI802=m
CONFIG_COMEDI_DAC02=m
CONFIG_COMEDI_DAS16M1=m
CONFIG_COMEDI_DAS08_ISA=m
CONFIG_COMEDI_DAS16=m
CONFIG_COMEDI_DAS800=m
CONFIG_COMEDI_DAS1800=m
CONFIG_COMEDI_DAS6402=m
CONFIG_COMEDI_DT2801=m
CONFIG_COMEDI_DT2811=m
CONFIG_COMEDI_DT2814=m
CONFIG_COMEDI_DT2815=m
CONFIG_COMEDI_DT2817=m
CONFIG_COMEDI_DT282X=m
CONFIG_COMEDI_DMM32AT=m
CONFIG_COMEDI_FL512=m
CONFIG_COMEDI_AIO_AIO12_8=m
CONFIG_COMEDI_AIO_IIRO_16=m
CONFIG_COMEDI_II_PCI20KC=m
CONFIG_COMEDI_C6XDIGIO=m
CONFIG_COMEDI_MPC624=m
CONFIG_COMEDI_ADQ12B=m
CONFIG_COMEDI_NI_AT_A2150=m
CONFIG_COMEDI_NI_AT_AO=m
CONFIG_COMEDI_NI_ATMIO=m
CONFIG_COMEDI_NI_ATMIO16D=m
CONFIG_COMEDI_NI_LABPC_ISA=m
CONFIG_COMEDI_PCMAD=m
CONFIG_COMEDI_PCMDA12=m
CONFIG_COMEDI_PCMMIO=m
CONFIG_COMEDI_PCMUIO=m
CONFIG_COMEDI_MULTIQ3=m
CONFIG_COMEDI_S526=m
CONFIG_COMEDI_PCMCIA_DRIVERS=m
CONFIG_COMEDI_CB_DAS16_CS=m
CONFIG_COMEDI_DAS08_CS=m
CONFIG_COMEDI_NI_DAQ_700_CS=m
CONFIG_COMEDI_NI_DAQ_DIO24_CS=m
CONFIG_COMEDI_NI_LABPC_CS=m
CONFIG_COMEDI_NI_MIO_CS=m
CONFIG_COMEDI_QUATECH_DAQP_CS=m
CONFIG_COMEDI_USB_DRIVERS=m
CONFIG_COMEDI_DT9812=m
CONFIG_COMEDI_NI_USB6501=m
CONFIG_COMEDI_USBDUX=m
CONFIG_COMEDI_USBDUXFAST=m
CONFIG_COMEDI_USBDUXSIGMA=m
CONFIG_COMEDI_VMK80XX=m
CONFIG_COMEDI_8254=m
CONFIG_COMEDI_8255=m
CONFIG_COMEDI_8255_SA=m
CONFIG_COMEDI_KCOMEDILIB=m
CONFIG_COMEDI_AMPLC_DIO200=m
CONFIG_COMEDI_AMPLC_PC236=m
CONFIG_COMEDI_DAS08=m
CONFIG_COMEDI_NI_LABPC=m
CONFIG_COMEDI_NI_TIO=m
CONFIG_COMEDI_NI_ROUTING=m
CONFIG_COMEDI_TESTS=m
CONFIG_COMEDI_TESTS_EXAMPLE=m
CONFIG_COMEDI_TESTS_NI_ROUTES=m
CONFIG_STAGING=y
CONFIG_PRISM2_USB=m
CONFIG_RTLLIB=m
CONFIG_RTLLIB_CRYPTO_CCMP=m
CONFIG_RTLLIB_CRYPTO_TKIP=m
CONFIG_RTLLIB_CRYPTO_WEP=m
CONFIG_RTL8723BS=m
CONFIG_R8712U=m
CONFIG_R8188EU=m
CONFIG_OCTEON_ETHERNET=m
CONFIG_VT6656=m

#
# IIO staging drivers
#

#
# Accelerometers
#
CONFIG_ADIS16203=m
CONFIG_ADIS16240=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD7816=m
# end of Analog to digital converters

#
# Analog digital bi-direction converters
#
CONFIG_ADT7316=m
CONFIG_ADT7316_SPI=m
CONFIG_ADT7316_I2C=m
# end of Analog digital bi-direction converters

#
# Direct Digital Synthesis
#
CONFIG_AD9832=m
CONFIG_AD9834=m
# end of Direct Digital Synthesis

#
# Network Analyzer, Impedance Converters
#
CONFIG_AD5933=m
# end of Network Analyzer, Impedance Converters

#
# Active energy metering IC
#
CONFIG_ADE7854=m
CONFIG_ADE7854_I2C=m
CONFIG_ADE7854_SPI=m
# end of Active energy metering IC

#
# Resolver to digital converters
#
CONFIG_AD2S1210=m
# end of Resolver to digital converters
# end of IIO staging drivers

CONFIG_USB_EMXX=m
CONFIG_STAGING_MEDIA=y
CONFIG_VIDEO_MAX96712=m
CONFIG_VIDEO_OMAP4=m
CONFIG_VIDEO_ROCKCHIP_VDEC=m
CONFIG_VIDEO_SUNXI=y
CONFIG_STAGING_MEDIA_DEPRECATED=y
CONFIG_VIDEO_CPIA2=m
CONFIG_VIDEO_VIU=m
CONFIG_VIDEO_STKWEBCAM=m
CONFIG_VIDEO_TM6000=m
CONFIG_VIDEO_TM6000_ALSA=m
CONFIG_VIDEO_TM6000_DVB=m
CONFIG_VIDEO_DM6446_CCDC=m
CONFIG_VIDEO_DM355_CCDC=m
CONFIG_VIDEO_DM365_ISIF=m
CONFIG_USB_ZR364XX=m
CONFIG_STAGING_BOARD=y
CONFIG_LTE_GDM724X=m
CONFIG_FB_TFT=m
CONFIG_FB_TFT_AGM1264K_FL=m
CONFIG_FB_TFT_BD663474=m
CONFIG_FB_TFT_HX8340BN=m
CONFIG_FB_TFT_HX8347D=m
CONFIG_FB_TFT_HX8353D=m
CONFIG_FB_TFT_HX8357D=m
CONFIG_FB_TFT_ILI9163=m
CONFIG_FB_TFT_ILI9320=m
CONFIG_FB_TFT_ILI9325=m
CONFIG_FB_TFT_ILI9340=m
CONFIG_FB_TFT_ILI9341=m
CONFIG_FB_TFT_ILI9481=m
CONFIG_FB_TFT_ILI9486=m
CONFIG_FB_TFT_PCD8544=m
CONFIG_FB_TFT_RA8875=m
CONFIG_FB_TFT_S6D02A1=m
CONFIG_FB_TFT_S6D1121=m
CONFIG_FB_TFT_SEPS525=m
CONFIG_FB_TFT_SH1106=m
CONFIG_FB_TFT_SSD1289=m
CONFIG_FB_TFT_SSD1305=m
CONFIG_FB_TFT_SSD1306=m
CONFIG_FB_TFT_SSD1331=m
CONFIG_FB_TFT_SSD1351=m
CONFIG_FB_TFT_ST7735R=m
CONFIG_FB_TFT_ST7789V=m
CONFIG_FB_TFT_TINYLCD=m
CONFIG_FB_TFT_TLS8204=m
CONFIG_FB_TFT_UC1611=m
CONFIG_FB_TFT_UC1701=m
CONFIG_FB_TFT_UPD161704=m
CONFIG_KS7010=m
CONFIG_GREYBUS_AUDIO=m
CONFIG_GREYBUS_AUDIO_APB_CODEC=m
CONFIG_GREYBUS_BOOTROM=m
CONFIG_GREYBUS_FIRMWARE=m
CONFIG_GREYBUS_HID=m
CONFIG_GREYBUS_LIGHT=m
CONFIG_GREYBUS_LOG=m
CONFIG_GREYBUS_LOOPBACK=m
CONFIG_GREYBUS_POWER=m
CONFIG_GREYBUS_RAW=m
CONFIG_GREYBUS_VIBRATOR=m
CONFIG_GREYBUS_BRIDGED_PHY=m
CONFIG_GREYBUS_GPIO=m
CONFIG_GREYBUS_I2C=m
CONFIG_GREYBUS_PWM=m
CONFIG_GREYBUS_SDIO=m
CONFIG_GREYBUS_SPI=m
CONFIG_GREYBUS_UART=m
CONFIG_GREYBUS_USB=m
CONFIG_GREYBUS_ARCHE=m
CONFIG_BCM_VIDEOCORE=m
CONFIG_SND_BCM2835=m
CONFIG_VIDEO_BCM2835=m
CONFIG_PI433=m
CONFIG_XIL_AXIS_FIFO=m
CONFIG_FIELDBUS_DEV=m
CONFIG_HMS_ANYBUSS_BUS=m
CONFIG_ARCX_ANYBUS_CONTROLLER=m
CONFIG_HMS_PROFINET=m
CONFIG_CHROME_PLATFORMS=y
CONFIG_CROS_EC=m
CONFIG_CROS_EC_I2C=m
CONFIG_CROS_EC_RPMSG=m
CONFIG_CROS_EC_SPI=m
CONFIG_CROS_EC_PROTO=y
CONFIG_CROS_KBD_LED_BACKLIGHT=m
CONFIG_CROS_EC_CHARDEV=m
CONFIG_CROS_EC_LIGHTBAR=m
CONFIG_CROS_EC_VBC=m
CONFIG_CROS_EC_DEBUGFS=m
CONFIG_CROS_EC_SENSORHUB=m
CONFIG_CROS_EC_SYSFS=m
CONFIG_CROS_EC_TYPEC=m
CONFIG_CROS_USBPD_LOGGER=m
CONFIG_CROS_USBPD_NOTIFY=m
CONFIG_CROS_KUNIT=m
CONFIG_MELLANOX_PLATFORM=y
CONFIG_MLXREG_HOTPLUG=m
CONFIG_MLXREG_IO=m
CONFIG_MLXREG_LC=m
CONFIG_NVSW_SN2201=m
CONFIG_OLPC_EC=y
CONFIG_OLPC_XO175=y
CONFIG_OLPC_XO175_EC=m
CONFIG_SURFACE_PLATFORMS=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_LEGACY_CLK=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_OMAP=m
CONFIG_HWSPINLOCK_QCOM=m
CONFIG_HWSPINLOCK_SPRD=m
CONFIG_HWSPINLOCK_STM32=m
CONFIG_HWSPINLOCK_SUN6I=m
CONFIG_HSEM_U8500=m

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_BCM2835_TIMER=y
CONFIG_BCM_KONA_TIMER=y
CONFIG_DAVINCI_TIMER=y
CONFIG_DIGICOLOR_TIMER=y
CONFIG_OMAP_DM_TIMER=y
CONFIG_DW_APB_TIMER=y
CONFIG_FTTMR010_TIMER=y
CONFIG_IXP4XX_TIMER=y
CONFIG_MESON6_TIMER=y
CONFIG_OWL_TIMER=y
CONFIG_RDA_TIMER=y
CONFIG_SUN4I_TIMER=y
CONFIG_TEGRA_TIMER=y
CONFIG_TEGRA186_TIMER=y
CONFIG_VT8500_TIMER=y
CONFIG_NPCM7XX_TIMER=y
CONFIG_ASM9260_TIMER=y
CONFIG_CLKSRC_DBX500_PRCMU=y
CONFIG_CLPS711X_TIMER=y
CONFIG_MXS_TIMER=y
CONFIG_NSPIRE_TIMER=y
CONFIG_INTEGRATOR_AP_TIMER=y
CONFIG_CLKSRC_PISTACHIO=y
CONFIG_CLKSRC_TI_32K=y
CONFIG_CLKSRC_STM32_LP=y
CONFIG_CLKSRC_MPS2=y
CONFIG_ARC_TIMERS=y
CONFIG_ARC_TIMERS_64BIT=y
CONFIG_ARM_TIMER_SP804=y
CONFIG_ARMV7M_SYSTICK=y
CONFIG_ATMEL_PIT=y
CONFIG_ATMEL_ST=y
CONFIG_CLKSRC_SAMSUNG_PWM=y
CONFIG_FSL_FTM_TIMER=y
CONFIG_OXNAS_RPS_TIMER=y
CONFIG_SYS_SUPPORTS_SH_CMT=y
CONFIG_MTK_TIMER=y
CONFIG_SPRD_TIMER=y
CONFIG_CLKSRC_JCORE_PIT=y
CONFIG_SH_TIMER_CMT=y
CONFIG_SH_TIMER_MTU2=y
CONFIG_RENESAS_OSTM=y
CONFIG_SH_TIMER_TMU=y
CONFIG_EM_TIMER_STI=y
CONFIG_CLKSRC_VERSATILE=y
CONFIG_CLKSRC_PXA=y
CONFIG_TIMER_IMX_SYS_CTR=y
CONFIG_CLKSRC_ST_LPC=y
CONFIG_GXP_TIMER=y
CONFIG_MSC313E_TIMER=y
CONFIG_MICROCHIP_PIT64B=y
CONFIG_GOLDFISH_TIMER=y
# end of Clock Source drivers

CONFIG_MAILBOX=y
CONFIG_IMX_MBOX=m
CONFIG_PLATFORM_MHU=m
CONFIG_ARMADA_37XX_RWTM_MBOX=m
CONFIG_ROCKCHIP_MBOX=y
CONFIG_ALTERA_MBOX=m
CONFIG_HI3660_MBOX=m
CONFIG_HI6220_MBOX=m
CONFIG_MAILBOX_TEST=m
CONFIG_POLARFIRE_SOC_MAILBOX=m
CONFIG_QCOM_APCS_IPC=m
CONFIG_BCM_PDC_MBOX=m
CONFIG_STM32_IPCC=m
CONFIG_MTK_ADSP_MBOX=m
CONFIG_MTK_CMDQ_MBOX=m
CONFIG_SUN6I_MSGBOX=m
CONFIG_SPRD_MBOX=m
CONFIG_QCOM_IPCC=m
CONFIG_IOMMU_IOVA=m
CONFIG_IOMMU_API=y

#
# Remoteproc drivers
#
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=m
CONFIG_RPMSG_CHAR=m
CONFIG_RPMSG_CTRL=m
CONFIG_RPMSG_NS=m
CONFIG_RPMSG_QCOM_GLINK=m
CONFIG_RPMSG_QCOM_GLINK_RPM=m
CONFIG_RPMSG_QCOM_GLINK_SMEM=m
CONFIG_RPMSG_QCOM_SMD=m
# end of Rpmsg drivers

CONFIG_SOUNDWIRE=m

#
# SoundWire Devices
#
CONFIG_SOUNDWIRE_QCOM=m

#
# SOC (System On Chip) specific Drivers
#
CONFIG_OWL_PM_DOMAINS_HELPER=y
CONFIG_OWL_PM_DOMAINS=y

#
# Amlogic SoC drivers
#
CONFIG_MESON_CANVAS=m
CONFIG_MESON_CLK_MEASURE=m
CONFIG_MESON_GX_SOCINFO=y
CONFIG_MESON_GX_PM_DOMAINS=m
CONFIG_MESON_EE_PM_DOMAINS=m
CONFIG_MESON_MX_SOCINFO=y
# end of Amlogic SoC drivers

#
# Apple SoC drivers
#
CONFIG_APPLE_PMGR_PWRSTATE=y
CONFIG_APPLE_RTKIT=m
CONFIG_APPLE_SART=m
# end of Apple SoC drivers

#
# ASPEED SoC drivers
#
CONFIG_ASPEED_LPC_CTRL=m
CONFIG_ASPEED_LPC_SNOOP=m
CONFIG_ASPEED_UART_ROUTING=m
CONFIG_ASPEED_P2A_CTRL=m
CONFIG_ASPEED_SOCINFO=y
# end of ASPEED SoC drivers

CONFIG_AT91_SOC_ID=y
CONFIG_AT91_SOC_SFR=m

#
# Broadcom SoC drivers
#
CONFIG_BCM2835_POWER=y
CONFIG_SOC_BCM63XX=y
CONFIG_SOC_BRCMSTB=y
CONFIG_BCM63XX_POWER=y
CONFIG_BCM_PMB=y
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
CONFIG_QUICC_ENGINE=y
CONFIG_UCC_SLOW=y
CONFIG_UCC_FAST=y
CONFIG_UCC=y
CONFIG_QE_TDM=y
CONFIG_DPAA2_CONSOLE=m
# end of NXP/Freescale QorIQ SoC drivers

#
# fujitsu SoC drivers
#
# end of fujitsu SoC drivers

#
# i.MX SoC drivers
#
CONFIG_IMX_GPCV2_PM_DOMAINS=y
CONFIG_SOC_IMX8M=y
CONFIG_SOC_IMX9=m
# end of i.MX SoC drivers

#
# IXP4xx SoC drivers
#
CONFIG_IXP4XX_QMGR=m
CONFIG_IXP4XX_NPE=m
# end of IXP4xx SoC drivers

#
# Enable LiteX SoC Builder specific drivers
#
CONFIG_LITEX=y
CONFIG_LITEX_SOC_CONTROLLER=m
# end of Enable LiteX SoC Builder specific drivers

#
# MediaTek SoC drivers
#
CONFIG_MTK_CMDQ=m
CONFIG_MTK_DEVAPC=m
CONFIG_MTK_INFRACFG=y
CONFIG_MTK_PMIC_WRAP=m
CONFIG_MTK_SCPSYS=y
CONFIG_MTK_SCPSYS_PM_DOMAINS=y
CONFIG_MTK_MMSYS=y
CONFIG_MTK_SVS=m
# end of MediaTek SoC drivers

CONFIG_POLARFIRE_SOC_SYS_CTRL=m

#
# Qualcomm SoC drivers
#
CONFIG_QCOM_COMMAND_DB=m
CONFIG_QCOM_GENI_SE=m
CONFIG_QCOM_GSBI=m
CONFIG_QCOM_LLCC=m
CONFIG_QCOM_PDR_HELPERS=m
CONFIG_QCOM_QMI_HELPERS=m
CONFIG_QCOM_RPMH=m
CONFIG_QCOM_RPMHPD=m
CONFIG_QCOM_RPMPD=m
CONFIG_QCOM_SMEM=m
CONFIG_QCOM_SMD_RPM=m
CONFIG_QCOM_SMEM_STATE=y
CONFIG_QCOM_SMP2P=m
CONFIG_QCOM_SMSM=m
CONFIG_QCOM_SOCINFO=m
CONFIG_QCOM_SPM=m
CONFIG_QCOM_STATS=m
CONFIG_QCOM_WCNSS_CTRL=m
CONFIG_QCOM_APR=m
CONFIG_QCOM_ICC_BWMON=m
# end of Qualcomm SoC drivers

CONFIG_SOC_RENESAS=y
CONFIG_RST_RCAR=y
CONFIG_SYSC_RCAR=y
CONFIG_SYSC_RCAR_GEN4=y
CONFIG_SYSC_R8A77995=y
CONFIG_SYSC_R8A7794=y
CONFIG_SYSC_R8A77990=y
CONFIG_SYSC_R8A7779=y
CONFIG_SYSC_R8A7790=y
CONFIG_SYSC_R8A7795=y
CONFIG_SYSC_R8A7791=y
CONFIG_SYSC_R8A77965=y
CONFIG_SYSC_R8A77960=y
CONFIG_SYSC_R8A77961=y
CONFIG_SYSC_R8A779F0=y
CONFIG_SYSC_R8A7792=y
CONFIG_SYSC_R8A77980=y
CONFIG_SYSC_R8A77970=y
CONFIG_SYSC_R8A779A0=y
CONFIG_SYSC_R8A779G0=y
CONFIG_SYSC_RMOBILE=y
CONFIG_SYSC_R8A77470=y
CONFIG_SYSC_R8A7745=y
CONFIG_SYSC_R8A7742=y
CONFIG_SYSC_R8A7743=y
CONFIG_SYSC_R8A774C0=y
CONFIG_SYSC_R8A774E1=y
CONFIG_SYSC_R8A774A1=y
CONFIG_SYSC_R8A774B1=y
CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_IODOMAIN=m
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_ROCKCHIP_DTPM=m
CONFIG_SOC_SAMSUNG=y
CONFIG_EXYNOS_ASV_ARM=y
CONFIG_EXYNOS_CHIPID=m
CONFIG_EXYNOS_USI=m
CONFIG_EXYNOS_PM_DOMAINS=y
CONFIG_EXYNOS_REGULATOR_COUPLER=y
CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER=y
CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER=y
CONFIG_SOC_TI=y
CONFIG_UX500_SOC_ID=y

#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m
CONFIG_DEVFREQ_GOV_PERFORMANCE=m
CONFIG_DEVFREQ_GOV_POWERSAVE=m
CONFIG_DEVFREQ_GOV_USERSPACE=m
CONFIG_DEVFREQ_GOV_PASSIVE=m

#
# DEVFREQ Drivers
#
CONFIG_ARM_EXYNOS_BUS_DEVFREQ=m
CONFIG_ARM_IMX_BUS_DEVFREQ=m
CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=m
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=m
CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU=m
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=m
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
CONFIG_EXTCON_ADC_JACK=m
CONFIG_EXTCON_FSA9480=m
CONFIG_EXTCON_GPIO=m
CONFIG_EXTCON_MAX14577=m
CONFIG_EXTCON_MAX3355=m
CONFIG_EXTCON_MAX77693=m
CONFIG_EXTCON_PTN5150=m
CONFIG_EXTCON_QCOM_SPMI_MISC=m
CONFIG_EXTCON_RT8973A=m
CONFIG_EXTCON_SM5502=m
CONFIG_EXTCON_USB_GPIO=m
CONFIG_EXTCON_USBC_CROS_EC=m
CONFIG_EXTCON_USBC_TUSB320=m
CONFIG_MEMORY=y
CONFIG_DDR=y
CONFIG_ATMEL_SDRAMC=y
CONFIG_ATMEL_EBI=y
CONFIG_BRCMSTB_DPFE=m
CONFIG_BRCMSTB_MEMC=m
CONFIG_BT1_L2_CTL=y
CONFIG_TI_AEMIF=m
CONFIG_TI_EMIF=m
CONFIG_OMAP_GPMC=m
CONFIG_OMAP_GPMC_DEBUG=y
CONFIG_FPGA_DFL_EMIF=m
CONFIG_MVEBU_DEVBUS=y
CONFIG_FSL_CORENET_CF=m
CONFIG_FSL_IFC=y
CONFIG_JZ4780_NEMC=y
CONFIG_MTK_SMI=m
CONFIG_DA8XX_DDRCTL=y
CONFIG_RENESAS_RPCIF=m
CONFIG_STM32_FMC2_EBI=m
CONFIG_SAMSUNG_MC=y
CONFIG_EXYNOS5422_DMC=m
CONFIG_EXYNOS_SROM=y
CONFIG_IIO=m
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=m
CONFIG_IIO_BUFFER_DMA=m
CONFIG_IIO_BUFFER_DMAENGINE=m
CONFIG_IIO_BUFFER_HW_CONSUMER=m
CONFIG_IIO_KFIFO_BUF=m
CONFIG_IIO_TRIGGERED_BUFFER=m
CONFIG_IIO_CONFIGFS=m
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
CONFIG_IIO_SW_DEVICE=m
CONFIG_IIO_SW_TRIGGER=m
CONFIG_IIO_TRIGGERED_EVENT=m

#
# Accelerometers
#
CONFIG_ADIS16201=m
CONFIG_ADIS16209=m
CONFIG_ADXL313=m
CONFIG_ADXL313_I2C=m
CONFIG_ADXL313_SPI=m
CONFIG_ADXL355=m
CONFIG_ADXL355_I2C=m
CONFIG_ADXL355_SPI=m
CONFIG_ADXL367=m
CONFIG_ADXL367_SPI=m
CONFIG_ADXL367_I2C=m
CONFIG_ADXL372=m
CONFIG_ADXL372_SPI=m
CONFIG_ADXL372_I2C=m
CONFIG_BMA220=m
CONFIG_BMA400=m
CONFIG_BMA400_I2C=m
CONFIG_BMA400_SPI=m
CONFIG_BMC150_ACCEL=m
CONFIG_BMC150_ACCEL_I2C=m
CONFIG_BMC150_ACCEL_SPI=m
CONFIG_BMI088_ACCEL=m
CONFIG_BMI088_ACCEL_SPI=m
CONFIG_DA280=m
CONFIG_DA311=m
CONFIG_DMARD06=m
CONFIG_DMARD09=m
CONFIG_DMARD10=m
CONFIG_FXLS8962AF=m
CONFIG_FXLS8962AF_I2C=m
CONFIG_FXLS8962AF_SPI=m
CONFIG_HID_SENSOR_ACCEL_3D=m
CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
CONFIG_IIO_ST_ACCEL_3AXIS=m
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
CONFIG_KXSD9=m
CONFIG_KXSD9_SPI=m
CONFIG_KXSD9_I2C=m
CONFIG_KXCJK1013=m
CONFIG_MC3230=m
CONFIG_MMA7455=m
CONFIG_MMA7455_I2C=m
CONFIG_MMA7455_SPI=m
CONFIG_MMA7660=m
CONFIG_MMA8452=m
CONFIG_MMA9551_CORE=m
CONFIG_MMA9551=m
CONFIG_MMA9553=m
CONFIG_MSA311=m
CONFIG_MXC4005=m
CONFIG_MXC6255=m
CONFIG_SCA3000=m
CONFIG_SCA3300=m
CONFIG_STK8312=m
CONFIG_STK8BA50=m
# end of Accelerometers

#
# Analog to digital converters
#
CONFIG_AD_SIGMA_DELTA=m
CONFIG_AD7091R5=m
CONFIG_AD7124=m
CONFIG_AD7192=m
CONFIG_AD7266=m
CONFIG_AD7280=m
CONFIG_AD7291=m
CONFIG_AD7292=m
CONFIG_AD7298=m
CONFIG_AD7476=m
CONFIG_AD7606=m
CONFIG_AD7606_IFACE_PARALLEL=m
CONFIG_AD7606_IFACE_SPI=m
CONFIG_AD7766=m
CONFIG_AD7768_1=m
CONFIG_AD7780=m
CONFIG_AD7791=m
CONFIG_AD7793=m
CONFIG_AD7887=m
CONFIG_AD7923=m
CONFIG_AD7949=m
CONFIG_AD799X=m
CONFIG_AD9467=m
CONFIG_ADI_AXI_ADC=m
CONFIG_AT91_ADC=m
CONFIG_AT91_SAMA5D2_ADC=m
CONFIG_AXP20X_ADC=m
CONFIG_AXP288_ADC=m
CONFIG_BCM_IPROC_ADC=m
CONFIG_BERLIN2_ADC=m
CONFIG_CC10001_ADC=m
CONFIG_CPCAP_ADC=m
CONFIG_DA9150_GPADC=m
CONFIG_DLN2_ADC=m
CONFIG_ENVELOPE_DETECTOR=m
CONFIG_EXYNOS_ADC=m
CONFIG_MXS_LRADC_ADC=m
CONFIG_FSL_MX25_ADC=m
CONFIG_HI8435=m
CONFIG_HX711=m
CONFIG_INA2XX_ADC=m
CONFIG_INGENIC_ADC=m
CONFIG_IMX7D_ADC=m
CONFIG_IMX8QXP_ADC=m
CONFIG_LPC18XX_ADC=m
CONFIG_LPC32XX_ADC=m
CONFIG_LTC2471=m
CONFIG_LTC2485=m
CONFIG_LTC2496=m
CONFIG_LTC2497=m
CONFIG_MAX1027=m
CONFIG_MAX11100=m
CONFIG_MAX1118=m
CONFIG_MAX11205=m
CONFIG_MAX1241=m
CONFIG_MAX1363=m
CONFIG_MAX9611=m
CONFIG_MCP320X=m
CONFIG_MCP3422=m
CONFIG_MCP3911=m
CONFIG_MEDIATEK_MT6360_ADC=m
CONFIG_MEDIATEK_MT6577_AUXADC=m
CONFIG_MEN_Z188_ADC=m
CONFIG_MP2629_ADC=m
CONFIG_NAU7802=m
CONFIG_NPCM_ADC=m
CONFIG_QCOM_VADC_COMMON=m
CONFIG_QCOM_PM8XXX_XOADC=m
CONFIG_QCOM_SPMI_RRADC=m
CONFIG_QCOM_SPMI_IADC=m
CONFIG_QCOM_SPMI_VADC=m
CONFIG_QCOM_SPMI_ADC5=m
CONFIG_RCAR_GYRO_ADC=m
CONFIG_RN5T618_ADC=m
CONFIG_ROCKCHIP_SARADC=m
CONFIG_RICHTEK_RTQ6056=m
CONFIG_RZG2L_ADC=m
CONFIG_SC27XX_ADC=m
CONFIG_SPEAR_ADC=m
CONFIG_SD_ADC_MODULATOR=m
CONFIG_STM32_ADC_CORE=m
CONFIG_STM32_ADC=m
CONFIG_STM32_DFSDM_CORE=m
CONFIG_STM32_DFSDM_ADC=m
CONFIG_STMPE_ADC=m
CONFIG_SUN4I_GPADC=m
CONFIG_TI_ADC081C=m
CONFIG_TI_ADC0832=m
CONFIG_TI_ADC084S021=m
CONFIG_TI_ADC12138=m
CONFIG_TI_ADC108S102=m
CONFIG_TI_ADC128S052=m
CONFIG_TI_ADC161S626=m
CONFIG_TI_ADS1015=m
CONFIG_TI_ADS7950=m
CONFIG_TI_ADS8344=m
CONFIG_TI_ADS8688=m
CONFIG_TI_ADS124S08=m
CONFIG_TI_ADS131E08=m
CONFIG_TI_TLC4541=m
CONFIG_TI_TSC2046=m
CONFIG_VF610_ADC=m
CONFIG_VIPERBOARD_ADC=m
CONFIG_XILINX_XADC=m
CONFIG_XILINX_AMS=m
# end of Analog to digital converters

#
# Analog to digital and digital to analog converters
#
CONFIG_AD74413R=m
# end of Analog to digital and digital to analog converters

#
# Analog Front Ends
#
CONFIG_IIO_RESCALE=m
# end of Analog Front Ends

#
# Amplifiers
#
CONFIG_AD8366=m
CONFIG_ADA4250=m
CONFIG_HMC425=m
# end of Amplifiers

#
# Capacitance to digital converters
#
CONFIG_AD7150=m
CONFIG_AD7746=m
# end of Capacitance to digital converters

#
# Chemical Sensors
#
CONFIG_ATLAS_PH_SENSOR=m
CONFIG_ATLAS_EZO_SENSOR=m
CONFIG_BME680=m
CONFIG_BME680_I2C=m
CONFIG_BME680_SPI=m
CONFIG_CCS811=m
CONFIG_IAQCORE=m
CONFIG_PMS7003=m
CONFIG_SCD30_CORE=m
CONFIG_SCD30_I2C=m
CONFIG_SCD30_SERIAL=m
CONFIG_SCD4X=m
CONFIG_SENSIRION_SGP30=m
CONFIG_SENSIRION_SGP40=m
CONFIG_SPS30=m
CONFIG_SPS30_I2C=m
CONFIG_SPS30_SERIAL=m
CONFIG_SENSEAIR_SUNRISE_CO2=m
CONFIG_VZ89X=m
# end of Chemical Sensors

CONFIG_IIO_CROS_EC_SENSORS_CORE=m
CONFIG_IIO_CROS_EC_SENSORS=m
CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m

#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=m
CONFIG_HID_SENSOR_IIO_TRIGGER=m
# end of Hid Sensor IIO Common

CONFIG_IIO_MS_SENSORS_I2C=m

#
# IIO SCMI Sensors
#
CONFIG_IIO_SCMI=m
# end of IIO SCMI Sensors

#
# SSP Sensor Common
#
CONFIG_IIO_SSP_SENSORS_COMMONS=m
CONFIG_IIO_SSP_SENSORHUB=m
# end of SSP Sensor Common

CONFIG_IIO_ST_SENSORS_I2C=m
CONFIG_IIO_ST_SENSORS_SPI=m
CONFIG_IIO_ST_SENSORS_CORE=m

#
# Digital to analog converters
#
CONFIG_AD3552R=m
CONFIG_AD5064=m
CONFIG_AD5360=m
CONFIG_AD5380=m
CONFIG_AD5421=m
CONFIG_AD5446=m
CONFIG_AD5449=m
CONFIG_AD5592R_BASE=m
CONFIG_AD5592R=m
CONFIG_AD5593R=m
CONFIG_AD5504=m
CONFIG_AD5624R_SPI=m
CONFIG_LTC2688=m
CONFIG_AD5686=m
CONFIG_AD5686_SPI=m
CONFIG_AD5696_I2C=m
CONFIG_AD5755=m
CONFIG_AD5758=m
CONFIG_AD5761=m
CONFIG_AD5764=m
CONFIG_AD5766=m
CONFIG_AD5770R=m
CONFIG_AD5791=m
CONFIG_AD7293=m
CONFIG_AD7303=m
CONFIG_AD8801=m
CONFIG_DPOT_DAC=m
CONFIG_DS4424=m
CONFIG_LPC18XX_DAC=m
CONFIG_LTC1660=m
CONFIG_LTC2632=m
CONFIG_M62332=m
CONFIG_MAX517=m
CONFIG_MAX5821=m
CONFIG_MCP4725=m
CONFIG_MCP4922=m
CONFIG_STM32_DAC=m
CONFIG_STM32_DAC_CORE=m
CONFIG_TI_DAC082S085=m
CONFIG_TI_DAC5571=m
CONFIG_TI_DAC7311=m
CONFIG_TI_DAC7612=m
CONFIG_VF610_DAC=m
# end of Digital to analog converters

#
# IIO dummy driver
#
CONFIG_IIO_DUMMY_EVGEN=m
CONFIG_IIO_SIMPLE_DUMMY=m
CONFIG_IIO_SIMPLE_DUMMY_EVENTS=y
CONFIG_IIO_SIMPLE_DUMMY_BUFFER=y
# end of IIO dummy driver

#
# Filters
#
# end of Filters

#
# Frequency Synthesizers DDS/PLL
#

#
# Clock Generator/Distribution
#
CONFIG_AD9523=m
# end of Clock Generator/Distribution

#
# Phase-Locked Loop (PLL) frequency synthesizers
#
CONFIG_ADF4350=m
CONFIG_ADF4371=m
CONFIG_ADMV4420=m
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL

#
# Digital gyroscope sensors
#
CONFIG_ADIS16080=m
CONFIG_ADIS16130=m
CONFIG_ADIS16136=m
CONFIG_ADIS16260=m
CONFIG_ADXRS290=m
CONFIG_ADXRS450=m
CONFIG_BMG160=m
CONFIG_BMG160_I2C=m
CONFIG_BMG160_SPI=m
CONFIG_FXAS21002C=m
CONFIG_FXAS21002C_I2C=m
CONFIG_FXAS21002C_SPI=m
CONFIG_HID_SENSOR_GYRO_3D=m
CONFIG_MPU3050=m
CONFIG_MPU3050_I2C=m
CONFIG_IIO_ST_GYRO_3AXIS=m
CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
CONFIG_ITG3200=m
# end of Digital gyroscope sensors

#
# Health Sensors
#

#
# Heart Rate Monitors
#
CONFIG_AFE4403=m
CONFIG_AFE4404=m
CONFIG_MAX30100=m
CONFIG_MAX30102=m
# end of Heart Rate Monitors
# end of Health Sensors

#
# Humidity sensors
#
CONFIG_AM2315=m
CONFIG_DHT11=m
CONFIG_HDC100X=m
CONFIG_HDC2010=m
CONFIG_HID_SENSOR_HUMIDITY=m
CONFIG_HTS221=m
CONFIG_HTS221_I2C=m
CONFIG_HTS221_SPI=m
CONFIG_HTU21=m
CONFIG_SI7005=m
CONFIG_SI7020=m
# end of Humidity sensors

#
# Inertial measurement units
#
CONFIG_ADIS16400=m
CONFIG_ADIS16460=m
CONFIG_ADIS16475=m
CONFIG_ADIS16480=m
CONFIG_BMI160=m
CONFIG_BMI160_I2C=m
CONFIG_BMI160_SPI=m
CONFIG_BOSCH_BNO055=m
CONFIG_BOSCH_BNO055_SERIAL=m
CONFIG_BOSCH_BNO055_I2C=m
CONFIG_FXOS8700=m
CONFIG_FXOS8700_I2C=m
CONFIG_FXOS8700_SPI=m
CONFIG_KMX61=m
CONFIG_INV_ICM42600=m
CONFIG_INV_ICM42600_I2C=m
CONFIG_INV_ICM42600_SPI=m
CONFIG_INV_MPU6050_IIO=m
CONFIG_INV_MPU6050_I2C=m
CONFIG_INV_MPU6050_SPI=m
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_LSM6DSX_I2C=m
CONFIG_IIO_ST_LSM6DSX_SPI=m
CONFIG_IIO_ST_LSM6DSX_I3C=m
CONFIG_IIO_ST_LSM9DS0=m
CONFIG_IIO_ST_LSM9DS0_I2C=m
CONFIG_IIO_ST_LSM9DS0_SPI=m
# end of Inertial measurement units

CONFIG_IIO_ADIS_LIB=m
CONFIG_IIO_ADIS_LIB_BUFFER=y

#
# Light sensors
#
CONFIG_ADJD_S311=m
CONFIG_ADUX1020=m
CONFIG_AL3010=m
CONFIG_AL3320A=m
CONFIG_APDS9300=m
CONFIG_APDS9960=m
CONFIG_AS73211=m
CONFIG_BH1750=m
CONFIG_BH1780=m
CONFIG_CM32181=m
CONFIG_CM3232=m
CONFIG_CM3323=m
CONFIG_CM3605=m
CONFIG_CM36651=m
CONFIG_IIO_CROS_EC_LIGHT_PROX=m
CONFIG_GP2AP002=m
CONFIG_GP2AP020A00F=m
CONFIG_IQS621_ALS=m
CONFIG_SENSORS_ISL29018=m
CONFIG_SENSORS_ISL29028=m
CONFIG_ISL29125=m
CONFIG_HID_SENSOR_ALS=m
CONFIG_HID_SENSOR_PROX=m
CONFIG_JSA1212=m
CONFIG_RPR0521=m
CONFIG_SENSORS_LM3533=m
CONFIG_LTR501=m
CONFIG_LTRF216A=m
CONFIG_LV0104CS=m
CONFIG_MAX44000=m
CONFIG_MAX44009=m
CONFIG_NOA1305=m
CONFIG_OPT3001=m
CONFIG_PA12203001=m
CONFIG_SI1133=m
CONFIG_SI1145=m
CONFIG_STK3310=m
CONFIG_ST_UVIS25=m
CONFIG_ST_UVIS25_I2C=m
CONFIG_ST_UVIS25_SPI=m
CONFIG_TCS3414=m
CONFIG_TCS3472=m
CONFIG_SENSORS_TSL2563=m
CONFIG_TSL2583=m
CONFIG_TSL2591=m
CONFIG_TSL2772=m
CONFIG_TSL4531=m
CONFIG_US5182D=m
CONFIG_VCNL4000=m
CONFIG_VCNL4035=m
CONFIG_VEML6030=m
CONFIG_VEML6070=m
CONFIG_VL6180=m
CONFIG_ZOPT2201=m
# end of Light sensors

#
# Magnetometer sensors
#
CONFIG_AK8974=m
CONFIG_AK8975=m
CONFIG_AK09911=m
CONFIG_BMC150_MAGN=m
CONFIG_BMC150_MAGN_I2C=m
CONFIG_BMC150_MAGN_SPI=m
CONFIG_MAG3110=m
CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
CONFIG_MMC35240=m
CONFIG_IIO_ST_MAGN_3AXIS=m
CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
CONFIG_SENSORS_HMC5843=m
CONFIG_SENSORS_HMC5843_I2C=m
CONFIG_SENSORS_HMC5843_SPI=m
CONFIG_SENSORS_RM3100=m
CONFIG_SENSORS_RM3100_I2C=m
CONFIG_SENSORS_RM3100_SPI=m
CONFIG_YAMAHA_YAS530=m
# end of Magnetometer sensors

#
# Multiplexers
#
CONFIG_IIO_MUX=m
# end of Multiplexers

#
# Inclinometer sensors
#
CONFIG_HID_SENSOR_INCLINOMETER_3D=m
CONFIG_HID_SENSOR_DEVICE_ROTATION=m
# end of Inclinometer sensors

CONFIG_IIO_RESCALE_KUNIT_TEST=m
CONFIG_IIO_FORMAT_KUNIT_TEST=m

#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=m
CONFIG_IIO_INTERRUPT_TRIGGER=m
CONFIG_IIO_STM32_LPTIMER_TRIGGER=m
CONFIG_IIO_STM32_TIMER_TRIGGER=m
CONFIG_IIO_TIGHTLOOP_TRIGGER=m
CONFIG_IIO_SYSFS_TRIGGER=m
# end of Triggers - standalone

#
# Linear and angular position sensors
#
CONFIG_IQS624_POS=m
CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
# end of Linear and angular position sensors

#
# Digital potentiometers
#
CONFIG_AD5110=m
CONFIG_AD5272=m
CONFIG_DS1803=m
CONFIG_MAX5432=m
CONFIG_MAX5481=m
CONFIG_MAX5487=m
CONFIG_MCP4018=m
CONFIG_MCP4131=m
CONFIG_MCP4531=m
CONFIG_MCP41010=m
CONFIG_TPL0102=m
# end of Digital potentiometers

#
# Digital potentiostats
#
CONFIG_LMP91000=m
# end of Digital potentiostats

#
# Pressure sensors
#
CONFIG_ABP060MG=m
CONFIG_BMP280=m
CONFIG_BMP280_I2C=m
CONFIG_BMP280_SPI=m
CONFIG_IIO_CROS_EC_BARO=m
CONFIG_DLHL60D=m
CONFIG_DPS310=m
CONFIG_HID_SENSOR_PRESS=m
CONFIG_HP03=m
CONFIG_ICP10100=m
CONFIG_MPL115=m
CONFIG_MPL115_I2C=m
CONFIG_MPL115_SPI=m
CONFIG_MPL3115=m
CONFIG_MS5611=m
CONFIG_MS5611_I2C=m
CONFIG_MS5611_SPI=m
CONFIG_MS5637=m
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_PRESS_I2C=m
CONFIG_IIO_ST_PRESS_SPI=m
CONFIG_T5403=m
CONFIG_HP206C=m
CONFIG_ZPA2326=m
CONFIG_ZPA2326_I2C=m
CONFIG_ZPA2326_SPI=m
# end of Pressure sensors

#
# Lightning sensors
#
CONFIG_AS3935=m
# end of Lightning sensors

#
# Proximity and distance sensors
#
CONFIG_CROS_EC_MKBP_PROXIMITY=m
CONFIG_ISL29501=m
CONFIG_LIDAR_LITE_V2=m
CONFIG_MB1232=m
CONFIG_PING=m
CONFIG_RFD77402=m
CONFIG_SRF04=m
CONFIG_SX_COMMON=m
CONFIG_SX9310=m
CONFIG_SX9324=m
CONFIG_SX9360=m
CONFIG_SX9500=m
CONFIG_SRF08=m
CONFIG_VCNL3020=m
CONFIG_VL53L0X_I2C=m
# end of Proximity and distance sensors

#
# Resolver to digital converters
#
CONFIG_AD2S90=m
CONFIG_AD2S1200=m
# end of Resolver to digital converters

#
# Temperature sensors
#
CONFIG_IQS620AT_TEMP=m
CONFIG_LTC2983=m
CONFIG_MAXIM_THERMOCOUPLE=m
CONFIG_HID_SENSOR_TEMP=m
CONFIG_MLX90614=m
CONFIG_MLX90632=m
CONFIG_TMP006=m
CONFIG_TMP007=m
CONFIG_TMP117=m
CONFIG_TSYS01=m
CONFIG_TSYS02D=m
CONFIG_MAX31856=m
CONFIG_MAX31865=m
# end of Temperature sensors

CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
CONFIG_PWM_DEBUG=y
CONFIG_PWM_ATMEL=m
CONFIG_PWM_ATMEL_HLCDC_PWM=m
CONFIG_PWM_ATMEL_TCB=m
CONFIG_PWM_BCM_KONA=m
CONFIG_PWM_BCM2835=m
CONFIG_PWM_BERLIN=m
CONFIG_PWM_BRCMSTB=m
CONFIG_PWM_CLK=m
CONFIG_PWM_CLPS711X=m
CONFIG_PWM_CROS_EC=m
CONFIG_PWM_EP93XX=m
CONFIG_PWM_FSL_FTM=m
CONFIG_PWM_HIBVT=m
CONFIG_PWM_IMX1=m
CONFIG_PWM_IMX27=m
CONFIG_PWM_IMX_TPM=m
CONFIG_PWM_INTEL_LGM=m
CONFIG_PWM_IQS620A=m
CONFIG_PWM_LP3943=m
CONFIG_PWM_LPC18XX_SCT=m
CONFIG_PWM_LPC32XX=m
CONFIG_PWM_LPSS=m
CONFIG_PWM_LPSS_PLATFORM=m
CONFIG_PWM_MTK_DISP=m
CONFIG_PWM_MEDIATEK=m
CONFIG_PWM_MXS=m
CONFIG_PWM_NTXEC=m
CONFIG_PWM_OMAP_DMTIMER=m
CONFIG_PWM_PCA9685=m
CONFIG_PWM_PXA=m
CONFIG_PWM_RASPBERRYPI_POE=m
CONFIG_PWM_RCAR=m
CONFIG_PWM_RENESAS_TPU=m
CONFIG_PWM_ROCKCHIP=m
CONFIG_PWM_SAMSUNG=m
CONFIG_PWM_SL28CPLD=m
CONFIG_PWM_SPEAR=m
CONFIG_PWM_SPRD=m
CONFIG_PWM_STI=m
CONFIG_PWM_STM32=m
CONFIG_PWM_STM32_LP=m
CONFIG_PWM_STMPE=y
CONFIG_PWM_SUNPLUS=m
CONFIG_PWM_TEGRA=m
CONFIG_PWM_TIECAP=m
CONFIG_PWM_TIEHRPWM=m
CONFIG_PWM_VISCONTI=m
CONFIG_PWM_VT8500=m

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_AL_FIC=y
CONFIG_MADERA_IRQ=m
CONFIG_JCORE_AIC=y
CONFIG_RENESAS_INTC_IRQPIN=y
CONFIG_RENESAS_IRQC=y
CONFIG_RENESAS_RZA1_IRQC=y
CONFIG_RENESAS_RZG2L_IRQC=y
CONFIG_SL28CPLD_INTC=y
CONFIG_TS4800_IRQ=m
CONFIG_XILINX_INTC=y
CONFIG_INGENIC_TCU_IRQ=y
CONFIG_IRQ_UNIPHIER_AIDET=y
CONFIG_MESON_IRQ_GPIO=m
CONFIG_IMX_IRQSTEER=y
CONFIG_IMX_INTMUX=y
CONFIG_IMX_MU_MSI=m
CONFIG_EXYNOS_IRQ_COMBINER=y
CONFIG_MST_IRQ=y
CONFIG_MCHP_EIC=y
CONFIG_SUNPLUS_SP7021_INTC=y
# end of IRQ chip support

CONFIG_IPACK_BUS=m
CONFIG_SERIAL_IPOCTAL=m
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_A10SR=m
CONFIG_RESET_ATH79=y
CONFIG_RESET_AXS10X=y
CONFIG_RESET_BCM6345=y
CONFIG_RESET_BERLIN=m
CONFIG_RESET_BRCMSTB=m
CONFIG_RESET_BRCMSTB_RESCAL=m
CONFIG_RESET_HSDK=y
CONFIG_RESET_IMX7=m
CONFIG_RESET_INTEL_GW=y
CONFIG_RESET_K210=y
CONFIG_RESET_LANTIQ=y
CONFIG_RESET_LPC18XX=y
CONFIG_RESET_MCHP_SPARX5=y
CONFIG_RESET_MESON=m
CONFIG_RESET_MESON_AUDIO_ARB=m
CONFIG_RESET_NPCM=y
CONFIG_RESET_PISTACHIO=y
CONFIG_RESET_QCOM_AOSS=m
CONFIG_RESET_QCOM_PDC=m
CONFIG_RESET_RASPBERRYPI=m
CONFIG_RESET_RZG2L_USBPHY_CTRL=m
CONFIG_RESET_SCMI=m
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_SOCFPGA=y
CONFIG_RESET_STARFIVE_JH7100=y
CONFIG_RESET_SUNPLUS=y
CONFIG_RESET_SUNXI=y
CONFIG_RESET_TI_SCI=m
CONFIG_RESET_TI_SYSCON=m
CONFIG_RESET_TI_TPS380X=m
CONFIG_RESET_TN48M_CPLD=m
CONFIG_RESET_UNIPHIER=m
CONFIG_RESET_UNIPHIER_GLUE=m
CONFIG_RESET_ZYNQ=y
CONFIG_COMMON_RESET_HI3660=m
CONFIG_COMMON_RESET_HI6220=m

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
CONFIG_PHY_LPC18XX_USB_OTG=m
CONFIG_PHY_PISTACHIO_USB=m
CONFIG_PHY_XGENE=m
CONFIG_USB_LGM_PHY=m
CONFIG_PHY_CAN_TRANSCEIVER=m
CONFIG_PHY_SUN4I_USB=m
CONFIG_PHY_SUN9I_USB=m
CONFIG_PHY_SUN50I_USB3=m
CONFIG_PHY_MESON8_HDMI_TX=m
CONFIG_PHY_MESON8B_USB2=m
CONFIG_PHY_MESON_GXL_USB2=m
CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=m
CONFIG_PHY_MESON_G12A_USB2=m
CONFIG_PHY_MESON_G12A_USB3_PCIE=m
CONFIG_PHY_MESON_AXG_PCIE=m
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=m
CONFIG_PHY_MESON_AXG_MIPI_DPHY=m

#
# PHY drivers for Broadcom platforms
#
CONFIG_PHY_BCM63XX_USBH=m
CONFIG_PHY_CYGNUS_PCIE=m
CONFIG_PHY_BCM_SR_USB=m
CONFIG_BCM_KONA_USB2_PHY=m
CONFIG_PHY_BCM_NS_USB2=m
CONFIG_PHY_BCM_NS_USB3=m
CONFIG_PHY_NS2_PCIE=m
CONFIG_PHY_NS2_USB_DRD=m
CONFIG_PHY_BRCM_SATA=m
CONFIG_PHY_BRCM_USB=m
CONFIG_PHY_BCM_SR_PCIE=m
# end of PHY drivers for Broadcom platforms

CONFIG_PHY_CADENCE_DPHY=m
CONFIG_PHY_CADENCE_DPHY_RX=m
CONFIG_PHY_CADENCE_SALVO=m
CONFIG_PHY_FSL_IMX8MQ_USB=m
CONFIG_PHY_MIXEL_LVDS_PHY=m
CONFIG_PHY_MIXEL_MIPI_DPHY=m
CONFIG_PHY_FSL_IMX8M_PCIE=m
CONFIG_PHY_FSL_LYNX_28G=m
CONFIG_PHY_HI6220_USB=m
CONFIG_PHY_HI3660_USB=m
CONFIG_PHY_HI3670_USB=m
CONFIG_PHY_HI3670_PCIE=m
CONFIG_PHY_HISTB_COMBPHY=m
CONFIG_PHY_HISI_INNO_USB2=m
CONFIG_PHY_INGENIC_USB=m
CONFIG_PHY_LANTIQ_VRX200_PCIE=m
CONFIG_PHY_LANTIQ_RCU_USB2=m
CONFIG_ARMADA375_USBCLUSTER_PHY=y
CONFIG_PHY_BERLIN_SATA=m
CONFIG_PHY_BERLIN_USB=m
CONFIG_PHY_MVEBU_A3700_UTMI=m
CONFIG_PHY_MVEBU_A38X_COMPHY=m
CONFIG_PHY_MVEBU_CP110_UTMI=m
CONFIG_PHY_PXA_28NM_HSIC=m
CONFIG_PHY_PXA_28NM_USB2=m
CONFIG_PHY_PXA_USB=m
CONFIG_PHY_MMP3_USB=m
CONFIG_PHY_MMP3_HSIC=m
CONFIG_PHY_MTK_PCIE=m
CONFIG_PHY_MTK_TPHY=m
CONFIG_PHY_MTK_UFS=m
CONFIG_PHY_MTK_XSPHY=m
CONFIG_PHY_MTK_DP=m
CONFIG_PHY_SPARX5_SERDES=m
CONFIG_PHY_LAN966X_SERDES=m
CONFIG_PHY_CPCAP_USB=m
CONFIG_PHY_MAPPHONE_MDM6600=m
CONFIG_PHY_OCELOT_SERDES=m
CONFIG_PHY_ATH79_USB=m
CONFIG_PHY_QCOM_IPQ4019_USB=m
CONFIG_PHY_QCOM_QUSB2=m
CONFIG_PHY_QCOM_USB_HS=m
CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=m
CONFIG_PHY_QCOM_USB_HSIC=m
CONFIG_PHY_QCOM_USB_HS_28NM=m
CONFIG_PHY_QCOM_USB_SS=m
CONFIG_PHY_QCOM_IPQ806X_USB=m
CONFIG_PHY_MT7621_PCI=m
CONFIG_PHY_RALINK_USB=m
CONFIG_PHY_RCAR_GEN3_USB3=m
CONFIG_PHY_ROCKCHIP_DPHY_RX0=m
CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m
CONFIG_PHY_ROCKCHIP_PCIE=m
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=m
CONFIG_PHY_ROCKCHIP_TYPEC=m
CONFIG_PHY_EXYNOS_DP_VIDEO=m
CONFIG_PHY_EXYNOS_MIPI_VIDEO=m
CONFIG_PHY_EXYNOS_PCIE=y
CONFIG_PHY_SAMSUNG_UFS=m
CONFIG_PHY_SAMSUNG_USB2=m
CONFIG_PHY_S5PV210_USB2=y
CONFIG_PHY_UNIPHIER_USB2=m
CONFIG_PHY_UNIPHIER_USB3=m
CONFIG_PHY_UNIPHIER_PCIE=m
CONFIG_PHY_UNIPHIER_AHCI=m
CONFIG_PHY_ST_SPEAR1310_MIPHY=m
CONFIG_PHY_ST_SPEAR1340_MIPHY=m
CONFIG_PHY_STIH407_USB=m
CONFIG_PHY_SUNPLUS_USB=m
CONFIG_PHY_TEGRA194_P2U=m
CONFIG_PHY_DA8XX_USB=m
CONFIG_PHY_DM816X_USB=m
CONFIG_OMAP_CONTROL_PHY=m
CONFIG_TI_PIPE3=m
CONFIG_PHY_TUSB1210=m
CONFIG_PHY_INTEL_KEEMBAY_EMMC=m
CONFIG_PHY_INTEL_KEEMBAY_USB=m
CONFIG_PHY_INTEL_LGM_COMBO=y
CONFIG_PHY_INTEL_LGM_EMMC=m
CONFIG_PHY_INTEL_THUNDERBAY_EMMC=m
CONFIG_PHY_XILINX_ZYNQMP=m
# end of PHY Subsystem

CONFIG_POWERCAP=y
CONFIG_IDLE_INJECT=y
CONFIG_DTPM=y
CONFIG_MCB=m
CONFIG_MCB_LPC=m

#
# Performance monitor support
#
CONFIG_ARM_CCN=m
CONFIG_ARM_CMN=m
CONFIG_FSL_IMX8_DDR_PMU=m
CONFIG_ARM_DMC620_PMU=m
CONFIG_ALIBABA_UNCORE_DRW_PMU=m
# end of Performance monitor support

CONFIG_RAS=y

#
# Android
#
# end of Android

CONFIG_DAX=m
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_NVMEM_APPLE_EFUSES=m
CONFIG_NVMEM_BCM_OCOTP=m
CONFIG_NVMEM_BRCM_NVRAM=m
CONFIG_NVMEM_IMX_IIM=m
CONFIG_NVMEM_IMX_OCOTP=m
CONFIG_NVMEM_JZ4780_EFUSE=m
CONFIG_NVMEM_LAN9662_OTPC=m
CONFIG_NVMEM_LAYERSCAPE_SFP=m
CONFIG_NVMEM_LPC18XX_EEPROM=m
CONFIG_NVMEM_LPC18XX_OTP=m
CONFIG_NVMEM_MESON_MX_EFUSE=m
CONFIG_NVMEM_MICROCHIP_OTPC=m
CONFIG_NVMEM_MTK_EFUSE=m
CONFIG_NVMEM_MXS_OCOTP=m
CONFIG_NVMEM_NINTENDO_OTP=m
CONFIG_NVMEM_QCOM_QFPROM=m
CONFIG_NVMEM_RAVE_SP_EEPROM=m
CONFIG_NVMEM_RMEM=m
CONFIG_NVMEM_ROCKCHIP_EFUSE=m
CONFIG_NVMEM_ROCKCHIP_OTP=m
CONFIG_NVMEM_SC27XX_EFUSE=m
CONFIG_NVMEM_SNVS_LPGPR=m
CONFIG_NVMEM_SPMI_SDAM=m
CONFIG_NVMEM_SPRD_EFUSE=m
CONFIG_NVMEM_STM32_ROMEM=m
CONFIG_NVMEM_SUNPLUS_OCOTP=m
CONFIG_NVMEM_U_BOOT_ENV=m
CONFIG_NVMEM_UNIPHIER_EFUSE=m
CONFIG_NVMEM_VF610_OCOTP=m

#
# HW tracing support
#
CONFIG_STM=m
CONFIG_STM_PROTO_BASIC=m
CONFIG_STM_PROTO_SYS_T=m
CONFIG_STM_DUMMY=m
CONFIG_STM_SOURCE_CONSOLE=m
CONFIG_STM_SOURCE_HEARTBEAT=m
CONFIG_STM_SOURCE_FTRACE=m
# end of HW tracing support

CONFIG_FPGA=m
CONFIG_FPGA_MGR_SOCFPGA=m
CONFIG_FPGA_MGR_SOCFPGA_A10=m
CONFIG_ALTERA_PR_IP_CORE=m
CONFIG_ALTERA_PR_IP_CORE_PLAT=m
CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
CONFIG_FPGA_MGR_ZYNQ_FPGA=m
CONFIG_FPGA_MGR_XILINX_SPI=m
CONFIG_FPGA_MGR_ICE40_SPI=m
CONFIG_FPGA_MGR_MACHXO2_SPI=m
CONFIG_FPGA_BRIDGE=m
CONFIG_ALTERA_FREEZE_BRIDGE=m
CONFIG_XILINX_PR_DECOUPLER=m
CONFIG_FPGA_REGION=m
CONFIG_OF_FPGA_REGION=m
CONFIG_FPGA_DFL=m
CONFIG_FPGA_DFL_FME=m
CONFIG_FPGA_DFL_FME_MGR=m
CONFIG_FPGA_DFL_FME_BRIDGE=m
CONFIG_FPGA_DFL_FME_REGION=m
CONFIG_FPGA_DFL_AFU=m
CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m
CONFIG_FPGA_MGR_ZYNQMP_FPGA=m
CONFIG_FPGA_MGR_VERSAL_FPGA=m
CONFIG_FPGA_M10_BMC_SEC_UPDATE=m
CONFIG_FPGA_MGR_MICROCHIP_SPI=m
CONFIG_FSI=m
CONFIG_FSI_NEW_DEV_NODE=y
CONFIG_FSI_MASTER_GPIO=m
CONFIG_FSI_MASTER_HUB=m
CONFIG_FSI_MASTER_AST_CF=m
CONFIG_FSI_MASTER_ASPEED=m
CONFIG_FSI_SCOM=m
CONFIG_FSI_SBEFIFO=m
CONFIG_FSI_OCC=m
CONFIG_TEE=m
CONFIG_MULTIPLEXER=m

#
# Multiplexer drivers
#
CONFIG_MUX_ADG792A=m
CONFIG_MUX_ADGS1408=m
CONFIG_MUX_GPIO=m
CONFIG_MUX_MMIO=m
# end of Multiplexer drivers

CONFIG_PM_OPP=y
CONFIG_SIOX=m
CONFIG_SIOX_BUS_GPIO=m
CONFIG_SLIMBUS=m
CONFIG_SLIM_QCOM_CTRL=m
CONFIG_INTERCONNECT=y
CONFIG_INTERCONNECT_IMX=m
CONFIG_INTERCONNECT_IMX8MM=m
CONFIG_INTERCONNECT_IMX8MN=m
CONFIG_INTERCONNECT_IMX8MQ=m
CONFIG_INTERCONNECT_IMX8MP=m
CONFIG_INTERCONNECT_QCOM_OSM_L3=m
CONFIG_INTERCONNECT_SAMSUNG=y
CONFIG_INTERCONNECT_EXYNOS=m
CONFIG_COUNTER=m
CONFIG_104_QUAD_8=m
CONFIG_INTERRUPT_CNT=m
CONFIG_STM32_TIMER_CNT=m
CONFIG_STM32_LPTIMER_CNT=m
CONFIG_TI_EQEP=m
CONFIG_FTM_QUADDEC=m
CONFIG_MICROCHIP_TCB_CAPTURE=m
CONFIG_TI_ECAP_CAPTURE=m
CONFIG_PECI=m
CONFIG_PECI_CPU=m
CONFIG_HTE=y
# end of Device Drivers

#
# File systems
#
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_FS_IOMAP=y
CONFIG_EXT2_FS=m
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=m
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_EXT4_FS=m
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_EXT4_DEBUG=y
CONFIG_EXT4_KUNIT_TESTS=m
CONFIG_JBD2=m
CONFIG_JBD2_DEBUG=y
CONFIG_FS_MBCACHE=m
CONFIG_REISERFS_FS=m
CONFIG_REISERFS_CHECK=y
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
CONFIG_JFS_DEBUG=y
CONFIG_JFS_STATISTICS=y
CONFIG_XFS_FS=m
CONFIG_XFS_SUPPORT_V4=y
CONFIG_XFS_QUOTA=y
CONFIG_XFS_POSIX_ACL=y
CONFIG_XFS_RT=y
CONFIG_XFS_ONLINE_SCRUB=y
CONFIG_XFS_ONLINE_REPAIR=y
CONFIG_XFS_DEBUG=y
CONFIG_XFS_ASSERT_FATAL=y
CONFIG_GFS2_FS=m
CONFIG_GFS2_FS_LOCKING_DLM=y
CONFIG_OCFS2_FS=m
CONFIG_OCFS2_FS_O2CB=m
CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
CONFIG_OCFS2_FS_STATS=y
CONFIG_OCFS2_DEBUG_MASKLOG=y
CONFIG_OCFS2_DEBUG_FS=y
CONFIG_BTRFS_FS=m
CONFIG_BTRFS_FS_POSIX_ACL=y
CONFIG_BTRFS_FS_CHECK_INTEGRITY=y
CONFIG_BTRFS_FS_RUN_SANITY_TESTS=y
CONFIG_BTRFS_DEBUG=y
CONFIG_BTRFS_ASSERT=y
CONFIG_BTRFS_FS_REF_VERIFY=y
CONFIG_NILFS2_FS=m
CONFIG_F2FS_FS=m
CONFIG_F2FS_STAT_FS=y
CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
CONFIG_F2FS_CHECK_FS=y
CONFIG_F2FS_FAULT_INJECTION=y
CONFIG_F2FS_FS_COMPRESSION=y
CONFIG_F2FS_FS_LZO=y
CONFIG_F2FS_FS_LZORLE=y
CONFIG_F2FS_FS_LZ4=y
CONFIG_F2FS_FS_LZ4HC=y
CONFIG_F2FS_FS_ZSTD=y
CONFIG_F2FS_IOSTAT=y
CONFIG_F2FS_UNFAIR_RWSEM=y
CONFIG_ZONEFS_FS=m
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FS_ENCRYPTION_ALGS=m
CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
CONFIG_FS_VERITY=y
CONFIG_FS_VERITY_DEBUG=y
CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
CONFIG_PRINT_QUOTA_WARNING=y
CONFIG_QUOTA_DEBUG=y
CONFIG_QUOTA_TREE=m
CONFIG_QFMT_V1=m
CONFIG_QFMT_V2=m
CONFIG_QUOTACTL=y
CONFIG_AUTOFS4_FS=m
CONFIG_AUTOFS_FS=m
CONFIG_FUSE_FS=m
CONFIG_CUSE=m
CONFIG_VIRTIO_FS=m
CONFIG_OVERLAY_FS=m
CONFIG_OVERLAY_FS_REDIRECT_DIR=y
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
CONFIG_OVERLAY_FS_INDEX=y
CONFIG_OVERLAY_FS_METACOPY=y

#
# Caches
#
CONFIG_NETFS_SUPPORT=m
CONFIG_NETFS_STATS=y
CONFIG_FSCACHE=m
CONFIG_FSCACHE_STATS=y
CONFIG_FSCACHE_DEBUG=y
CONFIG_CACHEFILES=m
CONFIG_CACHEFILES_DEBUG=y
CONFIG_CACHEFILES_ERROR_INJECTION=y
CONFIG_CACHEFILES_ONDEMAND=y
# end of Caches

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
# end of CD-ROM/DVD Filesystems

#
# DOS/FAT/EXFAT/NT Filesystems
#
CONFIG_FAT_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_FAT_KUNIT_TEST=m
CONFIG_EXFAT_FS=m
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_NTFS_FS=m
CONFIG_NTFS_DEBUG=y
CONFIG_NTFS_RW=y
CONFIG_NTFS3_FS=m
CONFIG_NTFS3_LZX_XPRESS=y
CONFIG_NTFS3_FS_POSIX_ACL=y
# end of DOS/FAT/EXFAT/NT Filesystems

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_VMCORE=y
CONFIG_PROC_VMCORE_DEVICE_DUMP=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=m
# end of Pseudo filesystems

CONFIG_MISC_FILESYSTEMS=y
CONFIG_ORANGEFS_FS=m
CONFIG_ADFS_FS=m
CONFIG_ADFS_FS_RW=y
CONFIG_AFFS_FS=m
CONFIG_ECRYPT_FS=m
CONFIG_ECRYPT_FS_MESSAGING=y
CONFIG_HFS_FS=m
CONFIG_HFSPLUS_FS=m
CONFIG_BEFS_FS=m
CONFIG_BEFS_DEBUG=y
CONFIG_BFS_FS=m
CONFIG_EFS_FS=m
CONFIG_JFFS2_FS=m
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
CONFIG_JFFS2_FS_WBUF_VERIFY=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_FS_XATTR=y
CONFIG_JFFS2_FS_POSIX_ACL=y
CONFIG_JFFS2_FS_SECURITY=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RTIME=y
CONFIG_JFFS2_RUBIN=y
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
CONFIG_UBIFS_FS=m
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
CONFIG_UBIFS_ATIME_SUPPORT=y
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_SECURITY=y
CONFIG_UBIFS_FS_AUTHENTICATION=y
CONFIG_CRAMFS=m
CONFIG_CRAMFS_BLOCKDEV=y
CONFIG_CRAMFS_MTD=y
CONFIG_SQUASHFS=m
CONFIG_SQUASHFS_FILE_CACHE=y
# CONFIG_SQUASHFS_FILE_DIRECT is not set
CONFIG_SQUASHFS_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_DECOMP_MULTI is not set
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
CONFIG_SQUASHFS_XATTR=y
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_ZSTD=y
CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
CONFIG_VXFS_FS=m
CONFIG_MINIX_FS=m
CONFIG_MINIX_FS_NATIVE_ENDIAN=y
CONFIG_OMFS_FS=m
CONFIG_HPFS_FS=m
CONFIG_QNX4FS_FS=m
CONFIG_QNX6FS_FS=m
CONFIG_QNX6FS_DEBUG=y
CONFIG_ROMFS_FS=m
CONFIG_ROMFS_BACKED_BY_BLOCK=y
# CONFIG_ROMFS_BACKED_BY_MTD is not set
# CONFIG_ROMFS_BACKED_BY_BOTH is not set
CONFIG_ROMFS_ON_BLOCK=y
CONFIG_PSTORE=m
CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
CONFIG_PSTORE_DEFLATE_COMPRESS=m
CONFIG_PSTORE_LZO_COMPRESS=m
CONFIG_PSTORE_LZ4_COMPRESS=m
CONFIG_PSTORE_LZ4HC_COMPRESS=m
CONFIG_PSTORE_842_COMPRESS=y
CONFIG_PSTORE_ZSTD_COMPRESS=y
CONFIG_PSTORE_COMPRESS=y
CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT is not set
CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
CONFIG_PSTORE_CONSOLE=y
CONFIG_PSTORE_PMSG=y
CONFIG_PSTORE_FTRACE=y
CONFIG_PSTORE_RAM=m
CONFIG_PSTORE_ZONE=m
CONFIG_PSTORE_BLK=m
CONFIG_PSTORE_BLK_BLKDEV=""
CONFIG_PSTORE_BLK_KMSG_SIZE=64
CONFIG_PSTORE_BLK_MAX_REASON=2
CONFIG_PSTORE_BLK_PMSG_SIZE=64
CONFIG_PSTORE_BLK_CONSOLE_SIZE=64
CONFIG_PSTORE_BLK_FTRACE_SIZE=64
CONFIG_SYSV_FS=m
CONFIG_UFS_FS=m
CONFIG_UFS_FS_WRITE=y
CONFIG_UFS_DEBUG=y
CONFIG_EROFS_FS=m
CONFIG_EROFS_FS_DEBUG=y
CONFIG_EROFS_FS_XATTR=y
CONFIG_EROFS_FS_POSIX_ACL=y
CONFIG_EROFS_FS_SECURITY=y
CONFIG_EROFS_FS_ZIP=y
CONFIG_EROFS_FS_ZIP_LZMA=y
CONFIG_EROFS_FS_ONDEMAND=y
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V2=m
CONFIG_NFS_V3=m
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=m
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_PNFS_FILE_LAYOUT=m
CONFIG_PNFS_BLOCK=m
CONFIG_PNFS_FLEXFILE_LAYOUT=m
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
CONFIG_NFS_V4_1_MIGRATION=y
CONFIG_NFS_V4_SECURITY_LABEL=y
CONFIG_NFS_FSCACHE=y
CONFIG_NFS_USE_LEGACY_DNS=y
CONFIG_NFS_DEBUG=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
CONFIG_NFS_V4_2_READ_PLUS=y
CONFIG_NFSD=m
CONFIG_NFSD_V2_ACL=y
CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y
CONFIG_NFSD_PNFS=y
CONFIG_NFSD_BLOCKLAYOUT=y
CONFIG_NFSD_SCSILAYOUT=y
CONFIG_NFSD_FLEXFILELAYOUT=y
CONFIG_NFSD_V4_2_INTER_SSC=y
CONFIG_NFSD_V4_SECURITY_LABEL=y
CONFIG_GRACE_PERIOD=m
CONFIG_LOCKD=m
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=m
CONFIG_NFS_COMMON=y
CONFIG_NFS_V4_2_SSC_HELPER=y
CONFIG_SUNRPC=m
CONFIG_SUNRPC_GSS=m
CONFIG_SUNRPC_BACKCHANNEL=y
CONFIG_RPCSEC_GSS_KRB5=m
CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES=y
CONFIG_SUNRPC_DEBUG=y
CONFIG_CEPH_FS=m
CONFIG_CEPH_FSCACHE=y
CONFIG_CEPH_FS_POSIX_ACL=y
CONFIG_CEPH_FS_SECURITY_LABEL=y
CONFIG_CIFS=m
CONFIG_CIFS_STATS2=y
CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
CONFIG_CIFS_UPCALL=y
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_CIFS_DEBUG=y
CONFIG_CIFS_DEBUG2=y
CONFIG_CIFS_DEBUG_DUMP_KEYS=y
CONFIG_CIFS_DFS_UPCALL=y
CONFIG_CIFS_SWN_UPCALL=y
CONFIG_CIFS_FSCACHE=y
CONFIG_SMB_SERVER=m
CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
CONFIG_SMB_SERVER_KERBEROS5=y
CONFIG_SMBFS_COMMON=m
CONFIG_CODA_FS=m
CONFIG_AFS_FS=m
CONFIG_AFS_DEBUG=y
CONFIG_AFS_FSCACHE=y
CONFIG_AFS_DEBUG_CURSOR=y
CONFIG_9P_FS=m
CONFIG_9P_FSCACHE=y
CONFIG_9P_FS_POSIX_ACL=y
CONFIG_9P_FS_SECURITY=y
CONFIG_NLS=m
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_MAC_ROMAN=m
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=m
CONFIG_NLS_MAC_CYRILLIC=m
CONFIG_NLS_MAC_GAELIC=m
CONFIG_NLS_MAC_GREEK=m
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=m
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=m
CONFIG_DLM=m
CONFIG_DLM_DEPRECATED_API=y
CONFIG_DLM_DEBUG=y
CONFIG_UNICODE=m
CONFIG_UNICODE_NORMALIZATION_SELFTEST=m
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
CONFIG_KEYS_REQUEST_CACHE=y
CONFIG_PERSISTENT_KEYRINGS=y
CONFIG_TRUSTED_KEYS=m
CONFIG_TRUSTED_KEYS_TPM=y
CONFIG_TRUSTED_KEYS_TEE=y
CONFIG_ENCRYPTED_KEYS=y
CONFIG_USER_DECRYPTED_DATA=y
CONFIG_KEY_DH_OPERATIONS=y
CONFIG_KEY_NOTIFICATIONS=y
CONFIG_SECURITY_DMESG_RESTRICT=y
CONFIG_SECURITY=y
CONFIG_SECURITY_WRITABLE_HOOKS=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
CONFIG_SECURITY_NETWORK_XFRM=y
CONFIG_SECURITY_PATH=y
CONFIG_LSM_MMAP_MIN_ADDR=65536
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
CONFIG_HARDENED_USERCOPY=y
CONFIG_STATIC_USERMODEHELPER=y
CONFIG_STATIC_USERMODEHELPER_PATH="/sbin/usermode-helper"
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
CONFIG_SECURITY_SELINUX_DISABLE=y
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
CONFIG_SECURITY_SMACK=y
CONFIG_SECURITY_SMACK_BRINGUP=y
CONFIG_SECURITY_SMACK_NETFILTER=y
CONFIG_SECURITY_SMACK_APPEND_SIGNALS=y
CONFIG_SECURITY_TOMOYO=y
CONFIG_SECURITY_TOMOYO_MAX_ACCEPT_ENTRY=2048
CONFIG_SECURITY_TOMOYO_MAX_AUDIT_LOG=1024
CONFIG_SECURITY_TOMOYO_OMIT_USERSPACE_LOADER=y
CONFIG_SECURITY_TOMOYO_INSECURE_BUILTIN_SETTING=y
CONFIG_SECURITY_APPARMOR=y
CONFIG_SECURITY_APPARMOR_DEBUG=y
CONFIG_SECURITY_APPARMOR_DEBUG_ASSERTS=y
CONFIG_SECURITY_APPARMOR_DEBUG_MESSAGES=y
CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y
CONFIG_SECURITY_APPARMOR_HASH=y
CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y
CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y
CONFIG_SECURITY_LOADPIN=y
CONFIG_SECURITY_LOADPIN_ENFORCE=y
CONFIG_SECURITY_YAMA=y
CONFIG_SECURITY_SAFESETID=y
CONFIG_SECURITY_LOCKDOWN_LSM=y
CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y
CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y
# CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY is not set
# CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY is not set
CONFIG_SECURITY_LANDLOCK=y
CONFIG_INTEGRITY=y
CONFIG_INTEGRITY_SIGNATURE=y
CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y
CONFIG_INTEGRITY_TRUSTED_KEYRING=y
CONFIG_INTEGRITY_PLATFORM_KEYRING=y
CONFIG_INTEGRITY_AUDIT=y
CONFIG_IMA=y
CONFIG_IMA_MEASURE_PCR_IDX=10
CONFIG_IMA_LSM_RULES=y
CONFIG_IMA_NG_TEMPLATE=y
# CONFIG_IMA_SIG_TEMPLATE is not set
CONFIG_IMA_DEFAULT_TEMPLATE="ima-ng"
CONFIG_IMA_DEFAULT_HASH_SHA1=y
# CONFIG_IMA_DEFAULT_HASH_SHA256 is not set
# CONFIG_IMA_DEFAULT_HASH_SHA512 is not set
CONFIG_IMA_DEFAULT_HASH="sha1"
CONFIG_IMA_WRITE_POLICY=y
CONFIG_IMA_READ_POLICY=y
CONFIG_IMA_APPRAISE=y
CONFIG_IMA_ARCH_POLICY=y
CONFIG_IMA_APPRAISE_BUILD_POLICY=y
CONFIG_IMA_APPRAISE_REQUIRE_FIRMWARE_SIGS=y
CONFIG_IMA_APPRAISE_REQUIRE_KEXEC_SIGS=y
CONFIG_IMA_APPRAISE_REQUIRE_MODULE_SIGS=y
CONFIG_IMA_APPRAISE_REQUIRE_POLICY_SIGS=y
CONFIG_IMA_APPRAISE_BOOTPARAM=y
CONFIG_IMA_APPRAISE_MODSIG=y
CONFIG_IMA_TRUSTED_KEYRING=y
CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY=y
CONFIG_IMA_BLACKLIST_KEYRING=y
CONFIG_IMA_LOAD_X509=y
CONFIG_IMA_X509_PATH="/etc/keys/x509_ima.der"
CONFIG_IMA_APPRAISE_SIGNED_INIT=y
CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y
CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y
CONFIG_IMA_DISABLE_HTABLE=y
CONFIG_EVM=y
CONFIG_EVM_ATTR_FSUUID=y
CONFIG_EVM_EXTRA_SMACK_XATTRS=y
CONFIG_EVM_ADD_XATTRS=y
CONFIG_EVM_LOAD_X509=y
CONFIG_EVM_X509_PATH="/etc/keys/x509_evm.der"
CONFIG_DEFAULT_SECURITY_SELINUX=y
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
# CONFIG_DEFAULT_SECURITY_APPARMOR is not set
# CONFIG_DEFAULT_SECURITY_DAC is not set
CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor,bpf"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
# CONFIG_INIT_STACK_NONE is not set
CONFIG_INIT_STACK_ALL_PATTERN=y
# CONFIG_INIT_STACK_ALL_ZERO is not set
CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y
CONFIG_INIT_ON_FREE_DEFAULT_ON=y
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
CONFIG_ZERO_CALL_USED_REGS=y
# end of Memory initialization

CONFIG_RANDSTRUCT_NONE=y
# end of Kernel hardening options
# end of Security options

CONFIG_XOR_BLOCKS=m
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=m
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=m
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=m
CONFIG_CRYPTO_NULL=m
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_CRYPTD=m
CONFIG_CRYPTO_AUTHENC=m
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_ENGINE=m
# end of Crypto core or helper

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
CONFIG_CRYPTO_ECC=m
CONFIG_CRYPTO_ECDH=m
CONFIG_CRYPTO_ECDSA=m
CONFIG_CRYPTO_ECRDSA=m
CONFIG_CRYPTO_SM2=m
CONFIG_CRYPTO_CURVE25519=m
# end of Public-key cryptography

#
# Block ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=m
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_ARIA=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_BLOWFISH_COMMON=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST_COMMON=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=m
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_SM4=m
CONFIG_CRYPTO_SM4_GENERIC=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_TWOFISH_COMMON=m
# end of Block ciphers

#
# Length-preserving ciphers and modes
#
CONFIG_CRYPTO_ADIANTUM=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_CHACHA20=m
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=m
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=m
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_HCTR2=m
CONFIG_CRYPTO_KEYWRAP=m
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_OFB=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XCTR=m
CONFIG_CRYPTO_XTS=m
CONFIG_CRYPTO_NHPOLY1305=m
# end of Length-preserving ciphers and modes

#
# AEAD (authenticated encryption with associated data) ciphers
#
CONFIG_CRYPTO_AEGIS128=m
CONFIG_CRYPTO_CHACHA20POLY1305=m
CONFIG_CRYPTO_CCM=m
CONFIG_CRYPTO_GCM=m
CONFIG_CRYPTO_SEQIV=m
CONFIG_CRYPTO_ECHAINIV=m
CONFIG_CRYPTO_ESSIV=m
# end of AEAD (authenticated encryption with associated data) ciphers

#
# Hashes, digests, and MACs
#
CONFIG_CRYPTO_BLAKE2B=m
CONFIG_CRYPTO_CMAC=m
CONFIG_CRYPTO_GHASH=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_POLYVAL=m
CONFIG_CRYPTO_POLY1305=m
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=m
CONFIG_CRYPTO_SM3=m
CONFIG_CRYPTO_SM3_GENERIC=m
CONFIG_CRYPTO_STREEBOG=m
CONFIG_CRYPTO_VMAC=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_XXHASH=m
# end of Hashes, digests, and MACs

#
# CRCs (cyclic redundancy checks)
#
CONFIG_CRYPTO_CRC32C=m
CONFIG_CRYPTO_CRC32=m
CONFIG_CRYPTO_CRCT10DIF=m
CONFIG_CRYPTO_CRC64_ROCKSOFT=m
# end of CRCs (cyclic redundancy checks)

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=m
CONFIG_CRYPTO_LZO=m
CONFIG_CRYPTO_842=m
CONFIG_CRYPTO_LZ4=m
CONFIG_CRYPTO_LZ4HC=m
CONFIG_CRYPTO_ZSTD=m
# end of Compression

#
# Random number generation
#
CONFIG_CRYPTO_ANSI_CPRNG=m
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_KDF800108_CTR=y
# end of Random number generation

#
# Userspace interface
#
CONFIG_CRYPTO_USER_API=m
CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=m
CONFIG_CRYPTO_USER_API_RNG=m
CONFIG_CRYPTO_USER_API_RNG_CAVP=y
CONFIG_CRYPTO_USER_API_AEAD=m
CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
CONFIG_CRYPTO_STATS=y
# end of Userspace interface

CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_ALLWINNER=y
CONFIG_CRYPTO_DEV_SUN8I_CE=m
CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG=y
CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y
CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
CONFIG_CRYPTO_DEV_SUN8I_SS=m
CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG=y
CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y
CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y
CONFIG_CRYPTO_DEV_SL3516=m
CONFIG_CRYPTO_DEV_SL3516_DEBUG=y
CONFIG_CRYPTO_DEV_EXYNOS_RNG=m
CONFIG_CRYPTO_DEV_S5P=m
CONFIG_CRYPTO_DEV_ATMEL_AUTHENC=y
CONFIG_CRYPTO_DEV_ATMEL_AES=m
CONFIG_CRYPTO_DEV_ATMEL_TDES=m
CONFIG_CRYPTO_DEV_ATMEL_SHA=m
CONFIG_CRYPTO_DEV_ATMEL_I2C=m
CONFIG_CRYPTO_DEV_ATMEL_ECC=m
CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m
CONFIG_CRYPTO_DEV_QCE=m
CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SHA=y
CONFIG_CRYPTO_DEV_QCE_AEAD=y
CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER is not set
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
CONFIG_CRYPTO_DEV_QCOM_RNG=m
CONFIG_CRYPTO_DEV_IMGTEC_HASH=m
CONFIG_CRYPTO_DEV_ZYNQMP_AES=m
CONFIG_CRYPTO_DEV_ZYNQMP_SHA3=m
CONFIG_CRYPTO_DEV_VIRTIO=m
CONFIG_CRYPTO_DEV_SAFEXCEL=m
CONFIG_CRYPTO_DEV_HISI_SEC=m
CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG=y
CONFIG_CRYPTO_DEV_SA2UL=m
CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4=m
CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_ECB=y
CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_CTS=y
CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECC=m
CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU=m
CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224=y
CONFIG_CRYPTO_DEV_ASPEED=m
CONFIG_CRYPTO_DEV_ASPEED_DEBUG=y
CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH=y
CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO=y
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
CONFIG_PKCS7_MESSAGE_PARSER=y
CONFIG_PKCS7_TEST_KEY=m
CONFIG_SIGNED_PE_FILE_VERIFICATION=y
CONFIG_FIPS_SIGNATURE_SELFTEST=y

#
# Certificates for signature checking
#
CONFIG_MODULE_SIG_KEY="certs/signing_key.pem"
CONFIG_MODULE_SIG_KEY_TYPE_RSA=y
# CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
CONFIG_SYSTEM_EXTRA_CERTIFICATE=y
CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096
CONFIG_SECONDARY_TRUSTED_KEYRING=y
CONFIG_SYSTEM_BLACKLIST_KEYRING=y
CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
CONFIG_SYSTEM_REVOCATION_LIST=y
CONFIG_SYSTEM_REVOCATION_KEYS=""
CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y
# end of Certificates for signature checking

CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_RAID6_PQ=m
CONFIG_RAID6_PQ_BENCHMARK=y
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=m
CONFIG_PRIME_NUMBERS=m
CONFIG_RATIONAL=m
CONFIG_STMP_DEVICE=y

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_ARC4=m
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
CONFIG_CRYPTO_LIB_CHACHA=m
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
CONFIG_CRYPTO_LIB_CURVE25519=m
CONFIG_CRYPTO_LIB_DES=m
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
CONFIG_CRYPTO_LIB_POLY1305=m
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines

CONFIG_CRC_CCITT=m
CONFIG_CRC16=m
CONFIG_CRC_T10DIF=m
CONFIG_CRC64_ROCKSOFT=m
CONFIG_CRC_ITU_T=m
CONFIG_CRC32=y
CONFIG_CRC32_SELFTEST=m
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=m
CONFIG_CRC4=m
CONFIG_CRC7=m
CONFIG_LIBCRC32C=m
CONFIG_CRC8=m
CONFIG_XXHASH=y
CONFIG_AUDIT_GENERIC=y
CONFIG_RANDOM32_SELFTEST=y
CONFIG_842_COMPRESS=m
CONFIG_842_DECOMPRESS=m
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=m
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=m
CONFIG_LZ4HC_COMPRESS=m
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=m
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
CONFIG_XZ_DEC_X86=y
CONFIG_XZ_DEC_POWERPC=y
CONFIG_XZ_DEC_IA64=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_XZ_DEC_SPARC=y
CONFIG_XZ_DEC_MICROLZMA=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_XZ_DEC_TEST=m
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_REED_SOLOMON=m
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_REED_SOLOMON_ENC16=y
CONFIG_REED_SOLOMON_DEC16=y
CONFIG_BCH=m
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_BTREE=y
CONFIG_INTERVAL_TREE=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_NO_DMA=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_API_DEBUG=y
CONFIG_DMA_API_DEBUG_SG=y
CONFIG_DMA_MAP_BENCHMARK=y
CONFIG_SGL_ALLOC=y
CONFIG_DQL=y
CONFIG_GLOB=y
CONFIG_GLOB_SELFTEST=m
CONFIG_NLATTR=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_LRU_CACHE=m
CONFIG_CLZ_TAB=y
CONFIG_IRQ_POLL=y
CONFIG_MPILIB=y
CONFIG_SIGNATURE=y
CONFIG_DIMLIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_FONT_SUPPORT=m
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_FONT_6x11=y
CONFIG_FONT_7x14=y
CONFIG_FONT_PEARL_8x8=y
CONFIG_FONT_ACORN_8x8=y
CONFIG_FONT_MINI_4x6=y
CONFIG_FONT_6x10=y
CONFIG_FONT_10x18=y
CONFIG_FONT_SUN8x16=y
CONFIG_FONT_SUN12x22=y
CONFIG_FONT_TER16x32=y
CONFIG_FONT_6x8=y
CONFIG_SG_SPLIT=y
CONFIG_SG_POOL=y
CONFIG_STACKDEPOT=y
CONFIG_STACKDEPOT_ALWAYS_INIT=y
CONFIG_REF_TRACKER=y
CONFIG_SBITMAP=y
CONFIG_PARMAN=m
CONFIG_OBJAGG=m
# end of Library routines

CONFIG_ASN1_ENCODER=m
CONFIG_POLYNOMIAL=m

#
# Kernel hacking
#

#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
CONFIG_PRINTK_CALLER=y
CONFIG_STACKTRACE_BUILD_ID=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y

#
# Compile-time checks and compiler options
#
CONFIG_AS_HAS_NON_CONST_LEB128=y
CONFIG_DEBUG_INFO_NONE=y
# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_DEBUG_INFO_DWARF5 is not set
CONFIG_FRAME_WARN=1024
CONFIG_STRIP_ASM_SYMS=y
CONFIG_READABLE_ASM=y
CONFIG_HEADERS_INSTALL=y
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
CONFIG_FRAME_POINTER=y
CONFIG_VMLINUX_MAP=y
CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_KGDB=y
CONFIG_KGDB_HONOUR_BLOCKLIST=y
CONFIG_KGDB_SERIAL_CONSOLE=m
CONFIG_KGDB_TESTS=y
CONFIG_KGDB_TESTS_ON_BOOT=y
CONFIG_KGDB_TESTS_BOOT_STRING="V1F100"
CONFIG_KGDB_KDB=y
CONFIG_KDB_DEFAULT_ENABLE=0x1
CONFIG_KDB_KEYBOARD=y
CONFIG_KDB_CONTINUE_CATASTROPHIC=0
CONFIG_UBSAN=y
CONFIG_CC_HAS_UBSAN_BOUNDS=y
CONFIG_UBSAN_BOUNDS=y
CONFIG_UBSAN_ONLY_BOUNDS=y
CONFIG_UBSAN_SHIFT=y
CONFIG_UBSAN_DIV_ZERO=y
CONFIG_UBSAN_UNREACHABLE=y
CONFIG_UBSAN_BOOL=y
CONFIG_UBSAN_ENUM=y
CONFIG_TEST_UBSAN=m
CONFIG_HAVE_KCSAN_COMPILER=y
# end of Generic Kernel Debugging Instruments

#
# Networking Debugging
#
CONFIG_NET_DEV_REFCNT_TRACKER=y
CONFIG_NET_NS_REFCNT_TRACKER=y
CONFIG_DEBUG_NET=y
# end of Networking Debugging

#
# Memory Debugging
#
CONFIG_PAGE_EXTENSION=y
CONFIG_DEBUG_PAGEALLOC=y
CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y
CONFIG_SLUB_DEBUG=y
CONFIG_SLUB_DEBUG_ON=y
CONFIG_PAGE_OWNER=y
CONFIG_PAGE_POISONING=y
CONFIG_DEBUG_PAGE_REF=y
CONFIG_DEBUG_OBJECTS=y
CONFIG_DEBUG_OBJECTS_SELFTEST=y
CONFIG_DEBUG_OBJECTS_FREE=y
CONFIG_DEBUG_OBJECTS_TIMERS=y
CONFIG_DEBUG_OBJECTS_WORK=y
CONFIG_DEBUG_OBJECTS_RCU_HEAD=y
CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y
CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1
CONFIG_SHRINKER_DEBUG=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_DEBUG_KMEMLEAK=y
CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000
CONFIG_DEBUG_KMEMLEAK_TEST=m
CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y
CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_SCHED_STACK_END_CHECK=y
CONFIG_DEBUG_VM_IRQSOFF=y
CONFIG_DEBUG_VM=y
CONFIG_DEBUG_VM_MAPLE_TREE=y
CONFIG_DEBUG_VM_RB=y
CONFIG_DEBUG_VM_PGFLAGS=y
CONFIG_DEBUG_NOMMU_REGIONS=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# end of Memory Debugging

CONFIG_DEBUG_SHIRQ=y

#
# Debug Oops, Lockups and Hangs
#
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_ON_OOPS_VALUE=1
CONFIG_PANIC_TIMEOUT=0
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
CONFIG_WQ_WATCHDOG=y
CONFIG_TEST_LOCKUP=m
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
CONFIG_SCHED_DEBUG=y
CONFIG_SCHED_INFO=y
CONFIG_SCHEDSTATS=y
# end of Scheduler Debugging

CONFIG_DEBUG_TIMEKEEPING=y

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_PROVE_LOCKING=y
CONFIG_PROVE_RAW_LOCK_NESTING=y
CONFIG_LOCK_STAT=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y
CONFIG_DEBUG_RWSEMS=y
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_LOCKDEP=y
CONFIG_LOCKDEP_BITS=15
CONFIG_LOCKDEP_CHAINS_BITS=16
CONFIG_LOCKDEP_STACK_TRACE_BITS=19
CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14
CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12
CONFIG_DEBUG_LOCKDEP=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
CONFIG_DEBUG_LOCKING_API_SELFTESTS=y
CONFIG_LOCK_TORTURE_TEST=m
CONFIG_WW_MUTEX_SELFTEST=m
CONFIG_SCF_TORTURE_TEST=m
# end of Lock Debugging (spinlocks, mutexes, etc...)

CONFIG_TRACE_IRQFLAGS=y
CONFIG_DEBUG_IRQFLAGS=y
CONFIG_STACKTRACE=y
CONFIG_WARN_ALL_UNSEEDED_RANDOM=y
CONFIG_DEBUG_KOBJECT=y
CONFIG_DEBUG_KOBJECT_RELEASE=y
CONFIG_HAVE_DEBUG_BUGVERBOSE=y

#
# Debug kernel data structures
#
CONFIG_DEBUG_LIST=y
CONFIG_DEBUG_PLIST=y
CONFIG_DEBUG_SG=y
CONFIG_DEBUG_NOTIFIERS=y
CONFIG_BUG_ON_DATA_CORRUPTION=y
CONFIG_DEBUG_MAPLE_TREE=y
# end of Debug kernel data structures

CONFIG_DEBUG_CREDENTIALS=y

#
# RCU Debugging
#
CONFIG_PROVE_RCU=y
CONFIG_PROVE_RCU_LIST=y
CONFIG_TORTURE_TEST=m
CONFIG_RCU_SCALE_TEST=m
CONFIG_RCU_TORTURE_TEST=m
CONFIG_RCU_REF_SCALE_TEST=m
CONFIG_RCU_TRACE=y
CONFIG_RCU_EQS_DEBUG=y
# end of RCU Debugging

CONFIG_DEBUG_WQ_FORCE_RR_CPU=y
CONFIG_LATENCYTOP=y
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_TRACER_MAX_TRACE=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_RING_BUFFER_ALLOW_SWAP=y
CONFIG_PREEMPTIRQ_TRACEPOINTS=y
CONFIG_TRACING=y
CONFIG_GENERIC_TRACER=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
CONFIG_BOOTTIME_TRACING=y
CONFIG_FUNCTION_TRACER=y
CONFIG_FUNCTION_GRAPH_TRACER=y
CONFIG_DYNAMIC_FTRACE=y
CONFIG_FUNCTION_PROFILER=y
CONFIG_STACK_TRACER=y
CONFIG_IRQSOFF_TRACER=y
CONFIG_SCHED_TRACER=y
CONFIG_HWLAT_TRACER=y
CONFIG_OSNOISE_TRACER=y
CONFIG_TIMERLAT_TRACER=y
CONFIG_FTRACE_SYSCALLS=y
CONFIG_TRACER_SNAPSHOT=y
CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_KPROBE_EVENTS=y
CONFIG_KPROBE_EVENTS_ON_NOTRACE=y
CONFIG_BPF_EVENTS=y
CONFIG_DYNAMIC_EVENTS=y
CONFIG_PROBE_EVENTS=y
CONFIG_FTRACE_MCOUNT_RECORD=y
CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT=y
CONFIG_SYNTH_EVENTS=y
CONFIG_USER_EVENTS=y
CONFIG_TRACE_EVENT_INJECT=y
CONFIG_TRACEPOINT_BENCHMARK=y
CONFIG_RING_BUFFER_BENCHMARK=m
CONFIG_TRACE_EVAL_MAP_FILE=y
CONFIG_FTRACE_RECORD_RECURSION=y
CONFIG_FTRACE_RECORD_RECURSION_SIZE=128
CONFIG_RING_BUFFER_RECORD_RECURSION=y
CONFIG_GCOV_PROFILE_FTRACE=y
CONFIG_FTRACE_SELFTEST=y
CONFIG_FTRACE_STARTUP_TEST=y
CONFIG_EVENT_TRACE_STARTUP_TEST=y
CONFIG_EVENT_TRACE_TEST_SYSCALLS=y
CONFIG_RING_BUFFER_STARTUP_TEST=y
CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS=y
CONFIG_PREEMPTIRQ_DELAY_TEST=m
CONFIG_SYNTH_EVENT_GEN_TEST=m
CONFIG_KPROBE_EVENT_GEN_TEST=m
CONFIG_DA_MON_EVENTS=y
CONFIG_DA_MON_EVENTS_ID=y
CONFIG_RV=y
CONFIG_RV_MON_WWNR=y
CONFIG_RV_REACTORS=y
CONFIG_RV_REACT_PRINTK=y
CONFIG_RV_REACT_PANIC=y
# CONFIG_SAMPLES is not set
# CONFIG_STRICT_DEVMEM is not set

#
# sh Debugging
#
CONFIG_SH_STANDARD_BIOS=y
CONFIG_STACK_DEBUG=y
CONFIG_DUMP_CODE=y
CONFIG_DWARF_UNWINDER=y
CONFIG_SH_NO_BSS_INIT=y
CONFIG_MCOUNT=y
# end of sh Debugging

#
# Kernel Testing and Coverage
#
CONFIG_KUNIT=m
CONFIG_KUNIT_DEBUGFS=y
CONFIG_KUNIT_TEST=m
CONFIG_KUNIT_EXAMPLE_TEST=m
CONFIG_KUNIT_ALL_TESTS=m
CONFIG_KUNIT_DEFAULT_ENABLED=y
CONFIG_NOTIFIER_ERROR_INJECTION=m
CONFIG_PM_NOTIFIER_ERROR_INJECT=m
CONFIG_OF_RECONFIG_NOTIFIER_ERROR_INJECT=m
CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=m
CONFIG_FAULT_INJECTION=y
CONFIG_FAILSLAB=y
CONFIG_FAIL_PAGE_ALLOC=y
CONFIG_FAULT_INJECTION_USERCOPY=y
CONFIG_FAIL_MAKE_REQUEST=y
CONFIG_FAIL_IO_TIMEOUT=y
CONFIG_FAIL_FUTEX=y
CONFIG_FAULT_INJECTION_DEBUG_FS=y
CONFIG_FAIL_MMC_REQUEST=y
CONFIG_FAIL_SUNRPC=y
CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
CONFIG_RUNTIME_TESTING_MENU=y
CONFIG_LKDTM=m
CONFIG_CPUMASK_KUNIT_TEST=m
CONFIG_TEST_LIST_SORT=m
CONFIG_TEST_MIN_HEAP=m
CONFIG_TEST_SORT=m
CONFIG_TEST_DIV64=m
CONFIG_KPROBES_SANITY_TEST=m
CONFIG_BACKTRACE_SELF_TEST=m
CONFIG_TEST_REF_TRACKER=m
CONFIG_RBTREE_TEST=m
CONFIG_REED_SOLOMON_TEST=m
CONFIG_INTERVAL_TREE_TEST=m
CONFIG_PERCPU_TEST=m
CONFIG_ATOMIC64_SELFTEST=m
CONFIG_ASYNC_RAID6_TEST=m
CONFIG_TEST_HEXDUMP=m
CONFIG_STRING_SELFTEST=m
CONFIG_TEST_STRING_HELPERS=m
CONFIG_TEST_STRSCPY=m
CONFIG_TEST_KSTRTOX=m
CONFIG_TEST_PRINTF=m
CONFIG_TEST_SCANF=m
CONFIG_TEST_BITMAP=m
CONFIG_TEST_UUID=m
CONFIG_TEST_XARRAY=m
CONFIG_TEST_MAPLE_TREE=m
CONFIG_TEST_RHASHTABLE=m
CONFIG_TEST_SIPHASH=m
CONFIG_TEST_IDA=m
CONFIG_TEST_PARMAN=m
CONFIG_TEST_LKM=m
CONFIG_TEST_BITOPS=m
CONFIG_TEST_USER_COPY=m
CONFIG_TEST_BPF=m
CONFIG_TEST_BLACKHOLE_DEV=m
CONFIG_FIND_BIT_BENCHMARK=m
CONFIG_TEST_FIRMWARE=m
CONFIG_TEST_SYSCTL=m
CONFIG_BITFIELD_KUNIT=m
CONFIG_HASH_KUNIT_TEST=m
CONFIG_RESOURCE_KUNIT_TEST=m
CONFIG_SYSCTL_KUNIT_TEST=m
CONFIG_LIST_KUNIT_TEST=m
CONFIG_LINEAR_RANGES_TEST=m
CONFIG_CMDLINE_KUNIT_TEST=m
CONFIG_BITS_TEST=m
CONFIG_SLUB_KUNIT_TEST=m
CONFIG_RATIONAL_KUNIT_TEST=m
CONFIG_MEMCPY_KUNIT_TEST=m
CONFIG_IS_SIGNED_TYPE_KUNIT_TEST=m
CONFIG_OVERFLOW_KUNIT_TEST=m
CONFIG_STACKINIT_KUNIT_TEST=m
CONFIG_TEST_UDELAY=m
CONFIG_TEST_STATIC_KEYS=m
CONFIG_TEST_DYNAMIC_DEBUG=m
CONFIG_TEST_KMOD=m
CONFIG_TEST_MEMCAT_P=m
CONFIG_TEST_OBJAGG=m
CONFIG_TEST_MEMINIT=m
CONFIG_TEST_FREE_PAGES=m
# end of Kernel Testing and Coverage

#
# Rust hacking
#
# end of Rust hacking

CONFIG_WARN_MISSING_DOCUMENTS=y
CONFIG_WARN_ABI_ERRORS=y
# end of Kernel hacking

Re: [PATCH V6 5/5] ASoC: dt-bindings: Add schema for "awinic, aw883xx"

[Rob Herring]

On Thu, Dec 8, 2022 at 6:28 AM <wangweidong.a@awinic.com> wrote:
>
> From: Weidong Wang <wangweidong.a@awinic.com>
>
> Add a DT schema for describing Awinic AW883xx audio amplifiers. They are
> controlled using I2C.

blank line

Pretty sure I said this before, but resend to the DT list if you want
this reviewed.

> Signed-off-by: Weidong Wang <wangweidong.a@awinic.com>
> ---
>  .../bindings/sound/awinic,aw883xx.yaml        | 49 +++++++++++++++++++
>  1 file changed, 49 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml
>
> diff --git a/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml b/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml
> new file mode 100644
> index 000000000000..b72c9177ebb7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml
> @@ -0,0 +1,49 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sound/awinic,aw883xx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Awinic AW883xx Smart Audio Amplifier
> +
> +maintainers:
> +  - Stephan Gerhold <stephan@gerhold.net>
> +
> +description:
> +  The Awinic AW883XX is an I2S/TDM input, high efficiency
> +  digital Smart K audio amplifier with an integrated 10.25V
> +  smart boost convert.
> +
> +allOf:
> +  - $ref: name-prefix.yaml#

I think this file has now been renamed upstream.

Re: [PATCH V6 1/5] ASoC: codecs: Add i2c and codec registration for aw883xx and their associated operation functions

[wangweidong.a]

On 12/8/2022 1:23 PM, wangweidong.a@awinic.com wrote:
> From: Weidong Wang <wangweidong.a@awinic.com>
> 
> The Awinic AW883XX is an I2S/TDM input, high efficiency
> digital Smart K audio amplifier with an integrated 10.25V
> smart boost convert
> 
> Signed-off-by: Nick Li <liweilei@awinic.com>
> Signed-off-by: Bruce zhao <zhaolei@awinic.com>
> Signed-off-by: Weidong Wang <wangweidong.a@awinic.com>
> ---
>   sound/soc/codecs/aw883xx/aw883xx.c | 909 +++++++++++++++++++++++++++++
>   sound/soc/codecs/aw883xx/aw883xx.h |  81 +++
>   2 files changed, 990 insertions(+)
>   create mode 100644 sound/soc/codecs/aw883xx/aw883xx.c
>   create mode 100644 sound/soc/codecs/aw883xx/aw883xx.h
> 
> diff --git a/sound/soc/codecs/aw883xx/aw883xx.c b/sound/soc/codecs/aw883xx/aw883xx.c
> new file mode 100644
> index 000000000000..f82e6d8c71a7
> --- /dev/null
> +++ b/sound/soc/codecs/aw883xx/aw883xx.c
> @@ -0,0 +1,909 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * aw883xx.c --  ALSA Soc AW883XX codec support

> Soc -> SoC

I will change it on patch v7

> + *
> + * Copyright (c) 2022 AWINIC Technology CO., LTD
> + *
> + * Author: Bruce zhao <zhaolei@awinic.com>
> + */
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/debugfs.h>
> +#include <linux/firmware.h>
> +#include <linux/hrtimer.h>
> +#include <linux/i2c.h>
> +#include <linux/input.h>
> +#include <linux/module.h>
> +#include <linux/of_gpio.h>
> +#include <linux/regmap.h>
> +#include <linux/syscalls.h>
> +#include <linux/timer.h>
> +#include <linux/uaccess.h>
> +#include <linux/version.h>
> +#include <linux/vmalloc.h>
> +#include <linux/workqueue.h>

> Are all those headers really needed? Just picking few, for example 
> debugfs.h, version.h and vmalloc.h seems unnecessary to me, and I 
> suspect few more can be removed.

I will change it on patch v7

> +#include <sound/core.h>
> +#include <sound/pcm.h>
> +#include <sound/pcm_params.h>
> +#include <sound/soc.h>
> +#include <sound/tlv.h>
> +#include "aw883xx_pid_2049_reg.h"
> +#include "aw883xx.h"
> +#include "aw883xx_bin_parse.h"
> +#include "aw883xx_device.h"
> +
> +static const struct regmap_config aw883xx_remap_config = {
> +	.val_bits = 16,
> +	.reg_bits = 8,
> +	.max_register = AW_PID_2049_REG_MAX - 1,
> +};
> +
> +/*
> + * aw883xx dsp write/read
> + */
> +static int aw883xx_dsp_write_16bit(struct aw883xx *aw883xx,
> +		unsigned short dsp_addr, unsigned int dsp_data)
> +{
> +	int ret;
> +	struct aw_dsp_mem_desc *desc = &aw883xx->aw_pa->dsp_mem_desc;
> +
> +	ret = regmap_write(aw883xx->regmap, desc->dsp_madd_reg, dsp_addr);
> +	if (ret < 0) {
> +		dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret);
> +		return ret;
> +	}
> +
> +	ret = regmap_write(aw883xx->regmap, desc->dsp_mdat_reg, (u16)dsp_data);
> +	if (ret < 0) {
> +		dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int aw883xx_dsp_write_32bit(struct aw883xx *aw883xx,
> +		unsigned short dsp_addr, unsigned int dsp_data)
> +{
> +	int ret;
> +	u16 temp_data = 0;
> +	struct aw_dsp_mem_desc *desc = &aw883xx->aw_pa->dsp_mem_desc;
> +
> +	ret = regmap_write(aw883xx->regmap, desc->dsp_madd_reg, dsp_addr);
> +	if (ret < 0) {
> +		dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret);
> +		return ret;
> +	}
> +
> +	temp_data = dsp_data & AW_DSP_16_DATA_MASK;
> +	ret = regmap_write(aw883xx->regmap, desc->dsp_mdat_reg, temp_data);
> +	if (ret < 0) {
> +		dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret);
> +		return ret;
> +	}
> +
> +	temp_data = dsp_data >> 16;
> +	ret = regmap_write(aw883xx->regmap, desc->dsp_mdat_reg, temp_data);
> +	if (ret < 0) {
> +		dev_err(aw883xx->dev, "%s error, ret=%d", __func__, ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +/*
> + * aw883xx clear dsp chip select state
> + */
> +static void aw883xx_clear_dsp_sel_st(struct aw883xx *aw883xx)
> +{
> +	unsigned int reg_value;
> +	u8 reg = aw883xx->aw_pa->soft_rst.reg;
> +
> +	regmap_read(aw883xx->regmap, reg, &reg_value);
> +}

> Is it enough to just read register to clear it?

Yes, this is because our chip hardware design,
just need to read, the hardware can automatically clear the register value

> +
> +int aw883xx_dsp_write(struct aw883xx *aw883xx,
> +		unsigned short dsp_addr, unsigned int dsp_data, unsigned char data_type)
> +{
> +	int ret = -1;


> No need to set "-1" value here, as following switch always sets ret and 
> -1 == -EPERM, which may lead to some confusion if something is changed 
> later and ret is returned. If you want to set it to anything, just set 
> it to -EINVAL.

> There is few more places in the patch, where ret is initialized to -1 
> only to be overwritten later, I won't mark them all, but it seems weird 
> to me and should probably be fixed.

I will change it on patch v7

> +
> +	mutex_lock(&aw883xx->dsp_lock);
> +	switch (data_type) {
> +	case AW_DSP_16_DATA:
> +		ret = aw883xx_dsp_write_16bit(aw883xx, dsp_addr, dsp_data);
> +		if (ret < 0)
> +			dev_err(aw883xx->dev, "write dsp_addr[0x%04x] 16 bit dsp_data[%04x] failed",
> +					(u32)dsp_addr, dsp_data);
> +		break;
> +	case AW_DSP_32_DATA:
> +		ret =  aw883xx_dsp_write_32bit(aw883xx, dsp_addr, dsp_data);

> remove double space after '='

I will change it on patch v7

> +		if (ret < 0)
> +			dev_err(aw883xx->dev, "write dsp_addr[0x%04x] 32 bit dsp_data[%08x] failed",
> +					(u32)dsp_addr, dsp_data);
> +		break;
> +	default:
> +		dev_err(aw883xx->dev, "data type[%d] unsupported", data_type);
> +		ret = -EINVAL;
> +		break;
> +	}
> +
> +	aw883xx_clear_dsp_sel_st(aw883xx);
> +	mutex_unlock(&aw883xx->dsp_lock);
> +	return ret;
> +}
> +

(...)

> diff --git a/sound/soc/codecs/aw883xx/aw883xx.h b/sound/soc/codecs/aw883xx/aw883xx.h
> new file mode 100644
> index 000000000000..209851cae7ef
> --- /dev/null
> +++ b/sound/soc/codecs/aw883xx/aw883xx.h
> @@ -0,0 +1,81 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * aw883xx.c --  ALSA Soc AW883XX codec support

> Soc -> SoC

I will change it on patch v7

> + *
> + * Copyright (c) 2022 AWINIC Technology CO., LTD
> + *
> + * Author: Bruce zhao <zhaolei@awinic.com>
> + */
> +
> +#ifndef __AW883XX_H__
> +#define __AW883XX_H__
> +
> +#include <linux/version.h>

> This header should be unnecessary

I will change it on patch v7

> +#include <sound/control.h>
> +#include <sound/soc.h>
> +#include "aw883xx_data_type.h"
> +
> +#define AW_CHIP_ID_REG			(0x00)
> +#define AW_START_RETRIES			(5)
> +#define AW_START_WORK_DELAY_MS	(0)
> +
> +#define AW_DSP_16_DATA_MASK	(0x0000ffff)
> +
> +#define AW_I2C_NAME "aw883xx_smartpa"
> +
> +#define AW_RATES (SNDRV_PCM_RATE_8000_48000 | \
> +			SNDRV_PCM_RATE_96000)
> +#define AW_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
> +			SNDRV_PCM_FMTBIT_S24_LE | \
> +			SNDRV_PCM_FMTBIT_S32_LE)
> +#define AW_REQUEST_FW_RETRIES		5	/* 5 times */

> Unnecessary comment

I will change it on patch v7

> +#define AW_SYNC_LOAD
> +
> +#define FADE_TIME_MAX 100000
> +#define FADE_TIME_MIN 0
> +
> +#define AW_PROFILE_EXT(xname, profile_info, profile_get, profile_set) \
> +{ \
> +	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
> +	.name = xname, \
> +	.info = profile_info, \
> +	.get = profile_get, \
> +	.put = profile_set, \
> +}
> +
> +enum {
> +	AW_SYNC_START = 0,
> +	AW_ASYNC_START,
> +};
> +
> +enum {
> +	AW883XX_STREAM_CLOSE = 0,
> +	AW883XX_STREAM_OPEN,
> +};
> +
> +struct aw883xx {
> +	struct i2c_client *i2c;
> +	struct device *dev;
> +	struct mutex lock;
> +	struct mutex dsp_lock;
> +	struct snd_soc_component *codec;
> +	struct aw_device *aw_pa;
> +	struct gpio_desc *reset_gpio;
> +	unsigned char phase_sync;	/*phase sync*/

> Also unnecessary comment

I will change it on patch v7

> +	bool allow_pw;
> +	u8 pstream;
> +	struct workqueue_struct *work_queue;
> +	struct delayed_work start_work;
> +	u16 chip_id;
> +	struct regmap *regmap;
> +	struct aw_container *aw_cfg;
> +};
> +
> +int aw883xx_init(struct aw883xx *aw883xx);
> +
> +int aw883xx_dsp_write(struct aw883xx *aw883xx,
> +		unsigned short dsp_addr, unsigned int dsp_data, unsigned char data_type);
> +int aw883xx_dsp_read(struct aw883xx *aw883xx,
> +		unsigned short dsp_addr, unsigned int *dsp_data, unsigned char data_type);
> +
> +#endif

Thank you very much for your advice

Best regards,
Weidong Wang

Re: [PATCH V6 2/5] ASoC: codecs: Implementation of aw883xx configuration file parsing function

[wangweidong.a]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 28880 bytes --]

On 12/8/2022 1:23 PM, wangweidong.a@awinic.com wrote:
> From: Weidong Wang <wangweidong.a@awinic.com>
> 
> The Awinic AW883XX is an I2S/TDM input, high efficiency
> digital Smart K audio amplifier with an integrated 10.25V
> smart boost convert
> 
> Signed-off-by: Nick Li <liweilei@awinic.com>
> Signed-off-by: Bruce zhao <zhaolei@awinic.com>
> Signed-off-by: Weidong Wang <wangweidong.a@awinic.com>
> ---
>   sound/soc/codecs/aw883xx/aw883xx_bin_parse.c | 1324 ++++++++++++++++++
>   sound/soc/codecs/aw883xx/aw883xx_bin_parse.h |  149 ++
>   2 files changed, 1473 insertions(+)
>   create mode 100644 sound/soc/codecs/aw883xx/aw883xx_bin_parse.c
>   create mode 100644 sound/soc/codecs/aw883xx/aw883xx_bin_parse.h
> 
> diff --git a/sound/soc/codecs/aw883xx/aw883xx_bin_parse.c b/sound/soc/codecs/aw883xx/aw883xx_bin_parse.c
> new file mode 100644
> index 000000000000..f3d9b8a9fdf2
> --- /dev/null
> +++ b/sound/soc/codecs/aw883xx/aw883xx_bin_parse.c
> @@ -0,0 +1,1324 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * aw_bin_parse.c  -- ALSA Soc AW883XX codec support

> Soc -> SoC

Thanks for your advice, I will modify it in patch v7

> + *
> + * Copyright (c) 2022 AWINIC Technology CO., LTD
> + */
> +
> +#include <linux/cdev.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/debugfs.h>
> +#include <linux/firmware.h>
> +#include <linux/hrtimer.h>
> +#include <linux/input.h>
> +#include <linux/i2c.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/list.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/miscdevice.h>
> +#include <linux/of_gpio.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +#include <linux/string.h>
> +#include <linux/timer.h>
> +#include <linux/uaccess.h>
> +#include <linux/version.h>
> +#include <linux/workqueue.h>
> +#include "aw883xx_bin_parse.h"
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +#include <linux/swab.h>
> +#include <linux/device.h>
> +#include <linux/regmap.h>
> +#include <linux/fs.h>
> +#include <linux/list.h>
> +#include <linux/wait.h>

> Same as on patch 1, there seems to be quite a few unnecessary headers, 
> and this one even has duplicates.

Thanks for your advice, I will modify it in patch v7

> +
> +static char *profile_name[AW_PROFILE_MAX] = {
> +	"Music", "Voice", "Voip", "Ringtone",
> +	"Ringtone_hs", "Lowpower", "Bypass",
> +	"Mmi", "Fm", "Notification", "Receiver"
> +};
> +
> +static int aw_parse_bin_header_1_0_0(struct aw_bin *bin);
> +
> +/*
> + * Interface function
> + *
> + * return value:
> + *       value = 0 :success;
> + *       value = -1 :check bin header version
> + *       value = -2 :check bin data type
> + *       value = -3 :check sum or check bin data len error
> + *       value = -4 :check data version
> + *       value = -5 :check register num
> + *       value = -6 :check dsp reg num
> + *       value = -7 :check soc app num
> + *       value = -8 :bin is NULL point
> + *
> + */
> +
> +/*
> + * check sum data
> + */
> +static int aw_check_sum(struct aw_bin *bin, int bin_num)
> +{
> +	unsigned int i = 0;
> +	unsigned int sum_data = 0;
> +	unsigned int check_sum = 0;
> +	unsigned char *p_check_sum = NULL;
> +
> +	p_check_sum = &(bin->info.data[(bin->header_info[bin_num].valid_data_addr -
> +						bin->header_info[bin_num].header_len)]);
> +
> +	pr_debug("aw_bin_parse p_check_sum = %p\n", p_check_sum);
> +
> +	check_sum = le32_to_cpup((void *)p_check_sum);
> +
> +	for (i = 4; i < bin->header_info[bin_num].bin_data_len +
> +					bin->header_info[bin_num].header_len; i++) {
> +		sum_data += *(p_check_sum + i);
> +	}
> +	pr_debug("aw_bin_parse bin_num = %d, check_sum = 0x%x, sum_data = 0x%x\n",
> +						bin_num, check_sum, sum_data);
> +	if (sum_data != check_sum) {
> +		p_check_sum = NULL;
> No need to assign NULL to pointer?

Thanks for your advice, I will modify it in patch v7

> +		pr_err("%s. CheckSum Fail.bin_num=%d, CheckSum:0x%x, SumData:0x%x",
> +				__func__, bin_num, check_sum, sum_data);
> +		return -BIN_DATA_LEN_ERR;

> Any reason to invent your own error codes, I went through few call paths 
> and you don't seem to use them anywhere, might as well return -EINVAL?

I will modify it in patch v7

> +	}
> +	p_check_sum = NULL;

> Same here, no need to set this to NULL?

Thanks for your advice, I will modify it in patch v7

> +
> +	return 0;
> +}
> +
> +static int aw_check_data_version(struct aw_bin *bin, int bin_num)
> +{
> +	if (bin->header_info[bin_num].bin_data_ver < DATA_VERSION_V1 ||
> +		bin->header_info[bin_num].bin_data_ver > DATA_VERSION_MAX) {
> +		pr_err("aw_bin_parse Unrecognized this bin data version\n");
> +		return -DATA_VER_ERR;

> Return -EINVAL?

Thanks for your advice, I will modify it in patch v7

> +	}
> +
> +	return 0;
> +}
> +
> +static int aw_check_register_num_v1(struct aw_bin *bin, int bin_num)
> +{
> +	unsigned int check_register_num = 0;
> +	unsigned int parse_register_num = 0;
> +	unsigned char *p_check_sum = NULL;
> +	struct bin_header_info temp_info;
> +
> +	temp_info = bin->header_info[bin_num];
> +	p_check_sum = &(bin->info.data[(temp_info.valid_data_addr)]);
> +	pr_debug("aw_bin_parse p_check_sum = %p\n", p_check_sum);
> +	parse_register_num = le32_to_cpup((void *)p_check_sum);
> +	check_register_num = (bin->header_info[bin_num].bin_data_len - 4) /
> +				(bin->header_info[bin_num].reg_byte_len +
> +				bin->header_info[bin_num].data_byte_len);
> +	pr_debug("%s bin_num = %d,parse_register_num = 0x%x,check_register_num = 0x%x\n",
> +				__func__, bin_num, parse_register_num, check_register_num);
> +	if (parse_register_num != check_register_num) {
> +		p_check_sum = NULL;
> Same weird pattern as in previous function.

Thanks for your advice, I will modify it in patch v7

> +		pr_err("%s bin_num = %d,parse_register_num = 0x%x,check_register_num = 0x%x\n",
> +				__func__, bin_num, parse_register_num, check_register_num);
> +
> +		return -REG_NUM_ERR;

> -EINVAL?

Thanks for your advice, I will return -EINVAL at patch v7

> +	}
> +	bin->header_info[bin_num].reg_num = parse_register_num;
> +	bin->header_info[bin_num].valid_data_len = temp_info.bin_data_len - 4;
> +	p_check_sum = NULL;

> Again. I see that it is same in following function, I won't comment 
> them, but it should be also fixed there.

Thanks for your advice, I will modify it in patch v7

> +	bin->header_info[bin_num].valid_data_addr = temp_info.valid_data_addr + 4;
> +
> +	return 0;
> +}
> +

(...)

> +
> +static int aw_dev_parse_dev_default_type(struct aw_device *aw_dev,
> +		struct aw_cfg_hdr *prof_hdr, struct aw_all_prof_info *all_prof_info)
> +{
> +	int i = 0;
> +	int ret;
> +	int sec_num = 0;
> +	struct aw_cfg_dde *cfg_dde =
> +		(struct aw_cfg_dde *)((char *)prof_hdr + prof_hdr->a_hdr_offset);
> +
> +	for (i = 0; i < prof_hdr->a_ddt_num; i++) {
> +		if ((aw_dev->channel == cfg_dde[i].dev_index) &&
> +			(cfg_dde[i].type == AW_DEV_DEFAULT_TYPE_ID)) {
> +			if (cfg_dde[i].data_type != ACF_SEC_TYPE_MONITOR) {

> "if" containing another "if", you can just use &&, so:
> if ((aw_dev->channel == cfg_dde[i].dev_index) &&
>	(cfg_dde[i].type == AW_DEV_DEFAULT_TYPE_ID) &&
>	(cfg_dde[i].data_type != ACF_SEC_TYPE_MONITOR)) {
> and then you can reduce one level of intendation here.

Thanks for your advice, I will modify it in patch v7

> +				if (cfg_dde[i].dev_profile >= AW_PROFILE_MAX) {
> +					dev_err(aw_dev->dev, "dev_profile [%d] overflow",
> +						cfg_dde[i].dev_profile);
> +					return -EINVAL;
> +				}
> +				ret = aw_dev_parse_data_by_sec_type(aw_dev, prof_hdr, &cfg_dde[i],
> +					&all_prof_info->prof_desc[cfg_dde[i].dev_profile]);
> +				if (ret < 0) {
> +					dev_err(aw_dev->dev, "parse failed");
> +					return ret;
> +				}
> +				sec_num++;
> +			}
> +		}
> +	}
> +
> +	if (sec_num == 0) {
> +		dev_err(aw_dev->dev, "get dev default type failed, get num[%d]", sec_num);
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
> +static int aw_dev_cfg_get_vaild_prof(struct aw_device *aw_dev,
> +				struct aw_all_prof_info all_prof_info)
> +{
> +	int i;
> +	int num = 0;
> +	struct aw_sec_data_desc *sec_desc = NULL;
> +	struct aw_prof_desc *prof_desc = all_prof_info.prof_desc;
> +	struct aw_prof_info *prof_info = &aw_dev->prof_info;
> +
> +	for (i = 0; i < AW_PROFILE_MAX; i++) {
> +		if (prof_desc[i].prof_st == AW_PROFILE_OK) {
> +			sec_desc = prof_desc[i].sec_desc;
> +			if ((sec_desc[AW_DATA_TYPE_REG].data != NULL) &&
> +				(sec_desc[AW_DATA_TYPE_REG].len != 0) &&
> +				(sec_desc[AW_DATA_TYPE_DSP_CFG].data != NULL) &&
> +				(sec_desc[AW_DATA_TYPE_DSP_CFG].len != 0) &&
> +				(sec_desc[AW_DATA_TYPE_DSP_FW].data != NULL) &&
> +				(sec_desc[AW_DATA_TYPE_DSP_FW].len != 0)) {
> +				prof_info->count++;
> +			}
> +		}
> +	}
> +
> +	dev_dbg(aw_dev->dev, "get valid profile:%d", aw_dev->prof_info.count);
> +
> +	if (!prof_info->count) {
> +		dev_err(aw_dev->dev, "no profile data");
> +		return -EPERM;
> +	}
> +
> +	prof_info->prof_desc = devm_kzalloc(aw_dev->dev,
> +					prof_info->count * sizeof(struct aw_prof_desc),
> +					GFP_KERNEL);
> +	if (!prof_info->prof_desc) {
> +		dev_err(aw_dev->dev, "prof_desc kzalloc failed");
> +		return -ENOMEM;
> +	}
> +
> +	for (i = 0; i < AW_PROFILE_MAX; i++) {
> +		if (prof_desc[i].prof_st == AW_PROFILE_OK) {
> +			sec_desc = prof_desc[i].sec_desc;
> +			if ((sec_desc[AW_DATA_TYPE_REG].data != NULL) &&
> +				(sec_desc[AW_DATA_TYPE_REG].len != 0) &&
> +				(sec_desc[AW_DATA_TYPE_DSP_CFG].data != NULL) &&
> +				(sec_desc[AW_DATA_TYPE_DSP_CFG].len != 0) &&
> +				(sec_desc[AW_DATA_TYPE_DSP_FW].data != NULL) &&
> +				(sec_desc[AW_DATA_TYPE_DSP_FW].len != 0)) {
> +				if (num >= prof_info->count) {
> +					dev_err(aw_dev->dev, "get scene num[%d] overflow count[%d]",
> +						num, prof_info->count);
> +					return -ENOMEM;
> +				}
> +				prof_info->prof_desc[num] = prof_desc[i];
> +				prof_info->prof_desc[num].id = i;
> +				num++;
> +			}
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static int aw_dev_load_cfg_by_hdr(struct aw_device *aw_dev,
> +		struct aw_cfg_hdr *prof_hdr)
> +{
> +	int ret;
> +	struct aw_all_prof_info *all_prof_info;
> +
> +	all_prof_info = devm_kzalloc(aw_dev->dev, sizeof(struct aw_all_prof_info), GFP_KERNEL);
> +	if (!all_prof_info)
> +		return -ENOMEM;
> +
> +	ret = aw_dev_parse_dev_type(aw_dev, prof_hdr, all_prof_info);
> +	if (ret < 0) {
> +		goto exit;
> +	} else if (ret == AW_DEV_TYPE_NONE) {
> +		dev_dbg(aw_dev->dev, "get dev type num is 0, parse default dev");
> +		ret = aw_dev_parse_dev_default_type(aw_dev, prof_hdr, all_prof_info);
> +		if (ret < 0)
> +			goto exit;
> +	}
> +
> +	ret = aw_dev_cfg_get_vaild_prof(aw_dev, *all_prof_info);
> +	if (ret < 0)
> +		goto exit;
> +
> +	aw_dev->prof_info.prof_name_list = profile_name;
> +exit:
> +	devm_kfree(aw_dev->dev, all_prof_info);
> +	return ret;
> +}
> +
> +static int aw_dev_create_prof_name_list_v_1_0_0_0(struct aw_device *aw_dev)
> +{
> +	struct aw_prof_info *prof_info = &aw_dev->prof_info;
> +	struct aw_prof_desc *prof_desc = prof_info->prof_desc;
> +	int i;
> +
> +	if (!prof_desc) {
> +		dev_err(aw_dev->dev, "prof_desc is NULL");
> +		return -EINVAL;
> +	}
> +
> +	prof_info->prof_name_list = devm_kzalloc(aw_dev->dev,
> +					prof_info->count * PROFILE_STR_MAX,
> +					GFP_KERNEL);

> You seem to be allocating an array here, consider devm_kcalloc instead?

Thanks for your advice, I will modify it in patch v7

> +	if (!prof_info->prof_name_list) {
> +		dev_err(aw_dev->dev, "prof_name_list devm_kzalloc failed");
> +		return -ENOMEM;
> +	}
> +
> +	for (i = 0; i < prof_info->count; i++) {
> +		prof_desc[i].id = i;
> +		prof_info->prof_name_list[i] = prof_desc[i].prf_str;
> +		dev_dbg(aw_dev->dev, "prof name is %s", prof_info->prof_name_list[i]);
> +	}
> +
> +	return 0;
> +}
> +

(...)

> +
> +static int aw_dev_load_cfg_by_hdr_v_1_0_0_0(struct aw_device *aw_dev,
> +									struct aw_container *aw_cfg)
> +{
> +	struct aw_prof_info *prof_info = &aw_dev->prof_info;
> +	struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
> +	int ret;
> +
> +	ret = aw_dev_parse_scene_count_v_1_0_0_0(aw_dev, aw_cfg, &prof_info->count);
> +	if (ret < 0) {
> +		dev_err(aw_dev->dev, "get scene count failed");
> +		return ret;
> +	}
> +
> +	prof_info->prof_desc = devm_kzalloc(aw_dev->dev,
> +					prof_info->count * sizeof(struct aw_prof_desc),
> +					GFP_KERNEL);

> You seem to be allocating an array here, consider devm_kcalloc instead?

Thanks for your advice, I will modify it in patch v7

> +	if (!prof_info->prof_desc)
> +		return -ENOMEM;
> +
> +	ret = aw_dev_parse_by_hdr_v_1_0_0_0(aw_dev, cfg_hdr);
> +	if (ret < 0) {
> +		dev_err(aw_dev->dev, " failed");
> +		return ret;
> +	}
> +
> +	ret = aw_dev_create_prof_name_list_v_1_0_0_0(aw_dev);
> +	if (ret < 0) {
> +		dev_err(aw_dev->dev, "create prof name list failed");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +int aw883xx_dev_cfg_load(struct aw_device *aw_dev, struct aw_container *aw_cfg)
> +{
> +	struct aw_cfg_hdr *cfg_hdr = NULL;
> +	int ret;
> +
> +	cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
> +
> +	switch (cfg_hdr->a_hdr_version) {
> +	case AW_CFG_HDR_VER_0_0_0_1:
> +		ret = aw_dev_load_cfg_by_hdr(aw_dev, cfg_hdr);
> +		if (ret < 0) {
> +			dev_err(aw_dev->dev, "hdr_cersion[0x%x] parse failed",
> +						cfg_hdr->a_hdr_version);
> +			return ret;
> +		}
> +		break;
> +	case AW_CFG_HDR_VER_1_0_0_0:
> +		ret = aw_dev_load_cfg_by_hdr_v_1_0_0_0(aw_dev, aw_cfg);
> +		if (ret < 0) {
> +			dev_err(aw_dev->dev, "hdr_cersion[0x%x] parse failed",
> +						cfg_hdr->a_hdr_version);
> +			return ret;
> +		}
> +		break;
> +	default:
> +		dev_err(aw_dev->dev, "unsupported hdr_version [0x%x]", cfg_hdr->a_hdr_version);
> +		return -EINVAL;
> +	}
> +	aw_dev->fw_status = AW_DEV_FW_OK;
> +	return 0;
> +}
> +
> +static unsigned char aw_dev_crc8_check(unsigned char *data, unsigned int data_size)
> +{
> +	u8 crc_value = 0x00;
> +	u8 pdatabuf = 0;
> +	int i;
> +
> +	while (data_size--) {
> +		pdatabuf = *data++;
> +		for (i = 0; i < 8; i++) {
> +			/*if the lowest bit is 1*/
> +			if ((crc_value ^ (pdatabuf)) & 0x01) {
> +				/*Xor multinomial*/
> +				crc_value ^= 0x18;
> +				crc_value >>= 1;
> +				crc_value |= 0x80;
> +			} else {
> +				crc_value >>= 1;
> +			}
> +			pdatabuf >>= 1;
> +		}
> +	}
> +	return crc_value;
> +}

> There seems to be crc8 implementation in Linux already, any reason to 
> implement your own?
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/crc8.h
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/lib/crc8.c

Thanks for your advice, I will modify it in patch v7

> +
> +static int aw_dev_check_cfg_by_hdr(struct aw_container *aw_cfg)
> +{
> +	struct aw_cfg_hdr *cfg_hdr = NULL;
> +	struct aw_cfg_dde *cfg_dde = NULL;
> +	unsigned int end_data_offset = 0;
> +	unsigned int act_data = 0;
> +	unsigned int hdr_ddt_len = 0;
> +	u8 act_crc8 = 0;
> +	int i;
> +
> +	cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
> +	/*check file type id is awinic acf file*/
> +	if (cfg_hdr->a_id != ACF_FILE_ID) {
> +		pr_err("not acf type file");
> +		return -EINVAL;
> +	}
> +
> +	hdr_ddt_len = cfg_hdr->a_hdr_offset + cfg_hdr->a_ddt_size;
> +	if (hdr_ddt_len > aw_cfg->len) {
> +		pr_err("hdrlen with ddt_len [%d] overflow file size[%d]",
> +		cfg_hdr->a_hdr_offset, aw_cfg->len);
> +		return -EINVAL;
> +	}
> +
> +	/*check data size*/
> +	cfg_dde = (struct aw_cfg_dde *)((char *)aw_cfg->data + cfg_hdr->a_hdr_offset);
> +	act_data += hdr_ddt_len;
> +	for (i = 0; i < cfg_hdr->a_ddt_num; i++)
> +		act_data += cfg_dde[i].data_size;
> +
> +	if (act_data != aw_cfg->len) {
> +		pr_err("act_data[%d] not equal to file size[%d]!",
> +			act_data, aw_cfg->len);
> +		return -EINVAL;
> +	}
> +
> +	for (i = 0; i < cfg_hdr->a_ddt_num; i++) {
> +		/* data check */
> +		end_data_offset = cfg_dde[i].data_offset + cfg_dde[i].data_size;
> +		if (end_data_offset > aw_cfg->len) {
> +			pr_err("a_ddt_num[%d] end_data_offset[%d] overflow file size[%d]",
> +				i, end_data_offset, aw_cfg->len);
> +			return -EINVAL;
> +		}
> +
> +		/* crc check */
> +		act_crc8 = aw_dev_crc8_check(aw_cfg->data + cfg_dde[i].data_offset,
> +									cfg_dde[i].data_size);
> +		if (act_crc8 != cfg_dde[i].data_crc) {
> +			pr_err("a_ddt_num[%d] crc8 check failed, act_crc8:0x%x != data_crc 0x%x",
> +				i, (u32)act_crc8, cfg_dde[i].data_crc);
> +			return -EINVAL;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static int aw_dev_check_acf_by_hdr_v_1_0_0_0(struct aw_container *aw_cfg)
> +{
> +	struct aw_cfg_hdr *cfg_hdr = NULL;
> +	struct aw_cfg_dde_v_1_0_0_0 *cfg_dde = NULL;
> +	unsigned int end_data_offset = 0;
> +	unsigned int act_data = 0;
> +	unsigned int hdr_ddt_len = 0;
> +	u8 act_crc8 = 0;
> +	int i;
> +
> +	cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
> +
> +	/*check file type id is awinic acf file*/
> +	if (cfg_hdr->a_id != ACF_FILE_ID) {
> +		pr_err("not acf type file");
> +		return -EINVAL;
> +	}
> +
> +	hdr_ddt_len = cfg_hdr->a_hdr_offset + cfg_hdr->a_ddt_size;
> +	if (hdr_ddt_len > aw_cfg->len) {
> +		pr_err("hdrlen with ddt_len [%d] overflow file size[%d]",
> +		cfg_hdr->a_hdr_offset, aw_cfg->len);
> +		return -EINVAL;
> +	}
> +
> +	/*check data size*/
> +	cfg_dde = (struct aw_cfg_dde_v_1_0_0_0 *)((char *)aw_cfg->data + cfg_hdr->a_hdr_offset);
> +	act_data += hdr_ddt_len;
> +	for (i = 0; i < cfg_hdr->a_ddt_num; i++)
> +		act_data += cfg_dde[i].data_size;
> +
> +	if (act_data != aw_cfg->len) {
> +		pr_err("act_data[%d] not equal to file size[%d]!",
> +			act_data, aw_cfg->len);
> +		return -EINVAL;
> +	}
> +
> +	for (i = 0; i < cfg_hdr->a_ddt_num; i++) {
> +		/* data check */
> +		end_data_offset = cfg_dde[i].data_offset + cfg_dde[i].data_size;
> +		if (end_data_offset > aw_cfg->len) {
> +			pr_err("a_ddt_num[%d] end_data_offset[%d] overflow file size[%d]",
> +				i, end_data_offset, aw_cfg->len);
> +			return -EINVAL;
> +		}
> +
> +		/* crc check */
> +		act_crc8 = aw_dev_crc8_check(aw_cfg->data + cfg_dde[i].data_offset,
> +							cfg_dde[i].data_size);
> +		if (act_crc8 != cfg_dde[i].data_crc) {
> +			pr_err("a_ddt_num[%d] crc8 check failed, act_crc8:0x%x != data_crc 0x%x",
> +				i, (u32)act_crc8, cfg_dde[i].data_crc);
> +			return -EINVAL;
> +		}
> +	}
> +
> +	return 0;
> +
> +}
> +
> +int aw883xx_dev_load_acf_check(struct aw_container *aw_cfg)
> +{
> +	struct aw_cfg_hdr *cfg_hdr = NULL;
> +
> +	if (!aw_cfg) {
> +		pr_err("aw_prof is NULL");
> +		return -ENOMEM;
> +	}
> +
> +	if (aw_cfg->len < sizeof(struct aw_cfg_hdr)) {
> +		pr_err("cfg hdr size[%d] overflow file size[%d]",
> +			aw_cfg->len, (int)sizeof(struct aw_cfg_hdr));
> +		return -EINVAL;
> +	}
> +
> +	cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
> +	switch (cfg_hdr->a_hdr_version) {
> +	case AW_CFG_HDR_VER_0_0_0_1:
> +		return aw_dev_check_cfg_by_hdr(aw_cfg);
> +	case AW_CFG_HDR_VER_1_0_0_0:
> +		return aw_dev_check_acf_by_hdr_v_1_0_0_0(aw_cfg);
> +	default:
> +		pr_err("unsupported hdr_version [0x%x]", cfg_hdr->a_hdr_version);
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
> +int aw883xx_dev_get_profile_count(struct aw_device *aw_dev)
> +{
> +	if (!aw_dev) {
> +		pr_err("aw_dev is NULL");
> +		return -ENOMEM;
> +	}
> +
> +	return aw_dev->prof_info.count;
> +}
> +
> +int aw883xx_dev_check_profile_index(struct aw_device *aw_dev, int index)
> +{
> +	if ((index >= aw_dev->prof_info.count) || (index < 0))
> +		return -EINVAL;
> +	else
> +		return 0;
> +}

> No need to do "else return 0;", you can just "return 0;" It looks bit 
> cleaner when it is:
> {
> if (check something)
> 	return -EINVAL;
>
> return 0;
> }

Thanks for your advice, I will modify it in patch v7

> +
> +int aw883xx_dev_get_profile_index(struct aw_device *aw_dev)
> +{
> +	return aw_dev->set_prof;
> +}
> +
> +int aw883xx_dev_set_profile_index(struct aw_device *aw_dev, int index)
> +{
> +	struct aw_prof_desc *prof_desc = NULL;
> +
> +	if ((index < aw_dev->prof_info.count) && (index >= 0)) {
> +		aw_dev->set_prof = index;
> +		prof_desc = &aw_dev->prof_info.prof_desc[index];
> +
> +		dev_dbg(aw_dev->dev, "set prof[%s]",
> +			aw_dev->prof_info.prof_name_list[prof_desc->id]);
> +	} else {
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}

> Similarly here, you can just check before hand and success path later:
> if ((index >= aw_dev->prof_info.count) || (index < 0))
>	return -EINVAL;
>
> aw_dev->set_prof = index;
> ...
> return 0;

Thanks for your advice, I will modify it in patch v7

> +
> +char *aw_dev_get_prof_name(struct aw_device *aw_dev, int index)
> +{
> +	struct aw_prof_desc *prof_desc = NULL;
> +	struct aw_prof_info *prof_info = &aw_dev->prof_info;
> +
> +	if ((index >= aw_dev->prof_info.count) || (index < 0)) {
> +		dev_err(aw_dev->dev, "index[%d] overflow count[%d]",
> +			index, aw_dev->prof_info.count);
> +		return NULL;
> +	}
> +
> +	prof_desc = &aw_dev->prof_info.prof_desc[index];
> +
> +	return prof_info->prof_name_list[prof_desc->id];
> +}
> +
> +int aw883xx_dev_get_prof_data(struct aw_device *aw_dev, int index,
> +			struct aw_prof_desc **prof_desc)
> +{
> +	if ((index >= aw_dev->prof_info.count) || (index < 0)) {
> +		dev_err(aw_dev->dev, "%s: index[%d] overflow count[%d]\n",
> +			__func__, index, aw_dev->prof_info.count);
> +		return -EINVAL;
> +	}
> +
> +	*prof_desc = &aw_dev->prof_info.prof_desc[index];
> +
> +	return 0;
> +}
> +
> diff --git a/sound/soc/codecs/aw883xx/aw883xx_bin_parse.h b/sound/soc/codecs/aw883xx/aw883xx_bin_parse.h
> new file mode 100644
> index 000000000000..7f5ce0b1f899
> --- /dev/null
> +++ b/sound/soc/codecs/aw883xx/aw883xx_bin_parse.h
> @@ -0,0 +1,149 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * aw883xx.c --  ALSA Soc AW883XX codec support

> Soc -> SoC

Thanks for your advice, I will modify it in patch v7

> + *
> + * Copyright (c) 2022 AWINIC Technology CO., LTD
> + *
> + * Author: Bruce zhao <zhaolei@awinic.com>
> + */
> +
> +#ifndef __AW883XX_BIN_PARSE_H__
> +#define __AW883XX_BIN_PARSE_H__
> +
> +#include "aw883xx_device.h"
> +
> +#define BIN_NUM_MAX				(100)
> +#define HEADER_LEN				(60)
> +#define CHECK_SUM_OFFSET		(0)
> +#define HEADER_VER_OFFSET		(4)
> +#define	BIN_DATA_TYPE_OFFSET	(8)
> +#define	BIN_DATA_VER_OFFSET		(12)
> +#define	BIN_DATA_LEN_OFFSET		(16)
> +#define	UI_VER_OFFSET			(20)
> +#define CHIP_TYPE_OFFSET		(24)
> +#define	REG_BYTE_LEN_OFFSET		(32)
> +#define	DATA_BYTE_LEN_OFFSET	(36)
> +#define	DEVICE_ADDR_OFFSET		(40)
> +
> +#define AW_FW_CHECK_PART		(10)
> +
> +/*
> + * header information
> + */
> +enum return_enum {
> +	BIN_HEADER_VER_ERR = 1,
> +	BIN_DATA_TYPE_ERR = 2,
> +	BIN_DATA_LEN_ERR = 3,
> +	DATA_VER_ERR = 4,
> +	REG_NUM_ERR = 5,
> +	DSP_REG_NUM_ERR = 6,
> +	SOC_APP_NUM_ERR = 7,
> +	BIN_IS_NULL = 8,
> +};

> As mentioned in the beginning, do you even need your own error values, 
> they seem to be just passed up to be later converted to -EINVAL, might 
> as well return -EINVAL directly.

Thanks for your advice, I will modify it in patch v7

> +
> +enum bin_header_version_enum {
> +	HEADER_VERSION_1_0_0 = 0x01000000,
> +};
> +
> +enum data_type_enum {
> +	DATA_TYPE_REGISTER = 0x00000000,
> +	DATA_TYPE_DSP_REG = 0x00000010,
> +	DATA_TYPE_DSP_CFG = 0x00000011,
> +	DATA_TYPE_SOC_REG = 0x00000020,
> +	DATA_TYPE_SOC_APP = 0x00000021,
> +	DATA_TYPE_DSP_FW = DATA_TYPE_SOC_APP,
> +	DATA_TYPE_MULTI_BINS = 0x00002000,
> +};
> +
> +/**
> + * @DATA_VERSION_V1：default little edian
> + */
> +enum data_version_enum {
> +	DATA_VERSION_V1 = 0X00000001,
> +	DATA_VERSION_MAX,
> +};
> +
> +/**
> + * @header_len: Frame header length
> + * @check_sum: Frame header information-Checksum
> + * @header_ver: Frame header information-Frame header version
> + * @bin_data_type: Frame header information-Data type
> + * @bin_data_ver: Frame header information-Data version
> + * @bin_data_len: Frame header information-Data length
> + * @ui_ver: Frame header information-ui version
> + * @chip_type[8]: Frame header information-chip type
> + * @reg_byte_len: Frame header information-reg byte len
> + * @data_byte_len: Frame header information-data byte len
> + * @device_addr: Frame header information-device addr
> + * @valid_data_len: Length of valid data obtained after parsing
> + * @valid_data_addr: The offset address of the valid data obtained
> + *                   after parsing relative to info
> + * @reg_num: The number of registers obtained after parsing
> + * @reg_data_byte_len: The byte length of the register obtained after parsing
> + * @download_addr: The starting address or download address obtained
> + *                 after parsing
> + * @app_version: The software version number obtained after parsing
> + */
> +struct bin_header_info {
> +	unsigned int header_len;
> +	unsigned int check_sum;
> +	unsigned int header_ver;
> +	unsigned int bin_data_type;
> +	unsigned int bin_data_ver;
> +	unsigned int bin_data_len;
> +	unsigned int ui_ver;
> +	unsigned char chip_type[8];
> +	unsigned int reg_byte_len;
> +	unsigned int data_byte_len;
> +	unsigned int device_addr;
> +	unsigned int valid_data_len;
> +	unsigned int valid_data_addr;
> +
> +	unsigned int reg_num;
> +	unsigned int reg_data_byte_len;
> +	unsigned int download_addr;
> +	unsigned int app_version;
> +};
> +
> +/*
> + * @len: The size of the bin file obtained from the firmware
> + * @data[]: Store the bin file obtained from the firmware
> + */
> +struct bin_container {
> +	unsigned int len;
> +	unsigned char data[];
> +};
> +
> +/**
> + * @p_addr: Offset pointer (backward offset pointer to obtain frame header
> + *          information and important information)
> + * @all_bin_parse_num: The number of all bin files
> + * @multi_bin_parse_num: The number of single bin files
> + * @single_bin_parse_num: The number of multiple bin files
> + * @header_info[BIN_NUM_MAX]: Frame header information and other important data
> + *                            obtained after parsing
> + * @info: Obtained bin file data that needs to be parsed
> + */
> +struct aw_bin {
> +	unsigned char *p_addr;
> +	unsigned int all_bin_parse_num;
> +	unsigned int multi_bin_parse_num;
> +	unsigned int single_bin_parse_num;
> +	struct bin_header_info header_info[BIN_NUM_MAX];
> +	struct bin_container info;
> +};
> +
> +/*******************awinic audio parse acf***********************/
> +int aw883xx_dev_dsp_data_order(struct aw_device *aw_dev,
> +				unsigned char *data, unsigned int data_len);
> +int aw883xx_dev_get_prof_data(struct aw_device *aw_dev, int index,
> +			struct aw_prof_desc **prof_desc);
> +char *aw_dev_get_prof_name(struct aw_device *aw_dev, int index);
> +int aw883xx_dev_set_profile_index(struct aw_device *aw_dev, int index);
> +int aw883xx_dev_get_profile_index(struct aw_device *aw_dev);
> +int aw883xx_dev_check_profile_index(struct aw_device *aw_dev, int index);
> +int aw883xx_dev_get_profile_count(struct aw_device *aw_dev);
> +int aw883xx_dev_cfg_load(struct aw_device *aw_dev, struct aw_container *aw_cfg);
> +int aw883xx_dev_load_acf_check(struct aw_container *aw_cfg);
> +
> +#endif

Re: [PATCH V6 5/5] ASoC: dt-bindings: Add schema for "awinic, aw883xx"

[wangweidong.a]

On Thu, Dec 8, 2022 at 6:28 AM <wangweidong.a@awinic.com> wrote:
>
> From: Weidong Wang <wangweidong.a@awinic.com>
>
> Add a DT schema for describing Awinic AW883xx audio amplifiers. They are
> controlled using I2C.

> blank line

> Pretty sure I said this before, but resend to the DT list if you want
> this reviewed.

Thank you for your advice, but could you please tell me how to resend it to the DT list

> Signed-off-by: Weidong Wang <wangweidong.a@awinic.com>
> ---
>  .../bindings/sound/awinic,aw883xx.yaml        | 49 +++++++++++++++++++
>  1 file changed, 49 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml
>
> diff --git a/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml b/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml
> new file mode 100644
> index 000000000000..b72c9177ebb7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml
> @@ -0,0 +1,49 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sound/awinic,aw883xx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Awinic AW883xx Smart Audio Amplifier
> +
> +maintainers:
> +  - Stephan Gerhold <stephan@gerhold.net>
> +
> +description:
> +  The Awinic AW883XX is an I2S/TDM input, high efficiency
> +  digital Smart K audio amplifier with an integrated 10.25V
> +  smart boost convert.
> +
> +allOf:
> +  - $ref: name-prefix.yaml#

> I think this file has now been renamed upstream.

Thank you for your advice, but could you please describe why

Thanks again for your advice

best regards
Weidong Wang

Re: [PATCH V6 5/5] ASoC: dt-bindings: Add schema for "awinic, aw883xx"

[Krzysztof Kozlowski]

On 13/12/2022 08:26, wangweidong.a@awinic.com wrote:
> On Thu, Dec 8, 2022 at 6:28 AM <wangweidong.a@awinic.com> wrote:
>>
>> From: Weidong Wang <wangweidong.a@awinic.com>
>>
>> Add a DT schema for describing Awinic AW883xx audio amplifiers. They are
>> controlled using I2C.
> 
>> blank line
> 
>> Pretty sure I said this before, but resend to the DT list if you want
>> this reviewed.
> 
> Thank you for your advice, but could you please tell me how to resend it to the DT list

Use scripts/get_maintainers.pl and send to all maintainers, reviewers
and lists. Not to some subset, based on your preference.

> 
>> Signed-off-by: Weidong Wang <wangweidong.a@awinic.com>
>> ---
>>  .../bindings/sound/awinic,aw883xx.yaml        | 49 +++++++++++++++++++
>>  1 file changed, 49 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml b/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml
>> new file mode 100644
>> index 000000000000..b72c9177ebb7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml
>> @@ -0,0 +1,49 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/sound/awinic,aw883xx.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Awinic AW883xx Smart Audio Amplifier
>> +
>> +maintainers:
>> +  - Stephan Gerhold <stephan@gerhold.net>
>> +
>> +description:
>> +  The Awinic AW883XX is an I2S/TDM input, high efficiency
>> +  digital Smart K audio amplifier with an integrated 10.25V
>> +  smart boost convert.
>> +
>> +allOf:
>> +  - $ref: name-prefix.yaml#
> 
>> I think this file has now been renamed upstream.
> 
> Thank you for your advice, but could you please describe why

Why? To better reflect the contents.

Best regards,
Krzysztof

Re: [PATCH V6 5/5] ASoC: dt-bindings: Add schema for "awinic, aw883xx"

[wangweidong.a]

On 13/12/2022 08:26, wangweidong.a@awinic.com wrote:
> On Thu, Dec 8, 2022 at 6:28 AM <wangweidong.a@awinic.com> wrote:
>>
>> From: Weidong Wang <wangweidong.a@awinic.com>
>>
>> Add a DT schema for describing Awinic AW883xx audio amplifiers. They are
>> controlled using I2C.
> 
>> blank line
> 
>> Pretty sure I said this before, but resend to the DT list if you want
>> this reviewed.
> 
> Thank you for your advice, but could you please tell me how to resend it to the DT list

> Use scripts/get_maintainers.pl and send to all maintainers, reviewers
> and lists. Not to some subset, based on your preference.

Thank you very much, I will change it in patch v7

> 
>> Signed-off-by: Weidong Wang <wangweidong.a@awinic.com>
>> ---
>>  .../bindings/sound/awinic,aw883xx.yaml        | 49 +++++++++++++++++++
>>  1 file changed, 49 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml b/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml
>> new file mode 100644
>> index 000000000000..b72c9177ebb7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/sound/awinic,aw883xx.yaml
>> @@ -0,0 +1,49 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/sound/awinic,aw883xx.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Awinic AW883xx Smart Audio Amplifier
>> +
>> +maintainers:
>> +  - Stephan Gerhold <stephan@gerhold.net>
>> +
>> +description:
>> +  The Awinic AW883XX is an I2S/TDM input, high efficiency
>> +  digital Smart K audio amplifier with an integrated 10.25V
>> +  smart boost convert.
>> +
>> +allOf:
>> +  - $ref: name-prefix.yaml#
> 
>> I think this file has now been renamed upstream.
> 
> Thank you for your advice, but could you please describe why

> Why? To better reflect the contents.

Thank you very much for your reply.
But I don't understand why this file has now been renamed upstream.

Best regards

Weidong Wang

Re: [PATCH V6 5/5] ASoC: dt-bindings: Add schema for "awinic, aw883xx"

[Krzysztof Kozlowski]

On 20/12/2022 12:25, wangweidong.a@awinic.com wrote:
>>> +allOf:
>>> +  - $ref: name-prefix.yaml#
>>
>>> I think this file has now been renamed upstream.
>>
>> Thank you for your advice, but could you please describe why
> 
>> Why? To better reflect the contents.
> 
> Thank you very much for your reply.
> But I don't understand why this file has now been renamed upstream.

You asked the same question without helping to understand which part you
did not understand... So you will get similar answer - because old name
did not match the contents. Contents is now for something else, so old
name is not correct anymore.

Best regards,
Krzysztof