Re: [PATCH v4 0/9] CXL: Process event logs

Re: [PATCH v4 0/9] CXL: Process event logs

[Ira Weiny]

My apologies.  Please ignore this series.

I'm trying to use the new b4 send functionality and was trying to send this
only to myself.  I'm not sure what went wrong.  The patches should be ok but
this did not get sent to all the intended lists and people.

I'm going to resend this hopefully to all the right addresses this time.

Ira

On Sun, Dec 11, 2022 at 09:12:19PM -0800, Ira wrote:
> This code has been tested with a newer qemu which allows for more events to be
> returned at a time as well an additional QMP event and interrupt injection.
> Those patches will follow once they have been cleaned up.
> 
> The series is now in 3 parts:
> 
> 	1) Base functionality including interrupts
> 	2) Tracing specific events (Dynamic Capacity Event Record is defered)
> 	3) cxl-test infrastructure for basic tests
> 
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> 
> ---
> Changes in v3:
>         Address comments from Dan
> 
> - Link to v3: https://lore.kernel.org/all/20221208052115.800170-1-ira.weiny@intel.com/
> 
> ---
> Davidlohr Bueso (1):
>       cxl/mem: Wire up event interrupts
> 
> Ira Weiny (8):
>       PCI/CXL: Export native CXL error reporting control
>       cxl/mem: Read, trace, and clear events on driver load
>       cxl/mem: Trace General Media Event Record
>       cxl/mem: Trace DRAM Event Record
>       cxl/mem: Trace Memory Module Event Record
>       cxl/test: Add generic mock events
>       cxl/test: Add specific events
>       cxl/test: Simulate event log overflow
> 
>  drivers/acpi/pci_root.c       |   3 +
>  drivers/cxl/core/mbox.c       | 186 ++++++++++++++++
>  drivers/cxl/core/trace.h      | 479 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/cxl/cxl.h             |  16 ++
>  drivers/cxl/cxlmem.h          | 171 +++++++++++++++
>  drivers/cxl/cxlpci.h          |   6 +
>  drivers/cxl/pci.c             | 236 +++++++++++++++++++++
>  drivers/pci/probe.c           |   1 +
>  include/linux/pci.h           |   1 +
>  tools/testing/cxl/test/Kbuild |   2 +-
>  tools/testing/cxl/test/mem.c  | 352 +++++++++++++++++++++++++++++++
>  11 files changed, 1452 insertions(+), 1 deletion(-)
> ---
> base-commit: acb704099642bc822ef2aed223a0b8db1f7ea76e
> change-id: 20221211-test-b4-e9de44001b6e
> 
> Best regards,
> -- 
> Ira Weiny <ira.weiny@intel.com>

Re: [PATCH v4 0/9] CXL: Process event logs

[Konstantin Ryabitsev]

On Sun, Dec 11, 2022 at 09:32:33PM -0800, Ira Weiny wrote:
> My apologies.  Please ignore this series.
> 
> I'm trying to use the new b4 send functionality and was trying to send this
> only to myself.  I'm not sure what went wrong.  The patches should be ok but
> this did not get sent to all the intended lists and people.
> 
> I'm going to resend this hopefully to all the right addresses this time.

Ira:

I don't think anything went wrong -- you probably used the new "reflect"
feature, right? It fills out the To: and Cc: headers but doesn't actually send
actual mail to those accounts. Mail servers don't actually pay any attention
to those headers -- all that matters is what destinations are given to the
server during the envelope negotiation.

I do realize that this is confusing. :/

Should I include anything in the output about this?

-K

Re: [PATCH v4 0/9] CXL: Process event logs

[Ira Weiny]

On Mon, Dec 12, 2022 at 11:16:13AM -0500, Konstantin Ryabitsev wrote:
> On Sun, Dec 11, 2022 at 09:32:33PM -0800, Ira Weiny wrote:
> > My apologies.  Please ignore this series.
> > 
> > I'm trying to use the new b4 send functionality and was trying to send this
> > only to myself.  I'm not sure what went wrong.  The patches should be ok but
> > this did not get sent to all the intended lists and people.
> > 
> > I'm going to resend this hopefully to all the right addresses this time.
> 
> Ira:

First off thanks for the quick response and I have to say b4 send looks like an
awesome tool.  So I hope the above was not taken the wrong way.

> 
> I don't think anything went wrong -- you probably used the new "reflect"
> feature, right?

I did!  :-D

> It fills out the To: and Cc: headers but doesn't actually send
> actual mail to those accounts. Mail servers don't actually pay any attention
> to those headers -- all that matters is what destinations are given to the
> server during the envelope negotiation.

I did not know that.  But I was kind of coming to that conclusion based on
what I saw happen.

> 
> I do realize that this is confusing. :/

Only to those mere mortals such as myself who don't know squat about mail
protocols!  :-D

> 
> Should I include anything in the output about this?

Maybe.  I'm not trying to put more burden on you.  But for the ignorant maybe
it is a good idea.  I did panic when I saw all the to/cc addresses filled in.

FWIW I do like the idea of seeing the headers as they appear.  My personal
scripts have features to dump emails before trying to send.  So now that I know
what happened I kind of like it.

Thanks,
Ira

Re: [PATCH v4 0/9] CXL: Process event logs

[Konstantin Ryabitsev]

On Mon, Dec 12, 2022 at 10:46:26AM -0800, Ira Weiny wrote:
> > It fills out the To: and Cc: headers but doesn't actually send
> > actual mail to those accounts. Mail servers don't actually pay any attention
> > to those headers -- all that matters is what destinations are given to the
> > server during the envelope negotiation.
> 
> I did not know that.  But I was kind of coming to that conclusion based on
> what I saw happen.
> 
> > 
> > I do realize that this is confusing. :/
> 
> Only to those mere mortals such as myself who don't know squat about mail
> protocols!  :-D

It's completely normal not to know how that works -- and you shouldn't either.

> > Should I include anything in the output about this?
> 
> Maybe.  I'm not trying to put more burden on you.  But for the ignorant maybe
> it is a good idea.  I did panic when I saw all the to/cc addresses filled in.

I added a large notice about that to the --reflect output:

	[...]
	---
	Ready to:
	  - send the above messages to just konstantin@linuxfoundation.org (REFLECT MODE)
	  - via web endpoint: https://lkml.kernel.org/_b4_submit

	REFLECT MODE:
		The To: and Cc: headers will be fully populated, but the only
		address given to the mail server for actual delivery will be
		konstantin@linuxfoundation.org

		Addresses in To: and Cc: headers will NOT receive this series.

	Press Enter to proceed or Ctrl-C to abort

Hopefully, it will be less worrisome to others in the future.

Thank you for trying out b4 prep/send!

-K

Re: [PATCH v4 0/9] CXL: Process event logs

[Ira Weiny]

On Mon, Dec 12, 2022 at 01:54:59PM -0500, Konstantin Ryabitsev wrote:
> On Mon, Dec 12, 2022 at 10:46:26AM -0800, Ira Weiny wrote:
> > > It fills out the To: and Cc: headers but doesn't actually send
> > > actual mail to those accounts. Mail servers don't actually pay any attention
> > > to those headers -- all that matters is what destinations are given to the
> > > server during the envelope negotiation.
> > 
> > I did not know that.  But I was kind of coming to that conclusion based on
> > what I saw happen.
> > 
> > > 
> > > I do realize that this is confusing. :/
> > 
> > Only to those mere mortals such as myself who don't know squat about mail
> > protocols!  :-D
> 
> It's completely normal not to know how that works -- and you shouldn't either.
> 
> > > Should I include anything in the output about this?
> > 
> > Maybe.  I'm not trying to put more burden on you.  But for the ignorant maybe
> > it is a good idea.  I did panic when I saw all the to/cc addresses filled in.
> 
> I added a large notice about that to the --reflect output:
> 
> 	[...]
> 	---
> 	Ready to:
> 	  - send the above messages to just konstantin@linuxfoundation.org (REFLECT MODE)
> 	  - via web endpoint: https://lkml.kernel.org/_b4_submit
> 
> 	REFLECT MODE:
> 		The To: and Cc: headers will be fully populated, but the only
> 		address given to the mail server for actual delivery will be
> 		konstantin@linuxfoundation.org
> 
> 		Addresses in To: and Cc: headers will NOT receive this series.
> 
> 	Press Enter to proceed or Ctrl-C to abort
> 
> Hopefully, it will be less worrisome to others in the future.

Yes that should help a lot!

> 
> Thank you for trying out b4 prep/send!

NP

Thanks!
Ira

Re: [PATCH V4 0/9] CXL: Process event logs

[Jonathan Cameron]

On Fri, 16 Dec 2022 09:01:13 -0800
Dan Williams <dan.j.williams@intel.com> wrote:

> Jonathan Cameron wrote:
> > On Sun, 11 Dec 2022 23:06:18 -0800
> > ira.weiny@intel.com wrote:
> >   
> > > From: Ira Weiny <ira.weiny@intel.com>
> > > 
> > > This code has been tested with a newer qemu which allows for more events to be
> > > returned at a time as well an additional QMP event and interrupt injection.
> > > Those patches will follow once they have been cleaned up.
> > > 
> > > The series is now in 3 parts:
> > > 
> > > 	1) Base functionality including interrupts
> > > 	2) Tracing specific events (Dynamic Capacity Event Record is defered)
> > > 	3) cxl-test infrastructure for basic tests
> > > 
> > > Changes from V3
> > > 	Feedback from Dan
> > > 	Spit out ACPI changes for Bjorn
> > > 
> > > - Link to v3: https://lore.kernel.org/all/20221208052115.800170-1-ira.weiny@intel.com/  
> > 
> > Because I'm in a grumpy mood (as my colleagues will attest!)...
> > This is dependent on the patch that moves the trace definitions and
> > that's not upstream yet except in cxl/preview which is optimistic
> > place to use for a base commit.  The id isn't the one below either which
> > isn't in either mailine or the current CXL trees.  
> 
> I do not want to commit to a new baseline until after -rc1, so yes this
> is in a messy period.

Fully understood. I only push trees out as 'testing' for 0-day to hit
until I can rebase on rc1.

> 
> > Not that I actually checked the cover letter until it failed to apply
> > (and hence already knew what was missing) but still, please call out
> > dependencies unless they are in the branches Dan has queued up to push.
> > 
> > I just want to play with Dave's fix for the RAS errors so having to jump
> > through these other sets.  
> 
> Yes, that is annoying, apologies.
Not really a problem I just felt like grumbling :)

Have a good weekend.

Jonathan

> 
> > 
> > Thanks,
> > 
> > Jonathan
> >   
> > > 
> > > 
> > > Davidlohr Bueso (1):
> > >   cxl/mem: Wire up event interrupts
> > > 
> > > Ira Weiny (8):
> > >   PCI/CXL: Export native CXL error reporting control
> > >   cxl/mem: Read, trace, and clear events on driver load
> > >   cxl/mem: Trace General Media Event Record
> > >   cxl/mem: Trace DRAM Event Record
> > >   cxl/mem: Trace Memory Module Event Record
> > >   cxl/test: Add generic mock events
> > >   cxl/test: Add specific events
> > >   cxl/test: Simulate event log overflow
> > > 
> > >  drivers/acpi/pci_root.c       |   3 +
> > >  drivers/cxl/core/mbox.c       | 186 +++++++++++++
> > >  drivers/cxl/core/trace.h      | 479 ++++++++++++++++++++++++++++++++++
> > >  drivers/cxl/cxl.h             |  16 ++
> > >  drivers/cxl/cxlmem.h          | 171 ++++++++++++
> > >  drivers/cxl/cxlpci.h          |   6 +
> > >  drivers/cxl/pci.c             | 236 +++++++++++++++++
> > >  drivers/pci/probe.c           |   1 +
> > >  include/linux/pci.h           |   1 +
> > >  tools/testing/cxl/test/Kbuild |   2 +-
> > >  tools/testing/cxl/test/mem.c  | 352 +++++++++++++++++++++++++
> > >  11 files changed, 1452 insertions(+), 1 deletion(-)
> > > 
> > > 
> > > base-commit: acb704099642bc822ef2aed223a0b8db1f7ea76e  
> >   
> 
> I think going forward these base-commits need to be something that are
> reachable on cxl.git. For now I have pushed out a baseline for both Dave
> and Ira's patches to cxl/preview which will rebase after -rc1 comes out.
> 
> Just the small matter of needing some acks/reviews on those lead in
> patches so I can move them to through cxl/pending to cxl/next:


Don't move too fast with Ira's.  Some issues coming up in testing..
(admittedly half of them were things where QEMU hadn't kept up with
what the kernel code now uses).


> 
> http://lore.kernel.org/r/167051869176.436579.9728373544811641087.stgit@dwillia2-xfh.jf.intel.com
> http://lore.kernel.org/r/20221212070627.1372402-2-ira.weiny@intel.com

Re: [PATCH V4 0/9] CXL: Process event logs

[Ira Weiny]

On Fri, Dec 16, 2022 at 09:01:13AM -0800, Dan Williams wrote:
> Jonathan Cameron wrote:
> > On Sun, 11 Dec 2022 23:06:18 -0800
> > ira.weiny@intel.com wrote:
> > 
> > > From: Ira Weiny <ira.weiny@intel.com>
> > > 
> > > This code has been tested with a newer qemu which allows for more events to be
> > > returned at a time as well an additional QMP event and interrupt injection.
> > > Those patches will follow once they have been cleaned up.
> > > 
> > > The series is now in 3 parts:
> > > 
> > > 	1) Base functionality including interrupts
> > > 	2) Tracing specific events (Dynamic Capacity Event Record is defered)
> > > 	3) cxl-test infrastructure for basic tests
> > > 
> > > Changes from V3
> > > 	Feedback from Dan
> > > 	Spit out ACPI changes for Bjorn
> > > 
> > > - Link to v3: https://lore.kernel.org/all/20221208052115.800170-1-ira.weiny@intel.com/
> > 
> > Because I'm in a grumpy mood (as my colleagues will attest!)...
> > This is dependent on the patch that moves the trace definitions and
> > that's not upstream yet except in cxl/preview which is optimistic
> > place to use for a base commit.  The id isn't the one below either which
> > isn't in either mailine or the current CXL trees.
> 
> I do not want to commit to a new baseline until after -rc1, so yes this
> is in a messy period.
> 
> > Not that I actually checked the cover letter until it failed to apply
> > (and hence already knew what was missing) but still, please call out
> > dependencies unless they are in the branches Dan has queued up to push.
> > 
> > I just want to play with Dave's fix for the RAS errors so having to jump
> > through these other sets.
> 
> Yes, that is annoying, apologies.
> 
> > 
> > Thanks,
> > 
> > Jonathan
> > 
> > > 
> > > 
> > > Davidlohr Bueso (1):
> > >   cxl/mem: Wire up event interrupts
> > > 
> > > Ira Weiny (8):
> > >   PCI/CXL: Export native CXL error reporting control
> > >   cxl/mem: Read, trace, and clear events on driver load
> > >   cxl/mem: Trace General Media Event Record
> > >   cxl/mem: Trace DRAM Event Record
> > >   cxl/mem: Trace Memory Module Event Record
> > >   cxl/test: Add generic mock events
> > >   cxl/test: Add specific events
> > >   cxl/test: Simulate event log overflow
> > > 
> > >  drivers/acpi/pci_root.c       |   3 +
> > >  drivers/cxl/core/mbox.c       | 186 +++++++++++++
> > >  drivers/cxl/core/trace.h      | 479 ++++++++++++++++++++++++++++++++++
> > >  drivers/cxl/cxl.h             |  16 ++
> > >  drivers/cxl/cxlmem.h          | 171 ++++++++++++
> > >  drivers/cxl/cxlpci.h          |   6 +
> > >  drivers/cxl/pci.c             | 236 +++++++++++++++++
> > >  drivers/pci/probe.c           |   1 +
> > >  include/linux/pci.h           |   1 +
> > >  tools/testing/cxl/test/Kbuild |   2 +-
> > >  tools/testing/cxl/test/mem.c  | 352 +++++++++++++++++++++++++
> > >  11 files changed, 1452 insertions(+), 1 deletion(-)
> > > 
> > > 
> > > base-commit: acb704099642bc822ef2aed223a0b8db1f7ea76e
> > 
> 
> I think going forward these base-commits need to be something that are
> reachable on cxl.git.

Agreed.  I thought this was in preview.  But even preview is not stable and I
should have waited and asked to see this land in next first.

Ira

> For now I have pushed out a baseline for both Dave
> and Ira's patches to cxl/preview which will rebase after -rc1 comes out.
> 
> Just the small matter of needing some acks/reviews on those lead in
> patches so I can move them to through cxl/pending to cxl/next:
> 
> http://lore.kernel.org/r/167051869176.436579.9728373544811641087.stgit@dwillia2-xfh.jf.intel.com
> http://lore.kernel.org/r/20221212070627.1372402-2-ira.weiny@intel.com

Re: [PATCH V4 0/9] CXL: Process event logs

[Dan Williams]

Jonathan Cameron wrote:
> On Sun, 11 Dec 2022 23:06:18 -0800
> ira.weiny@intel.com wrote:
> 
> > From: Ira Weiny <ira.weiny@intel.com>
> > 
> > This code has been tested with a newer qemu which allows for more events to be
> > returned at a time as well an additional QMP event and interrupt injection.
> > Those patches will follow once they have been cleaned up.
> > 
> > The series is now in 3 parts:
> > 
> > 	1) Base functionality including interrupts
> > 	2) Tracing specific events (Dynamic Capacity Event Record is defered)
> > 	3) cxl-test infrastructure for basic tests
> > 
> > Changes from V3
> > 	Feedback from Dan
> > 	Spit out ACPI changes for Bjorn
> > 
> > - Link to v3: https://lore.kernel.org/all/20221208052115.800170-1-ira.weiny@intel.com/
> 
> Because I'm in a grumpy mood (as my colleagues will attest!)...
> This is dependent on the patch that moves the trace definitions and
> that's not upstream yet except in cxl/preview which is optimistic
> place to use for a base commit.  The id isn't the one below either which
> isn't in either mailine or the current CXL trees.

I do not want to commit to a new baseline until after -rc1, so yes this
is in a messy period.

> Not that I actually checked the cover letter until it failed to apply
> (and hence already knew what was missing) but still, please call out
> dependencies unless they are in the branches Dan has queued up to push.
> 
> I just want to play with Dave's fix for the RAS errors so having to jump
> through these other sets.

Yes, that is annoying, apologies.

> 
> Thanks,
> 
> Jonathan
> 
> > 
> > 
> > Davidlohr Bueso (1):
> >   cxl/mem: Wire up event interrupts
> > 
> > Ira Weiny (8):
> >   PCI/CXL: Export native CXL error reporting control
> >   cxl/mem: Read, trace, and clear events on driver load
> >   cxl/mem: Trace General Media Event Record
> >   cxl/mem: Trace DRAM Event Record
> >   cxl/mem: Trace Memory Module Event Record
> >   cxl/test: Add generic mock events
> >   cxl/test: Add specific events
> >   cxl/test: Simulate event log overflow
> > 
> >  drivers/acpi/pci_root.c       |   3 +
> >  drivers/cxl/core/mbox.c       | 186 +++++++++++++
> >  drivers/cxl/core/trace.h      | 479 ++++++++++++++++++++++++++++++++++
> >  drivers/cxl/cxl.h             |  16 ++
> >  drivers/cxl/cxlmem.h          | 171 ++++++++++++
> >  drivers/cxl/cxlpci.h          |   6 +
> >  drivers/cxl/pci.c             | 236 +++++++++++++++++
> >  drivers/pci/probe.c           |   1 +
> >  include/linux/pci.h           |   1 +
> >  tools/testing/cxl/test/Kbuild |   2 +-
> >  tools/testing/cxl/test/mem.c  | 352 +++++++++++++++++++++++++
> >  11 files changed, 1452 insertions(+), 1 deletion(-)
> > 
> > 
> > base-commit: acb704099642bc822ef2aed223a0b8db1f7ea76e
> 

I think going forward these base-commits need to be something that are
reachable on cxl.git. For now I have pushed out a baseline for both Dave
and Ira's patches to cxl/preview which will rebase after -rc1 comes out.

Just the small matter of needing some acks/reviews on those lead in
patches so I can move them to through cxl/pending to cxl/next:

http://lore.kernel.org/r/167051869176.436579.9728373544811641087.stgit@dwillia2-xfh.jf.intel.com
http://lore.kernel.org/r/20221212070627.1372402-2-ira.weiny@intel.com

Re: [PATCH V4 0/9] CXL: Process event logs

[Jonathan Cameron]

On Sun, 11 Dec 2022 23:06:18 -0800
ira.weiny@intel.com wrote:

> From: Ira Weiny <ira.weiny@intel.com>
> 
> This code has been tested with a newer qemu which allows for more events to be
> returned at a time as well an additional QMP event and interrupt injection.
> Those patches will follow once they have been cleaned up.
> 
> The series is now in 3 parts:
> 
> 	1) Base functionality including interrupts
> 	2) Tracing specific events (Dynamic Capacity Event Record is defered)
> 	3) cxl-test infrastructure for basic tests
> 
> Changes from V3
> 	Feedback from Dan
> 	Spit out ACPI changes for Bjorn
> 
> - Link to v3: https://lore.kernel.org/all/20221208052115.800170-1-ira.weiny@intel.com/

Because I'm in a grumpy mood (as my colleagues will attest!)...
This is dependent on the patch that moves the trace definitions and
that's not upstream yet except in cxl/preview which is optimistic
place to use for a base commit.  The id isn't the one below either which
isn't in either mailine or the current CXL trees.

Not that I actually checked the cover letter until it failed to apply
(and hence already knew what was missing) but still, please call out
dependencies unless they are in the branches Dan has queued up to push.

I just want to play with Dave's fix for the RAS errors so having to jump
through these other sets.

Thanks,

Jonathan

> 
> 
> Davidlohr Bueso (1):
>   cxl/mem: Wire up event interrupts
> 
> Ira Weiny (8):
>   PCI/CXL: Export native CXL error reporting control
>   cxl/mem: Read, trace, and clear events on driver load
>   cxl/mem: Trace General Media Event Record
>   cxl/mem: Trace DRAM Event Record
>   cxl/mem: Trace Memory Module Event Record
>   cxl/test: Add generic mock events
>   cxl/test: Add specific events
>   cxl/test: Simulate event log overflow
> 
>  drivers/acpi/pci_root.c       |   3 +
>  drivers/cxl/core/mbox.c       | 186 +++++++++++++
>  drivers/cxl/core/trace.h      | 479 ++++++++++++++++++++++++++++++++++
>  drivers/cxl/cxl.h             |  16 ++
>  drivers/cxl/cxlmem.h          | 171 ++++++++++++
>  drivers/cxl/cxlpci.h          |   6 +
>  drivers/cxl/pci.c             | 236 +++++++++++++++++
>  drivers/pci/probe.c           |   1 +
>  include/linux/pci.h           |   1 +
>  tools/testing/cxl/test/Kbuild |   2 +-
>  tools/testing/cxl/test/mem.c  | 352 +++++++++++++++++++++++++
>  11 files changed, 1452 insertions(+), 1 deletion(-)
> 
> 
> base-commit: acb704099642bc822ef2aed223a0b8db1f7ea76e

[PATCH V4 0/9] CXL: Process event logs

[ira.weiny]

From: Ira Weiny <ira.weiny@intel.com>

This code has been tested with a newer qemu which allows for more events to be
returned at a time as well an additional QMP event and interrupt injection.
Those patches will follow once they have been cleaned up.

The series is now in 3 parts:

	1) Base functionality including interrupts
	2) Tracing specific events (Dynamic Capacity Event Record is defered)
	3) cxl-test infrastructure for basic tests

Changes from V3
	Feedback from Dan
	Spit out ACPI changes for Bjorn

- Link to v3: https://lore.kernel.org/all/20221208052115.800170-1-ira.weiny@intel.com/


Davidlohr Bueso (1):
  cxl/mem: Wire up event interrupts

Ira Weiny (8):
  PCI/CXL: Export native CXL error reporting control
  cxl/mem: Read, trace, and clear events on driver load
  cxl/mem: Trace General Media Event Record
  cxl/mem: Trace DRAM Event Record
  cxl/mem: Trace Memory Module Event Record
  cxl/test: Add generic mock events
  cxl/test: Add specific events
  cxl/test: Simulate event log overflow

 drivers/acpi/pci_root.c       |   3 +
 drivers/cxl/core/mbox.c       | 186 +++++++++++++
 drivers/cxl/core/trace.h      | 479 ++++++++++++++++++++++++++++++++++
 drivers/cxl/cxl.h             |  16 ++
 drivers/cxl/cxlmem.h          | 171 ++++++++++++
 drivers/cxl/cxlpci.h          |   6 +
 drivers/cxl/pci.c             | 236 +++++++++++++++++
 drivers/pci/probe.c           |   1 +
 include/linux/pci.h           |   1 +
 tools/testing/cxl/test/Kbuild |   2 +-
 tools/testing/cxl/test/mem.c  | 352 +++++++++++++++++++++++++
 11 files changed, 1452 insertions(+), 1 deletion(-)


base-commit: acb704099642bc822ef2aed223a0b8db1f7ea76e
-- 
2.37.2