[PATCH v5 0/9] Add RZ/G2L POEG support

[PATCH v5 0/9] Add RZ/G2L POEG support

[Biju Das]

The output pins of the general PWM timer (GPT) can be disabled by using the port
output enabling function for the GPT (POEG). Specifically, either of the
following ways can be used.

  * Input level detection of the GTETRGA to GTETRGD pins.
  * Output-disable request from the GPT.
  * Register setting(ie, by setting POEGGn.SSF to 1)

This patch series add support for controlling output disable function using sysfs.

For output disable operation, POEG group needs to be linked with GPT.
Plan to send a follow up patch with renesas,poeg-group as numeric
property in pwm bindings for linking both GPT and POEG devices.

Patch #3 to patch #9 are new and just for testing only(GPT Output-disable
request to POEG)

When dead time error occurs or the GTIOCA pin output value is
the same as the GTIOCB pin output value, output protection is
required. GPT detects this condition and generates output disable
requests to POEG based on the settings in the output disable request
permission bits, such as GTINTAD.GRPDTE, GTINTAD.GRPABH,
GTINTAD.GRPABL. After the POEG receives output disable requests from
each channel and calculates external input using an OR operation, the
POEG generates output disable requests to GPT.

POEG handles output disable request and send an event to userspace.
Userspace clears the fault condition and request poeg to cancel
the output disable request.

Logs:
root@smarc-rzg2l:~# /poeg_app &
[1] 182
root@smarc-rzg2l:~# [POEG]open

root@smarc-rzg2l:~# /poeg.sh
16
pwmchip0
Test case 1 user POEG control
 72:          0          0     GICv3 354 Level     10048800.poeg
 73:          0          0     GICv3 355 Level     10048c00.poeg
 74:          0          0     GICv3 356 Level     10049000.poeg
 76:          0          0     GICv3 357 Level     10049400.poeg
Read at address  0x10048434 (0xffff8d92b434): 0x0200031B
Read at address  0x10048438 (0xffff9884e438): 0x03000000
Read at address  0x10049400 (0xffffbd7b9400): 0x00000030
Test case 2 user GPT control both high
Read at address  0x10048434 (0xffff96dcf434): 0x021B031B
Read at address  0x10048438 (0xffff9ddfc438): 0x23000000
Read at address  0x10049400 (0xffff9a206400): 0x00000030
gpt ch:3, irq=2
gpt ch:3, irq=2
Read at address  0x10048434 (0xffff97fb2434): 0x021B031B
Read at address  0x10048438 (0xffff817a1438): 0x03000000
Read at address  0x10049400 (0xffffb8f5e400): 0x00000030
gpt ch:3, irq=2
 72:          0          0     GICv3 354 Level     10048800.poeg
 73:          0          0     GICv3 355 Level     10048c00.poeg
 74:          0          0     GICv3 356 Level     10049000.poeg
 76:          6          0     GICv3 357 Level     10049400.poeg
Test case 3 user GPT control both low
Read at address  0x10048434 (0xffff897d8434): 0x031B031B
Read at address  0x10048438 (0xffffa981a438): 0x43000000
Read at address  0x10049400 (0xffff90eba400): 0x00000030
gpt ch:3, irq=4
gpt ch:3, irq=4
Read at address  0x10048434 (0xffff959d7434): 0x021B031B
Read at address  0x10048438 (0xffff92b6d438): 0x03000000
Read at address  0x10049400 (0xffffb60b3400): 0x00000030
gpt ch:3, irq=4
 72:          0          0     GICv3 354 Level     10048800.poeg
 73:          0          0     GICv3 355 Level     10048c00.poeg
 74:          0          0     GICv3 356 Level     10049000.poeg
 76:         12          0     GICv3 357 Level     10049400.poeg
root@smarc-rzg2l:~#

v4->v5:
 * Added Rb tag from Rob.
 * Updated kernel version in sysfs doc.
v3->v4:
 * Replaced companion->renesas,gpt for the phandle to gpt instance
 * Replaced renesas,id->renesas,poeg-id
 * Removed default from renesas,poeg-id as default for a required
   property doesn't make much sense.
 * Updated the example and required properties with above changes
v2->v3:
 * Removed Rb tag from Rob as there are some changes introduced.
 * Added companion property, so that poeg can link with gpt device
 * Documented renesas,id, as identifier for POEGG{A,B,C,D}.
 * Updated the binding example.
 * Added sysfs documentation for output_disable
 * PWM_RZG2L_GPT implies ARCH_RZG2L. So removed ARCH_RZG2L dependency
 * Used dev_get_drvdata to get device data
 * Replaced sprintf->sysfs_emit in show().
v1->v2:
 * Updated binding description.
 * Renamed the file poeg-rzg2l->rzg2l-poeg
 * Removed the macro POEGG as there is only single register and
   updated rzg2l_poeg_write() and rzg2l_poeg_read()
 * Updated error handling in probe()
REF->v1:
 * Modelled as pincontrol as most of its configuration is intended to be
   static and moved driver files from soc to pincontrol directory.
 * Updated reg size in dt binding example.
 * Updated Kconfig

REF:
https://lore.kernel.org/linux-renesas-soc/20220510151112.16249-1-biju.das.jz@bp.renesas.com/


Biju Das (9):
  dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding
  drivers: pinctrl: renesas: Add RZ/G2L POEG driver support
  pwm: rzg2l-gpt: Add support for output disable request from gpt
  pinctrl: renesas: rzg2l-poeg: Add support for GPT Output-Disable
    Request
  pwm: rzg2l-gpt: Add support for output disable when both output low
  pinctrl: renesas: rzg2l-poeg: output-disable request from GPT when
    both outputs are low.
  pwm: rzg2l-gpt: Add support for output disable on dead time error
  pinctrl: renesas: rzg2l-poeg: output-disable request from GPT on dead
    time error
  tools/poeg: Add test app for poeg

 .../ABI/testing/sysfs-platform-rzg2l-poeg     |  87 ++++
 .../bindings/pinctrl/renesas,rzg2l-poeg.yaml  |  86 ++++
 drivers/pinctrl/renesas/Kconfig               |   2 +
 drivers/pinctrl/renesas/Makefile              |   2 +
 drivers/pinctrl/renesas/poeg/Kconfig          |  11 +
 drivers/pinctrl/renesas/poeg/Makefile         |   2 +
 drivers/pinctrl/renesas/poeg/rzg2l-poeg.c     | 476 ++++++++++++++++++
 drivers/pwm/pwm-rzg2l-gpt.c                   | 129 +++++
 include/linux/soc/renesas/rzg2l-gpt.h         |  44 ++
 include/linux/soc/renesas/rzg2l-poeg.h        |  16 +
 tools/poeg/Build                              |   1 +
 tools/poeg/Makefile                           |  53 ++
 tools/poeg/poeg_app.c                         |  60 +++
 13 files changed, 969 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-platform-rzg2l-poeg
 create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
 create mode 100644 drivers/pinctrl/renesas/poeg/Kconfig
 create mode 100644 drivers/pinctrl/renesas/poeg/Makefile
 create mode 100644 drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
 create mode 100644 include/linux/soc/renesas/rzg2l-gpt.h
 create mode 100644 include/linux/soc/renesas/rzg2l-poeg.h
 create mode 100644 tools/poeg/Build
 create mode 100644 tools/poeg/Makefile
 create mode 100644 tools/poeg/poeg_app.c

-- 
2.25.1

[PATCH v5 1/9] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding

[Biju Das]

Add device tree bindings for the RZ/G2L Port Output Enable for GPT (POEG).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v4->v5:
 * Added Rb tag from Rob.
v3->v4:
 * Replaced companion->renesas,gpt for the phandle to gpt instance
 * Replaced renesas,id->renesas,poeg-id
 * Removed default from renesas,poeg-id as default for a required
   property doesn't make much sense.
 * Updated the example and required properties with above changes
v2->v3:
 * Removed Rb tag from Rob as there are some changes introduced.
 * Added companion property, so that poeg can link with gpt device
 * Documented renesas,id, as identifier for POEGG{A,B,C,D}.
 * Updated the example.
v1->v2:
 * Updated the description.
REF->v1:
 * Modelled as pincontrol as most of its configuration is intended to be
   static.
 * Updated reg size in example.
---
 .../bindings/pinctrl/renesas,rzg2l-poeg.yaml  | 86 +++++++++++++++++++
 1 file changed, 86 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
new file mode 100644
index 000000000000..ab2d456c93e4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-poeg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
+
+maintainers:
+  - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+  The output pins(GTIOCxA and GTIOCxB) of the general PWM timer (GPT) can be
+  disabled by using the port output enabling function for the GPT (POEG).
+  Specifically, either of the following ways can be used.
+  * Input level detection of the GTETRGA to GTETRGD pins.
+  * Output-disable request from the GPT.
+  * SSF bit setting(ie, by setting POEGGn.SSF to 1)
+
+  The state of the GTIOCxA and the GTIOCxB pins when the output is disabled,
+  are controlled by the GPT module.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - renesas,r9a07g044-poeg  # RZ/G2{L,LC}
+          - renesas,r9a07g054-poeg  # RZ/V2L
+      - const: renesas,rzg2l-poeg
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  renesas,gpt:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle to gpt instance that serves the pwm operation.
+
+  renesas,poeg-id:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [ 0, 1, 2, 3 ]
+    description: |
+      POEG group index. Valid values are:
+        <0> : POEG group A
+        <1> : POEG group B
+        <2> : POEG group C
+        <3> : POEG group D
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - power-domains
+  - resets
+  - renesas,poeg-id
+  - renesas,gpt
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r9a07g044-cpg.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    poeggd: poeg@10049400 {
+        compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg";
+        reg = <0x10049400 0x400>;
+        interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>;
+        power-domains = <&cpg>;
+        resets = <&cpg R9A07G044_POEG_D_RST>;
+        renesas,poeg-id = <3>;
+        renesas,gpt = <&gpt>;
+    };
-- 
2.25.1

[PATCH v5 2/9] drivers: pinctrl: renesas: Add RZ/G2L POEG driver support

[Biju Das]

The output pins of the RZ/G2L general PWM timer (GPT) can be disabled
by using the port output enabling function for the GPT (POEG).

This patch adds basic support using s/w control through sysfs
to enable/disable output from GPT.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v4->v5:
 * Updated kernel version in sysfs doc.
v3->v4:
 * Updated commit description.
v2->v3:
 * Added sysfs documentation for output_disable
 * PWM_RZG2L_GPT implies ARCH_RZG2L. So removed ARCH_RZG2L dependency
 * Used dev_get_drvdata to get device data
 * Replaced sprintf->sysfs_emit in show().
v1->v2:
 * Renamed the file poeg-rzg2l->rzg2l-poeg
 * Removed the macro POEGG as there is only single register and
   updated rzg2l_poeg_write() and rzg2l_poeg_read()
 * Updated error handling in probe()
Ref->v1:
 * Moved driver files from soc to pincontrol directory
 * Updated KConfig
---
 .../ABI/testing/sysfs-platform-rzg2l-poeg     |  18 ++
 drivers/pinctrl/renesas/Kconfig               |   2 +
 drivers/pinctrl/renesas/Makefile              |   2 +
 drivers/pinctrl/renesas/poeg/Kconfig          |  11 ++
 drivers/pinctrl/renesas/poeg/Makefile         |   2 +
 drivers/pinctrl/renesas/poeg/rzg2l-poeg.c     | 157 ++++++++++++++++++
 6 files changed, 192 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-platform-rzg2l-poeg
 create mode 100644 drivers/pinctrl/renesas/poeg/Kconfig
 create mode 100644 drivers/pinctrl/renesas/poeg/Makefile
 create mode 100644 drivers/pinctrl/renesas/poeg/rzg2l-poeg.c

diff --git a/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg b/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg
new file mode 100644
index 000000000000..157c98c49940
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg
@@ -0,0 +1,18 @@
+What:		/sys/devices/platform/<rzg2l-poeg's name>/output_disable
+Date:		November 2022
+KernelVersion:	6.3
+Contact:	Biju Das <biju.das.jz@bp.renesas.com>
+Description:
+		This file can be read and write.
+		The file used to control the output disable using
+		register settings.
+
+		Write the following string to control the output disable:
+
+		- "1" - request output-disable from software.
+		- "0" - request no output-disable from software.
+
+		Read the file, then it shows the following strings:
+
+		- "1" - Output-disable request from software occurred.
+		- "0" - No output-disable request from software occurred.
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 0903a0a41831..92bdc2e1e125 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -308,4 +308,6 @@ config PINCTRL_PFC_SHX3
 	bool "pin control support for SH-X3" if COMPILE_TEST
 	select PINCTRL_SH_FUNC_GPIO
 
+source "drivers/pinctrl/renesas/poeg/Kconfig"
+
 endmenu
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 558b30ce0dec..de1bb592fbf3 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -52,6 +52,8 @@ obj-$(CONFIG_PINCTRL_RZG2L)	+= pinctrl-rzg2l.o
 obj-$(CONFIG_PINCTRL_RZN1)	+= pinctrl-rzn1.o
 obj-$(CONFIG_PINCTRL_RZV2M)	+= pinctrl-rzv2m.o
 
+obj-$(CONFIG_POEG_RZG2L)	+= poeg/
+
 ifeq ($(CONFIG_COMPILE_TEST),y)
 CFLAGS_pfc-sh7203.o	+= -I$(srctree)/arch/sh/include/cpu-sh2a
 CFLAGS_pfc-sh7264.o	+= -I$(srctree)/arch/sh/include/cpu-sh2a
diff --git a/drivers/pinctrl/renesas/poeg/Kconfig b/drivers/pinctrl/renesas/poeg/Kconfig
new file mode 100644
index 000000000000..306e8ae81cb2
--- /dev/null
+++ b/drivers/pinctrl/renesas/poeg/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0
+config POEG_RZG2L
+	tristate "Renesas RZ/G2L poeg support"
+	depends on PWM_RZG2L_GPT || COMPILE_TEST
+	depends on HAS_IOMEM
+	help
+	  This driver exposes the Port Output Enable for GPT(POEG) found
+	  in Renesas RZ/G2L alike SoCs.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called rzg2l-poeg.
diff --git a/drivers/pinctrl/renesas/poeg/Makefile b/drivers/pinctrl/renesas/poeg/Makefile
new file mode 100644
index 000000000000..610bdd6182be
--- /dev/null
+++ b/drivers/pinctrl/renesas/poeg/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_POEG_RZG2L)	+= rzg2l-poeg.o
diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
new file mode 100644
index 000000000000..3788191bc2f1
--- /dev/null
+++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2L Port Output Enable for GPT (POEG) driver
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#define POEGG_SSF	BIT(3)
+
+struct rzg2l_poeg_chip {
+	struct reset_control *rstc;
+	void __iomem *mmio;
+};
+
+static void rzg2l_poeg_write(struct rzg2l_poeg_chip *chip, u32 data)
+{
+	iowrite32(data, chip->mmio);
+}
+
+static u32 rzg2l_poeg_read(struct rzg2l_poeg_chip *chip)
+{
+	return ioread32(chip->mmio);
+}
+
+static ssize_t output_disable_store(struct device *dev,
+				    struct device_attribute *attr,
+				    const char *buf, size_t count)
+{
+	struct rzg2l_poeg_chip *chip;
+	unsigned int val;
+	u32 reg_val;
+	int ret;
+
+	chip = dev_get_drvdata(dev);
+	ret = kstrtouint(buf, 0, &val);
+	if (ret)
+		return ret;
+
+	reg_val = rzg2l_poeg_read(chip);
+	if (val)
+		reg_val |= POEGG_SSF;
+	else
+		reg_val &= ~POEGG_SSF;
+
+	rzg2l_poeg_write(chip, reg_val);
+
+	return count;
+}
+
+static ssize_t output_disable_show(struct device *dev,
+				   struct device_attribute *attr, char *buf)
+{
+	struct rzg2l_poeg_chip *chip;
+	u32 reg;
+
+	chip = dev_get_drvdata(dev);
+	reg = rzg2l_poeg_read(chip);
+
+	return sysfs_emit(buf, "%u\n", (reg & POEGG_SSF) ? 1 : 0);
+}
+
+static DEVICE_ATTR_RW(output_disable);
+
+static struct attribute *poeg_attrs[] = {
+	&dev_attr_output_disable.attr,
+	NULL,
+};
+
+static const struct attribute_group poeg_groups = {
+	.attrs = poeg_attrs,
+};
+
+static const struct of_device_id rzg2l_poeg_of_table[] = {
+	{ .compatible = "renesas,rzg2l-poeg", },
+	{ /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzg2l_poeg_of_table);
+
+static int rzg2l_poeg_probe(struct platform_device *pdev)
+{
+	struct rzg2l_poeg_chip *chip;
+	int ret;
+
+	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
+	if (!chip)
+		return -ENOMEM;
+
+	chip->mmio = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(chip->mmio))
+		return PTR_ERR(chip->mmio);
+
+	chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+	if (IS_ERR(chip->rstc))
+		return dev_err_probe(&pdev->dev, PTR_ERR(chip->rstc),
+				     "get reset failed\n");
+
+	ret = reset_control_deassert(chip->rstc);
+	if (ret)
+		return ret;
+
+	platform_set_drvdata(pdev, chip);
+	pm_runtime_enable(&pdev->dev);
+	ret = pm_runtime_resume_and_get(&pdev->dev);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret);
+		goto err_pm_disable;
+	}
+
+	ret = sysfs_create_group(&pdev->dev.kobj, &poeg_groups);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to create sysfs: %d\n", ret);
+		goto err_pm;
+	}
+
+	return 0;
+
+err_pm:
+	pm_runtime_put(&pdev->dev);
+err_pm_disable:
+	pm_runtime_disable(&pdev->dev);
+	reset_control_assert(chip->rstc);
+
+	return ret;
+}
+
+static int rzg2l_poeg_remove(struct platform_device *pdev)
+{
+	struct rzg2l_poeg_chip *chip = platform_get_drvdata(pdev);
+
+	sysfs_remove_group(&pdev->dev.kobj, &poeg_groups);
+	pm_runtime_put(&pdev->dev);
+	pm_runtime_disable(&pdev->dev);
+	reset_control_assert(chip->rstc);
+
+	return 0;
+}
+
+static struct platform_driver rzg2l_poeg_driver = {
+	.driver = {
+		.name = "rzg2l-poeg",
+		.of_match_table = of_match_ptr(rzg2l_poeg_of_table),
+	},
+	.probe = rzg2l_poeg_probe,
+	.remove = rzg2l_poeg_remove,
+};
+module_platform_driver(rzg2l_poeg_driver);
+
+MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
+MODULE_DESCRIPTION("Renesas RZ/G2L POEG Driver");
+MODULE_LICENSE("GPL");
-- 
2.25.1

[DO NOT APPLY PATCH v5 3/9] pwm: rzg2l-gpt: Add support for output disable request from gpt

[Biju Das]

When dead time error occurs or the GTIOCA pin output value is
the same as the GTIOCB pin output value, output protection is
required. GPT detects this condition and generates output disable
requests to POEG based on the settings in the output disable request
permission bits, such as GTINTAD.GRPDTE, GTINTAD.GRPABH,
GTINTAD.GRPABL. After the POEG receives output disable requests from
each channel and calculates external input using an OR operation, the
POEG generates output disable requests to GPT.

This patch adds support for output disable request from gpt,
when same time output level is high.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pwm/pwm-rzg2l-gpt.c           | 111 ++++++++++++++++++++++++++
 include/linux/soc/renesas/rzg2l-gpt.h |  32 ++++++++
 2 files changed, 143 insertions(+)
 create mode 100644 include/linux/soc/renesas/rzg2l-gpt.h

diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index 6bf407550326..bcf843b51e3d 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -26,12 +26,14 @@
 #include <linux/pm_runtime.h>
 #include <linux/pwm.h>
 #include <linux/reset.h>
+#include <linux/soc/renesas/rzg2l-gpt.h>
 #include <linux/time.h>
 
 #define RZG2L_GTCR		0x2c
 #define RZG2L_GTUDDTYC		0x30
 #define RZG2L_GTIOR		0x34
 #define RZG2L_GTINTAD		0x38
+#define RZG2L_GTST		0x3c
 #define RZG2L_GTBER		0x40
 #define RZG2L_GTCNT		0x48
 #define RZG2L_GTCCRA		0x4c
@@ -72,6 +74,12 @@
 	(FIELD_PREP(RZG2L_GTIOR_GTIOB, RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE) | RZG2L_GTIOR_OBE)
 
 #define RZG2L_GTINTAD_GRP_MASK			GENMASK(25, 24)
+#define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH	BIT(29)
+
+#define RZG2L_GTST_OABHF			BIT(29)
+#define RZG2L_GTST_OABLF			BIT(30)
+
+#define RZG2L_GTST_POEG_IRQ_MASK		GENMASK(30, 28)
 
 #define RZG2L_GTCCR(i) (0x4c + 4 * (i))
 
@@ -458,6 +466,109 @@ static const struct dev_pm_ops rzg2l_gpt_pm_ops = {
 	SET_RUNTIME_PM_OPS(rzg2l_gpt_pm_runtime_suspend, rzg2l_gpt_pm_runtime_resume, NULL)
 };
 
+u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp)
+{
+	u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS;
+	struct rzg2l_gpt_chip *rzg2l_gpt;
+	unsigned int i;
+	u32 val = 0;
+	u32 offs;
+	u32 reg;
+
+	rzg2l_gpt = dev_get_drvdata(dev);
+	for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) {
+		val <<= 3;
+		if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link))
+			continue;
+
+		offs = RZG2L_GET_CH_OFFS(i);
+		reg = rzg2l_gpt_read(rzg2l_gpt, offs + RZG2L_GTST);
+		val |= FIELD_GET(RZG2L_GTST_POEG_IRQ_MASK, reg);
+	}
+
+	return val;
+}
+EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_irq_status);
+
+int rzg2l_gpt_poeg_disable_req_clr(void *dev, u8 grp)
+{
+	u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS;
+	struct rzg2l_gpt_chip *rzg2l_gpt;
+	unsigned int i;
+	u32 offs;
+	u32 reg;
+
+	rzg2l_gpt = dev_get_drvdata(dev);
+	for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) {
+		if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link))
+			continue;
+
+		offs = RZG2L_GET_CH_OFFS(i);
+		reg = rzg2l_gpt_read(rzg2l_gpt, offs + RZG2L_GTST);
+
+		if (reg & (RZG2L_GTST_OABHF | RZG2L_GTST_OABLF))
+			rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTIOR,
+					 RZG2L_GTIOR_OBE, 0);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_clr);
+
+int rzg2l_gpt_pin_reenable(void *dev, u8 grp)
+{
+	u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS;
+	struct rzg2l_gpt_chip *rzg2l_gpt;
+	unsigned int i;
+	u32 offs;
+
+	rzg2l_gpt = dev_get_drvdata(dev);
+	for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) {
+		if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link))
+			continue;
+
+		offs = RZG2L_GET_CH_OFFS(i);
+		rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTIOR,
+				 RZG2L_GTIOR_OBE, RZG2L_GTIOR_OBE);
+	}
+	return 0;
+}
+EXPORT_SYMBOL_GPL(rzg2l_gpt_pin_reenable);
+
+static int rzg2l_gpt_poeg_disable_req_endisable(void *dev, u8 grp, int op, bool on)
+{
+	u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS;
+	struct rzg2l_gpt_chip *rzg2l_gpt;
+	unsigned int i;
+	u32 offs;
+
+	rzg2l_gpt = dev_get_drvdata(dev);
+	pm_runtime_get_sync(dev);
+
+	for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) {
+		if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link))
+			continue;
+
+		offs = RZG2L_GET_CH_OFFS(i);
+		if (on)
+			rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTINTAD, op, op);
+		else
+			rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTINTAD, op, 0);
+	}
+
+	pm_runtime_put(dev);
+
+	return 0;
+}
+
+int rzg2l_gpt_poeg_disable_req_both_high(void *dev, u8 grp, bool on)
+{
+	int id = RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH;
+
+	return rzg2l_gpt_poeg_disable_req_endisable(dev, grp, id, on);
+}
+EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_high);
+
 static void rzg2l_gpt_reset_assert_pm_disable(void *data)
 {
 	struct rzg2l_gpt_chip *rzg2l_gpt = data;
diff --git a/include/linux/soc/renesas/rzg2l-gpt.h b/include/linux/soc/renesas/rzg2l-gpt.h
new file mode 100644
index 000000000000..87e641fd8732
--- /dev/null
+++ b/include/linux/soc/renesas/rzg2l-gpt.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_SOC_RENESAS_RZG2L_GPT_H__
+#define __LINUX_SOC_RENESAS_RZG2L_GPT_H__
+
+#if IS_ENABLED(CONFIG_PWM_RZG2L_GPT)
+u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp);
+int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp);
+int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp);
+int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on);
+#else
+static inline u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp)
+{
+	return -ENODEV;
+}
+
+static inline int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp)
+{
+	return -ENODEV;
+}
+
+static inline int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp)
+{
+	return -ENODEV;
+}
+
+static inline int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on)
+{
+	return -ENODEV;
+}
+#endif
+
+#endif /* __LINUX_SOC_RENESAS_RZG2L_GPT_H__ */
-- 
2.25.1

[DO NOT APPLY PATCH v5 4/9] pinctrl: renesas: rzg2l-poeg: Add support for GPT Output-Disable Request

[Biju Das]

This patch supports output-disable requests from GPT.

Added sysfs to enable/disable request from GPT when both outputs
are high.

When both outputs are high, gpt detects the condition and triggers
an interrupt to POEG. POEG handles the interrupt and send notification
to userspace. userspace handles the fault and issue a write call to
cancel the disable output request.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../ABI/testing/sysfs-platform-rzg2l-poeg     |  23 ++
 drivers/pinctrl/renesas/poeg/rzg2l-poeg.c     | 252 +++++++++++++++++-
 include/linux/soc/renesas/rzg2l-poeg.h        |  16 ++
 3 files changed, 288 insertions(+), 3 deletions(-)
 create mode 100644 include/linux/soc/renesas/rzg2l-poeg.h

diff --git a/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg b/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg
index 157c98c49940..598fca265aad 100644
--- a/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg
+++ b/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg
@@ -16,3 +16,26 @@ Description:
 
 		- "1" - Output-disable request from software occurred.
 		- "0" - No output-disable request from software occurred.
+
+What:		/sys/devices/platform/<rzg2l-poeg's name>/gpt_req_both_high
+Date:		November 2022
+KernelVersion:	6.3
+Contact:	Biju Das <biju.das.jz@bp.renesas.com>
+Description:
+		This file can be read and write.
+		The file used to configure the output disable request from
+		gpt when same time output level high.
+
+		Write the following string to control the output disable:
+
+		- "1" - Enables output-disable request from gpt when same time
+		        output level high.
+		- "0" - Disables output-disable request from gpt when same time
+		        output level high.
+
+		Read the file, then it shows the following strings:
+
+		- "1" - Output-disable request from gpt when same time
+		        output level high is enabled.
+		- "0" - Output-disable request from gpt when same time
+		        output level high is disabled.
diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
index 3788191bc2f1..2a66dc869fd3 100644
--- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
+++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
@@ -4,19 +4,40 @@
  *
  * Copyright (C) 2022 Renesas Electronics Corporation
  */
-
+#include <linux/cdev.h>
+#include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/kfifo.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/poll.h>
 #include <linux/reset.h>
+#include <linux/soc/renesas/rzg2l-gpt.h>
+#include <linux/soc/renesas/rzg2l-poeg.h>
+#include <linux/wait.h>
 
+#define POEGG_IOCE	BIT(5)
+#define POEGG_PIDE	BIT(4)
 #define POEGG_SSF	BIT(3)
+#define POEGG_IOCF	BIT(1)
+#define POEGG_PIDF	BIT(0)
+
+static struct class *poeg_class;
+static dev_t g_poeg_dev;
+static int minor_n;
 
 struct rzg2l_poeg_chip {
+	struct device *gpt_dev;
 	struct reset_control *rstc;
 	void __iomem *mmio;
+	u8 index;
+	DECLARE_BITMAP(gpt_irq, 3);
+	struct cdev poeg_cdev;
+	wait_queue_head_t events_wait;
+	DECLARE_KFIFO_PTR(events, struct poeg_event);
 };
 
 static void rzg2l_poeg_write(struct rzg2l_poeg_chip *chip, u32 data)
@@ -66,10 +87,46 @@ static ssize_t output_disable_show(struct device *dev,
 	return sysfs_emit(buf, "%u\n", (reg & POEGG_SSF) ? 1 : 0);
 }
 
+static ssize_t gpt_req_both_high_store(struct device *dev,
+				       struct device_attribute *attr,
+				       const char *buf, size_t count)
+{
+	struct rzg2l_poeg_chip *chip;
+	unsigned int val;
+	int ret;
+
+	chip = dev_get_drvdata(dev);
+	ret = kstrtouint(buf, 0, &val);
+	if (ret)
+		return ret;
+
+	if (val)
+		set_bit(RZG2L_GPT_OABHF, chip->gpt_irq);
+	else
+		clear_bit(RZG2L_GPT_OABHF, chip->gpt_irq);
+
+	rzg2l_gpt_poeg_disable_req_both_high(chip->gpt_dev, chip->index,
+					     test_bit(RZG2L_GPT_OABHF, chip->gpt_irq));
+
+	return count;
+}
+
+static ssize_t gpt_req_both_high_show(struct device *dev,
+				      struct device_attribute *attr, char *buf)
+{
+	struct rzg2l_poeg_chip *chip;
+
+	chip = dev_get_drvdata(dev);
+
+	return sysfs_emit(buf, "%u\n", test_bit(RZG2L_GPT_OABHF, chip->gpt_irq));
+}
+
 static DEVICE_ATTR_RW(output_disable);
+static DEVICE_ATTR_RW(gpt_req_both_high);
 
 static struct attribute *poeg_attrs[] = {
 	&dev_attr_output_disable.attr,
+	&dev_attr_gpt_req_both_high.attr,
 	NULL,
 };
 
@@ -83,19 +140,161 @@ static const struct of_device_id rzg2l_poeg_of_table[] = {
 };
 MODULE_DEVICE_TABLE(of, rzg2l_poeg_of_table);
 
+static irqreturn_t rzg2l_poeg_irq(int irq, void *ptr)
+{
+	struct rzg2l_poeg_chip *chip = ptr;
+	struct poeg_event ev;
+	u32 val;
+
+	val = rzg2l_gpt_poeg_disable_req_irq_status(chip->gpt_dev, chip->index);
+	ev.channel = chip->index;
+	ev.gpt_disable_irq_status = val;
+	kfifo_in(&chip->events, &ev, 1);
+	wake_up_poll(&chip->events_wait, EPOLLIN);
+
+	val = rzg2l_poeg_read(chip);
+	if (val & POEGG_IOCF)
+		val &= ~POEGG_IOCF;
+
+	if (val & POEGG_PIDF)
+		val &= ~POEGG_PIDF;
+
+	rzg2l_poeg_write(chip, val);
+	rzg2l_gpt_poeg_disable_req_clr(chip->gpt_dev, chip->index);
+
+	return IRQ_HANDLED;
+}
+
+static void rzg2l_poeg_cleanup(void *data)
+{
+	struct rzg2l_poeg_chip *chip = data;
+
+	put_device(chip->gpt_dev);
+}
+
+static __poll_t rzg2l_poeg_chrdev_poll(struct file *filp,
+				       struct poll_table_struct *pollt)
+{
+	struct rzg2l_poeg_chip *const chip = filp->private_data;
+	__poll_t events = 0;
+
+	poll_wait(filp, &chip->events_wait, pollt);
+	if (!kfifo_is_empty(&chip->events))
+		events = EPOLLIN | EPOLLRDNORM;
+
+	return events;
+}
+
+static ssize_t rzg2l_poeg_chrdev_read(struct file *filp, char __user *buf,
+				      size_t len, loff_t *f_ps)
+{
+	struct rzg2l_poeg_chip *const chip = filp->private_data;
+	unsigned int copied;
+	int err;
+
+	if (len < sizeof(struct poeg_event))
+		return -EINVAL;
+
+	do {
+		if (kfifo_is_empty(&chip->events)) {
+			if (filp->f_flags & O_NONBLOCK)
+				return -EAGAIN;
+
+			err = wait_event_interruptible(chip->events_wait,
+						       !kfifo_is_empty(&chip->events));
+			if (err < 0)
+				return err;
+		}
+
+		err = kfifo_to_user(&chip->events, buf, len, &copied);
+		if (err < 0)
+			return err;
+	} while (!copied);
+
+	return copied;
+}
+
+static ssize_t rzg2l_poeg_chrdev_write(struct file *filp,
+				       const char __user *buf,
+				       size_t len, loff_t *f_ps)
+{
+	struct rzg2l_poeg_chip *const chip = filp->private_data;
+
+	rzg2l_gpt_pin_reenable(chip->gpt_dev, chip->index);
+
+	return len;
+}
+
+static int rzg2l_poeg_chrdev_open(struct inode *inode, struct file *filp)
+{
+	struct rzg2l_poeg_chip *const chip = container_of(inode->i_cdev,
+							  typeof(*chip),
+							  poeg_cdev);
+
+	filp->private_data = chip;
+
+	return nonseekable_open(inode, filp);
+}
+
+static int rzg2l_poeg_chrdev_release(struct inode *inode, struct file *filp)
+{
+	filp->private_data = NULL;
+
+	return 0;
+}
+
+static const struct file_operations poeg_fops = {
+	.owner = THIS_MODULE,
+	.read = rzg2l_poeg_chrdev_read,
+	.write = rzg2l_poeg_chrdev_write,
+	.poll = rzg2l_poeg_chrdev_poll,
+	.open = rzg2l_poeg_chrdev_open,
+	.release = rzg2l_poeg_chrdev_release,
+};
+
 static int rzg2l_poeg_probe(struct platform_device *pdev)
 {
+	struct platform_device *gpt_pdev = NULL;
 	struct rzg2l_poeg_chip *chip;
+	struct device_node *np;
+	u32 val;
+	int irq;
 	int ret;
 
 	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
 	if (!chip)
 		return -ENOMEM;
 
+	np = of_parse_phandle(pdev->dev.of_node, "renesas,gpt", 0);
+	if (np)
+		gpt_pdev = of_find_device_by_node(np);
+
+	of_node_put(np);
+	if (!gpt_pdev)
+		return -ENODEV;
+
+	if (!of_property_read_u32(pdev->dev.of_node, "renesas,poeg-id", &val))
+		chip->index = val;
+
+	chip->gpt_dev = &gpt_pdev->dev;
+	ret = devm_add_action_or_reset(&pdev->dev,
+				       rzg2l_poeg_cleanup, chip);
+	if (ret < 0)
+		return ret;
+
 	chip->mmio = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(chip->mmio))
 		return PTR_ERR(chip->mmio);
 
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return irq;
+
+	ret = devm_request_irq(&pdev->dev, irq, rzg2l_poeg_irq, 0,
+			       dev_name(&pdev->dev), chip);
+	if (ret < 0)
+		return dev_err_probe(&pdev->dev, ret, "cannot get irq\n");
+
 	chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 	if (IS_ERR(chip->rstc))
 		return dev_err_probe(&pdev->dev, PTR_ERR(chip->rstc),
@@ -113,13 +312,26 @@ static int rzg2l_poeg_probe(struct platform_device *pdev)
 		goto err_pm_disable;
 	}
 
+	rzg2l_poeg_write(chip, POEGG_IOCE | POEGG_PIDE);
+
 	ret = sysfs_create_group(&pdev->dev.kobj, &poeg_groups);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "failed to create sysfs: %d\n", ret);
 		goto err_pm;
 	}
 
-	return 0;
+	init_waitqueue_head(&chip->events_wait);
+	cdev_init(&chip->poeg_cdev, &poeg_fops);
+	chip->poeg_cdev.owner = THIS_MODULE;
+	ret = cdev_add(&chip->poeg_cdev,  MKDEV(MAJOR(g_poeg_dev), minor_n), 1);
+	if (ret)
+		goto err_pm;
+
+	device_create(poeg_class, NULL, MKDEV(MAJOR(g_poeg_dev), minor_n),
+		      NULL, "poeg%d", minor_n);
+	minor_n++;
+
+	return kfifo_alloc(&chip->events, 64, GFP_KERNEL);
 
 err_pm:
 	pm_runtime_put(&pdev->dev);
@@ -134,6 +346,10 @@ static int rzg2l_poeg_remove(struct platform_device *pdev)
 {
 	struct rzg2l_poeg_chip *chip = platform_get_drvdata(pdev);
 
+	kfifo_free(&chip->events);
+	device_destroy(poeg_class,
+		       MKDEV(MAJOR(g_poeg_dev), MINOR(chip->poeg_cdev.dev)));
+	cdev_del(&chip->poeg_cdev);
 	sysfs_remove_group(&pdev->dev.kobj, &poeg_groups);
 	pm_runtime_put(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
@@ -150,7 +366,37 @@ static struct platform_driver rzg2l_poeg_driver = {
 	.probe = rzg2l_poeg_probe,
 	.remove = rzg2l_poeg_remove,
 };
-module_platform_driver(rzg2l_poeg_driver);
+
+static int rzg2l_poeg_device_init(void)
+{
+	int err;
+
+	err = alloc_chrdev_region(&g_poeg_dev, 0, 1, "poeg");
+	if (err)
+		goto out;
+
+	poeg_class = class_create(THIS_MODULE, "poeg");
+	if (IS_ERR(poeg_class)) {
+		err = PTR_ERR(poeg_class);
+		goto err_free_chrdev;
+	}
+
+	return platform_driver_register(&rzg2l_poeg_driver);
+
+err_free_chrdev:
+	unregister_chrdev_region(g_poeg_dev, 1);
+out:
+	return err;
+}
+
+static void rzg2l_poeg_device_exit(void)
+{
+	class_destroy(poeg_class);
+	unregister_chrdev_region(g_poeg_dev, 1);
+}
+
+module_init(rzg2l_poeg_device_init);
+module_exit(rzg2l_poeg_device_exit);
 
 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
 MODULE_DESCRIPTION("Renesas RZ/G2L POEG Driver");
diff --git a/include/linux/soc/renesas/rzg2l-poeg.h b/include/linux/soc/renesas/rzg2l-poeg.h
new file mode 100644
index 000000000000..0b3d47d80af8
--- /dev/null
+++ b/include/linux/soc/renesas/rzg2l-poeg.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_SOC_RENESAS_RZG2L_POEG_H__
+#define __LINUX_SOC_RENESAS_RZG2L_POEG_H__
+
+#include <linux/types.h>
+
+#define RZG2L_GPT_DTEF	0
+#define RZG2L_GPT_OABHF	1
+#define RZG2L_GPT_OABLF	2
+
+struct poeg_event {
+	__u32 gpt_disable_irq_status;
+	__u8 channel;
+};
+
+#endif /* __LINUX_SOC_RENESAS_RZG2L_POEG_H__ */
-- 
2.25.1

[DO NOT APPLY PATCH v5 5/9] pwm: rzg2l-gpt: Add support for output disable when both output low

[Biju Das]

This patch adds support for output disable request from gpt,
when same time output level is low.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pwm/pwm-rzg2l-gpt.c           | 9 +++++++++
 include/linux/soc/renesas/rzg2l-gpt.h | 6 ++++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index bcf843b51e3d..749c468a5d66 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -75,6 +75,7 @@
 
 #define RZG2L_GTINTAD_GRP_MASK			GENMASK(25, 24)
 #define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH	BIT(29)
+#define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_LOW	BIT(30)
 
 #define RZG2L_GTST_OABHF			BIT(29)
 #define RZG2L_GTST_OABLF			BIT(30)
@@ -569,6 +570,14 @@ int rzg2l_gpt_poeg_disable_req_both_high(void *dev, u8 grp, bool on)
 }
 EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_high);
 
+int rzg2l_gpt_poeg_disable_req_both_low(void *dev, u8 grp, bool on)
+{
+	int id = RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_LOW;
+
+	return rzg2l_gpt_poeg_disable_req_endisable(dev, grp, id, on);
+}
+EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_low);
+
 static void rzg2l_gpt_reset_assert_pm_disable(void *data)
 {
 	struct rzg2l_gpt_chip *rzg2l_gpt = data;
diff --git a/include/linux/soc/renesas/rzg2l-gpt.h b/include/linux/soc/renesas/rzg2l-gpt.h
index 87e641fd8732..1977d94baf8d 100644
--- a/include/linux/soc/renesas/rzg2l-gpt.h
+++ b/include/linux/soc/renesas/rzg2l-gpt.h
@@ -7,6 +7,7 @@ u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp);
 int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp);
 int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp);
 int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on);
+int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, bool on);
 #else
 static inline u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp)
 {
@@ -27,6 +28,11 @@ static inline int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp,
 {
 	return -ENODEV;
 }
+
+static inline int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, bool on)
+{
+	return -ENODEV;
+}
 #endif
 
 #endif /* __LINUX_SOC_RENESAS_RZG2L_GPT_H__ */
-- 
2.25.1

[DO NOT APPLY PATCH v5 6/9] pinctrl: renesas: rzg2l-poeg: output-disable request from GPT when both outputs are low.

[Biju Das]

This patch adds support fpr output-disable requests from GPT, when both
outputs are low.

Added sysfs to enable/disable for configuring GPT output disable request
when both outputs are low.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../ABI/testing/sysfs-platform-rzg2l-poeg     | 23 ++++++++++++
 drivers/pinctrl/renesas/poeg/rzg2l-poeg.c     | 36 +++++++++++++++++++
 2 files changed, 59 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg b/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg
index 598fca265aad..45a7f44dccdd 100644
--- a/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg
+++ b/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg
@@ -39,3 +39,26 @@ Description:
 		        output level high is enabled.
 		- "0" - Output-disable request from gpt when same time
 		        output level high is disabled.
+
+What:		/sys/devices/platform/<rzg2l-poeg's name>/gpt_req_both_low
+Date:		November 2022
+KernelVersion:	6.3
+Contact:	Biju Das <biju.das.jz@bp.renesas.com>
+Description:
+		This file can be read and write.
+		The file used to configure the output disable request from
+		gpt when same time output level low.
+
+		Write the following string to control the output disable:
+
+		- "1" - Enables output-disable request from gpt when same time
+		        output level low.
+		- "0" - Disables output-disable request from gpt when same time
+		        output level low.
+
+		Read the file, then it shows the following strings:
+
+		- "1" - Output-disable request from gpt when same time
+		        output level low is enabled.
+		- "0" - Output-disable request from gpt when same time
+		        output level low is disabled.
diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
index 2a66dc869fd3..58a2cc9519e5 100644
--- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
+++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
@@ -121,12 +121,48 @@ static ssize_t gpt_req_both_high_show(struct device *dev,
 	return sysfs_emit(buf, "%u\n", test_bit(RZG2L_GPT_OABHF, chip->gpt_irq));
 }
 
+static ssize_t gpt_req_both_low_store(struct device *dev,
+				      struct device_attribute *attr,
+				      const char *buf, size_t count)
+{
+	struct rzg2l_poeg_chip *chip;
+	unsigned int val;
+	int ret;
+
+	chip = dev_get_drvdata(dev);
+	ret = kstrtouint(buf, 0, &val);
+	if (ret)
+		return ret;
+
+	if (val)
+		set_bit(RZG2L_GPT_OABLF, chip->gpt_irq);
+	else
+		clear_bit(RZG2L_GPT_OABLF, chip->gpt_irq);
+
+	rzg2l_gpt_poeg_disable_req_both_low(chip->gpt_dev, chip->index,
+					    test_bit(RZG2L_GPT_OABLF, chip->gpt_irq));
+
+	return count;
+}
+
+static ssize_t gpt_req_both_low_show(struct device *dev,
+				     struct device_attribute *attr, char *buf)
+{
+	struct rzg2l_poeg_chip *chip;
+
+	chip = dev_get_drvdata(dev);
+
+	return sysfs_emit(buf, "%u\n", test_bit(RZG2L_GPT_OABLF, chip->gpt_irq));
+}
+
 static DEVICE_ATTR_RW(output_disable);
 static DEVICE_ATTR_RW(gpt_req_both_high);
+static DEVICE_ATTR_RW(gpt_req_both_low);
 
 static struct attribute *poeg_attrs[] = {
 	&dev_attr_output_disable.attr,
 	&dev_attr_gpt_req_both_high.attr,
+	&dev_attr_gpt_req_both_low.attr,
 	NULL,
 };
 
-- 
2.25.1

[DO NOT APPLY PATCH v5 7/9] pwm: rzg2l-gpt: Add support for output disable on dead time error

[Biju Das]

This patch adds support for output disable request from gpt,
when dead time error occurred.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pwm/pwm-rzg2l-gpt.c           | 9 +++++++++
 include/linux/soc/renesas/rzg2l-gpt.h | 6 ++++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index 749c468a5d66..080cb582e38d 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -74,6 +74,7 @@
 	(FIELD_PREP(RZG2L_GTIOR_GTIOB, RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE) | RZG2L_GTIOR_OBE)
 
 #define RZG2L_GTINTAD_GRP_MASK			GENMASK(25, 24)
+#define RZG2L_GTINTAD_OUTPUT_DISABLE_DEADTIME_ERROR	BIT(28)
 #define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH	BIT(29)
 #define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_LOW	BIT(30)
 
@@ -578,6 +579,14 @@ int rzg2l_gpt_poeg_disable_req_both_low(void *dev, u8 grp, bool on)
 }
 EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_low);
 
+int rzg2l_gpt_poeg_disable_req_deadtime_error(void *dev, u8 grp, bool on)
+{
+	int id = RZG2L_GTINTAD_OUTPUT_DISABLE_DEADTIME_ERROR;
+
+	return rzg2l_gpt_poeg_disable_req_endisable(dev, grp, id, on);
+}
+EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_deadtime_error);
+
 static void rzg2l_gpt_reset_assert_pm_disable(void *data)
 {
 	struct rzg2l_gpt_chip *rzg2l_gpt = data;
diff --git a/include/linux/soc/renesas/rzg2l-gpt.h b/include/linux/soc/renesas/rzg2l-gpt.h
index 1977d94baf8d..c0827eaecdb7 100644
--- a/include/linux/soc/renesas/rzg2l-gpt.h
+++ b/include/linux/soc/renesas/rzg2l-gpt.h
@@ -8,6 +8,7 @@ int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp);
 int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp);
 int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on);
 int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, bool on);
+int rzg2l_gpt_poeg_disable_req_deadtime_error(void *gpt_device, u8 grp, bool on);
 #else
 static inline u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp)
 {
@@ -33,6 +34,11 @@ static inline int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp,
 {
 	return -ENODEV;
 }
+
+static inline int rzg2l_gpt_poeg_disable_req_deadtime_err(void *gpt_device, u8 grp, bool on)
+{
+	return -ENODEV;
+}
 #endif
 
 #endif /* __LINUX_SOC_RENESAS_RZG2L_GPT_H__ */
-- 
2.25.1

[DO NOT APPLY PATCH v5 8/9] pinctrl: renesas: rzg2l-poeg: output-disable request from GPT on dead time error

[Biju Das]

This patch adds support for output-disable requests from GPT,
when dead time error occurs.

Added sysfs to enable/disable for configuring GPT output disable request
for dead time error.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../ABI/testing/sysfs-platform-rzg2l-poeg     | 23 ++++++++++++
 drivers/pinctrl/renesas/poeg/rzg2l-poeg.c     | 37 +++++++++++++++++++
 2 files changed, 60 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg b/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg
index 45a7f44dccdd..4ad421fef3b9 100644
--- a/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg
+++ b/Documentation/ABI/testing/sysfs-platform-rzg2l-poeg
@@ -62,3 +62,26 @@ Description:
 		        output level low is enabled.
 		- "0" - Output-disable request from gpt when same time
 		        output level low is disabled.
+
+What:		/sys/devices/platform/<rzg2l-poeg's name>/gpt_req_deadtime_err
+Date:		November 2022
+KernelVersion:	6.3
+Contact:	Biju Das <biju.das.jz@bp.renesas.com>
+Description:
+		This file can be read and write.
+		The file used to configure the output disable request from
+		gpt when dead time error occurred.
+
+		Write the following string to control the output disable:
+
+		- "1" - Enables output-disable request from gpt when dead time
+		        error occurs.
+		- "0" - Disables output-disable request from gpt when dead time
+		        error occurs.
+
+		Read the file, then it shows the following strings:
+
+		- "1" - Output-disable request from gpt when dead time
+		        error occurs is enabled.
+		- "0" - Output-disable request from gpt when dead time
+		        error occurs is disabled.
diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
index 58a2cc9519e5..c712d26c4282 100644
--- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
+++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c
@@ -155,14 +155,51 @@ static ssize_t gpt_req_both_low_show(struct device *dev,
 	return sysfs_emit(buf, "%u\n", test_bit(RZG2L_GPT_OABLF, chip->gpt_irq));
 }
 
+static ssize_t gpt_req_deadtime_err_store(struct device *dev,
+					  struct device_attribute *attr,
+					  const char *buf, size_t count)
+{
+	struct rzg2l_poeg_chip *chip;
+	unsigned int val;
+	int ret;
+
+	chip = dev_get_drvdata(dev);
+	ret = kstrtouint(buf, 0, &val);
+	if (ret)
+		return ret;
+
+	if (val)
+		set_bit(RZG2L_GPT_DTEF, chip->gpt_irq);
+	else
+		clear_bit(RZG2L_GPT_DTEF, chip->gpt_irq);
+
+	rzg2l_gpt_poeg_disable_req_deadtime_error(chip->gpt_dev, chip->index,
+						  test_bit(RZG2L_GPT_DTEF, chip->gpt_irq));
+
+	return count;
+}
+
+static ssize_t gpt_req_deadtime_err_show(struct device *dev,
+					 struct device_attribute *attr,
+					 char *buf)
+{
+	struct rzg2l_poeg_chip *chip;
+
+	chip = dev_get_drvdata(dev);
+
+	return sysfs_emit(buf, "%u\n", test_bit(RZG2L_GPT_DTEF, chip->gpt_irq));
+}
+
 static DEVICE_ATTR_RW(output_disable);
 static DEVICE_ATTR_RW(gpt_req_both_high);
 static DEVICE_ATTR_RW(gpt_req_both_low);
+static DEVICE_ATTR_RW(gpt_req_deadtime_err);
 
 static struct attribute *poeg_attrs[] = {
 	&dev_attr_output_disable.attr,
 	&dev_attr_gpt_req_both_high.attr,
 	&dev_attr_gpt_req_both_low.attr,
+	&dev_attr_gpt_req_deadtime_err.attr,
 	NULL,
 };
 
-- 
2.25.1

[DO NOT APPLY PATCH v5 9/9] tools/poeg: Add test app for poeg

[Biju Das]

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 tools/poeg/Build      |  1 +
 tools/poeg/Makefile   | 53 ++++++++++++++++++++++++++++++++++++++
 tools/poeg/poeg_app.c | 60 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 114 insertions(+)
 create mode 100644 tools/poeg/Build
 create mode 100644 tools/poeg/Makefile
 create mode 100644 tools/poeg/poeg_app.c

diff --git a/tools/poeg/Build b/tools/poeg/Build
new file mode 100644
index 000000000000..f960920a4afb
--- /dev/null
+++ b/tools/poeg/Build
@@ -0,0 +1 @@
+poeg_app-y += poeg_app.o
diff --git a/tools/poeg/Makefile b/tools/poeg/Makefile
new file mode 100644
index 000000000000..6946e6956215
--- /dev/null
+++ b/tools/poeg/Makefile
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0
+include ../scripts/Makefile.include
+
+bindir ?= /usr/bin
+
+ifeq ($(srctree),)
+srctree := $(patsubst %/,%,$(dir $(CURDIR)))
+srctree := $(patsubst %/,%,$(dir $(srctree)))
+endif
+
+# Do not use make's built-in rules
+# (this improves performance and avoids hard-to-debug behaviour);
+MAKEFLAGS += -r
+
+override CFLAGS += -O2 -Wall -g -D_GNU_SOURCE -I$(OUTPUT)include
+
+ALL_TARGETS := poeg_app
+ALL_PROGRAMS := $(patsubst %,$(OUTPUT)%,$(ALL_TARGETS))
+
+all: $(ALL_PROGRAMS)
+
+export srctree OUTPUT CC LD CFLAGS
+include $(srctree)/tools/build/Makefile.include
+
+#
+# We need the following to be outside of kernel tree
+#
+$(OUTPUT)include/linux/poeg.h: ../../include/linux/soc/renesas/rzg2l-poeg.h
+	mkdir -p $(OUTPUT)include/linux 2>&1 || true
+	ln -sf $(CURDIR)/../../include/linux/soc/renesas/rzg2l-poeg.h $@
+
+prepare: $(OUTPUT)include/linux/poeg.h
+
+COUNTER_EXAMPLE := $(OUTPUT)poeg_app.o
+$(COUNTER_EXAMPLE): prepare FORCE
+	$(Q)$(MAKE) $(build)=poeg_app
+$(OUTPUT)poeg_app: $(COUNTER_EXAMPLE)
+	$(QUIET_LINK)$(CC) $(CFLAGS) $(LDFLAGS) $< -o $@
+
+clean:
+	rm -f $(ALL_PROGRAMS)
+	rm -rf $(OUTPUT)include/linux/counter.h
+	find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '\.*.d' -delete
+
+install: $(ALL_PROGRAMS)
+	install -d -m 755 $(DESTDIR)$(bindir);		\
+	for program in $(ALL_PROGRAMS); do		\
+		install $$program $(DESTDIR)$(bindir);	\
+	done
+
+FORCE:
+
+.PHONY: all install clean FORCE prepare
diff --git a/tools/poeg/poeg_app.c b/tools/poeg/poeg_app.c
new file mode 100644
index 000000000000..79cacb8c60c5
--- /dev/null
+++ b/tools/poeg/poeg_app.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * POEG - example userspace application
+ * Copyright (C) 2022 Biju Das
+ */
+#include <stdio.h>
+#include <stdlib.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <errno.h>
+#include <sys/ioctl.h>
+#include <linux/ioctl.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <poll.h>
+
+#include <linux/poeg.h>
+
+int main(int argc, char *arg[])
+{
+	struct poeg_event event_data;
+	unsigned int val;
+	int ret, fd, i;
+
+	fd = open("/dev/poeg3", O_RDWR);
+	if (fd < 0)
+		perror("open");
+	else
+		printf("[POEG]open\n");
+
+	for (;;) {
+		ret = read(fd, &event_data, sizeof(event_data));
+		if (ret == -1) {
+			perror("Failed to read event data");
+			return 1;
+		}
+
+		val = event_data.gpt_disable_irq_status;
+		if (val) {
+			/* emulate fault clearing condition by adding delay */
+			sleep(2);
+			for (i = 0; i < 8; i++) {
+				if (val & 7) {
+					printf("gpt ch:%u, irq=%x\n", i, val & 7);
+					ret = write(fd, &event_data, sizeof(event_data));
+				}
+				val >>= 3;
+			}
+		}
+	}
+
+	if (close(fd) != 0)
+		perror("close");
+	else
+		printf("[POEG]close\n");
+
+	return 0;
+}
-- 
2.25.1

Re: [PATCH v5 0/9] Add RZ/G2L POEG support

[Linus Walleij]

On Thu, Dec 15, 2022 at 10:32 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:

> This patch series add support for controlling output disable function using sysfs.

What's wrong with using the debugfs approach Drew implemented in
commit 6199f6becc869d30ca9394ca0f7a484bf9d598eb
"pinctrl: pinmux: Add pinmux-select debugfs file"
?

Something driver specific seems like a bit of a hack, does it not?

If this should go into sysfs we should probably create something
generic, such as a list of stuff to be exported as sysfs switches.

It generally also looks really dangerous, which is another reason
for keeping it in debugfs. It's the big hammer to hurt yourself with,
more or less.

Yours,
Linus Walleij

Re: [PATCH v5 1/9] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding

[Linus Walleij]

On Thu, Dec 15, 2022 at 10:32 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:

> Add device tree bindings for the RZ/G2L Port Output Enable for GPT (POEG).
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Rob Herring <robh@kernel.org>

Patch applied!

Yours,
Linus Walleij

Re: [PATCH v5 0/9] Add RZ/G2L POEG support

[Geert Uytterhoeven]

Hi Linus,

On Thu, Dec 29, 2022 at 2:17 AM Linus Walleij <linus.walleij@linaro.org> wrote:
> On Thu, Dec 15, 2022 at 10:32 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > This patch series add support for controlling output disable function using sysfs.
>
> What's wrong with using the debugfs approach Drew implemented in
> commit 6199f6becc869d30ca9394ca0f7a484bf9d598eb
> "pinctrl: pinmux: Add pinmux-select debugfs file"
> ?

I think the main difference is that debugfs is meant for debugging
and development features, while this feature is to be configured on
production systems.  There's just no existing API for it.

> Something driver specific seems like a bit of a hack, does it not?
>
> If this should go into sysfs we should probably create something
> generic, such as a list of stuff to be exported as sysfs switches.
>
> It generally also looks really dangerous, which is another reason
> for keeping it in debugfs. It's the big hammer to hurt yourself with,
> more or less.

Yes, generic would be nice.  Anyone familiar with other hardware
that could make use of this?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v5 0/9] Add RZ/G2L POEG support

[Geert Uytterhoeven]

Hi Linus,

On Tue, Jan 3, 2023 at 10:01 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Thu, Dec 29, 2022 at 2:17 AM Linus Walleij <linus.walleij@linaro.org> wrote:
> > On Thu, Dec 15, 2022 at 10:32 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > This patch series add support for controlling output disable function using sysfs.
> >
> > What's wrong with using the debugfs approach Drew implemented in
> > commit 6199f6becc869d30ca9394ca0f7a484bf9d598eb
> > "pinctrl: pinmux: Add pinmux-select debugfs file"
> > ?
>
> I think the main difference is that debugfs is meant for debugging
> and development features, while this feature is to be configured on
> production systems.  There's just no existing API for it.
>
> > Something driver specific seems like a bit of a hack, does it not?
> >
> > If this should go into sysfs we should probably create something
> > generic, such as a list of stuff to be exported as sysfs switches.
> >
> > It generally also looks really dangerous, which is another reason
> > for keeping it in debugfs. It's the big hammer to hurt yourself with,
> > more or less.
>
> Yes, generic would be nice.  Anyone familiar with other hardware
> that could make use of this?

That's also the reason why I have been rather hesitant in accepting
this driver and bindings (I just saw you applied the bindings): I wanted
to hear your input first ;-)

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v5 0/9] Add RZ/G2L POEG support

[Linus Walleij]

On Tue, Jan 3, 2023 at 10:01 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:

> > If this should go into sysfs we should probably create something
> > generic, such as a list of stuff to be exported as sysfs switches.
> >
> > It generally also looks really dangerous, which is another reason
> > for keeping it in debugfs. It's the big hammer to hurt yourself with,
> > more or less.
>
> Yes, generic would be nice.  Anyone familiar with other hardware
> that could make use of this?

Drew was using this for Beagle Bone IIRC, Drew?

Yours,
Linus Walleij

Re: [PATCH v5 0/9] Add RZ/G2L POEG support

[Geert Uytterhoeven]

Hi Linus,

On Mon, Jan 9, 2023 at 2:16 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> On Tue, Jan 3, 2023 at 10:01 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > If this should go into sysfs we should probably create something
> > > generic, such as a list of stuff to be exported as sysfs switches.
> > >
> > > It generally also looks really dangerous, which is another reason
> > > for keeping it in debugfs. It's the big hammer to hurt yourself with,
> > > more or less.
> >
> > Yes, generic would be nice.  Anyone familiar with other hardware
> > that could make use of this?
>
> Drew was using this for Beagle Bone IIRC, Drew?

Yes, that's what I remember, too.  And I tested it on Koelsch.

But again, that's for debugging purposes.  For non-debugging
operation, we need something different.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v5 0/9] Add RZ/G2L POEG support

[Andy Shevchenko]

On Mon, Jan 09, 2023 at 02:41:24PM +0100, Geert Uytterhoeven wrote:
> On Mon, Jan 9, 2023 at 2:16 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> > On Tue, Jan 3, 2023 at 10:01 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > If this should go into sysfs we should probably create something
> > > > generic, such as a list of stuff to be exported as sysfs switches.
> > > >
> > > > It generally also looks really dangerous, which is another reason
> > > > for keeping it in debugfs. It's the big hammer to hurt yourself with,
> > > > more or less.
> > >
> > > Yes, generic would be nice.  Anyone familiar with other hardware
> > > that could make use of this?
> >
> > Drew was using this for Beagle Bone IIRC, Drew?
> 
> Yes, that's what I remember, too.  And I tested it on Koelsch.
> 
> But again, that's for debugging purposes.  For non-debugging
> operation, we need something different.

I really would like to know the use case when you need to mux pins at run time.
And the guarantee it won't break users' devices into smoke or killing somebody
playing with robots.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v5 0/9] Add RZ/G2L POEG support

[Andy Shevchenko]

On Mon, Jan 09, 2023 at 04:00:35PM +0200, Andy Shevchenko wrote:
> On Mon, Jan 09, 2023 at 02:41:24PM +0100, Geert Uytterhoeven wrote:
> > On Mon, Jan 9, 2023 at 2:16 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> > > On Tue, Jan 3, 2023 at 10:01 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > If this should go into sysfs we should probably create something
> > > > > generic, such as a list of stuff to be exported as sysfs switches.
> > > > >
> > > > > It generally also looks really dangerous, which is another reason
> > > > > for keeping it in debugfs. It's the big hammer to hurt yourself with,
> > > > > more or less.
> > > >
> > > > Yes, generic would be nice.  Anyone familiar with other hardware
> > > > that could make use of this?
> > >
> > > Drew was using this for Beagle Bone IIRC, Drew?
> > 
> > Yes, that's what I remember, too.  And I tested it on Koelsch.
> > 
> > But again, that's for debugging purposes.  For non-debugging
> > operation, we need something different.
> 
> I really would like to know the use case when you need to mux pins at run time.
> And the guarantee it won't break users' devices into smoke or killing somebody
> playing with robots.

Btw, I might agree on having something like this in production, but enabling
it should print a BIG warning that the functionality is DANGEROUS. Something
like trace_printk() has.

-- 
With Best Regards,
Andy Shevchenko

RE: [PATCH v5 0/9] Add RZ/G2L POEG support

[Biju Das]

Hi Linus Walleij,

Thanks for the feedback.

> Subject: Re: [PATCH v5 0/9] Add RZ/G2L POEG support
> 
> On Thu, Dec 15, 2022 at 10:32 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> 
> > This patch series add support for controlling output disable function
> using sysfs.
> 
> What's wrong with using the debugfs approach Drew implemented in commit
> 6199f6becc869d30ca9394ca0f7a484bf9d598eb
> "pinctrl: pinmux: Add pinmux-select debugfs file"
> ?

I am not sure, we supposed to use debugfs for production environment??
 
Currently output pins of the general PWM timer (GPT) can be disabled by using the below methods.

  1) Register setting(ie, by setting POEGGn.SSF to 1) --> by Software control
  2) Input level detection of the GTETRGA to GTETRGD pins->  sending an active level signal to disable the output pins of PWM.
  3) Output-disable request from the GPT--> Here GPT detects short circuits and request POEG to disable the output pins.

In case, if any one doesn't want to use 2) and 3), we should be able to disable output pins of the general PWM timer (GPT) by register control.

> 
> Something driver specific seems like a bit of a hack, does it not?
> 
> If this should go into sysfs we should probably create something generic,

Yes, generic sysfs entry will be good

> such as a list of stuff to be exported as sysfs switches.

Can you please elaborate? Or Point me to an example for this?

Cheers,
Biju

Re: [PATCH v5 0/9] Add RZ/G2L POEG support

[Linus Walleij]

On Mon, Jan 9, 2023 at 2:41 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Mon, Jan 9, 2023 at 2:16 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> > On Tue, Jan 3, 2023 at 10:01 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > If this should go into sysfs we should probably create something
> > > > generic, such as a list of stuff to be exported as sysfs switches.
> > > >
> > > > It generally also looks really dangerous, which is another reason
> > > > for keeping it in debugfs. It's the big hammer to hurt yourself with,
> > > > more or less.
> > >
> > > Yes, generic would be nice.  Anyone familiar with other hardware
> > > that could make use of this?
> >
> > Drew was using this for Beagle Bone IIRC, Drew?
>
> Yes, that's what I remember, too.  And I tested it on Koelsch.
>
> But again, that's for debugging purposes.  For non-debugging
> operation, we need something different.

Actually Drew's usecase wasn't for debugging. It was kind-of production,
but it was for "one-offs" such as factory lines and other very specific-purpose
embedded.

The placement in debugfs was mostly because it is fragile and dangerous.

Yours,
Linus Walleij

Re: [PATCH v5 0/9] Add RZ/G2L POEG support

[Linus Walleij]

On Mon, Jan 9, 2023 at 4:10 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:

> > What's wrong with using the debugfs approach Drew implemented in commit
> > 6199f6becc869d30ca9394ca0f7a484bf9d598eb
> > "pinctrl: pinmux: Add pinmux-select debugfs file"
> > ?
>
> I am not sure, we supposed to use debugfs for production environment??

It depends what is meant by "production environment".

If you mean a controlled environment "one-off" such as a factory line,
a specific installation for a specific purpose such as a water purifier,
that is very custom and hacked together for that one usecase. It will
have other hacks too, so then Beagle is using debugfs in "production"
if that is what you mean by "production", i.e. used to produce something.

This is the same "production" use cases as used by i.e. the GPIO
character device.

If you mean that you are producing 6 million laptops where userspace is
going to hammer this constantly, then no. In that case a real sysfs
knob and ABI contract is needed.

Usually vendors know which usecase their hardware is intended for,
there is in my experience no unknown target audience, so which one is it in
your case?

> > such as a list of stuff to be exported as sysfs switches.
>
> Can you please elaborate? Or Point me to an example for this?

Not sure what to say about that, you will have to invent something I'm
afraid, good examples are in Documentation/ABI.

Yours,
Linus Walleij

RE: [PATCH v5 0/9] Add RZ/G2L POEG support

[Biju Das]

Hi Linus Walleij,

Thanks for the feedback.

> Subject: Re: [PATCH v5 0/9] Add RZ/G2L POEG support
> 
> On Mon, Jan 9, 2023 at 4:10 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> 
> > > What's wrong with using the debugfs approach Drew implemented in
> > > commit 6199f6becc869d30ca9394ca0f7a484bf9d598eb
> > > "pinctrl: pinmux: Add pinmux-select debugfs file"
> > > ?
> >
> > I am not sure, we supposed to use debugfs for production environment??
> 
> It depends what is meant by "production environment".

Sorry for the confusion. I meant the final product used by the customers.

I was under the impression that debugfs is for hacks and debugging.
(For eg: if the HW doesn't have a USB3 function port, but using debugfs,
we can emulate the condition and test)

> 
> If you mean a controlled environment "one-off" such as a factory line, a
> specific installation for a specific purpose such as a water purifier, that
> is very custom and hacked together for that one usecase. It will have other
> hacks too, so then Beagle is using debugfs in "production"
> if that is what you mean by "production", i.e. used to produce something.
> 
> This is the same "production" use cases as used by i.e. the GPIO character
> device.
> 
> If you mean that you are producing 6 million laptops where userspace is
> going to hammer this constantly, then no. In that case a real sysfs knob and
> ABI contract is needed.
> 
> Usually vendors know which usecase their hardware is intended for, there is
> in my experience no unknown target audience, so which one is it in your
> case?

POEG use case is related to protection from system failure(disable output pins in case of short circuits)

Either

1) we detect externally and use software control to disable output pins --> Here I am using sysfs variable
(/sys/devices/platform/soc/10049400.poeg/output_disable) to control it.

Or

2) we detect externally and send an active level signal to disable output pins

Or

3) we detect internally using GPT(PWM) and disable output pins --> Here 3 options or combination is possible
                              for configuring the short circuit detection like
		1) Dead Time Error Output Disable Request Enable
		2) Same Time Output Level High Disable Request Enable
		3) Same Time Output Level Low Disable Request Enable

I have exported 3 sysfs variables for configuring these 3 options.
  1) /sys/devices/platform/soc/10049400.poeg/gpt_req_both_high
  2) /sys/devices/platform/soc/10049400.poeg/gpt_req_both_low
  3) /sys/devices/platform/soc/10049400.poeg/gpt_req_deadtime_err

> 
> > > such as a list of stuff to be exported as sysfs switches.
> >
> > Can you please elaborate? Or Point me to an example for this?
> 
> Not sure what to say about that, you will have to invent something I'm
> afraid, good examples are in Documentation/ABI.

If it is preferable to use debugfs compared to sysfs for the use cases I mentioned above,
I could change it to debugfs like Drew's patch. Please let me know.

Cheers,
Biju

Re: [PATCH v5 0/9] Add RZ/G2L POEG support

[Drew Fustini]

On Tue, Jan 10, 2023 at 09:09:21AM +0100, Linus Walleij wrote:
> On Mon, Jan 9, 2023 at 2:41 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Mon, Jan 9, 2023 at 2:16 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> > > On Tue, Jan 3, 2023 at 10:01 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > If this should go into sysfs we should probably create something
> > > > > generic, such as a list of stuff to be exported as sysfs switches.
> > > > >
> > > > > It generally also looks really dangerous, which is another reason
> > > > > for keeping it in debugfs. It's the big hammer to hurt yourself with,
> > > > > more or less.
> > > >
> > > > Yes, generic would be nice.  Anyone familiar with other hardware
> > > > that could make use of this?
> > >
> > > Drew was using this for Beagle Bone IIRC, Drew?
> >
> > Yes, that's what I remember, too.  And I tested it on Koelsch.
> >
> > But again, that's for debugging purposes.  For non-debugging
> > operation, we need something different.
> 
> Actually Drew's usecase wasn't for debugging. It was kind-of production,
> but it was for "one-offs" such as factory lines and other very specific-purpose
> embedded.
> 
> The placement in debugfs was mostly because it is fragile and dangerous.
> 
> Yours,
> Linus Walleij

For the BeagleBone, the use case for selecting pin fuctions from
userspace with pinmux-select in debugfs is to allow for rapid
prototyping situations such as breadboarding. Our Debian install on the
boards has an utility named config-pin that allows the user to select
between defined pinctrl states for each pin on the expansion header.

Some users like this as it means they do not need to constantly be
editing device tree files and rebooting while protoyping. I agree that
this is not a fool-proof scheme but Beaglebones have been shipping with
this functionality for many years without any significant problems that
I'm aware of.

I do admit that it is possible for someone to potentially damage
circuits with this flexibility, so having a warning in the kernel log
like Andy suggested elsewhere in this thread might be a good idea.

Thanks,
Drew

RE: [PATCH v5 0/9] Add RZ/G2L POEG support

[Biju Das]

Hi Linus,

Thanks for feedback.

> Subject: Re: [PATCH v5 0/9] Add RZ/G2L POEG support
> 
> On Mon, Jan 9, 2023 at 4:10 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> 
> > > What's wrong with using the debugfs approach Drew implemented in
> > > commit 6199f6becc869d30ca9394ca0f7a484bf9d598eb
> > > "pinctrl: pinmux: Add pinmux-select debugfs file"
> > > ?
> >
> > I am not sure, we supposed to use debugfs for production environment??
> 
> It depends what is meant by "production environment".
> 
> If you mean a controlled environment "one-off" such as a factory line, a
> specific installation for a specific purpose such as a water purifier, that
> is very custom and hacked together for that one usecase. It will have other
> hacks too, so then Beagle is using debugfs in "production"
> if that is what you mean by "production", i.e. used to produce something.
> 
> This is the same "production" use cases as used by i.e. the GPIO character
> device.
> 
> If you mean that you are producing 6 million laptops where userspace is
> going to hammer this constantly, then no. In that case a real sysfs knob and
> ABI contract is needed.
> 
> Usually vendors know which usecase their hardware is intended for, there is
> in my experience no unknown target audience, so which one is it in your
> case?
> 
> > > such as a list of stuff to be exported as sysfs switches.
> >
> > Can you please elaborate? Or Point me to an example for this?
> 
> Not sure what to say about that, you will have to invent something I'm
> afraid, good examples are in Documentation/ABI.


For generic approach, here is my plan

From userspace

echo "fname gname config configvalue" > output_disable

At core level, we identify the device associated with the above "fname gname" --> this will be a new api.

Core calls respective pincontrol driver with output_disable_cb(dev, fname, gname, config configvalue)--> there will be a new cb in pinctrl.

The pincontrol driver has a list of devices with device_output_disable callbacks
which will be registered by different drivers (eg:poeg_driver, poe3-driver)

The poeg_driver gets callback and it will match against "fname gname" and configures the value.

If anything fails, it will report error and propagates to user space.

I will prototype based on the above. Please let me know if you have different opinion.

Cheers,
Biju